Merge branch 'dev/PELv2.0' into vscode

1. add GPIO feature in dev mode
2. update the dev_mode_input_resistor command

.clang-format

@@ -29,7 +29,6 @@ BinPackParameters: false
 BreakBeforeBinaryOperators: None
 BreakBeforeTernaryOperators: false
 BreakAfterJavaFieldAnnotations: true
-AlignConsecutiveAssignments: true
 AlignTrailingComments: true
 BreakConstructorInitializers: AfterColon
 AlignConsecutiveMacros:
@@ -50,6 +49,4 @@ AlignConsecutiveBitFields:
   AlignCompound: true
   PadOperators: true 
 AlignEscapedNewlines: Right
-BinPackArguments: false
-BinPackParameters: false
 ...

.gitignore

@@ -2,3 +2,6 @@
 /.visualgdb/
 /VisualGDB/
 *.vgdbsettings.*.user
+*.zip
+/build/
+/output/

.vscode/launch.json

@@ -0,0 +1,74 @@
+{
+  // Use IntelliSense to learn about possible attributes.
+  // Hover to view descriptions of existing attributes.
+  // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
+  "version": "0.2.0",
+  "configurations": [
+    {
+      "cwd": "${workspaceRoot}",
+      "executable": "${command:cmake.launchTargetPath}",
+      "name": "(Ubuntu) launch & debug",
+      "request": "launch",
+      "type": "cortex-debug",
+      "servertype": "jlink",
+      "serverpath": "/opt/SEGGER/JLink/JLinkGDBServerCLExe",
+      "serverArgs": [
+        "-halt",
+        "-ir",
+        "-vd",
+        "-strict",
+      ],
+      "rttConfig": {
+        "enabled": true,
+        "address": "auto",
+        "decoders": [
+          {
+            "label": "",
+            "port": 0,
+            "type": "console"
+          }
+        ],
+      },
+      "armToolchainPath": "/opt/arm-none-eabi/bin",
+      "device": "NRF52840_XXAA",
+      "interface": "swd",
+      "rtos": "FreeRTOS",
+      "svdFile": "${workspaceRoot}/../bmd380_sdk/modules/nrfx/mdk/nrf52840.svd",
+      "runToEntryPoint": "main",
+      "preLaunchTask": "CMake: build"
+    },
+    {
+      "cwd": "${workspaceRoot}",
+      "executable": "${command:cmake.launchTargetPath}",
+      "name": "(Windows) launch & debug",
+      "request": "launch",
+      "type": "cortex-debug",
+      "servertype": "jlink",
+      "serverpath": "C:/Program Files/SEGGER/JLink/JLinkGDBServerCL.exe",
+      "serverArgs": [
+        "-halt",
+        "-ir",
+        "-vd",
+        "-strict",
+      ],
+      "rttConfig": {
+        "enabled": true,
+        "address": "auto",
+        "decoders": [
+          {
+            "label": "",
+            "port": 0,
+            "type": "console"
+          }
+        ],
+      },
+      "armToolchainPath": "C:/sysgcc/arm-eabi/bin",
+      "device": "NRF52840_XXAA",
+      "interface": "swd",
+      "rtos": "FreeRTOS",
+      "svdFile": "${workspaceRoot}/../bmd380_sdk/modules/nrfx/mdk/nrf52840.svd",
+      "runToEntryPoint": "main",
+      "preLaunchTask": "CMake: build"
+    },
+  ]
+}

.vscode/settings.json

@@ -0,0 +1,15 @@
+{
+    "editor.formatOnSave": false,
+    "[c]": {
+        "editor.defaultFormatter": "xaver.clang-format",
+        "editor.formatOnSave": true
+    },
+    "[cpp]": {
+        "editor.defaultFormatter": "xaver.clang-format",
+        "editor.formatOnSave": true
+    },
+    "[python]": {
+        "editor.defaultFormatter": "ms-python.black-formatter",
+        "editor.formatOnSave": true
+    }
+}

.vscode/tasks.json

@@ -0,0 +1,29 @@
+{
+	"version": "2.0.0",
+	"tasks": [
+		{
+			"type": "cmake",
+			"label": "CMake: build",
+			"command": "build",
+			"targets": [
+				"all"
+			],
+			"preset": "Debug",
+			"group": "build",
+			"problemMatcher": [],
+			"detail": "CMake template build task"
+		},
+		{
+			"type": "cmake",
+			"label": "CMake: clean rebuild",
+			"command": "cleanRebuild",
+			"targets": [
+				"all"
+			],
+			"preset": "Debug",
+			"group": "build",
+			"problemMatcher": [],
+			"detail": "CMake template clean rebuild task"
+		}
+	]
+}

CMakeLists.txt

@@ -0,0 +1,261 @@
+cmake_minimum_required(VERSION 3.10.0)
+
+# ==========================
+# Toolchain Setup
+# ==========================
+set(CMAKE_TOOLCHAIN_FILE ${CMAKE_SOURCE_DIR}/cmake/arm-none-eabi-gcc.cmake)
+
+# ==========================
+# Project Setup
+# ==========================
+project(elite VERSION 0.1.0 LANGUAGES C ASM)
+
+set(CMAKE_C_STANDARD 99)
+set(CMAKE_C_STANDARD_REQUIRED ON)
+set(CMAKE_C_EXTENSIONS ON)
+
+set(EXECUTABLE ${PROJECT_NAME}.elf)
+set(NRF_SDK_DIR ${CMAKE_SOURCE_DIR}/../bmd380_sdk)
+set(NRF_SDK_LINKER_DIR ${NRF_SDK_DIR}/modules/nrfx/mdk)
+set(SD_LINKER_DIR ${CMAKE_SOURCE_DIR}/SoftdeviceLibraries/hard)
+set(LINKER_DIR ${CMAKE_SOURCE_DIR}/linkscripts)
+set(LINKER_FILE ${LINKER_DIR}/nRF52840_XXAA_S140_reserve.lds)
+
+# ==========================
+# Compiler Flags and Defines
+# ==========================
+set(COMMON_COMPILE_OPT
+    -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb
+    -fdata-sections -ffunction-sections -Wall -Os -g3 -std=gnu99
+    -Wno-unused-variable -Wno-pointer-sign -Wno-array-bounds
+)
+
+set(COMMON_COMPILE_DEF
+    -DDEBUG=1 -DNRF52840_XXAA -DS140_reserve -DCONFIG_GPIO_AS_PIN
+    -DRESETHNRF_DFU_SETTINGS_VERSION=2 -DNRF_SD_BLE_API_VERSION=7
+    -D__STACK_SIZE=1024 -D__HEAP_SIZE=1024 -DARM_MATH_CM4
+    -DSOFTDEVICE_PRESENT -DUSE_APP_CONFIG
+)
+
+set(COMMON_COMPILE_INC
+    ${ARM_TOOLCHAIN_DIR}/../arm-none-eabi/include
+    ${CMAKE_SOURCE_DIR}/app/inc
+    ${NRF_SDK_DIR}/components/ble/ble_db_discovery
+    ${NRF_SDK_DIR}/components/ble/ble_services/ble_dis
+    ${NRF_SDK_DIR}/components/ble/ble_services/ble_dis_c
+    ${NRF_SDK_DIR}/components/ble/common/
+    ${NRF_SDK_DIR}/components/ble/nrf_ble_gatt
+    ${NRF_SDK_DIR}/components/ble/nrf_ble_gq
+    ${NRF_SDK_DIR}/components/ble/nrf_ble_scan
+    ${NRF_SDK_DIR}/components/ble/ble_services/ble_dfu
+    ${NRF_SDK_DIR}/components/ble/ble_advertising
+    ${NRF_SDK_DIR}/components/ble/peer_manager
+
+    ${NRF_SDK_DIR}/components/libraries/atomic
+    ${NRF_SDK_DIR}/components/libraries/atomic_flags
+    ${NRF_SDK_DIR}/components/libraries/balloc
+    ${NRF_SDK_DIR}/components/libraries/delay
+    ${NRF_SDK_DIR}/components/libraries/experimental_section_vars
+  
+    ${NRF_SDK_DIR}/components/libraries/memobj
+    ${NRF_SDK_DIR}/components/libraries/queue
+    ${NRF_SDK_DIR}/components/libraries/ringbuf
+    ${NRF_SDK_DIR}/components/libraries/strerror
+    ${NRF_SDK_DIR}/components/libraries/util
+    ${NRF_SDK_DIR}/components/libraries/block_dev
+    ${NRF_SDK_DIR}/components/libraries/bootloader
+    ${NRF_SDK_DIR}/components/libraries/bootloader/ble_dfu
+    ${NRF_SDK_DIR}/components/libraries/bootloader/dfu
+    ${NRF_SDK_DIR}/components/libraries/pwr_mgmt
+    ${NRF_SDK_DIR}/components/libraries/usbd
+    ${NRF_SDK_DIR}/components/libraries/usbd/class/cdc
+    ${NRF_SDK_DIR}/components/libraries/usbd/class/cdc/acm
+    ${NRF_SDK_DIR}/components/libraries/usbd/class/nrf_dfu_trigger
+    ${NRF_SDK_DIR}/components/libraries/atomic_fifo
+    ${NRF_SDK_DIR}/components/libraries/svc
+    ${NRF_SDK_DIR}/components/libraries/mutex
+
+    ${NRF_SDK_DIR}/components/softdevice/common
+    ${NRF_SDK_DIR}/components/softdevice/mbr/headers
+    ${NRF_SDK_DIR}/components/softdevice/s140/headers
+
+    ${NRF_SDK_DIR}/components/toolchain/cmsis/include
+    ${NRF_SDK_DIR}/modules/nrfx
+    ${NRF_SDK_DIR}/modules/nrfx/hal
+    ${NRF_SDK_DIR}/modules/nrfx/mdk
+    ${NRF_SDK_DIR}/modules/nrfx/drivers/include
+
+    ${NRF_SDK_DIR}/external/fprintf
+    ${NRF_SDK_DIR}/external/segger_rtt
+    ${NRF_SDK_DIR}/external/utf_converter
+
+    ${NRF_SDK_DIR}/integration/nrfx
+    ${NRF_SDK_DIR}/integration/nrfx/legacy
+)
+
+# ==========================
+# Configuration Interface
+# ==========================
+add_library(prj_config INTERFACE)
+target_include_directories(prj_config INTERFACE ${COMMON_COMPILE_INC})
+target_compile_definitions(prj_config INTERFACE ${COMMON_COMPILE_DEF})
+target_compile_options(prj_config INTERFACE ${COMMON_COMPILE_OPT})
+
+
+# ==========================
+# Subdirectories
+# ==========================
+include(cmake/littlefs.cmake)
+include(cmake/freertos.cmake)
+include(cmake/nrf_log.cmake)
+
+# ==========================
+# Source Files
+# ==========================
+set(STARTUP_SRC
+    ${NRF_SDK_DIR}/modules/nrfx/mdk/gcc_startup_nrf52840.S
+    ${NRF_SDK_DIR}/modules/nrfx/mdk/system_nrf52.c
+)
+
+set(UTILS_SRC
+    ${NRF_SDK_DIR}/components/libraries/util/nrf_assert.c
+    ${NRF_SDK_DIR}/components/libraries/util/app_error.c
+    ${NRF_SDK_DIR}/components/libraries/util/app_error_handler_gcc.c
+    ${NRF_SDK_DIR}/components/libraries/util/app_error_weak.c
+    ${NRF_SDK_DIR}/components/libraries/util/app_util_platform.c
+    ${NRF_SDK_DIR}/components/libraries/strerror/nrf_strerror.c
+    ${NRF_SDK_DIR}/components/libraries/pwr_mgmt/nrf_pwr_mgmt.c
+)
+
+set(ATOMIC_SRC
+    ${NRF_SDK_DIR}/components/libraries/atomic/nrf_atomic.c
+    ${NRF_SDK_DIR}/components/libraries/atomic_fifo/nrf_atfifo.c
+    ${NRF_SDK_DIR}/components/libraries/atomic_flags/nrf_atflags.c
+    ${NRF_SDK_DIR}/components/libraries/memobj/nrf_memobj.c
+    ${NRF_SDK_DIR}/components/libraries/balloc/nrf_balloc.c
+    ${NRF_SDK_DIR}/components/libraries/ringbuf/nrf_ringbuf.c
+)
+
+set(USBD_SRC
+    ${NRF_SDK_DIR}/components/libraries/usbd/app_usbd.c
+    ${NRF_SDK_DIR}/components/libraries/usbd/app_usbd_core.c
+    ${NRF_SDK_DIR}/components/libraries/usbd/app_usbd_serial_num.c
+    ${NRF_SDK_DIR}/components/libraries/usbd/app_usbd_string_desc.c
+    ${NRF_SDK_DIR}/components/libraries/usbd/class/cdc/acm/app_usbd_cdc_acm.c
+    ${NRF_SDK_DIR}/components/libraries/usbd/class/nrf_dfu_trigger/app_usbd_nrf_dfu_trigger.c
+)
+
+set(SOFTDEVICE_SRC
+    ${NRF_SDK_DIR}/components/softdevice/common/nrf_sdh.c
+    ${NRF_SDK_DIR}/components/softdevice/common/nrf_sdh_freertos.c
+    ${NRF_SDK_DIR}/components/softdevice/common/nrf_sdh_ble.c
+)
+
+set(BLE_SRC
+    ${NRF_SDK_DIR}/components/ble/common/ble_advdata.c
+    ${NRF_SDK_DIR}/components/ble/common/ble_conn_state.c
+    ${NRF_SDK_DIR}/components/ble/common/ble_srv_common.c
+    ${NRF_SDK_DIR}/components/ble/ble_advertising/ble_advertising.c
+    ${NRF_SDK_DIR}/components/ble/ble_services/ble_dis/ble_dis.c
+    ${NRF_SDK_DIR}/components/ble/ble_services/ble_dfu/ble_dfu.c
+    ${NRF_SDK_DIR}/components/ble/ble_services/ble_dfu/ble_dfu_unbonded.c
+    ${NRF_SDK_DIR}/components/ble/nrf_ble_gatt/nrf_ble_gatt.c 
+)
+
+set(PRINTF_SRC
+    ${NRF_SDK_DIR}/external/fprintf/nrf_fprintf.c
+    ${NRF_SDK_DIR}/external/fprintf/nrf_fprintf_format.c
+    ${NRF_SDK_DIR}/external/segger_rtt/SEGGER_RTT.c
+    ${NRF_SDK_DIR}/external/segger_rtt/SEGGER_RTT_printf.c
+)
+
+set(NRFX_DRIVERS_SRC
+    ${NRF_SDK_DIR}/modules/nrfx/drivers/src/nrfx_clock.c
+    ${NRF_SDK_DIR}/modules/nrfx/drivers/src/nrfx_power.c
+    ${NRF_SDK_DIR}/modules/nrfx/drivers/src/nrfx_usbd.c
+    ${NRF_SDK_DIR}/modules/nrfx/drivers/src/nrfx_gpiote.c
+    ${NRF_SDK_DIR}/modules/nrfx/soc/nrfx_atomic.c
+    ${NRF_SDK_DIR}/modules/nrfx/drivers/src/nrfx_spim.c
+    ${NRF_SDK_DIR}/modules/nrfx/drivers/src/nrfx_twim.c
+    )
+    
+    set(NRFX_LEGACY_SRC
+    ${NRF_SDK_DIR}/integration/nrfx/legacy/nrf_drv_clock.c
+    ${NRF_SDK_DIR}/integration/nrfx/legacy/nrf_drv_power.c
+    ${NRF_SDK_DIR}/integration/nrfx/legacy/nrf_drv_spi.c
+    ${NRF_SDK_DIR}/integration/nrfx/legacy/nrf_drv_twi.c
+)
+
+set(EXPERIMENTAL_SRC
+    ${NRF_SDK_DIR}/components/libraries/experimental_section_vars/nrf_section_iter.c
+)
+
+file(GLOB_RECURSE APP_SOURCES "app/*.c")
+
+# ==========================
+# Executable and Linker
+# ==========================
+add_executable(${EXECUTABLE}
+    $<TARGET_OBJECTS:lfs>
+    $<TARGET_OBJECTS:freertos>
+    $<TARGET_OBJECTS:nrf_log>
+    ${APP_SOURCES}
+    ${STARTUP_SRC}
+    ${UTILS_SRC}
+    ${ATOMIC_SRC}
+    ${USBD_SRC}
+    ${SOFTDEVICE_SRC}
+    ${BLE_SRC}
+    ${PRINTF_SRC}
+    ${NRFX_DRIVERS_SRC}
+    ${NRFX_LEGACY_SRC}
+    ${EXPERIMENTAL_SRC}
+    ${NRF_SDK_DIR}/components/libraries/pwr_mgmt/nrf_pwr_mgmt.c
+)
+
+target_link_options(${EXECUTABLE} PRIVATE
+    -T${LINKER_FILE}
+    -L${LINKER_DIR}
+    -L${SD_LINKER_DIR}
+    -L${NRF_SDK_LINKER_DIR}
+    -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb
+    --specs=nano.specs --specs=nosys.specs -u _printf_float
+    -lc -lm
+    -Wl,-Map=${PROJECT_NAME}.map,--cref
+    -Wl,--gc-sections
+    -Xlinker -print-memory-usage -Xlinker
+)
+
+target_link_libraries(${EXECUTABLE} PRIVATE
+    prj_config
+    lfs
+    freertos
+    nrf_log
+    m
+    c
+)
+
+# Optional: Print executable size as part of the post build process
+add_custom_command(TARGET ${EXECUTABLE}
+        POST_BUILD
+        COMMAND ${CMAKE_SIZE} ${EXECUTABLE})
+
+string(TIMESTAMP BUILD_TIMESTAMP "%Y%m%d%H%M")
+set(OTA_ZIP_NAME "ota_${PROJECT_NAME}_${BUILD_TIMESTAMP}.zip")        
+
+# Optional: Create hex, bin and S-Record files after the build
+add_custom_command(TARGET ${EXECUTABLE}
+        POST_BUILD
+        COMMAND ${CMAKE_OBJCOPY} -O srec --srec-len=64 ${EXECUTABLE} ${PROJECT_NAME}.s19
+        COMMAND ${CMAKE_OBJCOPY} -O ihex ${EXECUTABLE} ${PROJECT_NAME}.hex
+        COMMAND ${CMAKE_OBJCOPY} -O binary ${EXECUTABLE} ${PROJECT_NAME}.bin
+        COMMAND nrfutil nrf5sdk-tools pkg generate
+            --hw-version 52
+            --sd-req 0x100
+            --application-version 0
+            --application ${PROJECT_NAME}.hex
+            --key-file ${CMAKE_SOURCE_DIR}/private.pem
+            ${OTA_ZIP_NAME}
+        COMMAND ${CMAKE_COMMAND} -E make_directory "${CMAKE_SOURCE_DIR}/output"
+        COMMAND ${CMAKE_COMMAND} -E rename "${OTA_ZIP_NAME}" "${CMAKE_SOURCE_DIR}/output/${OTA_ZIP_NAME}"
+)

CMakePresets.json

@@ -0,0 +1,59 @@
+{
+    "version": 3,
+    "configurePresets": [
+        {
+            "name": "default",
+            "hidden": true,
+            "generator": "Ninja",
+            "binaryDir": "${sourceDir}/build/${presetName}",
+            "cacheVariables": {
+            }
+        },
+        {
+            "name": "Debug",
+            "inherits": "default",
+            "cacheVariables": {
+                "CMAKE_BUILD_TYPE": "Debug"
+            }
+        },
+        {
+            "name": "RelWithDebInfo",
+            "inherits": "default",
+            "cacheVariables": {
+                "CMAKE_BUILD_TYPE": "RelWithDebInfo"
+            }
+        },
+        {
+            "name": "Release",
+            "inherits": "default",
+            "cacheVariables": {
+                "CMAKE_BUILD_TYPE": "Release"
+            }
+        },
+        {
+            "name": "MinSizeRel",
+            "inherits": "default",
+            "cacheVariables": {
+                "CMAKE_BUILD_TYPE": "MinSizeRel"
+            }
+        }
+    ],
+    "buildPresets": [
+        {
+            "name": "Debug",
+            "configurePreset": "Debug"
+        },
+        {
+            "name": "RelWithDebInfo",
+            "configurePreset": "RelWithDebInfo"
+        },
+        {
+            "name": "Release",
+            "configurePreset": "Release"
+        },
+        {
+            "name": "MinSizeRel",
+            "configurePreset": "MinSizeRel"
+        }
+    ]
+}

FreeRTOSConfig.h

@@ -1,207 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-#ifdef SOFTDEVICE_PRESENT
-#include "nrf_soc.h"
-#endif
-#include "app_util_platform.h"
-
-/*-----------------------------------------------------------
- * Possible configurations for system timer
- */
-#define FREERTOS_USE_RTC      0 /**< Use real time clock for the system */
-#define FREERTOS_USE_SYSTICK  1 /**< Use SysTick timer for system */
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-#define configTICK_SOURCE                                                         FREERTOS_USE_RTC
-
-#define configUSE_PREEMPTION                                                      1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION                                   1
-#define configUSE_TICKLESS_IDLE                                                   0
-#define configUSE_TICKLESS_IDLE_SIMPLE_DEBUG                                      1 /* See into vPortSuppressTicksAndSleep source code for explanation */
-#define configCPU_CLOCK_HZ                                                        ( SystemCoreClock )
-#define configTICK_RATE_HZ                                                        1024
-#define configMAX_PRIORITIES                                                      ( 6 )
-#define configMINIMAL_STACK_SIZE                                                  ( 192 )
-#define configTOTAL_HEAP_SIZE                                                     ( 32 * 1024 )
-#define configMAX_TASK_NAME_LEN                                                   ( 16 )
-#define configUSE_16_BIT_TICKS                                                    0
-#define configIDLE_SHOULD_YIELD                                                   1
-#define configUSE_MUTEXES                                                         1
-#define configUSE_RECURSIVE_MUTEXES                                               0
-#define configUSE_COUNTING_SEMAPHORES                                             0
-#define configUSE_ALTERNATIVE_API                                                 0    /* Deprecated! */
-#define configQUEUE_REGISTRY_SIZE                                                 2
-#define configUSE_QUEUE_SETS                                                      0
-#define configUSE_TIME_SLICING                                                    0
-#define configUSE_NEWLIB_REENTRANT                                                1
-#define configENABLE_BACKWARD_COMPATIBILITY                                       1
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                                                       0
-#define configUSE_TICK_HOOK                                                       0
-#define configCHECK_FOR_STACK_OVERFLOW                                            0
-#define configUSE_MALLOC_FAILED_HOOK                                              0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS                                             0
-#define configUSE_TRACE_FACILITY                                                  0
-#define configUSE_STATS_FORMATTING_FUNCTIONS                                      0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                                                     0
-#define configMAX_CO_ROUTINE_PRIORITIES                                           ( 2 )
-
-/* Software timer definitions. */
-#define configUSE_TIMERS                                                          1
-#define configTIMER_TASK_PRIORITY                                                 ( 2 )
-#define configTIMER_QUEUE_LENGTH                                                  32
-#define configTIMER_TASK_STACK_DEPTH                                              ( 80 )
-
-/* Tickless Idle configuration. */
-#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP                                     2
-
-/* Tickless idle/low power functionality. */
-
-
-/* Define to trap errors during development. */
-#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER)
-#define configASSERT( x )                                                         ASSERT(x)
-#endif
-
-/* FreeRTOS MPU specific definitions. */
-#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS                    1
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet                                                  0
-#define INCLUDE_uxTaskPriorityGet                                                 0
-#define INCLUDE_vTaskDelete                                                       0
-#define INCLUDE_vTaskSuspend                                                      1
-#define INCLUDE_xResumeFromISR                                                    0
-#define INCLUDE_vTaskDelayUntil                                                   1
-#define INCLUDE_vTaskDelay                                                        1
-#define INCLUDE_xTaskGetSchedulerState                                            1
-#define INCLUDE_xTaskGetCurrentTaskHandle                                         0
-#define INCLUDE_uxTaskGetStackHighWaterMark                                       0
-#define INCLUDE_xTaskGetIdleTaskHandle                                            0
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle                                    0
-#define INCLUDE_pcTaskGetTaskName                                                 0
-#define INCLUDE_eTaskGetState                                                     0
-#define INCLUDE_xEventGroupSetBitFromISR                                          1
-#define INCLUDE_xTimerPendFunctionCall                                            0
-
-/* The lowest interrupt priority that can be used in a call to a "set priority"
-function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY         0xf
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY    _PRIO_APP_HIGH
-
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY                 configLIBRARY_LOWEST_INTERRUPT_PRIORITY
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY            configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY
-
-/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
-standard names - or at least those used in the unmodified vector table. */
-
-#define vPortSVCHandler                                                           SVC_Handler
-#define xPortPendSVHandler                                                        PendSV_Handler
-
-
-/*-----------------------------------------------------------
- * Settings that are generated automatically
- * basing on the settings above
- */
-#if (configTICK_SOURCE == FREERTOS_USE_SYSTICK)
-    // do not define configSYSTICK_CLOCK_HZ for SysTick to be configured automatically
-    // to CPU clock source
-    #define xPortSysTickHandler     SysTick_Handler
-#elif (configTICK_SOURCE == FREERTOS_USE_RTC)
-    #define configSYSTICK_CLOCK_HZ  ( 32768UL )
-    #define xPortSysTickHandler     RTC1_IRQHandler
-#else
-    #error  Unsupported configTICK_SOURCE value
-#endif
-
-/* Code below should be only used by the compiler, and not the assembler. */
-#if !(defined(__ASSEMBLY__) || defined(__ASSEMBLER__))
-    #include "nrf.h"
-    #include "nrf_assert.h"
-
-    /* This part of definitions may be problematic in assembly - it uses definitions from files that are not assembly compatible. */
-    /* Cortex-M specific definitions. */
-    #ifdef __NVIC_PRIO_BITS
-        /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
-        #define configPRIO_BITS             __NVIC_PRIO_BITS
-    #else
-        #error "This port requires __NVIC_PRIO_BITS to be defined"
-    #endif
-
-    /* Access to current system core clock is required only if we are ticking the system by systimer */
-    #if (configTICK_SOURCE == FREERTOS_USE_SYSTICK)
-        #include <stdint.h>
-        extern uint32_t SystemCoreClock;
-    #endif
-#endif /* !assembler */
-
-/** Implementation note:  Use this with caution and set this to 1 ONLY for debugging
- * ----------------------------------------------------------
-     * Set the value of configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG to below for enabling or disabling RTOS tick auto correction:
-     * 0. This is default. If the RTC tick interrupt is masked for more than 1 tick by higher priority interrupts, then most likely
-     *    one or more RTC ticks are lost. The tick interrupt inside RTOS will detect this and make a correction needed. This is needed
-     *    for the RTOS internal timers to be more accurate.
-     * 1. The auto correction for RTOS tick is disabled even though few RTC tick interrupts were lost. This feature is desirable when debugging
-     *    the RTOS application and stepping though the code. After stepping when the application is continued in debug mode, the auto-corrections of
-     *    RTOS tick might cause asserts. Setting configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG to 1 will make RTC and RTOS go out of sync but could be
-     *    convenient for debugging.
-     */
-#define configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG     0
-
-#endif /* FREERTOS_CONFIG_H */

app/inc/FreeRTOSConfig.h

@@ -0,0 +1,203 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#ifdef SOFTDEVICE_PRESENT
+#include "nrf_soc.h"
+#endif
+#include "app_util_platform.h"
+
+/*-----------------------------------------------------------
+ * Possible configurations for system timer
+ */
+#define FREERTOS_USE_RTC                        0 /**< Use real time clock for the system */
+#define FREERTOS_USE_SYSTICK                    1 /**< Use SysTick timer for system */
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configTICK_SOURCE                       FREERTOS_USE_RTC
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configUSE_TICKLESS_IDLE                 0
+#define configUSE_TICKLESS_IDLE_SIMPLE_DEBUG    1 /* See into vPortSuppressTicksAndSleep source code for explanation */
+#define configCPU_CLOCK_HZ                      (SystemCoreClock)
+#define configTICK_RATE_HZ                      1024
+#define configMAX_PRIORITIES                    (6)
+#define configMINIMAL_STACK_SIZE                (192)
+#define configTOTAL_HEAP_SIZE                   (48 * 1024)
+#define configMAX_TASK_NAME_LEN                 (16)
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             0
+#define configUSE_COUNTING_SEMAPHORES           0
+#define configUSE_ALTERNATIVE_API               0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              1
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                     0
+#define configUSE_TICK_HOOK                     0
+#define configCHECK_FOR_STACK_OVERFLOW          0
+#define configUSE_MALLOC_FAILED_HOOK            0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS           0
+#define configUSE_TRACE_FACILITY                0
+#define configUSE_STATS_FORMATTING_FUNCTIONS    0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                   0
+#define configMAX_CO_ROUTINE_PRIORITIES         (2)
+
+/* Software timer definitions. */
+#define configUSE_TIMERS                        1
+#define configTIMER_TASK_PRIORITY               (2)
+#define configTIMER_QUEUE_LENGTH                32
+#define configTIMER_TASK_STACK_DEPTH            (80)
+
+/* Tickless Idle configuration. */
+#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP   2
+
+/* Tickless idle/low power functionality. */
+
+/* Define to trap errors during development. */
+#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER)
+#define configASSERT(x) ASSERT(x)
+#endif
+
+/* FreeRTOS MPU specific definitions. */
+#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 1
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet                               0
+#define INCLUDE_uxTaskPriorityGet                              0
+#define INCLUDE_vTaskDelete                                    1
+#define INCLUDE_vTaskSuspend                                   1
+#define INCLUDE_xResumeFromISR                                 0
+#define INCLUDE_vTaskDelayUntil                                1
+#define INCLUDE_vTaskDelay                                     1
+#define INCLUDE_xTaskGetSchedulerState                         1
+#define INCLUDE_xTaskGetCurrentTaskHandle                      0
+#define INCLUDE_uxTaskGetStackHighWaterMark                    0
+#define INCLUDE_xTaskGetIdleTaskHandle                         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle                 0
+#define INCLUDE_pcTaskGetTaskName                              0
+#define INCLUDE_eTaskGetState                                  0
+#define INCLUDE_xEventGroupSetBitFromISR                       1
+#define INCLUDE_xTimerPendFunctionCall                         0
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY                0xf
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY           _PRIO_APP_HIGH
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY                        configLIBRARY_LOWEST_INTERRUPT_PRIORITY
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY                   configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names - or at least those used in the unmodified vector table. */
+
+#define vPortSVCHandler                                        SVC_Handler
+#define xPortPendSVHandler                                     PendSV_Handler
+
+/*-----------------------------------------------------------
+ * Settings that are generated automatically
+ * basing on the settings above
+ */
+#if (configTICK_SOURCE == FREERTOS_USE_SYSTICK)
+// do not define configSYSTICK_CLOCK_HZ for SysTick to be configured automatically
+// to CPU clock source
+#define xPortSysTickHandler SysTick_Handler
+#elif (configTICK_SOURCE == FREERTOS_USE_RTC)
+#define configSYSTICK_CLOCK_HZ (32768UL)
+#define xPortSysTickHandler    RTC1_IRQHandler
+#else
+#error Unsupported configTICK_SOURCE value
+#endif
+
+/* Code below should be only used by the compiler, and not the assembler. */
+#if !(defined(__ASSEMBLY__) || defined(__ASSEMBLER__))
+#include "nrf.h"
+#include "nrf_assert.h"
+
+/* This part of definitions may be problematic in assembly - it uses definitions from files that are not assembly compatible. */
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#error "This port requires __NVIC_PRIO_BITS to be defined"
+#endif
+
+/* Access to current system core clock is required only if we are ticking the system by systimer */
+#if (configTICK_SOURCE == FREERTOS_USE_SYSTICK)
+#include <stdint.h>
+extern uint32_t SystemCoreClock;
+#endif
+#endif /* !assembler */
+
+/** Implementation note:  Use this with caution and set this to 1 ONLY for debugging
+ * ----------------------------------------------------------
+ * Set the value of configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG to below for enabling or disabling RTOS tick auto correction:
+ * 0. This is default. If the RTC tick interrupt is masked for more than 1 tick by higher priority interrupts, then most likely
+ *    one or more RTC ticks are lost. The tick interrupt inside RTOS will detect this and make a correction needed. This is needed
+ *    for the RTOS internal timers to be more accurate.
+ * 1. The auto correction for RTOS tick is disabled even though few RTC tick interrupts were lost. This feature is desirable when debugging
+ *    the RTOS application and stepping though the code. After stepping when the application is continued in debug mode, the auto-corrections of
+ *    RTOS tick might cause asserts. Setting configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG to 1 will make RTC and RTOS go out of sync but could be
+ *    convenient for debugging.
+ */
+#define configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG 0
+
+#endif /* FREERTOS_CONFIG_H */

app/inc/adc_drv.h

@@ -0,0 +1,39 @@
+#ifndef __ADC_DRV_H__
+#define __ADC_DRV_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+
+#include "adc_drv_if.h"
+
+#if (DEF_ADC_DRV_ENABLED)
+    int adc_init(void);
+    int adc_reset(void);
+    int adc_gain(adc_gain_t gain);
+    int adc_read(uint32_t channel, int32_t *adc_val);
+    int adc_read_milivolt(uint32_t channel, float *mv);
+    int adc_read_mutiple_channels(uint32_t *p_channel, int32_t *p_adc_val, uint32_t cnt);
+    int adc_read_mutiple_channels_ex(uint32_t *p_channel, int32_t *p_adc_val, uint32_t cnt, void (*preliminary_action)(void));
+    int adc_read_multiple_milivolt_ex(uint32_t *p_channel, float *p_val, uint32_t cnt, void (*preliminary_action)(void));
+    int adc_read_mutiple_channels_convert_milivolt(int32_t *p_val_14bit, float *p_val_f, uint32_t count);
+#else
+#define adc_init()
+#define adc_reset()
+#define adc_gain(x)
+#define adc_read(x, y)
+#define adc_read_milivolt(x, y)
+#define adc_read_mutiple_channels(x, y, z)
+#define adc_read_mutiple_channels_ex(x, y, z, a)
+#define adc_read_multiple_milivolt_ex(x, y, z, a)
+#define adc_read_mutiple_channels_convert_milivolt(x, y, z)
+#endif /* ! DEF_ADC_DRV_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __ADC_DRV_H__ */

app/inc/adc_drv_if.h

@@ -0,0 +1,46 @@
+#ifndef __ADC_DRV_IF_H__
+#define __ADC_DRV_IF_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+
+#define ADC_DRV_ERROR   (-1)
+#define ADC_DRV_SUCCESS (0)
+
+    typedef enum
+    {
+        GAIN_0P625,
+        GAIN_1P000,
+        GAIN_1P200,
+        GAIN_1P250,
+        GAIN_1P500,
+        GAIN_2P000,
+        GAIN_2P500,
+        GAIN_3P000,
+        GAIN_6P000,
+        GAIN_12P000,
+        GAIN_24P000,
+    } adc_gain_t;
+
+    typedef struct
+    {
+        int (*init)(void);
+        int (*reset)(void);
+        int (*read)(uint32_t channel, int32_t *adc_val);
+        int (*read_milivolt)(uint32_t channel, float *p_val);
+        int (*read_multiple_milivolt_ex)(uint32_t *p_channels, float *p_val, uint32_t count, void(*preliminary_action));
+        int (*read_multiple_channels)(uint32_t *p_channels, int32_t *adc_val, uint32_t count);
+        int (*read_multiple_channels_ex)(uint32_t *p_channels, int32_t *adc_val, uint32_t count, void (*preliminary_action)(void));
+        int (*gain)(adc_gain_t gain);
+        int (*adc_convert_multiple_milivolt)(int32_t *p_val_14bit, float *p_val_f, uint32_t count);
+    } adc_drv_if_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __ADC_DRV_IF_H__ */

app/inc/adgs1412.h

@@ -0,0 +1,30 @@
+#ifndef __ADGS1412_H__
+#define __ADGS1412_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "app_config.h"
+#include "sw_drv_if.h"
+
+#if (DEF_ADGS1412_ENABLED)
+
+#define ASGS1412_COUNT  2
+#define SW_PER_ASGS1412 4
+#define SW_TOTAL_COUNT  (SW_PER_ASGS1412 * ASGS1412_COUNT)
+#define SW_PER_BYTE     SW_PER_ASGS1412
+
+#if (SW_TOTAL_COUNT > 64)
+#error "unsupport"
+#endif /* ! SW_TOTAL_COUNT */
+
+extern const sw_drv_if_t adgs1412;
+
+#endif /* ! DEF_ADGS1412_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __ADGS1412_H__ */

app/inc/ads8691.h

@@ -0,0 +1,21 @@
+#ifndef __ADS8691_H__
+#define __ADS8691_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "app_config.h"
+#include "adc_drv_if.h"
+
+#if (DEF_ADS8691_ENABLED)
+
+extern const adc_drv_if_t ads8691;
+
+#endif /* ! DEF_ADS8691_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __ADS8691_H__ */

app/inc/apa102_2020.h

@@ -0,0 +1,23 @@
+#ifndef __APA102_2020_H__
+#define __APA102_2020_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+
+#if (DEF_APA102_2020_ENABLED)
+
+#include "led_drv_if.h"
+
+    extern const led_drv_if_t apa102_drv;
+
+#endif /* ! DEF_APA102_2020_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __APA102_2020_H__ */

app/inc/app_config.h

@@ -0,0 +1,477 @@
+#ifndef __APP_CONFIG_H__
+#define __APP_CONFIG_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LOG
+#define NRF_LOG_ENABLED                             1
+#define NRF_LOG_DEFAULT_LEVEL                       3
+#define NRF_LOG_BACKEND_RTT_ENABLED                 1
+
+#define NRF_LOG_BACKEND_UART_ENABLED                0
+#define NRF_LOG_BACKEND_RTT_TX_RETRY_DELAY_MS       1
+#define NRF_LOG_BACKEND_RTT_TX_RETRY_CNT            3
+#define NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE        64
+#define NRF_LOG_DEFERRED                            0
+#define NRF_LOG_USES_TIMESTAMP                      0
+#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 0
+#define NRF_LOG_MSGPOOL_ELEMENT_COUNT               31
+
+// SEGGER-RTT
+#define SEGGER_RTT_SECTION                          ".segger_rtt"
+#define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS        2
+#define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS      1
+#define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP            2048
+#define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN          16
+#define SEGGER_RTT_CONFIG_DEFAULT_MODE              0
+
+// SoftDevice SoC event handler
+#define NRF_SDH_SOC_ENABLED                         1
+
+// SoftDevice handler
+#define NRF_SDH_ENABLED                             1
+
+// SoftDevice clock configuration
+#define NRF_SDH_CLOCK_LF_SRC                        0
+#define NRF_SDH_CLOCK_LF_RC_CTIV                    12
+#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV               2
+#define NRF_SDH_CLOCK_LF_ACCURACY                   1
+
+// SDH Observers - Observers and priority levels
+#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS            2
+#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS          2
+#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS          2
+
+// SoC Observers - Observers and priority levels
+#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS            2
+
+// nrf_drv_power - POWER peripheral driver - legacy layer
+#define POWER_ENABLED                               1
+// The default configuration of main DCDC regulator
+#define POWER_CONFIG_DEFAULT_DCDCEN                 0
+//  The default configuration of High Voltage DCDC regulator
+#define POWER_CONFIG_DEFAULT_DCDCENHV               0
+
+// nrf_drv_clock - CLOCK peripheral driver - legacy layer
+#define NRF_CLOCK_ENABLED                           1
+//  LF Clock Source
+#define CLOCK_CONFIG_LF_SRC                         0
+#define CLOCK_CONFIG_LF_CAL_ENABLED                 0
+// nrf_section_iter - Section iterator
+#define NRF_SECTION_ITER_ENABLED                    1
+
+// State Observers priorities
+#define CLOCK_CONFIG_STATE_OBSERVER_PRIO            0
+#define POWER_CONFIG_STATE_OBSERVER_PRIO            0
+#define RNG_CONFIG_STATE_OBSERVER_PRIO              0
+
+// Stack Event Observers priorities
+#define NRF_SDH_SOC_STACK_OBSERVER_PRIO             0
+#define NRF_SDH_BLE_STACK_OBSERVER_PRIO             0
+
+// SoC Observers priorities
+#define POWER_CONFIG_SOC_OBSERVER_PRIO              0
+#define CLOCK_CONFIG_SOC_OBSERVER_PRIO              0
+
+// Interrupt priority
+#define POWER_CONFIG_IRQ_PRIORITY                   6
+#define CLOCK_CONFIG_IRQ_PRIORITY                   6
+
+// SoftDevice BLE event handler
+#define NRF_SDH_BLE_ENABLED                         1
+// The number of vendor-specific UUIDs.
+#define NRF_SDH_BLE_VS_UUID_COUNT                   2
+// Attribute Table size in bytes. The size must be a multiple of 4.
+#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE             1408
+// BLE Observers - Observers and priority levels
+#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS            4
+// Include the Service Changed characteristic in the Attribute Table.
+#define NRF_SDH_BLE_SERVICE_CHANGED                 1
+
+// This setting configures how Stack events are dispatched to the application.
+#define NRF_SDH_DISPATCH_MODEL                      2 /* SoftDevice events are to be fetched manually. */
+
+// BLE Observers priorities - Invididual priorities
+#define BLE_ADV_BLE_OBSERVER_PRIO                   1
+#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO           1
+#define BLE_CONN_STATE_BLE_OBSERVER_PRIO            0
+
+// Enable Advertising module
+#define BLE_ADVERTISING_ENABLED                     1
+
+// BLE device name
+#define DEF_ELITE_DEV                               0x00000000
+#define DEF_ELITE_EDC_V2_0                          0x00020109
+#define DEF_ELITE_PEL_V2_0                          0x00070001
+#define DEF_ELITE_PEL_V3_0                          0x00070002
+#define DEF_ELITE_CPG_V1_1                          0x00080001
+#define DEF_ELITE_MMM_V1_0                          0x00090001
+#define DEF_ELITE_MODEL                             DEF_ELITE_DEV
+
+#define DEF_ELITE_DEMO_W_SOFTDEVICE                 0
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
+#define ELITE_DEVICE_NAME       "Elite-Dev"
+#define ELITE_HW_NAME           "Elite-Dev"
+#define MAJOR_PRODUCT_NUMBER    0
+#define MINOR_PRODUCT_NUMBER    0
+#define MAJOR_VERSION_NUMBER    0
+#define MINOR_VERSION_NUMBER    0
+
+#define DEF_TW1508_ENABLED      0
+
+#define DEF_LED_DRV_ENABLED     0
+#define DEF_LED_COUNT           0
+#define DEF_APA102_2020_ENABLED 0
+#define DEF_RGB_ENABLED         0
+
+#define DEF_ADC_DRV_ENABLED     0
+#define DEF_ADS8691_ENABLED     0
+#define DEF_BULTIN_ADC_ENABED   0
+
+#define DEF_DAC_DRV_ENABLED     0
+#define DEF_MAX5136_ENABLED     0
+
+#define DEF_SW_DRV_ENABLED      0
+#define DEF_MAX14802_ENABLED    0
+#define DEF_ADGS1412_ENABLED    0
+
+#define DEF_FS_ENABLED          0
+#define DEF_FS_RTT_DIR          0
+#define DEF_GD25D10C_ENABLED    0
+
+#define DEF_BTN_ENABLED         0
+
+#define DEF_RTT_JSCOP_ENABLED   0
+
+#define DEF_USBD_ENABLED        1
+
+#define DEF_UARTE_ENABLED       0
+
+#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+#define ELITE_DEVICE_NAME       "Elite-EDC"
+#define ELITE_HW_NAME           "Elite-EDCv2.0"
+#define MAJOR_PRODUCT_NUMBER    0
+#define MINOR_PRODUCT_NUMBER    2
+#define MAJOR_VERSION_NUMBER    1
+#define MINOR_VERSION_NUMBER    9
+
+#define DEF_TW1508_ENABLED      0
+
+#define DEF_LED_DRV_ENABLED     1
+#define DEF_LED_COUNT           12
+#define DEF_APA102_2020_ENABLED 1
+#define DEF_RGB_ENABLED         0
+
+#define DEF_ADC_DRV_ENABLED     1
+#define DEF_ADS8691_ENABLED     1
+#define DEF_BULTIN_ADC_ENABED   0
+
+#define DEF_DAC_DRV_ENABLED     1
+#define DEF_MAX5136_ENABLED     1
+
+#define DEF_SW_DRV_ENABLED      1
+#define DEF_MAX14802_ENABLED    0
+#define DEF_ADGS1412_ENABLED    1
+
+#define DEF_FS_ENABLED          0
+#define DEF_FS_RTT_DIR          0
+#define DEF_GD25D10C_ENABLED    0
+
+#define DEF_BTN_ENABLED         1
+
+#define DEF_RTT_JSCOP_ENABLED   0
+
+#define DEF_USBD_ENABLED        1
+
+#define DEF_UARTE_ENABLED       0
+
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+#define BOARD_IOPH              1
+#define BOARD_IOPL              0
+
+#define ELITE_DEVICE_NAME       "Elite-PEL"
+#define ELITE_HW_NAME           "Elite-PELv2.0"
+#define BOARD_IOPx              BOARD_IOPH
+#define MAJOR_PRODUCT_NUMBER    0
+#define MINOR_PRODUCT_NUMBER    7
+#define MAJOR_VERSION_NUMBER    0
+#define MINOR_VERSION_NUMBER    1
+
+#define DEF_TW1508_ENABLED      0
+
+#define DEF_LED_DRV_ENABLED     0
+#define DEF_LED_COUNT           0
+#define DEF_APA102_2020_ENABLED 0
+#define DEF_RGB_ENABLED         0
+
+#define DEF_ADC_DRV_ENABLED     1
+#define DEF_ADS8691_ENABLED     0
+#define DEF_BULTIN_ADC_ENABED   1
+
+#define DEF_DAC_DRV_ENABLED     0
+#define DEF_MAX5136_ENABLED     0
+
+#define DEF_SW_DRV_ENABLED      0
+#define DEF_MAX14802_ENABLED    0
+#define DEF_ADGS1412_ENABLED    0
+
+#define DEF_FS_ENABLED          0
+#define DEF_FS_RTT_DIR          0
+#define DEF_GD25D10C_ENABLED    0
+
+#define DEF_BTN_ENABLED         0
+
+#define DEF_RTT_JSCOP_ENABLED   0
+
+#define DEF_USBD_ENABLED        1
+
+#define DEF_UARTE_ENABLED       0
+
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V3_0)
+#define BOARD_IOPH              1
+#define BOARD_IOPL              0
+
+#define ELITE_DEVICE_NAME       "Elite-PEL"
+#define ELITE_HW_NAME           "Elite-PELv3.0"
+#define BOARD_IOPx              BOARD_IOPH
+#define MAJOR_PRODUCT_NUMBER    0
+#define MINOR_PRODUCT_NUMBER    7
+#define MAJOR_VERSION_NUMBER    0
+#define MINOR_VERSION_NUMBER    2
+
+#define DEF_TW1508_ENABLED      0
+
+#define DEF_LED_DRV_ENABLED     1
+#define DEF_LED_COUNT           1
+#define DEF_APA102_2020_ENABLED 0
+#define DEF_RGB_ENABLED         1
+
+#define DEF_ADC_DRV_ENABLED     1
+#define DEF_ADS8691_ENABLED     0
+#define DEF_BULTIN_ADC_ENABED   1
+
+#define DEF_DAC_DRV_ENABLED     0
+#define DEF_MAX5136_ENABLED     0
+
+#define DEF_SW_DRV_ENABLED      0
+#define DEF_MAX14802_ENABLED    0
+#define DEF_ADGS1412_ENABLED    0
+
+#define DEF_FS_ENABLED          0
+#define DEF_FS_RTT_DIR          0
+#define DEF_GD25D10C_ENABLED    0
+
+#define DEF_BTN_ENABLED         0
+
+#define DEF_RTT_JSCOP_ENABLED   0
+
+#define DEF_USBD_ENABLED        1
+
+#define DEF_UARTE_ENABLED       0
+
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+#define ELITE_DEVICE_NAME       "Elite-CPG"
+#define ELITE_HW_NAME           "Elite-CPGv1.1"
+#define MAJOR_PRODUCT_NUMBER    0
+#define MINOR_PRODUCT_NUMBER    8
+#define MAJOR_VERSION_NUMBER    0
+#define MINOR_VERSION_NUMBER    1
+
+#define DEF_TW1508_ENABLED      1
+
+#define DEF_LED_DRV_ENABLED     0
+#define DEF_LED_COUNT           0
+#define DEF_APA102_2020_ENABLED 0
+#define DEF_RGB_ENABLED         0
+
+#define DEF_ADC_DRV_ENABLED     0
+#define DEF_ADS8691_ENABLED     0
+#define DEF_BULTIN_ADC_ENABED   0
+
+#define DEF_DAC_DRV_ENABLED     0
+#define DEF_MAX5136_ENABLED     0
+
+#define DEF_SW_DRV_ENABLED      1
+#define DEF_MAX14802_ENABLED    1
+#define DEF_ADGS1412_ENABLED    0
+
+#define DEF_FS_ENABLED          0
+#define DEF_FS_RTT_DIR          0
+#define DEF_GD25D10C_ENABLED    0
+
+#define DEF_BTN_ENABLED         0
+
+#define DEF_RTT_JSCOP_ENABLED   0
+
+#define DEF_USBD_ENABLED        1
+
+#define DEF_UARTE_ENABLED       0
+
+#elif (DEF_ELITE_MODEL == DEF_ELITE_MMM_V1_0)
+#define ELITE_DEVICE_NAME       "Elite-MMM"
+#define ELITE_HW_NAME           "Elite-MMM"
+#define MAJOR_PRODUCT_NUMBER    0
+#define MINOR_PRODUCT_NUMBER    9
+#define MAJOR_VERSION_NUMBER    0
+#define MINOR_VERSION_NUMBER    1
+
+#define DEF_TW1508_ENABLED      0
+
+#define DEF_LED_DRV_ENABLED     0
+#define DEF_LED_COUNT           0
+#define DEF_APA102_2020_ENABLED 0
+#define DEF_RGB_ENABLED         0
+
+#define DEF_ADC_DRV_ENABLED     0
+#define DEF_ADS8691_ENABLED     0
+#define DEF_BULTIN_ADC_ENABED   0
+
+#define DEF_DAC_DRV_ENABLED     0
+#define DEF_MAX5136_ENABLED     0
+
+#define DEF_SW_DRV_ENABLED      0
+#define DEF_MAX14802_ENABLED    0
+#define DEF_ADGS1412_ENABLED    0
+
+#define DEF_FS_ENABLED          0
+#define DEF_FS_RTT_DIR          0
+#define DEF_GD25D10C_ENABLED    0
+
+#define DEF_BTN_ENABLED         0
+
+#define DEF_RTT_JSCOP_ENABLED   0
+
+#define DEF_USBD_ENABLED        1
+
+#define DEF_UARTE_ENABLED       1
+
+#endif
+
+#define BLE_ELITE_SRV_ENABLED   1
+#define BLE_ELITE_OBSERVER_PRIO 3
+#define ELITE_UUID              0xFFF0
+#define ELITE_COMPANY_CODE      "BPHS"
+#define ELITE_HW_VER                                                                           \
+    {                                                                                          \
+        MAJOR_PRODUCT_NUMBER, MINOR_PRODUCT_NUMBER, MAJOR_VERSION_NUMBER, MINOR_VERSION_NUMBER \
+    }
+
+// Maximum number of peripheral links.
+#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT          1
+// Maximum number of central links.
+#define NRF_SDH_BLE_CENTRAL_LINK_COUNT             0
+// Total link count.
+#define NRF_SDH_BLE_TOTAL_LINK_COUNT               1
+
+// Enable GATT module.
+#define NRF_BLE_GATT_ENABLED                       1
+// Priority with which BLE events are dispatched to the GATT module.
+#define NRF_BLE_GATT_BLE_OBSERVER_PRIO             1
+// Requested BLE GAP data length to be negotiated.
+#define NRF_SDH_BLE_GAP_DATA_LENGTH                251
+// GAP event length. The time set aside for this connection on every connection interval in 1.25 ms units.
+#define NRF_SDH_BLE_GAP_EVENT_LENGTH               (0xFFFF)
+// Static maximum MTU size.
+#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE              247
+
+// Enable ble device info module
+#define BLE_DIS_ENABLED                            1
+
+// Enable ble uart module
+#define BLE_NUS_ENABLED                            1
+#define BLE_UART_SRV_ENABLED                       1
+#define BLE_UART_OBSERVER_PRIO                     3
+#define NRF_UARTE_ENABLED                          1
+
+// DFU
+#define NRF_DFU_TRANSPORT_BLE                      1
+#define BLE_DFU_BLE_OBSERVER_PRIO                  2
+#define NRF_PWR_MGMT_ENABLED                       1
+
+// Enable spim
+#define SPI_ENABLED                                1
+#define SPI1_ENABLED                               1
+#define SPI1_USE_EASY_DMA                          1
+#define SPI2_ENABLED                               1
+#define SPI2_USE_EASY_DMA                          1
+#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY            7
+#define NRFX_SPIM_MISO_PULL_CFG                    3
+
+// Enable twi(i2c)
+#define TWI_ENABLED                                1
+#define TWI0_ENABLED                               1
+#define TWI0_USE_EASY_DMA                          1
+
+// Enable gpiote
+#define NRFX_GPIOTE_ENABLED                        1
+#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY            6
+
+#define COUNT_ARRAY_SIZE(x)                        (sizeof(x) / sizeof(x[0]))
+#define COUNTOF(x)                                 (sizeof(x) / sizeof(x[0]))
+
+#define u8_to_u32(a, b, c, d)                      (((uint32_t)(a) << 24) | ((uint32_t)(b) << 16) | ((uint32_t)(c) << 8) | (d))
+#define u8_to_u16(a, b)                            (((uint16_t)(a) << 8) | (b))
+#define u8_to_i32(a, b, c, d)                      (((int32_t)(a) << 24) | ((int32_t)(b) << 16) | ((int32_t)(c) << 8) | ((int32_t)(d)))
+#define u8_to_i16(a, b)                            (((int16_t)(a) << 8) | (int16_t)(b))
+
+#define DEBUG_NRF                                  1
+
+    // USBD
+
+#define APP_USBD_ENABLED                           1
+#define APP_USBD_VID                               0x1915
+#define APP_USBD_PID                               0xC00A
+#define APP_USBD_DEVICE_VER_MAJOR                  1
+#define APP_USBD_DEVICE_VER_MINOR                  1
+#define USBD_CONFIG_IRQ_PRIORITY                   _PRIO_APP_MID
+#define APP_USBD_DEVICE_VER_SUB                    0
+#define APP_USBD_STRINGS_LANGIDS                   APP_USBD_LANG_AND_SUBLANG(APP_USBD_LANG_ENGLISH, APP_USBD_SUBLANG_ENGLISH_US)
+#define APP_USBD_STRINGS_USER                      X(APP_USER_1, , APP_USBD_STRING_DESC("User 1"))
+#define APP_USBD_STRINGS_MANUFACTURER              APP_USBD_STRING_DESC("Nordic Semiconductor")
+#define APP_USBD_STRINGS_PRODUCT                   APP_USBD_STRING_DESC("nRF52 USB Product")
+#define APP_USBD_STRINGS_CONFIGURATION             APP_USBD_STRING_DESC("Default configuration")
+#define APP_USBD_STRING_ID_MANUFACTURER            1
+#define APP_USBD_STRING_ID_PRODUCT                 2
+#define APP_USBD_STRING_ID_SERIAL                  3
+#define APP_USBD_STRING_ID_CONFIGURATION           4
+#define APP_USBD_STRING_SERIAL_EXTERN              1
+#define APP_USBD_CONFIG_SELF_POWERED               1
+#define APP_USBD_CONFIG_MAX_POWER                  100
+#define APP_USBD_CONFIG_DESC_STRING_SIZE           31
+#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE         1
+#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE           32
+
+    extern uint8_t g_extern_serial_number[];
+#define APP_USBD_STRING_SERIAL                      g_extern_serial_number
+
+// USBD CDC ACM
+#define APP_USBD_CDC_ACM_ENABLED                    1
+#define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE        1
+
+// USBD DFU TRIGGER
+#define APP_USBD_NRF_DFU_TRIGGER_ENABLED            1
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 1
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL   4
+#define NRF_DFU_TRIGGER_USB_USB_SHARED              1
+
+// NRF_USBD
+#define NRFX_USBD_ENABLED                           1
+#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST     1
+#define NRFX_USBD_CONFIG_IRQ_PRIORITY               _PRIO_APP_LOW
+
+#define NRF_DFU_TRIGGER_USB_INTERFACE_NUM           0
+#define NRF_CDC_ACM_COMM_INTERFACE                  1
+#define NRF_CDC_ACM_DATA_INTERFACE                  2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __APP_CONFIG_H__ */

app/inc/block_dev_drv_if.h

@@ -0,0 +1,33 @@
+#ifndef __BLOCK_DEV_DRV_IF_H__
+#define __BLOCK_DEV_DRV_IF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdlib.h>
+
+#define BLOCK_DEV_SUCCESS (0)
+#define BLOCK_DEV_ERROR   (-1)
+typedef struct
+{
+    int (*init)(void);
+    int (*reset)(void);
+    int (*sect_erase)(uint32_t addr, uint32_t sect_cnt);
+    int (*block_erase)(uint32_t addr, uint32_t block_cnt);
+    int (*read_data)(uint8_t *p_dest, uint32_t addr, uint32_t size);
+    int (*page_prog)(uint8_t *p_src, uint32_t addr, uint32_t page_cnt);
+    const uint32_t page_size;
+    const uint32_t sect_size;
+    const uint32_t sect_count;
+    const uint32_t block_size;
+    const uint32_t block_count;
+    const uint32_t page_per_sect;
+} block_dev_drv_if_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __BLOCK_DEV_DRV_IF_H__ */

app/inc/btn.h

@@ -0,0 +1,20 @@
+#ifndef __BTN_H__
+#define __BTN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "app_config.h"
+
+#if (DEF_BTN_ENABLED)
+void btn_init(void);
+#else
+#define btn_init() 
+#endif /* DEF_BTN_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __BTN_H__ */

app/inc/builtin_saadc.h

@@ -0,0 +1,16 @@
+#ifndef __BUILTIN_SAADC_H__
+#define __BUILTIN_SAADC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "adc_drv_if.h"
+
+extern const adc_drv_if_t builtin_saadc;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __BUILTIN_SAADC_H__ */

app/inc/dac_drv.h

@@ -0,0 +1,61 @@
+#ifndef __DAC_DRV_H__
+#define __DAC_DRV_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "app_config.h"
+#include "dac_drv_if.h"
+
+#define DAC_DRV_ERROR   (-1)
+#define DAC_DRV_SUCCESS (0)
+
+#define DAC_CH0         (0x01 << 0)
+#define DAC_CH1         (0x01 << 1)
+#define DAC_CH2         (0x01 << 2)
+#define DAC_CH3         (0x01 << 3)
+
+#if (DEF_DAC_DRV_ENABLED)
+int dac_init(void);
+int dac_load(uint32_t channel_mask);
+
+/*
+   single channel output example:
+        ...
+        dac_write(DAC_CH0, 128);
+        dac_load(DAC_CH0);
+        ...
+
+   muti-channel output example:
+        ...
+        dac_write(DAC_CH0 | DAC_CH1, 128);
+        dac_load(DAC_CH0 | DAC_CH1);
+        ...
+*/
+int dac_write(uint32_t channel_mask, int32_t dac_val);
+
+/*
+   single channel output example:
+        ...
+        dac_write_through(DAC_CH0, 128);
+        ...
+
+   muti-channel output example:
+        ...
+        dac_write_through(DAC_CH0 | DAC_CH1, 128);
+        ...
+*/
+int dac_write_through(uint32_t channel_mask, int32_t dac_val);
+#else
+#define dac_init();
+#define dac_load(x);
+#define dac_write(x, y);
+#define dac_write_through(x, y);
+#endif /* ! DEF_DAC_DRV_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __DAC_DRV_H__ */

app/inc/dac_drv_if.h

@@ -0,0 +1,30 @@
+#ifndef __DAC_DRV_IF_H__
+#define __DAC_DRV_IF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdlib.h>
+
+#define DAC0  (0x01 << 0)
+#define DAC1  (0x01 << 1)
+#define DAC2  (0x01 << 2)
+#define DAC3  (0x01 << 3)
+
+typedef struct
+{
+    int (*init)(void);
+    int (*write_mode)(uint32_t channel_mask, int32_t volts);
+    int (*ldac_mode)(uint32_t channel_mask);
+    int (*write_through_mode)(uint32_t channel_mask, int32_t volts);
+    int (*power_control_mode)(uint32_t channel_mask, uint32_t ready_enable);
+    int (*reset)(void);
+} dac_drv_if_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __DAC_DRV_IF_H__ */

app/inc/elite.h

@@ -0,0 +1,32 @@
+#ifndef __ELITE_H__
+#define __ELITE_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+
+#include "elite.h"
+
+#include "app_error.h"
+
+    void elite_init(void);
+    void elite_instr_send(void *p, size_t size);
+    ret_code_t le_data_notify(uint8_t *p_value, uint16_t len);
+    ret_code_t le_event_notify(uint8_t *p_value, uint16_t len);
+    ret_code_t le_event_async_notify(uint8_t *p_value, uint16_t len, uint32_t ms_to_wait);
+
+    typedef struct
+    {
+        void (*cis_func[256])(uint8_t *ins, uint16_t size);
+        void (*vis_func[256])(uint8_t *ins, uint16_t size);
+        void (*ris_func[256])(uint8_t *ins, uint16_t size);
+    } elite_instance_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __ELITE_H__ */

app/inc/elite_board.h

@@ -0,0 +1,42 @@
+#ifndef __ELITE_BOARD_H__
+#define __ELITE_BOARD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "adc_drv.h"
+#include "app_config.h"
+#include "btn.h"
+#include "dac_drv.h"
+#include "fs.h"
+#include "led_drv.h"
+#include "sw_drv.h"
+#include "uart_drv.h"
+#include "usbd.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+#include "elite_edc_v2_0_io.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+#include "elite_pel_v2_0_io.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V3_0)
+#include "elite_pel_v3_0_io.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+#include "elite_cpg_v1_1_io.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_MMM_V1_0)
+#else
+#error "Not implemented xxx_io.h"
+#endif
+
+    void elite_board_init(void);
+    void elite_board_power_off(void);
+    void elite_drv_init(void);
+    void elite_board_demo(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __ELITE_BOARD_H__ */

app/inc/elite_cpg_v1_1.h

@@ -0,0 +1,25 @@
+#ifndef __CPG_H__
+#define __CPG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite.h"
+#include "elite_board.h"
+
+#define VERSION_DATE_YEAR   25
+#define VERSION_DATE_MONTH  4
+#define VERSION_DATE_DAY    9
+#define VERSION_DATE_HOUR   14
+#define VERSION_DATE_MINUTE 45
+
+    const elite_instance_t *cpg_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __CPG_H__ */

app/inc/elite_cpg_v1_1_io.h

@@ -0,0 +1,98 @@
+#ifndef __CPG10_IO_H__
+#define __CPG10_IO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite_board.h"
+#include "nrf_gpio.h"
+#include "nrf_spim.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+
+#define UNDEF_GPIO      0xFFFFFFFF
+#define VA1H_PIN        NRF_GPIO_PIN_MAP(0, 22)
+#define VA1L_PIN        NRF_GPIO_PIN_MAP(0, 25)
+#define VB1H_PIN        NRF_GPIO_PIN_MAP(0, 19)
+#define VB1L_PIN        NRF_GPIO_PIN_MAP(0, 21)
+#define VA2H_PIN        NRF_GPIO_PIN_MAP(0, 17)
+#define VA2L_PIN        NRF_GPIO_PIN_MAP(0, 20)
+#define TW_SCKI_0_PIN   NRF_GPIO_PIN_MAP(0, 14)
+#define TW_SCKI_1_PIN   NRF_GPIO_PIN_MAP(0, 13)
+#define ADPT_CLK_PIN    NRF_GPIO_PIN_MAP(0, 11)
+#define HV_EN_PIN       NRF_GPIO_PIN_MAP(1, 8)
+#define SPIM_CLK_PIN    NRF_GPIO_PIN_MAP(0, 12)
+#define SPIM_MISO_PIN   NRF_GPIO_PIN_MAP(1, 9)
+#define VB2H_PIN        NRF_GPIO_PIN_MAP(0, 8)
+#define VB2L_PIN        NRF_GPIO_PIN_MAP(0, 6)
+#define VA3H_PIN        NRF_GPIO_PIN_MAP(0, 5)
+#define VA3L_PIN        NRF_GPIO_PIN_MAP(0, 27)
+#define VB3H_PIN        NRF_GPIO_PIN_MAP(0, 26)
+#define VB3L_PIN        NRF_GPIO_PIN_MAP(0, 4)
+#define VA4H_PIN        NRF_GPIO_PIN_MAP(0, 1)
+#define VA4L_PIN        NRF_GPIO_PIN_MAP(0, 0)
+#define ADPT_LE_PIN     NRF_GPIO_PIN_MAP(0, 31)
+#define ADPT_CLR_PIN    NRF_GPIO_PIN_MAP(1, 15)
+#define CS_MEM_PIN      NRF_GPIO_PIN_MAP(0, 2)
+#define AIN0_PIN        NRF_GPIO_PIN_MAP(0, 30)
+#define AIN1_PIN        NRF_GPIO_PIN_MAP(0, 28)
+#define ADPT0_S4_PIN    NRF_GPIO_PIN_MAP(1, 12)
+#define ADPT0_S3_PIN    NRF_GPIO_PIN_MAP(1, 14)
+#define ADPT0_S2_PIN    NRF_GPIO_PIN_MAP(0, 3)
+#define ADPT0_S1_PIN    NRF_GPIO_PIN_MAP(1, 13)
+#define ADPT1_S4_PIN    NRF_GPIO_PIN_MAP(1, 3)
+#define ADPT1_S3_PIN    NRF_GPIO_PIN_MAP(1, 10)
+#define ADPT1_S2_PIN    NRF_GPIO_PIN_MAP(1, 6)
+#define ADPT1_S1_PIN    NRF_GPIO_PIN_MAP(1, 11)
+#define LED_R_PIN       NRF_GPIO_PIN_MAP(0, 10)
+#define LED_G_PIN       NRF_GPIO_PIN_MAP(0, 9)
+#define LED_B_PIN       NRF_GPIO_PIN_MAP(1, 2)
+#define VB4H_PIN        NRF_GPIO_PIN_MAP(0, 24)
+#define VB4L_PIN        NRF_GPIO_PIN_MAP(0, 23)
+#define SPIM_MOSI_PIN   NRF_GPIO_PIN_MAP(0, 7)
+#define TW_SDI_PIN      NRF_GPIO_PIN_MAP(0, 7)
+#define ADPT_DIN_PIN    NRF_GPIO_PIN_MAP(0, 7)
+#define UNCONNECTED_PIN NRF_GPIO_PIN_MAP(0, 2)
+
+#define PULSE_ID_NULL   0
+#define PULSE_ID_A      1
+#define PULSE_ID_B      2
+#define PULSE_ID_C      3
+#define PULSE_ID_D      4
+
+    typedef struct
+    {
+        uint32_t VAxH;
+        uint32_t VAxL;
+        uint32_t VBxH;
+        uint32_t VBxL;
+        uint32_t idle_us;     // min: 500us, max: 60sec
+        uint32_t point_us[7]; // toggle point timestamp
+        uint32_t pulse_cnt;   // min: 1, max: 0xFFFFFFFF
+        uint32_t pulse_id;    // NO_USE_IRQ / USE_TIMER1_IRQ / USE_TIMER2_IRQ
+    } pulse_gen_t;
+
+    void spim_xfer(uint32_t cs_pin,
+                   nrf_spim_mode_t spi_mode,
+                   uint8_t *p_tx_buffer,
+                   uint16_t tx_buffer_length,
+                   uint8_t *p_rx_buf,
+                   uint16_t rx_buffer_length);
+
+    void cpg11_io_init(void);
+    void cpg11_pulse_init(uint32_t hw_idx, pulse_gen_t *p_pulse_gen, uint32_t len);
+    void cpg11_pulse_start(uint32_t idx, pulse_gen_t *p_pulse_gen);
+    void cpg11_pulse_stop(uint32_t hw_idx);
+    void cpg11_pulse_suspend_by_pulse_id(uint32_t pulse_id);
+    void cpg11_pulse_resume_by_pulse_id(uint32_t pulse_id);
+
+#endif /* ! DEF_ELITE_MODEL */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __CPG10_IO_H__ */

app/inc/elite_dev_v1_0.h

@@ -0,0 +1,18 @@
+#ifndef __ELITE_DEV_H__
+#define __ELITE_DEV_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite.h"
+
+    const elite_instance_t *dev_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __ELITE_DEV_H__ */

app/inc/elite_edc_v2_0.h

@@ -0,0 +1,48 @@
+#ifndef __EDC_H__
+#define __EDC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+
+#include "dac_drv.h"
+#include "elite.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+    typedef struct
+    {
+        void (*init)(void);
+        elite_instance_t *p_elite_instance;
+    } edc20_t;
+
+    typedef struct
+    {
+        struct
+        {
+            float coeff;
+            float offset;
+        } dac_c;
+        struct
+        {
+            float coeff;
+            float offset;
+            float Voffset;
+        } dac_f[3];
+    } edc20_dac_cal_data_t;
+
+    extern edc20_t edc;
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __EDC_H__ */

app/inc/elite_edc_v2_0_io.h

@@ -0,0 +1,100 @@
+#ifndef __EDC20_IO_H__
+#define __EDC20_IO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "nrf_drv_spi.h"
+#include "nrf_gpio.h"
+#include <stdint.h>
+
+
+#define ADCA2_PIN        NRF_GPIO_PIN_MAP(0, 25)
+#define ADCA1_PIN        NRF_GPIO_PIN_MAP(0, 19)
+#define ADCA0_PIN        NRF_GPIO_PIN_MAP(0, 21)
+#define RST_SW_PIN       NRF_GPIO_PIN_MAP(0, 17)
+#define POWER_5V_EN_PIN  NRF_GPIO_PIN_MAP(0, 24)
+#define POWER_12V_EN_PIN NRF_GPIO_PIN_MAP(0, 23)
+#define OFF_PIN          NRF_GPIO_PIN_MAP(0, 15)
+#define SHUT_DOWN_PIN    NRF_GPIO_PIN_MAP(1, 8)
+#define INT9466_PIN      NRF_GPIO_PIN_MAP(0, 27)
+#define Vout_FB_PIN      NRF_GPIO_PIN_MAP(0, 26)
+#define Vout_IN_PIN      NRF_GPIO_PIN_MAP(0, 4)
+#define LEDTH_PIN        NRF_GPIO_PIN_MAP(0, 28)
+#define Iin4_TEST_PIN    NRF_GPIO_PIN_MAP(1, 12)
+#define Iin3_SEL_PIN     NRF_GPIO_PIN_MAP(1, 14)
+#define VBAT_PIN         NRF_GPIO_PIN_MAP(0, 3)
+#define Iin3_PIN         NRF_GPIO_PIN_MAP(1, 13)
+#define Iin2_PIN         NRF_GPIO_PIN_MAP(1, 3)
+#define Iin1_PIN         NRF_GPIO_PIN_MAP(1, 10)
+#define Vin2_PIN         NRF_GPIO_PIN_MAP(1, 6)
+#define Vin1_PIN         NRF_GPIO_PIN_MAP(1, 11)
+#define CV_CTRL_PIN      NRF_GPIO_PIN_MAP(0, 16)
+
+#define I2C0_SDA         NRF_GPIO_PIN_MAP(0, 11)
+#define I2C0_SCL         NRF_GPIO_PIN_MAP(0, 22)
+
+#define SPI1_CLK_PIN     NRF_GPIO_PIN_MAP(0, 13)
+#define SPI1_MOSI_PIN    NRF_GPIO_PIN_MAP(0, 14)
+
+#define CS_SW_PIN        NRF_GPIO_PIN_MAP(0, 20)
+#define CS_MEM_PIN       NRF_GPIO_PIN_MAP(0, 8)
+#define CS_ADC_PIN       NRF_GPIO_PIN_MAP(0, 6)
+#define CS_DAC_PIN       NRF_GPIO_PIN_MAP(0, 5)
+#define SPIM_CLK_PIN     NRF_GPIO_PIN_MAP(0, 12)
+#define SPIM_MOSI_PIN    NRF_GPIO_PIN_MAP(0, 7)
+#define SPIM_MISO_PIN    NRF_GPIO_PIN_MAP(1, 9)
+
+    typedef struct
+    {
+        float mV_start;
+        float mV_stop;
+        float mV_step;
+        uint32_t uS_step;
+        uint32_t cycles;
+        bool hi_z_en;
+    } elite_dac_config_t;
+
+    void gpio_init(void);
+    void circuit_selection_vin_0(void);
+    void circuit_selection_vin_1(void);
+    void circuit_selection_vin_2(void);
+    void circuit_selection_Iin_0(void);
+    void circuit_selection_Iin_1(void);
+    void circuit_selection_Iin_2(void);
+    void circuit_selection_Iin_3(void);
+    void circuit_selection_Iin_4(void);
+    void circuit_selection_dac_coarse_tune_c(void);
+    void circuit_selection_dac_fine_tune_f0(void);
+    void circuit_selection_dac_fine_tune_f1(void);
+    void circuit_selection_dac_fine_tune_f2(void);
+    void circuit_selection_cv3_config(void);
+    void circuit_selection_cc_config(void);
+    void circuit_selection_dac_circuit_open(void);
+
+    void twi_init(void);
+    void twi0_write_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t data_len);
+    void twi0_read_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *p_rx_buf, uint8_t rx_buffer_length);
+
+    void spi_init(void);
+    void spi1_write(uint8_t *p_tx_buffer, uint16_t tx_buffer_length);
+    void spim_xfer(uint32_t cs_pin, nrf_spim_mode_t mode, uint8_t *p_tx_buffer, uint16_t tx_buffer_length, uint8_t *p_rx_buf, uint16_t rx_buffer_length);
+    void spi2_set_mode(nrf_drv_spi_mode_t mode);
+
+    void edc20_io_init(void);
+    void edc20_io_power_off(void);
+    void edc20_io_power_on(void);
+
+    void edc20_dac_tim_start(uint32_t period, void (*callback)(void *p_arg), void *p_arg);
+    void edc20_dac_tim_stop(void);
+
+    void edc20_adc_tim_start(elite_dac_config_t *p_config);
+    void edc20_adc_tim_stop(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __EDC20_IO_H__ */

app/inc/elite_mmm_v1_0.h

@@ -0,0 +1,18 @@
+#ifndef __ELITE_MMM_H__
+#define __ELITE_MMM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite.h"
+
+    const elite_instance_t *mmm_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __ELITE_MMM_H__ */

app/inc/elite_pel_v2_0.h

@@ -0,0 +1,70 @@
+#ifndef __ELITE_PEL_V2_0_H__
+#define __ELITE_PEL_V2_0_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite.h"
+#include "elite_board.h"
+
+#define VERSION_DATE_YEAR   25
+#define VERSION_DATE_MONTH  8
+#define VERSION_DATE_DAY    29
+#define VERSION_DATE_HOUR   17
+#define VERSION_DATE_MINUTE 24
+
+#define PEL_0P5R_MASK       (0x01 << 0)
+#define PEL_1P0R_MASK       (0x01 << 1)
+#define PEL_2P0R_MASK       (0x01 << 2)
+#define PEL_4P0R_MASK       (0x01 << 3)
+#define PEL_8P0R_MASK       (0x01 << 4)
+#define PEL_16P2R_MASK      (0x01 << 5)
+#define PEL_32P4R_MASK      (0x01 << 6)
+#define PEL_63P4R_MASK      (0x01 << 7)
+#define PEL_127R_MASK       (0x01 << 8)
+#define PEL_255R_MASK       (0x01 << 9)
+#define PEL_511R_MASK       (0x01 << 10)
+#define PEL_1000R_MASK      (0x01 << 11)
+
+    typedef struct __PACKED
+    {
+        uint16_t mem_board_id;
+        uint16_t packet_seq;
+        uint32_t notify_time;
+
+        int32_t raw_output_r1;
+        int32_t raw_output_r2;
+        int32_t raw_output_vo;
+        int32_t raw_output_vc;
+        int32_t raw_output_ve;
+        float output_r1_mv;
+        float output_r2_mv;
+        float output_vo_mv;
+        float output_vc_mv;
+        float output_ve_mv;
+
+        float hold_r1_v;
+        float hold_r2_v;
+        float hold_out_v;
+        float hold_vcc_v;
+        float hold_vee_v;
+        float current;
+
+        uint16_t resis_pattern_id;
+        uint16_t resis_bitsmask;
+        float resis_g_value;
+        uint32_t mode_complete : 4;
+        uint32_t rsvd          : 28;
+        uint32_t payload[9];
+    } scan_mode_notify_packet_t;
+
+    const elite_instance_t *pel_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __ELITE_PEL_V2_0_H__ */

app/inc/elite_pel_v2_0_io.h

@@ -0,0 +1,121 @@
+#ifndef __PEL20_IO_H__
+#define __PEL20_IO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite_board.h"
+#include "nrf_gpio.h"
+#include "nrf_saadc.h"
+#include "nrf_spim.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+
+#define RELAY1_PIN        NRF_GPIO_PIN_MAP(1, 10)
+#define RELAY2_PIN        NRF_GPIO_PIN_MAP(1, 15)
+
+#define TP1_PIN           NRF_GPIO_PIN_MAP(0, 5)
+#define TP2_PIN           NRF_GPIO_PIN_MAP(0, 26)
+
+#define SAMPLE_R_PIN      NRF_GPIO_PIN_MAP(1, 11)
+#define SAMPLE_V_PIN      NRF_GPIO_PIN_MAP(1, 6)
+
+#define CATHODE_PIN       NRF_GPIO_PIN_MAP(0, 8)
+#define ANODE_PIN         NRF_GPIO_PIN_MAP(0, 7)
+
+#define OUTPUT_R1_PIN     NRF_GPIO_PIN_MAP(0, 31)
+#define OUTPUT_R2_PIN     NRF_GPIO_PIN_MAP(0, 28)
+#define OUTPUT_VO_PIN     NRF_GPIO_PIN_MAP(0, 29)
+#define OUTPUT_VC_PIN     NRF_GPIO_PIN_MAP(0, 2)
+#define OUTPUT_VE_PIN     NRF_GPIO_PIN_MAP(0, 3)
+
+#define OUTPUT_R1_CHANNEL 7
+#define OUTPUT_R2_CHANNEL 4
+#define OUTPUT_VO_CHANNEL 5
+#define OUTPUT_VC_CHANNEL 0
+#define OUTPUT_VE_CHANNEL 1
+
+#define OUTPUT_R1_IDX     0
+#define OUTPUT_R2_IDX     1
+#define OUTPUT_VO_IDX     2
+#define OUTPUT_VC_IDX     3
+#define OUTPUT_VE_IDX     4
+
+#define INPUT_1_PIN       NRF_GPIO_PIN_MAP(0, 15)
+#define INPUT_2_PIN       NRF_GPIO_PIN_MAP(0, 13)
+#define INPUT_3_PIN       NRF_GPIO_PIN_MAP(0, 20)
+#define INPUT_4_PIN       NRF_GPIO_PIN_MAP(1, 0)
+#define INPUT_5_PIN       NRF_GPIO_PIN_MAP(0, 25)
+#define INPUT_6_PIN       NRF_GPIO_PIN_MAP(0, 11)
+#define INPUT_7_PIN       NRF_GPIO_PIN_MAP(0, 14)
+#define INPUT_8_PIN       NRF_GPIO_PIN_MAP(0, 17)
+#define INPUT_9_PIN       NRF_GPIO_PIN_MAP(0, 18)
+#define INPUT_10_PIN      NRF_GPIO_PIN_MAP(0, 21)
+#define INPUT_11_PIN      NRF_GPIO_PIN_MAP(0, 19)
+#define INPUT_12_PIN      NRF_GPIO_PIN_MAP(0, 22)
+
+#define WP_MEM_PIN        NRF_GPIO_PIN_MAP(0, 12)
+#define CS_MEM_PIN        NRF_GPIO_PIN_MAP(0, 6)
+#define SPIM_MOSI_PIN     NRF_GPIO_PIN_MAP(0, 27)
+#define SPIM_CLK_PIN      NRF_GPIO_PIN_MAP(0, 4)
+#define SPIM_MISO_PIN     NRF_GPIO_PIN_MAP(1, 9)
+
+    typedef struct
+    {
+        uint32_t anode_pin;
+        uint32_t cathode_pin;
+        uint32_t smaple_r_pin;
+        uint32_t sample_v_pin;
+        uint32_t test_pin;
+        uint32_t point_us[5]; // toggle point timestamp
+        uint32_t pulse_cnt;   // min: 1, max: 0xFFFFFFFF
+        uint32_t mode;        // 0: IOPL mode, 1: IOPH mode
+        nrf_saadc_gain_t gain;
+        nrf_saadc_acqtime_t smaple_time;
+        int32_t adc_timing_shift;
+        void (*convt_new_arrival_cb)(void);
+    } pel_config_t;
+
+    typedef struct
+    {
+        nrf_saadc_gain_t gain;
+        nrf_saadc_acqtime_t smaple_time;
+        uint32_t channels[5];
+        int16_t results[5];
+        float results_f[5];
+        void (*convt_new_arrival_cb)(void);
+    } pel_adc_t;
+
+    typedef struct
+    {
+        NRF_TIMER_Type *pulse_tmr;
+        uint32_t pulse_irq_n;
+        uint32_t pulse_cnt;
+        uint32_t pulse_is_running;
+        pel_adc_t adc;
+    } pel_hw_t;
+
+    extern pel_hw_t pel_hw;
+
+    void spim_xfer(uint32_t cs_pin,
+                   nrf_spim_mode_t spi_mode,
+                   uint8_t *p_tx_buffer,
+                   uint16_t tx_buffer_length,
+                   uint8_t *p_rx_buf,
+                   uint16_t rx_buffer_length);
+
+    void pel20_io_init(void);
+    void pel_pulse_gen_init(pel_config_t cfg);
+    void pel_pulse_gen_start(void);
+    void pel_pulse_gen_stop(void);
+
+#endif /* ! DEF_ELITE_MODEL */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __PEL20_IO_H__ */

app/inc/elite_pel_v3_0.h

@@ -0,0 +1,69 @@
+#ifndef __PEL_V3_0_H__
+#define __PEL_V3_0_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite.h"
+#include "elite_board.h"
+
+#define VERSION_DATE_YEAR   25
+#define VERSION_DATE_MONTH  8
+#define VERSION_DATE_DAY    28
+#define VERSION_DATE_HOUR   17
+#define VERSION_DATE_MINUTE 46
+
+#define PEL_0P5R_MASK       (0x01 << 0)
+#define PEL_1P0R_MASK       (0x01 << 1)
+#define PEL_2P0R_MASK       (0x01 << 2)
+#define PEL_4P0R_MASK       (0x01 << 3)
+#define PEL_8P0R_MASK       (0x01 << 4)
+#define PEL_16P2R_MASK      (0x01 << 5)
+#define PEL_32P4R_MASK      (0x01 << 6)
+#define PEL_63P4R_MASK      (0x01 << 7)
+#define PEL_127R_MASK       (0x01 << 8)
+#define PEL_255R_MASK       (0x01 << 9)
+#define PEL_511R_MASK       (0x01 << 10)
+#define PEL_1000R_MASK      (0x01 << 11)
+
+    typedef struct __PACKED
+    {
+        uint16_t mem_board_id;
+        uint16_t packet_seq;
+        uint32_t notify_time;
+
+        int32_t raw_acs37030_vref;
+        int32_t raw_i_out;
+        int32_t raw_output_vo;
+        int32_t raw_output_vc;
+        int32_t raw_output_ve;
+        float acs37030_vref_mv;
+        float i_out_mv;
+        float output_vo_mv;
+        float output_vc_mv;
+        float output_ve_mv;
+
+        float acs37030_vref_v;
+        float hold_acs37030_out_v;
+        float hold_out_v;
+        float hold_vcc_v;
+        float hold_vee_v;
+        float acs37030_current_a;
+
+        uint16_t resis_pattern_id;
+        uint16_t resis_bitsmask;
+        float resis_g_value;
+        uint32_t mode_complete : 4;
+        uint32_t rsvd          : 28;
+        uint32_t payload[9];
+    } scan_mode_notify_packet_t;
+    const elite_instance_t *pel_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __PEL_V3_0_H__ */

app/inc/elite_pel_v3_0_io.h

@@ -0,0 +1,129 @@
+#ifndef __PEL_V3_0_IO_H__
+#define __PEL_V3_0_IO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite_board.h"
+#include "nrf_gpio.h"
+#include "nrf_saadc.h"
+#include "nrf_spim.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_PEL_V3_0)
+#define INPUT_1_PIN         NRF_GPIO_PIN_MAP(0, 15)
+#define INPUT_2_PIN         NRF_GPIO_PIN_MAP(0, 13)
+#define INPUT_3_PIN         NRF_GPIO_PIN_MAP(0, 20)
+#define INPUT_4_PIN         NRF_GPIO_PIN_MAP(1, 0)
+#define INPUT_5_PIN         NRF_GPIO_PIN_MAP(0, 25)
+#define INPUT_6_PIN         NRF_GPIO_PIN_MAP(0, 11)
+#define INPUT_7_PIN         NRF_GPIO_PIN_MAP(0, 14)
+#define INPUT_8_PIN         NRF_GPIO_PIN_MAP(0, 17)
+#define INPUT_9_PIN         NRF_GPIO_PIN_MAP(1, 8)
+#define INPUT_10_PIN        NRF_GPIO_PIN_MAP(0, 21)
+#define INPUT_11_PIN        NRF_GPIO_PIN_MAP(0, 19)
+#define INPUT_12_PIN        NRF_GPIO_PIN_MAP(0, 22)
+
+#define RESET_PIN           NRF_GPIO_PIN_MAP(0, 18)
+#define TP1_PIN             NRF_GPIO_PIN_MAP(0, 5)
+#define TP2_PIN             NRF_GPIO_PIN_MAP(0, 26)
+#define SAMPLE_I_PIN        NRF_GPIO_PIN_MAP(1, 11)
+#define SAMPLE_V_PIN        NRF_GPIO_PIN_MAP(1, 6)
+#define ANODE_PIN           NRF_GPIO_PIN_MAP(0, 7)
+#define CATHODE_PIN         NRF_GPIO_PIN_MAP(0, 8)
+#define HOT_SWAP_1_PIN      NRF_GPIO_PIN_MAP(0, 1)
+#define HOT_SWAP_SIGNAL_PIN NRF_GPIO_PIN_MAP(0, 0)
+#define INA_HI_PIN          NRF_GPIO_PIN_MAP(1, 12)
+
+#define WP_MEM_PIN          NRF_GPIO_PIN_MAP(0, 12)
+#define CS_MEM_PIN          NRF_GPIO_PIN_MAP(0, 6)
+#define SPIM_MOSI_PIN       NRF_GPIO_PIN_MAP(0, 27)
+#define SPIM_CLK_PIN        NRF_GPIO_PIN_MAP(0, 4)
+#define SPIM_MISO_PIN       NRF_GPIO_PIN_MAP(1, 9)
+
+#define LED_IOPL_PIN        NRF_GPIO_PIN_MAP(0, 24) // pin60
+#define LED_IOPH_PIN        NRF_GPIO_PIN_MAP(0, 16) // pin62
+
+#define LED_R_PINS              \
+    {                           \
+        NRF_GPIO_PIN_MAP(1, 13) \
+    }
+#define LED_G_PINS             \
+    {                          \
+        NRF_GPIO_PIN_MAP(1, 3) \
+    }
+#define LED_B_PINS              \
+    {                           \
+        NRF_GPIO_PIN_MAP(1, 10) \
+    }
+
+#define OUTPUT_ACS37030_VREF_CHANNEL 7
+#define OUTPUT_I_OUT_CHANNEL         4
+#define OUTPUT_VO_CHANNEL            5
+#define OUTPUT_VC_CHANNEL            0
+#define OUTPUT_VE_CHANNEL            1
+
+#define OUTPUT_ACS37030_REF_IDX      0
+#define OUTPUT_I_OUT_IDX             1
+#define OUTPUT_VO_IDX                2
+#define OUTPUT_VC_IDX                3
+#define OUTPUT_VE_IDX                4
+
+    typedef struct
+    {
+        uint32_t anode_pin;
+        uint32_t ina_hi_pin;
+        uint32_t smaple_i_pin;
+        uint32_t sample_v_pin;
+        uint32_t test_pin;
+        uint32_t point_us[5]; // toggle point timestamp
+        uint32_t pulse_cnt;   // min: 1, max: 0xFFFFFFFF
+        uint32_t mode;        // 0: IOPL mode, 1: IOPH mode
+        nrf_saadc_gain_t gain;
+        nrf_saadc_acqtime_t smaple_time;
+        int32_t adc_timing_shift;
+        void (*convt_new_arrival_cb)(void);
+    } pel_config_t;
+
+    typedef struct
+    {
+        nrf_saadc_gain_t gain;
+        nrf_saadc_acqtime_t smaple_time;
+        uint32_t channels[5];
+        int16_t results[5];
+        float results_f[5];
+        void (*convt_new_arrival_cb)(void);
+    } pel_adc_t;
+
+    typedef struct
+    {
+        NRF_TIMER_Type *pulse_tmr;
+        uint32_t pulse_irq_n;
+        uint32_t pulse_cnt;
+        uint32_t pulse_is_running;
+        pel_adc_t adc;
+    } pel_hw_t;
+
+    extern pel_hw_t pel_hw;
+
+    void spim_xfer(uint32_t cs_pin,
+                   nrf_spim_mode_t spi_mode,
+                   uint8_t *p_tx_buffer,
+                   uint16_t tx_buffer_length,
+                   uint8_t *p_rx_buf,
+                   uint16_t rx_buffer_length);
+
+    void pel30_io_init(void);
+    void pel_pulse_gen_init(pel_config_t cfg);
+    void pel_pulse_gen_start(void);
+    void pel_pulse_gen_stop(void);
+
+#endif /* ! DEF_ELITE_MODEL */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __PEL_V3_0_IO_H__ */

app/inc/fs.h

@@ -0,0 +1,42 @@
+#ifndef __FS_H__
+#define __FS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "app_config.h"
+
+#include "lfs.h"
+#include "lfs_util.h"
+
+typedef lfs_file_t file_t;
+
+#define FS_O_RDONLY LFS_O_RDONLY // Open a file as read only
+#define FS_O_WRONLY LFS_O_WRONLY // Open a file as write only
+#define FS_O_RDWR   LFS_O_RDWR   // Open a file as read and write
+#define FS_O_CREAT  LFS_O_CREAT  // Create a file if it does not exist
+#define FS_O_EXCL   LFS_O_EXCL   // Fail if a file already exists
+#define FS_O_TRUNC  LFS_O_TRUNC  // Truncate the existing file to zero size
+#define FS_O_APPEND LFS_O_APPEND // Move to end of file on every write
+
+#if (DEF_FS_ENABLED)
+void fs_init(void);
+int fs_file_open(file_t *hFile, char *filename, uint32_t attr);
+int fs_file_write(file_t *hFile, void *write, uint32_t size);
+int fs_file_read(file_t *hFile, void *read, uint32_t size);
+int fs_file_close(file_t *hFile);
+int fs_dir(char *path);
+#else
+#define fs_init()
+#define fs_file_write(x, y, z)
+#define fs_file_read(x, y, z)
+#define fs_file_close(x)
+#define fs_dir(x)
+#endif /* ! DEF_FS_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __FS_H__ */

app/inc/gd25d10c.h

@@ -0,0 +1,22 @@
+#ifndef __GD25D10C_H__
+#define __GD25D10C_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "app_config.h"
+#include "elite_board.h"
+#include "block_dev_drv_if.h"
+
+#if (DEF_GD25D10C_ENABLED)
+
+extern const block_dev_drv_if_t gd25d110c;
+
+#endif /* ! DEF_GD25D10C_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __GD25D10C_H__ */

app/inc/le_uart_srv.h

@@ -0,0 +1,21 @@
+#ifndef __LE_UART_SRV_H__
+#define __LE_UART_SRV_H__
+
+#include "app_config.h"
+#include "sdk_errors.h"
+
+#define OPCODE_LENGTH 1
+#define HANDLE_LENGTH 2
+
+/**@brief   Maximum length of data (in bytes) that can be transmitted to the peer by the Nordic UART service module. */
+#if defined(NRF_SDH_BLE_GATT_MAX_MTU_SIZE) && (NRF_SDH_BLE_GATT_MAX_MTU_SIZE != 0)
+#define BLE_UART_MAX_DATA_LEN (NRF_SDH_BLE_GATT_MAX_MTU_SIZE - OPCODE_LENGTH - HANDLE_LENGTH)
+#else
+#define BLE_UART_MAX_DATA_LEN (BLE_GATT_MTU_SIZE_DEFAULT - OPCODE_LENGTH - HANDLE_LENGTH)
+#warning NRF_SDH_BLE_GATT_MAX_MTU_SIZE is not defined.
+#endif
+
+void le_uart_srv_init(void);
+ret_code_t le_uart_notify(uint8_t * p_value, uint16_t len);
+
+#endif // !__LE_UART_SRV_H__

app/inc/led_drv.h

@@ -0,0 +1,103 @@
+#ifndef __LED_DRV_H__
+#define __LED_DRV_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "led_drv_if.h"
+
+#define LED_DRV_ERROR   (-1)
+#define LED_DRV_SUCCESS (0)
+
+#if (DEF_APA102_2020_ENABLED)
+#define LED_NONE                        \
+    (struct led_color)                  \
+    {                                   \
+        .R = 0x00, .G = 0x00, .B = 0x00 \
+    }
+#define LED_RED                         \
+    (struct led_color)                  \
+    {                                   \
+        .R = 0xFF, .G = 0x00, .B = 0x00 \
+    }
+#define LED_ORANGE                      \
+    (struct led_color)                  \
+    {                                   \
+        .R = 0xFF, .G = 0x58, .B = 0x09 \
+    }
+#define LED_YELLOW                      \
+    (struct led_color)                  \
+    {                                   \
+        .R = 0xEF, .G = 0x9F, .B = 0x00 \
+    }
+#define LED_GREEN                       \
+    (struct led_color)                  \
+    {                                   \
+        .R = 0x00, .G = 0xFF, .B = 0x00 \
+    }
+#define LED_CYAN                        \
+    (struct led_color)                  \
+    {                                   \
+        .R = 0x00, .G = 0xFF, .B = 0xFF \
+    }
+#define LED_BLUE                        \
+    (struct led_color)                  \
+    {                                   \
+        .R = 0x00, .G = 0x00, .B = 0xFF \
+    }
+#define LED_PURPLE                      \
+    (struct led_color)                  \
+    {                                   \
+        .R = 0xFF, .G = 0x00, .B = 0xFF \
+    }
+
+#elif (DEF_RGB_ENABLED)
+#define LED_NONE \
+    (struct led_color) { .R = 0, .G = 0, .B = 0 }
+#define LED_RED \
+    (struct led_color) { .R = 1, .G = 0, .B = 0 }
+#define LED_YELLOW \
+    (struct led_color) { .R = 1, .G = 1, .B = 0 }
+#define LED_WHITE \
+    (struct led_color) { .R = 1, .G = 1, .B = 1 }
+#define LED_GREEN \
+    (struct led_color) { .R = 0, .G = 1, .B = 0 }
+#define LED_CYAN \
+    (struct led_color) { .R = 0, .G = 1, .B = 1 }
+#define LED_BLUE \
+    (struct led_color) { .R = 0, .G = 0, .B = 1 }
+#define LED_PURPLE \
+    (struct led_color) { .R = 1, .G = 0, .B = 1 }
+#endif
+
+#define LED_OFF               LED_NONE
+#define LED_ON                LED_GREEN
+#define LED_ERROR             LED_RED
+#define LED_IDLE_DISCONNECTED LED_YELLOW
+#define LED_IDLE_CONNECTED    LED_GREEN
+#define LED_REC               LED_CYAN
+#define LED_IDENTIFY_DEV      LED_PURPLE
+#define LED_BUTTON_PRESS      LED_YELLOW
+
+#if (DEF_LED_DRV_ENABLED)
+    int32_t led_init(void);
+    int32_t led_set(struct led_color color);
+    int32_t led_single_led_set(uint32_t idx, struct led_color color, uint8_t brightness);
+    int32_t led_as_rainbow(void);
+
+#else
+#define led_init()
+#define led_set(x)
+#define led_single_led_set(x, y, z)
+#define led_as_rainbow(x)
+
+#endif /* ! DEF_LED_DRV_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __LED_DRV_H__ */

app/inc/led_drv_if.h

@@ -0,0 +1,29 @@
+#ifndef __LED_DRV_IF_H__
+#define __LED_DRV_IF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+
+struct led_color
+{
+    uint8_t B;
+    uint8_t G;
+    uint8_t R;
+};
+
+typedef struct
+{
+    int32_t (*init)(uint32_t cnt);
+    int32_t (*set)(uint32_t idx, struct led_color color, uint8_t brightness);
+} led_drv_if_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __LED_DRV_IF_H__ */

app/inc/led_rgb.h

@@ -0,0 +1,26 @@
+#ifndef __LED_RGB_H__
+#define __LED_RGB_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+
+#include "elite_board.h"
+#include "led_drv_if.h"
+#if (DEF_RGB_ENABLED)
+
+#if !(defined(LED_R_PINS) && defined(LED_G_PINS) && defined(LED_B_PINS))
+#error "LED_R_PINS, LED_G_PINS and LED_B_PINS must all be defined"
+#endif
+    extern const led_drv_if_t led_rgb_drv;
+
+#endif /* ! DEF_RGB_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __LED_RGB_H__ */

app/inc/max14802.h

@@ -0,0 +1,31 @@
+#ifndef __MAX14802_H__
+#define __MAX14802_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "sw_drv_if.h"
+
+#if (DEF_MAX14802_ENABLED)
+
+#define MAX14802_COUNT  1
+#define SW_PER_MAX14802 16
+#define SW_TOTAL_COUNT  (SW_PER_MAX14802 * MAX14802_COUNT)
+#define SW_PER_BYTE     8
+
+#if (SW_TOTAL_COUNT > 64)
+#error "unsupport"
+#endif /* ! SW_TOTAL_COUNT */
+
+extern const sw_drv_if_t max14802;
+
+#endif /* ! DEF_MAX14802_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !__MAX14802_H__

app/inc/max5136.h

@@ -0,0 +1,20 @@
+#ifndef __MAX5136_H__
+#define __MAX5136_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "app_config.h"
+#include "elite_board.h"
+#include "dac_drv_if.h"
+
+#if (DEF_MAX5136_ENABLED)
+extern dac_drv_if_t max5136;
+#endif /* ! DEF_MAX5316_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __MAX5136_H__ */

app/inc/sw_drv.h

@@ -0,0 +1,36 @@
+#ifndef __SW_DRV_H__
+#define __SW_DRV_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "app_config.h"
+#include "sw_drv_if.h"
+
+#define SW_DRV_ERROR   (-1)
+#define SW_DRV_SUCCESS (0)
+
+#if (DEF_SW_DRV_ENABLED)
+
+int sw_init(void);
+int sw_reset(void);
+int sw_write(sw_t sw_mask);
+int sw_read(sw_t *p_sw_mask);
+int sw_count(uint32_t *p_sw_count);
+
+#else 
+
+#define sw_init() 
+#define sw_reset() 
+#define sw_write(x) 
+#define sw_read(x) 
+#define sw_count(x) 
+
+#endif /* ! DEF_SW_DRV_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __SW_DRV_H__ */

app/inc/sw_drv_if.h

@@ -0,0 +1,96 @@
+#ifndef __SW_DRV_IF_H__
+#define __SW_DRV_IF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdlib.h>
+
+typedef union
+{
+    uint64_t val;
+    struct
+    {
+        uint64_t sw0  : 1;
+        uint64_t sw1  : 1;
+        uint64_t sw2  : 1;
+        uint64_t sw3  : 1;
+        uint64_t sw4  : 1;
+        uint64_t sw5  : 1;
+        uint64_t sw6  : 1;
+        uint64_t sw7  : 1;
+        uint64_t sw8  : 1;
+        uint64_t sw9  : 1;
+        uint64_t sw10 : 1;
+        uint64_t sw11 : 1;
+        uint64_t sw12 : 1;
+        uint64_t sw13 : 1;
+        uint64_t sw14 : 1;
+        uint64_t sw15 : 1;
+        uint64_t sw16 : 1;
+        uint64_t sw17 : 1;
+        uint64_t sw18 : 1;
+        uint64_t sw19 : 1;
+        uint64_t sw20 : 1;
+        uint64_t sw21 : 1;
+        uint64_t sw22 : 1;
+        uint64_t sw23 : 1;
+        uint64_t sw24 : 1;
+        uint64_t sw25 : 1;
+        uint64_t sw26 : 1;
+        uint64_t sw27 : 1;
+        uint64_t sw28 : 1;
+        uint64_t sw29 : 1;
+        uint64_t sw30 : 1;
+        uint64_t sw31 : 1;
+        uint64_t sw32 : 1;
+        uint64_t sw33 : 1;
+        uint64_t sw34 : 1;
+        uint64_t sw35 : 1;
+        uint64_t sw36 : 1;
+        uint64_t sw37 : 1;
+        uint64_t sw38 : 1;
+        uint64_t sw39 : 1;
+        uint64_t sw40 : 1;
+        uint64_t sw41 : 1;
+        uint64_t sw42 : 1;
+        uint64_t sw43 : 1;
+        uint64_t sw44 : 1;
+        uint64_t sw45 : 1;
+        uint64_t sw46 : 1;
+        uint64_t sw47 : 1;
+        uint64_t sw48 : 1;
+        uint64_t sw49 : 1;
+        uint64_t sw50 : 1;
+        uint64_t sw51 : 1;
+        uint64_t sw52 : 1;
+        uint64_t sw53 : 1;
+        uint64_t sw54 : 1;
+        uint64_t sw55 : 1;
+        uint64_t sw56 : 1;
+        uint64_t sw57 : 1;
+        uint64_t sw58 : 1;
+        uint64_t sw59 : 1;
+        uint64_t sw60 : 1;
+        uint64_t sw61 : 1;
+        uint64_t sw62 : 1;
+        uint64_t sw63 : 1;
+    };
+} sw_t;
+
+typedef struct
+{
+    int (*init)(void);
+    int (*reset)(void);
+    int (*write)(sw_t sw_mask);
+    int (*read)(sw_t *p_sw_mask);
+    int (*get_sw_count)(uint32_t *p_sw_count);
+} sw_drv_if_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __SW_DRV_IF_H__ */

app/inc/tw1508.h

@@ -0,0 +1,21 @@
+#ifndef __TW1508_H__
+#define __TW1508_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite_board.h"
+
+#if (DEF_TW1508_ENABLED)
+    void tw1508_set(uint16_t out_0, uint16_t out_1);
+    void tw1508_init(void);
+#endif /* ! DEF_TW1508_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __CPG_H__ */

app/inc/uart_drv.h

@@ -0,0 +1,29 @@
+#pragma once
+#ifndef __UART_DRV_H__
+#define __UART_DRV_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "sdk_errors.h"
+
+#if (DEF_UARTE_ENABLED)
+    void uart_init(void);
+    int uart_send(void *p_data, uint32_t size);
+    int uart_recv(void *p_data, uint32_t max_size);
+    ret_code_t uart_set_baud(uint32_t baudrate);
+#else
+#define uart_init()
+#define uart_send(...) ;
+#define uart_recv(...) ;
+#define uart_set_baud(...)
+#endif /* ! DEF_UARTE_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __UART_DRV_H__ */

app/inc/usbd.h

@@ -0,0 +1,25 @@
+#ifndef __USBD_H__
+#define __USBD_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "app_config.h"
+
+#if (DEF_USBD_ENABLED)
+void usbd_init(void);
+int32_t usbd_ser_write(uint8_t *p_data, uint32_t size, TickType_t timeout);
+int32_t usbd_ser_read(uint8_t *p_data, uint32_t size, TickType_t timeout);
+#else
+#define usbd_init()
+#define usbd_ser_write(...);
+#define usbd_ser_read(...);
+
+#endif /* ! DEF_FS_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __USBD_H__ */

app/inc/usbd_dfu_trigger.h

@@ -0,0 +1,74 @@
+/**
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic
+ *    Semiconductor ASA integrated circuit in a product or a software update for
+ *    such product, must reproduce the above copyright notice, this list of
+ *    conditions and the following disclaimer in the documentation and/or other
+ *    materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ *    Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary form under this license must not be reverse
+ *    engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef USBD_DFU_TRIGGER_H
+#define USBD_DFU_TRIGGER_H
+
+#include "sdk_errors.h"
+
+/**
+ * @defgroup nrf_dfu_trigger_usb USB DFU trigger library
+ * @ingroup app_common
+ *
+ * @brief @tagAPI52840 USB DFU trigger library is used to enter the bootloader and read the firmware version.
+ *
+ * @details See @ref lib_dfu_trigger_usb for additional documentation.
+ * @{
+ */
+
+/**
+ * @brief Function for initializing the USB DFU trigger library.
+ *
+ * @note  If the USB is also used for other purposes, then this function must be called after USB is
+ *        initialized but before it is enabled. In this case, the configuration flag @ref
+ *        NRF_DFU_TRIGGER_USB_USB_SHARED must be set to 1.
+ *
+ * @note  Calling this again after the first success has no effect and returns @ref NRF_SUCCESS.
+ *
+ * @note  If @ref APP_USBD_CONFIG_EVENT_QUEUE_ENABLE is on (1), USB events must be handled manually.
+ *        See @ref app_usbd_event_queue_process.
+ *
+ * @retval NRF_SUCCESS  On successful initialization.
+ * @return An error code on failure, for example if called at a wrong time.
+ */
+ret_code_t nrf_dfu_trigger_usb_init(void);
+
+/** @} */
+
+#endif //NRF_DFU_TRIGGER_USB_H

app/src/adc_drv.c

@@ -0,0 +1,96 @@
+#include "adc_drv.h"
+
+#if (DEF_ADC_DRV_ENABLED && DEF_ADS8691_ENABLED)
+#include "ads8691.h"
+static const adc_drv_if_t *p_inst = &ads8691;
+#elif (DEF_ADC_DRV_ENABLED && DEF_BULTIN_ADC_ENABED)
+#include "builtin_saadc.h"
+static const adc_drv_if_t *p_inst = &builtin_saadc;
+#endif
+
+#if (DEF_ADC_DRV_ENABLED)
+
+#include <stdlib.h>
+
+int adc_init(void)
+{
+    if (p_inst == NULL)
+    {
+        return ADC_DRV_ERROR;
+    }
+    return p_inst->init();
+}
+
+int adc_reset(void)
+{
+    if (p_inst == NULL)
+    {
+        return ADC_DRV_ERROR;
+    }
+    return p_inst->reset();
+}
+
+int adc_gain(adc_gain_t gain)
+{
+    if (p_inst == NULL)
+    {
+        return ADC_DRV_ERROR;
+    }
+    return p_inst->gain(gain);
+}
+
+int adc_read(uint32_t channel, int32_t *adc_val)
+{
+    if (p_inst == NULL)
+    {
+        return ADC_DRV_ERROR;
+    }
+    return p_inst->read(channel, adc_val);
+}
+
+int adc_read_mutiple_channels(uint32_t *p_channel, int32_t *p_adc_val, uint32_t cnt)
+{
+    if (p_inst == NULL)
+    {
+        return ADC_DRV_ERROR;
+    }
+    return p_inst->read_multiple_channels(p_channel, p_adc_val, cnt);
+}
+
+int adc_read_mutiple_channels_ex(uint32_t *p_channel, int32_t *p_adc_val, uint32_t cnt, void (*preliminary_action)(void))
+{
+    if (p_inst == NULL)
+    {
+        return ADC_DRV_ERROR;
+    }
+    return p_inst->read_multiple_channels_ex(p_channel, p_adc_val, cnt, preliminary_action);
+}
+
+int adc_read_multiple_milivolt_ex(uint32_t *p_channel, float *p_val, uint32_t cnt, void (*preliminary_action)(void))
+{
+    if (p_inst == NULL)
+    {
+        return ADC_DRV_ERROR;
+    }
+    return p_inst->read_multiple_milivolt_ex(p_channel, p_val, cnt, preliminary_action);
+}
+
+int adc_read_milivolt(uint32_t channel, float *mv)
+{
+    if (p_inst == NULL)
+    {
+        return ADC_DRV_ERROR;
+    }
+    return p_inst->read_milivolt(channel, mv);
+}
+
+int adc_read_mutiple_channels_convert_milivolt(int32_t *p_val_14bit, float *p_val_f, uint32_t count)
+{
+    if (p_inst == NULL)
+    {
+        return ADC_DRV_ERROR;
+    }
+    return p_inst->adc_convert_multiple_milivolt(p_val_14bit, p_val_f, count);
+}
+
+#endif /* ! DEF_ADC_DRV_ENABLED */

app/src/adgs1412.c

@@ -0,0 +1,71 @@
+#include "adgs1412.h"
+#include "elite_board.h"
+
+#include "nrf_delay.h"
+
+#if (DEF_ADGS1412_ENABLED)
+
+#define DAISY_CHAIN_MODE 0x2500
+
+static sw_t m_sw;
+
+static int adgs1412_reset(void)
+{
+    // the datasheet lacks clarity, RST_SW_PIN needs to be delayed after the motion signal
+    nrf_gpio_pin_clear(RST_SW_PIN);
+    nrf_delay_ms(1);
+    nrf_gpio_pin_set(RST_SW_PIN);
+    nrf_delay_ms(1);
+    return 0;
+}
+
+static int adgs1412_write(sw_t sw_mask)
+{
+    uint8_t cmd[ASGS1412_COUNT];
+    uint64_t val = m_sw.val = sw_mask.val;
+    for (int i = 1; i <= ASGS1412_COUNT; i++)
+    {
+        cmd[sizeof(cmd) - i] = val & ((0x01 << SW_PER_BYTE) - 1);
+        val                  = val >> 4;
+    }
+    spim_xfer(CS_SW_PIN, NRF_SPIM_MODE_0, (uint8_t *)cmd, sizeof(cmd), NULL, 0);
+    return 0;
+}
+
+static int adgs1412_read(sw_t *p_sw_mask)
+{
+    *p_sw_mask = m_sw;
+    return 0;
+}
+
+static int adgs1412_get_sw_count(uint32_t *p_sw_cnt)
+{
+    *p_sw_cnt = SW_TOTAL_COUNT;
+    return 0;
+}
+
+static int adgs1412_init(void)
+{
+    /* reset */
+    adgs1412_reset();
+
+    /* enter daisy chain mode */
+    uint16_t cmd = __REV16(DAISY_CHAIN_MODE);
+    spim_xfer(CS_SW_PIN, NRF_SPIM_MODE_0, (uint8_t *)&cmd, sizeof(cmd), NULL, 0);
+
+    /* sw status initialize */
+    m_sw.val = 0;
+    adgs1412_write(m_sw);
+
+    return 0;
+}
+
+const sw_drv_if_t adgs1412 = {
+    .init         = adgs1412_init,
+    .reset        = adgs1412_reset,
+    .write        = adgs1412_write,
+    .read         = adgs1412_read,
+    .get_sw_count = adgs1412_get_sw_count,
+};
+
+#endif /* ! DEF_ADGS1412_ENABLED */

app/src/ads8691.c

@@ -0,0 +1,339 @@
+#include "app_config.h"
+
+#include "ads8691.h"
+
+#if (DEF_ADS8691_ENABLED)
+
+#include "elite_board.h"
+
+#include "nrf_delay.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include <string.h>
+
+/*
+ * ADS8691
+ * Features:
+ *     -18-Bit ADC With Integrated Analog Front-End
+ *     -High Speed: 1 MSPS
+ *
+ * Spi data:
+ *      1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ *     +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *     |    Input    |  9-bit address  |          16-bit data          |
+ *     |   Commands  |                 |                               |
+ *     +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
+ *     -CMD [7bits]
+ *      0b11000xx CLEAR_HWORD
+ *      0b11001xx READ_HWORD
+ *      0b01001xx READ
+ *      0b1101000 WRITE (We used this CMD)
+ *      0b1101001 WRITE
+ *      0b1101010 WRITE
+ *      0b11011xx SET_HWORD
+ *
+ *     -Address [9bits]
+ *      00h DEVICE_ID_REG
+ *      04h RST_PWRCTL_REG
+ *      08h SDI_CTL_REG
+ *      0Ch SDO_CTL_REG
+ *      10h DATAOUT_CTL_REG
+ *      14h RANGE_SEL_REG
+ *      20h ALARM_REG
+ *      24h ALARM_H_TH_REG
+ *      28h ALARM_L_TH_REG
+ *
+ */
+
+#define ADS8691_CMD_NOP        0b0000000 // 7 bits
+#define ADS8691_CMD_CLR_HWORD  0b1100000
+#define ADS8691_CMD_READ_HWORD 0b1100100
+#define ADS8691_CMD_READ       0b0100100
+#define ADS8691_CMD_WRITE      0b1101000
+#define ADS8691_CMD_WRITE_MSB  0b1101001
+#define ADS8691_CMD_WRITE_LSB  0b1101010
+#define ADS8691_CMD_SET_HWORD  0b1101100
+
+#define DEVICE_ID_REG          0x0000
+#define RST_PWRCTL_REG         0x0004
+#define SDI_CTL_REG            0x0008
+#define DATAOUT_CTL_REG        0x0010
+#define RANGE_SEL_REG          0x0014
+#define ALARM_H_TH_REG         0x0024
+#define ALARM_L_TH_REG         0x0028
+
+#define ADS8691_SPI_MODE0      0b00
+#define ADS8691_SPI_MODE1      0b01
+#define ADS8691_SPI_MODE2      0b10
+#define ADS8691_SPI_MODE3      0b11
+
+#define INT_VREF_ENABLE        0      // Internal reference is enabled
+#define INT_VREF_DISABLE       1      // Internal reference is disabled
+#define VREF_NP_3P000          0b0000 // +/- 3.000 x Vref
+#define VREF_NP_2P500          0b0001 // +/- 2.500 x Vref
+#define VREF_NP_1P500          0b0010 // +/- 1.500 x Vref
+#define VREF_NP_1P250          0b0011 // +/- 1.250 x Vref
+#define VREF_NP_0P625          0b0100 // +/- 0.625 x Vref
+#define VREF_P_3P000           0b1000 //     3.000 x Vref
+#define VREF_P_2P500           0b1001 //     2.500 x Vref
+#define VREF_P_1P500           0b1010 //     1.500 x Vref
+#define VREF_P_1P250           0b1011 //     1.250 x Vref
+
+typedef union
+{
+    struct
+    {
+        uint16_t data;
+        uint16_t addr : 9;
+        uint16_t cmd  : 7;
+    };
+    uint32_t val;
+} opcode_t;
+
+typedef union
+{
+    struct
+    {
+        uint16_t data_val              : 3;
+        uint16_t par_en                : 1;
+        uint16_t                       : 4;
+        uint16_t range_incl            : 1;
+        uint16_t                       : 1;
+        uint16_t in_active_alarm_incl  : 2;
+        uint16_t vdd_active_alarm_incl : 2;
+        uint16_t device_addr_incl      : 1;
+        uint16_t                       : 1;
+    };
+    uint16_t val;
+} dataout_ctl_t;
+
+typedef union
+{
+    struct
+    {
+        uint16_t range_sel  : 4;
+        uint16_t            : 2;
+        uint16_t intref_dis : 1;
+        uint16_t            : 1;
+        uint16_t            : 8;
+    };
+    uint16_t val;
+} range_sel_t;
+static dataout_ctl_t m_dataout_ctl;
+static range_sel_t m_range_sel;
+static uint32_t m_channel = 0;
+static void write_cmd(uint32_t cmd, uint32_t addr, uint16_t data)
+{
+    opcode_t opcode = {
+        .cmd  = cmd,
+        .addr = addr,
+        .data = data,
+    };
+    uint32_t tx = __REV(opcode.val);
+    spim_xfer(CS_ADC_PIN, NRF_SPIM_MODE_0, (uint8_t *)&tx, sizeof(tx), NULL, 0);
+}
+
+static uint16_t read_hword(void)
+{
+    uint32_t tx = 0x00000000;
+    uint32_t rx = 0x00000000;
+    spim_xfer(CS_ADC_PIN, NRF_SPIM_MODE_0, (uint8_t *)&tx, sizeof(tx), (uint8_t *)&rx, sizeof(rx));
+    rx = __REV(rx);
+    return rx >> 16;
+}
+
+static uint32_t read_word(void)
+{
+    uint32_t tx = 0x00000000;
+    uint32_t rx = 0x00000000;
+    spim_xfer(CS_ADC_PIN, NRF_SPIM_MODE_0, (uint8_t *)&tx, sizeof(tx), (uint8_t *)&rx, sizeof(rx));
+    rx = __REV(rx);
+    return rx;
+}
+
+static int write_dev_id(uint32_t new_id)
+{
+    write_cmd(ADS8691_CMD_WRITE, DEVICE_ID_REG + 2, new_id & 0b1111);
+    write_cmd(ADS8691_CMD_READ_HWORD, DEVICE_ID_REG + 2, 0x0000);
+    return read_hword() == (new_id & 0b1111) ? 0 : -1;
+}
+
+uint32_t read_dev_id(void)
+{
+    write_cmd(ADS8691_CMD_READ_HWORD, DEVICE_ID_REG + 2, 0x0000);
+    return read_hword();
+}
+
+// static int write_dataout_ctrl(dataout_ctl_t *dataout_ctl)
+// {
+//     write_cmd(ADS8691_CMD_WRITE, DATAOUT_CTL_REG, dataout_ctl->val);
+//     return 0;
+// }
+
+static int read_dataout_ctrl(dataout_ctl_t *dataout_ctl)
+{
+    write_cmd(ADS8691_CMD_READ_HWORD, DATAOUT_CTL_REG, 0x0000);
+    dataout_ctl->val = read_hword();
+    return 0;
+}
+
+static int write_range_sel(range_sel_t *range_sel)
+{
+    write_cmd(ADS8691_CMD_WRITE, RANGE_SEL_REG, range_sel->val);
+    return 0;
+}
+
+static int read_range_sel(range_sel_t *range_sel)
+{
+    write_cmd(ADS8691_CMD_READ_HWORD, DATAOUT_CTL_REG, 0x0000);
+    range_sel->val = read_hword();
+    return 0;
+}
+
+static double adc_convert_volt(uint16_t range_sel, int32_t val_18bit)
+{
+// LSB[uV]
+#define LSB_VREF_NP_3P000 93.75
+#define LSB_VREF_NP_2P500 78.125
+#define LSB_VREF_NP_1P500 48.875
+#define LSB_VREF_NP_1P250 39.06
+#define LSB_VREF_NP_0P625 19.53
+#define LSB_VREF_P_3P000  46.875
+#define LSB_VREF_P_2P500  39.06
+#define LSB_VREF_P_1P500  23.43
+#define LSB_VREF_P_1P250  19.53
+
+// FULL-SCALE RANGE[V]
+#define FSR_VREF_NP_3P000 24.576
+#define FSR_VREF_NP_2P500 20.48
+#define FSR_VREF_NP_1P500 12.288
+#define FSR_VREF_NP_1P250 10.24
+#define FSR_VREF_NP_0P625 5.12
+#define FSR_VREF_P_3P000  12.288
+#define FSR_VREF_P_2P500  10.24
+#define FSR_VREF_P_1P500  6.144
+#define FSR_VREF_P_1P250  5.12
+
+    double volt = 0;
+
+    if (range_sel == VREF_NP_3P000)
+        volt = (double)val_18bit * LSB_VREF_NP_3P000 / 1000000 - FSR_VREF_NP_3P000 / 2;
+    else if (range_sel == VREF_NP_2P500)
+        volt = (double)val_18bit * LSB_VREF_NP_2P500 / 1000000 - FSR_VREF_NP_2P500 / 2;
+    else if (range_sel == VREF_NP_1P500)
+        volt = (double)val_18bit * LSB_VREF_NP_1P500 / 1000000 - FSR_VREF_NP_1P500 / 2;
+    else if (range_sel == VREF_NP_1P250)
+        volt = (double)val_18bit * LSB_VREF_NP_1P250 / 1000000 - FSR_VREF_NP_1P250 / 2;
+    else if (range_sel == VREF_NP_0P625)
+        volt = (double)val_18bit * LSB_VREF_NP_0P625 / 1000000 - FSR_VREF_NP_0P625 / 2;
+    else if (range_sel == VREF_P_3P000)
+        volt = (double)val_18bit * LSB_VREF_P_3P000 / 1000000 - FSR_VREF_P_3P000 / 2;
+    else if (range_sel == VREF_P_2P500)
+        volt = (double)val_18bit * LSB_VREF_P_2P500 / 1000000 - FSR_VREF_P_2P500 / 2;
+    else if (range_sel == VREF_P_1P500)
+        volt = (double)val_18bit * LSB_VREF_P_1P500 / 1000000 - FSR_VREF_P_1P500 / 2;
+    else if (range_sel == VREF_P_1P250)
+        volt = (double)val_18bit * LSB_VREF_P_1P250 / 1000000 - FSR_VREF_P_1P250 / 2;
+
+    return volt;
+}
+
+static int ads8691_read(uint32_t channel, int32_t *adc_val)
+{
+    if (m_channel != channel)
+    {
+        m_channel = channel;
+        nrf_gpio_pin_write(ADCA0_PIN, m_channel & (0x01 << 0));
+        nrf_gpio_pin_write(ADCA1_PIN, m_channel & (0x01 << 1));
+        nrf_gpio_pin_write(ADCA2_PIN, m_channel & (0x01 << 2));
+        nrf_delay_us(100);
+    }
+
+    read_word();
+
+    uint32_t val = read_word();
+    *adc_val     = val >> 14;
+
+    return 0;
+}
+
+static int ads8691_read_milivolt(uint32_t channel, float *mv)
+{
+    int32_t val = 0;
+    ads8691_read(channel, &val);
+    *mv = adc_convert_volt(m_range_sel.range_sel, val) * 1000.0;
+    return 0;
+}
+
+static int ads8691_gain(adc_gain_t gain)
+{
+    switch (gain)
+    {
+        case GAIN_3P000:
+            m_range_sel.range_sel = VREF_NP_3P000;
+            break;
+        case GAIN_2P500:
+            m_range_sel.range_sel = VREF_NP_2P500;
+            break;
+        case GAIN_1P500:
+            m_range_sel.range_sel = VREF_NP_1P500;
+            break;
+        case GAIN_1P250:
+            m_range_sel.range_sel = VREF_NP_1P250;
+            break;
+        case GAIN_0P625:
+            m_range_sel.range_sel = VREF_NP_0P625;
+            break;
+        default:
+            break;
+    }
+    write_range_sel(&m_range_sel);
+    return 0;
+}
+
+static int ads8691_reset(void)
+{
+    return 0;
+}
+
+static int ads8691_init(void)
+{
+    int ret = -1;
+    for (int i = 0; i < 3; i++)
+    {
+        if (read_dev_id() == 0b0101)
+        {
+            ret = 0;
+            break;
+        }
+        if (write_dev_id(0b0101) == 0)
+        {
+            ret = 0;
+            break;
+        }
+    }
+
+    if (ret == 0)
+    {
+        read_dataout_ctrl(&m_dataout_ctl);
+        read_range_sel(&m_range_sel);
+        nrf_gpio_pin_write(ADCA0_PIN, m_channel & (0x01 << 0));
+        nrf_gpio_pin_write(ADCA1_PIN, m_channel & (0x01 << 1));
+        nrf_gpio_pin_write(ADCA2_PIN, m_channel & (0x01 << 2));
+    }
+
+    return ret;
+}
+
+const adc_drv_if_t ads8691 = {
+    .init          = ads8691_init,
+    .reset         = ads8691_reset,
+    .read          = ads8691_read,
+    .gain          = ads8691_gain,
+    .read_milivolt = ads8691_read_milivolt,
+};
+
+#endif /* ! DEF_ADS8691_ENABLED */

app/src/apa102_2020.c

@@ -0,0 +1,74 @@
+#include "app_config.h"
+
+#if (DEF_APA102_2020_ENABLED)
+#include "apa102_2020.h"
+
+#include "elite_board.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+typedef struct
+{
+    uint8_t brightness : 5;
+    uint8_t preamble   : 3;
+    struct led_color color;
+} led_t;
+
+static led_t *p_led       = NULL;
+static uint32_t led_count = 0;
+
+const led_t led_default = {
+    .brightness = 0b00000,
+    .preamble   = 0b111,
+    .color      = {
+                   .B = 0,
+                   .G = 0,
+                   .R = 0},
+};
+
+static void apa102_led_write(uint8_t *pucData, uint32_t ulSize)
+{
+    spi1_write(pucData, ulSize);
+}
+
+int32_t apa102_led_set(uint32_t idx, struct led_color color, uint8_t brightness)
+{
+    uint32_t start_frame  = 0x00000000;
+    uint32_t end_frame    = 0xFFFFFFFF;
+    p_led[idx].color      = color;
+    p_led[idx].brightness = brightness;
+
+    apa102_led_write((void *)&start_frame, sizeof(start_frame));
+    apa102_led_write((void *)p_led, led_count * sizeof(*p_led));
+    apa102_led_write((void *)&end_frame, sizeof(end_frame));
+
+    return 0;
+}
+
+int32_t apa102_init(uint32_t cnt)
+{
+    uint32_t start_frame = 0x00000000;
+    uint32_t end_frame   = 0xFFFFFFFF;
+
+    led_count = cnt;
+    p_led     = pvPortMalloc(led_count * sizeof(*p_led));
+
+    for (int i = 0; i < led_count; i++)
+    {
+        p_led[i] = led_default;
+    }
+
+    apa102_led_write((void *)&start_frame, sizeof(start_frame));
+    apa102_led_write((void *)p_led, led_count * sizeof(*p_led));
+    apa102_led_write((void *)&end_frame, sizeof(end_frame));
+
+    return 0;
+}
+
+const led_drv_if_t apa102_drv = {
+    .init = apa102_init,
+    .set  = apa102_led_set,
+};
+
+#endif /* ! DEF_APA102_2020_ENABLED */

app/src/btn.c

@@ -0,0 +1,200 @@
+#include "nrf_gpio.h"
+#include "nrf_gpiote.h"
+#include "nrfx_gpiote.h"
+
+#include "nrf_log.h"
+
+#include "elite_board.h"
+#include "led_drv.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+#if (DEF_BTN_ENABLED)
+
+#define TIME_DEBOUNCE       pdMS_TO_TICKS(25)
+#define TIME_CLICK_INTERVAL pdMS_TO_TICKS(200)
+#define TIME_PRESS_LONG     pdMS_TO_TICKS(1500)
+
+//--------------------------------------------------------------------
+static TaskHandle_t btn_task_handle = NULL;
+
+static void nrfx_gpiote_evt_handler(nrfx_gpiote_pin_t xPin, nrf_gpiote_polarity_t ePolarity)
+{
+    uint32_t pins = nrf_gpio_pin_read(SHUT_DOWN_PIN);
+    if (__get_IPSR() != 0)
+    {
+        BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+        xTaskNotifyFromISR(btn_task_handle, pins, eSetValueWithOverwrite, &xHigherPriorityTaskWoken);
+        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+    }
+    else
+    {
+        xTaskNotify(btn_task_handle, xPin, eSetValueWithOverwrite);
+    }
+}
+
+static bool wait_pressed(TickType_t xTimeout)
+{
+    uint32_t pins;
+    do {
+        if (!xTaskNotifyWait(0, 0, &pins, xTimeout))
+        {
+            return false;
+        }
+        do {
+        } while (xTaskNotifyWait(0, 0, &pins, TIME_DEBOUNCE));
+    } while (pins);
+    return true;
+}
+
+static bool wait_released(TickType_t xTimeout)
+{
+    uint32_t pins;
+    do {
+        if (!xTaskNotifyWait(0, 0, &pins, xTimeout))
+        {
+            return false;
+        }
+        do {
+        } while (xTaskNotifyWait(0, 0, &pins, TIME_DEBOUNCE));
+    } while (!pins);
+    return true;
+}
+
+//--------------------------------------------------------------------
+typedef enum
+{
+    BTN_EVENT_SHORTx1,
+    BTN_EVENT_SHORTx2,
+    BTN_EVENT_SHORTx3,
+    BTN_EVENT_LONG,
+} BtnEvent_t;
+
+static BtnEvent_t btn_event(void)
+{
+    while (1)
+    {
+        // drop previous/undefined clicks
+        while (wait_pressed(TIME_CLICK_INTERVAL))
+        {
+            wait_released(portMAX_DELAY);
+        }
+        // wait for clicks
+        wait_pressed(portMAX_DELAY);
+        if (!wait_released(TIME_PRESS_LONG))
+        {
+            return BTN_EVENT_LONG;
+        }
+        for (BtnEvent_t e = BTN_EVENT_SHORTx1; e < BTN_EVENT_LONG; e++)
+        {
+            if (!wait_pressed(TIME_CLICK_INTERVAL))
+            {
+                return e;
+            }
+            if (!wait_released(TIME_PRESS_LONG))
+            {
+                break;
+            }
+        }
+    }
+}
+
+static void btn_event_shortx1_cb(void)
+{
+    NRF_LOG_INFO("BTN_EVENT_SHORTx1");
+#if (DEF_APA102_2020_ENABLED)
+    const struct led_color color[6] = { LED_RED, LED_ORANGE, LED_YELLOW, LED_GREEN, LED_BLUE, LED_PURPLE };
+#elif (DEF_RGB_ENABLED)
+    const struct led_color color[6] = { LED_RED, LED_YELLOW, LED_GREEN, LED_CYAN, LED_BLUE, LED_PURPLE };
+#endif
+    static int idx = 0;
+    led_set(color[idx++ % COUNTOF(color)]);
+}
+
+static void btn_event_shortx2_cb(void)
+{
+    NRF_LOG_INFO("BTN_EVENT_SHORTx2");
+    for (int i = 0; i < 2; i++)
+    {
+        led_set(LED_OFF);
+        vTaskDelay(pdMS_TO_TICKS(250));
+        led_set(LED_BLUE);
+        vTaskDelay(pdMS_TO_TICKS(250));
+    }
+    led_set(LED_IDLE_DISCONNECTED);
+}
+
+static void btn_event_shortx3_cb(void)
+{
+    NRF_LOG_INFO("BTN_EVENT_SHORTx3");
+    for (int i = 0; i < 2; i++)
+    {
+        led_set(LED_OFF);
+        vTaskDelay(pdMS_TO_TICKS(250));
+        led_set(LED_CYAN);
+        vTaskDelay(pdMS_TO_TICKS(250));
+        led_set(LED_IDLE_DISCONNECTED);
+    }
+    led_set(LED_IDLE_DISCONNECTED);
+}
+
+static void btn_event_long(void)
+{
+    NRF_LOG_INFO("BTN_EVENT_LONG");
+#if (DEF_APA102_2020_ENABLED)
+    led_set(LED_ORANGE);
+#elif (DEF_RGB_ENABLED)
+    led_set(LED_YELLOW);
+#endif
+    if (!wait_released(TIME_PRESS_LONG))
+    {
+        led_set(LED_OFF);
+        elite_board_power_off();
+    }
+    led_set(LED_IDLE_DISCONNECTED);
+}
+
+static void btn_task(void *pvArg)
+{
+    for (;;)
+    {
+        switch (btn_event())
+        {
+            case BTN_EVENT_SHORTx1:
+                btn_event_shortx1_cb();
+                break;
+            case BTN_EVENT_SHORTx2:
+                btn_event_shortx2_cb();
+                break;
+            case BTN_EVENT_SHORTx3:
+                btn_event_shortx3_cb();
+                break;
+            case BTN_EVENT_LONG:
+                btn_event_long();
+                break;
+        }
+    }
+}
+
+void btn_init(void)
+{
+    nrfx_gpiote_in_config_t config = {
+        .hi_accuracy     = 1,
+        .is_watcher      = 0,
+        .pull            = NRF_GPIO_PIN_NOPULL,
+        .sense           = NRF_GPIOTE_POLARITY_TOGGLE,
+        .skip_gpio_setup = 0
+    };
+
+    nrfx_gpiote_init();
+
+    nrfx_gpiote_in_init(SHUT_DOWN_PIN, &config, nrfx_gpiote_evt_handler);
+
+    nrfx_gpiote_in_event_enable(SHUT_DOWN_PIN, true);
+
+    xTaskCreate(btn_task, "btn", 256, NULL, 3, &btn_task_handle);
+}
+
+#endif /* ! DEF_BTN_ENABLED */

app/src/builtin_saadc.c

@@ -0,0 +1,355 @@
+#include "builtin_saadc.h"
+#include "nrf_log.h"
+#include "nrf_saadc.h"
+
+#define VERF (0.60)
+
+static uint32_t m_gain = NRF_SAADC_GAIN1_6;
+static int read(uint32_t channel, int32_t *adc_val);
+static int init(void)
+{
+    /* enable ssadc */
+    NRF_SAADC->ENABLE = 1;
+    /* stop ssadc */
+    NRF_SAADC->EVENTS_STOPPED = 0;
+    NRF_SAADC->TASKS_STOP     = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_STOPPED == 0);
+    /* config resolution */
+    NRF_SAADC->RESOLUTION = SAADC_RESOLUTION_VAL_14bit;
+    /* auto calibration ssadc */
+    NRF_SAADC->EVENTS_CALIBRATEDONE  = 0;
+    NRF_SAADC->TASKS_CALIBRATEOFFSET = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_CALIBRATEDONE == 0);
+    /* disable ssadc */
+    NRF_SAADC->ENABLE = 0;
+    /* stop ssadc */
+    NRF_SAADC->EVENTS_STOPPED = 0;
+    NRF_SAADC->TASKS_STOP     = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_STOPPED == 0);
+    return 0;
+}
+
+static int reset(void)
+{
+    // Do nothing...
+    return 0;
+}
+
+static float adc_convert_milivolt(uint16_t range_sel, int32_t val_14bit, bool is_diff)
+{
+    float volt;
+    float gain = 1.0 / 6.0;
+    float vref;
+    uint32_t m = is_diff ? 1 : 0;
+
+    switch (range_sel)
+    {
+        case NRF_SAADC_GAIN1_6:
+            gain = 1.0 / 6.0;
+            vref = VERF;
+            break;
+        case NRF_SAADC_GAIN1_5:
+            gain = 1.0 / 5.0;
+            vref = VERF;
+            break;
+        case NRF_SAADC_GAIN1_4:
+            gain = 1.0 / 4.0;
+            vref = VERF;
+            break;
+        case NRF_SAADC_GAIN1_3:
+            gain = 1.0 / 3.0;
+            vref = VERF;
+            break;
+        case NRF_SAADC_GAIN1_2:
+            gain = 1.0 / 2.0;
+            vref = VERF;
+            break;
+        case NRF_SAADC_GAIN1:
+            gain = 1.0 / 1.0;
+            vref = VERF;
+            break;
+        case NRF_SAADC_GAIN2:
+            gain = 2.0;
+            vref = VERF;
+            break;
+        case NRF_SAADC_GAIN4:
+            gain = 4.0;
+            vref = VERF;
+            break;
+    }
+
+    // differential V(P) = RESULT * (REFERENCE / GAIN/) / 2(RESOLUTION - 1) - V(N)
+    // single end   V(P) = RESULT * (REFERENCE / GAIN/) / 2(RESOLUTION - 0)
+
+    volt = ((float)val_14bit * 1000.0) * (vref / gain) / (0x01 << (14 - m));
+
+    return volt;
+}
+
+static int read(uint32_t channel, int32_t *adc_val)
+{
+    /* disable ssadc */
+    NRF_SAADC->ENABLE = 0;
+    /* stop ssadc */
+    NRF_SAADC->EVENTS_STOPPED = 0;
+    NRF_SAADC->TASKS_STOP     = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_STOPPED == 0);
+    /*
+        ref: p.381, nrf52840_PS_v1.1.pdf
+        Note: Oversampling should only be used when a single input channel is enabled, as averaging is
+        performed over all enabled channels.
+    */
+    NRF_SAADC->OVERSAMPLE = NRF_SAADC_OVERSAMPLE_DISABLED;
+    /* config analog input */
+    NRF_SAADC->CH[0].PSELP = NRF_SAADC_INPUT_AIN0 + channel;
+    NRF_SAADC->CH[0].PSELN = NRF_SAADC_INPUT_DISABLED;
+    NRF_SAADC->CH[0].CONFIG =
+        (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESP_Pos) |
+        (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESN_Pos) |
+        (m_gain << SAADC_CH_CONFIG_GAIN_Pos) |
+        (NRF_SAADC_REFERENCE_INTERNAL << SAADC_CH_CONFIG_REFSEL_Pos) |
+        (NRF_SAADC_ACQTIME_40US << SAADC_CH_CONFIG_TACQ_Pos) |
+        (NRF_SAADC_MODE_SINGLE_ENDED << SAADC_CH_CONFIG_MODE_Pos) |
+        (NRF_SAADC_BURST_DISABLED << SAADC_CH_CONFIG_BURST_Pos);
+    /* enable ssadc */
+    NRF_SAADC->ENABLE = 1;
+    /* read single channel */
+    uint16_t val             = 0;
+    NRF_SAADC->RESULT.PTR    = (uint32_t)&val;
+    NRF_SAADC->RESULT.MAXCNT = 1;
+    NRF_SAADC->EVENTS_END    = 0;
+    NRF_SAADC->TASKS_SAMPLE  = 1;
+    NRF_SAADC->TASKS_START   = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_END == 0);
+    /* disable ssadc */
+    NRF_SAADC->ENABLE = 0;
+    /* stop ssadc */
+    NRF_SAADC->TASKS_STOP = 1;
+    /* copy value */
+    *adc_val = val;
+    adc_convert_milivolt(m_gain, *adc_val, 0);
+    return 0;
+}
+
+static int read_channels(uint32_t *p_channel, int32_t *adc_val, uint32_t count)
+{
+    /* disable ssadc */
+    NRF_SAADC->ENABLE = 0;
+    /* stop ssadc */
+    NRF_SAADC->EVENTS_STOPPED = 0;
+    NRF_SAADC->TASKS_STOP     = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_STOPPED == 0);
+    /*
+        ref: p.381, nrf52840_PS_v1.1.pdf
+        Note: Oversampling should only be used when a single input channel is enabled, as averaging is
+        performed over all enabled channels.
+    */
+    NRF_SAADC->OVERSAMPLE = NRF_SAADC_OVERSAMPLE_DISABLED;
+    /* config analog inputs */
+    for (uint32_t i = 0; i < COUNTOF(NRF_SAADC->CH); i++)
+    {
+        if (i < count)
+        {
+            NRF_SAADC->CH[i].PSELP = NRF_SAADC_INPUT_AIN0 + p_channel[i];
+            NRF_SAADC->CH[i].PSELN = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].CONFIG =
+                (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESP_Pos) |
+                (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESN_Pos) |
+                (m_gain << SAADC_CH_CONFIG_GAIN_Pos) |
+                (NRF_SAADC_REFERENCE_INTERNAL << SAADC_CH_CONFIG_REFSEL_Pos) |
+                (NRF_SAADC_ACQTIME_40US << SAADC_CH_CONFIG_TACQ_Pos) |
+                (NRF_SAADC_MODE_SINGLE_ENDED << SAADC_CH_CONFIG_MODE_Pos) |
+                (NRF_SAADC_BURST_DISABLED << SAADC_CH_CONFIG_BURST_Pos);
+        }
+        else
+        {
+            NRF_SAADC->CH[i].PSELP  = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].PSELN  = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].CONFIG = 0;
+        }
+    }
+    /* enable ssadc */
+    NRF_SAADC->ENABLE = 1;
+    /* start convert */
+    uint16_t val[16]         = { 0 };
+    NRF_SAADC->RESULT.PTR    = (uint32_t)&val[0];
+    NRF_SAADC->RESULT.MAXCNT = count;
+    NRF_SAADC->EVENTS_END    = 0;
+    NRF_SAADC->TASKS_SAMPLE  = 1;
+    NRF_SAADC->TASKS_START   = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_END == 0);
+    /* disable ssadc */
+    NRF_SAADC->ENABLE = 0;
+    /* stop ssadc */
+    NRF_SAADC->TASKS_STOP = 1;
+    /* copy values */
+    for (uint32_t i = 0; i < count; i++)
+    {
+        adc_val[i] = val[i];
+    }
+    return 0;
+}
+
+static int read_channels_ex(uint32_t *p_channel, int32_t *adc_val, uint32_t count, void (*preliminary_callback)(void))
+{
+    /* disable ssadc */
+    NRF_SAADC->ENABLE = 0;
+    /* stop ssadc */
+    NRF_SAADC->EVENTS_STOPPED = 0;
+    NRF_SAADC->TASKS_STOP     = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_STOPPED == 0);
+    /*
+        ref: p.381, nrf52840_PS_v1.1.pdf
+        Note: Oversampling should only be used when a single input channel is enabled, as averaging is
+        performed over all enabled channels.
+    */
+    NRF_SAADC->OVERSAMPLE = NRF_SAADC_OVERSAMPLE_DISABLED;
+    /* config analog inputs */
+    for (uint32_t i = 0; i < COUNTOF(NRF_SAADC->CH); i++)
+    {
+        if (i < count)
+        {
+            NRF_SAADC->CH[i].PSELP = NRF_SAADC_INPUT_AIN0 + p_channel[i];
+            NRF_SAADC->CH[i].PSELN = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].CONFIG =
+                (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESP_Pos) |
+                (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESN_Pos) |
+                (m_gain << SAADC_CH_CONFIG_GAIN_Pos) |
+                (NRF_SAADC_REFERENCE_INTERNAL << SAADC_CH_CONFIG_REFSEL_Pos) |
+                (NRF_SAADC_ACQTIME_40US << SAADC_CH_CONFIG_TACQ_Pos) |
+                (NRF_SAADC_MODE_SINGLE_ENDED << SAADC_CH_CONFIG_MODE_Pos) |
+                (NRF_SAADC_BURST_DISABLED << SAADC_CH_CONFIG_BURST_Pos);
+        }
+        else
+        {
+            NRF_SAADC->CH[i].PSELP  = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].PSELN  = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].CONFIG = 0;
+        }
+    }
+    /* enable ssadc */
+    NRF_SAADC->ENABLE = 1;
+    /* disable irq */
+    __disable_irq();
+    /* do preliminary job */
+    if (preliminary_callback)
+    {
+        preliminary_callback();
+    }
+    /* start convert */
+    int16_t val[COUNTOF(NRF_SAADC->CH)] = { 0 };
+    NRF_SAADC->RESULT.PTR               = (uint32_t)&val[0];
+    NRF_SAADC->RESULT.MAXCNT            = count;
+    NRF_SAADC->EVENTS_END               = 0;
+    NRF_SAADC->TASKS_SAMPLE             = 1;
+    NRF_SAADC->TASKS_START              = 1;
+    /* enabl irq */
+    __enable_irq();
+    do {
+    } while (NRF_SAADC->EVENTS_END == 0);
+    /* disable ssadc */
+    NRF_SAADC->ENABLE = 0;
+    /* stop ssadc */
+    NRF_SAADC->TASKS_STOP = 1;
+    /* copy values */
+    for (uint32_t i = 0; i < count; i++)
+    {
+        adc_val[i] = val[i];
+    }
+    return 0;
+}
+
+static int gain(adc_gain_t gain)
+{
+    int ret;
+    switch (gain)
+    {
+        case GAIN_1P000:
+            m_gain = NRF_SAADC_GAIN1_6;
+            ret    = 0;
+            break;
+        case GAIN_1P200:
+            m_gain = NRF_SAADC_GAIN1_5;
+            ret    = 0;
+            break;
+        case GAIN_1P500:
+            m_gain = NRF_SAADC_GAIN1_4;
+            ret    = 0;
+            break;
+        case GAIN_2P000:
+            m_gain = NRF_SAADC_GAIN1_3;
+            ret    = 0;
+            break;
+        case GAIN_3P000:
+            m_gain = NRF_SAADC_GAIN1_2;
+            ret    = 0;
+            break;
+        case GAIN_6P000:
+            m_gain = NRF_SAADC_GAIN1;
+            ret    = 0;
+            break;
+        case GAIN_12P000:
+            m_gain = NRF_SAADC_GAIN2;
+            ret    = 0;
+            break;
+        case GAIN_24P000:
+            m_gain = NRF_SAADC_GAIN4;
+            ret    = 0;
+            break;
+        default:
+            m_gain = SAADC_CH_CONFIG_GAIN_Gain1_6;
+            ret    = -1;
+            break;
+    }
+    return ret;
+}
+
+static int read_multiple_milivolt_ex(uint32_t *p_channels, float *p_val, uint32_t count, void(*preliminary_action))
+{
+    int32_t int_val[16];
+    double f_val[16];
+
+    if (read_channels_ex(p_channels, int_val, count, preliminary_action) != 0)
+    {
+        return -1;
+    }
+
+    for (int i = 0; i < count; i++)
+    {
+        p_val[i] = adc_convert_milivolt(m_gain, int_val[i], false);
+    }
+
+    return 0;
+}
+
+static int adc_convert_multiple_milivolt(int32_t *p_val_14bit, float *p_val_f, uint32_t count)
+{
+    int32_t int_val[16];
+
+    for (int i = 0; i < count; i++)
+    {
+        int_val[i] = p_val_14bit[i]; // copy values
+        p_val_f[i] = adc_convert_milivolt(m_gain, int_val[i], false);
+    }
+
+    return 0;
+}
+
+const adc_drv_if_t builtin_saadc = {
+    .init                          = init,
+    .reset                         = reset,
+    .read                          = read,
+    .gain                          = gain,
+    .read_multiple_channels        = read_channels,
+    .read_multiple_channels_ex     = read_channels_ex,
+    .read_multiple_milivolt_ex     = read_multiple_milivolt_ex,
+    .adc_convert_multiple_milivolt = adc_convert_multiple_milivolt,
+};

app/src/dac_drv.c

@@ -0,0 +1,48 @@
+#include "dac_drv.h"
+
+#if (DEF_MAX5136_ENABLED)
+extern dac_drv_if_t max5316_drv;
+static const dac_drv_if_t *p_inst = &max5316_drv;
+#else
+static dac_drv_if_t *p_inst = NULL;
+#endif /* ! DEF_MAX5136_ENABLED */
+
+#if (DEF_DAC_DRV_ENABLED)
+
+int dac_init(void)
+{
+    if (p_inst == NULL)
+    {
+        return DAC_DRV_ERROR;
+    }
+    return p_inst->init();
+}
+
+int dac_write(uint32_t channel_mask, int32_t dac_val)
+{
+    if (p_inst == NULL)
+    {
+        return DAC_DRV_ERROR;
+    }
+    return p_inst->write_mode(channel_mask, dac_val);
+}
+
+int dac_load(uint32_t channel_mask)
+{
+    if (p_inst == NULL)
+    {
+        return DAC_DRV_ERROR;
+    }
+    return p_inst->ldac_mode(channel_mask);
+}
+
+int dac_write_through(uint32_t channel_mask, int32_t dac_val)
+{
+    if (p_inst == NULL)
+    {
+        return DAC_DRV_ERROR;
+    }
+    return p_inst->write_through_mode(channel_mask, dac_val);
+}
+
+#endif /* ! DEF_DAC_DRV_ENABLED */

app/src/elite.c

@@ -0,0 +1,142 @@
+#include "app_config.h"
+
+#include "elite.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
+#include "elite_dev_v1_0.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+#include "elite_edc_v2_0.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+#include "elite_pel_v2_0.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V3_0)
+#include "elite_pel_v3_0.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+#include "elite_cpg_v1_1.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_MMM_V1_0)
+#include "elite_mmm_v1_0.h"
+#else
+#error "Unknown DEF_ELITE_MODEL"
+#endif
+
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+#include "nrf_log_default_backends.h"
+
+#include "FreeRTOS.h"
+#include "message_buffer.h"
+#include "stream_buffer.h"
+#include "task.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+static const elite_instance_t *p_instance = NULL;
+
+MessageBufferHandle_t instr_msg = NULL;
+
+static void decode_ris_ins(uint8_t *ins, uint16_t size)
+{
+    uint8_t oper = ins[2];
+    if (p_instance->ris_func[oper])
+    {
+        p_instance->ris_func[oper](ins, size);
+    }
+    else
+    {
+        NRF_LOG_INFO("unknown ris instruction");
+    }
+}
+
+static void decode_vis_ins(uint8_t *ins, uint16_t size)
+{
+    uint8_t oper = ins[1] & 0xF0; // this is don't care in RISASD;//
+    if (p_instance->vis_func[oper])
+    {
+        p_instance->vis_func[oper](ins, size);
+    }
+    else
+    {
+        NRF_LOG_INFO("unknown vis instruction");
+    }
+}
+
+static void decode_cis_ins(uint8_t *ins, uint16_t size)
+{
+    uint8_t oper = ins[1] & 0xF0;
+    if (p_instance->cis_func[oper])
+    {
+        p_instance->cis_func[oper](ins, size);
+    }
+    else
+    {
+        NRF_LOG_INFO("unknown vis instruction");
+    }
+}
+
+// define BT instruction
+#define INS_TYPE_RIS 0x30
+#define INS_TYPE_VIS 0xC0
+#define INS_TYPE_CIS 0x70
+
+static void elite_instr_task(void *p_arg)
+{
+    static size_t instr_size = 0;
+    static uint8_t instr[256];
+
+    for (;;)
+    {
+        instr_size = xMessageBufferReceive(instr_msg, instr, sizeof(instr), portMAX_DELAY);
+
+        if (instr_size)
+        {
+            uint16_t ins_type = instr[0] & 0b11110000;
+            uint16_t chip_id  = instr[0] & 0b00001111;
+            switch (ins_type)
+            {
+                case INS_TYPE_RIS:
+                    decode_ris_ins(instr, instr_size);
+                    break;
+                case INS_TYPE_VIS:
+                    decode_vis_ins(instr, instr_size);
+                    break;
+                case INS_TYPE_CIS:
+                    decode_cis_ins(instr, instr_size);
+                    break;
+                default:
+                    break;
+            }
+        }
+    }
+}
+
+void elite_init(void)
+{
+#if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
+    p_instance = dev_init();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+    edc.init();
+    p_instance = edc.p_elite_instance;
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+    p_instance = pel_init();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V3_0)
+    p_instance = pel_init();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+    p_instance = cpg_init();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_MMM_V1_0)
+    p_instance = mmm_init();
+#else
+#error "Unknown DEF_ELITE_MODEL"
+#endif
+
+    instr_msg = xMessageBufferCreate(1024);
+    xTaskCreate(elite_instr_task, "elite_instr", 2048, NULL, 3, NULL);
+}
+
+void elite_instr_send(void *p, size_t size)
+{
+    /* reply the instruction */
+    extern ret_code_t le_data_update(uint8_t *p_value, uint16_t len);
+    le_data_update(p, size);
+
+    xMessageBufferSend(instr_msg, p, size, portMAX_DELAY);
+}

app/src/elite_board.c

@@ -0,0 +1,81 @@
+#include "elite_board.h"
+
+void elite_board_init(void)
+{
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+    edc20_io_init();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+    pel20_io_init();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V3_0)
+    pel30_io_init();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+    cpg11_io_init();
+#endif
+}
+
+void elite_board_demo(void)
+{
+#if (DEF_ELITE_DEMO_WO_SOFTDEVICE || DEF_ELITE_DEMO_W_SOFTDEVICE)
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+    extern void pel_pulse_gen_demo(void);
+    pel_pulse_gen_demo();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V3_0)
+    extern void pel_pulse_gen_demo(void);
+    pel_pulse_gen_demo();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+    cpg_pulse_default_demo_ext();
+#endif
+
+#endif
+}
+
+void elite_board_power_off(void)
+{
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+    edc20_io_power_off();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V3_0)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+#endif
+}
+
+void elite_drv_init(void)
+{
+    btn_init();
+    led_init();
+    led_set(LED_IDLE_DISCONNECTED);
+    sw_init();
+    adc_init();
+    dac_init();
+    fs_init();
+    usbd_init();
+    uart_init();
+
+#if (DEF_FS_ENABLED && DEF_FS_RTT_DIR)
+    if (1)
+    {
+        static file_t hFile;
+        char write[64];
+        char read[64];
+
+        memset(write, 0x00, sizeof(write));
+        snprintf(write, sizeof(write), "Hellow %s Build: %s %s", ELITE_DEVICE_NAME, __TIME__, __DATE__);
+
+        fs_file_open(&hFile, "default.txt", FS_O_CREAT | FS_O_RDWR | FS_O_TRUNC);
+        fs_file_write(&hFile, write, strlen(write));
+        fs_file_close(&hFile);
+
+        memset(read, 0x00, sizeof(read));
+
+        fs_file_open(&hFile, "default.txt", FS_O_RDONLY);
+        fs_file_read(&hFile, read, sizeof(read));
+        fs_file_close(&hFile);
+        NRF_LOG_INFO("%s", read);
+
+        fs_dir("/");
+    }
+#endif /* ! DEF_FS_ENABLE */
+}

app/src/elite_cpg_v1_1_io.c

@@ -0,0 +1,574 @@
+#include "elite_board.h"
+
+#include "nrf_gpio.h"
+#include "nrf_gpiote.h"
+#include "nrf_log.h"
+#include "nrf_spim.h"
+#include "nrf_timer.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+#pragma GCC optimize("O2")
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+
+typedef struct
+{
+    const uint32_t gpiote_idx[4];
+    NRF_TIMER_Type *TMR_A;
+    NRF_TIMER_Type *TMR_B;
+    uint32_t TMR_A_IRQn;
+    uint32_t TMR_B_IRQn;
+    pulse_gen_t *p_pulse_gen;
+    struct
+    {
+        pulse_gen_t *p_pulse_gen;
+        uint32_t len;
+        uint32_t select;
+    } private;
+} pulse_gen_hw_t;
+
+pulse_gen_hw_t pulse_gen_hw[] = {
+    { .gpiote_idx  = { 0, 1, 2, 3 },
+     .TMR_A       = NRF_TIMER1,
+     .TMR_B       = NRF_TIMER3,
+     .TMR_A_IRQn  = TIMER1_IRQn,
+     .TMR_B_IRQn  = TIMER3_IRQn,
+     .p_pulse_gen = NULL,
+     .private     = { NULL, 0, 0 } },
+    { .gpiote_idx  = { 4, 5, 6, 7 },
+     .TMR_A       = NRF_TIMER2,
+     .TMR_B       = NRF_TIMER4,
+     .TMR_A_IRQn  = TIMER2_IRQn,
+     .TMR_B_IRQn  = TIMER4_IRQn,
+     .p_pulse_gen = NULL,
+     .private     = { NULL, 0, 0 } },
+};
+
+__STATIC_INLINE void config_tmrB(uint32_t hw_idx, pulse_gen_t *p_pulse_gen)
+{
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[2], p_pulse_gen->VBxH, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[3], p_pulse_gen->VAxL, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+
+    pulse_gen_hw[hw_idx].TMR_B->CC[0] = 1 + p_pulse_gen->point_us[3] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[1] = pulse_gen_hw[hw_idx].TMR_B->CC[0] + p_pulse_gen->point_us[4] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[2] = pulse_gen_hw[hw_idx].TMR_B->CC[1] + p_pulse_gen->point_us[5] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[3] = pulse_gen_hw[hw_idx].TMR_B->CC[2] + p_pulse_gen->point_us[6] * 16;
+}
+
+__STATIC_INLINE void cpg11_tmrB_cb(uint32_t hw_idx)
+{
+    if (pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[3])
+    {
+        uint32_t sel = pulse_gen_hw[hw_idx].private.select;
+
+        pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[3] = 0;
+
+        if (pulse_gen_hw[hw_idx].private.p_pulse_gen[sel].pulse_cnt > 0)
+        {
+            pulse_gen_hw[hw_idx].private.p_pulse_gen[sel].pulse_cnt--;
+        }
+
+        for (uint32_t i = 0; i < pulse_gen_hw[hw_idx].private.len; i++)
+        {
+            sel = (sel + 1) % pulse_gen_hw[hw_idx].private.len;
+            if (pulse_gen_hw[hw_idx].private.p_pulse_gen[sel].pulse_cnt > 0)
+            {
+                pulse_gen_hw[hw_idx].private.select = sel;
+                config_tmrB(hw_idx, &pulse_gen_hw[hw_idx].private.p_pulse_gen[sel]);
+                return;
+            }
+        }
+
+        pulse_gen_hw[hw_idx].TMR_A->TASKS_STOP = 1;
+        pulse_gen_hw[hw_idx].TMR_B->TASKS_STOP = 1;
+    }
+}
+
+__STATIC_INLINE void config_tmrA(uint32_t hw_idx, pulse_gen_t *p_pulse_gen)
+{
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[0], p_pulse_gen->VAxH, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[1], p_pulse_gen->VBxL, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+
+    pulse_gen_hw[hw_idx].TMR_A->CC[0] = 1 + p_pulse_gen->idle_us * 16;
+    pulse_gen_hw[hw_idx].TMR_A->CC[1] = pulse_gen_hw[hw_idx].TMR_A->CC[0] + p_pulse_gen->point_us[0] * 16;
+    pulse_gen_hw[hw_idx].TMR_A->CC[2] = pulse_gen_hw[hw_idx].TMR_A->CC[1] + p_pulse_gen->point_us[1] * 16;
+    pulse_gen_hw[hw_idx].TMR_A->CC[3] = pulse_gen_hw[hw_idx].TMR_A->CC[2] + p_pulse_gen->point_us[2] * 16;
+}
+
+__STATIC_INLINE void cpg11_tmrA_cb(uint32_t hw_idx)
+{
+    if (pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[3])
+    {
+        uint32_t sel = pulse_gen_hw[hw_idx].private.select;
+
+        pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[3] = 0;
+
+        for (uint32_t i = 0; i < pulse_gen_hw[hw_idx].private.len; i++)
+        {
+            sel = (sel + 1) % pulse_gen_hw[hw_idx].private.len;
+            if (pulse_gen_hw[hw_idx].private.p_pulse_gen[sel].pulse_cnt > 0)
+            {
+                config_tmrA(hw_idx, &pulse_gen_hw[hw_idx].private.p_pulse_gen[sel]);
+                return;
+            }
+        }
+    }
+}
+
+void TIMER1_IRQHandler(void)
+{
+    cpg11_tmrA_cb(0);
+}
+
+void TIMER3_IRQHandler(void)
+{
+    cpg11_tmrB_cb(0);
+}
+
+void TIMER2_IRQHandler(void)
+{
+    cpg11_tmrA_cb(1);
+}
+
+void TIMER4_IRQHandler(void)
+{
+    cpg11_tmrB_cb(1);
+}
+
+void cpg11_pulse_suspend_by_pulse_id(uint32_t pulse_id)
+{
+    for (uint32_t i = 0; i < COUNTOF(pulse_gen_hw); i++)
+    {
+        for (uint32_t j = 0; j < pulse_gen_hw[i].private.len; j++)
+        {
+            if (pulse_gen_hw[i].private.p_pulse_gen[j].pulse_id == pulse_id)
+            {
+                taskENTER_CRITICAL();
+                pulse_gen_hw[i].private.p_pulse_gen[j].VAxH = 0xFFFFFFFF;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VBxH = 0xFFFFFFFF;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VAxL = 0xFFFFFFFF;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VBxL = 0xFFFFFFFF;
+                taskEXIT_CRITICAL();
+            }
+        }
+    }
+}
+
+void cpg11_pulse_resume_by_pulse_id(uint32_t pulse_id)
+{
+    for (uint32_t i = 0; i < COUNTOF(pulse_gen_hw); i++)
+    {
+        for (uint32_t j = 0; j < pulse_gen_hw[i].private.len; j++)
+        {
+            if (pulse_gen_hw[i].private.p_pulse_gen[j].pulse_id == pulse_id)
+            {
+                taskENTER_CRITICAL();
+                pulse_gen_hw[i].private.p_pulse_gen[j].VAxH = pulse_gen_hw[i].p_pulse_gen[j].VAxH;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VBxH = pulse_gen_hw[i].p_pulse_gen[j].VBxH;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VAxL = pulse_gen_hw[i].p_pulse_gen[j].VAxL;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VBxL = pulse_gen_hw[i].p_pulse_gen[j].VBxL;
+                taskEXIT_CRITICAL();
+            }
+        }
+    }
+}
+
+void cpg11_pulse_stop(uint32_t hw_idx)
+{
+    pulse_gen_hw[hw_idx].TMR_B->TASKS_STOP = 1;
+    pulse_gen_hw[hw_idx].TMR_A->TASKS_STOP = 1;
+
+    sd_nvic_DisableIRQ(pulse_gen_hw[hw_idx].TMR_B_IRQn);
+    sd_nvic_ClearPendingIRQ(pulse_gen_hw[hw_idx].TMR_B_IRQn);
+
+    sd_nvic_DisableIRQ(pulse_gen_hw[hw_idx].TMR_A_IRQn);
+    sd_nvic_ClearPendingIRQ(pulse_gen_hw[hw_idx].TMR_A_IRQn);
+
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+}
+
+void cpg11_pulse_start(uint32_t hw_idx, pulse_gen_t *p_pulse_gen)
+{
+    pulse_gen_hw[hw_idx].TMR_B->TASKS_STOP = 1;
+    pulse_gen_hw[hw_idx].TMR_A->TASKS_STOP = 1;
+
+    sd_nvic_DisableIRQ(pulse_gen_hw[hw_idx].TMR_B_IRQn);
+    sd_nvic_ClearPendingIRQ(pulse_gen_hw[hw_idx].TMR_B_IRQn);
+
+    sd_nvic_DisableIRQ(pulse_gen_hw[hw_idx].TMR_A_IRQn);
+    sd_nvic_ClearPendingIRQ(pulse_gen_hw[hw_idx].TMR_A_IRQn);
+
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[0], p_pulse_gen->VAxH, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[1], p_pulse_gen->VBxL, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[2], p_pulse_gen->VBxH, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[3], p_pulse_gen->VAxL, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+
+    uint32_t offs = 8 * hw_idx;
+
+    NRF_PPI->CH[offs + 0].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[0];
+    NRF_PPI->CH[offs + 0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[0]];
+    NRF_PPI->CHENSET          = (1 << (offs + 0));
+
+    NRF_PPI->CH[offs + 1].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[1];
+    NRF_PPI->CH[offs + 1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[1]];
+    NRF_PPI->CHENSET          = (1 << (offs + 1));
+
+    NRF_PPI->CH[offs + 2].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[2];
+    NRF_PPI->CH[offs + 2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[1]];
+    NRF_PPI->CHENSET          = (1 << (offs + 2));
+
+    NRF_PPI->CH[offs + 3].EEP   = (uint32_t)&pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[3];
+    NRF_PPI->CH[offs + 3].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[0]];
+    NRF_PPI->FORK[offs + 3].TEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->TASKS_START;
+    NRF_PPI->CHENSET            = (1 << (offs + 3));
+
+    NRF_PPI->CH[offs + 4].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[0];
+    NRF_PPI->CH[offs + 4].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[2]];
+    NRF_PPI->CHENSET          = (1 << (offs + 4));
+
+    NRF_PPI->CH[offs + 5].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[1];
+    NRF_PPI->CH[offs + 5].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[3]];
+    NRF_PPI->CHENSET          = (1 << (offs + 5));
+
+    NRF_PPI->CH[offs + 6].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[2];
+    NRF_PPI->CH[offs + 6].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[3]];
+    NRF_PPI->CHENSET          = (1 << (offs + 6));
+
+    NRF_PPI->CH[offs + 7].EEP   = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[3];
+    NRF_PPI->CH[offs + 7].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[2]];
+    NRF_PPI->FORK[offs + 7].TEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_A->TASKS_START;
+    NRF_PPI->CHENSET            = (1 << (offs + 7));
+
+    pulse_gen_hw[hw_idx].TMR_B->TASKS_CLEAR = 1;
+    pulse_gen_hw[hw_idx].TMR_A->TASKS_CLEAR = 1;
+
+    pulse_gen_hw[hw_idx].TMR_B->CC[0]    = 1 + p_pulse_gen->point_us[3] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[1]    = pulse_gen_hw[hw_idx].TMR_B->CC[0] + p_pulse_gen->point_us[4] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[2]    = pulse_gen_hw[hw_idx].TMR_B->CC[1] + p_pulse_gen->point_us[5] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[3]    = pulse_gen_hw[hw_idx].TMR_B->CC[2] + p_pulse_gen->point_us[6] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->SHORTS   = NRF_TIMER_SHORT_COMPARE3_STOP_MASK | NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK;
+    pulse_gen_hw[hw_idx].TMR_B->INTENSET = NRF_TIMER_INT_COMPARE3_MASK;
+
+    pulse_gen_hw[hw_idx].TMR_A->CC[0]    = 1;
+    pulse_gen_hw[hw_idx].TMR_A->CC[1]    = pulse_gen_hw[hw_idx].TMR_A->CC[0] + p_pulse_gen->point_us[0] * 16;
+    pulse_gen_hw[hw_idx].TMR_A->CC[2]    = pulse_gen_hw[hw_idx].TMR_A->CC[1] + p_pulse_gen->point_us[1] * 16;
+    pulse_gen_hw[hw_idx].TMR_A->CC[3]    = pulse_gen_hw[hw_idx].TMR_A->CC[2] + p_pulse_gen->point_us[2] * 16;
+    pulse_gen_hw[hw_idx].TMR_A->SHORTS   = NRF_TIMER_SHORT_COMPARE3_STOP_MASK | NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK;
+    pulse_gen_hw[hw_idx].TMR_A->INTENSET = NRF_TIMER_INT_COMPARE3_MASK;
+
+    sd_nvic_EnableIRQ(pulse_gen_hw[hw_idx].TMR_A_IRQn);
+    sd_nvic_EnableIRQ(pulse_gen_hw[hw_idx].TMR_B_IRQn);
+
+    pulse_gen_hw[hw_idx].TMR_A->TASKS_START = 1;
+}
+
+void cpg11_pulse_init(uint32_t hw_idx, pulse_gen_t *p_pulse_gen, uint32_t len)
+{
+    taskENTER_CRITICAL();
+
+    if (pulse_gen_hw[hw_idx].private.p_pulse_gen != NULL)
+    {
+        pulse_gen_hw[hw_idx].TMR_B->TASKS_STOP = 1;
+        pulse_gen_hw[hw_idx].TMR_A->TASKS_STOP = 1;
+
+        sd_nvic_DisableIRQ(pulse_gen_hw[hw_idx].TMR_B_IRQn);
+        sd_nvic_ClearPendingIRQ(pulse_gen_hw[hw_idx].TMR_B_IRQn);
+
+        sd_nvic_DisableIRQ(pulse_gen_hw[hw_idx].TMR_A_IRQn);
+        sd_nvic_ClearPendingIRQ(pulse_gen_hw[hw_idx].TMR_A_IRQn);
+
+        nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+        nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+        nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+        nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+
+        vPortFree(pulse_gen_hw[hw_idx].private.p_pulse_gen);
+    }
+
+    uint32_t swap_idle_us = p_pulse_gen[len - 1].idle_us;
+    for (int i = len - 1; i > 0; i--)
+    {
+        p_pulse_gen[i].idle_us = p_pulse_gen[i - 1].idle_us;
+    }
+    p_pulse_gen[0].idle_us = swap_idle_us;
+
+    pulse_gen_hw[hw_idx].p_pulse_gen    = p_pulse_gen;
+    pulse_gen_hw[hw_idx].private.len    = len;
+    pulse_gen_hw[hw_idx].private.select = 0;
+
+    pulse_gen_hw[hw_idx].private.p_pulse_gen = pvPortMalloc(sizeof(pulse_gen_t) * len);
+    memcpy(pulse_gen_hw[hw_idx].private.p_pulse_gen, pulse_gen_hw[hw_idx].p_pulse_gen, sizeof(*p_pulse_gen) * len);
+
+    taskEXIT_CRITICAL();
+};
+
+void cpg_pulse_default_demo_ext(void)
+{
+    bool e1 = 1;
+    bool e2 = 1;
+    bool e3 = 1;
+    bool e4 = 1;
+    pulse_gen_t p_pulse_genA[2];
+    pulse_gen_t p_pulse_genB[2];
+
+    p_pulse_genA[0] = (pulse_gen_t) {
+        .VBxH        = VB1H_PIN,
+        .VBxL        = VB1L_PIN,
+        .VAxH        = VA1H_PIN,
+        .VAxL        = VA1L_PIN,
+        .point_us[0] = 1,
+        .point_us[1] = 50,
+        .point_us[2] = 1,
+        .point_us[3] = 0,
+        .point_us[4] = 1,
+        .point_us[5] = 50,
+        .point_us[6] = 1,
+        .idle_us     = 1000,
+        .pulse_cnt   = UINT32_MAX,
+        .pulse_id    = PULSE_ID_A,
+    };
+
+    p_pulse_genA[1] = (pulse_gen_t) {
+        .VBxH        = VB2H_PIN,
+        .VBxL        = VB2L_PIN,
+        .VAxH        = VA2H_PIN,
+        .VAxL        = VA2L_PIN,
+        .point_us[0] = 1,
+        .point_us[1] = 100,
+        .point_us[2] = 1,
+        .point_us[3] = 0,
+        .point_us[4] = 1,
+        .point_us[5] = 100,
+        .point_us[6] = 1,
+        .idle_us     = 2000,
+        .pulse_cnt   = UINT32_MAX,
+        .pulse_id    = PULSE_ID_B,
+    };
+
+    p_pulse_genB[0] = (pulse_gen_t) {
+        .VBxH        = VB3H_PIN,
+        .VBxL        = VB3L_PIN,
+        .VAxH        = VA3H_PIN,
+        .VAxL        = VA3L_PIN,
+        .point_us[0] = 1,
+        .point_us[1] = 150,
+        .point_us[2] = 1,
+        .point_us[3] = 0,
+        .point_us[4] = 1,
+        .point_us[5] = 150,
+        .point_us[6] = 1,
+        .idle_us     = 3000,
+        .pulse_cnt   = UINT32_MAX,
+        .pulse_id    = PULSE_ID_C,
+    };
+
+    p_pulse_genB[1] = (pulse_gen_t) {
+        .VBxH        = VB4H_PIN,
+        .VBxL        = VB4L_PIN,
+        .VAxH        = VA4H_PIN,
+        .VAxL        = VA4L_PIN,
+        .point_us[0] = 1,
+        .point_us[1] = 200,
+        .point_us[2] = 1,
+        .point_us[3] = 0,
+        .point_us[4] = 1,
+        .point_us[5] = 200,
+        .point_us[6] = 1,
+        .idle_us     = 4000,
+        .pulse_cnt   = UINT32_MAX,
+        .pulse_id    = PULSE_ID_D,
+    };
+
+    if (e1)
+    {
+        nrf_gpio_pin_clear(p_pulse_genA[0].VBxL);
+        nrf_gpio_pin_clear(p_pulse_genA[0].VBxH);
+        nrf_gpio_pin_clear(p_pulse_genA[0].VAxL);
+        nrf_gpio_pin_clear(p_pulse_genA[0].VAxH);
+    }
+
+    if (e2)
+    {
+        nrf_gpio_pin_clear(p_pulse_genA[1].VBxL);
+        nrf_gpio_pin_clear(p_pulse_genA[1].VBxH);
+        nrf_gpio_pin_clear(p_pulse_genA[1].VAxL);
+        nrf_gpio_pin_clear(p_pulse_genA[1].VAxH);
+    }
+
+    if (e3)
+    {
+        nrf_gpio_pin_clear(p_pulse_genB[0].VBxL);
+        nrf_gpio_pin_clear(p_pulse_genB[0].VBxH);
+        nrf_gpio_pin_clear(p_pulse_genB[0].VAxL);
+        nrf_gpio_pin_clear(p_pulse_genB[0].VAxH);
+    }
+
+    if (e4)
+    {
+        nrf_gpio_pin_clear(p_pulse_genB[1].VBxL);
+        nrf_gpio_pin_clear(p_pulse_genB[1].VBxH);
+        nrf_gpio_pin_clear(p_pulse_genB[1].VAxL);
+        nrf_gpio_pin_clear(p_pulse_genB[1].VAxH);
+    }
+
+    if (e1 && e2)
+    {
+        cpg11_pulse_init(0, p_pulse_genA, 2);
+        cpg11_pulse_start(0, p_pulse_genA);
+    }
+    else if (e1 && e2 == 0)
+    {
+        cpg11_pulse_init(0, p_pulse_genA, 1);
+        cpg11_pulse_start(0, p_pulse_genA);
+    }
+    else if (e2 && e1 == 0)
+    {
+        cpg11_pulse_init(0, &p_pulse_genA[1], 1);
+        cpg11_pulse_start(0, &p_pulse_genA[1]);
+    }
+
+    if (e3 && e4)
+    {
+        cpg11_pulse_init(1, p_pulse_genB, 2);
+        cpg11_pulse_start(1, p_pulse_genB);
+    }
+    else if (e3 && e4 == 0)
+    {
+        cpg11_pulse_init(1, p_pulse_genB, 1);
+        cpg11_pulse_start(1, p_pulse_genB);
+    }
+    else if (e4 && e3 == 0)
+    {
+        cpg11_pulse_init(1, &p_pulse_genB[1], 1);
+        cpg11_pulse_start(1, &p_pulse_genB[1]);
+    }
+}
+
+void cpg11_io_init(void)
+{
+    const uint32_t pel_pins_default_high[] = {
+        LED_R_PIN,
+        LED_G_PIN,
+        CS_MEM_PIN,
+        ADPT_CLR_PIN,
+        ADPT_LE_PIN
+    };
+
+    const uint32_t pel_pins_default_low[] = {
+        LED_B_PIN,
+        TW_SCKI_0_PIN,
+        TW_SCKI_1_PIN,
+        ADPT_CLK_PIN,
+        HV_EN_PIN,
+        SPIM_CLK_PIN,
+        SPIM_MOSI_PIN,
+        SPIM_MISO_PIN,
+        ADPT0_S4_PIN,
+        ADPT0_S3_PIN,
+        ADPT0_S2_PIN,
+        ADPT0_S1_PIN,
+        ADPT1_S4_PIN,
+        ADPT1_S3_PIN,
+        ADPT1_S2_PIN,
+        ADPT1_S1_PIN,
+
+        VB1L_PIN,
+        VB1H_PIN,
+        VA1L_PIN,
+        VA1H_PIN,
+
+        VB2L_PIN,
+        VB2H_PIN,
+        VA2L_PIN,
+        VA2H_PIN,
+
+        VB3L_PIN,
+        VB3H_PIN,
+        VA3L_PIN,
+        VA3H_PIN,
+
+        VB4L_PIN,
+        VB4H_PIN,
+        VA4L_PIN,
+        VA4H_PIN,
+    };
+
+    for (int i = 0; i < COUNTOF(pel_pins_default_high); i++)
+    {
+        nrf_gpio_cfg_output(pel_pins_default_high[i]);
+        nrf_gpio_pin_set(pel_pins_default_high[i]);
+    }
+
+    for (int i = 0; i < COUNTOF(pel_pins_default_low); i++)
+    {
+        nrf_gpio_cfg_output(pel_pins_default_low[i]);
+        nrf_gpio_pin_clear(pel_pins_default_low[i]);
+    }
+
+    nrf_gpio_cfg_input(AIN0_PIN, NRF_GPIO_PIN_NOPULL);
+    nrf_gpio_cfg_input(AIN1_PIN, NRF_GPIO_PIN_NOPULL);
+
+    for (uint32_t i = 0; i < COUNTOF(pulse_gen_hw); i++)
+    {
+        pulse_gen_hw[i].TMR_B->PRESCALER = NRF_TIMER_FREQ_16MHz;
+        pulse_gen_hw[i].TMR_B->MODE      = NRF_TIMER_MODE_TIMER;
+        pulse_gen_hw[i].TMR_B->BITMODE   = NRF_TIMER_BIT_WIDTH_32;
+
+        pulse_gen_hw[i].TMR_A->PRESCALER = NRF_TIMER_FREQ_16MHz;
+        pulse_gen_hw[i].TMR_A->MODE      = NRF_TIMER_MODE_TIMER;
+        pulse_gen_hw[i].TMR_A->BITMODE   = NRF_TIMER_BIT_WIDTH_32;
+
+        sd_nvic_SetPriority(pulse_gen_hw[i].TMR_B_IRQn, _PRIO_APP_HIGH);
+        sd_nvic_SetPriority(pulse_gen_hw[i].TMR_A_IRQn, _PRIO_APP_HIGH);
+    }
+
+    for (int i = 0; i < 2; i++)
+    {
+        pulse_gen_hw[i].p_pulse_gen[0].VAxH         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[0].VBxH         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[0].VAxL         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[0].VBxL         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[1].VAxH         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[1].VBxH         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[1].VAxL         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[1].VBxL         = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[0].VAxH = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[0].VBxH = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[0].VAxL = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[0].VBxL = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[1].VAxH = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[1].VBxH = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[1].VAxL = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[1].VBxL = 0xFFFFFFFF;
+    }
+}
+
+#endif

app/src/elite_dev_v1_0.c

@@ -0,0 +1,274 @@
+#include "app_config.h"
+
+#include "elite_dev_v1_0.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
+
+#include "app_error.h"
+#include "nrf_gpio.h"
+#include "nrf_log.h"
+
+#include <stdint.h>
+
+// RIS (real instruction)
+#define DEV_MODE            0xFF // Develop Mode
+
+// VIS (virtual instruction)
+#define VIS_RST             0xF0
+#define VIS_DEVICE_SHINY    0x10
+
+// CIS (control instruction)
+#define CIS_VERSION         0x40
+#define CIS_VOLT            0x10
+#define CIS_TEMPERATURE     0x80
+#define CIS_CALI            0x30
+
+#define VERSION_DATE_YEAR   24
+#define VERSION_DATE_MONTH  7
+#define VERSION_DATE_DAY    2
+#define VERSION_DATE_HOUR   11
+#define VERSION_DATE_MINUTE 32
+static void cis_version(uint8_t *ins, uint16_t size)
+{
+    NRF_LOG_INFO("%s", __FUNCTION__);
+    uint8_t cis_ver[] = {
+        CIS_VERSION,
+        VERSION_DATE_YEAR,
+        VERSION_DATE_MONTH,
+        VERSION_DATE_DAY,
+        VERSION_DATE_HOUR,
+        VERSION_DATE_MINUTE,
+    };
+    extern ret_code_t le_data_update(uint8_t *p_value, uint16_t len);
+    le_data_update((void *)cis_ver, sizeof(cis_ver));
+}
+
+static void vis_rst(uint8_t *ins, uint16_t size)
+{
+    NRF_LOG_INFO("%s", __FUNCTION__);
+}
+
+#define UNDEF_GPIO 0xFFFFFFFF
+
+// The GPIO corresponding to the pin
+const uint32_t pin_to_gpio_table[] = {
+    [6]  = NRF_GPIO_PIN_MAP(0, 22),
+    [8]  = NRF_GPIO_PIN_MAP(0, 25),
+    [9]  = NRF_GPIO_PIN_MAP(0, 19),
+    [10] = NRF_GPIO_PIN_MAP(0, 21),
+    [11] = NRF_GPIO_PIN_MAP(1, 00),
+    [12] = NRF_GPIO_PIN_MAP(0, 18),
+    [13] = NRF_GPIO_PIN_MAP(0, 17),
+    [14] = NRF_GPIO_PIN_MAP(0, 20),
+    [16] = NRF_GPIO_PIN_MAP(0, 14),
+    [17] = NRF_GPIO_PIN_MAP(0, 13),
+    [18] = NRF_GPIO_PIN_MAP(0, 11),
+    [20] = NRF_GPIO_PIN_MAP(0, 15),
+    [25] = NRF_GPIO_PIN_MAP(1, 8),
+    [26] = NRF_GPIO_PIN_MAP(0, 12),
+    [27] = NRF_GPIO_PIN_MAP(0, 7),
+    [28] = NRF_GPIO_PIN_MAP(1, 9),
+    [29] = NRF_GPIO_PIN_MAP(0, 8),
+    [30] = NRF_GPIO_PIN_MAP(0, 6),
+    [31] = NRF_GPIO_PIN_MAP(0, 5),
+    [32] = NRF_GPIO_PIN_MAP(0, 27),
+    [33] = NRF_GPIO_PIN_MAP(0, 26),
+    [34] = NRF_GPIO_PIN_MAP(0, 4),
+    [36] = NRF_GPIO_PIN_MAP(0, 1),
+    [37] = NRF_GPIO_PIN_MAP(0, 29),
+    [38] = NRF_GPIO_PIN_MAP(0, 0),
+    [39] = NRF_GPIO_PIN_MAP(0, 31),
+    [40] = NRF_GPIO_PIN_MAP(1, 15),
+    [41] = NRF_GPIO_PIN_MAP(0, 2),
+    [42] = NRF_GPIO_PIN_MAP(0, 30),
+    [43] = NRF_GPIO_PIN_MAP(0, 28),
+    [44] = NRF_GPIO_PIN_MAP(1, 12),
+    [45] = NRF_GPIO_PIN_MAP(1, 14),
+    [46] = NRF_GPIO_PIN_MAP(0, 3),
+    [47] = NRF_GPIO_PIN_MAP(1, 13),
+    [48] = NRF_GPIO_PIN_MAP(1, 3),
+    [49] = NRF_GPIO_PIN_MAP(1, 10),
+    [50] = NRF_GPIO_PIN_MAP(1, 6),
+    [51] = NRF_GPIO_PIN_MAP(1, 11),
+    [52] = NRF_GPIO_PIN_MAP(0, 10),
+    [53] = NRF_GPIO_PIN_MAP(0, 9),
+    [59] = NRF_GPIO_PIN_MAP(1, 2),
+    [60] = NRF_GPIO_PIN_MAP(0, 24),
+    [61] = NRF_GPIO_PIN_MAP(0, 23),
+    [62] = NRF_GPIO_PIN_MAP(0, 16),
+};
+
+static uint32_t bmd380pins_convert_to_gpio(uint32_t pin)
+{
+    uint32_t gpio;
+
+    switch (pin)
+    {
+        case 6:
+        case 8:
+        case 9:
+        case 10:
+        case 11:
+        case 12:
+        case 13:
+        case 14:
+        case 16:
+        case 17:
+        case 18:
+        case 20:
+        case 25:
+        case 26:
+        case 27:
+        case 28:
+        case 29:
+        case 30:
+        case 31:
+        case 32:
+        case 33:
+        case 34:
+        case 36:
+        case 37:
+        case 38:
+        case 39:
+        case 40:
+        case 41:
+        case 42:
+        case 43:
+        case 44:
+        case 45:
+        case 46:
+        case 47:
+        case 48:
+        case 49:
+        case 50:
+        case 51:
+        case 52:
+        case 53:
+        case 59:
+        case 60:
+        case 61:
+        case 62:
+            gpio = pin_to_gpio_table[pin];
+            break;
+        default:
+            gpio = UNDEF_GPIO;
+            NRF_LOG_INFO("UNDEF_GPIO: pin %d can't convert to gpio number", pin);
+            break;
+    }
+
+    return gpio;
+}
+
+static void set_bmd380_pin_signal(uint32_t pin, uint32_t high_low)
+{
+    uint32_t gpio = bmd380pins_convert_to_gpio(pin);
+
+    if (gpio != UNDEF_GPIO)
+    {
+        nrf_gpio_cfg_output(gpio);
+        nrf_gpio_pin_write(gpio, high_low);
+        NRF_LOG_INFO("set pin %d (gpio %d) = %d", pin, gpio, high_low);
+    }
+}
+
+/*
+    dev_mode_gpio_function
+    (1)0x3000FFA000ppss
+            -func: set_bmd380_pin_signal
+            -pp: pin number     06h-3Fh
+                06h: P0.22_GPIO
+                08h: P0.25_GPIO
+                ......
+                3Eh: P0.16_GPIO
+            -ss: signal         00h-01h
+                00h: low
+                01h: high
+
+    (2)0x3000FFA001ss
+        -func: set_bmd380 all pin signal high/low
+        -ss: signal         00h-01h
+            00h: low
+            01h: high
+*/
+void dev_mode_gpio_function(uint8_t *ins)
+{
+    struct __PACKED
+    {
+        uint8_t id     : 4;
+        uint8_t        : 4;
+        uint16_t magic : 16;
+        uint8_t dev_opcode;
+        uint8_t gpio_function_opcode;
+        uint8_t param[];
+    } *p_ins = (void *)ins;
+
+    switch (p_ins->gpio_function_opcode)
+    {
+        case 0x00: {
+            uint32_t pin      = p_ins->param[0];
+            uint32_t high_low = p_ins->param[1];
+            set_bmd380_pin_signal(pin, high_low);
+            break;
+        }
+
+        case 0x01: {
+            uint32_t high_low    = p_ins->param[0];
+            uint32_t set_pin[44] = { 6, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 59, 60, 61, 62 };
+
+            for (int i = 0; i < sizeof(set_pin) / sizeof(set_pin[0]); i++)
+            {
+                set_bmd380_pin_signal(set_pin[i], high_low);
+            }
+            break;
+        }
+    }
+}
+
+#define MAGIC_NUM 0xFF00
+static void dev_mode(uint8_t *ins, uint16_t size)
+{
+    NRF_LOG_INFO("%s", __FUNCTION__);
+    struct __PACKED
+    {
+        uint8_t id     : 4;
+        uint8_t        : 4;
+        uint16_t magic : 16;
+        uint8_t opcode;
+        uint8_t param[];
+    } *p_ins = (void *)ins;
+
+    if (p_ins->magic != MAGIC_NUM)
+    {
+        return;
+    }
+
+    // TODO...
+    switch (p_ins->opcode)
+    {
+        case 0xA0:
+            dev_mode_gpio_function(ins);
+            break;
+
+        default:
+            break;
+    }
+}
+
+const elite_instance_t pel_elite_instance = {
+    .cis_func = {
+                 [CIS_VERSION] = cis_version,
+                 },
+    .vis_func = {
+                 [VIS_RST] = vis_rst,
+                 },
+    .ris_func = {
+                 [DEV_MODE] = dev_mode,
+                 }
+};
+
+const elite_instance_t *dev_init(void)
+{
+    return &pel_elite_instance;
+}
+
+#endif /* !DEF_ELITE_MODEL */

app/src/elite_edc_v2_0_cycle_iv_mode.c

@@ -0,0 +1,430 @@
+#include "app_config.h"
+
+#include "elite_edc_v2_0.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+
+#include "dac_drv.h"
+#include "elite.h"
+#include "elite_board.h"
+
+#include "nrf.h"
+#include "nrf_log.h"
+
+#include "FreeRTOS.h"
+#include "elite_board.h"
+#include "semphr.h"
+#include "task.h"
+
+#include <math.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#define OUT_0 DAC0
+#define OUT_1 DAC1
+
+typedef struct __PACKED
+{
+    uint32_t notify_time;
+    int32_t ch1_data;
+    int32_t ch2_data;
+    int32_t ch3_data;
+    uint16_t cycle;
+    uint8_t finish_flag;
+    uint32_t bat_volt;
+    uint8_t packet_seq;
+    int32_t ch4_data;
+    int32_t ch5_data;
+    int32_t ch6_data;
+} payload_t;
+
+typedef struct __PACKED
+{
+    uint8_t mem_board_id;
+    payload_t payload;
+    uint8_t : 8;
+    uint8_t : 8;
+    uint8_t : 8;
+} elite_notify_packet_t;
+
+typedef struct
+{
+    uint32_t id;
+    uint32_t mS_period;
+    elite_dac_config_t config;
+} iv_cycle_mode_param_t;
+
+const edc20_dac_cal_data_t edc20_dac_cal_data = {
+    .dac_c = { 2.9701475, 121.9763670 },
+    .dac_f = {
+              [0] = { 65.7454092, -290.3872456, -36.65060000 },
+              [1] = { 27.4300538, -100.6332479, -37.39872222 },
+              [2] = { 7.61192880, -0.568019000, -40.99282222 } }
+};
+#define FS_1000mV 1000
+#define FS_2800mV 2800
+#define FS_8000mV 8000
+const float edc20_range_mV[] = {
+    [0] = FS_1000mV,
+    [1] = FS_2800mV,
+    [2] = FS_8000mV,
+};
+
+static SemaphoreHandle_t semphr_start = NULL;
+
+static TaskHandle_t task_handle = NULL;
+
+static bool running = false;
+
+extern ret_code_t le_event_notify(uint8_t *p_value, uint16_t len);
+
+static ret_code_t _send_start_packet(elite_notify_packet_t *p_buf, uint32_t loops)
+{
+    memset(&p_buf->payload, 0x00, sizeof(p_buf->payload));
+    for (uint32_t i = 0; i < loops; i++)
+    {
+        ret_code_t ret = le_event_notify((void *)p_buf, sizeof(*p_buf));
+        if (ret != NRF_SUCCESS)
+        {
+            return ret;
+        }
+    }
+    return NRF_SUCCESS;
+}
+
+static ret_code_t _send_data_packet(elite_notify_packet_t *p_notify_buf, bool is_last_notify)
+{
+    static int32_t ch1 = 0;
+    static int32_t ch2 = 0;
+    static int32_t ch3 = 0;
+
+    ch1 += 100;
+    ch2++;
+    ch3 = ch2;
+
+    p_notify_buf->payload.notify_time = xTaskGetTickCount();
+    p_notify_buf->payload.ch1_data    = ch1;
+    p_notify_buf->payload.ch2_data    = ch2;
+    p_notify_buf->payload.ch3_data    = ch3;
+    p_notify_buf->payload.bat_volt    = 3600;
+    p_notify_buf->payload.packet_seq++;
+    p_notify_buf->payload.finish_flag = is_last_notify;
+
+    return le_event_notify((void *)p_notify_buf, sizeof(*p_notify_buf));
+}
+
+typedef struct
+{
+    float dir;
+    float mV_output;
+    float mV_max;
+    float mV_min;
+    float mV_start;
+    float mV_stop;
+    float step;
+    uint32_t cycle_cnt;
+    uint32_t cycle_max;
+    uint32_t fullscale;
+    struct
+    {
+        float eta_c;
+        float eta_f;
+        float Voffset;
+        float Vc;
+        float Nc;
+        float Nc0;
+        float Nf;
+    };
+} cycle_iv_dac_t;
+
+typedef struct
+{
+    uint32_t period;
+} cycle_iv_adc_t;
+
+static uint32_t mV_out_0(cycle_iv_dac_t *p)
+{
+    for (uint32_t i = 0; i < COUNTOF(edc20_range_mV); i++)
+    {
+        if ((p->mV_max - p->mV_min) <= edc20_range_mV[i])
+        {
+            p->fullscale = edc20_range_mV[i];
+            p->eta_c     = edc20_dac_cal_data.dac_c.coeff;
+            p->eta_f     = edc20_dac_cal_data.dac_f[i].coeff;
+            p->Voffset   = edc20_dac_cal_data.dac_f[i].Voffset;
+            break;
+        }
+    }
+    p->Vc  = (p->mV_max + p->mV_min) / 2;
+    p->Nc  = round((p->Vc - p->Voffset) * p->eta_c) + 32768;
+    p->Nc0 = round((0 - p->Voffset) * p->eta_c) + 32768;
+    return p->Nc;
+}
+
+static uint32_t mV_out_1(cycle_iv_dac_t *p)
+{
+    p->Nf = round((p->mV_output - p->Vc - p->Voffset - (p->Nc0 - 32768) / p->eta_c) * p->eta_f) + 32768;
+    return p->Nf;
+}
+
+static uint32_t cal_dac_timer_interval(elite_dac_config_t *p_config, cycle_iv_dac_t *p_cycle_iv_dac)
+{
+    uint32_t intvl;
+    float step_time = p_config->uS_step;
+    for (intvl = 100; intvl < 1000000; intvl *= 10)
+    {
+        p_cycle_iv_dac->step = (p_config->mV_step * intvl) / step_time;
+        if (p_cycle_iv_dac->step >= 0.001)
+        {
+            return intvl;
+        }
+    }
+    return intvl;
+}
+
+static void dac_select_circuit(cycle_iv_dac_t *p)
+{
+    float scan_range = p->mV_max - p->mV_min;
+
+    if (scan_range <= FS_1000mV)
+    {
+        circuit_selection_dac_fine_tune_f0();
+    }
+    else if (scan_range <= FS_2800mV)
+    {
+        circuit_selection_dac_fine_tune_f1();
+    }
+    else if (scan_range <= FS_8000mV)
+    {
+        circuit_selection_dac_fine_tune_f2();
+    }
+}
+
+void _callback(void *p_arg)
+{
+    cycle_iv_dac_t *p = p_arg;
+
+    if (p->mV_output <= p->mV_min)
+    {
+        p->mV_output = p->mV_min;
+        p->dir       = 1;
+    }
+
+    if (p->mV_output >= p->mV_max)
+    {
+        p->mV_output = p->mV_max;
+        p->dir       = -1;
+    }
+
+    dac_write_through(OUT_1, mV_out_1(p));
+
+    if (p->mV_output == p->mV_start)
+    {
+        p->cycle_cnt++;
+        if (p->cycle_cnt > p->cycle_max)
+        {
+            running = false;
+        }
+    }
+    p->mV_output += p->dir * p->step;
+}
+
+static void edc20_cycle_iv_mode_task(void *p_arg)
+{
+    elite_notify_packet_t packet_buf;
+    cycle_iv_dac_t dac_param;
+    cycle_iv_adc_t adc_param;
+    iv_cycle_mode_param_t mode_param;
+
+    taskENTER_CRITICAL();
+
+    /* copy iv cycle parameter */
+    memcpy(&mode_param, p_arg, sizeof(mode_param));
+
+    memset(&packet_buf, 0x00, sizeof(packet_buf));
+    memset(&dac_param, 0x00, sizeof(dac_param));
+    memset(&adc_param, 0x00, sizeof(adc_param));
+
+    taskEXIT_CRITICAL();
+
+    if (1)
+    {
+        char info[256];
+        snprintf(info, 256, "%s() @ %p start", __FUNCTION__, xTaskGetCurrentTaskHandle());
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%8ld", "id", mode_param.id);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%7.0fmV", "V_start", mode_param.config.mV_start);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%7.0fmV", "V_stop", mode_param.config.mV_stop);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%7.0fmV", "uV_step", mode_param.config.mV_step);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%8ldus", "uS_step_time", mode_param.config.uS_step);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%8ld", "cycles", mode_param.config.cycles);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%8ldms", "mS_period", mode_param.mS_period);
+        NRF_LOG_INFO("%s", info);
+    }
+
+    /* set memborad id */
+    packet_buf.mem_board_id = mode_param.id;
+
+    /* send start packet 4 times */
+    _send_start_packet(&packet_buf, 4);
+
+    dac_param.mV_output = mode_param.config.mV_start;
+    dac_param.mV_max    = MAX(mode_param.config.mV_start, mode_param.config.mV_stop);
+    dac_param.mV_min    = MIN(mode_param.config.mV_start, mode_param.config.mV_stop);
+    dac_param.mV_start  = mode_param.config.mV_start;
+    dac_param.mV_stop   = mode_param.config.mV_stop;
+    dac_param.dir       = dac_param.mV_output == dac_param.mV_min ? 1 : -1;
+    dac_param.cycle_cnt = 0;
+    dac_param.cycle_max = mode_param.config.cycles;
+    dac_param.fullscale = 0;
+
+    if (1)
+    {
+        NRF_LOG_INFO("%s", "");
+        mV_out_0(&dac_param);
+        char info[256];
+        snprintf(info, 256, "%16s:%10.3f", "eta_c", dac_param.eta_c);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%10.3f", "eta_f", dac_param.eta_f);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%10.3f", "Voffset", dac_param.Voffset);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%10.3f", "Vc", dac_param.Vc);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%10.3f", "Nc", dac_param.Nc);
+        NRF_LOG_INFO("%s", info);
+        snprintf(info, 256, "%16s:%10.3f", "Nc0", dac_param.Nc0);
+        NRF_LOG_INFO("%s", info);
+
+        dac_param.mV_output = dac_param.mV_start;
+        mV_out_1(&dac_param);
+        snprintf(info, 256, "%16s:%10.3f", "V1 Nf", dac_param.Nf);
+        NRF_LOG_INFO("%s", info);
+
+        dac_param.mV_output = dac_param.mV_stop;
+        mV_out_1(&dac_param);
+        snprintf(info, 256, "%16s:%10.3f", "V2 Nf", dac_param.Nf);
+        NRF_LOG_INFO("%s", info);
+    }
+
+    led_set(LED_REC);
+    dac_write_through(OUT_0, mV_out_0(&dac_param));
+
+    dac_param.mV_output = dac_param.mV_start;
+    dac_write_through(OUT_1, mV_out_1(&dac_param));
+
+    dac_select_circuit(&dac_param);
+
+    /* start DAC timer */
+    edc20_dac_tim_start(cal_dac_timer_interval(&mode_param.config, &dac_param), _callback, &dac_param);
+
+    /* start ADC timer */
+    edc20_adc_tim_start(&mode_param.config);
+
+    /* get current tick */
+    TickType_t tick = xTaskGetTickCount();
+
+    uint32_t notify_delay = pdMS_TO_TICKS(mode_param.mS_period);
+
+    /* start data update process */
+    running = true;
+
+    while (running)
+    {
+        ret_code_t ret = _send_data_packet(&packet_buf, false);
+        switch (ret)
+        {
+            case NRF_SUCCESS:
+            case NRF_ERROR_RESOURCES:
+                vTaskDelayUntil(&tick, notify_delay);
+                break;
+            default:
+                running = false;
+                break;
+        }
+    }
+
+    edc20_dac_tim_stop();
+    edc20_adc_tim_stop();
+    dac_init();
+    led_set(LED_IDLE_CONNECTED);
+
+    if (1)
+    {
+        char info[256];
+        snprintf(info, 256, "%s() @ %p stop", __FUNCTION__, xTaskGetCurrentTaskHandle());
+        NRF_LOG_INFO("%s", info);
+    }
+
+    vTaskDelete(NULL);
+}
+
+#define VDIRECTION(v1, v2) ((v1 > v2) ? 0 : 1)
+#define VMAX(v1, v2)       ((v1 >= v2) ? v1 : v2)
+#define VMIN(v1, v2)       ((v1 < v2) ? v1 : v2)
+
+static uint32_t convt_uS_step(uint32_t idx)
+{
+    switch (idx)
+    {
+        case 0: { // 0.5 sec
+            return 500000;
+        }
+        case 1: { // 1 sec
+            return 1000000;
+        }
+        case 2: { // 2 sec
+            return 2000000;
+        }
+        default: { // 1 sec
+            return 1000000;
+        }
+    }
+}
+
+bool is_mode_running(void)
+{
+    return running;
+}
+
+void edc20_cycle_iv_mode_start(uint8_t *ins, uint16_t size)
+{
+    struct __PACKED
+    {
+        uint8_t id : 4;
+        uint8_t    : 4;
+        uint8_t    : 8;
+        uint8_t    : 8;
+        uint16_t volt_start; // unit: 100uV, -5V = 0, 0V = 25000, 5V = 50000
+        uint16_t volt_stop;  // unit: 100uV, -5V = 0, 0V = 25000, 5V = 50000
+        uint16_t step;       // unit: 100uV
+        uint8_t step_time;   // enum: 0 = 5000us, 1 = 10000us, 2 = 20000us
+        uint16_t cycles;     // 0 ~ 500000
+        uint8_t : 8;
+        uint8_t hi_z_en;      // lower nibble
+        uint16_t sample_rate; // unit: 0.1Hz
+    } *p = (void *)ins;
+
+    iv_cycle_mode_param_t mode_param = {
+        .id              = p->id,
+        .mS_period       = 1000 * 10 / __REVSH(p->sample_rate),
+        .config.mV_start = ((__REVSH(p->volt_start) & 0xFFFF) / 10 - 2500) * 2,
+        .config.mV_stop  = ((__REVSH(p->volt_stop) & 0xFFFF) / 10 - 2500) * 2,
+        .config.mV_step  = (uint32_t)__REVSH(p->step) / 10,
+        .config.uS_step  = convt_uS_step(p->step_time),
+        .config.cycles   = (__REVSH(p->cycles) & 0xFFFF)
+    };
+
+    xTaskCreate(edc20_cycle_iv_mode_task, "iv_mode", 2048, (void *)&mode_param, 3, &task_handle);
+
+    portYIELD();
+}
+
+#endif /* ! DEF_ELITE_MODEL */

app/src/elite_edc_v2_0_io.c

@@ -0,0 +1,721 @@
+#include "elite_board.h"
+
+#include "nrf_drv_spi.h"
+#include "nrf_drv_twi.h"
+#include "nrf_gpio.h"
+#include "nrf_log.h"
+#include "nrf_timer.h"
+
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "semphr.h"
+
+#include "adc_drv.h"
+#include "dac_drv.h"
+#include "sw_drv.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
+
+//==========================================================
+// gpio
+//==========================================================
+void gpio_init(void)
+{
+    nrf_gpio_pin_set(POWER_5V_EN_PIN);
+    nrf_gpio_pin_set(POWER_12V_EN_PIN);
+    nrf_gpio_pin_set(OFF_PIN);
+
+    nrf_gpio_pin_clear(Vout_FB_PIN);
+    nrf_gpio_pin_clear(Vout_IN_PIN);
+    nrf_gpio_pin_clear(Iin4_TEST_PIN);
+    nrf_gpio_pin_clear(Iin3_SEL_PIN);
+    nrf_gpio_pin_clear(Iin3_PIN);
+    nrf_gpio_pin_clear(Iin2_PIN);
+    nrf_gpio_pin_clear(Iin1_PIN);
+    nrf_gpio_pin_clear(Vin2_PIN);
+    nrf_gpio_pin_clear(Vin1_PIN);
+    nrf_gpio_pin_clear(CV_CTRL_PIN);
+    nrf_gpio_pin_clear(ADCA2_PIN);
+    nrf_gpio_pin_clear(ADCA1_PIN);
+    nrf_gpio_pin_clear(ADCA0_PIN);
+    nrf_gpio_pin_clear(RST_SW_PIN);
+
+    nrf_gpio_cfg_output(POWER_5V_EN_PIN);
+    nrf_gpio_cfg_output(POWER_12V_EN_PIN);
+    nrf_gpio_cfg_output(OFF_PIN);
+    nrf_gpio_cfg_output(Vout_FB_PIN);
+    nrf_gpio_cfg_output(Vout_IN_PIN);
+    nrf_gpio_cfg_output(Iin4_TEST_PIN);
+    nrf_gpio_cfg_output(Iin3_SEL_PIN);
+    nrf_gpio_cfg_output(Iin3_PIN);
+    nrf_gpio_cfg_output(Iin2_PIN);
+    nrf_gpio_cfg_output(Iin1_PIN);
+    nrf_gpio_cfg_output(Vin2_PIN);
+    nrf_gpio_cfg_output(Vin1_PIN);
+    nrf_gpio_cfg_output(CV_CTRL_PIN);
+    nrf_gpio_cfg_output(ADCA2_PIN);
+    nrf_gpio_cfg_output(ADCA1_PIN);
+    nrf_gpio_cfg_output(ADCA0_PIN);
+    nrf_gpio_cfg_output(RST_SW_PIN);
+    nrf_gpio_cfg_output(CS_SW_PIN);
+    nrf_gpio_cfg_output(CS_MEM_PIN);
+    nrf_gpio_cfg_output(CS_ADC_PIN);
+    nrf_gpio_cfg_output(CS_DAC_PIN);
+
+    nrf_gpio_cfg_input(VBAT_PIN, NRF_GPIO_PIN_NOPULL);
+    nrf_gpio_cfg_input(SHUT_DOWN_PIN, NRF_GPIO_PIN_NOPULL);
+    nrf_gpio_cfg_input(INT9466_PIN, NRF_GPIO_PIN_NOPULL);
+
+    // Config spi cs pin
+
+    uint32_t cs_pins[] = {
+        CS_SW_PIN, CS_MEM_PIN, CS_ADC_PIN, CS_DAC_PIN
+    };
+
+    for (int i = 0; i < COUNTOF(cs_pins); i++)
+    {
+        nrf_gpio_pin_set(cs_pins[i]);
+        nrf_gpio_cfg(
+            cs_pins[i],
+            NRF_GPIO_PIN_DIR_OUTPUT,
+            NRF_GPIO_PIN_INPUT_DISCONNECT,
+            NRF_GPIO_PIN_NOPULL,
+            NRF_GPIO_PIN_H0H1,
+            NRF_GPIO_PIN_NOSENSE);
+    }
+
+    // Config spi mosi pin
+    nrf_gpio_pin_set(SPIM_MOSI_PIN);
+    nrf_gpio_cfg(
+        SPIM_MOSI_PIN,
+        NRF_GPIO_PIN_DIR_OUTPUT,
+        NRF_GPIO_PIN_INPUT_DISCONNECT,
+        NRF_GPIO_PIN_NOPULL,
+        NRF_GPIO_PIN_H0H1,
+        NRF_GPIO_PIN_NOSENSE);
+
+    // Config spi miso pin
+    nrf_gpio_cfg_input(SPIM_MISO_PIN, NRF_GPIO_PIN_NOPULL);
+
+    // Config spi clk pin
+    nrf_gpio_pin_clear(SPIM_CLK_PIN);
+    nrf_gpio_cfg(
+        SPIM_CLK_PIN,
+        NRF_GPIO_PIN_DIR_OUTPUT,
+        NRF_GPIO_PIN_INPUT_DISCONNECT,
+        NRF_GPIO_PIN_NOPULL,
+        NRF_GPIO_PIN_H0H1,
+        NRF_GPIO_PIN_NOSENSE);
+}
+
+// circuit_select combination
+void circuit_selection_vin_0(void)
+{
+    nrf_gpio_pin_clear(Vin1_PIN);
+    nrf_gpio_pin_clear(Vin2_PIN);
+}
+
+void circuit_selection_vin_1(void)
+{
+    nrf_gpio_pin_set(Vin1_PIN);
+    nrf_gpio_pin_clear(Vin2_PIN);
+}
+
+void circuit_selection_vin_2(void)
+{
+    nrf_gpio_pin_clear(Vin1_PIN);
+    nrf_gpio_pin_set(Vin2_PIN);
+}
+
+void circuit_selection_Iin_0(void)
+{
+    nrf_gpio_pin_clear(Iin4_TEST_PIN);
+    nrf_gpio_pin_clear(Iin3_SEL_PIN);
+    nrf_gpio_pin_clear(Iin1_PIN);
+    nrf_gpio_pin_clear(Iin2_PIN);
+    nrf_gpio_pin_clear(Iin3_PIN);
+}
+
+void circuit_selection_Iin_1(void)
+{
+    nrf_gpio_pin_clear(Iin4_TEST_PIN);
+    nrf_gpio_pin_clear(Iin3_SEL_PIN);
+    nrf_gpio_pin_set(Iin1_PIN);
+    nrf_gpio_pin_clear(Iin2_PIN);
+    nrf_gpio_pin_clear(Iin3_PIN);
+}
+
+void circuit_selection_Iin_2(void)
+{
+    nrf_gpio_pin_clear(Iin4_TEST_PIN);
+    nrf_gpio_pin_clear(Iin3_SEL_PIN);
+    nrf_gpio_pin_clear(Iin1_PIN);
+    nrf_gpio_pin_set(Iin2_PIN);
+    nrf_gpio_pin_clear(Iin3_PIN);
+}
+
+void circuit_selection_Iin_3(void)
+{
+    nrf_gpio_pin_clear(Iin4_TEST_PIN);
+    nrf_gpio_pin_set(Iin3_SEL_PIN);
+    nrf_gpio_pin_clear(Iin1_PIN);
+    nrf_gpio_pin_clear(Iin2_PIN);
+    nrf_gpio_pin_set(Iin3_PIN);
+}
+
+void circuit_selection_Iin_4(void)
+{
+    nrf_gpio_pin_set(Iin4_TEST_PIN);
+    nrf_gpio_pin_clear(Iin3_SEL_PIN);
+    nrf_gpio_pin_clear(Iin1_PIN);
+    nrf_gpio_pin_clear(Iin2_PIN);
+    nrf_gpio_pin_clear(Iin3_PIN);
+}
+
+void circuit_selection_dac_coarse_tune_c(void)
+{
+    sw_t sw;
+    uint32_t sw_cnt;
+
+    sw_count(&sw_cnt);
+    sw_read(&sw);
+    sw.val = 0b10000000;
+    NRF_LOG_INFO("sw.val= %08X", sw.val);
+    NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
+    NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
+    sw_write(sw);
+
+    nrf_gpio_pin_set(Vout_FB_PIN);
+    nrf_gpio_pin_clear(Vout_IN_PIN);
+}
+
+void circuit_selection_dac_fine_tune_f0(void)
+{
+    sw_t sw;
+    uint32_t sw_cnt;
+
+    sw_count(&sw_cnt);
+    sw_read(&sw);
+    sw.val = 0b10000100;
+    NRF_LOG_INFO("sw.val= %08X", sw.val);
+    NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
+    NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
+    sw_write(sw);
+
+    nrf_gpio_pin_set(Vout_FB_PIN);
+    nrf_gpio_pin_clear(Vout_IN_PIN);
+}
+
+void circuit_selection_dac_fine_tune_f1(void)
+{
+    sw_t sw;
+    uint32_t sw_cnt;
+
+    sw_count(&sw_cnt);
+    sw_read(&sw);
+    sw.val = 0b10001000;
+    NRF_LOG_INFO("sw.val= %08X", sw.val);
+    NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
+    NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
+    sw_write(sw);
+
+    nrf_gpio_pin_set(Vout_FB_PIN);
+    nrf_gpio_pin_clear(Vout_IN_PIN);
+}
+
+void circuit_selection_dac_fine_tune_f2(void)
+{
+    sw_t sw;
+    uint32_t sw_cnt;
+
+    sw_count(&sw_cnt);
+    sw_read(&sw);
+    sw.val = 0b10000000;
+    NRF_LOG_INFO("sw.val= %08X", sw.val);
+    NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
+    NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
+    sw_write(sw);
+
+    nrf_gpio_pin_set(Vout_FB_PIN);
+    nrf_gpio_pin_clear(Vout_IN_PIN);
+}
+
+void circuit_selection_dac_circuit_open(void)
+{
+    sw_t sw;
+    uint32_t sw_cnt;
+
+    sw_count(&sw_cnt);
+    sw_read(&sw);
+    sw.sw4 = 0;
+    sw.sw5 = 0;
+    sw.sw6 = 0;
+    sw.sw7 = 0;
+    NRF_LOG_INFO("sw.val= %08X", sw.val);
+    NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
+    NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
+    sw_write(sw);
+}
+
+void circuit_selection_cv3_config(void)
+{
+    nrf_gpio_pin_clear(Vout_FB_PIN);
+    nrf_gpio_pin_set(Vout_IN_PIN);
+    nrf_gpio_pin_clear(Iin4_TEST_PIN);
+    nrf_gpio_pin_clear(Iin3_SEL_PIN);
+    nrf_gpio_pin_clear(Iin1_PIN);
+    nrf_gpio_pin_clear(Iin2_PIN);
+    nrf_gpio_pin_clear(Iin3_PIN);
+    nrf_gpio_pin_set(CV_CTRL_PIN);
+}
+
+void circuit_selection_cc_config(void)
+{
+    nrf_gpio_pin_clear(Vout_FB_PIN);
+    nrf_gpio_pin_set(Vout_IN_PIN);
+    nrf_gpio_pin_clear(Iin4_TEST_PIN);
+    nrf_gpio_pin_clear(Iin3_SEL_PIN);
+    nrf_gpio_pin_clear(Iin1_PIN);
+    nrf_gpio_pin_clear(Iin2_PIN);
+    nrf_gpio_pin_clear(Iin3_PIN);
+    nrf_gpio_pin_clear(CV_CTRL_PIN);
+}
+
+//==========================================================
+// i2c
+//==========================================================
+static const nrf_drv_twi_t twi0    = NRF_DRV_TWI_INSTANCE(0);
+static SemaphoreHandle_t i2c_sem   = NULL;
+static SemaphoreHandle_t i2c_mutex = NULL;
+static QueueHandle_t i2c_evt_queue = NULL;
+
+static void nrf_drv_twi_evt_handler(nrf_drv_twi_evt_t const *p_event, void *p_context)
+{
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+    xQueueSendFromISR(i2c_evt_queue, p_event, &xHigherPriorityTaskWoken);
+    portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+}
+
+void twi_init(void)
+{
+    ret_code_t err_code;
+
+    i2c_sem       = xSemaphoreCreateBinary();
+    i2c_mutex     = xSemaphoreCreateMutex();
+    i2c_evt_queue = xQueueCreate(2, sizeof(nrf_drv_twi_evt_t));
+
+    const nrf_drv_twi_config_t twi0_config = {
+        .scl                = I2C0_SCL,
+        .sda                = I2C0_SDA,
+        .frequency          = NRF_DRV_TWI_FREQ_100K,
+        .interrupt_priority = APP_IRQ_PRIORITY_HIGH,
+        .clear_bus_init     = true
+    };
+
+    err_code = nrf_drv_twi_init(&twi0, &twi0_config, nrf_drv_twi_evt_handler, NULL);
+    APP_ERROR_CHECK(err_code);
+
+    nrf_drv_twi_enable(&twi0);
+}
+
+void twi0_write_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t data_len)
+{
+    xSemaphoreTake(i2c_mutex, portMAX_DELAY);
+
+    static uint8_t i2c_buf[255];
+    static nrf_drv_twi_evt_t evt;
+    ret_code_t err_code;
+
+    memcpy(i2c_buf, &reg_addr, sizeof(reg_addr));
+    memcpy(i2c_buf + sizeof(reg_addr), data, data_len);
+
+    err_code = nrf_drv_twi_tx(&twi0, slave_addr, i2c_buf, data_len + 1, false);
+    APP_ERROR_CHECK(err_code);
+
+    xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
+
+    switch (evt.type)
+    {
+        /* Transfer completed event. */
+        case NRF_DRV_TWI_EVT_DONE:
+            // TODO...
+            break;
+        /* Error event: NACK received after sending the address. */
+        case NRF_DRV_TWI_EVT_ADDRESS_NACK:
+            // TODO...
+            __BKPT(255);
+            break;
+        /* Error event: NACK received after sending a data byte. */
+        case NRF_DRV_TWI_EVT_DATA_NACK:
+            // TODO...
+            __BKPT(255);
+            break;
+        default:
+            __BKPT(255);
+            break;
+    }
+
+    xSemaphoreGive(i2c_mutex);
+
+    NRF_LOG_INFO("i2c(W): slave_addr=0x%02x", slave_addr);
+    NRF_LOG_HEXDUMP_INFO(i2c_buf, data_len + 1);
+}
+
+void twi0_read_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *p_rx_buf, uint8_t rx_buffer_length)
+{
+    xSemaphoreTake(i2c_mutex, portMAX_DELAY);
+
+    nrf_drv_twi_evt_t evt;
+    ret_code_t err_code;
+
+    err_code = nrf_drv_twi_tx(&twi0, slave_addr, &reg_addr, sizeof(reg_addr), false);
+    APP_ERROR_CHECK(err_code);
+    xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
+
+    switch (evt.type)
+    {
+        /* Transfer completed event. */
+        case NRF_DRV_TWI_EVT_DONE:
+            // TODO...
+            break;
+        /* Error event: NACK received after sending the address. */
+        case NRF_DRV_TWI_EVT_ADDRESS_NACK:
+            // TODO...
+            __BKPT(255);
+            break;
+        /* Error event: NACK received after sending a data byte. */
+        case NRF_DRV_TWI_EVT_DATA_NACK:
+            // TODO...
+            __BKPT(255);
+            break;
+        default:
+            break;
+    }
+
+    err_code = nrf_drv_twi_rx(&twi0, slave_addr, p_rx_buf, rx_buffer_length);
+    APP_ERROR_CHECK(err_code);
+    xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
+
+    switch (evt.type)
+    {
+        /* Transfer completed event. */
+        case NRF_DRV_TWI_EVT_DONE:
+            // TODO...
+            break;
+        /* Error event: NACK received after sending the address. */
+        case NRF_DRV_TWI_EVT_ADDRESS_NACK:
+            // TODO...
+            __BKPT(255);
+            break;
+        /* Error event: NACK received after sending a data byte. */
+        case NRF_DRV_TWI_EVT_DATA_NACK:
+            // TODO...
+            __BKPT(255);
+            break;
+        default:
+            break;
+    }
+
+    xSemaphoreGive(i2c_mutex);
+
+    NRF_LOG_INFO("i2c(R): slave_addr=0x%02x reg_addr=0x%02x", slave_addr, reg_addr);
+    NRF_LOG_HEXDUMP_INFO(p_rx_buf, rx_buffer_length);
+}
+
+//==========================================================
+// spi
+//==========================================================
+static const nrf_drv_spi_t spim1   = NRF_DRV_SPI_INSTANCE(1); /**< SPI instance. */
+static SemaphoreHandle_t spim1_sem = NULL;
+
+static void nrf_drv_spim1_evt_handler(nrf_drv_spi_evt_t const *p_event, void *p_context)
+{
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+    switch (p_event->type)
+    {
+        case NRF_DRV_SPI_EVENT_DONE:
+            xSemaphoreGiveFromISR(spim1_sem, &xHigherPriorityTaskWoken);
+            portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+            break;
+        default:
+            break;
+    }
+}
+
+void spi_init(void)
+{
+    spim1_sem = xSemaphoreCreateBinary();
+
+    nrf_drv_spi_config_t spi1_config = NRF_DRV_SPI_DEFAULT_CONFIG;
+    spi1_config.ss_pin               = NRF_DRV_SPI_PIN_NOT_USED;
+    spi1_config.miso_pin             = NRF_DRV_SPI_PIN_NOT_USED;
+    spi1_config.mosi_pin             = SPI1_MOSI_PIN;
+    spi1_config.sck_pin              = SPI1_CLK_PIN;
+    spi1_config.mode                 = NRF_DRV_SPI_MODE_0;
+    spi1_config.frequency            = NRF_DRV_SPI_FREQ_8M;
+    APP_ERROR_CHECK(nrf_drv_spi_init(&spim1, &spi1_config, nrf_drv_spim1_evt_handler, NULL));
+
+    // Config spi module
+    NRF_SPIM3->ENABLE          = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
+    NRF_SPIM3->ORC             = 0x00000000;
+    NRF_SPIM3->FREQUENCY       = SPIM_FREQUENCY_FREQUENCY_M32;
+    NRF_SPIM3->CSNPOL          = SPIM_CSNPOL_CSNPOL_LOW;
+    NRF_SPIM3->IFTIMING.CSNDUR = 8;
+    NRF_SPIM3->PSEL.SCK        = SPIM_CLK_PIN;
+    NRF_SPIM3->PSEL.MOSI       = SPIM_MOSI_PIN;
+    NRF_SPIM3->PSEL.MISO       = SPIM_MISO_PIN;
+    NRF_SPIM3->ENABLE          = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+}
+
+void spi1_write(uint8_t *p_tx_buffer, uint16_t tx_buffer_length)
+{
+    APP_ERROR_CHECK(nrf_drv_spi_transfer(&spim1, p_tx_buffer, tx_buffer_length, NULL, 0));
+    xSemaphoreTake(spim1_sem, portMAX_DELAY);
+}
+
+void spim_xfer(uint32_t cs_pin, nrf_spim_mode_t spi_mode, uint8_t *p_tx_buffer, uint16_t tx_buffer_length, uint8_t *p_rx_buf, uint16_t rx_buffer_length)
+{
+    __disable_irq();
+
+    /* set spi mode and order  */
+    NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
+    switch (spi_mode)
+    {
+        default:
+        case NRF_SPIM_MODE_0:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
+            break;
+
+        case NRF_SPIM_MODE_1:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
+            break;
+
+        case NRF_SPIM_MODE_2:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
+            break;
+
+        case NRF_SPIM_MODE_3:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
+            break;
+    }
+    NRF_SPIM3->PSEL.CSN = cs_pin;
+    NRF_SPIM3->ENABLE   = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+
+    if (p_tx_buffer != NULL)
+    {
+        NRF_SPIM3->TXD.PTR    = (uint32_t)p_tx_buffer;
+        NRF_SPIM3->TXD.MAXCNT = tx_buffer_length;
+    }
+    else
+    {
+        NRF_SPIM3->TXD.MAXCNT = 0;
+    }
+    if (p_rx_buf != NULL)
+    {
+        NRF_SPIM3->RXD.PTR    = (uint32_t)p_rx_buf;
+        NRF_SPIM3->RXD.MAXCNT = rx_buffer_length;
+    }
+    else
+    {
+        NRF_SPIM3->RXD.MAXCNT = 0;
+    }
+
+    /* workaround for ADC acquisition time */
+    nrf_gpio_pin_set(CS_ADC_PIN);
+
+    NRF_SPIM3->EVENTS_END  = 0;
+    NRF_SPIM3->TASKS_START = 1;
+    do {
+    } while (NRF_SPIM3->EVENTS_END == 0);
+
+    NRF_SPIM3->ENABLE   = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
+    NRF_SPIM3->PSEL.CSN = 0xFFFFFFFF;
+    NRF_SPIM3->ENABLE   = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+
+    /* workaround for ADC acquisition time */
+    nrf_gpio_pin_clear(CS_ADC_PIN);
+
+    __enable_irq();
+}
+
+//==========================================================
+// timer
+//==========================================================
+
+#if (DEF_DAC_DRV_ENABLED)
+
+#define ELITE_DAC_TMR NRF_TIMER2
+
+static void (*dac_tmr_cb)(void *p_arg) = NULL;
+static void *dac_tmr_p_arg             = NULL;
+
+void TIMER2_IRQHandler(void)
+{
+    if (ELITE_DAC_TMR->EVENTS_COMPARE[0])
+    {
+        ELITE_DAC_TMR->EVENTS_COMPARE[0] = 0;
+        if (dac_tmr_cb)
+        {
+            dac_tmr_cb(dac_tmr_p_arg);
+        }
+        return;
+    }
+}
+void edc20_dac_tim_start(uint32_t period, void (*callback)(void *p_arg), void *p_arg)
+{
+    NRF_LOG_INFO("%s()", __FUNCTION__);
+
+    __disable_irq();
+
+    sd_nvic_DisableIRQ(TIMER2_IRQn);
+    sd_nvic_ClearPendingIRQ(TIMER2_IRQn);
+    ELITE_DAC_TMR->SHORTS     = 0;
+    ELITE_DAC_TMR->TASKS_STOP = 1;
+
+    dac_tmr_p_arg = p_arg;
+    dac_tmr_cb    = callback;
+
+    ELITE_DAC_TMR->PRESCALER = NRF_TIMER_FREQ_1MHz;
+    ELITE_DAC_TMR->MODE      = NRF_TIMER_MODE_TIMER;
+    ELITE_DAC_TMR->BITMODE   = NRF_TIMER_BIT_WIDTH_32;
+    ELITE_DAC_TMR->INTENSET  = NRF_TIMER_INT_COMPARE0_MASK;
+    ELITE_DAC_TMR->CC[0]     = period;
+    ELITE_DAC_TMR->SHORTS    = NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK;
+    sd_nvic_SetPriority(TIMER2_IRQn, _PRIO_APP_HIGH);
+    sd_nvic_EnableIRQ(TIMER2_IRQn);
+
+    ELITE_DAC_TMR->TASKS_CLEAR = 1;
+    ELITE_DAC_TMR->TASKS_START = 1;
+
+    __enable_irq();
+}
+
+void edc20_dac_tim_stop(void)
+{
+    NRF_LOG_INFO("%s()", __FUNCTION__);
+
+    __disable_irq();
+
+    dac_tmr_cb    = NULL;
+    dac_tmr_p_arg = NULL;
+
+    sd_nvic_DisableIRQ(TIMER2_IRQn);
+    sd_nvic_ClearPendingIRQ(TIMER2_IRQn);
+    ELITE_DAC_TMR->TASKS_STOP = 1;
+    ELITE_DAC_TMR->SHORTS     = 0;
+
+    __enable_irq();
+}
+
+#endif /* ! DEF_DAC_DRV_ENABLED */
+
+#if (DEF_ADC_DRV_ENABLED)
+
+#define ELITE_ADC_TMR NRF_TIMER3
+
+void TIMER3_IRQHandler(void)
+{
+    if (ELITE_ADC_TMR->EVENTS_COMPARE[0])
+    {
+        ELITE_ADC_TMR->EVENTS_COMPARE[0] = 0;
+
+        float mv;
+        extern int adc_read_milivolt(uint32_t channel, float *mv);
+        adc_read_milivolt(2, &mv);
+
+        float v = mv / 1000.0 - 5;
+
+#if (DEF_RTT_JSCOP_ENABLED)
+        extern void j_scope_update(float f);
+        j_scope_update(v * 5);
+#endif
+
+        return;
+    }
+
+    if (ELITE_ADC_TMR->EVENTS_COMPARE[1])
+    {
+        ELITE_ADC_TMR->EVENTS_COMPARE[1] = 0;
+        int32_t val;
+        adc_read(1, &val);
+        return;
+    }
+
+    if (ELITE_ADC_TMR->EVENTS_COMPARE[2])
+    {
+        ELITE_ADC_TMR->EVENTS_COMPARE[2] = 0;
+        int32_t val;
+        adc_read(2, &val);
+        return;
+    }
+}
+
+void edc20_adc_tim_start(elite_dac_config_t *p_config)
+{
+    NRF_LOG_INFO("%s()", __FUNCTION__);
+
+    /*
+    ADC Sample rate 10KHz
+    */
+    ELITE_ADC_TMR->PRESCALER = NRF_TIMER_FREQ_1MHz;
+    ELITE_ADC_TMR->MODE      = NRF_TIMER_MODE_TIMER;
+    ELITE_ADC_TMR->BITMODE   = NRF_TIMER_BIT_WIDTH_32;
+    ELITE_ADC_TMR->INTENSET  = NRF_TIMER_INT_COMPARE0_MASK;
+    ELITE_ADC_TMR->CC[0]     = 1000;
+    ELITE_ADC_TMR->SHORTS    = NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK;
+    sd_nvic_SetPriority(TIMER3_IRQn, _PRIO_APP_HIGH);
+    sd_nvic_EnableIRQ(TIMER3_IRQn);
+}
+
+void edc20_adc_tim_stop(void)
+{
+    NRF_LOG_INFO("%s()", __FUNCTION__);
+}
+
+#endif /* ! DEF_ADC_DRV_ENABLED */
+
+void edc20_io_init(void)
+{
+    gpio_init();
+    twi_init();
+    spi_init();
+}
+
+void edc20_io_power_off(void)
+{
+    nrf_gpio_pin_clear(OFF_PIN);
+    nrf_gpio_pin_clear(POWER_12V_EN_PIN);
+    nrf_gpio_pin_clear(POWER_5V_EN_PIN);
+    for (;;)
+    {
+        __DSB();
+        __ISB();
+    }
+}
+
+void edc20_io_power_on(void)
+{
+    uint32_t cnt = 0;
+    for (int i = 0; i < 1000 / 50; i++)
+    {
+        vTaskDelay(pdMS_TO_TICKS(50));
+        if (nrf_gpio_pin_read(SHUT_DOWN_PIN))
+        {
+            cnt++;
+            if (cnt == 2)
+            {
+                edc20_io_power_off();
+            }
+        }
+    }
+}
+
+#endif /* ! DEF_ELITE_MODEL */

app/src/elite_mmm_v1_0.c

@@ -0,0 +1,271 @@
+#include "app_config.h"
+
+#include "elite_mmm_v1_0.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_MMM_V1_0)
+
+#include "nrf_gpio.h"
+#include "nrf_log.h"
+
+// RIS (real instruction)
+#define DEV_MODE            0xFF // Develop Mode
+
+// VIS (virtual instruction)
+#define VIS_RST             0xF0
+#define VIS_DEVICE_SHINY    0x10
+
+// CIS (control instruction)
+#define CIS_VERSION         0x40
+#define CIS_VOLT            0x10
+#define CIS_TEMPERATURE     0x80
+#define CIS_CALI            0x30
+
+#define VERSION_DATE_YEAR   25
+#define VERSION_DATE_MONTH  6
+#define VERSION_DATE_DAY    4
+#define VERSION_DATE_HOUR   16
+#define VERSION_DATE_MINUTE 44
+static void cis_version(uint8_t *ins, uint16_t size)
+{
+    NRF_LOG_INFO("%s", __FUNCTION__);
+    uint8_t cis_ver[] = {
+        CIS_VERSION,
+        VERSION_DATE_YEAR,
+        VERSION_DATE_MONTH,
+        VERSION_DATE_DAY,
+        VERSION_DATE_HOUR,
+        VERSION_DATE_MINUTE,
+    };
+    extern ret_code_t le_data_update(uint8_t *p_value, uint16_t len);
+    le_data_update((void *)cis_ver, sizeof(cis_ver));
+}
+
+static void vis_rst(uint8_t *ins, uint16_t size)
+{
+    NRF_LOG_INFO("%s", __FUNCTION__);
+}
+
+#define UNDEF_GPIO 0xFFFFFFFF
+
+// The GPIO corresponding to the pin
+const uint32_t pin_to_gpio_table[] = {
+    [6]  = NRF_GPIO_PIN_MAP(0, 22),
+    [8]  = NRF_GPIO_PIN_MAP(0, 25),
+    [9]  = NRF_GPIO_PIN_MAP(0, 19),
+    [10] = NRF_GPIO_PIN_MAP(0, 21),
+    [11] = NRF_GPIO_PIN_MAP(1, 00),
+    [12] = NRF_GPIO_PIN_MAP(0, 18),
+    [13] = NRF_GPIO_PIN_MAP(0, 17),
+    [14] = NRF_GPIO_PIN_MAP(0, 20),
+    [16] = NRF_GPIO_PIN_MAP(0, 14),
+    [17] = NRF_GPIO_PIN_MAP(0, 13),
+    [18] = NRF_GPIO_PIN_MAP(0, 11),
+    [20] = NRF_GPIO_PIN_MAP(0, 15),
+    [25] = NRF_GPIO_PIN_MAP(1, 8),
+    [26] = NRF_GPIO_PIN_MAP(0, 12),
+    [27] = NRF_GPIO_PIN_MAP(0, 7),
+    [28] = NRF_GPIO_PIN_MAP(1, 9),
+    [29] = NRF_GPIO_PIN_MAP(0, 8),
+    [30] = NRF_GPIO_PIN_MAP(0, 6),
+    [31] = NRF_GPIO_PIN_MAP(0, 5),
+    [32] = NRF_GPIO_PIN_MAP(0, 27),
+    [33] = NRF_GPIO_PIN_MAP(0, 26),
+    [34] = NRF_GPIO_PIN_MAP(0, 4),
+    [36] = NRF_GPIO_PIN_MAP(0, 1),
+    [37] = NRF_GPIO_PIN_MAP(0, 29),
+    [38] = NRF_GPIO_PIN_MAP(0, 0),
+    [39] = NRF_GPIO_PIN_MAP(0, 31),
+    [40] = NRF_GPIO_PIN_MAP(1, 15),
+    [41] = NRF_GPIO_PIN_MAP(0, 2),
+    [42] = NRF_GPIO_PIN_MAP(0, 30),
+    [43] = NRF_GPIO_PIN_MAP(0, 28),
+    [44] = NRF_GPIO_PIN_MAP(1, 12),
+    [45] = NRF_GPIO_PIN_MAP(1, 14),
+    [46] = NRF_GPIO_PIN_MAP(0, 3),
+    [47] = NRF_GPIO_PIN_MAP(1, 13),
+    [48] = NRF_GPIO_PIN_MAP(1, 3),
+    [49] = NRF_GPIO_PIN_MAP(1, 10),
+    [50] = NRF_GPIO_PIN_MAP(1, 6),
+    [51] = NRF_GPIO_PIN_MAP(1, 11),
+    [52] = NRF_GPIO_PIN_MAP(0, 10),
+    [53] = NRF_GPIO_PIN_MAP(0, 9),
+    [59] = NRF_GPIO_PIN_MAP(1, 2),
+    [60] = NRF_GPIO_PIN_MAP(0, 24),
+    [61] = NRF_GPIO_PIN_MAP(0, 23),
+    [62] = NRF_GPIO_PIN_MAP(0, 16),
+};
+
+static uint32_t bmd380pins_convert_to_gpio(uint32_t pin)
+{
+    uint32_t gpio;
+
+    switch (pin)
+    {
+        case 6:
+        case 8:
+        case 9:
+        case 10:
+        case 11:
+        case 12:
+        case 13:
+        case 14:
+        case 16:
+        case 17:
+        case 18:
+        case 20:
+        case 25:
+        case 26:
+        case 27:
+        case 28:
+        case 29:
+        case 30:
+        case 31:
+        case 32:
+        case 33:
+        case 34:
+        case 36:
+        case 37:
+        case 38:
+        case 39:
+        case 40:
+        case 41:
+        case 42:
+        case 43:
+        case 44:
+        case 45:
+        case 46:
+        case 47:
+        case 48:
+        case 49:
+        case 50:
+        case 51:
+        case 52:
+        case 53:
+        case 59:
+        case 60:
+        case 61:
+        case 62:
+            gpio = pin_to_gpio_table[pin];
+            break;
+        default:
+            gpio = UNDEF_GPIO;
+            NRF_LOG_INFO("UNDEF_GPIO: pin %d can't convert to gpio number", pin);
+            break;
+    }
+
+    return gpio;
+}
+
+static void set_bmd380_pin_signal(uint32_t pin, uint32_t high_low)
+{
+    uint32_t gpio = bmd380pins_convert_to_gpio(pin);
+
+    if (gpio != UNDEF_GPIO)
+    {
+        nrf_gpio_cfg_output(gpio);
+        nrf_gpio_pin_write(gpio, high_low);
+        NRF_LOG_INFO("set pin %d (gpio %d) = %d", pin, gpio, high_low);
+    }
+}
+
+/*
+    dev_mode_gpio_function
+    (1)0x3000FFA000ppss
+            -func: set_bmd380_pin_signal
+            -pp: pin number     06h-3Fh
+                06h: P0.22_GPIO
+                08h: P0.25_GPIO
+                ......
+                3Eh: P0.16_GPIO
+            -ss: signal         00h-01h
+                00h: low
+                01h: high
+
+    (2)0x3000FFA001ss
+        -func: set_bmd380 all pin signal high/low
+        -ss: signal         00h-01h
+            00h: low
+            01h: high
+*/
+void dev_mode_gpio_function(uint8_t *ins)
+{
+    struct __PACKED
+    {
+        uint8_t id     : 4;
+        uint8_t        : 4;
+        uint16_t magic : 16;
+        uint8_t dev_opcode;
+        uint8_t gpio_function_opcode;
+        uint8_t param[];
+    } *p_ins = (void *)ins;
+
+    switch (p_ins->gpio_function_opcode)
+    {
+        case 0x00: {
+            uint32_t pin      = p_ins->param[0];
+            uint32_t high_low = p_ins->param[1];
+            set_bmd380_pin_signal(pin, high_low);
+            break;
+        }
+
+        case 0x01: {
+            uint32_t high_low    = p_ins->param[0];
+            uint32_t set_pin[44] = { 6, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 59, 60, 61, 62 };
+
+            for (int i = 0; i < sizeof(set_pin) / sizeof(set_pin[0]); i++)
+            {
+                set_bmd380_pin_signal(set_pin[i], high_low);
+            }
+            break;
+        }
+    }
+}
+
+#define MAGIC_NUM 0xFF00
+static void dev_mode(uint8_t *ins, uint16_t size)
+{
+    NRF_LOG_INFO("%s", __FUNCTION__);
+    struct __PACKED
+    {
+        uint8_t id     : 4;
+        uint8_t        : 4;
+        uint16_t magic : 16;
+        uint8_t opcode;
+        uint8_t param[];
+    } *p_ins = (void *)ins;
+
+    if (p_ins->magic != MAGIC_NUM)
+    {
+        return;
+    }
+
+    // TODO...
+    switch (p_ins->opcode)
+    {
+        case 0xA0:
+            dev_mode_gpio_function(ins);
+            break;
+
+        default:
+            break;
+    }
+}
+
+const elite_instance_t mmm_elite_instance = {
+    .cis_func = {
+                 [CIS_VERSION] = cis_version,
+                 },
+    .vis_func = {
+                 [VIS_RST] = vis_rst,
+                 },
+    .ris_func = {
+                 [DEV_MODE] = dev_mode,
+                 }
+};
+
+const elite_instance_t *mmm_init(void)
+{
+    return &mmm_elite_instance;
+}
+
+#endif /* !DEF_ELITE_MODEL */

app/src/elite_pel_v2_0_io.c

@@ -0,0 +1,397 @@
+#include "elite_board.h"
+
+#include "nrf_gpio.h"
+#include "nrf_gpiote.h"
+
+#include "nrf_spim.h"
+#include "nrf_timer.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+#include "SEGGER_RTT.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+
+pel_hw_t pel_hw = {
+    .pulse_tmr    = NRF_TIMER3,
+    .pulse_irq_n  = TIMER3_IRQn,
+    .pulse_cnt    = 0,
+    .adc.channels = {
+                     [OUTPUT_R1_IDX] = OUTPUT_R1_CHANNEL,
+                     [OUTPUT_R2_IDX] = OUTPUT_R2_CHANNEL,
+                     [OUTPUT_VO_IDX] = OUTPUT_VO_CHANNEL,
+                     [OUTPUT_VC_IDX] = OUTPUT_VC_CHANNEL,
+                     [OUTPUT_VE_IDX] = OUTPUT_VE_CHANNEL },
+    .adc.gain        = NRF_SAADC_GAIN1_6,
+    .adc.smaple_time = NRF_SAADC_ACQTIME_3US
+};
+
+void spim_xfer(uint32_t cs_pin,
+               nrf_spim_mode_t spi_mode,
+               uint8_t *p_tx_buffer,
+               uint16_t tx_buffer_length,
+               uint8_t *p_rx_buf,
+               uint16_t rx_buffer_length)
+{
+    __disable_irq();
+
+    NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
+
+    switch (spi_mode)
+    {
+        default:
+        case NRF_SPIM_MODE_0:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
+            break;
+
+        case NRF_SPIM_MODE_1:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
+            break;
+
+        case NRF_SPIM_MODE_2:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
+            break;
+
+        case NRF_SPIM_MODE_3:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
+            break;
+    }
+
+    NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+
+    NRF_SPIM3->TXD.MAXCNT = tx_buffer_length;
+    NRF_SPIM3->TXD.PTR    = (uint32_t)p_tx_buffer;
+
+    NRF_SPIM3->RXD.MAXCNT = rx_buffer_length;
+    NRF_SPIM3->RXD.PTR    = (uint32_t)p_rx_buf;
+
+    nrf_gpio_pin_clear(cs_pin);
+
+    NRF_SPIM3->EVENTS_END  = 0;
+    NRF_SPIM3->TASKS_START = 1;
+    do {
+    } while (NRF_SPIM3->EVENTS_END == 0);
+
+    nrf_gpio_pin_set(cs_pin);
+
+    __enable_irq();
+}
+
+#define MIN_PULSE_WIDTH 2
+#define MIN_PULSE_IDLE  2
+#define MAX_PULSE_WIDTH INT16_MAX
+#define MAX_PULSE_IDLE  INT16_MAX
+
+static void pel_saadc_init(pel_adc_t *p_adc)
+{
+    /* stop ssadc */
+    NRF_SAADC->EVENTS_STOPPED = 0;
+    NRF_SAADC->TASKS_STOP     = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_STOPPED == 0);
+
+    /* disable ssadc */
+    NRF_SAADC->ENABLE = 0;
+
+    /*
+        ref: p.381, nrf52840_PS_v1.1.pdf
+        Note: Oversampling should only be used when a single input channel is enabled, as averaging is
+        performed over all enabled channels.
+    */
+    NRF_SAADC->OVERSAMPLE = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass;
+    NRF_SAADC->RESOLUTION = SAADC_RESOLUTION_VAL_14bit;
+    /* config analog inputs */
+    for (uint32_t i = 0; i < COUNTOF(NRF_SAADC->CH); i++)
+    {
+        if (i < COUNTOF(p_adc->channels))
+        {
+            NRF_SAADC->CH[i].PSELP = NRF_SAADC_INPUT_AIN0 + p_adc->channels[i];
+            NRF_SAADC->CH[i].PSELN = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].CONFIG =
+                (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESP_Pos) |
+                (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESN_Pos) |
+                (p_adc->gain << SAADC_CH_CONFIG_GAIN_Pos) |
+                (NRF_SAADC_REFERENCE_INTERNAL << SAADC_CH_CONFIG_REFSEL_Pos) |
+                (p_adc->smaple_time << SAADC_CH_CONFIG_TACQ_Pos) |
+                (NRF_SAADC_MODE_SINGLE_ENDED << SAADC_CH_CONFIG_MODE_Pos) |
+                (NRF_SAADC_BURST_DISABLED << SAADC_CH_CONFIG_BURST_Pos);
+        }
+        else
+        {
+            NRF_SAADC->CH[i].PSELP  = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].PSELN  = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].CONFIG = 0;
+        }
+    }
+    /* enable ssadc */
+    NRF_SAADC->INTENSET      = NRF_SAADC_INT_STARTED | NRF_SAADC_INT_END;
+    NRF_SAADC->ENABLE        = 1;
+    NRF_SAADC->RESULT.PTR    = (uint32_t)p_adc->results;
+    NRF_SAADC->RESULT.MAXCNT = COUNTOF(p_adc->results);
+}
+
+void TIMER3_IRQHandler(void)
+{
+    if (pel_hw.pulse_tmr->EVENTS_COMPARE[0])
+    {
+        pel_hw.pulse_tmr->EVENTS_COMPARE[0] = 0;
+
+        pel_hw.pulse_is_running = 1;
+
+        if (pel_hw.pulse_cnt)
+        {
+            pel_hw.pulse_cnt--;
+        }
+    }
+}
+
+void SAADC_IRQHandler(void)
+{
+    if (NRF_SAADC->EVENTS_STARTED)
+    {
+        NRF_SAADC->EVENTS_STARTED = 0;
+        if (pel_hw.pulse_cnt == 0)
+        {
+            pel_hw.pulse_tmr->TASKS_STOP = 1;
+        }
+        return;
+    }
+
+    if (NRF_SAADC->EVENTS_END)
+    {
+        NRF_SAADC->EVENTS_END    = 0;
+        NRF_SAADC->RESULT.PTR    = (uint32_t)pel_hw.adc.results;
+        NRF_SAADC->RESULT.MAXCNT = COUNTOF(pel_hw.adc.results);
+        pel_hw.pulse_is_running  = 0;
+        if (pel_hw.adc.convt_new_arrival_cb)
+        {
+            pel_hw.adc.convt_new_arrival_cb();
+        }
+    }
+}
+
+void pel_pulse_gen_init(pel_config_t cfg)
+{
+    pel_hw.pulse_tmr->TASKS_STOP = 1;
+    sd_nvic_DisableIRQ(pel_hw.pulse_irq_n);
+    sd_nvic_ClearPendingIRQ(pel_hw.pulse_irq_n);
+    sd_nvic_DisableIRQ(SAADC_IRQn);
+    sd_nvic_ClearPendingIRQ(SAADC_IRQn);
+
+    pel_hw.pulse_cnt                = cfg.pulse_cnt;
+    pel_hw.adc.gain                 = cfg.gain;
+    pel_hw.adc.smaple_time          = cfg.smaple_time;
+    pel_hw.adc.convt_new_arrival_cb = cfg.convt_new_arrival_cb;
+    pel_saadc_init(&pel_hw.adc);
+
+    // disable gpio task
+    for (int i = 0; i < 4; i++)
+    {
+        nrf_gpiote_task_disable(i);
+    }
+
+    // config gpiote task
+    nrf_gpiote_task_configure(0, cfg.anode_pin, NRF_GPIOTE_POLARITY_TOGGLE, (cfg.mode == 0) ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(1, cfg.smaple_r_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(2, cfg.sample_v_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+
+    NRF_PPI->CH[0].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[0];
+    NRF_PPI->CH[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0]; // anode_pin
+    NRF_PPI->CHENSET   = (1 << (0));
+
+    NRF_PPI->CH[1].EEP   = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[1];
+    NRF_PPI->CH[1].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1]; // smaple_r_pin
+    NRF_PPI->FORK[1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2]; // sample_v_pin
+    NRF_PPI->CHENSET     = (1 << (1));
+
+    NRF_PPI->CH[2].EEP   = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[2];
+    NRF_PPI->CH[2].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1];
+    NRF_PPI->FORK[2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2];
+    NRF_PPI->CHENSET     = (1 << (2));
+
+    NRF_PPI->CH[3].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[3];
+    NRF_PPI->CH[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0];
+    NRF_PPI->CHENSET   = (1 << (3));
+
+    NRF_PPI->CH[4].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[4];
+    NRF_PPI->CH[4].TEP = (uint32_t)&NRF_SAADC->TASKS_START;
+    NRF_PPI->CHENSET   = (1 << (4));
+
+    NRF_PPI->CH[5].EEP = (uint32_t)&NRF_SAADC->EVENTS_STARTED;
+    NRF_PPI->CH[5].TEP = (uint32_t)&NRF_SAADC->TASKS_SAMPLE;
+    NRF_PPI->CHENSET   = (1 << (5));
+
+    NRF_PPI->CH[6].EEP = (uint32_t)&NRF_SAADC->EVENTS_END;
+    NRF_PPI->CHENSET   = (1 << (6));
+
+    // enable gpio task
+    for (int i = 0; i < 3; i++)
+    {
+        nrf_gpiote_task_enable(i);
+    }
+
+    if (cfg.test_pin != 0xFFFFFFFF)
+    {
+        nrf_gpiote_task_configure(3, cfg.test_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+        NRF_PPI->FORK[5].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3]; // test_pin
+        NRF_PPI->CH[6].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3];
+        nrf_gpiote_task_enable(3);
+    }
+
+    pel_hw.pulse_tmr->PRESCALER = NRF_TIMER_FREQ_16MHz;
+    pel_hw.pulse_tmr->MODE      = NRF_TIMER_MODE_TIMER;
+    pel_hw.pulse_tmr->BITMODE   = NRF_TIMER_BIT_WIDTH_32;
+    pel_hw.pulse_tmr->CC[0]     = cfg.point_us[0] * 16;
+    pel_hw.pulse_tmr->CC[1]     = pel_hw.pulse_tmr->CC[0] + cfg.point_us[1] * 16;
+    pel_hw.pulse_tmr->CC[2]     = pel_hw.pulse_tmr->CC[1] + cfg.point_us[2] * 16;
+    pel_hw.pulse_tmr->CC[3]     = pel_hw.pulse_tmr->CC[2] + cfg.point_us[3] * 16;
+    pel_hw.pulse_tmr->CC[4]     = pel_hw.pulse_tmr->CC[3] + cfg.point_us[4] * 16 + cfg.adc_timing_shift;
+    pel_hw.pulse_tmr->CC[5]     = pel_hw.pulse_tmr->CC[4];
+    pel_hw.pulse_tmr->SHORTS    = NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK;
+    pel_hw.pulse_tmr->INTENSET  = NRF_TIMER_INT_COMPARE0_MASK;
+
+    sd_nvic_SetPriority(SAADC_IRQn, _PRIO_APP_HIGH);
+    sd_nvic_EnableIRQ(SAADC_IRQn);
+
+    sd_nvic_SetPriority(pel_hw.pulse_irq_n, _PRIO_APP_HIGH);
+    sd_nvic_EnableIRQ(pel_hw.pulse_irq_n);
+}
+
+void pel_pulse_gen_start(void)
+{
+    pel_hw.pulse_tmr->TASKS_START = 1;
+}
+
+void pel_pulse_gen_stop(void)
+{
+    pel_hw.pulse_cnt = 0;
+    do {
+    } while (pel_hw.pulse_is_running == 1);
+    pel_hw.adc.convt_new_arrival_cb = NULL;
+}
+
+#if (DEF_ELITE_DEMO_W_SOFTDEVICE == 1) || (DEF_ELITE_DEMO_WO_SOFTDEVICE == 1)
+static void pel_pulse_gen_demo_task(void *p_arg)
+{
+    pel_config_t pel_cfg = {
+        .anode_pin    = ANODE_PIN,
+        .cathode_pin  = CATHODE_PIN,
+        .smaple_r_pin = SAMPLE_R_PIN,
+        .sample_v_pin = SAMPLE_V_PIN,
+        .test_pin     = TP1_PIN,
+        .mode         = BOARD_IOPx,
+        .point_us     = {
+                         10000,
+                         3,
+                         5,
+                         2,
+                         0,
+                         },
+        .pulse_cnt        = 0xFFFFFFFF,
+        .gain             = NRF_SAADC_GAIN1_6,
+        .smaple_time      = NRF_SAADC_ACQTIME_10US,
+        .adc_timing_shift = 0,
+    };
+
+    pel_pulse_gen_init(pel_cfg);
+
+    pel_pulse_gen_start();
+
+    for (;;)
+    {
+        static uint32_t i = 0;
+        vTaskDelay(pdMS_TO_TICKS(pel_cfg.point_us[0] / 1000));
+        SEGGER_RTT_printf(0, "%d, %d, %d, %d, %d, %d\r\n", i++, pel_hw.adc.results[0], pel_hw.adc.results[1], pel_hw.adc.results[2], pel_hw.adc.results[3], pel_hw.adc.results[4]);
+    }
+}
+
+void pel_pulse_gen_demo(void)
+{
+}
+#endif
+
+void pel20_io_init(void)
+{
+    // common gpio
+    const uint32_t config_output_and_set[] = {
+        INPUT_1_PIN,
+        INPUT_2_PIN,
+        INPUT_3_PIN,
+        INPUT_4_PIN,
+        INPUT_5_PIN,
+        INPUT_6_PIN,
+        INPUT_7_PIN,
+        INPUT_8_PIN,
+        INPUT_9_PIN,
+        INPUT_10_PIN,
+        INPUT_11_PIN,
+        INPUT_12_PIN
+    };
+
+    const uint32_t config_output_and_clear[] = {
+        TP1_PIN,
+        TP2_PIN,
+        SAMPLE_R_PIN,
+        SAMPLE_V_PIN,
+    };
+
+    for (int i = 0; i < ARRAY_SIZE(config_output_and_set); i++)
+    {
+        nrf_gpio_pin_set(config_output_and_set[i]);
+        nrf_gpio_cfg_output(config_output_and_set[i]);
+    }
+
+    for (int i = 0; i < ARRAY_SIZE(config_output_and_clear); i++)
+    {
+        nrf_gpio_pin_clear(config_output_and_clear[i]);
+        nrf_gpio_cfg_output(config_output_and_clear[i]);
+    }
+
+    nrf_gpio_cfg_input(CATHODE_PIN, NRF_GPIO_PIN_NOPULL);
+
+    // specific gpio
+    if (BOARD_IOPx == BOARD_IOPH)
+    {
+        nrf_gpio_pin_clear(ANODE_PIN);
+        nrf_gpio_cfg_output(ANODE_PIN);
+    }
+    else if (BOARD_IOPx == BOARD_IOPL)
+    {
+        nrf_gpio_pin_set(ANODE_PIN);
+        nrf_gpio_cfg_output(ANODE_PIN);
+    }
+
+    // Config spi module
+    nrf_gpio_pin_set(WP_MEM_PIN);
+    nrf_gpio_pin_set(CS_MEM_PIN);
+    nrf_gpio_pin_clear(SPIM_MOSI_PIN);
+    nrf_gpio_pin_clear(SPIM_CLK_PIN);
+    nrf_gpio_cfg_output(WP_MEM_PIN);
+    nrf_gpio_cfg_output(CS_MEM_PIN);
+    nrf_gpio_cfg_output(SPIM_MOSI_PIN);
+    nrf_gpio_cfg_output(SPIM_CLK_PIN);
+    nrf_gpio_cfg_input(SPIM_MISO_PIN, NRF_GPIO_PIN_NOPULL);
+
+    NRF_SPIM3->ENABLE          = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
+    NRF_SPIM3->ORC             = 0x00000000;
+    NRF_SPIM3->FREQUENCY       = SPIM_FREQUENCY_FREQUENCY_M32;
+    NRF_SPIM3->CSNPOL          = SPIM_CSNPOL_CSNPOL_LOW;
+    NRF_SPIM3->IFTIMING.CSNDUR = 8;
+    NRF_SPIM3->PSEL.CSN        = CS_MEM_PIN;
+    NRF_SPIM3->PSEL.SCK        = SPIM_CLK_PIN;
+    NRF_SPIM3->PSEL.MOSI       = SPIM_MOSI_PIN;
+    NRF_SPIM3->PSEL.MISO       = SPIM_MISO_PIN;
+    NRF_SPIM3->ENABLE          = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+}
+
+#endif

app/src/elite_pel_v3_0_io.c

@@ -0,0 +1,411 @@
+#include "app_config.h"
+#include "elite_board.h"
+
+#include "nrf_gpio.h"
+#include "nrf_gpiote.h"
+
+#include "nrf_spim.h"
+#include "nrf_timer.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+#include "SEGGER_RTT.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_PEL_V3_0)
+
+pel_hw_t pel_hw = {
+    .pulse_tmr    = NRF_TIMER3,
+    .pulse_irq_n  = TIMER3_IRQn,
+    .pulse_cnt    = 0,
+    .adc.channels = {
+                     [OUTPUT_ACS37030_REF_IDX] = OUTPUT_ACS37030_VREF_CHANNEL,
+                     [OUTPUT_I_OUT_IDX]        = OUTPUT_I_OUT_CHANNEL,
+                     [OUTPUT_VO_IDX]           = OUTPUT_VO_CHANNEL,
+                     [OUTPUT_VC_IDX]           = OUTPUT_VC_CHANNEL,
+                     [OUTPUT_VE_IDX]           = OUTPUT_VE_CHANNEL },
+    .adc.gain        = NRF_SAADC_GAIN1_6,
+    .adc.smaple_time = NRF_SAADC_ACQTIME_3US
+};
+
+void spim_xfer(uint32_t cs_pin,
+               nrf_spim_mode_t spi_mode,
+               uint8_t *p_tx_buffer,
+               uint16_t tx_buffer_length,
+               uint8_t *p_rx_buf,
+               uint16_t rx_buffer_length)
+{
+    __disable_irq();
+
+    NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
+
+    switch (spi_mode)
+    {
+        default:
+        case NRF_SPIM_MODE_0:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
+            break;
+
+        case NRF_SPIM_MODE_1:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
+            break;
+
+        case NRF_SPIM_MODE_2:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
+            break;
+
+        case NRF_SPIM_MODE_3:
+            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+                                (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
+                                (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
+            break;
+    }
+
+    NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+
+    NRF_SPIM3->TXD.MAXCNT = tx_buffer_length;
+    NRF_SPIM3->TXD.PTR    = (uint32_t)p_tx_buffer;
+
+    NRF_SPIM3->RXD.MAXCNT = rx_buffer_length;
+    NRF_SPIM3->RXD.PTR    = (uint32_t)p_rx_buf;
+
+    nrf_gpio_pin_clear(cs_pin);
+
+    NRF_SPIM3->EVENTS_END  = 0;
+    NRF_SPIM3->TASKS_START = 1;
+    do {
+    } while (NRF_SPIM3->EVENTS_END == 0);
+
+    nrf_gpio_pin_set(cs_pin);
+
+    __enable_irq();
+}
+
+#define MIN_PULSE_WIDTH 2
+#define MIN_PULSE_IDLE  2
+#define MAX_PULSE_WIDTH INT16_MAX
+#define MAX_PULSE_IDLE  INT16_MAX
+
+static void pel_saadc_init(pel_adc_t *p_adc)
+{
+    /* stop ssadc */
+    NRF_SAADC->EVENTS_STOPPED = 0;
+    NRF_SAADC->TASKS_STOP     = 1;
+    do {
+    } while (NRF_SAADC->EVENTS_STOPPED == 0);
+
+    /* disable ssadc */
+    NRF_SAADC->ENABLE = 0;
+
+    /*
+        ref: p.381, nrf52840_PS_v1.1.pdf
+        Note: Oversampling should only be used when a single input channel is enabled, as averaging is
+        performed over all enabled channels.
+    */
+    NRF_SAADC->OVERSAMPLE = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass;
+    NRF_SAADC->RESOLUTION = SAADC_RESOLUTION_VAL_14bit;
+    /* config analog inputs */
+    for (uint32_t i = 0; i < COUNTOF(NRF_SAADC->CH); i++)
+    {
+        if (i < COUNTOF(p_adc->channels))
+        {
+            NRF_SAADC->CH[i].PSELP = NRF_SAADC_INPUT_AIN0 + p_adc->channels[i];
+            NRF_SAADC->CH[i].PSELN = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].CONFIG =
+                (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESP_Pos) |
+                (NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESN_Pos) |
+                (p_adc->gain << SAADC_CH_CONFIG_GAIN_Pos) |
+                (NRF_SAADC_REFERENCE_INTERNAL << SAADC_CH_CONFIG_REFSEL_Pos) |
+                (p_adc->smaple_time << SAADC_CH_CONFIG_TACQ_Pos) |
+                (NRF_SAADC_MODE_SINGLE_ENDED << SAADC_CH_CONFIG_MODE_Pos) |
+                (NRF_SAADC_BURST_DISABLED << SAADC_CH_CONFIG_BURST_Pos);
+        }
+        else
+        {
+            NRF_SAADC->CH[i].PSELP  = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].PSELN  = NRF_SAADC_INPUT_DISABLED;
+            NRF_SAADC->CH[i].CONFIG = 0;
+        }
+    }
+    /* enable ssadc */
+    NRF_SAADC->INTENSET      = NRF_SAADC_INT_STARTED | NRF_SAADC_INT_END;
+    NRF_SAADC->ENABLE        = 1;
+    NRF_SAADC->RESULT.PTR    = (uint32_t)p_adc->results;
+    NRF_SAADC->RESULT.MAXCNT = COUNTOF(p_adc->results);
+}
+
+void TIMER3_IRQHandler(void)
+{
+    if (pel_hw.pulse_tmr->EVENTS_COMPARE[0])
+    {
+        pel_hw.pulse_tmr->EVENTS_COMPARE[0] = 0;
+
+        pel_hw.pulse_is_running = 1;
+
+        if (pel_hw.pulse_cnt)
+        {
+            pel_hw.pulse_cnt--;
+        }
+    }
+}
+
+void SAADC_IRQHandler(void)
+{
+    if (NRF_SAADC->EVENTS_STARTED)
+    {
+        NRF_SAADC->EVENTS_STARTED = 0;
+        if (pel_hw.pulse_cnt == 0)
+        {
+            pel_hw.pulse_tmr->TASKS_STOP = 1;
+        }
+        return;
+    }
+
+    if (NRF_SAADC->EVENTS_END)
+    {
+        NRF_SAADC->EVENTS_END    = 0;
+        NRF_SAADC->RESULT.PTR    = (uint32_t)pel_hw.adc.results;
+        NRF_SAADC->RESULT.MAXCNT = COUNTOF(pel_hw.adc.results);
+        pel_hw.pulse_is_running  = 0;
+        if (pel_hw.adc.convt_new_arrival_cb)
+        {
+            pel_hw.adc.convt_new_arrival_cb();
+        }
+    }
+}
+
+void pel_pulse_gen_init(pel_config_t cfg)
+{
+    pel_hw.pulse_tmr->TASKS_STOP = 1;
+    sd_nvic_DisableIRQ(pel_hw.pulse_irq_n);
+    sd_nvic_ClearPendingIRQ(pel_hw.pulse_irq_n);
+    sd_nvic_DisableIRQ(SAADC_IRQn);
+    sd_nvic_ClearPendingIRQ(SAADC_IRQn);
+
+    pel_hw.pulse_cnt                = cfg.pulse_cnt;
+    pel_hw.adc.gain                 = cfg.gain;
+    pel_hw.adc.smaple_time          = cfg.smaple_time;
+    pel_hw.adc.convt_new_arrival_cb = cfg.convt_new_arrival_cb;
+    pel_saadc_init(&pel_hw.adc);
+
+    // disable gpio task
+    for (int i = 0; i < 5; i++)
+    {
+        nrf_gpiote_task_disable(i);
+    }
+
+    // config gpiote task
+    nrf_gpiote_task_configure(0, cfg.anode_pin, NRF_GPIOTE_POLARITY_TOGGLE, (cfg.mode == 0) ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(1, cfg.ina_hi_pin, NRF_GPIOTE_POLARITY_TOGGLE, (cfg.mode == 0) ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(2, cfg.smaple_i_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(3, cfg.sample_v_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+
+    NRF_PPI->CH[0].EEP   = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[0];
+    NRF_PPI->CH[0].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0]; // anode_pin
+    NRF_PPI->FORK[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1]; // ina_hi_pin
+    NRF_PPI->CHENSET     = (1 << (0));
+
+    NRF_PPI->CH[1].EEP   = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[1];
+    NRF_PPI->CH[1].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2]; // smaple_i_pin
+    NRF_PPI->FORK[1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3]; // sample_v_pin
+    NRF_PPI->CHENSET     = (1 << (1));
+
+    NRF_PPI->CH[2].EEP   = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[2];
+    NRF_PPI->CH[2].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2];
+    NRF_PPI->FORK[2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3];
+    NRF_PPI->CHENSET     = (1 << (2));
+
+    NRF_PPI->CH[3].EEP   = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[3];
+    NRF_PPI->CH[3].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0];
+    NRF_PPI->FORK[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1];
+    NRF_PPI->CHENSET     = (1 << (3));
+
+    NRF_PPI->CH[4].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[4];
+    NRF_PPI->CH[4].TEP = (uint32_t)&NRF_SAADC->TASKS_START;
+    NRF_PPI->CHENSET   = (1 << (4));
+
+    NRF_PPI->CH[5].EEP = (uint32_t)&NRF_SAADC->EVENTS_STARTED;
+    NRF_PPI->CH[5].TEP = (uint32_t)&NRF_SAADC->TASKS_SAMPLE;
+    NRF_PPI->CHENSET   = (1 << (5));
+
+    NRF_PPI->CH[6].EEP = (uint32_t)&NRF_SAADC->EVENTS_END;
+    NRF_PPI->CHENSET   = (1 << (6));
+
+    // enable gpio task
+    for (int i = 0; i < 4; i++)
+    {
+        nrf_gpiote_task_enable(i);
+    }
+
+    if (cfg.test_pin != 0xFFFFFFFF)
+    {
+        nrf_gpiote_task_configure(4, cfg.test_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+        NRF_PPI->FORK[5].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4]; // test_pin
+        NRF_PPI->CH[6].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4];
+        nrf_gpiote_task_enable(4);
+    }
+
+    pel_hw.pulse_tmr->PRESCALER = NRF_TIMER_FREQ_16MHz;
+    pel_hw.pulse_tmr->MODE      = NRF_TIMER_MODE_TIMER;
+    pel_hw.pulse_tmr->BITMODE   = NRF_TIMER_BIT_WIDTH_32;
+    pel_hw.pulse_tmr->CC[0]     = cfg.point_us[0] * 16;
+    pel_hw.pulse_tmr->CC[1]     = pel_hw.pulse_tmr->CC[0] + cfg.point_us[1] * 16;
+    pel_hw.pulse_tmr->CC[2]     = pel_hw.pulse_tmr->CC[1] + cfg.point_us[2] * 16;
+    pel_hw.pulse_tmr->CC[3]     = pel_hw.pulse_tmr->CC[2] + cfg.point_us[3] * 16;
+    pel_hw.pulse_tmr->CC[4]     = pel_hw.pulse_tmr->CC[3] + cfg.point_us[4] * 16 + cfg.adc_timing_shift;
+    pel_hw.pulse_tmr->CC[5]     = pel_hw.pulse_tmr->CC[4];
+    pel_hw.pulse_tmr->SHORTS    = NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK;
+    pel_hw.pulse_tmr->INTENSET  = NRF_TIMER_INT_COMPARE0_MASK;
+
+    sd_nvic_SetPriority(SAADC_IRQn, _PRIO_APP_HIGH);
+    sd_nvic_EnableIRQ(SAADC_IRQn);
+
+    sd_nvic_SetPriority(pel_hw.pulse_irq_n, _PRIO_APP_HIGH);
+    sd_nvic_EnableIRQ(pel_hw.pulse_irq_n);
+}
+
+void pel_pulse_gen_start(void)
+{
+    pel_hw.pulse_tmr->TASKS_START = 1;
+}
+
+void pel_pulse_gen_stop(void)
+{
+    pel_hw.pulse_cnt = 0;
+    do {
+    } while (pel_hw.pulse_is_running == 1);
+    pel_hw.adc.convt_new_arrival_cb = NULL;
+}
+
+#if (DEF_ELITE_DEMO_W_SOFTDEVICE == 1) || (DEF_ELITE_DEMO_WO_SOFTDEVICE == 1)
+static void pel_pulse_gen_demo_task(void *p_arg)
+{
+    pel_config_t pel_cfg = {
+        .anode_pin    = ANODE_PIN,
+        .ina_hi_pin   = INA_HI_PIN,
+        .smaple_i_pin = SAMPLE_I_PIN,
+        .sample_v_pin = SAMPLE_V_PIN,
+        .test_pin     = TP1_PIN,
+        .mode         = BOARD_IOPx,
+        .point_us     = {
+                         10000,
+                         3,
+                         5,
+                         2,
+                         0,
+                         },
+        .pulse_cnt        = 0xFFFFFFFF,
+        .gain             = NRF_SAADC_GAIN1_6,
+        .smaple_time      = NRF_SAADC_ACQTIME_10US,
+        .adc_timing_shift = 0,
+    };
+
+    pel_pulse_gen_init(pel_cfg);
+
+    pel_pulse_gen_start();
+
+    for (;;)
+    {
+        static uint32_t i = 0;
+        vTaskDelay(pdMS_TO_TICKS(pel_cfg.point_us[0] / 1000));
+        SEGGER_RTT_printf(0, "%d, %d, %d, %d, %d, %d\r\n", i++, pel_hw.adc.results[0], pel_hw.adc.results[1], pel_hw.adc.results[2], pel_hw.adc.results[3], pel_hw.adc.results[4]);
+    }
+}
+
+void pel_pulse_gen_demo(void)
+{
+}
+#endif
+
+void pel30_io_init(void)
+{
+    const uint32_t config_output_and_set[] = {
+        INPUT_1_PIN,
+        INPUT_2_PIN,
+        INPUT_3_PIN,
+        INPUT_4_PIN,
+        INPUT_5_PIN,
+        INPUT_6_PIN,
+        INPUT_7_PIN,
+        INPUT_8_PIN,
+        INPUT_9_PIN,
+        INPUT_10_PIN,
+        INPUT_11_PIN,
+        INPUT_12_PIN
+    };
+
+    const uint32_t config_output_and_clear[] = {
+        TP1_PIN,
+        TP2_PIN,
+        SAMPLE_I_PIN,
+        SAMPLE_V_PIN,
+        HOT_SWAP_1_PIN
+    };
+
+    for (int i = 0; i < ARRAY_SIZE(config_output_and_set); i++)
+    {
+        nrf_gpio_pin_set(config_output_and_set[i]);
+        nrf_gpio_cfg_output(config_output_and_set[i]);
+    }
+
+    for (int i = 0; i < ARRAY_SIZE(config_output_and_clear); i++)
+    {
+        nrf_gpio_pin_clear(config_output_and_clear[i]);
+        nrf_gpio_cfg_output(config_output_and_clear[i]);
+    }
+
+    nrf_gpio_cfg_input(RESET_PIN, NRF_GPIO_PIN_NOPULL);
+    nrf_gpio_cfg_input(CATHODE_PIN, NRF_GPIO_PIN_NOPULL);
+    nrf_gpio_cfg_input(HOT_SWAP_SIGNAL_PIN, NRF_GPIO_PIN_PULLUP);
+
+    if (BOARD_IOPx == BOARD_IOPH)
+    {
+        nrf_gpio_pin_clear(ANODE_PIN);
+        nrf_gpio_pin_clear(INA_HI_PIN);
+        nrf_gpio_pin_set(LED_IOPL_PIN);
+        nrf_gpio_pin_clear(LED_IOPH_PIN);
+    }
+    else if (BOARD_IOPx == BOARD_IOPL)
+    {
+        nrf_gpio_pin_set(ANODE_PIN);
+        nrf_gpio_pin_set(INA_HI_PIN);
+        nrf_gpio_pin_clear(LED_IOPL_PIN);
+        nrf_gpio_pin_set(LED_IOPH_PIN);
+    }
+
+    nrf_gpio_cfg_output(ANODE_PIN);
+    nrf_gpio_cfg_output(INA_HI_PIN);
+    nrf_gpio_cfg_output(LED_IOPL_PIN);
+    nrf_gpio_cfg_output(LED_IOPH_PIN);
+
+    // Config spi module
+    nrf_gpio_pin_set(WP_MEM_PIN);
+    nrf_gpio_pin_set(CS_MEM_PIN);
+    nrf_gpio_pin_clear(SPIM_MOSI_PIN);
+    nrf_gpio_pin_clear(SPIM_CLK_PIN);
+    nrf_gpio_cfg_output(WP_MEM_PIN);
+    nrf_gpio_cfg_output(CS_MEM_PIN);
+    nrf_gpio_cfg_output(SPIM_MOSI_PIN);
+    nrf_gpio_cfg_output(SPIM_CLK_PIN);
+    nrf_gpio_cfg_input(SPIM_MISO_PIN, NRF_GPIO_PIN_NOPULL);
+
+    NRF_SPIM3->ENABLE          = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
+    NRF_SPIM3->ORC             = 0x00000000;
+    NRF_SPIM3->FREQUENCY       = SPIM_FREQUENCY_FREQUENCY_M32;
+    NRF_SPIM3->CSNPOL          = SPIM_CSNPOL_CSNPOL_LOW;
+    NRF_SPIM3->IFTIMING.CSNDUR = 8;
+    NRF_SPIM3->PSEL.CSN        = CS_MEM_PIN;
+    NRF_SPIM3->PSEL.SCK        = SPIM_CLK_PIN;
+    NRF_SPIM3->PSEL.MOSI       = SPIM_MOSI_PIN;
+    NRF_SPIM3->PSEL.MISO       = SPIM_MISO_PIN;
+    NRF_SPIM3->ENABLE          = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+}
+
+#endif

app/src/fs.c

@@ -0,0 +1,205 @@
+#include "fs.h"
+
+#include "nrf.h"
+#include "nrf_log.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+#if (DEF_GD25D10C_ENABLED)
+#include "gd25d10c.h"
+static const block_dev_drv_if_t *p_inst = &gd25d110c;
+#endif /* ! DEF_GD25D10C_ENABLED */
+
+#if (DEF_FS_ENABLED)
+static SemaphoreHandle_t m_sem = NULL;
+static struct lfs_config lfs_config;
+static lfs_t lfs;
+
+static int lfs_read(const struct lfs_config *c, lfs_block_t block, lfs_off_t off, void *buffer, lfs_size_t size)
+{
+    if (c->context == NULL)
+    {
+        return LFS_ERR_IO;
+    }
+    p_inst->read_data(buffer, block * c->block_size + off, size);
+    return LFS_ERR_OK;
+}
+
+static int lfs_prog(const struct lfs_config *c, lfs_block_t block, lfs_off_t off, const void *buffer, lfs_size_t size)
+{
+    if (c->context == NULL)
+    {
+        return LFS_ERR_IO;
+    }
+    p_inst->page_prog((void *)buffer, block * c->block_size + off, size / c->prog_size);
+    return LFS_ERR_OK;
+}
+
+static int lfs_erase(const struct lfs_config *c, lfs_block_t block)
+{
+    if (c->context == NULL)
+    {
+        return LFS_ERR_IO;
+    }
+    p_inst->sect_erase(block * c->block_size, 1);
+    return LFS_ERR_OK;
+}
+
+static int lfs_sync(const struct lfs_config *c)
+{
+    if (c->context == NULL)
+    {
+        return LFS_ERR_IO;
+    }
+    return LFS_ERR_OK;
+}
+
+static int lfs_lock(const struct lfs_config *c)
+{
+    if (c->context == NULL)
+    {
+        return LFS_ERR_IO;
+    }
+    xSemaphoreTake(m_sem, portMAX_DELAY);
+    return LFS_ERR_OK;
+}
+
+static int lfs_unlock(const struct lfs_config *c)
+{
+    if (c->context == NULL)
+    {
+        return LFS_ERR_IO;
+    }
+    xSemaphoreGive(m_sem);
+    return LFS_ERR_OK;
+}
+
+void fs_init(void)
+{
+    m_sem = xSemaphoreCreateMutex();
+
+    if (p_inst->init() == BLOCK_DEV_SUCCESS)
+    {
+        lfs_config.context = (void *)p_inst;
+
+        // block device operations
+        lfs_config.read   = lfs_read;
+        lfs_config.prog   = lfs_prog;
+        lfs_config.erase  = lfs_erase;
+        lfs_config.sync   = lfs_sync;
+        lfs_config.lock   = lfs_lock;
+        lfs_config.unlock = lfs_unlock;
+
+        // block device configuration
+        lfs_config.read_size      = 1;
+        lfs_config.prog_size      = p_inst->page_size;
+        lfs_config.block_size     = p_inst->sect_size;
+        lfs_config.block_count    = p_inst->sect_count;
+        lfs_config.block_cycles   = 5000;
+        lfs_config.cache_size     = p_inst->page_size;
+        lfs_config.lookahead_size = sizeof(uint32_t);
+    }
+
+    if (lfs_mount(&lfs, &lfs_config) < 0)
+    {
+        if (lfs_format(&lfs, &lfs_config) < 0)
+        {
+            __BKPT(255);
+        }
+        if (lfs_mount(&lfs, &lfs_config) < 0)
+        {
+            return;
+        }
+    }
+}
+
+int fs_file_open(file_t *hFile, char *filename, uint32_t attr)
+{
+    int ret = lfs_file_open(&lfs, hFile, filename, attr);
+    return ret;
+}
+
+int fs_file_write(file_t *hFile, void *write, uint32_t size)
+{
+    int ret = lfs_file_write(&lfs, hFile, write, size);
+    return ret;
+}
+
+int fs_file_read(file_t *hFile, void *read, uint32_t size)
+{
+    int ret = lfs_file_read(&lfs, hFile, read, size);
+    return ret;
+}
+
+int fs_file_close(file_t *hFile)
+{
+    int ret = lfs_file_close(&lfs, hFile);
+    return ret;
+}
+
+int fs_dir(char *path)
+{
+    int ret           = 0;
+    int fileCount     = 0;
+    int dirCount      = 0;
+    int totalFileSize = 0;
+
+    char *str             = pvPortMalloc(256);
+    lfs_dir_t *dir        = pvPortMalloc(sizeof(lfs_dir_t));
+    struct lfs_info *info = pvPortMalloc(sizeof(struct lfs_info));
+
+    snprintf(str, 256, "Directory of %s", path);
+    NRF_LOG_INFO("%s", str);
+
+    ret = lfs_dir_open(&lfs, dir, path);
+
+    if (ret == LFS_ERR_OK)
+    {
+        do {
+            ret = lfs_dir_read(&lfs, dir, info);
+
+            if (ret > 0)
+            {
+                snprintf(str,
+                         256,
+                         "%5s%10ld bytes    %s",
+                         info->type == LFS_TYPE_REG ? "     " : info->type == LFS_TYPE_DIR ? "<dir>" :
+                                                                                             "unkown",
+                         info->size,
+                         info->name);
+                NRF_LOG_INFO("%s", str);
+                switch (info->type)
+                {
+                    case LFS_TYPE_REG:
+                        fileCount++;
+                        totalFileSize += info->size;
+                        break;
+                    case LFS_TYPE_DIR:
+                        dirCount++;
+                        break;
+                    default:
+                        break;
+                }
+            }
+            else
+            {
+                snprintf(str, 256, "%15d dir(s)", dirCount);
+                NRF_LOG_INFO("%s", str);
+                snprintf(str, 256, "%15d file(s), total %d byets", fileCount, totalFileSize);
+                NRF_LOG_INFO("%s", str);
+            }
+        } while (ret > 0);
+
+        ret = lfs_dir_close(&lfs, dir);
+    }
+
+    vPortFree(info);
+    vPortFree(dir);
+    vPortFree(str);
+
+    return ret;
+}
+
+#endif /* !DEF_FS_ENABLED */

app/src/gd25d10c.c

@@ -0,0 +1,275 @@
+#include "gd25d10c.h"
+
+#include <string.h>
+
+#if (DEF_GD25D10C_ENABLED)
+
+#define ERASE_BLOCK_SIZE (32 * 1024)
+#define ERASE_SECT_SIZE  4096
+#define PROG_PAGE_SIZE   256
+#define PAGE_PER_SECT    16
+#define PAGE_PER_BLOCK   128
+#define SECT_PER_BLOCK   8
+#define BLOCK_PER_DEV    4
+
+#define CMD_READ         0x03
+#define CMD_WREN         0x06
+#define CMD_WRDI         0x04
+#define CMD_RDSR         0x05
+#define CMD_WRSR         0x01
+#define CMD_PP           0x02
+#define CMD_RDID         0x9F
+#define CMD_SE           0x20
+#define CMD_BE           0x52
+
+#define WIP_BIT          0x01
+#define WEL_BIT          0x02
+
+#define MANUFACTURER_ID  0xC8
+#define MEMORY_TYPE      0x40
+#define CAPACITY         0x11
+
+#define EXPECT_ID        ((MANUFACTURER_ID << 16) | (MEMORY_TYPE << 8) | (CAPACITY << 0))
+
+uint8_t xfer_buf[4096 + 32];
+
+static int read_data(uint8_t *p_dest, uint32_t addr, uint32_t size)
+{
+    struct send
+    {
+        union
+        {
+            uint32_t val;
+            struct
+            {
+                uint32_t addr : 24;
+                uint32_t cmd  : 8;
+            };
+        };
+    } *p_tx = (void *)xfer_buf;
+
+    struct recv
+    {
+        uint32_t dummy;
+        uint8_t recv[0];
+    } *p_rx = (void *)xfer_buf;
+
+    p_tx->cmd  = CMD_READ;
+    p_tx->addr = addr;
+    p_tx->val  = __REV(p_tx->val);
+    spim_xfer(CS_MEM_PIN, NRF_SPIM_MODE_0, (void *)p_tx, sizeof(*p_tx), (void *)p_rx, offsetof(struct recv, recv) + size);
+    memcpy(p_dest, &xfer_buf[sizeof(*p_tx)], size);
+    return BLOCK_DEV_SUCCESS;
+}
+
+static void write_enable(void)
+{
+    uint32_t tx = 0;
+    struct send
+    {
+        uint8_t cmd;
+    } *p_tx   = (void *)&tx;
+    p_tx->cmd = CMD_WREN;
+    spim_xfer(CS_MEM_PIN, NRF_SPIM_MODE_0, (void *)p_tx, sizeof(*p_tx), NULL, 0);
+}
+
+static void write_disable(void)
+{
+    uint32_t tx = 0;
+    struct send
+    {
+        uint8_t cmd;
+    } *p_tx   = (void *)&tx;
+    p_tx->cmd = CMD_WRDI;
+    spim_xfer(CS_MEM_PIN, NRF_SPIM_MODE_0, (void *)p_tx, sizeof(*p_tx), NULL, 0);
+}
+
+static uint32_t read_status(void)
+{
+    uint32_t tx = 0, rx = 0;
+
+    struct send
+    {
+        uint8_t cmd;
+        uint8_t dummy;
+    } *p_tx = (void *)&tx;
+
+    struct recv
+    {
+        uint8_t dummy;
+        uint8_t status;
+    } *p_rx = (void *)&rx;
+
+    p_tx->cmd   = CMD_RDSR;
+    p_tx->dummy = 0xFF;
+    spim_xfer(CS_MEM_PIN, NRF_SPIM_MODE_0, (void *)p_tx, sizeof(*p_tx), (void *)p_rx, offsetof(struct recv, status) + sizeof(p_rx->status));
+    return p_rx->status;
+}
+
+static void write_status(uint8_t stauts)
+{
+    uint32_t tx = 0;
+    struct send
+    {
+        uint8_t cmd;
+        uint8_t stauts;
+    } *p_tx      = (void *)&tx;
+    p_tx->cmd    = CMD_RDSR;
+    p_tx->stauts = stauts;
+    spim_xfer(CS_MEM_PIN, NRF_SPIM_MODE_0, (void *)p_tx, sizeof(*p_tx), NULL, 0);
+}
+
+static int page_prog(uint8_t *p_src, uint32_t addr, uint32_t page_cnt)
+{
+    for (uint32_t i = 0; i < page_cnt; i++)
+    {
+        write_enable();
+
+        struct send
+        {
+            union
+            {
+                uint32_t val;
+                struct
+                {
+                    uint32_t addr : 24;
+                    uint32_t cmd  : 8;
+                };
+            };
+
+            uint8_t data[256];
+        } *p_tx = (void *)xfer_buf;
+
+        p_tx->cmd  = CMD_PP;
+        p_tx->addr = addr + PROG_PAGE_SIZE * i;
+        p_tx->val  = __REV(p_tx->val);
+        memcpy(p_tx->data, (void *)(&p_src[PROG_PAGE_SIZE * i]), PROG_PAGE_SIZE);
+
+        spim_xfer(CS_MEM_PIN, NRF_SPIM_MODE_0, (void *)p_tx, sizeof(*p_tx), NULL, 0);
+
+        do {
+        } while ((read_status() & WIP_BIT));
+    }
+    return BLOCK_DEV_SUCCESS;
+}
+
+int sect_erase(uint32_t addr, uint32_t sect_cnt)
+{
+    for (uint32_t i = 0; i < sect_cnt; i++)
+    {
+        write_enable();
+
+        struct send
+        {
+            union
+            {
+                uint32_t val;
+                struct
+                {
+                    uint32_t addr : 24;
+                    uint32_t cmd  : 8;
+                };
+            };
+        } *p_tx = (void *)xfer_buf;
+
+        p_tx->cmd  = CMD_SE;
+        p_tx->addr = addr + i * ERASE_SECT_SIZE;
+        p_tx->val  = __REV(p_tx->val);
+        spim_xfer(CS_MEM_PIN, NRF_SPIM_MODE_0, (void *)p_tx, sizeof(*p_tx), NULL, 0);
+
+        do {
+        } while ((read_status() & WIP_BIT));
+    }
+    return BLOCK_DEV_SUCCESS;
+}
+
+int block_erase(uint32_t addr, uint32_t block_cnt)
+{
+
+    for (uint32_t i = 0; i < block_cnt; i++)
+    {
+        write_enable();
+
+        struct send
+        {
+            union
+            {
+                uint32_t val;
+                struct
+                {
+                    uint32_t addr : 24;
+                    uint32_t cmd  : 8;
+                };
+            };
+        } *p_tx = (void *)xfer_buf;
+
+        p_tx->cmd  = CMD_BE;
+        p_tx->addr = addr + i * ERASE_BLOCK_SIZE;
+        p_tx->val  = __REV(p_tx->val);
+
+        spim_xfer(CS_MEM_PIN, NRF_SPIM_MODE_0, (void *)p_tx, sizeof(*p_tx), NULL, 0);
+
+        do {
+        } while ((read_status() & WIP_BIT));
+    }
+    return BLOCK_DEV_SUCCESS;
+}
+
+uint32_t dev_id(void)
+{
+    uint32_t tx = 0, rx = 0;
+
+    struct send
+    {
+        uint32_t cmd   : 8;
+        uint32_t dummy : 24;
+    } *p_tx     = (void *)&tx;
+    p_tx->cmd   = CMD_RDID;
+    p_tx->dummy = 0x000000;
+
+    struct recv
+    {
+        uint32_t dummy        : 8;
+        uint32_t manufacturer : 8;
+        uint32_t memory_type  : 8;
+        uint32_t capacity     : 8;
+    } *p_rx = (void *)&rx;
+
+    spim_xfer(CS_MEM_PIN, NRF_SPIM_MODE_0, (void *)p_tx, sizeof(*p_tx), (void *)p_rx, sizeof(*p_rx));
+
+    return __REV(rx) & 0x00FFFFFF;
+}
+
+static int init(void)
+{
+    uint32_t id = dev_id();
+
+    if (EXPECT_ID == id)
+    {
+        return BLOCK_DEV_SUCCESS;
+    }
+
+    return BLOCK_DEV_ERROR;
+}
+
+static int reset(void)
+{
+    //  Do nothing
+    return 0;
+}
+
+const block_dev_drv_if_t gd25d110c = {
+    .init          = init,
+    .reset         = reset,
+    .read_data     = read_data,
+    .page_prog     = page_prog,
+    .sect_erase    = sect_erase,
+    .block_erase   = block_erase,
+    .block_size    = ERASE_BLOCK_SIZE,
+    .sect_size     = ERASE_SECT_SIZE,
+    .sect_count    = BLOCK_PER_DEV * SECT_PER_BLOCK,
+    .page_size     = PROG_PAGE_SIZE,
+    .page_per_sect = (ERASE_SECT_SIZE / PROG_PAGE_SIZE)
+};
+
+#endif /* ! DEF_GD25D10C_ENABLED */

app/src/j_scop.c

@@ -0,0 +1,23 @@
+#include "app_config.h"
+
+#include <SEGGER_RTT.h>
+
+#if (DEF_RTT_JSCOP_ENABLED)
+
+static char JS_RTT_UpBuffer[4096]; // J-Scope RTT Buffer
+static int JS_RTT_Channel = 1;     // J-Scope RTT Channel
+
+void j_scop_init(void)
+{
+    //
+    // Configure J-Scope RTT buffer for one unsigned int and one signed int
+    //
+    SEGGER_RTT_ConfigUpBuffer(JS_RTT_Channel, "JScope_f4", &JS_RTT_UpBuffer[0], sizeof(JS_RTT_UpBuffer), SEGGER_RTT_MODE_NO_BLOCK_SKIP);
+}
+
+void j_scope_update(float f)
+{
+    SEGGER_RTT_Write(JS_RTT_Channel, &f, sizeof(f));
+}
+
+#endif

app/src/le_adv.c

@@ -1,29 +1,14 @@
-#include <stdbool.h>
-#include <stdint.h>
-
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
 #include "app_config.h"
-#include "apply_old_config.h"
-#include "sdk_config.h"
+#include "app_error.h"
 
-#include "nrf_log.h"
-#include "nrf_log_ctrl.h"
-#include "nrf_log_default_backends.h"
-
-#include "nrf_delay.h"
-#include "nrf_gpio.h"
-
-#include "nrf_sdh.h"
-#include "nrf_sdh_ble.h"
-#include "nrf_sdh_freertos.h"
-
-#include "ble_advdata.h"
 #include "ble_advertising.h"
-#include "ble_srv_common.h"
+
+#include "nrf_sdh_ble.h"
 
 #ifdef __cplusplus
 }
@@ -31,6 +16,13 @@ extern "C"
 
 BLE_ADVERTISING_DEF(m_advertising); /**< Advertising module instance. */
 
+#define BLE_ADV_UUID                      \
+    {                                     \
+        {                                 \
+            ELITE_UUID, BLE_UUID_TYPE_BLE \
+        }                                 \
+    }
+
 static void le_adv_evt_handler(ble_adv_evt_t const adv_evt)
 {
     switch (adv_evt)
@@ -59,33 +51,39 @@ void le_adv_init(uint8_t ble_conn_cfg_tag)
 {
     uint32_t err_code;
     ble_advertising_init_t init;
+
     memset(&init, 0, sizeof(init));
 
     struct
     {
-        const uint8_t company_code[5];
-        const uint8_t hw_ver[4];
+        uint8_t company_code[2];
+        uint8_t hw_ver[4];
+        uint8_t build_time[2];
+        uint8_t bat_str[3];
         uint16_t bat_volt;
     } __PACKED data = {
-        .company_code = ELITE_COMPANY_CODE,
-        .hw_ver       = ELITE_HW_VER,
-        .bat_volt     = 100,
+        .hw_ver     = ELITE_HW_VER,
+        .build_time = {24, 01},
+        .bat_str    = "BAT",
+        .bat_volt   = 0x0C1C,
     };
 
-    ble_advdata_manuf_data_t manuf_specific_data; // Advertising Data: add manuf_specific_data = FF FF 45 6C 69 74 65 00 04 01 01 1C 0C
-    manuf_specific_data.data.p_data        = (uint8_t *)&data;
-    manuf_specific_data.data.size          = sizeof(data);
-    manuf_specific_data.company_identifier = 0xFFFF;
-    init.advdata.p_manuf_specific_data     = &manuf_specific_data;
-    init.advdata.name_type                 = BLE_ADVDATA_FULL_NAME;
-    init.advdata.flags                     = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE;
+    ble_advdata_manuf_data_t manuf_specific_data;
+    manuf_specific_data.data.p_data = (uint8_t *)&data;
+    manuf_specific_data.data.size   = sizeof(data);
+    memcpy(&manuf_specific_data.company_identifier, &ELITE_COMPANY_CODE[0], 2);
+    memcpy(&data.company_code[0], &ELITE_COMPANY_CODE[2], 2);
+
+    ble_uuid_t m_adv_uuids[]             = BLE_ADV_UUID;
+    init.advdata.uuids_complete.uuid_cnt = sizeof(m_adv_uuids) / sizeof(m_adv_uuids[0]);
+    init.advdata.uuids_complete.p_uuids  = m_adv_uuids;
+    init.advdata.flags                   = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE;
+    init.srdata.p_manuf_specific_data    = &manuf_specific_data;
+    init.srdata.name_type                = BLE_ADVDATA_FULL_NAME;
 
     init.config.ble_adv_fast_enabled  = true;
-    init.config.ble_adv_fast_interval = MSEC_TO_UNITS(25, UNIT_0_625_MS);
-    init.config.ble_adv_fast_timeout  = MSEC_TO_UNITS(3000, UNIT_10_MS);
-    init.config.ble_adv_slow_enabled  = true;
-    init.config.ble_adv_slow_interval = MSEC_TO_UNITS(250, UNIT_0_625_MS);
-    init.config.ble_adv_slow_timeout  = MSEC_TO_UNITS(0, UNIT_10_MS);
+    init.config.ble_adv_fast_interval = MSEC_TO_UNITS(75, UNIT_0_625_MS);
+    init.config.ble_adv_fast_timeout  = MSEC_TO_UNITS(0, UNIT_10_MS);
 
     init.evt_handler   = le_adv_evt_handler;
     init.error_handler = le_adv_error_handler;

app/src/le_dfu.c

@@ -1,31 +1,15 @@
-#include <stdbool.h>
-#include <stdint.h>
-
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
 #include "app_config.h"
-#include "apply_old_config.h"
-#include "sdk_config.h"
-
-#include "nrf_log.h"
-#include "nrf_log_ctrl.h"
-#include "nrf_log_default_backends.h"
-
-#include "nrf_delay.h"
-#include "nrf_gpio.h"
-
-#include "nrf_sdh.h"
-#include "nrf_sdh_ble.h"
-#include "nrf_sdh_freertos.h"
+#include "app_error.h"
 
 #include "ble_conn_state.h"
-
 #include "ble_dfu.h"
-#include "ble_dis.h"
-#include "nrf_ble_gatt.h"
+
+#include "nrf_log.h"
 
 #ifdef __cplusplus
 }

app/src/le_elite_srv.c

@@ -0,0 +1,345 @@
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <string.h>
+
+#include "app_config.h"
+#include "app_error.h"
+
+#include "ble_srv_common.h"
+
+#include "nrf_log.h"
+#include "nrf_sdh_ble.h"
+
+#include "FreeRTOS.h"
+#include "message_buffer.h"
+#include "task.h"
+
+#include "elite.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#if NRF_MODULE_ENABLED(BLE_ELITE_SRV)
+
+#define BLE_UUID_ELITE_SERVICE    0xFFF0
+#define BLE_UUID_ELITE_DATA_CHAR  0xFFF1
+#define BLE_UUID_ELITE_INST_CHAR  0xFFF2
+#define BLE_UUID_ELITE_EVENT_CHAR 0xFFF3
+#define BLE_UUID_ELITE_BEGIN_CHAR BLE_UUID_ELITE_DATA_CHAR
+#define BLE_UUID_ELITE_END_CHAR   (BLE_UUID_ELITE_EVENT_CHAR + 1)
+
+typedef struct
+{
+    uint16_t conn_handle;
+    uint16_t service_handle;
+    ble_gatts_char_handles_t data_char_handle;
+    ble_gatts_char_handles_t inst_char_handle;
+    ble_gatts_char_handles_t event_char_handle;
+    bool data_notify_enable;
+    bool inst_notify_enable;
+    bool event_notify_enable;
+} elite_context_t;
+
+static elite_context_t elite_context = {
+    .conn_handle         = BLE_CONN_HANDLE_INVALID,
+    .data_notify_enable  = false,
+    .inst_notify_enable  = false,
+    .event_notify_enable = false,
+};
+
+static MessageBufferHandle_t async_notify_msg = NULL;
+
+static void on_connect(elite_context_t *p_context, ble_evt_t const *p_ble_evt)
+{
+    taskENTER_CRITICAL();
+    p_context->conn_handle = p_ble_evt->evt.common_evt.conn_handle;
+    taskEXIT_CRITICAL();
+}
+
+static void on_disconnect(elite_context_t *p_context, ble_evt_t const *p_ble_evt)
+{
+    taskENTER_CRITICAL();
+    p_context->conn_handle         = BLE_CONN_HANDLE_INVALID;
+    p_context->data_notify_enable  = false;
+    p_context->inst_notify_enable  = false;
+    p_context->event_notify_enable = false;
+    taskEXIT_CRITICAL();
+}
+
+static void elite_srv_ccc_update(elite_context_t *p_context, ble_evt_t const *p_ble_evt)
+{
+    ble_gatts_evt_write_t const *p_evt_write = &p_ble_evt->evt.gatts_evt.params.write;
+    if (p_evt_write->handle == p_context->data_char_handle.cccd_handle)
+    {
+        p_context->data_notify_enable = ble_srv_is_notification_enabled(p_evt_write->data);
+        NRF_LOG_INFO("data_notify:%s", p_context->data_notify_enable ? "enable" : "disable");
+        return;
+    }
+
+    if (p_evt_write->handle == p_context->inst_char_handle.cccd_handle)
+    {
+        p_context->inst_notify_enable = ble_srv_is_notification_enabled(p_evt_write->data);
+        NRF_LOG_INFO("inst_notify_notify:%s", p_context->inst_notify_enable ? "enable" : "disable");
+        return;
+    }
+
+    if (p_evt_write->handle == p_context->event_char_handle.cccd_handle)
+    {
+        p_context->event_notify_enable = ble_srv_is_notification_enabled(p_evt_write->data);
+        NRF_LOG_INFO("event_notify:%s", p_context->event_notify_enable ? "enable" : "disable");
+        return;
+    }
+}
+
+static void on_write(elite_context_t *p_context, ble_evt_t const *p_ble_evt)
+{
+    ble_uuid_t uuid                          = p_ble_evt->evt.gatts_evt.params.write.uuid;
+    uint16_t handle                          = p_ble_evt->evt.gatts_evt.params.write.handle;
+    ble_gatts_evt_write_t const *p_evt_write = &p_ble_evt->evt.gatts_evt.params.write;
+    switch (uuid.uuid)
+    {
+        case BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG:
+            elite_srv_ccc_update(p_context, p_ble_evt);
+            break;
+
+        case BLE_UUID_ELITE_INST_CHAR:
+            NRF_LOG_INFO("");
+            NRF_LOG_HEXDUMP_INFO(p_evt_write->data, p_evt_write->len);
+            elite_instr_send((void *)p_evt_write->data, p_evt_write->len);
+            break;
+        default:
+            break;
+    }
+}
+
+static void on_hvx_tx_complete(elite_context_t *p_context, ble_evt_t const *p_ble_evt)
+{
+}
+
+static void on_ble_evt_handler(ble_evt_t const *p_ble_evt, void *p_context)
+{
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_CONNECTED:
+            on_connect(p_context, p_ble_evt);
+            break;
+        case BLE_GAP_EVT_DISCONNECTED:
+            on_disconnect(p_context, p_ble_evt);
+            break;
+        case BLE_GATTS_EVT_WRITE:
+            on_write(p_context, p_ble_evt);
+            break;
+        case BLE_GATTS_EVT_HVN_TX_COMPLETE:
+            on_hvx_tx_complete(p_context, p_ble_evt);
+            break;
+        default:
+            // No implementation needed.
+            break;
+    }
+}
+
+static ret_code_t add_characteristic(uint16_t uuid, uint8_t uuid_type, uint32_t val_max_len, void *p_init_val, uint32_t init_len, ble_gatts_char_handles_t *p_handles, bool enable_cccd)
+{
+    ble_add_char_params_t add_char_params;
+    memset(&add_char_params, 0, sizeof(add_char_params));
+    add_char_params.uuid              = uuid;
+    add_char_params.uuid_type         = uuid_type;
+    add_char_params.max_len           = val_max_len;
+    add_char_params.init_len          = init_len;
+    add_char_params.p_init_value      = p_init_val;
+    add_char_params.is_value_user     = false;
+    add_char_params.is_var_len        = true;
+    add_char_params.write_access      = SEC_OPEN;
+    add_char_params.char_props.write  = 1;
+    add_char_params.read_access       = SEC_OPEN;
+    add_char_params.char_props.read   = 1;
+    add_char_params.cccd_write_access = SEC_OPEN;
+    add_char_params.char_props.notify = enable_cccd;
+    ret_code_t err_code               = characteristic_add(elite_context.service_handle, &add_char_params, p_handles);
+    return err_code;
+}
+
+static ret_code_t add_characteristic_ro(uint16_t uuid, uint8_t uuid_type, uint32_t val_max_len, void *p_init_val, uint32_t init_len, ble_gatts_char_handles_t *p_handles, bool enable_cccd)
+{
+    ble_add_char_params_t add_char_params;
+    memset(&add_char_params, 0, sizeof(add_char_params));
+    add_char_params.uuid              = uuid;
+    add_char_params.uuid_type         = uuid_type;
+    add_char_params.max_len           = val_max_len;
+    add_char_params.init_len          = init_len;
+    add_char_params.p_init_value      = p_init_val;
+    add_char_params.is_value_user     = true;
+    add_char_params.is_var_len        = true;
+    add_char_params.read_access       = SEC_OPEN;
+    add_char_params.char_props.read   = 1;
+    add_char_params.cccd_write_access = SEC_OPEN;
+    add_char_params.char_props.notify = enable_cccd;
+    ret_code_t err_code               = characteristic_add(elite_context.service_handle, &add_char_params, p_handles);
+    return err_code;
+}
+
+static uint32_t elite_srv_init(void)
+{
+    ret_code_t err_code;
+    ble_uuid_t ble_uuid = {
+        .type = BLE_UUID_TYPE_BLE,
+        .uuid = BLE_UUID_ELITE_SERVICE,
+    };
+
+    // Adding proprietary service to the SoftDevice
+    err_code = sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY, &ble_uuid, &elite_context.service_handle);
+    APP_ERROR_CHECK(err_code);
+
+    uint8_t init_val[NRF_SDH_BLE_GATT_MAX_MTU_SIZE - 3];
+    memset(init_val, 0x00, sizeof(init_val));
+
+    // Adding data characteristic to the SoftDevice
+    err_code = add_characteristic_ro(BLE_UUID_ELITE_DATA_CHAR, ble_uuid.type, sizeof(init_val), init_val, sizeof(init_val), &elite_context.data_char_handle, true);
+    APP_ERROR_CHECK(err_code);
+
+    // Adding instruction characteristic to the SoftDevice
+    err_code = add_characteristic(BLE_UUID_ELITE_INST_CHAR, ble_uuid.type, sizeof(init_val), init_val, sizeof(init_val), &elite_context.inst_char_handle, true);
+    APP_ERROR_CHECK(err_code);
+
+    // Adding event characteristic to the SoftDevice
+    err_code = add_characteristic_ro(BLE_UUID_ELITE_EVENT_CHAR, ble_uuid.type, sizeof(init_val), init_val, sizeof(init_val), &elite_context.event_char_handle, true);
+    APP_ERROR_CHECK(err_code);
+
+    // Register a handler for BLE events.
+    NRF_SDH_BLE_OBSERVER(m_ble_elite_observer, BLE_ELITE_OBSERVER_PRIO, on_ble_evt_handler, &elite_context);
+
+    return NRF_SUCCESS;
+}
+
+static void le_elite_srv_async_notify_task(void *p_arg)
+{
+    static uint8_t buf[256];
+    for (;;)
+    {
+        uint32_t size = xMessageBufferReceive(async_notify_msg, buf, sizeof(buf), portMAX_DELAY);
+        if (size)
+        {
+            for (uint32_t i = 0; i < 10; i++)
+            {
+                ret_code_t ret = le_event_notify(buf, size);
+                if (ret == NRF_ERROR_BUSY)
+                {
+                    vTaskDelay(pdMS_TO_TICKS(5));
+                }
+                else
+                {
+                    break;
+                }
+            }
+        }
+    }
+}
+
+void le_elite_srv_init(void)
+{
+    async_notify_msg = xMessageBufferCreate(10 * 1024);
+    if (xTaskCreate(le_elite_srv_async_notify_task, "async_notify", 512, NULL, 4, NULL) == pdFALSE)
+    {
+        APP_ERROR_CHECK(NRF_ERROR_RESOURCES);
+    }
+    ret_code_t err_code = elite_srv_init();
+    APP_ERROR_CHECK(err_code);
+
+    elite_init();
+}
+
+ret_code_t le_data_notify(uint8_t *p_value, uint16_t len)
+{
+    ble_gatts_hvx_params_t hvx_params = {
+        .handle = elite_context.data_char_handle.value_handle,
+        .type   = BLE_GATT_HVX_NOTIFICATION,
+        .offset = 0,
+        .p_len  = &len,
+        .p_data = p_value,
+    };
+    return sd_ble_gatts_hvx(elite_context.conn_handle, &hvx_params);
+}
+
+ret_code_t le_data_update(uint8_t *p_value, uint16_t len)
+{
+    static uint8_t values[1 + NRF_SDH_BLE_GATT_MAX_MTU_SIZE - 3];
+
+    values[0] = len < 20 ? 20 : len;
+
+    memcpy(&values[1], p_value, len);
+
+    // update database.
+    ble_gatts_value_t gatts_value = {
+        .offset  = 0,
+        .len     = values[0] + 1,
+        .p_value = values,
+    };
+
+    uint32_t err_code = sd_ble_gatts_value_set(BLE_CONN_HANDLE_INVALID, elite_context.data_char_handle.value_handle, &gatts_value);
+
+    memset(&values[1], 0x00, len);
+
+    return err_code;
+}
+
+ret_code_t le_event_notify(uint8_t *p_value, uint16_t len)
+{
+    ble_gatts_hvx_params_t hvx_params = {
+        .handle = elite_context.event_char_handle.value_handle,
+        .type   = BLE_GATT_HVX_NOTIFICATION,
+        .offset = 0,
+        .p_len  = &len,
+        .p_data = p_value,
+    };
+    return sd_ble_gatts_hvx(elite_context.conn_handle, &hvx_params);
+}
+
+ret_code_t le_event_update(uint8_t *p_value, uint16_t len)
+{
+    // update database.
+    ble_gatts_value_t gatts_value = {
+        .offset  = 0,
+        .len     = len,
+        .p_value = p_value,
+    };
+    return sd_ble_gatts_value_set(BLE_CONN_HANDLE_INVALID, elite_context.event_char_handle.value_handle, &gatts_value);
+}
+
+ret_code_t le_event_async_notify(uint8_t *p_value, uint16_t len, uint32_t ms_to_wait)
+{
+    ret_code_t ret                      = NRF_SUCCESS;
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+
+    if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) == 0)
+    {
+        // not inside ISR (Thread mode)
+        if (ms_to_wait)
+        {
+            ret = xMessageBufferSend(async_notify_msg, p_value, len, pdMS_TO_TICKS(ms_to_wait)) == len ? NRF_SUCCESS : NRF_ERROR_BUSY;
+        }
+        else
+        {
+            taskENTER_CRITICAL();
+            ret = xMessageBufferSend(async_notify_msg, p_value, len, 0) == len ? NRF_SUCCESS : NRF_ERROR_BUSY;
+            taskEXIT_CRITICAL();
+        }
+    }
+    else
+    {
+        // inside  ISR
+        ret = xMessageBufferSendFromISR(async_notify_msg, p_value, len, &xHigherPriorityTaskWoken) == len ? NRF_SUCCESS : NRF_ERROR_BUSY;
+        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+    }
+    return ret;
+}
+
+bool is_ble_connected(void)
+{
+    return (elite_context.conn_handle != BLE_CONN_HANDLE_INVALID);
+}
+
+#endif // NRF_MODULE_ENABLED(BLE_ELITE)

app/src/le_gap.c

@@ -1,22 +1,18 @@
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "app_config.h"
-#include "apply_old_config.h"
-#include "sdk_config.h"
+#include <string.h>
 
-#include "nrf_sdh.h"
-#include "nrf_sdh_ble.h"
+#include "app_config.h"
+#include "app_error.h"
+#include "app_util.h"
+
+#include "ble_gap.h"
 
 #include "nrf_log.h"
-
-#include "app_error.h"
+#include "nrf_sdh_ble.h"
 
 #ifdef __cplusplus
 }
@@ -64,4 +60,4 @@ void le_gap_disconnect(uint16_t conn_handle, void *p_context)
     {
         NRF_LOG_DEBUG("Disconnected connection handle %d", conn_handle);
     }
-}
+}

app/src/le_gatt.c

@@ -1,28 +1,13 @@
-#include <stdbool.h>
-#include <stdint.h>
-
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
 #include "app_config.h"
-#include "apply_old_config.h"
-#include "sdk_config.h"
+#include "app_error.h"
 
-#include "nrf_log.h"
-#include "nrf_log_ctrl.h"
-#include "nrf_log_default_backends.h"
-
-#include "nrf_delay.h"
-#include "nrf_gpio.h"
-
-#include "nrf_sdh.h"
-#include "nrf_sdh_ble.h"
-#include "nrf_sdh_freertos.h"
-
-#include "ble_gatt.h"
 #include "nrf_ble_gatt.h"
+#include "nrf_sdh_ble.h"
 
 #ifdef __cplusplus
 }

app/src/le_srv.c

@@ -0,0 +1,58 @@
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <string.h>
+
+#include "app_config.h"
+#include "app_error.h"
+
+#include "ble_dis.h"
+#include "ble_srv_common.h"
+
+#include "le_uart_srv.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#define MANUFACTURER_NAME "Wisetop Technology Co." /**< Manufacturer. Will be passed to Device Information Service. */
+#define SERIAL_NUMBER     "0000-00-00-00001"
+#define MODEL_NUMBER      ELITE_HW_NAME
+#define HARDWARE_REVISION STRINGIFY(MAJOR_PRODUCT_NUMBER) "." STRINGIFY(MINOR_PRODUCT_NUMBER) "." STRINGIFY(MAJOR_VERSION_NUMBER) "." STRINGIFY(MINOR_VERSION_NUMBER)
+#define FIRMWARE_REVISION "0.1.0"
+
+static void le_dis_init(void)
+{
+    ble_dis_init_t dis_init;
+    ble_dis_sys_id_t sys_id;
+
+    memset(&dis_init, 0, sizeof(dis_init));
+    memset(&sys_id, 0, sizeof(sys_id));
+
+    ble_srv_ascii_to_utf8(&dis_init.manufact_name_str, MANUFACTURER_NAME);
+    ble_srv_ascii_to_utf8(&dis_init.fw_rev_str, FIRMWARE_REVISION);
+    ble_srv_ascii_to_utf8(&dis_init.hw_rev_str, HARDWARE_REVISION);
+    ble_srv_ascii_to_utf8(&dis_init.model_num_str, MODEL_NUMBER);
+    ble_srv_ascii_to_utf8(&dis_init.serial_num_str, SERIAL_NUMBER);
+    dis_init.p_sys_id        = &sys_id;
+    dis_init.dis_char_rd_sec = SEC_OPEN;
+
+    ret_code_t err_code = ble_dis_init(&dis_init);
+    APP_ERROR_CHECK(err_code);
+}
+
+void le_srv_init(void)
+{
+    le_dis_init();
+
+    extern void le_dfu_init(void);
+    le_dfu_init();
+
+    extern void le_elite_srv_init(void);
+    le_elite_srv_init(); // customer service
+
+    le_uart_srv_init(); // customer service
+}

app/src/le_uart_srv.c

@@ -0,0 +1,243 @@
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "app_error.h"
+#include "sdk_common.h"
+
+#include "ble.h"
+#include "ble_srv_common.h"
+#include "le_uart_srv.h"
+#include "uart_drv.h"
+
+#include "nrf_log.h"
+#include "nrf_sdh_ble.h"
+
+#include "FreeRTOS.h"
+#include "message_buffer.h"
+#include "task.h"
+
+#include <string.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#if NRF_MODULE_ENABLED(BLE_UART_SRV)
+
+#define BLE_UUID_UART_SERVICE   0xFFF8 /**< The UUID of the Service. */
+#define BLE_UUID_UART_RX_CHAR   0xFFF9 /**< The UUID of the RX Characteristic. */
+#define BLE_UUID_UART_TX_CHAR   0xFFFA /**< The UUID of the TX Characteristic. */
+#define BLE_UUID_UART_BAUD_CHAR 0xFFFB /**< The UUID of the Baud Characteristic. */
+
+#define BLE_UART_BASE_UUID                                                                                 \
+    {                                                                                                      \
+        {                                                                                                  \
+            0x9E, 0xCA, 0xDC, 0x24, 0x0E, 0xE5, 0xA9, 0xE0, 0x93, 0xF3, 0xA3, 0xB5, 0x00, 0x00, 0x40, 0x6E \
+        }                                                                                                  \
+    } /**< Used vendor specific UUID. */
+
+#define DEF_BAUD_RATE 115200
+
+typedef struct
+{
+    uint16_t conn_handle;
+    uint16_t service_handle;
+    ble_gatts_char_handles_t rx_handle;
+    ble_gatts_char_handles_t tx_handle;
+    ble_gatts_char_handles_t baud_handle;
+    bool tx_notify_enable;
+    uint8_t rx_buf[BLE_UART_MAX_DATA_LEN];
+    uint8_t tx_buf[BLE_UART_MAX_DATA_LEN];
+    uint32_t baudrate;
+} ble_uart_context_t;
+
+static ble_uart_context_t ble_uart_context = {
+    .conn_handle      = BLE_CONN_HANDLE_INVALID,
+    .tx_notify_enable = false,
+    .baudrate         = DEF_BAUD_RATE
+};
+
+static void on_connect(ble_evt_t const *p_ble_evt, ble_uart_context_t *p_context)
+{
+    taskENTER_CRITICAL();
+    p_context->conn_handle = p_ble_evt->evt.common_evt.conn_handle;
+    taskEXIT_CRITICAL();
+}
+
+static void on_disconnect(ble_evt_t const *p_ble_evt, ble_uart_context_t *p_context)
+{
+    taskENTER_CRITICAL();
+    p_context->conn_handle      = BLE_CONN_HANDLE_INVALID;
+    p_context->tx_notify_enable = false;
+    taskEXIT_CRITICAL();
+}
+
+static void ble_uart_ccc_update(ble_evt_t const *p_ble_evt, ble_uart_context_t *p_context)
+{
+    ble_gatts_evt_write_t const *p_evt_write = &p_ble_evt->evt.gatts_evt.params.write;
+    if (p_evt_write->handle == p_context->tx_handle.cccd_handle)
+    {
+        p_context->tx_notify_enable = ble_srv_is_notification_enabled(p_evt_write->data);
+        NRF_LOG_INFO("data_notify:%s", p_context->tx_notify_enable ? "enable" : "disable");
+    }
+}
+
+static void on_write(ble_evt_t const *p_ble_evt, ble_uart_context_t *p_context)
+{
+    ble_uuid_t uuid                          = p_ble_evt->evt.gatts_evt.params.write.uuid;
+    uint16_t handle                          = p_ble_evt->evt.gatts_evt.params.write.handle;
+    ble_gatts_evt_write_t const *p_evt_write = &p_ble_evt->evt.gatts_evt.params.write;
+    switch (uuid.uuid)
+    {
+        case BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG:
+            ble_uart_ccc_update(p_ble_evt, p_context);
+            break;
+
+        case BLE_UUID_UART_RX_CHAR:
+            NRF_LOG_INFO("RX:");
+            NRF_LOG_HEXDUMP_INFO(p_evt_write->data, p_evt_write->len);
+            uart_send((void *)p_evt_write->data, p_evt_write->len);
+            break;
+
+        case BLE_UUID_UART_BAUD_CHAR:
+            NRF_LOG_INFO("BAUD: %d", *(uint32_t *)p_evt_write->data);
+            uart_set_baud(*(uint32_t *)p_evt_write->data);
+            break;
+        default:
+            break;
+    }
+}
+
+static void on_hvx_tx_complete(ble_evt_t const *p_ble_evt, ble_uart_context_t *p_context)
+{
+    // TODO...
+}
+
+static void on_ble_evt_handler(ble_evt_t const *p_ble_evt, void *p_context)
+{
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_CONNECTED:
+            on_connect(p_ble_evt, p_context);
+            break;
+        case BLE_GAP_EVT_DISCONNECTED:
+            on_disconnect(p_ble_evt, p_context);
+            break;
+        case BLE_GATTS_EVT_WRITE:
+            on_write(p_ble_evt, p_context);
+            break;
+        case BLE_GATTS_EVT_HVN_TX_COMPLETE:
+            on_hvx_tx_complete(p_ble_evt, p_context);
+        default:
+            // No implementation needed.
+            break;
+    }
+}
+
+static ret_code_t add_rx_characteristic(uint16_t uuid, uint8_t uuid_type, ble_uart_context_t *context)
+{
+    ble_add_char_params_t add_char_params;
+    memset(&add_char_params, 0, sizeof(add_char_params));
+    add_char_params.uuid                     = uuid;
+    add_char_params.uuid_type                = uuid_type;
+    add_char_params.max_len                  = sizeof(context->rx_buf);
+    add_char_params.init_len                 = 0;
+    add_char_params.p_init_value             = (void *)context->rx_buf;
+    add_char_params.is_var_len               = true;
+    add_char_params.write_access             = SEC_OPEN;
+    add_char_params.char_props.write         = 1;
+    add_char_params.char_props.write_wo_resp = 1;
+    add_char_params.read_access              = SEC_OPEN;
+    add_char_params.char_props.read          = 1;
+    ret_code_t err_code                      = characteristic_add(context->service_handle, &add_char_params, &context->rx_handle);
+    return err_code;
+}
+
+static ret_code_t add_tx_characteristic(uint16_t uuid, uint8_t uuid_type, ble_uart_context_t *context)
+{
+    ble_add_char_params_t add_char_params;
+    memset(&add_char_params, 0, sizeof(add_char_params));
+    add_char_params.uuid              = uuid;
+    add_char_params.uuid_type         = uuid_type;
+    add_char_params.max_len           = sizeof(context->tx_buf);
+    add_char_params.init_len          = 0;
+    add_char_params.p_init_value      = (void *)context->tx_buf;
+    add_char_params.is_value_user     = true;
+    add_char_params.is_var_len        = true;
+    add_char_params.read_access       = SEC_OPEN;
+    add_char_params.char_props.read   = 1;
+    add_char_params.cccd_write_access = SEC_OPEN;
+    add_char_params.char_props.notify = 1;
+    ret_code_t err_code               = characteristic_add(context->service_handle, &add_char_params, &context->tx_handle);
+    return err_code;
+}
+
+static ret_code_t add_baud_characteristic(uint16_t uuid, uint8_t uuid_type, ble_uart_context_t *context)
+{
+    ble_add_char_params_t add_char_params;
+    memset(&add_char_params, 0, sizeof(add_char_params));
+    add_char_params.uuid             = uuid;
+    add_char_params.uuid_type        = uuid_type;
+    add_char_params.max_len          = sizeof(context->baudrate);
+    add_char_params.init_len         = sizeof(context->baudrate);
+    add_char_params.p_init_value     = (void *)&context->baudrate;
+    add_char_params.is_value_user    = true;
+    add_char_params.is_var_len       = false;
+    add_char_params.write_access     = SEC_OPEN;
+    add_char_params.char_props.write = 1;
+    add_char_params.read_access      = SEC_OPEN;
+    add_char_params.char_props.read  = 1;
+    ret_code_t err_code              = characteristic_add(context->service_handle, &add_char_params, &context->baud_handle);
+    return err_code;
+}
+
+void le_uart_srv_init(void)
+{
+    ret_code_t err_code;
+    uint8_t uuid_type = 0;
+
+    /**@snippet [Adding proprietary Service to the SoftDevice] */
+
+    ble_uuid_t ble_uuid = {
+        .type = BLE_UUID_TYPE_BLE,
+        .uuid = BLE_UUID_UART_SERVICE,
+    };
+
+    // Add the service.
+    err_code = sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY,
+                                        &ble_uuid,
+                                        &ble_uart_context.service_handle);
+    APP_ERROR_CHECK(err_code);
+
+    // Add rx char
+    err_code = add_rx_characteristic(BLE_UUID_UART_RX_CHAR, ble_uuid.type, &ble_uart_context);
+    APP_ERROR_CHECK(err_code);
+
+    // Add tx char
+    err_code = add_tx_characteristic(BLE_UUID_UART_TX_CHAR, ble_uuid.type, &ble_uart_context);
+    APP_ERROR_CHECK(err_code);
+
+    // Add baud char
+    err_code = add_baud_characteristic(BLE_UUID_UART_BAUD_CHAR, ble_uuid.type, &ble_uart_context);
+    APP_ERROR_CHECK(err_code);
+
+    // Register a handler for BLE events.
+    NRF_SDH_BLE_OBSERVER(m_ble_uart_observer, BLE_UART_OBSERVER_PRIO, on_ble_evt_handler, &ble_uart_context);
+}
+
+ret_code_t le_uart_notify(uint8_t *p_value, uint16_t len)
+{
+    ble_gatts_hvx_params_t hvx_params = {
+        .handle = ble_uart_context.tx_handle.value_handle,
+        .type   = BLE_GATT_HVX_NOTIFICATION,
+        .offset = 0,
+        .p_len  = &len,
+        .p_data = p_value,
+    };
+    return sd_ble_gatts_hvx(ble_uart_context.conn_handle, &hvx_params);
+}
+
+#endif

app/src/led_drv.c

@@ -0,0 +1,89 @@
+#include "app_config.h"
+#if (DEF_LED_DRV_ENABLED)
+#include "led_drv.h"
+
+#include "nrf_log.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+#if (DEF_APA102_2020_ENABLED)
+#include "apa102_2020.h"
+static const led_drv_if_t *p_inst = &apa102_drv;
+
+#elif (DEF_RGB_ENABLED)
+#include "led_rgb.h"
+static const led_drv_if_t *p_inst = &led_rgb_drv;
+
+#else
+static led_drv_if_t *p_inst = NULL;
+#endif
+
+int32_t led_set(struct led_color color)
+{
+    if (p_inst == NULL)
+    {
+        return LED_DRV_ERROR;
+    }
+
+    if (p_inst->set != NULL)
+    {
+        for (int i = 0; i < DEF_LED_COUNT; i++)
+        {
+            p_inst->set(i, color, 1);
+        }
+        return LED_DRV_SUCCESS;
+    }
+
+    return LED_DRV_SUCCESS;
+}
+
+int32_t led_single_led_set(uint32_t idx, struct led_color color, uint8_t brightness)
+{
+    if (p_inst == NULL)
+    {
+        return LED_DRV_ERROR;
+    }
+
+    if (p_inst->set != NULL)
+    {
+        p_inst->set(idx, color, brightness);
+        return LED_DRV_SUCCESS;
+    }
+
+    return LED_DRV_SUCCESS;
+}
+
+int32_t led_init(void)
+{
+    if (p_inst == NULL)
+    {
+        return LED_DRV_ERROR;
+    }
+
+    return p_inst->init(DEF_LED_COUNT);
+}
+
+int32_t led_as_rainbow(void)
+{
+    uint8_t color_idx;
+
+#if (DEF_APA102_2020_ENABLED)
+    struct led_color color[6] = { LED_RED, LED_ORANGE, LED_YELLOW, LED_GREEN, LED_BLUE, LED_PURPLE };
+#endif
+
+#if (DEF_RGB_ENABLED)
+    struct led_color color[6] = { LED_RED, LED_YELLOW, LED_GREEN, LED_CYAN, LED_BLUE, LED_PURPLE };
+#endif
+
+    for (int i = 0; i < DEF_LED_COUNT; i++)
+    {
+        color_idx = i % COUNT_ARRAY_SIZE(color);
+        led_single_led_set(i, color[color_idx], 1);
+    }
+
+    return 0;
+}
+
+#endif /* ! DEF_LED_DRV_ENABLED */

app/src/led_rgb.c

@@ -0,0 +1,47 @@
+
+#include "app_config.h"
+
+#if (DEF_RGB_ENABLED)
+#include "led_rgb.h"
+
+#include "elite_board.h"
+
+#include "nrf_gpio.h"
+
+static const uint32_t r_pins[DEF_LED_COUNT] = LED_R_PINS;
+static const uint32_t g_pins[DEF_LED_COUNT] = LED_G_PINS;
+static const uint32_t b_pins[DEF_LED_COUNT] = LED_B_PINS;
+static uint32_t led_count                   = 0;
+
+int32_t rgb_led_set(uint32_t idx, struct led_color color, uint8_t brightness)
+{
+    if (idx >= led_count) return 1;
+    nrf_gpio_pin_write(r_pins[idx], color.R ? 0 : 1);
+    nrf_gpio_pin_write(g_pins[idx], color.G ? 0 : 1);
+    nrf_gpio_pin_write(b_pins[idx], color.B ? 0 : 1);
+    return 0;
+}
+
+int32_t rgb_init(uint32_t cnt)
+{
+    led_count = cnt;
+    for (uint8_t i = 0; i < led_count; i++)
+    {
+        nrf_gpio_cfg_output(r_pins[i]);
+        nrf_gpio_cfg_output(g_pins[i]);
+        nrf_gpio_cfg_output(b_pins[i]);
+        /* all dark */
+        nrf_gpio_pin_set(r_pins[i]);
+        nrf_gpio_pin_set(g_pins[i]);
+        nrf_gpio_pin_set(b_pins[i]);
+    }
+
+    return 0;
+}
+
+const led_drv_if_t led_rgb_drv = {
+    .init = rgb_init,
+    .set  = rgb_led_set,
+};
+
+#endif /* ! DEF_RGB_ENABLED */

app/src/main.c

@@ -7,25 +7,18 @@ extern "C"
 #endif
 
 #include "app_config.h"
-#include "apply_old_config.h"
+#include "elite_board.h"
 #include "sdk_config.h"
 
 #include "nrf_log.h"
 #include "nrf_log_ctrl.h"
 #include "nrf_log_default_backends.h"
-
-#include "nrf_delay.h"
-#include "nrf_gpio.h"
-
 #include "nrf_sdh.h"
 #include "nrf_sdh_ble.h"
 #include "nrf_sdh_freertos.h"
 
-#include "FreeRTOS.h"
-#include "task.h"
-#include "timers.h"
-
-#include "led.h"
+#include "nrf_drv_clock.h"
+#include "nrf_drv_power.h"
 
 #ifdef __cplusplus
 }
@@ -45,18 +38,18 @@ static void le_evt_handler(ble_evt_t const *p_ble_evt, void *p_context)
         case BLE_GAP_EVT_CONN_PARAM_UPDATE:
             NRF_LOG_INFO("Connection parameters updated.");
             break;
-        case BLE_GAP_EVT_CONNECTED: {
+        case BLE_GAP_EVT_CONNECTED:
             NRF_LOG_INFO("Connect to peer.");
             err_code = sd_ble_gap_tx_power_set(BLE_GAP_TX_POWER_ROLE_CONN, p_ble_evt->evt.gap_evt.conn_handle, 8);
             APP_ERROR_CHECK(err_code);
-        }
-        break;
-        case BLE_GAP_EVT_DISCONNECTED: {
+            led_set(LED_IDLE_CONNECTED);
+            break;
+        case BLE_GAP_EVT_DISCONNECTED:
             NRF_LOG_INFO("Disconnect from peer.");
             err_code = sd_ble_gap_tx_power_set(BLE_GAP_TX_POWER_ROLE_ADV, p_ble_evt->evt.gap_evt.conn_handle, 0);
             APP_ERROR_CHECK(err_code);
-        }
-        break;
+            led_set(LED_IDLE_DISCONNECTED);
+            break;
         case BLE_GAP_EVT_PHY_UPDATE_REQUEST: {
             NRF_LOG_INFO("PHY update response. (AUTO)");
             ble_gap_phys_t const phys = {
@@ -105,108 +98,20 @@ static void le_stack_Init(void)
     NRF_SDH_BLE_OBSERVER(m_ble_observer, APP_BLE_OBSERVER_PRIO, le_evt_handler, NULL);
 }
 
-/* edc2.0 pin */
-#define ADCA2_PIN        NRF_GPIO_PIN_MAP(0, 25)
-#define ADCA1_PIN        NRF_GPIO_PIN_MAP(0, 19)
-#define ADCA0_PIN        NRF_GPIO_PIN_MAP(0, 21)
-#define RST_SW_PIN       NRF_GPIO_PIN_MAP(0, 17)
-#define CS_SW_PIN        NRF_GPIO_PIN_MAP(0, 20)
-#define OFF_PIN          NRF_GPIO_PIN_MAP(0, 15)
-#define SHUT_DOWN_PIN    NRF_GPIO_PIN_MAP(1, 8)
-#define CS_MEM_PIN       NRF_GPIO_PIN_MAP(0, 8)
-#define CS_ADC_PIN       NRF_GPIO_PIN_MAP(0, 6)
-#define CS_DAC_PIN       NRF_GPIO_PIN_MAP(0, 5)
-#define INT9466_PIN      NRF_GPIO_PIN_MAP(0, 27)
-#define Vout_FB_PIN      NRF_GPIO_PIN_MAP(0, 26)
-#define Vout_IN_PIN      NRF_GPIO_PIN_MAP(0, 4)
-#define LEDTH_PIN        NRF_GPIO_PIN_MAP(0, 28)
-#define Iin4_TEST_PIN    NRF_GPIO_PIN_MAP(1, 12)
-#define Iin3_SEL_PIN     NRF_GPIO_PIN_MAP(1, 14)
-#define VBAT_PIN         NRF_GPIO_PIN_MAP(0, 3)
-#define Iin3_PIN         NRF_GPIO_PIN_MAP(1, 13)
-#define Iin2_PIN         NRF_GPIO_PIN_MAP(1, 3)
-#define Iin1_PIN         NRF_GPIO_PIN_MAP(1, 10)
-#define Vin2_PIN         NRF_GPIO_PIN_MAP(1, 6)
-#define Vin1_PIN         NRF_GPIO_PIN_MAP(1, 11)
-#define POWER_5V_EN_PIN  NRF_GPIO_PIN_MAP(0, 24)
-#define POWER_12V_EN_PIN NRF_GPIO_PIN_MAP(0, 23)
-#define CV_CTRL_PIN      NRF_GPIO_PIN_MAP(0, 16)
-
-void gpio_init(void)
-{
-    nrf_gpio_cfg_output(POWER_5V_EN_PIN);
-    nrf_gpio_cfg_output(POWER_12V_EN_PIN);
-    nrf_gpio_cfg_output(OFF_PIN);
-    nrf_gpio_cfg_output(Vout_FB_PIN);
-    nrf_gpio_cfg_output(Vout_IN_PIN);
-    nrf_gpio_cfg_output(Iin4_TEST_PIN);
-    nrf_gpio_cfg_output(Iin3_SEL_PIN);
-    nrf_gpio_cfg_output(Iin3_PIN);
-    nrf_gpio_cfg_output(Iin2_PIN);
-    nrf_gpio_cfg_output(Iin1_PIN);
-    nrf_gpio_cfg_output(Vin2_PIN);
-    nrf_gpio_cfg_output(Vin1_PIN);
-    nrf_gpio_cfg_output(CV_CTRL_PIN);
-    nrf_gpio_cfg_output(ADCA2_PIN);
-    nrf_gpio_cfg_output(ADCA1_PIN);
-    nrf_gpio_cfg_output(ADCA0_PIN);
-    nrf_gpio_cfg_output(RST_SW_PIN);
-    nrf_gpio_cfg_output(CS_SW_PIN);
-    nrf_gpio_cfg_output(CS_MEM_PIN);
-    nrf_gpio_cfg_output(CS_ADC_PIN);
-    nrf_gpio_cfg_output(CS_DAC_PIN);
-
-    nrf_gpio_cfg_input(VBAT_PIN, NRF_GPIO_PIN_NOPULL);
-    nrf_gpio_cfg_input(SHUT_DOWN_PIN, NRF_GPIO_PIN_NOPULL);
-    nrf_gpio_cfg_input(INT9466_PIN, NRF_GPIO_PIN_NOPULL);
-
-    nrf_gpio_pin_set(POWER_5V_EN_PIN);
-    nrf_gpio_pin_set(POWER_12V_EN_PIN);
-    nrf_gpio_pin_set(OFF_PIN); // disable 6994
-    nrf_gpio_pin_set(CS_SW_PIN);
-    nrf_gpio_pin_set(CS_MEM_PIN);
-    nrf_gpio_pin_set(CS_ADC_PIN);
-    nrf_gpio_pin_set(CS_DAC_PIN);
-
-    nrf_gpio_pin_clear(Vout_FB_PIN);
-    nrf_gpio_pin_clear(Vout_IN_PIN);
-    nrf_gpio_pin_clear(Iin4_TEST_PIN);
-    nrf_gpio_pin_clear(Iin3_SEL_PIN);
-    nrf_gpio_pin_clear(Iin3_PIN);
-    nrf_gpio_pin_clear(Iin2_PIN);
-    nrf_gpio_pin_clear(Iin1_PIN);
-    nrf_gpio_pin_clear(Vin2_PIN);
-    nrf_gpio_pin_clear(Vin1_PIN);
-    nrf_gpio_pin_clear(CV_CTRL_PIN);
-    nrf_gpio_pin_clear(ADCA2_PIN);
-    nrf_gpio_pin_clear(ADCA1_PIN);
-    nrf_gpio_pin_clear(ADCA0_PIN);
-    nrf_gpio_pin_clear(RST_SW_PIN);
-}
-
-static void enable_6994_callback(void *pvParameter)
-{
-    nrf_gpio_pin_clear(OFF_PIN); // enable 6994
-    NRF_LOG_INFO("enable 6994");
-}
-
 static void nrf_sdh_freertos_task_hook(void *p_context)
 {
-    extern void twi0_init(void);
-    extern void spi_init(void);
-
     UNUSED_PARAMETER(p_context);
 
-    twi0_init();
-    spi_init();
-    gpio_init();
-    led_init();
+    elite_board_init();
 
-    NRF_LOG_INFO("LED_GREEN");
-    for (int i = 0; i < 12; i++)
+#if DEF_ELITE_DEMO_WO_SOFTDEVICE
+    elite_board_demo();
+    for (;;)
     {
-        led_set(i, LED_GREEN, 1);
     }
+#endif
+
+    elite_drv_init();
 
     le_stack_Init(); // enable ble stack, but unscannable!! register "le_evt_handler" handle(CB)
 
@@ -222,10 +127,9 @@ static void nrf_sdh_freertos_task_hook(void *p_context)
     extern void le_adv_init(uint8_t ble_conn_cfg_tag);
     le_adv_init(APP_BLE_CONN_CFG_TAG); // could be scanned
 
-    /* Start timer to call enable_6994_callback() */
-    TimerHandle_t timer_handle;                                                            /**< Reference to counter FreeRTOS timer. */
-    timer_handle = xTimerCreate("enable 6994", 1000, pdFALSE, NULL, enable_6994_callback); // 1000ms no repeat
-    xTimerStart(timer_handle, 0);
+#if DEF_ELITE_DEMO_W_SOFTDEVICE
+    elite_board_demo();
+#endif
 }
 
 int main(void)
@@ -233,6 +137,10 @@ int main(void)
     NRF_LOG_INIT(NULL, 0);
     NRF_LOG_DEFAULT_BACKENDS_INIT();
     NRF_LOG_INFO("%s Build: %s %s", ELITE_DEVICE_NAME, __TIME__, __DATE__);
+    NRF_LOG_INFO("[Board] HW ver: %d.%d.%d.%d(%s)", MAJOR_PRODUCT_NUMBER, MINOR_PRODUCT_NUMBER, MAJOR_VERSION_NUMBER, MINOR_VERSION_NUMBER, ELITE_HW_NAME);
+
+    nrf_drv_power_init(NULL);
+    nrf_drv_clock_init();
 
     nrf_sdh_freertos_init(nrf_sdh_freertos_task_hook, NULL); // create event: softdevice_task - wireless protocal stack
 

app/src/max14802.c

@@ -0,0 +1,190 @@
+#include "max14802.h"
+#include "elite_board.h"
+
+#include "nrf_delay.h"
+#include "nrf_gpio.h"
+
+#include "string.h"
+
+#pragma GCC optimize("O2")
+
+#if (DEF_MAX14802_ENABLED)
+
+static sw_t m_sw = { .val = UINT64_MAX };
+
+#define EXCLUDE_IO_ENABLE  1
+#define EXCLUDE_IO_DISABLE 0
+
+static const uint32_t exclude_io[64] = {
+    ADPT0_S1_PIN,
+    ADPT0_S2_PIN,
+    ADPT0_S3_PIN,
+    ADPT0_S4_PIN,
+    ADPT1_S1_PIN,
+    ADPT1_S2_PIN,
+    ADPT1_S3_PIN,
+    ADPT1_S4_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+};
+
+static void shift_out(uint8_t *p, uint32_t len)
+{
+    nrf_gpio_pin_set(ADPT_LE_PIN);
+
+    for (int32_t j = len; j > 0; j--)
+    {
+        uint32_t val = p[j - 1];
+        for (uint32_t i = 0x01 << (SW_PER_BYTE - 1); i > 0; i >>= 1)
+        {
+            nrf_gpio_pin_clear(ADPT_CLK_PIN);
+            nrf_gpio_pin_write(ADPT_DIN_PIN, val & i);
+            nrf_gpio_pin_set(ADPT_CLK_PIN);
+            nrf_gpio_pin_write(ADPT_DIN_PIN, val & i);
+        }
+    }
+
+    nrf_gpio_pin_clear(ADPT_CLK_PIN);
+    nrf_gpio_pin_clear(ADPT_DIN_PIN);
+    nrf_gpio_pin_clear(ADPT_LE_PIN);
+    nrf_gpio_pin_set(ADPT_LE_PIN);
+}
+
+int max14802_reset(void)
+{
+    m_sw.val = 0;
+    shift_out((uint8_t *)&m_sw.val, SW_TOTAL_COUNT / SW_PER_BYTE);
+    return 0;
+}
+
+int max14802_write(sw_t sw_mask)
+{
+    if (m_sw.val != sw_mask.val)
+    {
+        m_sw = sw_mask;
+
+        // Disable A1_AOUT,A2_AOUT,B1_AOUT, .... B3_AOUT, B4_AOUT
+
+        for (uint32_t i = 0; i < SW_TOTAL_COUNT; i++)
+        {
+            nrf_gpio_pin_write(exclude_io[i], EXCLUDE_IO_DISABLE);
+        }
+
+        nrf_delay_ms(1);
+
+        // Set max14082
+        shift_out((uint8_t *)&m_sw.val, SW_TOTAL_COUNT / SW_PER_BYTE);
+
+        // Enable A1_AOUT,A2_AOUT,B1_AOUT, .... B3_AOUT, B4_AOUT are all disable when all max14082 off
+
+        if (m_sw.val == 0)
+        {
+            nrf_delay_ms(1);
+            for (uint32_t i = 0; i < SW_TOTAL_COUNT; i++)
+            {
+                nrf_gpio_pin_write(exclude_io[i], EXCLUDE_IO_ENABLE);
+            }
+        }
+    }
+
+    return 0;
+}
+
+int max14802_read(sw_t *p_sw_mask)
+{
+    *p_sw_mask = m_sw;
+    return 0;
+}
+int max14802_get_sw_count(uint32_t *p_sw_count)
+{
+    *p_sw_count = SW_TOTAL_COUNT;
+    return 0;
+}
+
+int max14802_init(void)
+{
+    nrf_gpio_pin_set(ADPT_CLR_PIN);
+    nrf_gpio_pin_set(ADPT_LE_PIN);
+    nrf_gpio_pin_clear(ADPT_CLK_PIN);
+    nrf_gpio_pin_clear(ADPT_DIN_PIN);
+
+    nrf_gpio_cfg_output(ADPT_CLR_PIN);
+    nrf_gpio_cfg_output(ADPT_LE_PIN);
+    nrf_gpio_cfg_output(ADPT_CLK_PIN);
+    nrf_gpio_cfg_output(ADPT_DIN_PIN);
+
+    for (uint32_t i = 0; i < COUNTOF(exclude_io); i++)
+    {
+        nrf_gpio_pin_write(exclude_io[i], EXCLUDE_IO_DISABLE);
+    }
+
+    max14802_write((sw_t) { .val = 0 });
+
+    nrf_gpio_pin_clear(ADPT_CLR_PIN);
+
+    return 0;
+}
+
+const sw_drv_if_t max14802 = {
+    .init         = max14802_init,
+    .reset        = max14802_reset,
+    .write        = max14802_write,
+    .read         = max14802_read,
+    .get_sw_count = max14802_get_sw_count,
+};
+
+#endif

app/src/max5136.c

@@ -0,0 +1,133 @@
+#include "max5136.h"
+
+
+#include "dac_drv_if.h"
+
+#include "nrf_log.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if (DEF_MAX5136_ENABLED)
+#define MAX5136_NOP_MODE           (0x00 << 0)
+#define MAX5136_LDAC_MODE          (0x01 << 0)
+#define MAX5136_CLR_MODE           (0x02 << 0)
+#define MAX5136_PWR_CTRL_MODE      (0x03 << 0)
+#define MAX5136_LINEARITY_MODE     (0x05 << 0)
+#define MAX5136_WRITE_MODE         (0x01 << 4)
+#define MAX5136_WRITE_THROUGH_MODE (0x03 << 4)
+
+#define MAX5136_LINEARITY_SET      (0b1000000000)
+#define MAX5136_LINEARITY_CLR      (0b0000000000)
+
+typedef struct __PACKED
+{
+    uint8_t ctrl_bits;
+    uint16_t data_bits;
+} max5136_opcode_t;
+
+static int max5136_ldac_mode(uint32_t channel_mask)
+{
+    /*
+        Move contents of input to DAC registers indicated by 1's.
+        No effect on registers indicated by 0's.
+    */
+    max5136_opcode_t op_code = {
+        .ctrl_bits = MAX5136_LDAC_MODE,
+        .data_bits = __REVSH((channel_mask & 0b1111) << 8),
+    };
+    spim_xfer(CS_DAC_PIN, NRF_SPIM_MODE_2, (uint8_t *)&op_code, sizeof(op_code), NULL, 0);
+    return 0;
+}
+
+static int max5136_power_control_mode(uint32_t channel_mask, uint32_t ready_enable)
+{
+    /*
+        Power down DACs indicated by 1's.
+        Set READY_EN = 1 to enable READY.
+    */
+    max5136_opcode_t op_code = {
+        .ctrl_bits = MAX5136_PWR_CTRL_MODE | (channel_mask & 0b1111),
+        .data_bits = __REVSH(((channel_mask & 0b1111) << 8) | (ready_enable == 0 ? 0 : 1)),
+    };
+    spim_xfer(CS_DAC_PIN, NRF_SPIM_MODE_2, (uint8_t *)&op_code, sizeof(op_code), NULL, 0);
+    return 0;
+}
+
+static int max5136_write_mode(uint32_t channel_mask, int32_t dac_val)
+{
+    /*
+        Write to selected input  registers (DAC output not affected).
+    */
+    max5136_opcode_t op_code = {
+        .ctrl_bits = MAX5136_WRITE_MODE | (channel_mask & 0b1111),
+        .data_bits = __REVSH(dac_val),
+    };
+    spim_xfer(CS_DAC_PIN, NRF_SPIM_MODE_2, (uint8_t *)&op_code, sizeof(op_code), NULL, 0);
+    return 0;
+}
+
+static int max5136_write_through_mode(uint32_t channel_mask, int32_t dac_val)
+{
+    /*
+        Write to selected input and DAC registers,  DAC outputs updated (writethrough).
+    */
+    max5136_opcode_t op_code = {
+        .ctrl_bits = MAX5136_WRITE_THROUGH_MODE | (channel_mask & 0b1111),
+        .data_bits = __REVSH(dac_val),
+    };
+    spim_xfer(CS_DAC_PIN, NRF_SPIM_MODE_2, (uint8_t *)&op_code, sizeof(op_code), NULL, 0);
+    return 0;
+}
+
+static void max5136_linearity(void)
+{
+    /*
+        To guarantee DAC linearity, wait until the supplies have
+        settled. Set the LIN bit in the DAC linearity register; wait
+        10ms, and clear the LIN bit.
+    */
+    max5136_opcode_t op_code = { .ctrl_bits = MAX5136_LINEARITY_MODE };
+
+    op_code.data_bits = __REVSH(MAX5136_LINEARITY_SET);
+    spim_xfer(CS_DAC_PIN, NRF_SPIM_MODE_2, (uint8_t *)&op_code, sizeof(op_code), NULL, 0);
+
+    vTaskDelay(pdMS_TO_TICKS(10));
+
+    op_code.data_bits = __REVSH(MAX5136_LINEARITY_CLR);
+    spim_xfer(CS_DAC_PIN, NRF_SPIM_MODE_2, (uint8_t *)&op_code, sizeof(op_code), NULL, 0);
+}
+
+static int max5136_soft_reset(void)
+{
+    /*
+        The software clear command acts as a  software POR,
+        erasing the contents of all registers. All outputs
+        return to the state determined by the M/Z input.
+    */
+
+    max5136_opcode_t op_code = {
+        .ctrl_bits = MAX5136_CLR_MODE,
+        .data_bits = 0,
+    };
+    spim_xfer(CS_DAC_PIN, NRF_SPIM_MODE_2, (uint8_t *)&op_code, sizeof(op_code), NULL, 0);
+    return 0;
+}
+
+static int max5136_init(void)
+{
+    max5136_soft_reset();
+    max5136_linearity();
+    return 0;
+}
+
+dac_drv_if_t max5316_drv = {
+    .init               = max5136_init,
+    .ldac_mode          = max5136_ldac_mode,
+    .reset              = max5136_soft_reset,
+    .power_control_mode = max5136_power_control_mode,
+    .write_mode         = max5136_write_mode,
+    .write_through_mode = max5136_write_through_mode,
+};
+
+#endif /* !DEF_MAX5136_ENABLED */

app/src/nrf5x.xml

@@ -2,9 +2,9 @@
 <EmbeddedProfile xmlns:xsd="http://www.w3.org/2001/XMLSchema" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
   <ToolchainID>com.visualgdb.arm-eabi</ToolchainID>
   <ToolchainVersion>
-    <GCC>12.3.1</GCC>
-    <GDB>13.2</GDB>
-    <Revision>1</Revision>
+    <GCC>14.2.1</GCC>
+    <GDB>15.2</GDB>
+    <Revision>2</Revision>
   </ToolchainVersion>
   <BspID>com.sysprogs.arm.nordic.nrf5x</BspID>
   <BspVersion>17.0</BspVersion>
@@ -18,7 +18,7 @@
       </KeyValue>
       <KeyValue>
         <Key>com.sysprogs.bspoptions.nrf5x.pinreset</Key>
-        <Value>CONFIG_GPIO_AS_PINRESET</Value>
+        <Value />
       </KeyValue>
       <KeyValue>
         <Key>com.sysprogs.bspoptions.primary_memory</Key>
@@ -53,32 +53,33 @@
   <BSPSourceFolderName>Device-specific files</BSPSourceFolderName>
   <MCUMakFile>nrf5x.mak</MCUMakFile>
   <ReferencedFrameworks>
+    <string>com.sysprogs.arm.nordic.nrf5x.periph_legacy</string>
     <string>com.sysprogs.arm.nordic.nrf5x.util</string>
-    <string>com.sysprogs.arm.nordic.nrf5x.drivers_nrf</string>
     <string>com.sysprogs.arm.nordic.nrf5x.libraries</string>
     <string>com.sysprogs.arm.nordic.nrf5x.modules_nrfx</string>
-    <string>com.sysprogs.arm.nordic.nrf5x.periph_legacy</string>
+    <string>com.sysprogs.arm.nordic.nrf5x.drivers_nrf</string>
   </ReferencedFrameworks>
   <FrameworkProperties>
     <Entries>
       <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.nrf_soc_nosd</Key>
-      </KeyValue>
-      <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.radio_config</Key>
-      </KeyValue>
-      <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.sdio</Key>
-      </KeyValue>
-      <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.spi_master</Key>
-      </KeyValue>
-      <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.twi_master</Key>
+        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.spi</Key>
         <Value>none</Value>
       </KeyValue>
+      <KeyValue>
+        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.swi</Key>
+      </KeyValue>
+      <KeyValue>
+        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.twi</Key>
+      </KeyValue>
+      <KeyValue>
+        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.uart</Key>
+      </KeyValue>
+      <KeyValue>
+        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.clock</Key>
+      </KeyValue>
       <KeyValue>
         <Key>com.sysprogs.bspoptions.nrf5x.libraries.atomic_fifo</Key>
+        <Value>yes</Value>
       </KeyValue>
       <KeyValue>
         <Key>com.sysprogs.bspoptions.nrf5x.libraries.atomic_flags</Key>
@@ -246,27 +247,28 @@
       </KeyValue>
       <KeyValue>
         <Key>com.sysprogs.bspoptions.nrf5x.libraries.usbd</Key>
+        <Value />
       </KeyValue>
       <KeyValue>
         <Key>com.sysprogs.bspoptions.nrf5x.libraries.fprintf</Key>
         <Value>yes</Value>
       </KeyValue>
       <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.spi</Key>
+        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.nrf_soc_nosd</Key>
+      </KeyValue>
+      <KeyValue>
+        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.radio_config</Key>
+      </KeyValue>
+      <KeyValue>
+        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.sdio</Key>
+      </KeyValue>
+      <KeyValue>
+        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.spi_master</Key>
+      </KeyValue>
+      <KeyValue>
+        <Key>com.sysprogs.bspoptions.nrf5x.drivers_nrf.twi_master</Key>
         <Value>none</Value>
       </KeyValue>
-      <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.swi</Key>
-      </KeyValue>
-      <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.twi</Key>
-      </KeyValue>
-      <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.uart</Key>
-      </KeyValue>
-      <KeyValue>
-        <Key>com.sysprogs.bspoptions.nrf5x.legacy_drivers.clock</Key>
-      </KeyValue>
     </Entries>
   </FrameworkProperties>
   <TestFrameworkProperties>

app/src/private.pem

@@ -0,0 +1,5 @@
+-----BEGIN EC PRIVATE KEY-----
+MHcCAQEEIEM6TVi/ofxCYEb2O9OYK4sNHlpwd0ZrW3yFOIeRJKqKoAoGCCqGSM49
+AwEHoUQDQgAEYUIRVGOQwmOEfsuYSufu4hHxRsQSUzh9lMBkvc3ewrPkpbfiXfa/
+vGyIM8HAY2Jemux9+FyFERXRjgj5RxOJAA==
+-----END EC PRIVATE KEY-----

app/src/sw_drv.c

@@ -0,0 +1,67 @@
+#include "sw_drv.h"
+
+#if (DEF_ADGS1412_ENABLED)
+
+#include "adgs1412.h"
+const sw_drv_if_t *p_inst = &adgs1412;
+
+#elif (DEF_MAX14802_ENABLED)
+
+#include "max14802.h"
+const sw_drv_if_t *p_inst = &max14802;
+
+#else
+
+const sw_drv_if_t *p_inst = NULL;
+
+#endif /* ! DEF_ADGS1412_ENABLED */
+
+#if (DEF_SW_DRV_ENABLED)
+
+int sw_init(void)
+{
+    if (p_inst == NULL)
+    {
+        return SW_DRV_ERROR;
+    }
+    return p_inst->init();
+}
+
+int sw_reset(void)
+{
+    if (p_inst == NULL)
+    {
+        return SW_DRV_ERROR;
+    }
+    return p_inst->reset();
+}
+
+int sw_write(sw_t sw_mask)
+{
+    if (p_inst == NULL)
+    {
+        return SW_DRV_ERROR;
+    }
+    return p_inst->write(sw_mask);
+}
+
+int sw_read(sw_t *p_sw_mask)
+{
+    if (p_inst == NULL)
+    {
+        return SW_DRV_ERROR;
+    }
+    return p_inst->read(p_sw_mask);
+}
+
+
+int sw_count(uint32_t *p_sw_count)
+{
+    if (p_inst == NULL)
+    {
+        return SW_DRV_ERROR;
+    }
+    return p_inst->get_sw_count(p_sw_count);
+}
+
+#endif /* ! DEF_SW_DRV_ENABLED */

app/src/tw1508.c

@@ -0,0 +1,49 @@
+#include "tw1508.h"
+
+#include "nrf_delay.h"
+#include "nrf_log.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if (DEF_TW1508_ENABLED)
+
+void tw1508_set(uint16_t out_0, uint16_t out_1)
+{
+    NRF_LOG_INFO("%s(0x%04X, 0x%04X)", __FUNCTION__, out_0, out_1);
+    typedef struct
+    {
+        uint32_t scki_pin;
+        uint32_t sdi_pin;
+        uint32_t val;
+    } tw1805_t;
+
+    tw1805_t tw1508[2] = {
+        {TW_SCKI_0_PIN, TW_SDI_PIN, out_0},
+        {TW_SCKI_1_PIN, TW_SDI_PIN, out_1},
+    };
+
+    nrf_gpio_pin_write(tw1508[0].scki_pin, 0);
+    nrf_gpio_pin_write(tw1508[1].scki_pin, 0);
+
+    for (uint32_t i = 0; i < COUNTOF(tw1508); i++)
+    {
+        for (uint16_t j = 0b1000000000; j > 0; j >>= 1)
+        {
+            nrf_delay_us(1);
+            nrf_gpio_pin_write(tw1508[i].sdi_pin, j & tw1508[i].val);
+            nrf_delay_us(1);
+            nrf_gpio_pin_write(tw1508[i].scki_pin, 1);
+            nrf_delay_us(1);
+            nrf_gpio_pin_write(tw1508[i].scki_pin, 0);
+        }
+    }
+    nrf_delay_us(256);
+}
+
+void tw1508_init(void)
+{
+    tw1508_set(0, 0);
+}
+
+#endif /* ! DEF_TW1508_ENABLED */

app/src/uart.drv.c

@@ -0,0 +1,243 @@
+#include "nrf.h"
+#include "nrf_gpio.h"
+#include "nrf_uarte.h"
+
+#include "le_uart_srv.h"
+#include "uart_drv.h"
+
+#include "nrf_error.h"
+
+#include "FreeRTOS.h"
+#include "message_buffer.h"
+#include "semphr.h"
+#include "task.h"
+
+#include <string.h>
+
+#if (DEF_UARTE_ENABLED)
+
+#define UART_TX_PIN NRF_GPIO_PIN_MAP(0, 6)
+#define UART_RX_PIN NRF_GPIO_PIN_MAP(0, 8)
+
+static MessageBufferHandle_t rx_message = NULL;
+static MessageBufferHandle_t tx_message = NULL;
+static SemaphoreHandle_t tx_done_sem    = NULL;
+
+void UARTE0_UART0_IRQHandler(void)
+{
+    if (NRF_UARTE0->EVENTS_ENDTX)
+    {
+        NRF_UARTE0->EVENTS_ENDTX            = 0;
+        BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+        xSemaphoreGiveFromISR(tx_done_sem, &xHigherPriorityTaskWoken);
+        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+    }
+}
+
+ret_code_t uart_set_baud(uint32_t baudrate)
+{
+    ret_code_t ret = NRF_SUCCESS;
+
+    vTaskSuspendAll();
+
+    NRF_UARTE0->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
+    switch (baudrate)
+    {
+        case 4800:
+            NRF_UARTE0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud4800;
+            break;
+        case 9600:
+            NRF_UARTE0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud9600;
+            break;
+        case 19200:
+            NRF_UARTE0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud19200;
+            break;
+        case 38400:
+            NRF_UARTE0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud38400;
+            break;
+        case 56000:
+            NRF_UARTE0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud56000;
+            break;
+        case 57600:
+            NRF_UARTE0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud57600;
+            break;
+        case 115200:
+            NRF_UARTE0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud115200;
+            break;
+        case 250000:
+            NRF_UARTE0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud250000;
+            break;
+        case 1000000:
+            NRF_UARTE0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1M;
+            break;
+        default:
+            ret = NRF_ERROR_INVALID_PARAM;
+            break;
+    }
+    NRF_UARTE0->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
+
+    xTaskResumeAll();
+
+    return ret;
+}
+
+void uart_tx_task(void *p_arg)
+{
+    for (;;)
+    {
+        static uint8_t tx[2048];
+        size_t tx_size = xMessageBufferReceive(tx_message, tx, sizeof(tx), portMAX_DELAY);
+        if (tx_size)
+        {
+            NRF_UARTE0->TXD.PTR          = (uint32_t)tx;
+            NRF_UARTE0->TXD.MAXCNT       = tx_size;
+            NRF_UARTE0->EVENTS_ENDTX     = 0;
+            NRF_UARTE0->EVENTS_TXSTOPPED = 0;
+            NRF_UARTE0->EVENTS_TXSTARTED = 0;
+            NRF_UARTE0->TASKS_STARTTX    = 1;
+            NRF_UARTE0->INTENSET         = UARTE_INTENSET_ENDTX_Msk;
+            if (xSemaphoreTake(tx_done_sem, pdMS_TO_TICKS(10000)) == pdFALSE)
+            {
+                NRF_UARTE0->TASKS_STOPTX = 1;
+            }
+            NRF_UARTE0->INTENCLR = UARTE_INTEN_ENDTX_Msk;
+        }
+    }
+}
+
+void uart_rx_task(void *p_arg)
+{
+    static uint8_t rx[2][2048];
+    int idx                   = 0;
+    NRF_UARTE0->SHORTS        = UARTE_SHORTS_ENDRX_STARTRX_Msk;
+    NRF_UARTE0->RXD.PTR       = (uint32_t)rx[idx];
+    NRF_UARTE0->RXD.MAXCNT    = sizeof(rx[idx]);
+    NRF_UARTE0->TASKS_STOPRX  = 1;
+    NRF_UARTE0->TASKS_STARTRX = 1;
+    do {
+    } while (NRF_UARTE0->EVENTS_RXSTARTED == 0);
+    NRF_UARTE0->RXD.PTR    = (uint32_t)rx[idx ^ 1];
+    NRF_UARTE0->RXD.MAXCNT = sizeof(rx[idx ^ 1]);
+
+    for (;;)
+    {
+        NRF_UARTE0->EVENTS_RXDRDY = 0;
+
+        do {
+            vTaskDelay(pdMS_TO_TICKS(5));
+        } while (NRF_UARTE0->EVENTS_RXDRDY == 0);
+
+        do {
+            NRF_UARTE0->EVENTS_RXDRDY = 0;
+            vTaskDelay(pdMS_TO_TICKS(5));
+        } while (NRF_UARTE0->EVENTS_RXDRDY == 1);
+
+        NRF_UARTE0->EVENTS_ENDRX     = 0;
+        NRF_UARTE0->EVENTS_RXSTARTED = 0;
+        NRF_UARTE0->TASKS_STOPRX     = 1;
+
+        do {
+            vTaskDelay(pdMS_TO_TICKS(1));
+        } while (NRF_UARTE0->EVENTS_RXSTARTED == 0);
+
+        NRF_UARTE0->RXD.PTR    = (uint32_t)rx[idx];
+        NRF_UARTE0->RXD.MAXCNT = sizeof(rx[idx]);
+
+        xMessageBufferSend(rx_message, rx[idx], NRF_UARTE0->RXD.AMOUNT, portMAX_DELAY);
+
+        idx ^= 1;
+    }
+}
+
+void uart_rx_notify_task(void *p_arg)
+{
+    for (;;)
+    {
+        static uint8_t buf[2048];
+        uint32_t recv_size = uart_recv(buf, sizeof(buf));
+        if (recv_size)
+        {
+            uint8_t *p      = buf;
+            uint32_t loops  = recv_size / BLE_UART_MAX_DATA_LEN;
+            uint32_t remain = recv_size % BLE_UART_MAX_DATA_LEN;
+
+            for (int i = 0; i < loops; i++)
+            {
+                for (int i = 0; i < 10; i++)
+                {
+                    if (le_uart_notify((void *)p, BLE_UART_MAX_DATA_LEN) == NRF_SUCCESS)
+                    {
+                        p += BLE_UART_MAX_DATA_LEN;
+                        break;
+                    }
+                    else
+                    {
+                        vTaskDelay(pdMS_TO_TICKS(5));
+                    }
+                }
+            }
+
+            if (remain)
+            {
+                for (int i = 0; i < 10; i++)
+                {
+                    if (le_uart_notify((void *)p, remain) == NRF_SUCCESS)
+                    {
+                        p += BLE_UART_MAX_DATA_LEN;
+                        break;
+                    }
+                    else
+                    {
+                        vTaskDelay(pdMS_TO_TICKS(5));
+                    }
+                }
+            }
+        }
+    }
+}
+
+void uart_init(void)
+{
+    rx_message  = xMessageBufferCreate(4096);
+    tx_message  = xMessageBufferCreate(2048);
+    tx_done_sem = xSemaphoreCreateBinary();
+
+    NRF_UARTE0->ENABLE   = UARTE_ENABLE_ENABLE_Disabled;
+    NRF_UARTE0->PSEL.TXD = UART_TX_PIN | (UARTE_PSEL_TXD_CONNECT_Connected << UARTE_PSEL_TXD_CONNECT_Pos);
+    NRF_UARTE0->PSEL.RXD = UART_RX_PIN | (UARTE_PSEL_RXD_CONNECT_Connected << UARTE_PSEL_RXD_CONNECT_Pos);
+    NRF_UARTE0->PSEL.CTS = 0;
+    NRF_UARTE0->PSEL.RTS = 0;
+    NRF_UARTE0->CONFIG   = 0;
+    NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud115200;
+    NRF_UARTE0->ENABLE   = UARTE_ENABLE_ENABLE_Enabled;
+
+    // Config uart tx pin
+    nrf_gpio_cfg(
+        UART_TX_PIN,
+        NRF_GPIO_PIN_DIR_OUTPUT,
+        NRF_GPIO_PIN_INPUT_DISCONNECT,
+        NRF_GPIO_PIN_NOPULL,
+        NRF_GPIO_PIN_H0H1,
+        NRF_GPIO_PIN_NOSENSE);
+
+    // Config uart rx pin
+    nrf_gpio_cfg_input(UART_RX_PIN, NRF_GPIO_PIN_PULLUP);
+
+    sd_nvic_SetPriority(UARTE0_UART0_IRQn, _PRIO_APP_LOWEST);
+    sd_nvic_EnableIRQ(UARTE0_UART0_IRQn);
+
+    xTaskCreate(uart_tx_task, "uart tx", 64, NULL, 4, NULL);
+    xTaskCreate(uart_rx_task, "uart rx", 64, NULL, 4, NULL);
+    xTaskCreate(uart_rx_notify_task, "uart rx notify", 128, NULL, 3, NULL);
+}
+
+int uart_send(void *p_data, uint32_t size)
+{
+    return xMessageBufferSend(tx_message, p_data, size, portMAX_DELAY);
+}
+
+int uart_recv(void *p_data, uint32_t max_size)
+{
+    return xMessageBufferReceive(rx_message, p_data, max_size, portMAX_DELAY);
+}
+#endif

app/src/usbd.c

@@ -0,0 +1,256 @@
+#include "nrf.h"
+
+#include "app_usbd.h"
+#include "app_usbd_cdc_acm.h"
+#include "app_usbd_cdc_types.h"
+#include "app_usbd_serial_num.h"
+
+#include "nrf_log.h"
+
+#include "FreeRTOS.h"
+#include "message_buffer.h"
+#include "semphr.h"
+#include "stream_buffer.h"
+#include "task.h"
+
+#define DEBUG_ACM_CDC_READ 1
+
+static void cdc_acm_user_ev_handler(app_usbd_class_inst_t const *p_inst, app_usbd_cdc_acm_user_event_t event);
+
+#define CDC_ACM_COMM_EPIN  NRF_DRV_USBD_EPIN1
+#define CDC_ACM_DATA_EPIN  NRF_DRV_USBD_EPIN2
+#define CDC_ACM_DATA_EPOUT NRF_DRV_USBD_EPOUT2
+
+APP_USBD_CDC_ACM_GLOBAL_DEF(cdc_acm_inst,
+                            cdc_acm_user_ev_handler,
+                            NRF_CDC_ACM_COMM_INTERFACE,
+                            NRF_CDC_ACM_DATA_INTERFACE,
+                            CDC_ACM_COMM_EPIN,
+                            CDC_ACM_DATA_EPIN,
+                            CDC_ACM_DATA_EPOUT,
+                            APP_USBD_CDC_COMM_PROTOCOL_AT_V250);
+
+static SemaphoreHandle_t usbd_ready_rx_done_sem = NULL;
+static SemaphoreHandle_t usbd_ready_tx_done_sem = NULL;
+static SemaphoreHandle_t usbd_evt_queue_sem     = NULL;
+static MessageBufferHandle_t usbd_tx_message    = NULL;
+static MessageBufferHandle_t usbd_rx_message    = NULL;
+static bool is_port_closed                      = true;
+
+static void usbd_isr_handler(app_usbd_internal_evt_t const *const p_event, bool queued)
+{
+    if (queued)
+    {
+        BaseType_t xHigherPriorityTaskWoken = false;
+        xSemaphoreGiveFromISR(usbd_evt_queue_sem, &xHigherPriorityTaskWoken);
+        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+    }
+}
+
+static void usbd_state_proc(app_usbd_event_type_t event)
+{
+    switch (event)
+    {
+        case APP_USBD_EVT_DRV_SUSPEND:
+            break;
+        case APP_USBD_EVT_DRV_RESUME:
+            break;
+        case APP_USBD_EVT_STARTED:
+            NRF_LOG_INFO("APP_USBD_EVT_STARTED");
+            break;
+        case APP_USBD_EVT_STOPPED:
+            NRF_LOG_INFO("APP_USBD_EVT_STOPPED");
+            app_usbd_disable();
+            break;
+        case APP_USBD_EVT_POWER_DETECTED:
+            NRF_LOG_INFO("USB power detected");
+            if (!nrf_drv_usbd_is_enabled())
+            {
+                app_usbd_enable();
+            }
+            break;
+        case APP_USBD_EVT_POWER_REMOVED:
+            NRF_LOG_INFO("USB power removed");
+            app_usbd_stop();
+            break;
+        case APP_USBD_EVT_POWER_READY:
+            NRF_LOG_INFO("USB ready");
+            app_usbd_start();
+            break;
+        default:
+            break;
+    }
+}
+
+static void usbd_ser_send_task(void *p_arg)
+{
+    static uint8_t buf[512];
+    for (;;)
+    {
+        size_t send_size = xStreamBufferReceive(usbd_tx_message, buf, sizeof(buf), portMAX_DELAY);
+        if (send_size && is_port_closed == false)
+        {
+            ret_code_t ret_code = app_usbd_cdc_acm_write(&cdc_acm_inst, buf, send_size);
+            switch (ret_code)
+            {
+                case NRF_SUCCESS:
+                    xSemaphoreTake(usbd_ready_tx_done_sem, pdMS_TO_TICKS(1000));
+                    break;
+                default:
+                    break;
+            }
+        }
+    }
+}
+
+static void cdc_acm_user_ev_handler(app_usbd_class_inst_t const *p_inst, app_usbd_cdc_acm_user_event_t event)
+{
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+    switch (event)
+    {
+        case APP_USBD_CDC_ACM_USER_EVT_PORT_OPEN:
+            is_port_closed = false;
+            xSemaphoreGiveFromISR(usbd_ready_rx_done_sem, &xHigherPriorityTaskWoken);
+            break;
+        case APP_USBD_CDC_ACM_USER_EVT_PORT_CLOSE:
+            is_port_closed = true;
+            break;
+        case APP_USBD_CDC_ACM_USER_EVT_TX_DONE:
+            xSemaphoreGiveFromISR(usbd_ready_tx_done_sem, &xHigherPriorityTaskWoken);
+            break;
+        case APP_USBD_CDC_ACM_USER_EVT_RX_DONE:
+            xSemaphoreGiveFromISR(usbd_ready_rx_done_sem, &xHigherPriorityTaskWoken);
+            break;
+        default:
+            break;
+    }
+    portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+}
+
+static void usbd_ser_recv_task(void *arg)
+{
+    static uint8_t recv[NRFX_USBD_EPSIZE];
+    static uint32_t recv_size;
+    for (;;)
+    {
+        if (is_port_closed)
+        {
+            xSemaphoreTake(usbd_ready_rx_done_sem, portMAX_DELAY);
+        }
+
+        taskENTER_CRITICAL();
+        xSemaphoreTake(usbd_ready_rx_done_sem, 0);
+        taskEXIT_CRITICAL();
+
+        ret_code_t ret_code = app_usbd_cdc_acm_read_any(&cdc_acm_inst, recv, NRFX_USBD_EPSIZE);
+
+        switch (ret_code)
+        {
+            case NRF_SUCCESS:
+                recv_size = xMessageBufferSend(usbd_rx_message, recv, app_usbd_cdc_acm_rx_size(&cdc_acm_inst), portMAX_DELAY);
+                break;
+            case NRF_ERROR_IO_PENDING:
+                xSemaphoreTake(usbd_ready_rx_done_sem, portMAX_DELAY);
+                recv_size = xMessageBufferSend(usbd_rx_message, recv, app_usbd_cdc_acm_rx_size(&cdc_acm_inst), portMAX_DELAY);
+                break;
+            default:
+                break;
+        }
+#if (DEBUG_ACM_CDC_READ == 1)
+        {
+            static uint8_t str[256];
+            memcpy(str, recv, recv_size);
+            str[recv_size] = '\0';
+            NRF_LOG_INFO("%s", str);
+        }
+#endif
+    }
+}
+
+static void usbd_evt_task(void *arg)
+{
+    app_usbd_serial_num_generate();
+
+    app_usbd_config_t usbd_config = {
+        .ev_isr_handler = usbd_isr_handler,
+        .ev_state_proc  = usbd_state_proc,
+    };
+
+    ret_code_t ret;
+    ret = app_usbd_init(&usbd_config);
+    APP_ERROR_CHECK(ret);
+
+    extern ret_code_t nrf_dfu_trigger_usb_init(void);
+    ret = nrf_dfu_trigger_usb_init();
+    APP_ERROR_CHECK(ret);
+
+    app_usbd_class_inst_t const *pxInst = app_usbd_cdc_acm_class_inst_get(&cdc_acm_inst);
+    ret                                 = app_usbd_class_append(pxInst);
+    APP_ERROR_CHECK(ret);
+
+    app_usbd_enable();
+
+    app_usbd_start();
+
+    for (;;)
+    {
+        xSemaphoreTake(usbd_evt_queue_sem, portMAX_DELAY);
+        do {
+        } while (app_usbd_event_queue_process());
+    }
+}
+
+void usbd_init(void)
+{
+    usbd_ready_rx_done_sem = xSemaphoreCreateBinary();
+    usbd_ready_tx_done_sem = xSemaphoreCreateBinary();
+    usbd_evt_queue_sem     = xSemaphoreCreateBinary();
+    usbd_tx_message        = xMessageBufferCreate(512);
+    usbd_rx_message        = xMessageBufferCreate(512);
+
+    xTaskCreate(usbd_evt_task, "usb_evt", 1024, NULL, 3, NULL);
+    xTaskCreate(usbd_ser_recv_task, "usb_recv", 256, NULL, 3, NULL);
+    xTaskCreate(usbd_ser_send_task, "usb_send", 256, NULL, 3, NULL);
+}
+
+int32_t usbd_ser_write(uint8_t *p_data, uint32_t size, TickType_t timeout)
+{
+    int32_t ret = 0;
+
+    if (size)
+    {
+        if (timeout)
+        {
+            xMessageBufferSend(usbd_tx_message, p_data, size, timeout);
+        }
+        else
+        {
+            taskENTER_CRITICAL();
+            xMessageBufferSend(usbd_tx_message, p_data, size, 0);
+            taskEXIT_CRITICAL();
+        }
+    }
+
+    return ret;
+}
+
+int32_t usbd_ser_read(uint8_t *p_data, uint32_t size, TickType_t timeout)
+{
+    int32_t ret = 0;
+
+    if (size)
+    {
+        if (timeout)
+        {
+            ret = xMessageBufferReceive(usbd_rx_message, p_data, size, timeout);
+        }
+        else
+        {
+            taskENTER_CRITICAL();
+            ret = xMessageBufferReceive(usbd_rx_message, p_data, size, 0);
+            taskEXIT_CRITICAL();
+        }
+    }
+
+    return ret;
+}

app/src/usbd_dfu_trigger.c

@@ -0,0 +1,132 @@
+/**
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic
+ *    Semiconductor ASA integrated circuit in a product or a software update for
+ *    such product, must reproduce the above copyright notice, this list of
+ *    conditions and the following disclaimer in the documentation and/or other
+ *    materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ *    Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary form under this license must not be reverse
+ *    engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include "usbd_dfu_trigger.h"
+#include "app_usbd.h"
+#include "app_usbd_nrf_dfu_trigger.h"
+#include "nrf_drv_clock.h"
+#include "nrf_gpio.h"
+#include "nrf_log_ctrl.h"
+
+#include "app_usbd_serial_num.h"
+#include "app_util.h"
+#include "nrf_bootloader_info.h"
+#include "nrf_pwr_mgmt.h"
+#define NRF_LOG_MODULE_NAME nrf_dfu_trigger_usb
+#include "nrf_log.h"
+NRF_LOG_MODULE_REGISTER();
+
+#define DFU_FLASH_PAGE_SIZE  (NRF_FICR->CODEPAGESIZE)
+#define DFU_FLASH_PAGE_COUNT (NRF_FICR->CODESIZE)
+
+#define APP_NAME             ELITE_DEVICE_NAME
+#define APP_VERSION_STRING   "1.0.0"
+
+static uint8_t m_version_string[] = APP_NAME " " APP_VERSION_STRING; ///< Human-readable version string.
+static app_usbd_nrf_dfu_trigger_nordic_info_t m_dfu_info;            ///< Struct with various information about the current firmware.
+
+static void dfu_trigger_evt_handler(app_usbd_class_inst_t const *p_inst, app_usbd_nrf_dfu_trigger_user_event_t event)
+{
+    UNUSED_PARAMETER(p_inst);
+    ret_code_t err_code;
+    switch (event)
+    {
+        case APP_USBD_NRF_DFU_TRIGGER_USER_EVT_DETACH:
+            NRF_LOG_INFO("DFU Detach request received. Triggering a pin reset.");
+            NRF_LOG_FINAL_FLUSH();
+            {
+                err_code = sd_power_gpregret_clr(0, 0xFFFFFFFF);
+                APP_ERROR_CHECK(err_code);
+                err_code = sd_power_gpregret_set(0, BOOTLOADER_DFU_START);
+                APP_ERROR_CHECK(err_code);
+                // Signal that DFU mode is to be enter to the power management module
+                nrf_pwr_mgmt_shutdown(NRF_PWR_MGMT_SHUTDOWN_GOTO_DFU);
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+APP_USBD_NRF_DFU_TRIGGER_GLOBAL_DEF(m_app_dfu,
+                                    NRF_DFU_TRIGGER_USB_INTERFACE_NUM,
+                                    &m_dfu_info,
+                                    m_version_string,
+                                    dfu_trigger_evt_handler);
+
+static void strings_create(void)
+{
+    uint8_t prev_char = 'a'; // Arbitrary valid char, not '-'.
+    // Remove characters that are not supported in semantic version strings.
+    for (size_t i = strlen(APP_NAME) + 1; i < strlen((char *)m_version_string); i++)
+    {
+        if (((m_version_string[i] >= 'a') && (m_version_string[i] <= 'z')) || ((m_version_string[i] >= 'A') && (m_version_string[i] <= 'Z')) || ((m_version_string[i] >= '0') && (m_version_string[i] <= '9')) || (m_version_string[i] == '+') || (m_version_string[i] == '.') || (m_version_string[i] == '-'))
+        {
+            // Valid semantic version character.
+        }
+        else if (prev_char == '-')
+        {
+            m_version_string[i] = '0';
+        }
+        else
+        {
+            m_version_string[i] = '-';
+        }
+        prev_char = m_version_string[i];
+    }
+}
+
+ret_code_t nrf_dfu_trigger_usb_init(void)
+{
+
+    m_dfu_info.wAddress       = CODE_START;
+    m_dfu_info.wFirmwareSize  = CODE_SIZE;
+    m_dfu_info.wVersionMajor  = 1;
+    m_dfu_info.wVersionMinor  = 0;
+    m_dfu_info.wFirmwareID    = 0;
+    m_dfu_info.wFlashPageSize = DFU_FLASH_PAGE_SIZE;
+    m_dfu_info.wFlashSize     = m_dfu_info.wFlashPageSize * DFU_FLASH_PAGE_COUNT;
+
+    strings_create();
+
+    app_usbd_class_inst_t const *class_dfu = app_usbd_nrf_dfu_trigger_class_inst_get(&m_app_dfu);
+    ret_code_t ret                         = app_usbd_class_append(class_dfu);
+
+    return ret;
+}

app_config.h

@@ -1,205 +0,0 @@
-#pragma once
-#ifndef __APP_CONFIG_H__
-#define __APP_CONFIG_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-// LOG
-#define NRF_LOG_ENABLED                             1
-#define NRF_LOG_DEFAULT_LEVEL                       3
-#define NRF_LOG_BACKEND_RTT_ENABLED                 1
-
-#define NRF_LOG_BACKEND_UART_ENABLED                0
-#define NRF_LOG_BACKEND_RTT_TX_RETRY_DELAY_MS       1
-#define NRF_LOG_BACKEND_RTT_TX_RETRY_CNT            3
-#define NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE        64
-#define NRF_LOG_DEFERRED                            0
-#define NRF_LOG_USES_TIMESTAMP                      0
-#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 0
-
-// SEGGER-RTT
-#define SEGGER_RTT_SECTION                          ".segger_rtt"
-#define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS        1
-#define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS      1
-#define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP            4000
-#define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN          16
-#define SEGGER_RTT_CONFIG_DEFAULT_MODE              0
-
-// SoftDevice SoC event handler
-#define NRF_SDH_SOC_ENABLED                         1
-
-// SoftDevice handler
-#define NRF_SDH_ENABLED                             1
-
-// SoftDevice clock configuration
-#define NRF_SDH_CLOCK_LF_SRC                        0
-#define NRF_SDH_CLOCK_LF_RC_CTIV                    12
-#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV               2
-#define NRF_SDH_CLOCK_LF_ACCURACY                   1
-
-// SDH Observers - Observers and priority levels
-#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS            2
-#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS          2
-#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS          2
-
-// SoC Observers - Observers and priority levels
-#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS            2
-
-// nrf_drv_power - POWER peripheral driver - legacy layer
-#define POWER_ENABLED                               1
-// The default configuration of main DCDC regulator
-#define POWER_CONFIG_DEFAULT_DCDCEN                 0
-//  The default configuration of High Voltage DCDC regulator
-#define POWER_CONFIG_DEFAULT_DCDCENHV               0
-
-// nrf_drv_clock - CLOCK peripheral driver - legacy layer
-#define NRF_CLOCK_ENABLED                           1
-//  LF Clock Source
-#define CLOCK_CONFIG_LF_SRC                         0
-#define CLOCK_CONFIG_LF_CAL_ENABLED                 0
-// nrf_section_iter - Section iterator
-#define NRF_SECTION_ITER_ENABLED                    1
-
-// State Observers priorities
-#define CLOCK_CONFIG_STATE_OBSERVER_PRIO            0
-#define POWER_CONFIG_STATE_OBSERVER_PRIO            0
-#define RNG_CONFIG_STATE_OBSERVER_PRIO              0
-
-// Stack Event Observers priorities
-#define NRF_SDH_SOC_STACK_OBSERVER_PRIO             0
-#define NRF_SDH_BLE_STACK_OBSERVER_PRIO             0
-
-// SoC Observers priorities
-#define POWER_CONFIG_SOC_OBSERVER_PRIO              0
-#define CLOCK_CONFIG_SOC_OBSERVER_PRIO              0
-
-// Interrupt priority
-#define POWER_CONFIG_IRQ_PRIORITY                   6
-#define CLOCK_CONFIG_IRQ_PRIORITY                   6
-
-// SoftDevice BLE event handler
-#define NRF_SDH_BLE_ENABLED                         1
-// The number of vendor-specific UUIDs.
-#define NRF_SDH_BLE_VS_UUID_COUNT                   2
-// Attribute Table size in bytes. The size must be a multiple of 4.
-#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE             1408
-// BLE Observers - Observers and priority levels
-#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS            4
-// Include the Service Changed characteristic in the Attribute Table.
-#define NRF_SDH_BLE_SERVICE_CHANGED                 1
-
-// This setting configures how Stack events are dispatched to the application.
-#define NRF_SDH_DISPATCH_MODEL                      2 /* SoftDevice events are to be fetched manually. */
-
-// BLE Observers priorities - Invididual priorities
-#define BLE_ADV_BLE_OBSERVER_PRIO                   1
-#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO           1
-#define BLE_CONN_STATE_BLE_OBSERVER_PRIO            0
-
-// Enable Advertising module
-#define BLE_ADVERTISING_ENABLED                     1
-
-// BLE device name
-#define DEF_ELITE_EDC_15RE                          0x00020107
-#define DEF_ELITE_EDC_15R2                          0x00020108
-#define DEF_ELITE_EIS_10                            0x00040100
-#define DEF_ELITE_EIS_11                            0x00040101
-#define DEF_ELITE_EIS_MINI_10                       0x00040102
-#define DEF_ELITE_MODEL                             DEF_ELITE_EDC_15RE
-
-#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_15RE)
-#define ELITE_DEVICE_NAME     "EDC"
-#define MAJOR_PRODUCT_NUMBER  0
-#define MINOR_PRODUCT_NUMBER  2
-#define MAJOR_VERSION_NUMBER  1
-#define MINOR_VERSION_NUMBER  7
-#define BLE_EDC_ENABLED       1
-#define EDC_BLE_OBSERVER_PRIO 3
-#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_15R2)
-#define ELITE_DEVICE_NAME     "EDC"
-#define MAJOR_PRODUCT_NUMBER  0
-#define MINOR_PRODUCT_NUMBER  2
-#define MAJOR_VERSION_NUMBER  1
-#define MINOR_VERSION_NUMBER  8
-#define BLE_EDC_ENABLED       1
-#define EDC_BLE_OBSERVER_PRIO 3
-#elif (DEF_ELITE_MODEL == DEF_ELITE_EIS_10)
-#define ELITE_DEVICE_NAME     "EIS"
-#define MAJOR_PRODUCT_NUMBER  0
-#define MINOR_PRODUCT_NUMBER  4
-#define MAJOR_VERSION_NUMBER  1
-#define MINOR_VERSION_NUMBER  0
-#define BLE_EIS_ENABLED       1
-#define EDC_BLE_OBSERVER_PRIO 3
-#elif (DEF_ELITE_MODEL == DEF_ELITE_EIS_11)
-#define ELITE_DEVICE_NAME     "EIS"
-#define MAJOR_PRODUCT_NUMBER  0
-#define MINOR_PRODUCT_NUMBER  4
-#define MAJOR_VERSION_NUMBER  1
-#define MINOR_VERSION_NUMBER  1
-#define BLE_EIS_ENABLED       1
-#define EDC_BLE_OBSERVER_PRIO 3
-#elif (DEF_ELITE_MODEL == DEF_ELITE_EIS_MINI_10)
-#define ELITE_DEVICE_NAME     "EIS"
-#define MAJOR_PRODUCT_NUMBER  0
-#define MINOR_PRODUCT_NUMBER  4
-#define MAJOR_VERSION_NUMBER  1
-#define MINOR_VERSION_NUMBER  2
-#define BLE_EIS_ENABLED       1
-#define EDC_BLE_OBSERVER_PRIO 3
-#endif
-
-#define ELITE_COMPANY_CODE "Elite"
-#define ELITE_HW_VER                                                                           \
-    {                                                                                          \
-        MAJOR_PRODUCT_NUMBER, MINOR_PRODUCT_NUMBER, MAJOR_VERSION_NUMBER, MINOR_VERSION_NUMBER \
-    }
-
-// Maximum number of peripheral links.
-#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 1
-// Maximum number of central links.
-#define NRF_SDH_BLE_CENTRAL_LINK_COUNT    0
-// Total link count.
-#define NRF_SDH_BLE_TOTAL_LINK_COUNT      1
-
-// Enable GATT module.
-#define NRF_BLE_GATT_ENABLED              1
-// Priority with which BLE events are dispatched to the GATT module.
-#define NRF_BLE_GATT_BLE_OBSERVER_PRIO    1
-// Requested BLE GAP data length to be negotiated.
-#define NRF_SDH_BLE_GAP_DATA_LENGTH       251
-// GAP event length. The time set aside for this connection on every connection interval in 1.25 ms units.
-#define NRF_SDH_BLE_GAP_EVENT_LENGTH      (0xFFFF)
-// Static maximum MTU size.
-#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE     247
-
-// Enable ble device info module
-#define BLE_DIS_ENABLED                   1
-
-// DFU
-#define NRF_DFU_TRANSPORT_BLE             1
-#define BLE_DFU_BLE_OBSERVER_PRIO         2
-#define NRF_PWR_MGMT_ENABLED              1
-
-// Enable spim
-#define SPI_ENABLED                       1
-#define SPI1_ENABLED                      1
-#define SPI1_USE_EASY_DMA                 1
-#define SPI2_ENABLED                      1
-#define SPI2_USE_EASY_DMA                 1
-#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY   7
-#define NRFX_SPIM_MISO_PULL_CFG           3
-
-// Enable twi(i2c)
-#define TWI_ENABLED                       1
-#define TWI0_ENABLED                      1
-#define TWI0_USE_EASY_DMA                 1
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // !__APP_CONFIG_H__

bmd380_peripheral-Debug.vgdbsettings

@@ -107,17 +107,17 @@
       <EnableAsyncExecutionMode>false</EnableAsyncExecutionMode>
       <AsyncModeSupportsBreakpoints>true</AsyncModeSupportsBreakpoints>
       <TemporaryBreakConsolidationTimeout>0</TemporaryBreakConsolidationTimeout>
+      <BacktraceFrameLimit>0</BacktraceFrameLimit>
       <EnableNonStopMode>false</EnableNonStopMode>
       <MaxBreakpointLimit>0</MaxBreakpointLimit>
       <EnableVerboseMode>true</EnableVerboseMode>
       <EnablePrettyPrinters>false</EnablePrettyPrinters>
+      <EnableAbsolutePathReporting>true</EnableAbsolutePathReporting>
     </AdditionalGDBSettings>
     <DebugMethod>
       <ID>jlink-jtag</ID>
-      <InterfaceID>com.sysprogs.debug.jlink.jlinksw</InterfaceID>
-      <InterfaceSerialNumber>000682409936</InterfaceSerialNumber>
       <Configuration xsi:type="com.visualgdb.edp.segger.settings">
-        <CommandLine>-select USB -device $$SYS:MCU_ID$$ -speed auto -if SWD</CommandLine>
+        <CommandLine>-select USB=682409936 -device $$SYS:MCU_ID$$ -speed auto -if SWD</CommandLine>
         <ProgramMode>Enabled</ProgramMode>
         <StartupCommands>
           <string>target remote :$$SYS:GDB_PORT$$</string>
@@ -140,9 +140,17 @@
     <EnableVirtualHalts>false</EnableVirtualHalts>
     <DynamicAnalysisSettings />
     <EndOfStackSymbol>_estack</EndOfStackSymbol>
-    <TimestampProviderTicksPerSecond>0</TimestampProviderTicksPerSecond>
+    <TimestampProvider>com.sysprogs.arm.dwt</TimestampProvider>
+    <TimestampProviderTicksPerSecond>64000000</TimestampProviderTicksPerSecond>
     <KeepConsoleAfterExit>false</KeepConsoleAfterExit>
     <UnusedStackFillPattern xsi:nil="true" />
+    <RelatedExecutables>
+      <RelatedExecutable>
+        <Program>false</Program>
+        <LoadSymbols>false</LoadSymbols>
+        <ShowInLiveWatch>false</ShowInLiveWatch>
+      </RelatedExecutable>
+    </RelatedExecutables>
     <CheckInterfaceDrivers>true</CheckInterfaceDrivers>
   </Debug>
 </VisualGDBProjectSettings2>

bmd380_peripheral-Release.vgdbsettings

@@ -23,7 +23,10 @@
       </Version>
     </ToolchainID>
     <ProjectFile>bmd380_peripheral.vcxproj</ProjectFile>
-    <ParallelJobCount>0</ParallelJobCount>
+    <RemoteBuildEnvironment>
+      <Records />
+    </RemoteBuildEnvironment>
+    <ParallelJobCount>1</ParallelJobCount>
     <SuppressDirectoryChangeMessages>true</SuppressDirectoryChangeMessages>
     <BuildAsRoot>false</BuildAsRoot>
   </Build>
@@ -45,6 +48,7 @@
     <ShowMessageAfterExecuting>true</ShowMessageAfterExecuting>
   </CustomShortcuts>
   <UserDefinedVariables />
+  <ImportedPropertySheets />
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     <Enabled>Unknown</Enabled>
     <ExtraSettings>
@@ -57,6 +61,8 @@
       <Enabled>false</Enabled>
     </CodeAnalyzerSettings>
   </CodeSense>
+  <Configurations />
+  <ProgramArgumentsSuggestions />
   <Debug xsi:type="com.visualgdb.debug.embedded">
     <AdditionalStartupCommands />
     <AdditionalGDBSettings>
@@ -88,10 +94,12 @@
       <EnableAsyncExecutionMode>false</EnableAsyncExecutionMode>
       <AsyncModeSupportsBreakpoints>true</AsyncModeSupportsBreakpoints>
       <TemporaryBreakConsolidationTimeout>0</TemporaryBreakConsolidationTimeout>
+      <BacktraceFrameLimit>0</BacktraceFrameLimit>
       <EnableNonStopMode>false</EnableNonStopMode>
       <MaxBreakpointLimit>0</MaxBreakpointLimit>
       <EnableVerboseMode>true</EnableVerboseMode>
       <EnablePrettyPrinters>false</EnablePrettyPrinters>
+      <EnableAbsolutePathReporting>true</EnableAbsolutePathReporting>
     </AdditionalGDBSettings>
     <DebugMethod>
       <ID>jlink-jtag</ID>

bmd380_peripheral.code-workspace

@@ -0,0 +1,11 @@
+{
+	"folders": [
+		{
+			"path": "."
+		},
+		{
+			"path": "../bmd380_sdk"
+		}
+	],
+	"settings": {}
+}

bmd380_peripheral.vcxproj

@@ -32,37 +32,48 @@
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     <GNUConfigurationType>Debug</GNUConfigurationType>
     <ToolchainID>com.visualgdb.arm-eabi</ToolchainID>
-    <ToolchainVersion>12.3.1/13.2/r1</ToolchainVersion>
+    <ToolchainVersion>14.2.1/15.2/r2</ToolchainVersion>
     <GenerateHexFile>true</GenerateHexFile>
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     <ToolchainID>com.visualgdb.arm-eabi</ToolchainID>
-    <ToolchainVersion>12.3.1/13.2/r1</ToolchainVersion>
+    <ToolchainVersion>14.2.1/15.2/r2</ToolchainVersion>
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     <ClCompile>
       <CLanguageStandard>GNU99</CLanguageStandard>
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-      <PreprocessorDefinitions>DEBUG=1;USE_APP_CONFIG=1;%(ClCompile.PreprocessorDefinitions)</PreprocessorDefinitions>
+      <AdditionalIncludeDirectories>.;../bmd380_sdk/components/softdevice/s140/headers;../bmd380_sdk/components/softdevice/s140/headers/nrf52;../bmd380_sdk/external/segger_rtt;../bmd380_sdk/components/libraries/log;../bmd380_sdk/components/libraries/log/src;../bmd380_sdk/components/libraries/memobj;../bmd380_sdk/components/libraries/ringbuf;../bmd380_sdk/components/libraries/atomic;../bmd380_sdk/components/libraries/balloc;../bmd380_sdk/external/freertos/portable/CMSIS/nrf52;../bmd380_sdk/external/freertos/portable/GCC/nrf52;../bmd380_sdk/integration/nrfx;../bmd380_sdk/integration/nrfx/legacy;../bmd380_sdk/components/libraries/experimental_section_vars;../bmd380_sdk/components/libraries/strerror;../bmd380_sdk/external/freertos/source/include;../bmd380_sdk/components/softdevice/common;../bmd380_sdk/components/ble/common;../bmd380_sdk/components/ble/ble_advertising;../bmd380_sdk/components/libraries/atomic_flags;../bmd380_sdk/components/ble/ble_db_discovery;../bmd380_sdk/components/ble/ble_dtm;../bmd380_sdk/components/ble/ble_link_ctx_manager;../bmd380_sdk/components/ble/ble_racp;../bmd380_sdk/components/ble/ble_radio_notification;../bmd380_sdk/components/ble/ble_services/ble_ancs_c;../bmd380_sdk/components/ble/ble_services/ble_ans_c;../bmd380_sdk/components/ble/ble_services/ble_bas;../bmd380_sdk/components/ble/ble_services/ble_bas_c;../bmd380_sdk/components/ble/ble_services/ble_bps;../bmd380_sdk/components/ble/ble_services/ble_cscs;../bmd380_sdk/components/ble/ble_services/ble_cts_c;../bmd380_sdk/components/ble/ble_services/ble_dfu;../bmd380_sdk/components/ble/ble_services/ble_dis;../bmd380_sdk/components/ble/ble_services/ble_dis_c;../bmd380_sdk/components/ble/ble_services/ble_escs;../bmd380_sdk/components/ble/ble_services/ble_gls;../bmd380_sdk/components/ble/ble_services/ble_hids;../bmd380_sdk/components/ble/ble_services/ble_hrs;../bmd380_sdk/components/ble/ble_services/ble_hrs_c;../bmd380_sdk/components/ble/ble_services/ble_hts;../bmd380_sdk/components/ble/ble_services/ble_ias;../bmd380_sdk/components/ble/ble_services/ble_ias_c;../bmd380_sdk/components/ble/ble_services/ble_ipsp;../bmd380_sdk/components/ble/ble_services/ble_lbs;../bmd380_sdk/components/ble/ble_services/ble_lbs_c;../bmd380_sdk/components/ble/ble_services/ble_lls;../bmd380_sdk/components/ble/ble_services/ble_nus;../bmd380_sdk/components/ble/ble_services/ble_nus_c;../bmd380_sdk/components/ble/ble_services/ble_rscs;../bmd380_sdk/components/ble/ble_services/ble_rscs_c;../bmd380_sdk/components/ble/ble_services/ble_tps;../bmd380_sdk/components/ble/ble_services/eddystone;../bmd380_sdk/components/ble/ble_services/experimental_ble_lns;../bmd380_sdk/components/ble/ble_services/experimental_ble_ots;../bmd380_sdk/components/ble/ble_services/experimental_gatts_c;../bmd380_sdk/components/ble/ble_services/experimental_nrf_ble_cgms;../bmd380_sdk/components/ble/ble_services/experimental_nrf_ble_ots_c;../bmd380_sdk/components/ble/ble_services/nrf_ble_bms;../bmd380_sdk/components/ble/nrf_ble_gatt;../bmd380_sdk/components/ble/nrf_ble_gq;../bmd380_sdk/components/ble/nrf_ble_qwr;../bmd380_sdk/components/ble/nrf_ble_scan;../bmd380_sdk/components/ble/peer_manager;../bmd380_sdk/components/libraries/pwr_mgmt;littlefs;../bmd380_sdk/external/utf_converter;../bmd380_sdk/components/boards;../bmd380_sdk/components/libraries/usbd;../bmd380_sdk/components/libraries/usbd/class/audio;../bmd380_sdk/components/libraries/usbd/class/cdc;../bmd380_sdk/components/libraries/usbd/class/cdc/acm;../bmd380_sdk/components/libraries/usbd/class/dummy;../bmd380_sdk/components/libraries/usbd/class/hid;../bmd380_sdk/components/libraries/usbd/class/hid/generic;../bmd380_sdk/components/libraries/usbd/class/hid/kbd;../bmd380_sdk/components/libraries/usbd/class/hid/mouse;../bmd380_sdk/components/libraries/usbd/class/msc;../bmd380_sdk/components/libraries/usbd/class/nrf_dfu_trigger;%(ClCompile.AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <PreprocessorDefinitions>DEBUG=1;USE_APP_CONFIG=1;LFS_THREADSAFE=1;CONFIG_NFCT_PINS_AS_GPIOS;NRF52840_XXAA;%(ClCompile.PreprocessorDefinitions)</PreprocessorDefinitions>
       <AdditionalOptions />
       <CPPLanguageStandard />
+      <Optimization>O0</Optimization>
     </ClCompile>
     <Link>
-      <AdditionalLinkerInputs>%(Link.AdditionalLinkerInputs)</AdditionalLinkerInputs>
-      <LibrarySearchDirectories>%(Link.LibrarySearchDirectories)</LibrarySearchDirectories>
-      <AdditionalLibraryNames>%(Link.AdditionalLibraryNames)</AdditionalLibraryNames>
+      <AdditionalLinkerInputs>;%(Link.AdditionalLinkerInputs)</AdditionalLinkerInputs>
+      <LibrarySearchDirectories>;%(Link.LibrarySearchDirectories)</LibrarySearchDirectories>
+      <AdditionalLibraryNames>;%(Link.AdditionalLibraryNames)</AdditionalLibraryNames>
       <LinkerScript>nRF52840_XXAA_S140_reserve.lds</LinkerScript>
       <AdditionalOptions />
     </Link>
+    <ToolchainSettingsContainer>
+      <InstructionSet>THUMB</InstructionSet>
+    </ToolchainSettingsContainer>
+    <ToolchainSettingsContainer>
+      <FloatABI>hard</FloatABI>
+    </ToolchainSettingsContainer>
+    <ToolchainSettingsContainer>
+      <ARMFPU>fpv4-sp-d16</ARMFPU>
+      <ARMCPU>cortex-m4</ARMCPU>
+    </ToolchainSettingsContainer>
   </ItemDefinitionGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|VisualGDB'">
     <ClCompile>
       <CLanguageStandard>GNU99</CLanguageStandard>
       <AdditionalIncludeDirectories>.;../bmd380_sdk/components/softdevice/s140/headers;../bmd380_sdk/components/softdevice/s140/headers/nrf52;../bmd380_sdk/external/segger_rtt;../bmd380_sdk/components/libraries/log;../bmd380_sdk/components/libraries/log/src;../bmd380_sdk/components/libraries/memobj;../bmd380_sdk/components/libraries/ringbuf;../bmd380_sdk/components/libraries/atomic;../bmd380_sdk/components/libraries/balloc;../bmd380_sdk/external/freertos/portable/CMSIS/nrf52;../bmd380_sdk/external/freertos/portable/GCC/nrf52;../bmd380_sdk/integration/nrfx;../bmd380_sdk/integration/nrfx/legacy;../bmd380_sdk/components/libraries/experimental_section_vars;../bmd380_sdk/components/libraries/strerror;../bmd380_sdk/external/freertos/source/include;../bmd380_sdk/components/softdevice/common;../bmd380_sdk/components/ble/common;../bmd380_sdk/components/ble/ble_advertising;../bmd380_sdk/components/libraries/atomic_flags;../bmd380_sdk/components/ble/ble_db_discovery;../bmd380_sdk/components/ble/ble_dtm;../bmd380_sdk/components/ble/ble_link_ctx_manager;../bmd380_sdk/components/ble/ble_racp;../bmd380_sdk/components/ble/ble_radio_notification;../bmd380_sdk/components/ble/ble_services/ble_ancs_c;../bmd380_sdk/components/ble/ble_services/ble_ans_c;../bmd380_sdk/components/ble/ble_services/ble_bas;../bmd380_sdk/components/ble/ble_services/ble_bas_c;../bmd380_sdk/components/ble/ble_services/ble_bps;../bmd380_sdk/components/ble/ble_services/ble_cscs;../bmd380_sdk/components/ble/ble_services/ble_cts_c;../bmd380_sdk/components/ble/ble_services/ble_dfu;../bmd380_sdk/components/ble/ble_services/ble_dis;../bmd380_sdk/components/ble/ble_services/ble_dis_c;../bmd380_sdk/components/ble/ble_services/ble_escs;../bmd380_sdk/components/ble/ble_services/ble_gls;../bmd380_sdk/components/ble/ble_services/ble_hids;../bmd380_sdk/components/ble/ble_services/ble_hrs;../bmd380_sdk/components/ble/ble_services/ble_hrs_c;../bmd380_sdk/components/ble/ble_services/ble_hts;../bmd380_sdk/components/ble/ble_services/ble_ias;../bmd380_sdk/components/ble/ble_services/ble_ias_c;../bmd380_sdk/components/ble/ble_services/ble_ipsp;../bmd380_sdk/components/ble/ble_services/ble_lbs;../bmd380_sdk/components/ble/ble_services/ble_lbs_c;../bmd380_sdk/components/ble/ble_services/ble_lls;../bmd380_sdk/components/ble/ble_services/ble_nus;../bmd380_sdk/components/ble/ble_services/ble_nus_c;../bmd380_sdk/components/ble/ble_services/ble_rscs;../bmd380_sdk/components/ble/ble_services/ble_rscs_c;../bmd380_sdk/components/ble/ble_services/ble_tps;../bmd380_sdk/components/ble/ble_services/eddystone;../bmd380_sdk/components/ble/ble_services/experimental_ble_lns;../bmd380_sdk/components/ble/ble_services/experimental_ble_ots;../bmd380_sdk/components/ble/ble_services/experimental_gatts_c;../bmd380_sdk/components/ble/ble_services/experimental_nrf_ble_cgms;../bmd380_sdk/components/ble/ble_services/experimental_nrf_ble_ots_c;../bmd380_sdk/components/ble/ble_services/nrf_ble_bms;../bmd380_sdk/components/ble/nrf_ble_gatt;../bmd380_sdk/components/ble/nrf_ble_gq;../bmd380_sdk/components/ble/nrf_ble_qwr;../bmd380_sdk/components/ble/nrf_ble_scan;../bmd380_sdk/components/ble/peer_manager;%(ClCompile.AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
-      <PreprocessorDefinitions>NDEBUG=1;RELEASE=1;USE_APP_CONFIG=1;%(ClCompile.PreprocessorDefinitions)</PreprocessorDefinitions>
+      <PreprocessorDefinitions>NDEBUG=1;RELEASE=1;USE_APP_CONFIG=1;NRF52840_XXAA;%(ClCompile.PreprocessorDefinitions)</PreprocessorDefinitions>
     </ClCompile>
     <Link>
       <AdditionalLinkerInputs>;%(Link.AdditionalLinkerInputs)</AdditionalLinkerInputs>
@@ -156,6 +167,7 @@
     <ClCompile Include="..\bmd380_sdk\integration\nrfx\legacy\nrf_drv_clock.c" />
     <ClCompile Include="..\bmd380_sdk\integration\nrfx\legacy\nrf_drv_power.c">
       <ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|VisualGDB'">true</ExcludedFromBuild>
+      <ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|VisualGDB'">true</ExcludedFromBuild>
     </ClCompile>
     <ClCompile Include="..\bmd380_sdk\integration\nrfx\legacy\nrf_drv_ppi.c">
       <ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|VisualGDB'">true</ExcludedFromBuild>
@@ -179,19 +191,56 @@
     </ClCompile>
     <ClCompile Include="..\bmd380_sdk\integration\nrfx\legacy\nrf_drv_uart.c">
       <ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|VisualGDB'">true</ExcludedFromBuild>
+      <ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|VisualGDB'">true</ExcludedFromBuild>
     </ClCompile>
-    <ClCompile Include="edc_regular_data.c" />
-    <ClCompile Include="i2c.c" />
-    <ClCompile Include="led.c" />
+    <ClCompile Include="adc_drv.c" />
+    <ClCompile Include="adgs1412.c" />
+    <ClCompile Include="ads8691.c" />
+    <ClCompile Include="apa102_2020.c" />
+    <ClCompile Include="btn.c" />
+    <ClCompile Include="builtin_saadc.c" />
+    <ClCompile Include="cpg.c" />
+    <ClCompile Include="cpg11_io.c" />
+    <ClCompile Include="elite_board.c" />
+    <ClCompile Include="dac_drv.c" />
+    <ClCompile Include="elite_dev.c" />
+    <ClCompile Include="edc20_cycle_iv_mode.c" />
+    <ClCompile Include="elite_mmm.c" />
+    <ClCompile Include="fs.c" />
+    <ClCompile Include="gd25d10c.c" />
+    <ClCompile Include="le_uart_srv.c" />
+    <ClCompile Include="max14802.c" />
+    <ClCompile Include="max5136.c" />
+    <ClCompile Include="edc20_io.c" />
+    <ClCompile Include="edc20.c" />
+    <ClCompile Include="elite.c" />
+    <ClCompile Include="elite_adc.c" />
+    <ClCompile Include="elite_dac.c" />
+    <ClCompile Include="elite_correction.c" />
+    <ClCompile Include="led_drv.c" />
     <ClCompile Include="le_adv.c" />
     <ClCompile Include="le_dfu.c" />
-    <ClCompile Include="le_edc_srv.c" />
+    <ClCompile Include="le_elite_srv.c" />
     <ClCompile Include="le_gap.c" />
     <ClCompile Include="le_gatt.c" />
     <ClCompile Include="le_srv.c" />
     <ClCompile Include="main.c" />
-    <ClCompile Include="spi.c" />
+    <ClCompile Include="j_scop.c" />
+    <ClCompile Include="pel.c" />
+    <ClCompile Include="pel20_io.c" />
+    <ClCompile Include="sw_drv.c" />
     <ClCompile Include="syscalls.c" />
+    <ClCompile Include="tw1508.c" />
+    <ClCompile Include="uart.drv.c" />
+    <ClCompile Include="usbd.c" />
+    <ClCompile Include="usbd_dfu_trigger.c" />
+    <ClInclude Include="elite_mmm.h" />
+    <ClInclude Include="le_uart_srv.h" />
+    <ClInclude Include="max14802.h" />
+    <ClInclude Include="pel20_io.h" />
+    <ClInclude Include="tw1508.h" />
+    <ClInclude Include="uart_drv.h" />
+    <ClInclude Include="usbd.h" />
     <None Include="nRF52811_XXAA_s140.lds" />
     <None Include="nRF52840_XXAA_S140_reserve.lds" />
     <None Include="nrf5x.props" />
@@ -334,9 +383,38 @@
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     <ClInclude Include="..\bmd380_sdk\integration\nrfx\nrfx_glue.h" />
     <ClInclude Include="..\bmd380_sdk\integration\nrfx\nrfx_log.h" />
+    <ClInclude Include="adc_drv.h" />
+    <ClInclude Include="adc_drv_if.h" />
+    <ClInclude Include="adgs1412.h" />
+    <ClInclude Include="ads8691.h" />
+    <ClInclude Include="apa102_2020.h" />
     <ClInclude Include="app_config.h" />
+    <ClInclude Include="block_dev_drv_if.h" />
+    <ClInclude Include="btn.h" />
+    <ClInclude Include="cpg.h" />
+    <ClInclude Include="cpg11_io.h" />
+    <ClInclude Include="dac_drv.h" />
+    <ClInclude Include="dac_drv_if.h" />
+    <ClInclude Include="edc.h" />
+    <ClInclude Include="edc20_io.h" />
+    <ClInclude Include="eis.h" />
+    <ClInclude Include="elite.h" />
+    <ClInclude Include="elite_adc.h" />
+    <ClInclude Include="elite_dac.h" />
+    <ClInclude Include="elite_correction.h" />
+    <ClInclude Include="elite_board.h" />
+    <ClInclude Include="elite_dev.h" />
     <ClInclude Include="FreeRTOSConfig.h" />
-    <ClInclude Include="led.h" />
+    <ClInclude Include="elite_def.h" />
+    <ClInclude Include="builtin_saadc.h" />
+    <ClInclude Include="fs.h" />
+    <ClInclude Include="gd25d10c.h" />
+    <ClInclude Include="led_drv.h" />
+    <ClInclude Include="led_drv_if.h" />
+    <ClInclude Include="max5136.h" />
+    <ClInclude Include="pel.h" />
+    <ClInclude Include="sw_drv.h" />
+    <ClInclude Include="sw_drv_if.h" />
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     <ClInclude Include="radio_config.h" />
     <ClInclude Include="sdio_config.h" />
@@ -593,5 +671,59 @@
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     <ClInclude Include="..\bmd380_sdk\components\ble\common\ble_sensor_location.h" />
     <ClInclude Include="..\bmd380_sdk\components\ble\common\ble_srv_common.h" />
+    <ClCompile Include="littlefs\lfs.c" />
+    <ClCompile Include="littlefs\lfs_util.c" />
+    <ClInclude Include="littlefs\lfs.h" />
+    <ClInclude Include="littlefs\lfs_util.h" />
+    <ClCompile Include="$(BSP_ROOT)\nRF5x\components\libraries\atomic_fifo\nrf_atfifo.c" />
+    <ClInclude Include="$(BSP_ROOT)\nRF5x\components\libraries\atomic_fifo\nrf_atfifo.h" />
+    <ClInclude Include="$(BSP_ROOT)\nRF5x\components\libraries\atomic_fifo\nrf_atfifo_internal.h" />
+    <ClCompile Include="..\bmd380_sdk\components\libraries\usbd\app_usbd.c" />
+    <ClCompile Include="..\bmd380_sdk\components\libraries\usbd\app_usbd_core.c" />
+    <ClCompile Include="..\bmd380_sdk\components\libraries\usbd\app_usbd_serial_num.c" />
+    <ClCompile Include="..\bmd380_sdk\components\libraries\usbd\app_usbd_string_desc.c" />
+    <ClCompile Include="..\bmd380_sdk\components\libraries\usbd\class\cdc\acm\app_usbd_cdc_acm.c" />
+    <ClCompile Include="..\bmd380_sdk\components\libraries\usbd\class\nrf_dfu_trigger\app_usbd_nrf_dfu_trigger.c" />
+    <ClInclude Include="..\bmd380_sdk\components\libraries\usbd\app_usbd.h" />
+    <ClInclude Include="..\bmd380_sdk\components\libraries\usbd\app_usbd_class_base.h" />
+    <ClInclude Include="..\bmd380_sdk\components\libraries\usbd\app_usbd_core.h" />
+    <ClInclude Include="..\bmd380_sdk\components\libraries\usbd\app_usbd_descriptor.h" />
+    <ClInclude Include="..\bmd380_sdk\components\libraries\usbd\app_usbd_langid.h" />
+    <ClInclude Include="..\bmd380_sdk\components\libraries\usbd\app_usbd_request.h" />
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+      <Filter>Source files\ble_nus</Filter>
+    </ClCompile>
+    <ClInclude Include="..\bmd380_sdk\components\ble\ble_services\ble_nus\ble_nus.h">
+      <Filter>Header files\ble_nus</Filter>
+    </ClInclude>
+    <ClCompile Include="uart.drv.c">
       <Filter>Source files</Filter>
     </ClCompile>
   </ItemGroup>
@@ -1627,7 +1960,112 @@
     <ClInclude Include="..\bmd380_sdk\components\libraries\pwr_mgmt\nrf_pwr_mgmt.h">
       <Filter>Header files</Filter>
     </ClInclude>
-    <ClInclude Include="led.h">
+    <ClInclude Include="apa102_2020.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="led_drv.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="led_drv_if.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="dac_drv_if.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="max5136.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="dac_drv.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="adc_drv.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="adc_drv_if.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="ads8691.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="adgs1412.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="builtin_saadc.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="sw_drv.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="sw_drv_if.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="gd25d10c.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="block_dev_drv_if.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="fs.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="edc.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="edc20_io.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="eis.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="elite.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="elite_adc.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="elite_board.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="elite_correction.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="elite_dac.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="elite_def.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="btn.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="elite_dev.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="pel.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="tw1508.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="cpg.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="cpg11_io.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="max14802.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="pel20_io.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="usbd.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="uart_drv.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="le_uart_srv.h">
       <Filter>Header files</Filter>
     </ClInclude>
   </ItemGroup>