wisetop/microchip-application-bmd380-bmd380_peripheral
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gpio相關的函式都放在edc20_pin_ctrl.c (包含gpio、spi、i2c)

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This commit is contained in:
Roy_01
2024-03-08 11:16:01 +08:00
parent 0c9b8d2b8d
commit 6d8edfbf40
8 changed files with 376 additions and 343 deletions
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bmd380_peripheral.vcxproj
+3 -2
View File
@@ -180,10 +180,10 @@
<ClCompile Include="..\bmd380_sdk\integration\nrfx\legacy\nrf_drv_uart.c">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|VisualGDB'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="edc20_pin_ctrl.c" />
<ClCompile Include="edc_2_0.c" />
<ClCompile Include="eis_2_0.c" />
<ClCompile Include="elite.c" />
<ClCompile Include="i2c.c" />
<ClCompile Include="led.c" />
<ClCompile Include="le_adv.c" />
<ClCompile Include="le_dfu.c" />
@@ -192,7 +192,6 @@
<ClCompile Include="le_gatt.c" />
<ClCompile Include="le_srv.c" />
<ClCompile Include="main.c" />
<ClCompile Include="spi.c" />
<ClCompile Include="syscalls.c" />
<None Include="nRF52811_XXAA_s140.lds" />
<None Include="nRF52840_XXAA_S140_reserve.lds" />
@@ -338,8 +337,10 @@
<ClInclude Include="..\bmd380_sdk\integration\nrfx\nrfx_log.h" />
<ClInclude Include="app_config.h" />
<ClInclude Include="edc.h" />
<ClInclude Include="edc20_pin_ctrl.h" />
<ClInclude Include="eis.h" />
<ClInclude Include="elite.h" />
<ClInclude Include="elite_pin_ctrl.h" />
<ClInclude Include="FreeRTOSConfig.h" />
<ClInclude Include="elite_def.h" />
<ClInclude Include="led.h" />
edc20_pin_ctrl.c
+301
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@@ -0,0 +1,301 @@
#include "nrf_drv_spi.h"
#include "nrf_drv_twi.h"
#include "nrf_gpio.h"
#include "nrf_log.h"
#include "FreeRTOS.h"
#include "queue.h"
#include "semphr.h"
#include "edc20_pin_ctrl.h"
//==========================================================
// gpio
//==========================================================
void gpio_init(void)
{
nrf_gpio_pin_set(POWER_5V_EN_PIN);
nrf_gpio_pin_set(POWER_12V_EN_PIN);
nrf_gpio_pin_set(CS_SW_PIN);
nrf_gpio_pin_set(CS_MEM_PIN);
nrf_gpio_pin_set(CS_ADC_PIN);
nrf_gpio_pin_set(CS_DAC_PIN);
nrf_gpio_pin_set(OFF_PIN);
nrf_gpio_pin_clear(Vout_FB_PIN);
nrf_gpio_pin_clear(Vout_IN_PIN);
nrf_gpio_pin_clear(Iin4_TEST_PIN);
nrf_gpio_pin_clear(Iin3_SEL_PIN);
nrf_gpio_pin_clear(Iin3_PIN);
nrf_gpio_pin_clear(Iin2_PIN);
nrf_gpio_pin_clear(Iin1_PIN);
nrf_gpio_pin_clear(Vin2_PIN);
nrf_gpio_pin_clear(Vin1_PIN);
nrf_gpio_pin_clear(CV_CTRL_PIN);
nrf_gpio_pin_clear(ADCA2_PIN);
nrf_gpio_pin_clear(ADCA1_PIN);
nrf_gpio_pin_clear(ADCA0_PIN);
nrf_gpio_pin_clear(RST_SW_PIN);
nrf_gpio_cfg_output(POWER_5V_EN_PIN);
nrf_gpio_cfg_output(POWER_12V_EN_PIN);
nrf_gpio_cfg_output(OFF_PIN);
nrf_gpio_cfg_output(Vout_FB_PIN);
nrf_gpio_cfg_output(Vout_IN_PIN);
nrf_gpio_cfg_output(Iin4_TEST_PIN);
nrf_gpio_cfg_output(Iin3_SEL_PIN);
nrf_gpio_cfg_output(Iin3_PIN);
nrf_gpio_cfg_output(Iin2_PIN);
nrf_gpio_cfg_output(Iin1_PIN);
nrf_gpio_cfg_output(Vin2_PIN);
nrf_gpio_cfg_output(Vin1_PIN);
nrf_gpio_cfg_output(CV_CTRL_PIN);
nrf_gpio_cfg_output(ADCA2_PIN);
nrf_gpio_cfg_output(ADCA1_PIN);
nrf_gpio_cfg_output(ADCA0_PIN);
nrf_gpio_cfg_output(RST_SW_PIN);
nrf_gpio_cfg_output(CS_SW_PIN);
nrf_gpio_cfg_output(CS_MEM_PIN);
nrf_gpio_cfg_output(CS_ADC_PIN);
nrf_gpio_cfg_output(CS_DAC_PIN);
nrf_gpio_cfg_input(VBAT_PIN, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(SHUT_DOWN_PIN, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(INT9466_PIN, NRF_GPIO_PIN_NOPULL);
}
//==========================================================
// i2c
//==========================================================
static const nrf_drv_twi_t twi0 = NRF_DRV_TWI_INSTANCE(0);
static SemaphoreHandle_t i2c_sem = NULL;
static SemaphoreHandle_t i2c_mutex = NULL;
static QueueHandle_t i2c_evt_queue = NULL;
static void nrf_drv_twi_evt_handler(nrf_drv_twi_evt_t const *p_event, void *p_context)
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
xQueueSendFromISR(i2c_evt_queue, p_event, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
}
void twi_init(void)
{
ret_code_t err_code;
i2c_sem = xSemaphoreCreateBinary();
i2c_mutex = xSemaphoreCreateMutex();
i2c_evt_queue = xQueueCreate(2, sizeof(nrf_drv_twi_evt_t));
const nrf_drv_twi_config_t twi0_config = {
.scl = I2C0_SCL,
.sda = I2C0_SDA,
.frequency = NRF_DRV_TWI_FREQ_100K,
.interrupt_priority = APP_IRQ_PRIORITY_HIGH,
.clear_bus_init = true
};
err_code = nrf_drv_twi_init(&twi0, &twi0_config, nrf_drv_twi_evt_handler, NULL);
APP_ERROR_CHECK(err_code);
nrf_drv_twi_enable(&twi0);
}
void twi0_write_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t data_len)
{
xSemaphoreTake(i2c_mutex, portMAX_DELAY);
static uint8_t i2c_buf[255];
static nrf_drv_twi_evt_t evt;
ret_code_t err_code;
memcpy(i2c_buf, &reg_addr, sizeof(reg_addr));
memcpy(i2c_buf + sizeof(reg_addr), data, data_len);
err_code = nrf_drv_twi_tx(&twi0, slave_addr, i2c_buf, data_len + 1, false);
APP_ERROR_CHECK(err_code);
xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
switch (evt.type)
{
/* Transfer completed event. */
case NRF_DRV_TWI_EVT_DONE:
// TODO...
break;
/* Error event: NACK received after sending the address. */
case NRF_DRV_TWI_EVT_ADDRESS_NACK:
// TODO...
__BKPT(255);
break;
/* Error event: NACK received after sending a data byte. */
case NRF_DRV_TWI_EVT_DATA_NACK:
// TODO...
__BKPT(255);
break;
default:
__BKPT(255);
break;
}
xSemaphoreGive(i2c_mutex);
NRF_LOG_INFO("i2c(W): slave_addr=0x%02x", slave_addr);
NRF_LOG_HEXDUMP_INFO(i2c_buf, data_len + 1);
}
void twi0_read_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *p_rx_buf, uint8_t rx_buffer_length)
{
xSemaphoreTake(i2c_mutex, portMAX_DELAY);
nrf_drv_twi_evt_t evt;
ret_code_t err_code;
err_code = nrf_drv_twi_tx(&twi0, slave_addr, &reg_addr, sizeof(reg_addr), false);
APP_ERROR_CHECK(err_code);
xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
switch (evt.type)
{
/* Transfer completed event. */
case NRF_DRV_TWI_EVT_DONE:
// TODO...
break;
/* Error event: NACK received after sending the address. */
case NRF_DRV_TWI_EVT_ADDRESS_NACK:
// TODO...
__BKPT(255);
break;
/* Error event: NACK received after sending a data byte. */
case NRF_DRV_TWI_EVT_DATA_NACK:
// TODO...
__BKPT(255);
break;
default:
break;
}
err_code = nrf_drv_twi_rx(&twi0, slave_addr, p_rx_buf, rx_buffer_length);
APP_ERROR_CHECK(err_code);
xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
switch (evt.type)
{
/* Transfer completed event. */
case NRF_DRV_TWI_EVT_DONE:
// TODO...
break;
/* Error event: NACK received after sending the address. */
case NRF_DRV_TWI_EVT_ADDRESS_NACK:
// TODO...
__BKPT(255);
break;
/* Error event: NACK received after sending a data byte. */
case NRF_DRV_TWI_EVT_DATA_NACK:
// TODO...
__BKPT(255);
break;
default:
break;
}
xSemaphoreGive(i2c_mutex);
NRF_LOG_INFO("i2c(R): slave_addr=0x%02x reg_addr=0x%02x", slave_addr, reg_addr);
NRF_LOG_HEXDUMP_INFO(p_rx_buf, rx_buffer_length);
}
//==========================================================
// spi
//==========================================================
static const nrf_drv_spi_t spim1 = NRF_DRV_SPI_INSTANCE(1); /**< SPI instance. */
static const nrf_drv_spi_t spim2 = NRF_DRV_SPI_INSTANCE(2); /**< SPI instance. */
static SemaphoreHandle_t spim1_sem = NULL;
static SemaphoreHandle_t spim2_sem = NULL;
static SemaphoreHandle_t spim2_mutex = NULL;
static void nrf_drv_spim1_evt_handler(nrf_drv_spi_evt_t const *p_event, void *p_context)
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
switch (p_event->type)
{
case NRF_DRV_SPI_EVENT_DONE:
xSemaphoreGiveFromISR(spim1_sem, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
break;
default:
break;
}
}
static void nrf_drv_spim2_evt_handler(nrf_drv_spi_evt_t const *p_event, void *p_context)
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
switch (p_event->type)
{
case NRF_DRV_SPI_EVENT_DONE:
xSemaphoreGiveFromISR(spim2_sem, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
break;
default:
break;
}
}
void spi_init(void)
{
spim1_sem = xSemaphoreCreateBinary();
spim2_sem = xSemaphoreCreateBinary();
spim2_mutex = xSemaphoreCreateMutex();
nrf_drv_spi_config_t spi1_config = NRF_DRV_SPI_DEFAULT_CONFIG;
spi1_config.ss_pin = NRF_DRV_SPI_PIN_NOT_USED;
spi1_config.miso_pin = NRF_DRV_SPI_PIN_NOT_USED;
spi1_config.mosi_pin = SPI1_MOSI_PIN;
spi1_config.sck_pin = SPI1_CLK_PIN;
spi1_config.mode = NRF_DRV_SPI_MODE_0;
spi1_config.frequency = NRF_DRV_SPI_FREQ_8M;
APP_ERROR_CHECK(nrf_drv_spi_init(&spim1, &spi1_config, nrf_drv_spim1_evt_handler, NULL));
nrf_drv_spi_config_t spi2_config = NRF_DRV_SPI_DEFAULT_CONFIG;
spi2_config.ss_pin = NRF_DRV_SPI_PIN_NOT_USED;
spi2_config.miso_pin = SPI2_MISO_PIN;
spi2_config.mosi_pin = SPI2_MOSI_PIN;
spi2_config.sck_pin = SPI2_CLK_PIN;
spi2_config.mode = NRF_DRV_SPI_MODE_0;
spi2_config.frequency = NRF_DRV_SPI_FREQ_8M;
APP_ERROR_CHECK(nrf_drv_spi_init(&spim2, &spi2_config, nrf_drv_spim2_evt_handler, NULL));
}
void spi1_write(uint8_t *p_tx_buffer, uint8_t tx_buffer_length)
{
APP_ERROR_CHECK(nrf_drv_spi_transfer(&spim1, p_tx_buffer, tx_buffer_length, NULL, 0));
xSemaphoreTake(spim1_sem, portMAX_DELAY);
}
void spi2_write(uint32_t cs_pin, uint8_t *p_tx_buffer, uint8_t tx_buffer_length, uint8_t *p_rx_buf, uint8_t rx_buffer_length)
{
xSemaphoreTake(spim2_mutex, portMAX_DELAY);
nrf_gpio_pin_clear(cs_pin);
APP_ERROR_CHECK(nrf_drv_spi_transfer(&spim2, p_tx_buffer, tx_buffer_length, p_rx_buf, rx_buffer_length));
if (xSemaphoreTake(spim2_sem, pdMS_TO_TICKS(100)) == pdFALSE)
{
// TODO... spi transfer timeout.
}
nrf_gpio_pin_set(cs_pin);
xSemaphoreGive(spim2_mutex);
NRF_LOG_INFO("spi(W)");
NRF_LOG_HEXDUMP_INFO(p_tx_buffer, tx_buffer_length);
if (rx_buffer_length > 0)
{
NRF_LOG_INFO("spi(R)");
NRF_LOG_HEXDUMP_INFO(p_rx_buf, rx_buffer_length);
}
}
edc20_pin_ctrl.h
+56
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@@ -0,0 +1,56 @@
#pragma once
#ifndef __EDC20_PIN_CTRL_H__
#define __EDC20_PIN_CTRL_H__
#include <stdint.h>
#include "nrf_drv_spi.h"
#include "nrf_gpio.h"
#define ADCA2_PIN NRF_GPIO_PIN_MAP(0, 25)
#define ADCA1_PIN NRF_GPIO_PIN_MAP(0, 19)
#define ADCA0_PIN NRF_GPIO_PIN_MAP(0, 21)
#define RST_SW_PIN NRF_GPIO_PIN_MAP(0, 17)
#define POWER_5V_EN_PIN NRF_GPIO_PIN_MAP(0, 24)
#define POWER_12V_EN_PIN NRF_GPIO_PIN_MAP(0, 23)
#define OFF_PIN NRF_GPIO_PIN_MAP(0, 15)
#define SHUT_DOWN_PIN NRF_GPIO_PIN_MAP(1, 8)
#define INT9466_PIN NRF_GPIO_PIN_MAP(0, 27)
#define Vout_FB_PIN NRF_GPIO_PIN_MAP(0, 26)
#define Vout_IN_PIN NRF_GPIO_PIN_MAP(0, 4)
#define LEDTH_PIN NRF_GPIO_PIN_MAP(0, 28)
#define Iin4_TEST_PIN NRF_GPIO_PIN_MAP(1, 12)
#define Iin3_SEL_PIN NRF_GPIO_PIN_MAP(1, 14)
#define VBAT_PIN NRF_GPIO_PIN_MAP(0, 3)
#define Iin3_PIN NRF_GPIO_PIN_MAP(1, 13)
#define Iin2_PIN NRF_GPIO_PIN_MAP(1, 3)
#define Iin1_PIN NRF_GPIO_PIN_MAP(1, 10)
#define Vin2_PIN NRF_GPIO_PIN_MAP(1, 6)
#define Vin1_PIN NRF_GPIO_PIN_MAP(1, 11)
#define CV_CTRL_PIN NRF_GPIO_PIN_MAP(0, 16)
#define I2C0_SDA NRF_GPIO_PIN_MAP(0, 11)
#define I2C0_SCL NRF_GPIO_PIN_MAP(0, 22)
#define SPI1_CLK_PIN NRF_GPIO_PIN_MAP(0, 13)
#define SPI1_MOSI_PIN NRF_GPIO_PIN_MAP(0, 14)
#define CS_SW_PIN NRF_GPIO_PIN_MAP(0, 20)
#define CS_MEM_PIN NRF_GPIO_PIN_MAP(0, 8)
#define CS_ADC_PIN NRF_GPIO_PIN_MAP(0, 6)
#define CS_DAC_PIN NRF_GPIO_PIN_MAP(0, 5)
#define SPI2_CLK_PIN NRF_GPIO_PIN_MAP(0, 12)
#define SPI2_MOSI_PIN NRF_GPIO_PIN_MAP(0, 7)
#define SPI2_MISO_PIN NRF_GPIO_PIN_MAP(1, 9)
void gpio_init(void);
void twi_init(void);
void twi0_write_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t data_len);
void twi0_read_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *p_rx_buf, uint8_t rx_buffer_length);
void spi_init(void);
void spi1_write(uint8_t *p_tx_buffer, uint8_t tx_buffer_length);
void spi2_write(uint32_t cs_pin, uint8_t *p_tx_buffer, uint8_t tx_buffer_length, uint8_t *p_rx_buf, uint8_t rx_buffer_length);
#endif // !__EDC20_PIN_CTRL_H__
elite_pin_ctrl.h
+11
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@@ -0,0 +1,11 @@
#pragma once
#ifndef __ELITE_PIN_CTRL_H__
#define __ELITE_PIN_CTRL_H__
#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
#include "edc20_pin_ctrl.h"
#else
#error "Not implemented xxx_pin_ctrl.h"
#endif
#endif // !__ELITE_PIN_CTRL_H__
i2c.c
-149
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@@ -1,149 +0,0 @@
#include "nrf_drv_twi.h"
#include "nrf_gpio.h"
#include "nrf_log.h"
#include "FreeRTOS.h"
#include "queue.h"
#include "semphr.h"
#include "task.h"
#define I2C_SDA NRF_GPIO_PIN_MAP(0, 11)
#define I2C_SCL NRF_GPIO_PIN_MAP(0, 22)
static const nrf_drv_twi_t twi0 = NRF_DRV_TWI_INSTANCE(0);
static SemaphoreHandle_t i2c_sem = NULL;
static SemaphoreHandle_t i2c_mutex = NULL;
static QueueHandle_t i2c_evt_queue = NULL;
void nrf_drv_twi_evt_handler(nrf_drv_twi_evt_t const *p_event, void *p_context)
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
xQueueSendFromISR(i2c_evt_queue, p_event, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
}
void twi0_init(void)
{
ret_code_t err_code;
i2c_sem = xSemaphoreCreateBinary();
i2c_mutex = xSemaphoreCreateMutex();
i2c_evt_queue = xQueueCreate(2, sizeof(nrf_drv_twi_evt_t));
const nrf_drv_twi_config_t twi0_config = {
.scl = I2C_SCL,
.sda = I2C_SDA,
.frequency = NRF_DRV_TWI_FREQ_100K,
.interrupt_priority = APP_IRQ_PRIORITY_HIGH,
.clear_bus_init = true
};
err_code = nrf_drv_twi_init(&twi0, &twi0_config, nrf_drv_twi_evt_handler, NULL);
APP_ERROR_CHECK(err_code);
nrf_drv_twi_enable(&twi0);
}
void twi0_write_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t data_len)
{
xSemaphoreTake(i2c_mutex, portMAX_DELAY);
static uint8_t i2c_buf[255];
static nrf_drv_twi_evt_t evt;
ret_code_t err_code;
memcpy(i2c_buf, &reg_addr, sizeof(reg_addr));
memcpy(i2c_buf + sizeof(reg_addr), data, data_len);
err_code = nrf_drv_twi_tx(&twi0, slave_addr, i2c_buf, data_len + 1, false);
APP_ERROR_CHECK(err_code);
xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
switch (evt.type)
{
/* Transfer completed event. */
case NRF_DRV_TWI_EVT_DONE:
// TODO...
break;
/* Error event: NACK received after sending the address. */
case NRF_DRV_TWI_EVT_ADDRESS_NACK:
// TODO...
__BKPT(255);
break;
/* Error event: NACK received after sending a data byte. */
case NRF_DRV_TWI_EVT_DATA_NACK:
// TODO...
__BKPT(255);
break;
default:
__BKPT(255);
break;
}
xSemaphoreGive(i2c_mutex);
NRF_LOG_INFO("i2c(W): slave_addr=0x%02x", slave_addr);
NRF_LOG_HEXDUMP_INFO(i2c_buf, data_len + 1);
}
void twi0_read_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *p_rx_buf, uint8_t rx_buffer_length)
{
xSemaphoreTake(i2c_mutex, portMAX_DELAY);
nrf_drv_twi_evt_t evt;
ret_code_t err_code;
err_code = nrf_drv_twi_tx(&twi0, slave_addr, &reg_addr, sizeof(reg_addr), false);
APP_ERROR_CHECK(err_code);
xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
switch (evt.type)
{
/* Transfer completed event. */
case NRF_DRV_TWI_EVT_DONE:
// TODO...
break;
/* Error event: NACK received after sending the address. */
case NRF_DRV_TWI_EVT_ADDRESS_NACK:
// TODO...
__BKPT(255);
break;
/* Error event: NACK received after sending a data byte. */
case NRF_DRV_TWI_EVT_DATA_NACK:
// TODO...
__BKPT(255);
break;
default:
break;
}
err_code = nrf_drv_twi_rx(&twi0, slave_addr, p_rx_buf, rx_buffer_length);
APP_ERROR_CHECK(err_code);
xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
switch (evt.type)
{
/* Transfer completed event. */
case NRF_DRV_TWI_EVT_DONE:
// TODO...
break;
/* Error event: NACK received after sending the address. */
case NRF_DRV_TWI_EVT_ADDRESS_NACK:
// TODO...
__BKPT(255);
break;
/* Error event: NACK received after sending a data byte. */
case NRF_DRV_TWI_EVT_DATA_NACK:
// TODO...
__BKPT(255);
break;
default:
break;
}
xSemaphoreGive(i2c_mutex);
NRF_LOG_INFO("i2c(R): slave_addr=0x%02x reg_addr=0x%02x", slave_addr, reg_addr);
NRF_LOG_HEXDUMP_INFO(p_rx_buf, rx_buffer_length);
}
led.c
+3 -3
View File
@@ -1,5 +1,3 @@
#include "led.h"
#include "nrf_gpio.h"
#include "nrf_log.h"
#include "nrf_spim.h"
@@ -8,6 +6,9 @@
#include "semphr.h"
#include "task.h"
#include "elite_pin_ctrl.h"
#include "led.h"
#define DISP_LED_COLOR 0
#define LED_COUNT 12
@@ -31,7 +32,6 @@ const led_t led_default = {
static void led_write(uint8_t *pucData, uint32_t ulSize)
{
extern void spi1_write(uint8_t * p_tx_buffer, uint8_t tx_buffer_length);
spi1_write(pucData, ulSize);
}
main.c
+2 -83
View File
@@ -25,6 +25,7 @@ extern "C"
#include "task.h"
#include "timers.h"
#include "elite_pin_ctrl.h"
#include "led.h"
#ifdef __cplusplus
@@ -105,94 +106,12 @@ static void le_stack_Init(void)
NRF_SDH_BLE_OBSERVER(m_ble_observer, APP_BLE_OBSERVER_PRIO, le_evt_handler, NULL);
}
/* edc2.0 pin */
#define ADCA2_PIN NRF_GPIO_PIN_MAP(0, 25)
#define ADCA1_PIN NRF_GPIO_PIN_MAP(0, 19)
#define ADCA0_PIN NRF_GPIO_PIN_MAP(0, 21)
#define RST_SW_PIN NRF_GPIO_PIN_MAP(0, 17)
#define CS_SW_PIN NRF_GPIO_PIN_MAP(0, 20)
#define OFF_PIN NRF_GPIO_PIN_MAP(0, 15)
#define SHUT_DOWN_PIN NRF_GPIO_PIN_MAP(1, 8)
#define CS_MEM_PIN NRF_GPIO_PIN_MAP(0, 8)
#define CS_ADC_PIN NRF_GPIO_PIN_MAP(0, 6)
#define CS_DAC_PIN NRF_GPIO_PIN_MAP(0, 5)
#define INT9466_PIN NRF_GPIO_PIN_MAP(0, 27)
#define Vout_FB_PIN NRF_GPIO_PIN_MAP(0, 26)
#define Vout_IN_PIN NRF_GPIO_PIN_MAP(0, 4)
#define LEDTH_PIN NRF_GPIO_PIN_MAP(0, 28)
#define Iin4_TEST_PIN NRF_GPIO_PIN_MAP(1, 12)
#define Iin3_SEL_PIN NRF_GPIO_PIN_MAP(1, 14)
#define VBAT_PIN NRF_GPIO_PIN_MAP(0, 3)
#define Iin3_PIN NRF_GPIO_PIN_MAP(1, 13)
#define Iin2_PIN NRF_GPIO_PIN_MAP(1, 3)
#define Iin1_PIN NRF_GPIO_PIN_MAP(1, 10)
#define Vin2_PIN NRF_GPIO_PIN_MAP(1, 6)
#define Vin1_PIN NRF_GPIO_PIN_MAP(1, 11)
#define POWER_5V_EN_PIN NRF_GPIO_PIN_MAP(0, 24)
#define POWER_12V_EN_PIN NRF_GPIO_PIN_MAP(0, 23)
#define CV_CTRL_PIN NRF_GPIO_PIN_MAP(0, 16)
void gpio_init(void)
{
nrf_gpio_pin_set(POWER_5V_EN_PIN);
nrf_gpio_pin_set(POWER_12V_EN_PIN);
nrf_gpio_pin_set(CS_SW_PIN);
nrf_gpio_pin_set(CS_MEM_PIN);
nrf_gpio_pin_set(CS_ADC_PIN);
nrf_gpio_pin_set(CS_DAC_PIN);
nrf_gpio_pin_set(OFF_PIN);
nrf_gpio_pin_clear(Vout_FB_PIN);
nrf_gpio_pin_clear(Vout_IN_PIN);
nrf_gpio_pin_clear(Iin4_TEST_PIN);
nrf_gpio_pin_clear(Iin3_SEL_PIN);
nrf_gpio_pin_clear(Iin3_PIN);
nrf_gpio_pin_clear(Iin2_PIN);
nrf_gpio_pin_clear(Iin1_PIN);
nrf_gpio_pin_clear(Vin2_PIN);
nrf_gpio_pin_clear(Vin1_PIN);
nrf_gpio_pin_clear(CV_CTRL_PIN);
nrf_gpio_pin_clear(ADCA2_PIN);
nrf_gpio_pin_clear(ADCA1_PIN);
nrf_gpio_pin_clear(ADCA0_PIN);
nrf_gpio_pin_clear(RST_SW_PIN);
nrf_gpio_cfg_output(POWER_5V_EN_PIN);
nrf_gpio_cfg_output(POWER_12V_EN_PIN);
nrf_gpio_cfg_output(OFF_PIN);
nrf_gpio_cfg_output(Vout_FB_PIN);
nrf_gpio_cfg_output(Vout_IN_PIN);
nrf_gpio_cfg_output(Iin4_TEST_PIN);
nrf_gpio_cfg_output(Iin3_SEL_PIN);
nrf_gpio_cfg_output(Iin3_PIN);
nrf_gpio_cfg_output(Iin2_PIN);
nrf_gpio_cfg_output(Iin1_PIN);
nrf_gpio_cfg_output(Vin2_PIN);
nrf_gpio_cfg_output(Vin1_PIN);
nrf_gpio_cfg_output(CV_CTRL_PIN);
nrf_gpio_cfg_output(ADCA2_PIN);
nrf_gpio_cfg_output(ADCA1_PIN);
nrf_gpio_cfg_output(ADCA0_PIN);
nrf_gpio_cfg_output(RST_SW_PIN);
nrf_gpio_cfg_output(CS_SW_PIN);
nrf_gpio_cfg_output(CS_MEM_PIN);
nrf_gpio_cfg_output(CS_ADC_PIN);
nrf_gpio_cfg_output(CS_DAC_PIN);
nrf_gpio_cfg_input(VBAT_PIN, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(SHUT_DOWN_PIN, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(INT9466_PIN, NRF_GPIO_PIN_NOPULL);
}
static void nrf_sdh_freertos_task_hook(void *p_context)
{
extern void twi0_init(void);
extern void spi_init(void);
UNUSED_PARAMETER(p_context);
gpio_init();
twi0_init();
twi_init();
spi_init();
led_init();
spi.c
-106
View File
@@ -1,106 +0,0 @@
#include "nrf_drv_spi.h"
#include "nrf_gpio.h"
#include "nrf_log.h"
#include "FreeRTOS.h"
#include "semphr.h"
#include "task.h"
#define SPI1_CLK_PIN NRF_GPIO_PIN_MAP(0, 13)
#define SPI1_MOSI_PIN NRF_GPIO_PIN_MAP(0, 14)
#define SPI2_CLK_PIN NRF_GPIO_PIN_MAP(0, 12)
#define SPI2_MOSI_PIN NRF_GPIO_PIN_MAP(0, 7)
#define SPI2_MISO_PIN NRF_GPIO_PIN_MAP(1, 9)
static const nrf_drv_spi_t spim1 = NRF_DRV_SPI_INSTANCE(1); /**< SPI instance. */
static const nrf_drv_spi_t spim2 = NRF_DRV_SPI_INSTANCE(2); /**< SPI instance. */
static SemaphoreHandle_t spim1_sem = NULL;
static SemaphoreHandle_t spim2_sem = NULL;
static SemaphoreHandle_t spim2_mutex = NULL;
void nrf_drv_spim1_evt_handler(nrf_drv_spi_evt_t const *p_event, void *p_context)
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
switch (p_event->type)
{
case NRF_DRV_SPI_EVENT_DONE:
xSemaphoreGiveFromISR(spim1_sem, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
break;
default:
break;
}
}
void nrf_drv_spim2_evt_handler(nrf_drv_spi_evt_t const *p_event, void *p_context)
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
switch (p_event->type)
{
case NRF_DRV_SPI_EVENT_DONE:
xSemaphoreGiveFromISR(spim2_sem, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
break;
default:
break;
}
}
void spi_init(void)
{
spim1_sem = xSemaphoreCreateBinary();
spim2_sem = xSemaphoreCreateBinary();
spim2_mutex = xSemaphoreCreateMutex();
nrf_drv_spi_config_t spi1_config = NRF_DRV_SPI_DEFAULT_CONFIG;
spi1_config.ss_pin = NRF_DRV_SPI_PIN_NOT_USED;
spi1_config.miso_pin = NRF_DRV_SPI_PIN_NOT_USED;
spi1_config.mosi_pin = SPI1_MOSI_PIN;
spi1_config.sck_pin = SPI1_CLK_PIN;
spi1_config.mode = NRF_DRV_SPI_MODE_0;
spi1_config.frequency = NRF_DRV_SPI_FREQ_8M;
APP_ERROR_CHECK(nrf_drv_spi_init(&spim1, &spi1_config, nrf_drv_spim1_evt_handler, NULL));
nrf_drv_spi_config_t spi2_config = NRF_DRV_SPI_DEFAULT_CONFIG;
spi2_config.ss_pin = NRF_DRV_SPI_PIN_NOT_USED;
spi2_config.miso_pin = SPI2_MISO_PIN;
spi2_config.mosi_pin = SPI2_MOSI_PIN;
spi2_config.sck_pin = SPI2_CLK_PIN;
spi2_config.mode = NRF_DRV_SPI_MODE_0;
spi2_config.frequency = NRF_DRV_SPI_FREQ_8M;
APP_ERROR_CHECK(nrf_drv_spi_init(&spim2, &spi2_config, nrf_drv_spim2_evt_handler, NULL));
}
void spi1_write(uint8_t *p_tx_buffer, uint8_t tx_buffer_length)
{
APP_ERROR_CHECK(nrf_drv_spi_transfer(&spim1, p_tx_buffer, tx_buffer_length, NULL, 0));
xSemaphoreTake(spim1_sem, portMAX_DELAY);
}
void spi2_write(uint32_t cs_pin, uint8_t *p_tx_buffer, uint8_t tx_buffer_length, uint8_t *p_rx_buf, uint8_t rx_buffer_length)
{
xSemaphoreTake(spim2_mutex, portMAX_DELAY);
nrf_gpio_pin_clear(cs_pin);
APP_ERROR_CHECK(nrf_drv_spi_transfer(&spim2, p_tx_buffer, tx_buffer_length, p_rx_buf, rx_buffer_length));
if (xSemaphoreTake(spim2_sem, pdMS_TO_TICKS(100)) == pdFALSE)
{
// TODO... spi transfer timeout.
}
nrf_gpio_pin_set(cs_pin);
xSemaphoreGive(spim2_mutex);
NRF_LOG_INFO("spi(W)");
NRF_LOG_HEXDUMP_INFO(p_tx_buffer, tx_buffer_length);
if (rx_buffer_length > 0)
{
NRF_LOG_INFO("spi(R)");
NRF_LOG_HEXDUMP_INFO(p_rx_buf, rx_buffer_length);
}
}