Compare commits
42 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
| acd0080929 | |||
| 1cde4cfe02 | |||
| 764bd9364d | |||
| b5e0026f2e | |||
| 823016d4b7 | |||
| bee57486e0 | |||
| 214222cb1e | |||
| 38572e128d | |||
| 9e19642081 | |||
| 5f2a258f49 | |||
| d5158775b8 | |||
| 282b8077a7 | |||
| 5b6430cec9 | |||
| 9484008d1e | |||
| bd0c282d25 | |||
| acd590de44 | |||
| b8d96c32b0 | |||
| c3ab78e16a | |||
| fde824ee34 | |||
| fc3adb450c | |||
| 747752640a | |||
| 7a73097666 | |||
| 8a95874b0b | |||
| 9db0984a92 | |||
| b9c9cc0bbc | |||
| cd44c2ecaa | |||
| 3bb5cee129 | |||
| 2480d7775f | |||
| 3b9e972397 | |||
| 36df3abed1 | |||
| 918584c915 | |||
| cc0a21c364 | |||
| 388c06efe7 | |||
| 8bcb4cd27e | |||
| 5d88871e58 | |||
| 8635b1b878 | |||
| 6e9acfda78 | |||
| 81d5d86890 | |||
| 0c8c92dc83 | |||
| 308de54833 | |||
| e4c999b8c7 | |||
| 5c0c2cc9a5 |
@@ -8,7 +8,7 @@ no device y=ax+b MAC a+ b+ a- b- avg
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||||
7 c652 c652 18:04:ED:37:C6:52 2024 -7687 2086 -11283 4.88850143182858
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||||
8 c5ed c5ed 18:04:ED:37:C5:ED 2231 -1711 2353 -70845 4.45265043545859
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||||
9 9bef 9bef 0081F9E49BEF 2383 -8585 2415 -20347 4.2758539244186
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||||
10 8b50 8b50 00:81:F9:E4:8B:50 2369 -11005 2360 -11797 4.30475635707671
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||||
10 8b50 8b50 00:81:F9:E4:8B:50 2366 -5223 2402 -14971 4.35162291666667
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||||
11 c641 c641 18:04:ED:37:C6:41 2090 4616 1997 -40665 5.07591391714942
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||||
12 E8E6 E8E6 A4:DA:32:D4:E8:E6 2306 -88454 2418 -15140 4.2686494968089
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||||
13 E73B E73B A4:DA:32:D4:E7:3B 2262 -564 2298 44746 4.35551198222141
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+1
-1
@@ -4,7 +4,7 @@
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#folder=$($path | awk -F"/" '{$NF}')
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folder=$(basename "$(pwd)")
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if [ "$folder" == "ti" ]; then
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if [ "$folder" == "ti" ] ; then
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year=$(date +%-y)
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month=$(date +%-m)
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day=$(date +%-d)
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BIN
Binary file not shown.
BIN
Binary file not shown.
+3
-3
@@ -103,7 +103,7 @@ typedef enum {
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READ_REG, // read DBS register value, used after a "read" SPI instruction (MISO)
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READ_REG2, // read DBS register value, used after a "read" SPI instruction (MISO)
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END_TRANSMIT, // read DBS register value, used after a "read" SPI instruction (MISO)
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ONE_SHOT_SPI, // end spi instruction
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CONTI_SPI_WITH_FLUSH, // end spi instruction
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READ_MOSI
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} SPI_CB_MODE;
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@@ -214,7 +214,7 @@ extern ICall_Semaphore semaphore;
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// command return characteristic
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#define BLE_CDR_BUFF_CHAR SIMPLEPROFILE_CHAR2
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#define BLE_CDR_BUFF_SIZE SIMPLEPROFILE_CHAR2_LEN
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#define BLE_CDR_SAMLL_SIZE 10
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#define BLE_CDR_SMALL_SIZE 10
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// instruction input characteristic
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#define BLE_INS_BUFF_CHAR SIMPLEPROFILE_CHAR3
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@@ -356,7 +356,7 @@ static uint16_t CONNECT_HANDLE = 0;
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/**
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* command instruction buffer
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*/
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static uint8_t cdr_buf[BLE_CDR_SAMLL_SIZE] = {0};
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static uint8_t cdr_buf[BLE_CDR_SMALL_SIZE] = {0};
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/*====================
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==== event table ====
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+4
-5
@@ -27,14 +27,14 @@ static void SendCaliValue(uint8_t CaliNumber){
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// ch = 2 * (CaliNumber % 4);
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// uint8_t gain_level = CaliNumber / 4; // 0:gain, 1:offset
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uint8_t channel_number = 8, index = 1;
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uint8_t channel_number = 8, index = 2;
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uint8_t gain_level = 0;
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if(CaliNumber < 4){
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gain_level = CaliNumber;
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}
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cali_buf[0] = CHIP_ID;
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cali_buf[1] = CHIP_ID;
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for(int i=0 ; i<channel_number ; i++){
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cali_buf[index++] = (uint8_t) (CaliTable.Ch[i].Gain[gain_level] >> 8) & 0xFF;
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cali_buf[index++] = (uint8_t) CaliTable.Ch[i].Gain[gain_level] & 0x00FF;
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@@ -42,9 +42,8 @@ static void SendCaliValue(uint8_t CaliNumber){
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cali_buf[index++] = (uint8_t) CaliTable.Ch[i].Offset[gain_level] & 0x00FF;
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}
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// for(int i=1 ; i<BLE_CDR_BUFF_SIZE ; i++){
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// cali_buf[i] = i;
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// }
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cali_buf[0] = index - 1;
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SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, index, cali_buf);
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}
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+3
-3
@@ -27,7 +27,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
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check_reg_counter = 0;
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if(check_ins(instruction_to_fit)){
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NEULIVE_STATE.state = next_state;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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// update rec_sti_command
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if(!(rec_sti_command & ENABLE_STI)){
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@@ -70,7 +70,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
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IsFirstData = true;
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}
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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ReopenSPI();
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}
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headstage_spi_transaction(3);
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@@ -167,7 +167,7 @@ static void check_sti_t1_t5(NEU_WORK_STATE next_state){
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else{
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NEULIVE_STATE.state = next_state;
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}
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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headstage_spi_transaction(3);
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}
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+167
@@ -0,0 +1,167 @@
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#ifndef DBS_OBJECT_H
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#define DBS_OBJECT_H
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#include "neu/headstage_spi.h"
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#define SYS_RESERVED_INDEX 0
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#define SYS_GENERAL_ENABLE_INDEX 1
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#define SYS_LNA_BIOS1_INDEX 2
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#define SYS_LNA_BIOS2_INDEX 3
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#define SYS_STI_CLK_RATIO_INDEX 4
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#define REC_CHANNEL_INDEX 0
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#define REC_GAIN_INDEX 1
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#define REC_ADC_CLOCK_INDEX 2
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#define STI_ENABLE_INDEX 0
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#define STI_AMP_POS_INDEX 1
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#define STI_AMP_NEG_INDEX 2
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#define STI_POLARITY_INDEX 3
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#define STI_CYCLE_CH01_INDEX 4
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#define STI_CYCLE_CH23_INDEX 5
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#define STI_CYCLE_CH45_INDEX 6
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#define STI_CYCLE_CH67_INDEX 7
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#define STI_CLK_RATIO_INDEX 8
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#define STI_ARBITRARY_EN_INDEX 9
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#define STI_MODE_INDEX 10
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#define STI_DURATION0_INDEX 11
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#define STI_DURATION1_INDEX 12
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#define STI_DURATION2_INDEX 13
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#define STI_DURATION3_INDEX 14
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//#define DBS_REGISTER \
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// uint8_t address; \
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// void (*write_reg) (DBSRegister *self, uint32_t reg_value); \
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// uint32_t (*read_reg) (DBSRegister *self)
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typedef struct _DBSRegister{
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uint8_t address;
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bool WriteRegister, CheckRegister;
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void (*write_reg) (struct _DBSRegister *self, uint16_t reg_value);
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void (*read_reg) (struct _DBSRegister *self);
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}DBSRegister;
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void write_reg(DBSRegister *self, uint16_t reg_value){
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spi_txbuf[0] = 0x80 | self->address;
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spi_txbuf[1] = (reg_value >> 8) & 0xFF ;
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spi_txbuf[2] = reg_value & 0xFF;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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void read_reg(DBSRegister *self){
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spi_txbuf[0] = 0x7F & self->address;
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spi_txbuf[1] = 0x7F & self->address; // it's don't care actually
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spi_txbuf[2] = 0x7F & self->address; // it's don't care actually
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SPICallBack = READ_REG;
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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static uint16_t sys_register_default_value[5] = {
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0x0000,
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0x40F2,
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0x0210,
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0x4210,
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0x0002
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};
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static uint16_t rec_register_value[3];
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static uint16_t sti_register_value[43];
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static DBSRegister sys_register[5];
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static DBSRegister rec_register[3];
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static DBSRegister sti_register[43];
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static void InitSysRegister(){
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sys_register[SYS_RESERVED_INDEX].address = 0x00;
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sys_register[SYS_GENERAL_ENABLE_INDEX].address = 47; // general enable
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sys_register[SYS_LNA_BIOS1_INDEX].address = 57;
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sys_register[SYS_LNA_BIOS2_INDEX].address = 58;
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sys_register[SYS_STI_CLK_RATIO_INDEX].address = 52;
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for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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sys_register[i].WriteRegister = false;
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sys_register[i].CheckRegister = false;
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sys_register[i].write_reg = &write_reg;
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sys_register[i].read_reg = &read_reg;
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}
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}
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static void InitRecRegister(){
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rec_register[REC_CHANNEL_INDEX].address = 48;
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rec_register[REC_GAIN_INDEX].address = 49;
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rec_register[REC_ADC_CLOCK_INDEX].address = 51; // sampling rate
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for(int i=0 ; i<sizeof(rec_register)/sizeof(DBSRegister) ; i++){
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rec_register[i].WriteRegister = false;
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rec_register[i].CheckRegister = false;
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rec_register[i].write_reg = &write_reg;
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rec_register[i].read_reg = &read_reg;
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}
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}
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static void InitStiRegister(){
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sti_register[STI_ENABLE_INDEX].address = 46;
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sti_register[STI_AMP_POS_INDEX].address = 37;
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sti_register[STI_AMP_NEG_INDEX].address = 38;
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sti_register[STI_POLARITY_INDEX].address = 40;
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sti_register[STI_CYCLE_CH01_INDEX].address = 42;
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sti_register[STI_CYCLE_CH23_INDEX].address = 43;
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sti_register[STI_CYCLE_CH45_INDEX].address = 44;
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sti_register[STI_CYCLE_CH67_INDEX].address = 45;
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sti_register[STI_CLK_RATIO_INDEX].address = 52;
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sti_register[STI_ARBITRARY_EN_INDEX].address = 54;
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sti_register[STI_MODE_INDEX].address = 56;
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for(int ch=0 ; ch<8 ; ch++){
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sti_register[ch*4 + STI_DURATION0_INDEX].address = ch*4 + 1;
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sti_register[ch*4 + STI_DURATION1_INDEX].address = ch*4 + 2;
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sti_register[ch*4 + STI_DURATION2_INDEX].address = ch*4 + 3;
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sti_register[ch*4 + STI_DURATION3_INDEX].address = ch*4 + 4;
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}
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for(int i=0 ; i<sizeof(sti_register)/sizeof(DBSRegister) ; i++){
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sti_register[i].WriteRegister = false;
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sti_register[i].CheckRegister = false;
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sti_register[i].write_reg = &write_reg;
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sti_register[i].read_reg = &read_reg;
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}
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}
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static void InitDBSRegister(){
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InitSysRegister();
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InitRecRegister();
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InitStiRegister();
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// for(int i=1 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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for(int i=1 ; i<5 ; i++){
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sys_register[i].WriteRegister = true;
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}
|
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flag_notify(EVT_NEU_SPI);
|
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}
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|
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static void ResetDBSRegister(){
|
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for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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sys_register[i].WriteRegister = false;
|
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sys_register[i].CheckRegister = false;
|
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sys_register[i].write_reg = &write_reg;
|
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sys_register[i].read_reg = &read_reg;
|
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}
|
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|
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for(int i=0 ; i<sizeof(rec_register)/sizeof(DBSRegister) ; i++){
|
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rec_register[i].WriteRegister = false;
|
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rec_register[i].CheckRegister = false;
|
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rec_register[i].write_reg = &write_reg;
|
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rec_register[i].read_reg = &read_reg;
|
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}
|
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|
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for(int i=0 ; i<sizeof(sti_register)/sizeof(DBSRegister) ; i++){
|
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sti_register[i].WriteRegister = false;
|
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sti_register[i].CheckRegister = false;
|
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sti_register[i].write_reg = &write_reg;
|
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sti_register[i].read_reg = &read_reg;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
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+438
-285
File diff suppressed because it is too large
Load Diff
+6
-6
@@ -3,15 +3,15 @@
|
||||
#define VERSION_DATE
|
||||
|
||||
#define VERSION_DATE_YEAR 20
|
||||
#define VERSION_DATE_MONTH 8
|
||||
#define VERSION_DATE_DAY 3
|
||||
#define VERSION_DATE_HOUR 17
|
||||
#define VERSION_DATE_MINUTE 42
|
||||
#define VERSION_DATE_MONTH 11
|
||||
#define VERSION_DATE_DAY 13
|
||||
#define VERSION_DATE_HOUR 18
|
||||
#define VERSION_DATE_MINUTE 30
|
||||
|
||||
// this is NOT the version hash !!
|
||||
// it's the last version hash
|
||||
#define VERSION_HASH f4861bb6cb427dcb36cb0cb6e8f1c962dbd89fa8
|
||||
#define VERSION_GIT_BRANCH neulive20_linux_debug
|
||||
#define VERSION_HASH 1cde4cfe026202aae24460eb1cf778477a9828e3
|
||||
#define VERSION_GIT_BRANCH neulive_onchange_central_debug
|
||||
|
||||
static void get_board_name(char *board_name_ch, uint8 *board_name_int, uint8 name_size){
|
||||
uint8 name_offset = 18;
|
||||
|
||||
+51
-11
@@ -8,12 +8,60 @@
|
||||
#error "headstage/headstage_notify.h not included"
|
||||
#endif
|
||||
|
||||
#include "headstage_dbs_object.h"
|
||||
|
||||
#define NOT_BUF_OFFSET_INIT 8
|
||||
|
||||
static uint8_t not_buf_offset = NOT_BUF_OFFSET_INIT;
|
||||
static uint32_t not_time_stamp = 0;
|
||||
|
||||
static uint32_t debug_counter = 0;
|
||||
static void headstage_notify_set_timestamp();
|
||||
static void headstage_notify_flip_buffer();
|
||||
static uint8_t headstage_notify_append_data(uint8_t *data_value);
|
||||
|
||||
/**
|
||||
* @fn headstage_neu_append_notify_data
|
||||
*/
|
||||
#define CHANNEL_VALID (INSTRUCTION.recording_channel & (0x0001 << channel))
|
||||
static void headstage_neu_append_notify_data() {
|
||||
|
||||
uint8_t channel = spi_rxbuf[0];
|
||||
|
||||
// close-reopen SPI, if the first channel received is invalid
|
||||
if(IsFirstData){
|
||||
// start record
|
||||
if((INSTRUCTION.recording_channel & (0x0001 << channel)) && (channel < 16)){
|
||||
IsFirstData = false;
|
||||
}
|
||||
// restart SPI
|
||||
else{
|
||||
SPI_close(headstage_spi_handle);
|
||||
ReopenSPI();
|
||||
IsFirstData = true;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// discard illegal channel
|
||||
uint16_t valid_channel = INSTRUCTION.recording_channel & (0x0001 << channel);
|
||||
if(!(INSTRUCTION.recording_channel & (0x0001 << channel)) || (channel > 15)){
|
||||
// illegal channel
|
||||
return;
|
||||
}
|
||||
|
||||
uint8_t not_buf[2];
|
||||
not_buf[0] = (channel & 0x0F) << 4 | (spi_rxbuf[1] & 0x0F);
|
||||
not_buf[1] = spi_rxbuf[2];
|
||||
|
||||
uint8_t data_size = headstage_notify_append_data(not_buf);
|
||||
|
||||
if (data_size >= BLE_NOT_BUFF_SIZE) {
|
||||
headstage_notify_flip_buffer();
|
||||
headstage_notify_send();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void headstage_notify_set_timestamp() {
|
||||
not_time_stamp = headstage_time_stamp_us();
|
||||
|
||||
@@ -21,18 +69,12 @@ static void headstage_notify_set_timestamp() {
|
||||
headstage_notify_buffer[3] = (not_time_stamp >> 8) & 0xFF;
|
||||
headstage_notify_buffer[4] = (not_time_stamp >> 16) & 0xFF;
|
||||
headstage_notify_buffer[5] = (not_time_stamp >> 24) & 0xFF;
|
||||
|
||||
// headstage_notify_buffer[2] = (debug_counter >> 24) & 0xFF;
|
||||
// headstage_notify_buffer[3] = (debug_counter >> 16) & 0xFF;
|
||||
// headstage_notify_buffer[4] = (debug_counter >> 8) & 0xFF;
|
||||
// headstage_notify_buffer[5] = debug_counter & 0xFF;
|
||||
// debug_counter ++;
|
||||
}
|
||||
|
||||
static void headstage_notify_flip_buffer() {
|
||||
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 3;
|
||||
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 2;
|
||||
|
||||
headstage_notify_buffer[0] = 4;
|
||||
headstage_notify_buffer[0] = CHIP_ID;
|
||||
headstage_notify_buffer[1] = data_count;
|
||||
|
||||
not_buf_offset = NOT_BUF_OFFSET_INIT;
|
||||
@@ -47,11 +89,9 @@ static uint8_t headstage_notify_append_data(uint8_t *data_value) {
|
||||
if (data_value == NULL) {
|
||||
headstage_notify_buffer[not_buf_offset++] = 0x00;
|
||||
headstage_notify_buffer[not_buf_offset++] = 0x00;
|
||||
headstage_notify_buffer[not_buf_offset++] = 0x00;
|
||||
} else {
|
||||
headstage_notify_buffer[not_buf_offset++] = data_value[0];
|
||||
headstage_notify_buffer[not_buf_offset++] = data_value[1];
|
||||
headstage_notify_buffer[not_buf_offset++] = data_value[2];
|
||||
}
|
||||
|
||||
if (not_buf_offset >= BLE_NOT_BUFF_SIZE - 1) {
|
||||
|
||||
+2
-2
@@ -25,7 +25,7 @@ static void MCUReset(){
|
||||
spi_txbuf[i] = 0;
|
||||
spi_rxbuf[i] = 0;
|
||||
}
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
ReopenSPI();
|
||||
|
||||
for(int i=0 ; i<SPI_LED_BUFF_SIZE ; i++){
|
||||
@@ -33,7 +33,7 @@ static void MCUReset(){
|
||||
}
|
||||
|
||||
// CIS buffer reset
|
||||
for(int i=0 ; i<BLE_CDR_SAMLL_SIZE ; i++){
|
||||
for(int i=0 ; i<BLE_CDR_SMALL_SIZE ; i++){
|
||||
cdr_buf[i] = 0;
|
||||
}
|
||||
|
||||
|
||||
+68
@@ -120,4 +120,72 @@ static void AppendSPITX(uint8_t index, uint32_t value){
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn headstage_spi_callback
|
||||
*
|
||||
* description: callback function to deal with data transmission between DBS and CC2650
|
||||
*/
|
||||
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction) {
|
||||
switch(SPICallBack){
|
||||
case CONTINUOUS_TRANS:{
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER:{
|
||||
SPICallBack = FLUSH_BUFFER2;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER2:{
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
// headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case CONTI_SPI_WITH_FLUSH:{
|
||||
SPICallBack = FLUSH_BUFFER;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_MOSI:{
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_REG:{
|
||||
check_reg_counter ++;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case CLOSE_SPI:{
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
SPI_close(headstage_spi_handle);
|
||||
break;
|
||||
}
|
||||
|
||||
case END_TRANSMIT:{
|
||||
tx_put_u24(0, 0);
|
||||
SPICallBack = CONTINUOUS_TRANS;
|
||||
break;
|
||||
}
|
||||
default:{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
+4
-3
@@ -120,17 +120,17 @@
|
||||
// Maximum connection interval (units of 1.25ms, 800=1000ms) if automatic
|
||||
// parameter update request is enabled
|
||||
//#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 6
|
||||
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 40
|
||||
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 30
|
||||
|
||||
#else //! FEATURE_OAD
|
||||
// Minimum connection interval (units of 1.25ms, 8=10ms) if automatic
|
||||
// parameter update request is enabled
|
||||
#define DEFAULT_DESIRED_MIN_CONN_INTERVAL 8
|
||||
#define DEFAULT_DESIRED_MIN_CONN_INTERVAL 80
|
||||
//#define DEFAULT_DESIRED_MIN_CONN_INTERVAL 14
|
||||
|
||||
// Maximum connection interval (units of 1.25ms, 8=10ms) if automatic
|
||||
// parameter update request is enabled
|
||||
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 40
|
||||
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 80
|
||||
//#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 25
|
||||
|
||||
#endif // FEATURE_OAD
|
||||
@@ -561,6 +561,7 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
|
||||
headstage_init_device_info();
|
||||
|
||||
headstage_init();
|
||||
InitDBSRegister();
|
||||
|
||||
for (;;) {
|
||||
// Waits for a signal to the semaphore associated with the calling thread.
|
||||
|
||||
@@ -82,7 +82,8 @@ extern "C" {
|
||||
|
||||
// Length of Characteristic 5 in bytes
|
||||
#define SIMPLEPROFILE_CHAR1_LEN 2
|
||||
#define SIMPLEPROFILE_CHAR2_LEN 50
|
||||
//#define SIMPLEPROFILE_CHAR2_LEN 50
|
||||
#define SIMPLEPROFILE_CHAR2_LEN 34
|
||||
#define SIMPLEPROFILE_CHAR3_LEN 20
|
||||
#define SIMPLEPROFILE_CHAR4_LEN 200
|
||||
//#define SIMPLEPROFILE_CHAR4_LEN 20
|
||||
|
||||
Reference in New Issue
Block a user