Compare commits
42 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
| acd0080929 | |||
| 1cde4cfe02 | |||
| 764bd9364d | |||
| b5e0026f2e | |||
| 823016d4b7 | |||
| bee57486e0 | |||
| 214222cb1e | |||
| 38572e128d | |||
| 9e19642081 | |||
| 5f2a258f49 | |||
| d5158775b8 | |||
| 282b8077a7 | |||
| 5b6430cec9 | |||
| 9484008d1e | |||
| bd0c282d25 | |||
| acd590de44 | |||
| b8d96c32b0 | |||
| c3ab78e16a | |||
| fde824ee34 | |||
| fc3adb450c | |||
| 747752640a | |||
| 7a73097666 | |||
| 8a95874b0b | |||
| 9db0984a92 | |||
| b9c9cc0bbc | |||
| cd44c2ecaa | |||
| 3bb5cee129 | |||
| 2480d7775f | |||
| 3b9e972397 | |||
| 36df3abed1 | |||
| 918584c915 | |||
| cc0a21c364 | |||
| 388c06efe7 | |||
| 8bcb4cd27e | |||
| 5d88871e58 | |||
| 8635b1b878 | |||
| 6e9acfda78 | |||
| 81d5d86890 | |||
| 0c8c92dc83 | |||
| 308de54833 | |||
| e4c999b8c7 | |||
| 5c0c2cc9a5 |
@@ -8,7 +8,7 @@ no device y=ax+b MAC a+ b+ a- b- avg
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||||
7 c652 c652 18:04:ED:37:C6:52 2024 -7687 2086 -11283 4.88850143182858
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||||
8 c5ed c5ed 18:04:ED:37:C5:ED 2231 -1711 2353 -70845 4.45265043545859
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||||
9 9bef 9bef 0081F9E49BEF 2383 -8585 2415 -20347 4.2758539244186
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||||
10 8b50 8b50 00:81:F9:E4:8B:50 2369 -11005 2360 -11797 4.30475635707671
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||||
10 8b50 8b50 00:81:F9:E4:8B:50 2366 -5223 2402 -14971 4.35162291666667
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11 c641 c641 18:04:ED:37:C6:41 2090 4616 1997 -40665 5.07591391714942
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12 E8E6 E8E6 A4:DA:32:D4:E8:E6 2306 -88454 2418 -15140 4.2686494968089
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13 E73B E73B A4:DA:32:D4:E7:3B 2262 -564 2298 44746 4.35551198222141
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+1
-1
@@ -4,7 +4,7 @@
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#folder=$($path | awk -F"/" '{$NF}')
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folder=$(basename "$(pwd)")
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if [ "$folder" == "bioprocc2650" ]; then
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if [ "$folder" == "ti" ] ; then
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year=$(date +%-y)
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month=$(date +%-m)
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day=$(date +%-d)
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BIN
Binary file not shown.
BIN
Binary file not shown.
+3
-3
@@ -103,7 +103,7 @@ typedef enum {
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READ_REG, // read DBS register value, used after a "read" SPI instruction (MISO)
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READ_REG2, // read DBS register value, used after a "read" SPI instruction (MISO)
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END_TRANSMIT, // read DBS register value, used after a "read" SPI instruction (MISO)
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ONE_SHOT_SPI, // end spi instruction
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CONTI_SPI_WITH_FLUSH, // end spi instruction
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READ_MOSI
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} SPI_CB_MODE;
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@@ -214,7 +214,7 @@ extern ICall_Semaphore semaphore;
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// command return characteristic
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#define BLE_CDR_BUFF_CHAR SIMPLEPROFILE_CHAR2
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#define BLE_CDR_BUFF_SIZE SIMPLEPROFILE_CHAR2_LEN
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#define BLE_CDR_SAMLL_SIZE 10
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#define BLE_CDR_SMALL_SIZE 10
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// instruction input characteristic
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#define BLE_INS_BUFF_CHAR SIMPLEPROFILE_CHAR3
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@@ -356,7 +356,7 @@ static uint16_t CONNECT_HANDLE = 0;
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/**
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* command instruction buffer
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*/
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static uint8_t cdr_buf[BLE_CDR_SAMLL_SIZE] = {0};
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static uint8_t cdr_buf[BLE_CDR_SMALL_SIZE] = {0};
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/*====================
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==== event table ====
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+4
-5
@@ -27,14 +27,14 @@ static void SendCaliValue(uint8_t CaliNumber){
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// ch = 2 * (CaliNumber % 4);
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// uint8_t gain_level = CaliNumber / 4; // 0:gain, 1:offset
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uint8_t channel_number = 8, index = 1;
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uint8_t channel_number = 8, index = 2;
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uint8_t gain_level = 0;
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if(CaliNumber < 4){
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gain_level = CaliNumber;
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}
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cali_buf[0] = CHIP_ID;
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cali_buf[1] = CHIP_ID;
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for(int i=0 ; i<channel_number ; i++){
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cali_buf[index++] = (uint8_t) (CaliTable.Ch[i].Gain[gain_level] >> 8) & 0xFF;
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cali_buf[index++] = (uint8_t) CaliTable.Ch[i].Gain[gain_level] & 0x00FF;
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@@ -42,9 +42,8 @@ static void SendCaliValue(uint8_t CaliNumber){
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cali_buf[index++] = (uint8_t) CaliTable.Ch[i].Offset[gain_level] & 0x00FF;
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}
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// for(int i=1 ; i<BLE_CDR_BUFF_SIZE ; i++){
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// cali_buf[i] = i;
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// }
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cali_buf[0] = index - 1;
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SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, index, cali_buf);
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}
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+3
-3
@@ -27,7 +27,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
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check_reg_counter = 0;
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if(check_ins(instruction_to_fit)){
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NEULIVE_STATE.state = next_state;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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// update rec_sti_command
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if(!(rec_sti_command & ENABLE_STI)){
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@@ -70,7 +70,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
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IsFirstData = true;
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}
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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ReopenSPI();
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}
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headstage_spi_transaction(3);
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@@ -167,7 +167,7 @@ static void check_sti_t1_t5(NEU_WORK_STATE next_state){
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else{
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NEULIVE_STATE.state = next_state;
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}
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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headstage_spi_transaction(3);
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}
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+167
@@ -0,0 +1,167 @@
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#ifndef DBS_OBJECT_H
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#define DBS_OBJECT_H
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#include "neu/headstage_spi.h"
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#define SYS_RESERVED_INDEX 0
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#define SYS_GENERAL_ENABLE_INDEX 1
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#define SYS_LNA_BIOS1_INDEX 2
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#define SYS_LNA_BIOS2_INDEX 3
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#define SYS_STI_CLK_RATIO_INDEX 4
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#define REC_CHANNEL_INDEX 0
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#define REC_GAIN_INDEX 1
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#define REC_ADC_CLOCK_INDEX 2
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#define STI_ENABLE_INDEX 0
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#define STI_AMP_POS_INDEX 1
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#define STI_AMP_NEG_INDEX 2
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#define STI_POLARITY_INDEX 3
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#define STI_CYCLE_CH01_INDEX 4
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#define STI_CYCLE_CH23_INDEX 5
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#define STI_CYCLE_CH45_INDEX 6
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#define STI_CYCLE_CH67_INDEX 7
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#define STI_CLK_RATIO_INDEX 8
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#define STI_ARBITRARY_EN_INDEX 9
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#define STI_MODE_INDEX 10
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#define STI_DURATION0_INDEX 11
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#define STI_DURATION1_INDEX 12
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#define STI_DURATION2_INDEX 13
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#define STI_DURATION3_INDEX 14
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//#define DBS_REGISTER \
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// uint8_t address; \
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// void (*write_reg) (DBSRegister *self, uint32_t reg_value); \
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// uint32_t (*read_reg) (DBSRegister *self)
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typedef struct _DBSRegister{
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uint8_t address;
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bool WriteRegister, CheckRegister;
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void (*write_reg) (struct _DBSRegister *self, uint16_t reg_value);
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void (*read_reg) (struct _DBSRegister *self);
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}DBSRegister;
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void write_reg(DBSRegister *self, uint16_t reg_value){
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spi_txbuf[0] = 0x80 | self->address;
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spi_txbuf[1] = (reg_value >> 8) & 0xFF ;
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spi_txbuf[2] = reg_value & 0xFF;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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void read_reg(DBSRegister *self){
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spi_txbuf[0] = 0x7F & self->address;
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spi_txbuf[1] = 0x7F & self->address; // it's don't care actually
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spi_txbuf[2] = 0x7F & self->address; // it's don't care actually
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SPICallBack = READ_REG;
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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static uint16_t sys_register_default_value[5] = {
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0x0000,
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0x40F2,
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0x0210,
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0x4210,
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0x0002
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};
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static uint16_t rec_register_value[3];
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static uint16_t sti_register_value[43];
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static DBSRegister sys_register[5];
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static DBSRegister rec_register[3];
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static DBSRegister sti_register[43];
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static void InitSysRegister(){
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sys_register[SYS_RESERVED_INDEX].address = 0x00;
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sys_register[SYS_GENERAL_ENABLE_INDEX].address = 47; // general enable
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sys_register[SYS_LNA_BIOS1_INDEX].address = 57;
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sys_register[SYS_LNA_BIOS2_INDEX].address = 58;
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sys_register[SYS_STI_CLK_RATIO_INDEX].address = 52;
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for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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sys_register[i].WriteRegister = false;
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sys_register[i].CheckRegister = false;
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sys_register[i].write_reg = &write_reg;
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sys_register[i].read_reg = &read_reg;
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}
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}
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static void InitRecRegister(){
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rec_register[REC_CHANNEL_INDEX].address = 48;
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rec_register[REC_GAIN_INDEX].address = 49;
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rec_register[REC_ADC_CLOCK_INDEX].address = 51; // sampling rate
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for(int i=0 ; i<sizeof(rec_register)/sizeof(DBSRegister) ; i++){
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rec_register[i].WriteRegister = false;
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rec_register[i].CheckRegister = false;
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rec_register[i].write_reg = &write_reg;
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rec_register[i].read_reg = &read_reg;
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}
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}
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static void InitStiRegister(){
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sti_register[STI_ENABLE_INDEX].address = 46;
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sti_register[STI_AMP_POS_INDEX].address = 37;
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sti_register[STI_AMP_NEG_INDEX].address = 38;
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sti_register[STI_POLARITY_INDEX].address = 40;
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sti_register[STI_CYCLE_CH01_INDEX].address = 42;
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sti_register[STI_CYCLE_CH23_INDEX].address = 43;
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sti_register[STI_CYCLE_CH45_INDEX].address = 44;
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sti_register[STI_CYCLE_CH67_INDEX].address = 45;
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sti_register[STI_CLK_RATIO_INDEX].address = 52;
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sti_register[STI_ARBITRARY_EN_INDEX].address = 54;
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sti_register[STI_MODE_INDEX].address = 56;
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for(int ch=0 ; ch<8 ; ch++){
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sti_register[ch*4 + STI_DURATION0_INDEX].address = ch*4 + 1;
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sti_register[ch*4 + STI_DURATION1_INDEX].address = ch*4 + 2;
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sti_register[ch*4 + STI_DURATION2_INDEX].address = ch*4 + 3;
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sti_register[ch*4 + STI_DURATION3_INDEX].address = ch*4 + 4;
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}
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for(int i=0 ; i<sizeof(sti_register)/sizeof(DBSRegister) ; i++){
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sti_register[i].WriteRegister = false;
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sti_register[i].CheckRegister = false;
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sti_register[i].write_reg = &write_reg;
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sti_register[i].read_reg = &read_reg;
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}
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}
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static void InitDBSRegister(){
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InitSysRegister();
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InitRecRegister();
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InitStiRegister();
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// for(int i=1 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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for(int i=1 ; i<5 ; i++){
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sys_register[i].WriteRegister = true;
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}
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flag_notify(EVT_NEU_SPI);
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}
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static void ResetDBSRegister(){
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for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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sys_register[i].WriteRegister = false;
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sys_register[i].CheckRegister = false;
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sys_register[i].write_reg = &write_reg;
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sys_register[i].read_reg = &read_reg;
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}
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for(int i=0 ; i<sizeof(rec_register)/sizeof(DBSRegister) ; i++){
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rec_register[i].WriteRegister = false;
|
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rec_register[i].CheckRegister = false;
|
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rec_register[i].write_reg = &write_reg;
|
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rec_register[i].read_reg = &read_reg;
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}
|
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|
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for(int i=0 ; i<sizeof(sti_register)/sizeof(DBSRegister) ; i++){
|
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sti_register[i].WriteRegister = false;
|
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sti_register[i].CheckRegister = false;
|
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sti_register[i].write_reg = &write_reg;
|
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sti_register[i].read_reg = &read_reg;
|
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}
|
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}
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||||
|
||||
#endif
|
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+438
-192
@@ -160,13 +160,17 @@ static void FlushNotify();
|
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#define NEU_REC_PARAM 0x20
|
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#define NEU_MULTI_STI 0x40
|
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#define NEU_TEST_INS 0x60
|
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#define RIS_STOP_STI 0x80
|
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#define RIS_REC_ON_CHANGE 0x80
|
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#define RIS_STI_ON_CHANGE 0xA0
|
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|
||||
/** event */
|
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#define EVT_NEU_SPI 0x0001 /**< spi transaction event */
|
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#define EVT_NEU_LED 0x0002 /**< set led event */
|
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#define EVT_NEU_CHECK 0x0004 /**< check neulive single instruction */
|
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#define EVT_NEU_REG_SPI 0x0008 /** register spi event */
|
||||
#define EVT_NEU_PREPARE 0x0010 /** prepare to record or stimulate **/
|
||||
#define EVT_NEU_REC 0x0020
|
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#define EVT_NEU_STI 0x0040
|
||||
|
||||
/** clock setting */
|
||||
#define NEU_SYS_CLK 2000000 /**< 10Mhz */
|
||||
@@ -298,7 +302,7 @@ typedef enum{
|
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#include "string.h"
|
||||
#include "headstage_rec_ins.h"
|
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#include "headstage_sti_ins.h"
|
||||
|
||||
#include "headstage_dbs_object.h"
|
||||
|
||||
/*
|
||||
* todo: need to define some procedure to detect this device status
|
||||
@@ -338,53 +342,8 @@ static void headstage_init() {
|
||||
#undef THREE_POINT_THREE_VOLT
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn headstage_neu_append_notify_data
|
||||
*/
|
||||
#define CHANNEL_VALID (INSTRUCTION.recording_channel & (0x0001 << channel))
|
||||
static void headstage_neu_append_notify_data() {
|
||||
|
||||
uint8_t channel = spi_rxbuf[0];
|
||||
|
||||
// close-reopen SPI, if the first channel received is invalid
|
||||
if(IsFirstData){
|
||||
// start record
|
||||
if((INSTRUCTION.recording_channel & (0x0001 << channel)) && (channel < 16)){
|
||||
IsFirstData = false;
|
||||
}
|
||||
// restart SPI
|
||||
else{
|
||||
SPI_close(headstage_spi_handle);
|
||||
ReopenSPI();
|
||||
IsFirstData = true;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// discard illegal channel
|
||||
// uint16_t valid_channel = INSTRUCTION.recording_channel & (0x0001 << channel);
|
||||
if(!(INSTRUCTION.recording_channel & (0x0001 << channel)) || (channel > 15)){
|
||||
// illegal channel
|
||||
return;
|
||||
}
|
||||
|
||||
uint8_t not_buf[3];
|
||||
not_buf[0] = channel; // ch
|
||||
not_buf[1] = spi_rxbuf[1];
|
||||
not_buf[2] = spi_rxbuf[2];
|
||||
|
||||
// not_buf[1] = (INSTRUCTION.recording_channel | 0xFF00) >> 8;
|
||||
// not_buf[2] = (INSTRUCTION.recording_channel | 0x00FF);
|
||||
|
||||
uint8_t data_size = headstage_notify_append_data(not_buf);
|
||||
|
||||
if (data_size >= BLE_NOT_BUFF_SIZE) {
|
||||
headstage_notify_flip_buffer();
|
||||
headstage_notify_send();
|
||||
}
|
||||
}
|
||||
|
||||
static void headstage_neu_state_spi();
|
||||
static void headstage_neu_spi();
|
||||
|
||||
/**
|
||||
* @fn headstage_neu_event
|
||||
@@ -393,93 +352,27 @@ static void headstage_neu_state_spi();
|
||||
*/
|
||||
|
||||
static void headstage_neu_event() {
|
||||
if (EVENT_MASK == 0) {
|
||||
// fast return
|
||||
return;
|
||||
}
|
||||
|
||||
if (flag_mask(EVT_NEU_SPI)) {
|
||||
flag_disable(EVT_NEU_SPI);
|
||||
headstage_neu_state_spi();
|
||||
// headstage_neu_state_spi();
|
||||
headstage_neu_spi();
|
||||
}
|
||||
|
||||
if (flag_mask(EVT_NEU_LED)) {
|
||||
flag_disable(EVT_NEU_LED); /** reserved to set led power and set color manually */
|
||||
}
|
||||
|
||||
if (EVENT_MASK == 0) {
|
||||
// fast return
|
||||
}
|
||||
|
||||
if (flag_mask(EVT_DISCONNECTED)) {
|
||||
ConnectState = false;
|
||||
headstage_update_vis_instruction(VIS_INT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn headstage_spi_callback
|
||||
*
|
||||
* description: callback function to deal with data transmission between DBS and CC2650
|
||||
*/
|
||||
|
||||
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction) {
|
||||
switch(SPICallBack){
|
||||
case CONTINUOUS_TRANS:{
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER:{
|
||||
SPICallBack = FLUSH_BUFFER2;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER2:{
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
// headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case ONE_SHOT_SPI:{
|
||||
SPICallBack = FLUSH_BUFFER;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_MOSI:{
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_REG:{
|
||||
check_reg_counter ++;
|
||||
break;
|
||||
}
|
||||
|
||||
case CLOSE_SPI:{
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPI_close(headstage_spi_handle);
|
||||
break;
|
||||
}
|
||||
|
||||
case END_TRANSMIT:{
|
||||
tx_put_u24(0, 0);
|
||||
SPICallBack = CONTINUOUS_TRANS;
|
||||
break;
|
||||
}
|
||||
default:{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn headstage_update_ris_instruction
|
||||
*
|
||||
@@ -614,6 +507,123 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
|
||||
break;
|
||||
}
|
||||
|
||||
case RIS_REC_ON_CHANGE:{
|
||||
uint16_t reg_value = instruction[2] << 8 | instruction[3];
|
||||
switch(instruction[1]){
|
||||
case REC_CHANNEL_INDEX:{
|
||||
rec_register[REC_CHANNEL_INDEX].WriteRegister = true;
|
||||
rec_register_value[REC_CHANNEL_INDEX] = reg_value;
|
||||
INSTRUCTION.recording_channel = reg_value;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case REC_GAIN_INDEX:{
|
||||
rec_register[REC_GAIN_INDEX].WriteRegister = true;
|
||||
rec_register_value[REC_GAIN_INDEX] = reg_value;
|
||||
// flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case REC_ADC_CLOCK_INDEX:{
|
||||
rec_register[REC_ADC_CLOCK_INDEX].WriteRegister = true;
|
||||
rec_register_value[REC_ADC_CLOCK_INDEX] = reg_value;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
default:{
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case RIS_STI_ON_CHANGE:{
|
||||
uint16_t sti_reg_value = instruction[2] << 8 | instruction[3];
|
||||
switch(instruction[1]){
|
||||
case STI_ENABLE_INDEX:{
|
||||
sti_register_value[STI_ENABLE_INDEX] = sti_reg_value;
|
||||
INSTRUCTION.sti_channel = sti_reg_value;
|
||||
break;
|
||||
}
|
||||
|
||||
case STI_AMP_POS_INDEX:{
|
||||
sti_register[STI_AMP_POS_INDEX].WriteRegister = true;
|
||||
sti_register_value[STI_AMP_POS_INDEX] = sti_reg_value;
|
||||
|
||||
// pos, neg amplitude should be same at this DBS version
|
||||
sti_register[STI_AMP_NEG_INDEX].WriteRegister = true;
|
||||
sti_register_value[STI_AMP_NEG_INDEX] = sti_reg_value;
|
||||
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case STI_AMP_NEG_INDEX:{
|
||||
sti_register[STI_AMP_NEG_INDEX].WriteRegister = true;
|
||||
sti_register_value[STI_AMP_NEG_INDEX] = sti_reg_value;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case STI_POLARITY_INDEX:{
|
||||
sti_register[STI_POLARITY_INDEX].WriteRegister = true;
|
||||
sti_register_value[STI_POLARITY_INDEX] = sti_reg_value;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case STI_MODE_INDEX:{
|
||||
sti_register[STI_MODE_INDEX].WriteRegister = true;
|
||||
sti_register_value[STI_MODE_INDEX] = instruction[2];
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case STI_CYCLE_CH01_INDEX:{
|
||||
sti_register[STI_CYCLE_CH01_INDEX].WriteRegister = true;
|
||||
sti_register_value[STI_CYCLE_CH01_INDEX] = sti_reg_value;
|
||||
sti_register[STI_CYCLE_CH23_INDEX].WriteRegister = true;
|
||||
sti_register_value[STI_CYCLE_CH23_INDEX] = sti_reg_value;
|
||||
sti_register[STI_CYCLE_CH45_INDEX].WriteRegister = true;
|
||||
sti_register_value[STI_CYCLE_CH45_INDEX] = sti_reg_value;
|
||||
sti_register[STI_CYCLE_CH67_INDEX].WriteRegister = true;
|
||||
sti_register_value[STI_CYCLE_CH67_INDEX] = sti_reg_value;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case STI_DURATION0_INDEX:{
|
||||
uint16_t t1 = instruction[2] << 8 | instruction[3]; // t1 is 10 bits
|
||||
uint16_t t2 = instruction[4] << 8 | instruction[5]; // t2 is 10 bits
|
||||
uint16_t t3 = instruction[6] << 8 | instruction[7]; // t3 is 10 bits
|
||||
uint32_t t4 = instruction[8] << 16 | instruction[9] << 8 | instruction[10]; // t4 is 17 bits
|
||||
uint16_t t5 = instruction[11] << 8 | instruction[12]; // t5 is 10 bits
|
||||
|
||||
for(int ch=0 ; ch<8 ; ch++){
|
||||
sti_register[ch*4 + STI_DURATION0_INDEX].WriteRegister = true;
|
||||
sti_register_value[ch*4 + STI_DURATION0_INDEX] = (t2 & 0x003F) << 10 | (t1 & 0x03FF);
|
||||
|
||||
sti_register[ch*4 + STI_DURATION1_INDEX].WriteRegister = true;
|
||||
sti_register_value[ch*4 + STI_DURATION1_INDEX] = (t4 & 0x0003) << 14 | (t3 & 0x03FF) << 4 | (t2 & 0x03C0) >> 6;
|
||||
|
||||
sti_register[ch*4 + STI_DURATION2_INDEX].WriteRegister = true;
|
||||
sti_register_value[ch*4 + STI_DURATION2_INDEX] = (t4 & 0x0007FFFC) >> 2;
|
||||
|
||||
sti_register[ch*4 + STI_DURATION3_INDEX].WriteRegister = true;
|
||||
sti_register_value[ch*4 + STI_DURATION3_INDEX] = t5;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
default:{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
default: {
|
||||
break;
|
||||
}
|
||||
@@ -634,50 +644,53 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
|
||||
FlushNotify();
|
||||
}
|
||||
NEULIVE_STATE.state = NEU_RST;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
/**< stop spi transaction */
|
||||
break; /**< reset all the parameter */
|
||||
}
|
||||
|
||||
case VIS_FAST_SET:{
|
||||
INSTRUCTION.sti_t1[7] = 25;
|
||||
INSTRUCTION.sti_t2[7] = 0;
|
||||
INSTRUCTION.sti_t3[7] = 25;
|
||||
INSTRUCTION.sti_t4[7] = 0;
|
||||
INSTRUCTION.sti_t5[7] = 0;
|
||||
uint8_t ch = 7;
|
||||
uint8_t t1=25, t2=0, t3=25 , t4=0, t5=0;
|
||||
|
||||
INSTRUCTION.sti_t1[7] = 25;
|
||||
INSTRUCTION.sti_t2[7] = 0;
|
||||
INSTRUCTION.sti_t3[7] = 25;
|
||||
INSTRUCTION.sti_t4[7] = 0;
|
||||
INSTRUCTION.sti_t5[7] = 0;
|
||||
// using ch8 to fast settle
|
||||
INSTRUCTION.sti_channel = 0b0000000010000000;
|
||||
sti_register_value[STI_ENABLE_INDEX] = 0b0000000010000000; // 0bxxxx_xxxv_cccc_cccc, c = current; v = volt, x = don't care
|
||||
sti_register[STI_ENABLE_INDEX].WriteRegister = true;
|
||||
|
||||
INSTRUCTION.current_sti_cycle[7] = 0;
|
||||
INSTRUCTION.current_sti_cycle[8] = 10; // ch8 is volt ch
|
||||
INSTRUCTION.sti_channel = 0b0000000010000000; // 0bxxxx_xxxv_cccc_cccc, c = current; v = volt, x = don't care
|
||||
INSTRUCTION.arbitrary_en = 0;
|
||||
INSTRUCTION.arbitrary_index = 0;
|
||||
INSTRUCTION.sti_mode = 0; // 1 = continuous mode; 0 = limit mode
|
||||
INSTRUCTION.sti_h_bridge = 0; // voltage sti must use H-bridge
|
||||
INSTRUCTION.sti_ref = 0; // 1 = GND; 0 = Vref
|
||||
// setting t1~t5
|
||||
sti_register_value[ch*4 + STI_DURATION0_INDEX] = (t2 & 0x003F) << 10 | (t1 & 0x03FF);
|
||||
sti_register_value[ch*4 + STI_DURATION1_INDEX] = (t4 & 0x0003) << 14 | (t3 & 0x03FF) << 4 | (t2 & 0x03C0) >> 6;
|
||||
sti_register_value[ch*4 + STI_DURATION2_INDEX] = (t4 & 0x0007FFFC) >> 2;
|
||||
sti_register_value[ch*4 + STI_DURATION3_INDEX] = t5;
|
||||
sti_register[ch*4 + STI_DURATION0_INDEX].WriteRegister = true;
|
||||
sti_register[ch*4 + STI_DURATION1_INDEX].WriteRegister = true;
|
||||
sti_register[ch*4 + STI_DURATION2_INDEX].WriteRegister = true;
|
||||
sti_register[ch*4 + STI_DURATION3_INDEX].WriteRegister = true;
|
||||
|
||||
/* the first byte decide current sti polarity */
|
||||
// e.g. 0b0000_0101 => ch0, ch2 positive, others negative
|
||||
// cycle number
|
||||
sti_register_value[STI_CYCLE_CH67_INDEX] = 10 << 8 | 0;
|
||||
sti_register[STI_CYCLE_CH67_INDEX].WriteRegister = true;
|
||||
|
||||
/* the second byte decide voltage sti polarity */
|
||||
// for the second byte, 0bxxxx_XXXX, decide voltage sti p & n channel;
|
||||
// xxxx is p-channel (16 choose 1), XXXX is n-channel
|
||||
INSTRUCTION.current_sti_polarity = 0b1000000000000000;
|
||||
INSTRUCTION.sti_amplitude_h = 0x0000; // it's t1 amplitude
|
||||
INSTRUCTION.sti_amplitude_l = 0x0000; // it's t3 amplitude
|
||||
INSTRUCTION.voltage_sti_amplitude = 0x0F;
|
||||
// set polarity, it's don't care in fast settle
|
||||
sti_register_value[STI_POLARITY_INDEX] = 0;
|
||||
sti_register[STI_POLARITY_INDEX].WriteRegister = true;
|
||||
|
||||
// set stimulate mode
|
||||
sti_register_value[STI_MODE_INDEX] = 0;
|
||||
sti_register[STI_MODE_INDEX].WriteRegister = true;
|
||||
// INSTRUCTION.sti_mode = 0; // 1 = continuous mode; 0 = limit mode
|
||||
// INSTRUCTION.sti_h_bridge = 0; // voltage sti must use H-bridge
|
||||
// INSTRUCTION.sti_ref = 0; // 1 = GND; 0 = Vref
|
||||
|
||||
// using minimum amplitude
|
||||
sti_register_value[STI_AMP_POS_INDEX] = 0;
|
||||
sti_register_value[STI_AMP_NEG_INDEX] = 0;
|
||||
sti_register[STI_AMP_POS_INDEX].WriteRegister = true;
|
||||
sti_register[STI_AMP_NEG_INDEX].WriteRegister = true;
|
||||
|
||||
rec_sti_command |= ENABLE_STI;
|
||||
NEULIVE_STATE.state = NEU_WRITE_STI_INS;
|
||||
NEULIVE_STATE.config_type = NEU_WARM_UP;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
INSTRUCTION.ins_opcode = T_ZE;
|
||||
|
||||
// is neu wording now?
|
||||
if( (rec_sti_command & STATUS_STI) || (rec_sti_command & STATUS_REC) ){
|
||||
@@ -713,7 +726,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
|
||||
}
|
||||
|
||||
NEULIVE_STATE.config_type = NEU_WARM_UP;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
// is neu wording now?
|
||||
if( (rec_sti_command & STATUS_STI) || (rec_sti_command & STATUS_REC) ){
|
||||
@@ -726,14 +739,13 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
|
||||
}
|
||||
|
||||
case VIS_REC: {
|
||||
|
||||
if(INSTRUCTION.recording_channel){
|
||||
rec_sti_command |= ENABLE_REC;
|
||||
NEULIVE_STATE.state = NEU_WRITE_REC_INS;
|
||||
INSTRUCTION.ins_opcode = BIAS_ONE;
|
||||
|
||||
NEULIVE_STATE.config_type = NEU_WARM_UP;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
// is neu wording now?
|
||||
if( (rec_sti_command & STATUS_STI) || (rec_sti_command & STATUS_REC) ){
|
||||
@@ -751,7 +763,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
|
||||
rec_sti_command |= ENABLE_STI;
|
||||
NEULIVE_STATE.state = NEU_WRITE_STI_INS;
|
||||
NEULIVE_STATE.config_type = NEU_WARM_UP;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
INSTRUCTION.ins_opcode = T_ZE;
|
||||
|
||||
// is neu wording now?
|
||||
@@ -768,6 +780,8 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
|
||||
case VIS_STOP_REC:{
|
||||
rec_sti_command &= ~ENABLE_REC;
|
||||
|
||||
ResetDBSRegister();
|
||||
|
||||
// is neu wording now?
|
||||
if( (rec_sti_command & STATUS_STI) || (rec_sti_command & STATUS_REC) ){
|
||||
// nothing to do
|
||||
@@ -796,7 +810,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
|
||||
rec_sti_command &= ~ENABLE_REC;
|
||||
rec_sti_command &= ~ENABLE_STI;
|
||||
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
NEULIVE_STATE.state = NEU_IDLE;
|
||||
STI = false;
|
||||
Neu2Reset();
|
||||
@@ -820,6 +834,10 @@ static void headstage_update_cis_instruction(uint8_t cis_oper) {
|
||||
switch (cis_oper) {
|
||||
case CIS_NOP: {
|
||||
// nothing
|
||||
for(int i=0 ; i<BLE_CDR_SMALL_SIZE ; i++ ){
|
||||
cdr_buf[i] = 0;
|
||||
}
|
||||
|
||||
cdr_buf[0] = _B_4b4b(CIS_NOP, CHIP_ID);
|
||||
cdr_buf[1] = _B_4b4b(CDR_SUCCESS, 0);
|
||||
|
||||
@@ -828,11 +846,16 @@ static void headstage_update_cis_instruction(uint8_t cis_oper) {
|
||||
}
|
||||
//#ifdef HEADSTAGE_CIS_VOLT_H
|
||||
case CIS_VOLT: {
|
||||
cdr_buf[0] = CIS_VOLT | CHIP_ID;
|
||||
cdr_buf[1] = headstage_battery_volt1();
|
||||
cdr_buf[2] = headstage_battery_volt2();
|
||||
for(int i=0 ; i<BLE_CDR_SMALL_SIZE ; i++ ){
|
||||
cdr_buf[i] = 0;
|
||||
}
|
||||
|
||||
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_SAMLL_SIZE, cdr_buf);
|
||||
cdr_buf[0] = BLE_CDR_SMALL_SIZE; // data length
|
||||
cdr_buf[1] = CIS_VOLT | CHIP_ID;
|
||||
cdr_buf[2] = headstage_battery_volt1();
|
||||
cdr_buf[3] = headstage_battery_volt2();
|
||||
|
||||
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_SMALL_SIZE, cdr_buf);
|
||||
|
||||
#define THREE_POINT_THREE_VOLT 845
|
||||
if (AONBatMonBatteryVoltageGet() < THREE_POINT_THREE_VOLT){
|
||||
@@ -862,35 +885,44 @@ static void headstage_update_cis_instruction(uint8_t cis_oper) {
|
||||
//#endif
|
||||
|
||||
case CIS_VERSION:{
|
||||
cdr_buf[0] = VERSION_DATE_YEAR;
|
||||
cdr_buf[1] = VERSION_DATE_MONTH;
|
||||
cdr_buf[2] = VERSION_DATE_DAY;
|
||||
cdr_buf[3] = VERSION_DATE_HOUR;
|
||||
cdr_buf[4] = VERSION_DATE_MINUTE;
|
||||
for(int i=0 ; i<BLE_CDR_SMALL_SIZE ; i++ ){
|
||||
cdr_buf[i] = 0;
|
||||
}
|
||||
|
||||
cdr_buf[0] = BLE_CDR_SMALL_SIZE;
|
||||
cdr_buf[1] = VERSION_DATE_YEAR;
|
||||
cdr_buf[2] = VERSION_DATE_MONTH;
|
||||
cdr_buf[3] = VERSION_DATE_DAY;
|
||||
cdr_buf[4] = VERSION_DATE_HOUR;
|
||||
cdr_buf[5] = VERSION_DATE_MINUTE;
|
||||
|
||||
uint8_t mac_int[4];
|
||||
if( strncmp(CaliTable.DeviceName, "BOARD_TEST", 25)){
|
||||
// has a specific cali data
|
||||
get_board_name(CaliTable.DeviceName, mac_int, 4);
|
||||
cdr_buf[5] = mac_int[0];
|
||||
cdr_buf[6] = mac_int[1];
|
||||
cdr_buf[6] = mac_int[0];
|
||||
cdr_buf[7] = mac_int[1];
|
||||
}
|
||||
else{
|
||||
// this board use default cali setting
|
||||
cdr_buf[5] = 0xAB;
|
||||
cdr_buf[6] = 0xCD;
|
||||
cdr_buf[6] = 0xAB;
|
||||
cdr_buf[7] = 0xCD;
|
||||
}
|
||||
|
||||
|
||||
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_SAMLL_SIZE, cdr_buf);
|
||||
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_SMALL_SIZE, cdr_buf);
|
||||
break;
|
||||
}
|
||||
|
||||
default: {
|
||||
for(int i=0 ; i<BLE_CDR_SMALL_SIZE ; i++ ){
|
||||
cdr_buf[i] = 0;
|
||||
}
|
||||
|
||||
cdr_buf[0] = _B_4b4b(cis_oper, CHIP_ID);
|
||||
cdr_buf[1] = _B_4b4b(CDR_FAILURE, 0);
|
||||
|
||||
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_SAMLL_SIZE, cdr_buf);
|
||||
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_SMALL_SIZE, cdr_buf);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -941,7 +973,7 @@ static void headstage_neu_state_spi() {
|
||||
|
||||
/* recording */
|
||||
case NEU_WRITE_REC_INS: {
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
nxt_ins = build_rec_ins(NEULIVE_STATE.config_type, &value); /**< set instruction one by one in order to set all the parameter.*/
|
||||
NEULIVE_STATE.config_type = nxt_ins;
|
||||
@@ -995,7 +1027,7 @@ static void headstage_neu_state_spi() {
|
||||
value = (0x01 << 23) | (0x33 << 16) | INSTRUCTION.adc_clock_ratio;
|
||||
AppendSPITX(0, value);
|
||||
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
NEULIVE_STATE.state = NEU_CHECK_SAMPLE_RATE;
|
||||
headstage_spi_transaction(3);
|
||||
break;
|
||||
@@ -1009,7 +1041,7 @@ static void headstage_neu_state_spi() {
|
||||
|
||||
case NEU_PREPARE_READ:{
|
||||
if(spi_state_counter < 6){
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
NEULIVE_STATE.state = NEU_PREPARE_READ;
|
||||
spi_state_counter ++;
|
||||
AppendSPITX(0, 0);
|
||||
@@ -1035,22 +1067,22 @@ static void headstage_neu_state_spi() {
|
||||
}
|
||||
case NEU_READ_DATA: {
|
||||
|
||||
// recv sti enable command
|
||||
// sti enable command
|
||||
if( (rec_sti_command & ENABLE_STI) && !(rec_sti_command & STATUS_STI) ){
|
||||
// go to send sti instruction
|
||||
NEULIVE_STATE.state = NEU_WRITE_STI_INS;
|
||||
NEULIVE_STATE.config_type = NEU_WARM_UP;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
INSTRUCTION.ins_opcode = T_ZE;
|
||||
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
|
||||
// recv disable stimulation
|
||||
// disable stimulation
|
||||
else if( !(rec_sti_command & ENABLE_STI) && (rec_sti_command & STATUS_STI) ){
|
||||
NEULIVE_STATE.state = NEU_STI_INT;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
@@ -1059,12 +1091,11 @@ static void headstage_neu_state_spi() {
|
||||
// recv disable recording
|
||||
else if( !(rec_sti_command & ENABLE_REC) ){
|
||||
rec_sti_command &= ~STATUS_REC;
|
||||
headstage_led_color(COLOR_WHITE);
|
||||
headstage_led_control();
|
||||
|
||||
if(rec_sti_command & STATUS_STI){
|
||||
NEULIVE_STATE.state = NEU_STI;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
@@ -1080,7 +1111,7 @@ static void headstage_neu_state_spi() {
|
||||
spi_txbuf[i] = 0;
|
||||
spi_rxbuf[i] = 0;
|
||||
}
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
ReopenSPI();
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
@@ -1098,7 +1129,7 @@ static void headstage_neu_state_spi() {
|
||||
|
||||
/* stimulation */
|
||||
case NEU_WRITE_STI_INS:{
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
nxt_ins = build_sti_ins(NEULIVE_STATE.config_type, &value); /**< set instruction one by one in order to set all the parameter.*/
|
||||
NEULIVE_STATE.config_type = nxt_ins;
|
||||
@@ -1150,7 +1181,7 @@ static void headstage_neu_state_spi() {
|
||||
value = (0x01 << 23) | (0x2E << 16) | INSTRUCTION.sti_channel;
|
||||
AppendSPITX(0, value);
|
||||
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
NEULIVE_STATE.state = NEU_STI_LED;
|
||||
headstage_spi_transaction(3);
|
||||
break;
|
||||
@@ -1161,7 +1192,7 @@ static void headstage_neu_state_spi() {
|
||||
// value = (0x01 << 23) | (0x2E << 16) | INSTRUCTION.sti_channel;
|
||||
// AppendSPITX(0, value);
|
||||
//
|
||||
// SPICallBack = ONE_SHOT_SPI;
|
||||
// SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
// NEULIVE_STATE.state = NEU_CHECK_STI_CH;
|
||||
// headstage_spi_transaction(3);
|
||||
// break;
|
||||
@@ -1178,7 +1209,7 @@ static void headstage_neu_state_spi() {
|
||||
|
||||
headstage_led_control();
|
||||
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
@@ -1189,7 +1220,7 @@ static void headstage_neu_state_spi() {
|
||||
// recv disable sti command
|
||||
if(!(rec_sti_command & ENABLE_STI)){
|
||||
NEULIVE_STATE.state = NEU_STI_INT;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
@@ -1199,7 +1230,7 @@ static void headstage_neu_state_spi() {
|
||||
else if(rec_sti_command & ENABLE_REC){
|
||||
NEULIVE_STATE.state = NEU_WRITE_REC_INS;
|
||||
NEULIVE_STATE.config_type = NEU_WARM_UP;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
INSTRUCTION.ins_opcode = BIAS_ONE;
|
||||
|
||||
AppendSPITX(0, 0);
|
||||
@@ -1219,7 +1250,7 @@ static void headstage_neu_state_spi() {
|
||||
// terminate stimulation
|
||||
case NEU_STI_INT: {
|
||||
NEULIVE_STATE.state = NEU_STI_INT_TWICE;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
value = (0x01 << 23) | (0x2E << 16) | 0;
|
||||
AppendSPITX(0, value);
|
||||
@@ -1229,7 +1260,7 @@ static void headstage_neu_state_spi() {
|
||||
|
||||
case NEU_STI_INT_TWICE: {
|
||||
NEULIVE_STATE.state = NEU_CHECK_STI_INT;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
value = (0x01 << 23) | (0x2E << 16) | 0;
|
||||
AppendSPITX(0, value);
|
||||
@@ -1250,7 +1281,7 @@ static void headstage_neu_state_spi() {
|
||||
|
||||
case NEU_LED:{
|
||||
NEULIVE_STATE.state = NEU_IDLE;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
AppendSPITX(0, 0);
|
||||
headstage_led_control();
|
||||
@@ -1274,4 +1305,219 @@ static void headstage_neu_state_spi() {
|
||||
}
|
||||
}
|
||||
|
||||
static uint8_t check_register_value(DBSRegister *dbs_register, uint8_t reg_size, uint16_t *value_to_fit);
|
||||
static uint8_t write_register(DBSRegister *dbs_register, uint8_t reg_size, uint16_t *value_to_write);
|
||||
static void stimulation_handle();
|
||||
|
||||
static void headstage_neu_spi(){
|
||||
|
||||
// check system register if we have written it before
|
||||
if( check_register_value(sys_register, sizeof(sys_register)/sizeof(DBSRegister), sys_register_default_value) ){
|
||||
return;
|
||||
}
|
||||
// write system register
|
||||
if (write_register(sys_register, sizeof(sys_register)/sizeof(DBSRegister), sys_register_default_value)){
|
||||
return;
|
||||
}
|
||||
|
||||
if(check_register_value(rec_register, sizeof(rec_register)/sizeof(DBSRegister), rec_register_value)){
|
||||
return;
|
||||
}
|
||||
if(write_register(rec_register, sizeof(rec_register)/sizeof(DBSRegister), rec_register_value)){
|
||||
return;
|
||||
}
|
||||
|
||||
if(check_register_value(sti_register, sizeof(sti_register)/sizeof(DBSRegister), sti_register_value)){
|
||||
return;
|
||||
}
|
||||
if(write_register(sti_register, sizeof(sti_register)/sizeof(DBSRegister), sti_register_value)){
|
||||
return;
|
||||
}
|
||||
|
||||
// enable recording channel
|
||||
if(rec_register[REC_CHANNEL_INDEX].WriteRegister){
|
||||
rec_register[REC_CHANNEL_INDEX].WriteRegister = false;
|
||||
rec_register[REC_CHANNEL_INDEX].CheckRegister = true;
|
||||
rec_register[REC_CHANNEL_INDEX].write_reg(rec_register+REC_CHANNEL_INDEX, rec_register_value[REC_CHANNEL_INDEX]);
|
||||
return;
|
||||
}
|
||||
|
||||
// enable stimulation
|
||||
// WriteRegister will only be enable at check_register_value()
|
||||
if(sti_register[STI_ENABLE_INDEX].WriteRegister){
|
||||
sti_register[STI_ENABLE_INDEX].WriteRegister = false;
|
||||
sti_register[STI_ENABLE_INDEX].CheckRegister = true;
|
||||
sti_register[STI_ENABLE_INDEX].write_reg(sti_register+STI_ENABLE_INDEX, sti_register_value[STI_ENABLE_INDEX]);
|
||||
return;
|
||||
}
|
||||
|
||||
// enable/disable stimulation
|
||||
if (((rec_sti_command & ENABLE_STI) && !(rec_sti_command & STATUS_STI) ) ||
|
||||
(!(rec_sti_command & ENABLE_STI) && (rec_sti_command & STATUS_STI))){
|
||||
|
||||
if(rec_sti_command & ENABLE_STI){
|
||||
if(sti_register_value[STI_ENABLE_INDEX]){
|
||||
rec_sti_command |= STATUS_STI;
|
||||
}
|
||||
// change LED base on working status
|
||||
headstage_led_control();
|
||||
|
||||
sti_register[STI_ENABLE_INDEX].WriteRegister = false;
|
||||
sti_register[STI_ENABLE_INDEX].CheckRegister = true;
|
||||
sti_register[STI_ENABLE_INDEX].write_reg(sti_register+STI_ENABLE_INDEX, sti_register_value[STI_ENABLE_INDEX]);
|
||||
return;
|
||||
}
|
||||
else{
|
||||
rec_sti_command &= ~STATUS_STI;
|
||||
headstage_led_control();
|
||||
|
||||
// enable stimulation and check register
|
||||
sti_register[STI_ENABLE_INDEX].WriteRegister = false;
|
||||
sti_register[STI_ENABLE_INDEX].CheckRegister = true;
|
||||
sti_register_value[STI_ENABLE_INDEX] = 0;
|
||||
sti_register[STI_ENABLE_INDEX].write_reg(sti_register+STI_ENABLE_INDEX, sti_register_value[STI_ENABLE_INDEX]);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// start recording
|
||||
if(!(rec_sti_command & STATUS_REC) && (rec_sti_command & ENABLE_REC)){
|
||||
IsFirstData = true;
|
||||
|
||||
if(rec_sti_command & ENABLE_REC){
|
||||
rec_sti_command |= STATUS_REC; // neu is recording now
|
||||
}
|
||||
|
||||
// change LED base on working status
|
||||
headstage_led_control();
|
||||
|
||||
AppendSPITX(0, 0);
|
||||
SPICallBack = READ_MOSI;
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
return;
|
||||
}
|
||||
|
||||
if(rec_sti_command & STATUS_REC){
|
||||
if(!(rec_sti_command & ENABLE_REC)){
|
||||
// terminate record
|
||||
rec_sti_command &= ~STATUS_REC;
|
||||
headstage_led_control();
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
else{
|
||||
if(SPICallBack != READ_MOSI){
|
||||
SPICallBack = READ_MOSI;
|
||||
}
|
||||
|
||||
headstage_neu_append_notify_data();
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if(rec_sti_command & STATUS_STI){
|
||||
stimulation_handle();
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
#define RESEND_SPI_READ_NUMBER 3
|
||||
static uint8_t check_register_value(DBSRegister *dbs_register, uint8_t reg_size, uint16_t *value_to_fit){
|
||||
for(int i=0 ; i<reg_size ; i++){
|
||||
if(dbs_register[i].CheckRegister){
|
||||
if(check_reg_counter < RESEND_SPI_READ_NUMBER){
|
||||
dbs_register[i].read_reg(dbs_register+i);
|
||||
}
|
||||
else{
|
||||
// check register value
|
||||
check_reg_counter = 0;
|
||||
dbs_register[i].CheckRegister = false;
|
||||
|
||||
uint16_t ins_to_fit = value_to_fit[i];
|
||||
uint16_t ins_recv = spi_rxbuf[1] << 8 | spi_rxbuf[2];
|
||||
|
||||
if(ins_recv != ins_to_fit){
|
||||
SPI_close(headstage_spi_handle);
|
||||
dbs_register[i].WriteRegister = true;
|
||||
ReopenSPI();
|
||||
dbs_register[i].write_reg(dbs_register+i, value_to_fit[i]);
|
||||
}
|
||||
else{
|
||||
AppendSPITX(0, 0);
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint8_t write_register(DBSRegister *dbs_register, uint8_t reg_size, uint16_t *value_to_write){
|
||||
|
||||
// start from index 1, since 0 is rec/sti enable
|
||||
for(int i=1 ; i<reg_size ; i++){
|
||||
if(dbs_register[i].WriteRegister){
|
||||
dbs_register[i].WriteRegister = false;
|
||||
dbs_register[i].CheckRegister = true;
|
||||
dbs_register[i].write_reg(dbs_register+i, value_to_write[i]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void recording_handle(){
|
||||
if(!(rec_sti_command & ENABLE_REC)){
|
||||
// terminate record
|
||||
rec_sti_command &= ~STATUS_REC;
|
||||
headstage_led_control();
|
||||
|
||||
if(rec_sti_command & STATUS_STI){
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
else{
|
||||
AppendSPITX(0, 0);
|
||||
ResetINSTRUCTION();
|
||||
|
||||
SPI_close(headstage_spi_handle);
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++ ){
|
||||
spi_txbuf[i] = 0;
|
||||
spi_rxbuf[i] = 0;
|
||||
}
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
ReopenSPI();
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
else{
|
||||
headstage_neu_append_notify_data();
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
static void stimulation_handle(){
|
||||
if(!(rec_sti_command & ENABLE_STI)){
|
||||
rec_sti_command &= ~STATUS_STI;
|
||||
headstage_led_control();
|
||||
sti_register[STI_ENABLE_INDEX].WriteRegister = false;
|
||||
sti_register[STI_ENABLE_INDEX].CheckRegister = true;
|
||||
sti_register_value[STI_ENABLE_INDEX] = 0;
|
||||
sti_register[STI_ENABLE_INDEX].write_reg(sti_register+STI_ENABLE_INDEX, sti_register_value[STI_ENABLE_INDEX]);
|
||||
}
|
||||
|
||||
// nothing to do
|
||||
else{
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
+6
-6
@@ -3,15 +3,15 @@
|
||||
#define VERSION_DATE
|
||||
|
||||
#define VERSION_DATE_YEAR 20
|
||||
#define VERSION_DATE_MONTH 7
|
||||
#define VERSION_DATE_DAY 9
|
||||
#define VERSION_DATE_HOUR 17
|
||||
#define VERSION_DATE_MINUTE 7
|
||||
#define VERSION_DATE_MONTH 11
|
||||
#define VERSION_DATE_DAY 13
|
||||
#define VERSION_DATE_HOUR 18
|
||||
#define VERSION_DATE_MINUTE 30
|
||||
|
||||
// this is NOT the version hash !!
|
||||
// it's the last version hash
|
||||
#define VERSION_HASH b19b8189278e6ef6b9d9db3b7bc8f6f9df565f05
|
||||
#define VERSION_GIT_BRANCH Neulive2.0_developement
|
||||
#define VERSION_HASH 1cde4cfe026202aae24460eb1cf778477a9828e3
|
||||
#define VERSION_GIT_BRANCH neulive_onchange_central_debug
|
||||
|
||||
static void get_board_name(char *board_name_ch, uint8 *board_name_int, uint8 name_size){
|
||||
uint8 name_offset = 18;
|
||||
|
||||
+50
-3
@@ -8,11 +8,60 @@
|
||||
#error "headstage/headstage_notify.h not included"
|
||||
#endif
|
||||
|
||||
#include "headstage_dbs_object.h"
|
||||
|
||||
#define NOT_BUF_OFFSET_INIT 8
|
||||
|
||||
static uint8_t not_buf_offset = NOT_BUF_OFFSET_INIT;
|
||||
static uint32_t not_time_stamp = 0;
|
||||
|
||||
static void headstage_notify_set_timestamp();
|
||||
static void headstage_notify_flip_buffer();
|
||||
static uint8_t headstage_notify_append_data(uint8_t *data_value);
|
||||
|
||||
/**
|
||||
* @fn headstage_neu_append_notify_data
|
||||
*/
|
||||
#define CHANNEL_VALID (INSTRUCTION.recording_channel & (0x0001 << channel))
|
||||
static void headstage_neu_append_notify_data() {
|
||||
|
||||
uint8_t channel = spi_rxbuf[0];
|
||||
|
||||
// close-reopen SPI, if the first channel received is invalid
|
||||
if(IsFirstData){
|
||||
// start record
|
||||
if((INSTRUCTION.recording_channel & (0x0001 << channel)) && (channel < 16)){
|
||||
IsFirstData = false;
|
||||
}
|
||||
// restart SPI
|
||||
else{
|
||||
SPI_close(headstage_spi_handle);
|
||||
ReopenSPI();
|
||||
IsFirstData = true;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// discard illegal channel
|
||||
uint16_t valid_channel = INSTRUCTION.recording_channel & (0x0001 << channel);
|
||||
if(!(INSTRUCTION.recording_channel & (0x0001 << channel)) || (channel > 15)){
|
||||
// illegal channel
|
||||
return;
|
||||
}
|
||||
|
||||
uint8_t not_buf[2];
|
||||
not_buf[0] = (channel & 0x0F) << 4 | (spi_rxbuf[1] & 0x0F);
|
||||
not_buf[1] = spi_rxbuf[2];
|
||||
|
||||
uint8_t data_size = headstage_notify_append_data(not_buf);
|
||||
|
||||
if (data_size >= BLE_NOT_BUFF_SIZE) {
|
||||
headstage_notify_flip_buffer();
|
||||
headstage_notify_send();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void headstage_notify_set_timestamp() {
|
||||
not_time_stamp = headstage_time_stamp_us();
|
||||
|
||||
@@ -23,7 +72,7 @@ static void headstage_notify_set_timestamp() {
|
||||
}
|
||||
|
||||
static void headstage_notify_flip_buffer() {
|
||||
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 3;
|
||||
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 2;
|
||||
|
||||
headstage_notify_buffer[0] = CHIP_ID;
|
||||
headstage_notify_buffer[1] = data_count;
|
||||
@@ -40,11 +89,9 @@ static uint8_t headstage_notify_append_data(uint8_t *data_value) {
|
||||
if (data_value == NULL) {
|
||||
headstage_notify_buffer[not_buf_offset++] = 0x00;
|
||||
headstage_notify_buffer[not_buf_offset++] = 0x00;
|
||||
headstage_notify_buffer[not_buf_offset++] = 0x00;
|
||||
} else {
|
||||
headstage_notify_buffer[not_buf_offset++] = data_value[0];
|
||||
headstage_notify_buffer[not_buf_offset++] = data_value[1];
|
||||
headstage_notify_buffer[not_buf_offset++] = data_value[2];
|
||||
}
|
||||
|
||||
if (not_buf_offset >= BLE_NOT_BUFF_SIZE - 1) {
|
||||
|
||||
+2
-2
@@ -25,7 +25,7 @@ static void MCUReset(){
|
||||
spi_txbuf[i] = 0;
|
||||
spi_rxbuf[i] = 0;
|
||||
}
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
ReopenSPI();
|
||||
|
||||
for(int i=0 ; i<SPI_LED_BUFF_SIZE ; i++){
|
||||
@@ -33,7 +33,7 @@ static void MCUReset(){
|
||||
}
|
||||
|
||||
// CIS buffer reset
|
||||
for(int i=0 ; i<BLE_CDR_SAMLL_SIZE ; i++){
|
||||
for(int i=0 ; i<BLE_CDR_SMALL_SIZE ; i++){
|
||||
cdr_buf[i] = 0;
|
||||
}
|
||||
|
||||
|
||||
+68
@@ -120,4 +120,72 @@ static void AppendSPITX(uint8_t index, uint32_t value){
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn headstage_spi_callback
|
||||
*
|
||||
* description: callback function to deal with data transmission between DBS and CC2650
|
||||
*/
|
||||
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction) {
|
||||
switch(SPICallBack){
|
||||
case CONTINUOUS_TRANS:{
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER:{
|
||||
SPICallBack = FLUSH_BUFFER2;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER2:{
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
// headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case CONTI_SPI_WITH_FLUSH:{
|
||||
SPICallBack = FLUSH_BUFFER;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_MOSI:{
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_REG:{
|
||||
check_reg_counter ++;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case CLOSE_SPI:{
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
SPI_close(headstage_spi_handle);
|
||||
break;
|
||||
}
|
||||
|
||||
case END_TRANSMIT:{
|
||||
tx_put_u24(0, 0);
|
||||
SPICallBack = CONTINUOUS_TRANS;
|
||||
break;
|
||||
}
|
||||
default:{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
+1
@@ -561,6 +561,7 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
|
||||
headstage_init_device_info();
|
||||
|
||||
headstage_init();
|
||||
InitDBSRegister();
|
||||
|
||||
for (;;) {
|
||||
// Waits for a signal to the semaphore associated with the calling thread.
|
||||
|
||||
@@ -82,7 +82,8 @@ extern "C" {
|
||||
|
||||
// Length of Characteristic 5 in bytes
|
||||
#define SIMPLEPROFILE_CHAR1_LEN 2
|
||||
#define SIMPLEPROFILE_CHAR2_LEN 50
|
||||
//#define SIMPLEPROFILE_CHAR2_LEN 50
|
||||
#define SIMPLEPROFILE_CHAR2_LEN 34
|
||||
#define SIMPLEPROFILE_CHAR3_LEN 20
|
||||
#define SIMPLEPROFILE_CHAR4_LEN 200
|
||||
//#define SIMPLEPROFILE_CHAR4_LEN 20
|
||||
|
||||
Reference in New Issue
Block a user