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Author SHA1 Message Date
weiting2 acd0080929 sti_clk ratio should be system register 2020-11-13 18:30:41 +08:00
7 changed files with 46 additions and 43 deletions
@@ -103,7 +103,7 @@ typedef enum {
READ_REG, // read DBS register value, used after a "read" SPI instruction (MISO)
READ_REG2, // read DBS register value, used after a "read" SPI instruction (MISO)
END_TRANSMIT, // read DBS register value, used after a "read" SPI instruction (MISO)
ONE_SHOT_SPI, // end spi instruction
CONTI_SPI_WITH_FLUSH, // end spi instruction
READ_MOSI
} SPI_CB_MODE;
@@ -27,7 +27,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
check_reg_counter = 0;
if(check_ins(instruction_to_fit)){
NEULIVE_STATE.state = next_state;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
// update rec_sti_command
if(!(rec_sti_command & ENABLE_STI)){
@@ -70,7 +70,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
IsFirstData = true;
}
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
ReopenSPI();
}
headstage_spi_transaction(3);
@@ -167,7 +167,7 @@ static void check_sti_t1_t5(NEU_WORK_STATE next_state){
else{
NEULIVE_STATE.state = next_state;
}
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
headstage_spi_transaction(3);
}
@@ -8,6 +8,7 @@
#define SYS_GENERAL_ENABLE_INDEX 1
#define SYS_LNA_BIOS1_INDEX 2
#define SYS_LNA_BIOS2_INDEX 3
#define SYS_STI_CLK_RATIO_INDEX 4
#define REC_CHANNEL_INDEX 0
#define REC_GAIN_INDEX 1
@@ -45,7 +46,7 @@ void write_reg(DBSRegister *self, uint16_t reg_value){
spi_txbuf[0] = 0x80 | self->address;
spi_txbuf[1] = (reg_value >> 8) & 0xFF ;
spi_txbuf[2] = reg_value & 0xFF;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
headstage_spi_transaction(SPI_BUFFER_SIZE);
}
@@ -58,16 +59,17 @@ void read_reg(DBSRegister *self){
}
static uint16_t sys_register_default_value[4] = {
static uint16_t sys_register_default_value[5] = {
0x0000,
0x40F2,
0x0210,
0x4210
0x4210,
0x0002
};
static uint16_t rec_register_value[3];
static uint16_t sti_register_value[43];
static DBSRegister sys_register[4];
static DBSRegister sys_register[5];
static DBSRegister rec_register[3];
static DBSRegister sti_register[43];
@@ -76,6 +78,7 @@ static void InitSysRegister(){
sys_register[SYS_GENERAL_ENABLE_INDEX].address = 47; // general enable
sys_register[SYS_LNA_BIOS1_INDEX].address = 57;
sys_register[SYS_LNA_BIOS2_INDEX].address = 58;
sys_register[SYS_STI_CLK_RATIO_INDEX].address = 52;
for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
sys_register[i].WriteRegister = false;
@@ -132,7 +135,7 @@ static void InitDBSRegister(){
InitStiRegister();
// for(int i=1 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
for(int i=1 ; i<4 ; i++){
for(int i=1 ; i<5 ; i++){
sys_register[i].WriteRegister = true;
}
flag_notify(EVT_NEU_SPI);
@@ -644,7 +644,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
FlushNotify();
}
NEULIVE_STATE.state = NEU_RST;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
flag_notify(EVT_NEU_SPI);
/**< stop spi transaction */
break; /**< reset all the parameter */
@@ -726,7 +726,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
}
NEULIVE_STATE.config_type = NEU_WARM_UP;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
// is neu wording now?
if( (rec_sti_command & STATUS_STI) || (rec_sti_command & STATUS_REC) ){
@@ -745,7 +745,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
INSTRUCTION.ins_opcode = BIAS_ONE;
NEULIVE_STATE.config_type = NEU_WARM_UP;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
// is neu wording now?
if( (rec_sti_command & STATUS_STI) || (rec_sti_command & STATUS_REC) ){
@@ -763,7 +763,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
rec_sti_command |= ENABLE_STI;
NEULIVE_STATE.state = NEU_WRITE_STI_INS;
NEULIVE_STATE.config_type = NEU_WARM_UP;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
INSTRUCTION.ins_opcode = T_ZE;
// is neu wording now?
@@ -810,7 +810,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
rec_sti_command &= ~ENABLE_REC;
rec_sti_command &= ~ENABLE_STI;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
NEULIVE_STATE.state = NEU_IDLE;
STI = false;
Neu2Reset();
@@ -973,7 +973,7 @@ static void headstage_neu_state_spi() {
/* recording */
case NEU_WRITE_REC_INS: {
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
nxt_ins = build_rec_ins(NEULIVE_STATE.config_type, &value); /**< set instruction one by one in order to set all the parameter.*/
NEULIVE_STATE.config_type = nxt_ins;
@@ -1027,7 +1027,7 @@ static void headstage_neu_state_spi() {
value = (0x01 << 23) | (0x33 << 16) | INSTRUCTION.adc_clock_ratio;
AppendSPITX(0, value);
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
NEULIVE_STATE.state = NEU_CHECK_SAMPLE_RATE;
headstage_spi_transaction(3);
break;
@@ -1041,7 +1041,7 @@ static void headstage_neu_state_spi() {
case NEU_PREPARE_READ:{
if(spi_state_counter < 6){
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
NEULIVE_STATE.state = NEU_PREPARE_READ;
spi_state_counter ++;
AppendSPITX(0, 0);
@@ -1072,7 +1072,7 @@ static void headstage_neu_state_spi() {
// go to send sti instruction
NEULIVE_STATE.state = NEU_WRITE_STI_INS;
NEULIVE_STATE.config_type = NEU_WARM_UP;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
INSTRUCTION.ins_opcode = T_ZE;
AppendSPITX(0, 0);
@@ -1082,7 +1082,7 @@ static void headstage_neu_state_spi() {
// disable stimulation
else if( !(rec_sti_command & ENABLE_STI) && (rec_sti_command & STATUS_STI) ){
NEULIVE_STATE.state = NEU_STI_INT;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
AppendSPITX(0, 0);
headstage_spi_transaction(SPI_BUFFER_SIZE);
@@ -1095,7 +1095,7 @@ static void headstage_neu_state_spi() {
if(rec_sti_command & STATUS_STI){
NEULIVE_STATE.state = NEU_STI;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
AppendSPITX(0, 0);
headstage_spi_transaction(SPI_BUFFER_SIZE);
@@ -1111,7 +1111,7 @@ static void headstage_neu_state_spi() {
spi_txbuf[i] = 0;
spi_rxbuf[i] = 0;
}
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
ReopenSPI();
headstage_spi_transaction(SPI_BUFFER_SIZE);
}
@@ -1129,7 +1129,7 @@ static void headstage_neu_state_spi() {
/* stimulation */
case NEU_WRITE_STI_INS:{
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
nxt_ins = build_sti_ins(NEULIVE_STATE.config_type, &value); /**< set instruction one by one in order to set all the parameter.*/
NEULIVE_STATE.config_type = nxt_ins;
@@ -1181,7 +1181,7 @@ static void headstage_neu_state_spi() {
value = (0x01 << 23) | (0x2E << 16) | INSTRUCTION.sti_channel;
AppendSPITX(0, value);
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
NEULIVE_STATE.state = NEU_STI_LED;
headstage_spi_transaction(3);
break;
@@ -1192,7 +1192,7 @@ static void headstage_neu_state_spi() {
// value = (0x01 << 23) | (0x2E << 16) | INSTRUCTION.sti_channel;
// AppendSPITX(0, value);
//
// SPICallBack = ONE_SHOT_SPI;
// SPICallBack = CONTI_SPI_WITH_FLUSH;
// NEULIVE_STATE.state = NEU_CHECK_STI_CH;
// headstage_spi_transaction(3);
// break;
@@ -1209,7 +1209,7 @@ static void headstage_neu_state_spi() {
headstage_led_control();
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
AppendSPITX(0, 0);
headstage_spi_transaction(SPI_BUFFER_SIZE);
break;
@@ -1220,7 +1220,7 @@ static void headstage_neu_state_spi() {
// recv disable sti command
if(!(rec_sti_command & ENABLE_STI)){
NEULIVE_STATE.state = NEU_STI_INT;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
AppendSPITX(0, 0);
headstage_spi_transaction(SPI_BUFFER_SIZE);
@@ -1230,7 +1230,7 @@ static void headstage_neu_state_spi() {
else if(rec_sti_command & ENABLE_REC){
NEULIVE_STATE.state = NEU_WRITE_REC_INS;
NEULIVE_STATE.config_type = NEU_WARM_UP;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
INSTRUCTION.ins_opcode = BIAS_ONE;
AppendSPITX(0, 0);
@@ -1250,7 +1250,7 @@ static void headstage_neu_state_spi() {
// terminate stimulation
case NEU_STI_INT: {
NEULIVE_STATE.state = NEU_STI_INT_TWICE;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
value = (0x01 << 23) | (0x2E << 16) | 0;
AppendSPITX(0, value);
@@ -1260,7 +1260,7 @@ static void headstage_neu_state_spi() {
case NEU_STI_INT_TWICE: {
NEULIVE_STATE.state = NEU_CHECK_STI_INT;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
value = (0x01 << 23) | (0x2E << 16) | 0;
AppendSPITX(0, value);
@@ -1281,7 +1281,7 @@ static void headstage_neu_state_spi() {
case NEU_LED:{
NEULIVE_STATE.state = NEU_IDLE;
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
AppendSPITX(0, 0);
headstage_led_control();
@@ -1446,7 +1446,7 @@ static uint8_t check_register_value(DBSRegister *dbs_register, uint8_t reg_size,
}
else{
AppendSPITX(0, 0);
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
headstage_spi_transaction(SPI_BUFFER_SIZE);
}
}
@@ -1477,7 +1477,7 @@ static void recording_handle(){
headstage_led_control();
if(rec_sti_command & STATUS_STI){
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
AppendSPITX(0, 0);
headstage_spi_transaction(SPI_BUFFER_SIZE);
}
@@ -1490,7 +1490,7 @@ static void recording_handle(){
spi_txbuf[i] = 0;
spi_rxbuf[i] = 0;
}
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
ReopenSPI();
headstage_spi_transaction(SPI_BUFFER_SIZE);
}
@@ -3,15 +3,15 @@
#define VERSION_DATE
#define VERSION_DATE_YEAR 20
#define VERSION_DATE_MONTH 10
#define VERSION_DATE_DAY 26
#define VERSION_DATE_HOUR 17
#define VERSION_DATE_MINUTE 3
#define VERSION_DATE_MONTH 11
#define VERSION_DATE_DAY 13
#define VERSION_DATE_HOUR 18
#define VERSION_DATE_MINUTE 30
// this is NOT the version hash !!
// it's the last version hash
#define VERSION_HASH 764bd9364d7a99761ada31d35af557a39e1d65a4
#define VERSION_GIT_BRANCH neulive20_development_onchange_central
#define VERSION_HASH 1cde4cfe026202aae24460eb1cf778477a9828e3
#define VERSION_GIT_BRANCH neulive_onchange_central_debug
static void get_board_name(char *board_name_ch, uint8 *board_name_int, uint8 name_size){
uint8 name_offset = 18;
@@ -25,7 +25,7 @@ static void MCUReset(){
spi_txbuf[i] = 0;
spi_rxbuf[i] = 0;
}
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
ReopenSPI();
for(int i=0 ; i<SPI_LED_BUFF_SIZE ; i++){
@@ -143,7 +143,7 @@ static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transacti
break;
}
case FLUSH_BUFFER2:{
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
}
@@ -151,7 +151,7 @@ static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transacti
// headstage_spi_transaction(SPI_BUFFER_SIZE);
break;
}
case ONE_SHOT_SPI:{
case CONTI_SPI_WITH_FLUSH:{
SPICallBack = FLUSH_BUFFER;
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
@@ -172,7 +172,7 @@ static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transacti
}
case CLOSE_SPI:{
SPICallBack = ONE_SHOT_SPI;
SPICallBack = CONTI_SPI_WITH_FLUSH;
SPI_close(headstage_spi_handle);
break;
}