Compare commits
1 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
| acd0080929 |
+1
-1
@@ -103,7 +103,7 @@ typedef enum {
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READ_REG, // read DBS register value, used after a "read" SPI instruction (MISO)
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READ_REG2, // read DBS register value, used after a "read" SPI instruction (MISO)
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END_TRANSMIT, // read DBS register value, used after a "read" SPI instruction (MISO)
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ONE_SHOT_SPI, // end spi instruction
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CONTI_SPI_WITH_FLUSH, // end spi instruction
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READ_MOSI
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} SPI_CB_MODE;
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+3
-3
@@ -27,7 +27,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
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check_reg_counter = 0;
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if(check_ins(instruction_to_fit)){
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NEULIVE_STATE.state = next_state;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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// update rec_sti_command
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if(!(rec_sti_command & ENABLE_STI)){
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@@ -70,7 +70,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
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IsFirstData = true;
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}
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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ReopenSPI();
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}
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headstage_spi_transaction(3);
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@@ -167,7 +167,7 @@ static void check_sti_t1_t5(NEU_WORK_STATE next_state){
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else{
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NEULIVE_STATE.state = next_state;
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}
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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headstage_spi_transaction(3);
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}
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+8
-5
@@ -8,6 +8,7 @@
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#define SYS_GENERAL_ENABLE_INDEX 1
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#define SYS_LNA_BIOS1_INDEX 2
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#define SYS_LNA_BIOS2_INDEX 3
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#define SYS_STI_CLK_RATIO_INDEX 4
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#define REC_CHANNEL_INDEX 0
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#define REC_GAIN_INDEX 1
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@@ -45,7 +46,7 @@ void write_reg(DBSRegister *self, uint16_t reg_value){
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spi_txbuf[0] = 0x80 | self->address;
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spi_txbuf[1] = (reg_value >> 8) & 0xFF ;
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spi_txbuf[2] = reg_value & 0xFF;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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@@ -58,16 +59,17 @@ void read_reg(DBSRegister *self){
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}
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static uint16_t sys_register_default_value[4] = {
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static uint16_t sys_register_default_value[5] = {
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0x0000,
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0x40F2,
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0x0210,
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0x4210
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0x4210,
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0x0002
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};
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static uint16_t rec_register_value[3];
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static uint16_t sti_register_value[43];
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static DBSRegister sys_register[4];
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static DBSRegister sys_register[5];
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static DBSRegister rec_register[3];
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static DBSRegister sti_register[43];
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@@ -76,6 +78,7 @@ static void InitSysRegister(){
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sys_register[SYS_GENERAL_ENABLE_INDEX].address = 47; // general enable
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sys_register[SYS_LNA_BIOS1_INDEX].address = 57;
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sys_register[SYS_LNA_BIOS2_INDEX].address = 58;
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sys_register[SYS_STI_CLK_RATIO_INDEX].address = 52;
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for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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sys_register[i].WriteRegister = false;
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@@ -132,7 +135,7 @@ static void InitDBSRegister(){
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InitStiRegister();
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// for(int i=1 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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for(int i=1 ; i<4 ; i++){
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for(int i=1 ; i<5 ; i++){
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sys_register[i].WriteRegister = true;
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}
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flag_notify(EVT_NEU_SPI);
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+24
-24
@@ -644,7 +644,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
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FlushNotify();
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}
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NEULIVE_STATE.state = NEU_RST;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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flag_notify(EVT_NEU_SPI);
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/**< stop spi transaction */
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break; /**< reset all the parameter */
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@@ -726,7 +726,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
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}
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NEULIVE_STATE.config_type = NEU_WARM_UP;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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// is neu wording now?
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if( (rec_sti_command & STATUS_STI) || (rec_sti_command & STATUS_REC) ){
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@@ -745,7 +745,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
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INSTRUCTION.ins_opcode = BIAS_ONE;
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NEULIVE_STATE.config_type = NEU_WARM_UP;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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// is neu wording now?
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if( (rec_sti_command & STATUS_STI) || (rec_sti_command & STATUS_REC) ){
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@@ -763,7 +763,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
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rec_sti_command |= ENABLE_STI;
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NEULIVE_STATE.state = NEU_WRITE_STI_INS;
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NEULIVE_STATE.config_type = NEU_WARM_UP;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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INSTRUCTION.ins_opcode = T_ZE;
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// is neu wording now?
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@@ -810,7 +810,7 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
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rec_sti_command &= ~ENABLE_REC;
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rec_sti_command &= ~ENABLE_STI;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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NEULIVE_STATE.state = NEU_IDLE;
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STI = false;
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Neu2Reset();
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@@ -973,7 +973,7 @@ static void headstage_neu_state_spi() {
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/* recording */
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case NEU_WRITE_REC_INS: {
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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nxt_ins = build_rec_ins(NEULIVE_STATE.config_type, &value); /**< set instruction one by one in order to set all the parameter.*/
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NEULIVE_STATE.config_type = nxt_ins;
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@@ -1027,7 +1027,7 @@ static void headstage_neu_state_spi() {
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value = (0x01 << 23) | (0x33 << 16) | INSTRUCTION.adc_clock_ratio;
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AppendSPITX(0, value);
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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NEULIVE_STATE.state = NEU_CHECK_SAMPLE_RATE;
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headstage_spi_transaction(3);
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break;
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@@ -1041,7 +1041,7 @@ static void headstage_neu_state_spi() {
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case NEU_PREPARE_READ:{
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if(spi_state_counter < 6){
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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NEULIVE_STATE.state = NEU_PREPARE_READ;
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spi_state_counter ++;
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AppendSPITX(0, 0);
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@@ -1072,7 +1072,7 @@ static void headstage_neu_state_spi() {
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// go to send sti instruction
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NEULIVE_STATE.state = NEU_WRITE_STI_INS;
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NEULIVE_STATE.config_type = NEU_WARM_UP;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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INSTRUCTION.ins_opcode = T_ZE;
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AppendSPITX(0, 0);
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@@ -1082,7 +1082,7 @@ static void headstage_neu_state_spi() {
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// disable stimulation
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else if( !(rec_sti_command & ENABLE_STI) && (rec_sti_command & STATUS_STI) ){
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NEULIVE_STATE.state = NEU_STI_INT;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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AppendSPITX(0, 0);
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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@@ -1095,7 +1095,7 @@ static void headstage_neu_state_spi() {
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if(rec_sti_command & STATUS_STI){
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NEULIVE_STATE.state = NEU_STI;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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AppendSPITX(0, 0);
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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@@ -1111,7 +1111,7 @@ static void headstage_neu_state_spi() {
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spi_txbuf[i] = 0;
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spi_rxbuf[i] = 0;
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}
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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ReopenSPI();
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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@@ -1129,7 +1129,7 @@ static void headstage_neu_state_spi() {
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/* stimulation */
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case NEU_WRITE_STI_INS:{
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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nxt_ins = build_sti_ins(NEULIVE_STATE.config_type, &value); /**< set instruction one by one in order to set all the parameter.*/
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NEULIVE_STATE.config_type = nxt_ins;
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@@ -1181,7 +1181,7 @@ static void headstage_neu_state_spi() {
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value = (0x01 << 23) | (0x2E << 16) | INSTRUCTION.sti_channel;
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AppendSPITX(0, value);
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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NEULIVE_STATE.state = NEU_STI_LED;
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headstage_spi_transaction(3);
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break;
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@@ -1192,7 +1192,7 @@ static void headstage_neu_state_spi() {
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// value = (0x01 << 23) | (0x2E << 16) | INSTRUCTION.sti_channel;
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// AppendSPITX(0, value);
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//
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// SPICallBack = ONE_SHOT_SPI;
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// SPICallBack = CONTI_SPI_WITH_FLUSH;
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// NEULIVE_STATE.state = NEU_CHECK_STI_CH;
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// headstage_spi_transaction(3);
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// break;
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@@ -1209,7 +1209,7 @@ static void headstage_neu_state_spi() {
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headstage_led_control();
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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AppendSPITX(0, 0);
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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break;
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@@ -1220,7 +1220,7 @@ static void headstage_neu_state_spi() {
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// recv disable sti command
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if(!(rec_sti_command & ENABLE_STI)){
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NEULIVE_STATE.state = NEU_STI_INT;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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AppendSPITX(0, 0);
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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@@ -1230,7 +1230,7 @@ static void headstage_neu_state_spi() {
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else if(rec_sti_command & ENABLE_REC){
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NEULIVE_STATE.state = NEU_WRITE_REC_INS;
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NEULIVE_STATE.config_type = NEU_WARM_UP;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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INSTRUCTION.ins_opcode = BIAS_ONE;
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AppendSPITX(0, 0);
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@@ -1250,7 +1250,7 @@ static void headstage_neu_state_spi() {
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// terminate stimulation
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case NEU_STI_INT: {
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NEULIVE_STATE.state = NEU_STI_INT_TWICE;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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value = (0x01 << 23) | (0x2E << 16) | 0;
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AppendSPITX(0, value);
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@@ -1260,7 +1260,7 @@ static void headstage_neu_state_spi() {
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case NEU_STI_INT_TWICE: {
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NEULIVE_STATE.state = NEU_CHECK_STI_INT;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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value = (0x01 << 23) | (0x2E << 16) | 0;
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AppendSPITX(0, value);
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@@ -1281,7 +1281,7 @@ static void headstage_neu_state_spi() {
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case NEU_LED:{
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NEULIVE_STATE.state = NEU_IDLE;
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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AppendSPITX(0, 0);
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headstage_led_control();
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@@ -1446,7 +1446,7 @@ static uint8_t check_register_value(DBSRegister *dbs_register, uint8_t reg_size,
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}
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else{
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AppendSPITX(0, 0);
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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}
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@@ -1477,7 +1477,7 @@ static void recording_handle(){
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headstage_led_control();
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if(rec_sti_command & STATUS_STI){
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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AppendSPITX(0, 0);
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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@@ -1490,7 +1490,7 @@ static void recording_handle(){
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spi_txbuf[i] = 0;
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spi_rxbuf[i] = 0;
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}
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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ReopenSPI();
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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+6
-6
@@ -3,15 +3,15 @@
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#define VERSION_DATE
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#define VERSION_DATE_YEAR 20
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#define VERSION_DATE_MONTH 10
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#define VERSION_DATE_DAY 26
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#define VERSION_DATE_HOUR 17
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#define VERSION_DATE_MINUTE 3
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#define VERSION_DATE_MONTH 11
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#define VERSION_DATE_DAY 13
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#define VERSION_DATE_HOUR 18
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#define VERSION_DATE_MINUTE 30
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// this is NOT the version hash !!
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// it's the last version hash
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#define VERSION_HASH 764bd9364d7a99761ada31d35af557a39e1d65a4
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#define VERSION_GIT_BRANCH neulive20_development_onchange_central
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#define VERSION_HASH 1cde4cfe026202aae24460eb1cf778477a9828e3
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#define VERSION_GIT_BRANCH neulive_onchange_central_debug
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static void get_board_name(char *board_name_ch, uint8 *board_name_int, uint8 name_size){
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uint8 name_offset = 18;
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+1
-1
@@ -25,7 +25,7 @@ static void MCUReset(){
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spi_txbuf[i] = 0;
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spi_rxbuf[i] = 0;
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}
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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ReopenSPI();
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for(int i=0 ; i<SPI_LED_BUFF_SIZE ; i++){
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+3
-3
@@ -143,7 +143,7 @@ static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transacti
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break;
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}
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case FLUSH_BUFFER2:{
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
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spi_txbuf[i] = 0x00;
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}
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@@ -151,7 +151,7 @@ static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transacti
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// headstage_spi_transaction(SPI_BUFFER_SIZE);
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break;
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}
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case ONE_SHOT_SPI:{
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case CONTI_SPI_WITH_FLUSH:{
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SPICallBack = FLUSH_BUFFER;
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for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
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spi_txbuf[i] = 0x00;
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@@ -172,7 +172,7 @@ static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transacti
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}
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case CLOSE_SPI:{
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SPICallBack = ONE_SHOT_SPI;
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SPICallBack = CONTI_SPI_WITH_FLUSH;
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SPI_close(headstage_spi_handle);
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break;
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}
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