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48 Commits

Author SHA1 Message Date
hchen3 657b1b2b0e add HCI 2020-02-04 16:48:33 +08:00
yichin aa410bec37 debug channel swap 2019-10-07 21:56:14 +08:00
yichin 3ac4620c7d debug channel swap 2019-10-04 18:20:41 +08:00
yichin 5283d905b7 debug channel swap 2019-10-04 16:11:23 +08:00
yichin f1b30c3ba7 channel length extension done 2019-10-03 19:01:26 +08:00
yichin 37d16a41b7 channel length extension don 2019-10-03 15:22:35 +08:00
yichin 4d5704d99e temporary modification 2019-10-01 12:18:10 +08:00
yichin 95f667e3b0 neulive 1.3 parameter done 2019-09-30 11:16:33 +08:00
yichin 1d33c05ca3 debug neulive1.3 2019-09-27 13:39:35 +08:00
yichin 5b4e14ec73 pass 2019-09-25 23:32:36 +08:00
yichin fb5cbe212e pass 2019-09-25 14:40:25 +08:00
yichin f675ff0b66 debug done 2019-09-24 16:15:00 +08:00
yichin 83ad8302c1 neulive1.3 with bug 2019-09-24 15:31:22 +08:00
yichin 955c3a2e7c json parameter table renew and modification 2019-09-23 20:12:21 +08:00
yichin 664b6e56b9 framework modified 2019-09-20 19:20:13 +08:00
yichin f94e4375f3 neulive 2.0 structure modify 2019-09-19 20:49:25 +08:00
yichin 1cf1c01163 for neulive 2.0 test 2019-09-18 21:03:52 +08:00
yichin 0cd2fe0528 neulive2.0 modified 2019-09-17 20:34:09 +08:00
yichin fb34754e1f debug neulive 2.0 2019-09-17 15:29:17 +08:00
yichin 20d5804a87 neulive2.0 debug 2019-09-17 11:22:50 +08:00
yichin 5851dc9707 some bugs with system clock 2019-09-10 20:38:55 +08:00
yichin 7cc337c0fd begin to debug 2019-09-10 10:05:30 +08:00
yichin 09685951c3 check sti firmware done 2019-09-09 20:52:20 +08:00
yichin 720f6d3548 add device information 2019-09-09 16:36:30 +08:00
yichin 1393d568a0 build pass 2019-09-09 15:54:37 +08:00
YiChin2018 92b6a3a4f2 add build instruction 2019-09-06 22:09:15 +08:00
YiChin2018 becdca9dc7 add build instruction 2019-09-06 18:26:05 +08:00
YiChin2018 dc3cce9990 add build instruction 2019-09-05 20:25:48 +08:00
YiChin2018 f8d7296f76 develop 2.0 firmware 2019-09-04 21:57:53 +08:00
YiChin2018 615eba69bd develop 2.0 firmware 2019-09-04 11:18:09 +08:00
YiChin2018 aab6d49812 develop 2.0 firmware 2019-09-01 10:57:36 +08:00
YiChin2018 9bfef795e7 develop 2.0 firmware 2019-08-30 18:32:08 +08:00
YiChin2018 428808715a develop 2.0 firmware 2019-08-30 17:51:10 +08:00
YiChin2018 7dfc856318 develop 2.0 firmware 2019-08-30 11:12:10 +08:00
YiChin2018 c87fb49656 temporary version of neulive 1.2 / 1.3
porting to neulive 2.0
2019-08-29 18:00:31 +08:00
YiChin2018 df21b2021a temporary version of neulive 1.2 / 1.3
porting to neulive 2.0
2019-08-29 17:53:06 +08:00
YiChin2018 6cb386e578 temporary version of neulive 1.2 / 1.3
porting to neulive 2.0
2019-08-29 17:02:33 +08:00
YiChin2018 bd7c73f2a5 add software interrupt and documentations 2019-08-29 09:27:13 +08:00
YiChin2018 ea21075a1d add software interrupt and documentations 2019-08-28 20:08:57 +08:00
YiChin2018 71a5d93a21 add software interrupt and documentations 2019-08-28 19:57:18 +08:00
YiChin2018 c461f71cf2 add software interrupt 2019-08-27 18:14:27 +08:00
YiChin2018 9ce8ea1400 prepare to add hwi to implement our system 2019-08-26 11:54:41 +08:00
YiChin2018 b181d9273b configure file modify and add hareware interrupt 2019-08-23 19:02:27 +08:00
YiChin2018 069881f5c4 interrupt do the same thing 2019-08-23 13:43:46 +08:00
YiChin2018 ce61501d43 interrupt with bugs 2019-08-22 19:11:34 +08:00
YiChin2018 386f2940ad interrupt with bugs 2019-08-21 19:24:27 +08:00
YiChin2018 1965f6e182 there are some bugs need to be fixed 2019-08-21 10:56:20 +08:00
YiChin2018 f699ecdae9 format 2019-08-20 13:27:47 +08:00
34 changed files with 4736 additions and 358 deletions
+1
View File
@@ -3,6 +3,7 @@
# CSS package
xdctools_*/
ccsv8/
simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/app/.config/
# CSS build files
FlashROM/
+6 -6
View File
@@ -33,13 +33,13 @@ NEULIVE_PARAMETER = {
'AG': 5, # AMP GAIN
'PW': 0, # PULSE WIDTH
'TT': 9, # STIMULATION TIMES
'SB': 3, # STIMULATION BEHAVIOR
'TF': 10, # STIMULATION FREQUENCY
'SB': 2, # STIMULATION BEHAVIOR
'TF': 1, # STIMULATION FREQUENCY
'CA': 1, # AMP CHANNEL A ENABLE
'CB': 0, # AMP CHANNEL B ENABLE
'CC': 0, # AMP CHANNEL C ENABLE
'CD': 0, # AMP CHANNEL D ENABLE
'CHA': 0, # AMP CHANNEL A
'CB': 1, # AMP CHANNEL B ENABLE
'CC': 1, # AMP CHANNEL C ENABLE
'CD': 1, # AMP CHANNEL D ENABLE
'CHA': 9, # AMP CHANNEL A
'CHB': 1, # AMP CHANNEL B
'CHC': 2, # AMP CHANNEL C
'CHD': 3, # AMP CHANNEL D
@@ -335,7 +335,7 @@ def paint_fft_result(result: Result, options: Options):
plt.figure(1)
f1, pxx_den = signal.periodogram(value_seq, 1e3)
plt.semilogy(f1, pxx_den)
plt.ylim([1e-7, 1e3])
plt.ylim([1e-7, 1e7])
plt.xlabel('frequency [hz]')
plt.ylabel('PSD[v**2/Hz')
@@ -62,9 +62,9 @@
</option>
<option id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.DEFINE.986125825" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.DEFINE" valueType="definedSymbols">
<listOptionValue builtIn="false" value="CC26XX"/>
<listOptionValue builtIn="false" value="POWER_SAVING"/>
<listOptionValue builtIn="false" value="GATT_NO_CLIENT"/>
<listOptionValue builtIn="false" value="HEADSTAGE_NOTIFY_USE_ATT"/>
<listOptionValue builtIn="false" value="POWER_SAVING"/>
<listOptionValue builtIn="false" value="CC26XXWARE"/>
<listOptionValue builtIn="false" value="DATA="/>
<listOptionValue builtIn="false" value="EXT_HAL_ASSERT"/>
@@ -219,53 +219,64 @@ SPICC26XXDMA_Object spiCC26XXDMAObjects[BOOSTXL_CC2650MA_SPICOUNT];
/* SPI configuration structure, describing which pins are to be used */
const SPICC26XXDMA_HWAttrsV1 spiCC26XXDMAHWAttrs[BOOSTXL_CC2650MA_SPICOUNT] = {
//
{
.baseAddr = SSI0_BASE,
.intNum = INT_SSI0_COMB,
.intPriority = ~0,
.swiPriority = 0,
.powerMngrId = PowerCC26XX_PERIPH_SSI0,
.defaultTxBufValue = 0,
.rxChannelBitMask = 1<<UDMA_CHAN_SSI0_RX,
.txChannelBitMask = 1<<UDMA_CHAN_SSI0_TX,
.mosiPin = Board_SPI0_MOSI,
.misoPin = Board_SPI0_MISO,
.clkPin = Board_SPI0_CLK,
.csnPin = Board_SPI0_CS
//
.baseAddr = SSI0_BASE,
.intNum = INT_SSI0_COMB,
.intPriority = ~0,
.swiPriority = 0,
.powerMngrId = PowerCC26XX_PERIPH_SSI0,
.defaultTxBufValue = 0,
.rxChannelBitMask = 1 << UDMA_CHAN_SSI0_RX,
.txChannelBitMask = 1 << UDMA_CHAN_SSI0_TX,
.mosiPin = Board_SPI0_MOSI,
.misoPin = Board_SPI0_MISO,
.clkPin = Board_SPI0_CLK,
.csnPin = Board_SPI0_CSN
//
},
#ifdef HEADSTAGE_MA_USE_SPI2
{
.baseAddr = SSI1_BASE,
.intNum = INT_SSI1_COMB,
.intPriority = ~0,
.swiPriority = 0,
.powerMngrId = PowerCC26XX_PERIPH_SSI1,
.defaultTxBufValue = 0,
.rxChannelBitMask = 1<<UDMA_CHAN_SSI1_RX,
.txChannelBitMask = 1<<UDMA_CHAN_SSI1_TX,
.mosiPin = Board_SPI1_MOSI,
.misoPin = Board_SPI1_MISO,
.clkPin = Board_SPI1_CLK,
.csnPin = Board_SPI1_CS
//
.baseAddr = SSI1_BASE,
.intNum = INT_SSI1_COMB,
.intPriority = ~0,
.swiPriority = 0,
.powerMngrId = PowerCC26XX_PERIPH_SSI1,
.defaultTxBufValue = 0,
.rxChannelBitMask = 1 << UDMA_CHAN_SSI1_RX,
.txChannelBitMask = 1 << UDMA_CHAN_SSI1_TX,
.mosiPin = Board_SPI1_MOSI,
.misoPin = Board_SPI1_MISO,
.clkPin = Board_SPI1_CLK,
.csnPin = Board_SPI1_CSN //
},
#endif
};
/* SPI configuration structure */
const SPI_Config SPI_config[] = {
const SPI_Config SPI_config[] = { //
{
.fxnTablePtr = &SPICC26XXDMA_fxnTable,
.object = &spiCC26XXDMAObjects[0],
.hwAttrs = &spiCC26XXDMAHWAttrs[0]
//
.fxnTablePtr = &SPICC26XXDMA_fxnTable,
.object = &spiCC26XXDMAObjects[0],
.hwAttrs = &spiCC26XXDMAHWAttrs[0]
//
},
#ifdef HEADSTAGE_MA_USE_SPI2
{
.fxnTablePtr = &SPICC26XXDMA_fxnTable,
.object = &spiCC26XXDMAObjects[1],
.hwAttrs = &spiCC26XXDMAHWAttrs[1]
//
.fxnTablePtr = &SPICC26XXDMA_fxnTable,
.object = &spiCC26XXDMAObjects[1],
.hwAttrs = &spiCC26XXDMAHWAttrs[1]
//
},
{NULL, NULL, NULL}
};
#endif
{NULL, NULL, NULL}};
/*
* ========================== SPI DMA end =====================================
*/
*/
/*
* ========================== Crypto begin ====================================
@@ -504,21 +515,12 @@ const PWM_Config PWM_config[BOOSTXL_CC2650MA_PWMCOUNT + 1] = {
/*
* ============================= I2C Begin=====================================
*/
#ifdef ELITE_I2C
/* Generic I2C instance identifiers */
#define Board_I2C CC2650_MA_I2C0
/*!
* @def CC2650_LAUNCHXL_I2CName
* @brief Enum of I2C names on the CC2650 dev board
*/
typedef enum CC2650_MA_I2CName {
CC2650_MA_I2C0 = 0,
CC2650_MA_I2CCOUNT
} CC2650_MA_I2CName;
#ifdef HEADSTAGE_LED_USE_I2C
#define Board_I2C0_SCL0 IOID_10
#define Board_I2C0_SDA0 IOID_11
/* Place into subsections to allow the TI linker to remove items properly */
#if defined(__TI_COMPILER_VERSION__)
@@ -530,10 +532,10 @@ typedef enum CC2650_MA_I2CName {
#include <ti/drivers/i2c/I2CCC26XX.h>
/* I2C objects */
I2CCC26XX_Object i2cCC26xxObjects[CC2650_MA_I2CCOUNT];
I2CCC26XX_Object i2cCC26xxObjects[BOOSTXL_CC2650MA_I2CCOUNT];
/* I2C configuration structure, describing which pins are to be used */
const I2CCC26XX_HWAttrsV1 i2cCC26xxHWAttrs[CC2650_MA_I2CCOUNT] = {
const I2CCC26XX_HWAttrsV1 i2cCC26xxHWAttrs[BOOSTXL_CC2650MA_I2CCOUNT] = {
{
.baseAddr = I2C0_BASE,
.powerMngrId = PowerCC26XX_PERIPH_I2C0,
@@ -554,9 +556,11 @@ const I2C_Config I2C_config[] = {
},
{NULL, NULL, NULL}
};
#endif
/*
* ========================== I2C end =========================================
*/
/*
* ============================= Watchdog begin =====================================
*/
@@ -51,6 +51,11 @@ extern "C" {
#include <ti/drivers/PIN.h>
#include <driverlib/ioc.h>
#ifdef HEADSTAGE_UNI_2_0
#include "neu/headstage_pin.h"
#else
#include "uni/headstage_pin.h"
#endif
/** ============================================================================
* Externs
* ==========================================================================*/
@@ -144,36 +149,36 @@ extern const PIN_Config BoardGpioInitTable[];
#define Board_UART_TX Board_BP_UART_Rx /* RXD */
#define Board_UART_RX Board_BP_UART_Tx /* TXD */
/*
* SPI0 is LSK interface
*/
#define Board_SPI0_MISO PIN_UNASSIGNED
#define Board_SPI0_MOSI IOID_0
#define Board_SPI0_CLK IOID_1
#define Board_SPI0_CS IOID_3
/*
* SPI1 is ASK interface
*/
#define Board_SPI1_MISO PIN_UNASSIGNED
#define Board_SPI1_MOSI IOID_13
#define Board_SPI1_CLK PIN_UNASSIGNED
#define Board_SPI1_CS IOID_4
/* Power Management Board */
#define Board_SRDY Board_BP_Pin_J2_19
#define Board_MRDY Board_BP_Pin_J1_2
/* PWM outputs */
#define Board_PWMPIN0 IOID_6
#define Board_PWMPIN1 PIN_UNASSIGNED
#define Board_PWMPIN2 IOID_8
#define Board_PWMPIN3 PIN_UNASSIGNED
#define Board_PWMPIN4 PIN_UNASSIGNED
#define Board_PWMPIN5 PIN_UNASSIGNED
#define Board_PWMPIN6 PIN_UNASSIGNED
#define Board_PWMPIN7 PIN_UNASSIGNED
///*
// * SPI0 interface with DBS chip 2.0
// */
//#define Board_SPI0_MISO PIN_UNASSIGNED
//#define Board_SPI0_MOSI PIN_UNASSIGNED
//#define Board_SPI0_CLK PIN_UNASSIGNED
//#define Board_SPI0_CS PIN_UNASSIGNED
//
///*
// * SPI1 interface work with LED
// */
//
//#define Board_SPI1_MISO PIN_UNASSIGNED
//#define Board_SPI1_MOSI PIN_UNASSIGNED
//#define Board_SPI1_CLK PIN_UNASSIGNED
//#define Board_SPI1_CS PIN_UNASSIGNED
//
///* Power Management Board */
//#define Board_SRDY Board_BP_Pin_J2_19
//#define Board_MRDY Board_BP_Pin_J1_2
//
///* PWM outputs */
//#define Board_PWMPIN0 PIN_UNASSIGNED
//#define Board_PWMPIN1 PIN_UNASSIGNED
//#define Board_PWMPIN2 PIN_UNASSIGNED
//#define Board_PWMPIN3 PIN_UNASSIGNED
//#define Board_PWMPIN4 PIN_UNASSIGNED
//#define Board_PWMPIN5 PIN_UNASSIGNED
//#define Board_PWMPIN6 PIN_UNASSIGNED
//#define Board_PWMPIN7 PIN_UNASSIGNED
/** ============================================================================
@@ -51,6 +51,8 @@ extern "C" {
#include <ti/drivers/PIN.h>
#include <driverlib/ioc.h>
#include "neu/headstage_pin.h"
/** ============================================================================
* Externs
* ==========================================================================*/
@@ -68,34 +70,34 @@ extern const PIN_Config BoardGpioInitTable[];
*/
/* Discrete outputs */
#define Board_RLED IOID_6
#define Board_GLED IOID_7
#define Board_RLED PIN_UNASSIGNED
#define Board_GLED PIN_UNASSIGNED
#define Board_LED_ON 1
#define Board_LED_OFF 0
/* Discrete inputs */
#define Board_BTN1 IOID_13
#define Board_BTN2 IOID_14
#define Board_BTN1 PIN_UNASSIGNED
#define Board_BTN2 PIN_UNASSIGNED
/* UART Board */
#define Board_UART_RX IOID_1 /* RXD */
#define Board_UART_TX IOID_2 /* TXD */
#define Board_UART_RX PIN_UNASSIGNED /* RXD */
#define Board_UART_TX PIN_UNASSIGNED /* TXD */
#define Board_UART_CTS PIN_UNASSIGNED /* CTS */
#define Board_UART_RTS PIN_UNASSIGNED /* RTS */
/* SPI Board */
#define Board_SPI0_MISO PIN_UNASSIGNED /* RF1.20 */
#define Board_SPI0_MOSI IOID_12 /* RF1.18 */
#define Board_SPI0_CLK PIN_UNASSIGNED /* RF1.16 */
#define Board_SPI0_CSN IOID_4
#define Board_SPI1_MISO PIN_UNASSIGNED
#define Board_SPI1_MOSI IOID_10
#define Board_SPI1_CLK IOID_9
#define Board_SPI1_CSN IOID_3
//#define Board_SPI0_MISO PIN_UNASSIGNED /* RF1.20 */
//#define Board_SPI0_MOSI PIN_UNASSIGNED /* RF1.18 */
//#define Board_SPI0_CLK PIN_UNASSIGNED /* RF1.16 */
//#define Board_SPI0_CSN PIN_UNASSIGNED
//#define Board_SPI1_MISO PIN_UNASSIGNED
//#define Board_SPI1_MOSI PIN_UNASSIGNED
//#define Board_SPI1_CLK PIN_UNASSIGNED
//#define Board_SPI1_CSN PIN_UNASSIGNED
/* I2C */
#define Board_I2C0_SCL0 IOID_4
#define Board_I2C0_SDA0 IOID_5
#define Board_I2C0_SCL0 PIN_UNASSIGNED
#define Board_I2C0_SDA0 PIN_UNASSIGNED
/* SPI */
#define Board_SPI_FLASH_CS IOID_20
@@ -123,21 +125,21 @@ extern const PIN_Config BoardGpioInitTable[];
/* Booster pack LCD (430BOOST - Sharp96 Rev 1.1) */
#define Board_LCD_CS IOID_24 // SPI chip select
#define Board_LCD_EXTCOMIN IOID_12 // External COM inversion
#define Board_LCD_EXTCOMIN PIN_UNASSIGNED // External COM inversion
#define Board_LCD_ENABLE IOID_22 // LCD enable
#define Board_LCD_POWER IOID_23 // LCD power control
#define Board_LCD_CS_ON 1
#define Board_LCD_CS_OFF 0
/* PWM outputs */
#define Board_PWMPIN0 Board_RLED
#define Board_PWMPIN1 Board_GLED
#define Board_PWMPIN2 IOID_5
#define Board_PWMPIN3 IOID_11
#define Board_PWMPIN4 PIN_UNASSIGNED
#define Board_PWMPIN5 PIN_UNASSIGNED
#define Board_PWMPIN6 PIN_UNASSIGNED
#define Board_PWMPIN7 PIN_UNASSIGNED
//#define Board_PWMPIN0 PIN_UNASSIGNED
//#define Board_PWMPIN1 PIN_UNASSIGNED
//#define Board_PWMPIN2 PIN_UNASSIGNED
//#define Board_PWMPIN3 PIN_UNASSIGNED
//#define Board_PWMPIN4 PIN_UNASSIGNED
//#define Board_PWMPIN5 PIN_UNASSIGNED
//#define Board_PWMPIN6 PIN_UNASSIGNED
//#define Board_PWMPIN7 PIN_UNASSIGNED
/** ============================================================================
* Instance identifiers
@@ -205,6 +205,7 @@ Error.maxDepth = 2;
/* ================ Hwi configuration ================ */
var halHwi = xdc.useModule('ti.sysbios.hal.Hwi');
var m3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
/*
* Checks for Hwi (system) stack overruns while in the Idle loop.
*
@@ -218,6 +219,7 @@ var m3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
*/
//halHwi.checkStackFlag = true;
halHwi.checkStackFlag = false;
//C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\.config\xconfig_app_ble
/*
* The following options alter the system's behavior when a hardware exception
@@ -287,6 +287,11 @@ static uint8_t CHIP_ID = 0;
*/
static uint16_t CONNECT_HANDLE = 0;
/**
* command instruction buffer
*/
static uint8_t cdr_buf[BLE_CDR_BUFF_SIZE] = {0};
/*====================
==== event table ====
====================*/
@@ -311,8 +316,7 @@ typedef struct {
==== device implement implement header ====
=========================================*/
#include "headstage_zm.h"
#include "headstage_uni.h"
/*======================
==== main function ====
======================*/
@@ -329,6 +333,9 @@ static EventTableEntry EVENT_TABLE[] = { //
#endif
#ifdef HEADSTAGE_STI_H
{EVT_ALL, &headstage_sti_event},
#endif
#ifdef HEADSTAGE_NEU_H
{EVT_ALL, &headstage_neu_event},
#endif
// terminated
{0, NULL}};
@@ -352,8 +359,6 @@ static void headstage_event_handle() {
* system handle for instruction input.
*/
static void headstage_update_instruction(uint8_t *instruction) {
static uint8_t cdr_buf[BLE_CDR_BUFF_SIZE] = {0};
uint8_t ins_type = instruction[0] & 0xF0;
CHIP_ID = instruction[0] & 0x0F;
uint8_t ins_oper = instruction[1] & 0xF0;
@@ -369,45 +374,8 @@ static void headstage_update_instruction(uint8_t *instruction) {
break;
}
case INS_TYPE_CIS: {
switch (ins_oper) {
case CIS_NOP: {
// nothing
cdr_buf[0] = _B_4b4b(CIS_NOP, CHIP_ID);
cdr_buf[1] = _B_4b4b(CDR_SUCCESS, 0);
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, 2, cdr_buf);
break;
}
#ifdef HEADSTAGE_CIS_VOLT_H
case CIS_VOLT: {
uint8_t status = headstage_update_vis_volt(ins_len, instruction + 2, cdr_buf + 2);
cdr_buf[0] = _B_4b4b(CIS_VOLT, CHIP_ID);
cdr_buf[1] = status;
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
#endif
#ifdef HEADSTAGE_CIS_LED_H
case CIS_LED: {
uint8_t status = headstage_update_vis_led(ins_len, instruction + 2, cdr_buf + 2);
cdr_buf[0] = _B_4b4b(CIS_LED, CHIP_ID);
cdr_buf[1] = status;
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
#endif
default: {
cdr_buf[0] = _B_4b4b(ins_oper, CHIP_ID);
cdr_buf[1] = _B_4b4b(CDR_FAILURE, 0);
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
}
headstage_update_cis_instruction(ins_oper);
break;
}
}
}
@@ -3,9 +3,9 @@
#ifndef HEADSTAGE_ARM_H
#define HEADSTAGE_ARM_H
static uint16_t headstage_ramp_data_counter = 0;
static void headstage_arm_append_ramp_data(uint8_t *buff) {
static uint16_t headstage_ramp_data_counter = 0;
uint16_t v = headstage_ramp_data_counter++;
@@ -25,8 +25,8 @@ static void headstage_cis_led_enable(uint8_t enable);
static uint8_t headstage_cis_led_set_pattern(uint8_t pattern);
/**
* @para pattern: pattern number
* @para parameter: led parameter, NULL to unset
* @param pattern: pattern number
* @param parameter: led parameter, NULL to unset
* @return: CDR_SUCCESS
*/
static uint8_t headstage_cis_led_set_value(uint8_t pattern, //
@@ -192,7 +192,7 @@ static void headstage_led_color(uint8_t color) {
==== LED implement (GPIO) ====
============================*/
#ifdef BOOSTXL_CC2650MA
#ifdef HEADSTAGE_UNI_H
#define HEADSTAGE_LED_USE_GPIO
#endif
@@ -208,10 +208,10 @@ static void headstage_led_spi_transmit() {
for (int8_t j = 15; j >= 0; j--) {
int16_t v = (d & (1 << j)); // why check > 0 or not
bool SET_LED = (v > 0) ? 1 : 0;
headstage_pin_output(PIN_LED_CLK, 1);
headstage_pin_output(PIN_LED_CLK, 0);
CPUdelay(16 * 400); // 2500hz
headstage_pin_output(PIN_LED_OUT, SET_LED);
headstage_pin_output(PIN_LED_CLK, 0);
headstage_pin_output(PIN_LED_CLK, 1);
CPUdelay(16 * 400); // 2500hz
}
}
@@ -31,7 +31,7 @@ optional implement
#include <xdc/runtime/Timestamp.h>
#define headstage_time_stamp_us() (Timestamp_get32() / 2)
#define headstage_time_stamp_us() (Timestamp_get32() / 2)
/*========================
==== notify function ====
@@ -66,7 +66,7 @@ static void headstage_notify_send() {
}
#else
SimpleProfile_SetParameter(BLE_NOT_BUFF_CHAR, BLE_NOT_BUFF_SIZE, headstage_notify_buffer) ;
SimpleProfile_SetParameter(BLE_NOT_BUFF_CHAR, BLE_NOT_BUFF_SIZE, headstage_notify_buffer);
#endif
}
@@ -14,6 +14,8 @@
#include "zm/headstage_pin.h"
#elif defined(HEADSTAGE_STI_H)
#include "sti/headstage_pin.h"
#elif defined(HEADSTAGE_NEU_H)
#include "neu/headstage_pin.h"
#else
#error "headstage_pin headstage_pin_configuration not defined"
@@ -0,0 +1,30 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
/**
\file headstage_swi.h
In order to enable interrupt, hookset function need declaring.
reference:ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/docs/Bios_User_Guide.pdf
*/
#ifndef HEADSTAGE_SWI_H
#define HEADSTAGE_SWI_H
#include <ti/sysbios/knl/Swi.h>
#include <xdc/runtime/Error.h>
/*
software interrupt
*/
Swi_Handle headstage_swi;
typedef void (*headstage_swiFxn)(UArg arg0, UArg arg1);
void headstage_swi_init(headstage_swiFxn callback) {
Error_Block eb;
Error_init(&eb);
headstage_swiFxn my_swi = callback;
headstage_swi = Swi_create(my_swi, NULL, &eb);
}
#endif
@@ -1,5 +1,5 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_H
#error "headstage.h not include"
#endif
@@ -7,6 +7,72 @@
#ifndef HEADSTAGE_UNI_H
#define HEADSTAGE_UNI_H
/**
* @file headstage_uni.h
*
* Copyright (c) 2019. BioPro. Scientific.
*
* NEULIVE firmware structure:
*
* headstage_init()
* headstage_uni_event()
* headstage_umc_state_transfer_lsk()
* headstage_umc_state_transfer_ask()
*
* description:
*
* Construct corresponding headstage_uni_event to implement the communication between
* DBS and CC2650. Because finite state machine is used to build the digital core,
* a similar structure to monitor its state is needed.
*
* headstage_uni_event:
*
* 1. LSK transmit event :
* receive LSK and process raw data
*
* 2. ASK transmit event :
* transmit ASK to DBS chip
*
* 3. trigger stimulation event:
* transmit trigger flag to DBS chip
*
* 4. Disconnect :
* stop system working
*
* ...reserved
*
* protocol between DBS chip and cc2650:
*
* DBS (LSK) -> CC2650 (SPI):
* format: 9'b PREAMBLE + 4'b HEADER + 10'bit DATA
* PREAMBLE: imply the channel order, refer to rearrange channel for more detail.
*
* cc2650 (SPI) -> DBS (ASK):
* format: 4'bHEADER + ( 10'b INSTRUCTION + 4'b ID ) * 2
* INSTRUCTION: construct the instruction corresponding to DBS chip
*
* state machine:
*
* In order to control the digital core inside DBS chip, this application needs to simulate a similar structure.
* (interrupt)
* IDLE -> HANDSHAKE -> HANDSHAKE_RECEIVE -> INITIAL -> CONFIGURE -> WAIT_START --> TRIGGER -> WAIT_TRIGGER ----------------> CONFIGURE
* | |
* --> LIMITED --|
* | |
* --> CONTINUOUS --
*
* State Description:
* There are two state machines implemented in this structure.
* Different state acts differently,
* e.g., CONFIGURE and WAIT_START would transmit the same code to DBS with different meaning
* state transfer in LSK:
* After receiving LSK data, acts corresponding to current state and decide to change state or not
* state transfer in ASK:
* After receiving ASK data, acts corresponding to current state
*
*/
// TODO low frequency mode
// TODO battery record
// TODO watchdog function need implementing
@@ -15,12 +81,30 @@
/*=================
==== constant ====
=================*/
// data transmit format 9'b PREAMBLE + 4'b HEADER + 10'bit DATA
// clang-format off
/**
specific data from DBS
In order to set recording channel, arrange a set of selected channel.
The first select channel data will come with preamble.
*/
#define UMC_PREAMBLE 0b011000001
/**
header used in LSK and ASK transmission
*/
#define UMC_HEADER 0b0101
// clang-format on
/**
The data format between NEULIVE and CONTROLL BOX
Use notification to transmit data to control box through BLE.
Definition of the protocol:
4'B timestamp + 2'B time delta + (4'b channel + 10'b voltage + 2'b flag) * (N)
N: numbers of data transmitted in a transaction
*/
#define HEADSTAGE_NOTIFY_USE_TDC4VAF2
/*================
==== include ====
@@ -33,22 +117,41 @@
#include "headstage_led.h"
#include "headstage_watchdog.h"
#include "headstage_notify.h"
#include "headstage_indicate.h"
#include "headstage_swi.h"
#include "tni/headstage_notify.h"
#include "uni/headstage_spi.h"
#include "uni/headstage_pwm.h"
#include "uni/headstage_adc.h"
#include "uni/uni1.2_parameter.h"
#include "headstage_indicate.h"
#include "uni/uni1.3_parameter.h"
/*===================================
==== instruction building macro ====
==================================*/
/**
construct final instruction
Construct the final instruction transmitted to DBS chip
final instruction = Header + instruction + instruction
@param code: prebuilt instruction
@return final instruction
*/
#define build_instruction(code) \
({ \
uint32_t __x = (code)&0x3FFF; \
(UMC_HEADER << 28) | (__x << 14) | (__x); \
})
/**
construct instruction
Construct the instruction and pass it to build_instruction.
Instruction = 4'b type(opcode) + 6'b value + 4'b chip_id
@param type: the opcode is going to be transmitted
@param value: the operating value
@return final instruction
*/
#define build_configure_instruction(type, value) \
({ \
@@ -58,14 +161,11 @@
build_instruction((__t << 10) | (__v << 4) | __c); \
})
#define build_conservative_instruction(type, value) \
({ \
uint32_t __t = (type)&0xF; \
uint32_t __v = (value)&0x3F; \
uint32_t __c = (CHIP_ID)&0xFF; \
uint32_t __x = ((__t << 6) | (__v)) & 0x3FF; \
(UMC_HEADER << 28) | (__x << 18) | (__c << 10) | (__x); \
})
/**
get data from spi_rxbuf and convert it to uint16_t
@param index: getting value from the index
@return receive data casting in uint16_t
*/
#define rx_get_u16(index) \
({ \
@@ -75,6 +175,12 @@
(__a << 8) | __b; \
})
/**
get data from spi_rxbuf and convert it to uint32_t
@param index: the index of spi_rxbuf
@return receive data casting in uint32_t
*/
#define rx_get_u32(index) \
({ \
uint32_t __i = (uint32_t)(index); \
@@ -85,6 +191,12 @@
(__a << 24) | (__b << 16) | (__c << 8) | __d; \
})
/**
put uint16_t into spi_txbuf
@param index: the index of spi_txbuf
@param value: the data is going to be set
*/
#define tx_put_u16(index, value) \
do { \
uint32_t __i = (uint32_t)(index); \
@@ -93,6 +205,12 @@
spi_txbuf[__i++] = (__v)&0xFF; \
} while (0)
/**
put uint32_t into spi_txbuf
@param index: the index of spi_txbuf
@param value: the data is going to be set
*/
#define tx_put_u32(index, value) \
do { \
uint32_t __i = (uint32_t)(index); \
@@ -107,37 +225,72 @@
==== constant ====
=================*/
// data rate
/**
this part frequency is controlling the operating
*/
// clang-format off
#define UMC_LSK_FREQ 100000 // 500 khz
#define UMC_ASK_FREQ 20000 // 100 khz
#define UMC_SYS_CLK 2000000 // target is 8Mhz
#define UMC_POLY_R_CLK 1000 // poly-R switching clock
/** target LSK data rate is 50 khz */
#define UMC_LSK_FREQ 50000
/** target ASK data rate is 10 khz */
#define UMC_ASK_FREQ 10000
/** target SYSTEM clock frequency is 1Mhz */
#define UMC_SYS_CLK 1000000
/** poly-R switching clock frequency */
#define UMC_POLY_R_CLK 100
// Neulive instruction macro
/// Neulive instruction macro
/** handshake information receive from DBS */
#define UMC_HAND_SHAKE_SEND 0b0011000011
/** handshake information send to DBS */
#define UMC_HAND_SHAKE_RECV 0b01010011000110000000110001100000
/** set the interface with DBS */
#define UMC_MODE_LSK_OUT 0b101001
#define UMC_CALIB_DONE 0b1010 // UMC_CALIB_DONE + UMC_MODE_LSK_OUT -> leave initial state and set "CHIP ID"
#define UMC_CONFIG_DONE 0b0100 // UMC_CONFIG_DONE + 6'bxxxxxx -> EXIT config state
/** UMC_CALIB_DONE + UMC_MODE_LSK_OUT : leave initial state and set "CHIP ID" */
#define UMC_CALIB_DONE 0b1010
/** UMC_CONFIG_DONE + 6 bits don't care : EXIT config state */
#define UMC_CONFIG_DONE 0b0100
/**
UMC_IRQ + UMC_IRQ_CODE + CHIP ID : go back to configure data from continuous, trigger, limited
UMC_IRQ type of interrupt
*/
#define UMC_IRQ 0b1110
#define UMC_IRQ_CODE 0b001001 // UMC_IRQ + UMC_IRQ_CODE + CHIP ID -> when we want to go back to configure data.
/** UMC_IRQ_CODE value of interrupt */
#define UMC_IRQ_CODE 0b001001
/** leave wait trigger state by this instruction */
#define UMC_GOLDEN_KEY 0b01011010010110000010100101100000 //this is important to leave wait trigger state.
// we need to check transfer data meets or not
#define UMC_TRANSMIT_S 0b101 // transmit success
/** we need to check transfer data meets or not */
#define UMC_TRANSMIT_S 0b101
// trigger stimulation by ask
/**
trigger a stimulation by ASK
UMC_TRIG + UMC_STIMULUS + CHIP ID
UMC_TRIG type of trigger a stimulus
*/
#define UMC_TRIG 0b1100
/**
UMC_STIMULUS value of trigger a stimulus
*/
#define UMC_STIMULUS 0b000011
/**
type of opcode, control box to cc2650.
*/
/** control box to cc2650:default type instruction */
#define RIS_DEFAULT 0x00
/** control box to cc2650 instruction opcode, parameter set 1 */
#define RIS_SET_PARA 0x20
/** control box to cc2650 instruction opcode, remove amplifier offset */
#define RIS_RESET_AMP 0x60
/** control box to cc2650 instruction opcode, parameter set 2 */
#define RIS_DIR 0xA0
/** control box to cc2650 instruction opcode, trigger stimulation */
#define RIS_UMC_TRIG 0xC0
/**
stimulation waveform
*/
#define STI_MODE_DISABLE 0
#define STI_MODE_POS 1
#define STI_MODE_NEG 2
@@ -146,11 +299,18 @@
#define STI_MODE_AWF 5
#define ARM_MODE_RAMP 8
/**
reserved virtual instruction
*/
#define VIS_BLE_T 0b10100000
#define VIS_SHIFT_T 0b01010000
// all the categories of instruction we can change .
/**
configuration set for DBS instruction
*/
#define CONFIG_AMP_CH 0x10 // this state is for transmit amp channel one more time
#define CONFIG_AMP_MUX 0x01
#define CONFIG_AMP_GAIN 0x02
@@ -280,7 +440,7 @@ struct HEADSTAGE_PARAMETER_TABLE {
/** MODE */
uint8_t mode;
uint8_t channel_table[REC_CHANNEL_COUNT];
bool channel_table[REC_CHANNEL_COUNT];
uint8_t channel_mux[REC_CHANNEL_COUNT];
uint8_t last_enable_channel;
uint8_t enable_channel_number;
@@ -332,12 +492,21 @@ struct HEADSTAGE_PARAMETER_TABLE {
*/
bool adc_clock_signal;
/*
/**
* amplifier reset
*/
bool amp_rst;
} INSTRUCTION = {0};
/**
@fn static void headstage_uni_delay()
@brief make some delay
*/
static void headstage_uni_delay() {
for (uint16_t i = 0; i < 1023; i++)
;
}
static void rearrange_channel_mux_table() {
uint8_t enable_channel_number = 0;
uint8_t last_enable_channel = 0;
@@ -351,7 +520,6 @@ static void rearrange_channel_mux_table() {
INSTRUCTION.last_enable_channel = last_enable_channel;
INSTRUCTION.enable_channel_number = enable_channel_number;
if (enable_channel_number == 0) {
// no channel enable
memset(INSTRUCTION.channel_mux, 0, REC_CHANNEL_COUNT);
@@ -372,11 +540,12 @@ static void rearrange_channel_mux_table() {
while (channel_mux_index >= 0) {
int8_t i = next_enable_channel - 1;
for (; i >= 0; i--) {
while (i >= 0) {
if (INSTRUCTION.channel_table[i]) {
next_enable_channel = i;
break;
}
i--;
}
if (i < 0) {
@@ -415,6 +584,10 @@ static void rearrange_channel_mux_table() {
#define UPDATE_DONE 0xFF
// clang-format on
/**
@struct UMC_STATE
*/
struct {
uint8_t state;
@@ -485,6 +658,7 @@ static void headstage_spi_ask_callback(SPI_Handle handle, SPI_Transaction* trans
}
static void headstage_spi_lsk_callback(SPI_Handle handle, SPI_Transaction* transaction) {
if (not_buf_offset >= BLE_NOT_BUFF_SIZE) Swi_post(headstage_swi);
if (UMC_STATE.reset_flag == 0) flag_notify(EVT_UMC_LSK);
}
@@ -507,6 +681,8 @@ static void headstage_reset() {
==== function implement ====
==========================*/
static void headstage_swi_func(UArg a0, UArg a1) {}
/**
* initialize parameter and device.
*/
@@ -514,6 +690,7 @@ static void headstage_init() {
headstage_pin_open();
headstage_spi_open();
headstage_pwm_open();
headstage_swi_init(headstage_swi_func);
headstage_led_spi_color(COLOR_GREEN);
// headstage_watchdog_open();
// if(headstage_watchdog_handle == NULL)
@@ -552,22 +729,20 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
break;
}
case RIS_SET_PARA: {
uint8_t amp_gain = (instruction[0] & 0x1C) >> 2;
uint8_t pulse_width = ((instruction[0] & 0x03) << 2) | ((instruction[1] & 0xC0) >> 6);
uint8_t sti_times = (instruction[1] & 0x3F);
uint8_t sti_freq = (instruction[2] & 0x3F);
uint8_t mode = (instruction[2] & 0xC0) >> 6;
uint8_t cha = (instruction[3] & 0x0F);
uint8_t chb = (instruction[4] & 0xF0) >> 4;
uint8_t chc = (instruction[4] & 0x0F);
uint8_t chd = (instruction[5] & 0xF0) >> 4;
uint8_t amp_gain = (instruction[0] & 0x1C) >> 2;
uint8_t pulse_width = ((instruction[0] & 0x03) << 2) | ((instruction[1] & 0xC0) >> 6);
uint8_t sti_times = (instruction[1] & 0x3F);
uint8_t sti_freq = (instruction[2] & 0x3F);
uint8_t mode = (instruction[2] & 0xC0) >> 6;
uint8_t cha = (instruction[3] & 0x0F);
uint8_t chb = (instruction[4] & 0xF0) >> 4;
uint8_t chc = (instruction[4] & 0x0F);
uint8_t chd = (instruction[5] & 0xF0) >> 4;
INSTRUCTION.amp_gain = amp_gain;
INSTRUCTION.pulse_width = pulse_width;
INSTRUCTION.sti_times = sti_times;
INSTRUCTION.mode = mode;
INSTRUCTION.sti_freq = sti_freq;
INSTRUCTION.mode = mode;
if (instruction[3] & 0b10000000) INSTRUCTION.channel_table[amp_channel_table[cha] - 1] = TRUE;
if (instruction[3] & 0b01000000) INSTRUCTION.channel_table[amp_channel_table[chb] - 1] = TRUE;
if (instruction[3] & 0b00100000) INSTRUCTION.channel_table[amp_channel_table[chc] - 1] = TRUE;
@@ -581,7 +756,7 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
INSTRUCTION.amp_gain = 5; // x1000
INSTRUCTION.pulse_width = 0; // 40us
INSTRUCTION.sti_times = 0; // repeat stimulation x1
INSTRUCTION.mode = 1; // trigger mode
INSTRUCTION.mode = 3; // trigger mode
INSTRUCTION.sti_freq = 3; // 30hz
INSTRUCTION.sti_waveform = 1; // positive
INSTRUCTION.chopper = 0; // turn off chopper
@@ -590,7 +765,6 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
INSTRUCTION.sti_channel_nmos = 0; // sti nch = ch2 means sti turn off
INSTRUCTION.sti_channel_pmos = 1; // sti pch = ch1 means sti turn off
INSTRUCTION.amp_low_band_freq = 0; // the maximum
// this for-loop is used for setting the amplifier channel
// for (unsigned int i = 0; i < REC_CHANNEL_COUNT; i++) {
// INSTRUCTION.channel_table[i] = (4 <= i && i <= 8);
@@ -598,18 +772,16 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
break;
}
case RIS_UMC_TRIG:
case RIS_UMC_TRIG: {
tx_put_u32(0, build_configure_instruction(UMC_TRIG, UMC_STIMULUS));
flag_notify(EVT_UMC_STI);
/*
load
*/
break;
case RIS_RESET_AMP:
}
case RIS_RESET_AMP:{
tx_put_u32(0, build_configure_instruction(UMC_TRIG, UMC_STIMULUS));
headstage_spi_ask_transaction(4);
break;
}
default:
break;
}
@@ -625,9 +797,10 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
break;
case VIS_STI:
if (headstage_state == UMC_STATE_INTERRUPT) {
headstage_state = UMC_STATE_CONFIGURE;
headstage_state = UMC_STATE_INITIAL;
rearrange_channel_mux_table();
UMC_STATE.config_type = CONFIG_AMP_MUX;
headstage_led_spi_color(COLOR_BLACK);
tx_put_u32(0, build_configure_instruction(UMC_IRQ, UMC_IRQ_CODE));
headstage_spi_ask_transaction(4);
} else {
@@ -645,11 +818,8 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
// interrupt
case VIS_INT:
headstage_state = UMC_STATE_INTERRUPT;
headstage_spi_transaction_cancel(headstage_spi_lsk_handle);
memset(headstage_debug_buffer, 0, BLE_NOT_BUFF_SIZE);
tx_put_u32(0, build_configure_instruction(UMC_IRQ, UMC_IRQ_CODE));
headstage_spi_ask_transaction(4);
headstage_reset();
headstage_state = UMC_STATE_HANDSHAKE;
break;
case VIS_BLE_T:
@@ -667,6 +837,52 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
}
}
/**
* @fn headstage_update_cis_instruction
*/
static void headstage_update_cis_instruction(uint8_t cis_oper) {
switch (cis_oper) {
case CIS_NOP: {
// nothing
cdr_buf[0] = _B_4b4b(CIS_NOP, CHIP_ID);
cdr_buf[1] = _B_4b4b(CDR_SUCCESS, 0);
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, 2, cdr_buf);
break;
}
#ifdef HEADSTAGE_CIS_VOLT_H
case CIS_VOLT: {
uint8_t status = headstage_update_vis_volt(ins_len, instruction + 2, cdr_buf + 2);
cdr_buf[0] = _B_4b4b(CIS_VOLT, CHIP_ID);
cdr_buf[1] = status;
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
#endif
#ifdef HEADSTAGE_CIS_LED_H
case CIS_LED: {
uint8_t status = headstage_update_vis_led(ins_len, instruction + 2, cdr_buf + 2);
cdr_buf[0] = _B_4b4b(CIS_LED, CHIP_ID);
cdr_buf[1] = status;
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
#endif
default: {
cdr_buf[0] = _B_4b4b(cis_oper, CHIP_ID);
cdr_buf[1] = _B_4b4b(CDR_FAILURE, 0);
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
}
}
/*
* todo: need to define some procedure to detect this device status
*/
@@ -689,12 +905,6 @@ static void headstage_uni_test_data_append_notify_buffer(uint8_t* dat_buf) {
headstage_notify_send();
}
// implement this function to detect
static void headstage_uni_delay() {
for (uint16_t i = 0; i < 1023; i++)
;
}
// todo: check data length extension with this function -> this function should be
static void headstage_uni_umc_data_append_notify_buffer(uint8_t* dat_buf) {
// check LSK data preamble ( 0b01100_0001 ) 58(01011000) 2c(00101100)
@@ -702,46 +912,43 @@ static void headstage_uni_umc_data_append_notify_buffer(uint8_t* dat_buf) {
// 0110_0000_1010_1xxx_xxxx_xxxX_XXXX_XXXX and
// 1100_0001_0101_xxxx_xxxx_xxXX_XXXX_XXXX
if (((spi_rxbuf[0] & 0xC1) != 0xC1) && (spi_rxbuf[0] != 0x00)) {
headstage_uni_delay();
headstage_led_spi_color(COLOR_CYAN);
headstage_uni_delay();
} else {
if ((dat_buf[1] & 0x28) == 0x28) {
dat_buf[0] = (dat_buf[0] << 1) | ((dat_buf[1] >> 7) & 0x01);
dat_buf[1] = (dat_buf[1] << 1) | ((dat_buf[2] >> 7) & 0x01);
dat_buf[2] = (dat_buf[2] << 1) | ((dat_buf[3] >> 7) & 0x01);
if ((spi_rxbuf[1] & 0x28) == 0x28) {
spi_rxbuf[0] = (spi_rxbuf[0] << 1) | ((spi_rxbuf[1] >> 7) & 0x01);
spi_rxbuf[1] = (spi_rxbuf[1] << 1) | ((spi_rxbuf[2] >> 7) & 0x01);
spi_rxbuf[2] = (spi_rxbuf[2] << 1) | ((spi_rxbuf[3] >> 7) & 0x01);
}
uint8_t channel;
if ((INSTRUCTION.enable_channel_number == 1) || (dat_buf[0] == 0xc1)) {
if ((INSTRUCTION.enable_channel_number == 1) || (spi_rxbuf[0] == 0xc1)) {
channel = reverse_channel[INSTRUCTION.last_enable_channel];
} else {
uint8_t channel_pointer = (INSTRUCTION.channel_pointer + 1) % INSTRUCTION.last_enable_channel;
INSTRUCTION.channel_pointer = channel_pointer;
channel = reverse_channel[INSTRUCTION.channel_mux[channel_pointer]];
INSTRUCTION.channel_pointer = channel_pointer;
}
// uint16_t data_value = (uint16_t)(((dat_buf[1] & 0x0F) << 6) | ((dat_buf[2] & 0xFC) >> 2));
uint8_t data_size = headstage_notify_append_data(channel, dat_buf);
uint8_t data_size = headstage_notify_append_data(channel, spi_rxbuf);
if (data_size >= BLE_NOT_BUFF_SIZE) {
headstage_notify_send();
headstage_notify_flip_buffer();
}
}
// uint16_t data_value = (uint16_t)(((dat_buf[1] & 0x0F) << 6) | ((dat_buf[2] & 0xFC) >> 2));
headstage_spi_lsk_transaction(3);
}
/*=====================
==== instruction ====
=====================*/
static uint8_t build_umn_ins_config(uint8_t config_type, uint32_t* value) {
switch (config_type) {
case CONFIG_AMP_MUX: {
uint8_t channel_pointer = INSTRUCTION.channel_pointer + 1;
*value = build_configure_instruction(CONFIG_AMP_MUX, INSTRUCTION.channel_mux[INSTRUCTION.channel_pointer] + 1);
INSTRUCTION.channel_pointer = channel_pointer;
if (channel_pointer < INSTRUCTION.enable_channel_number) {
return CONFIG_AMP_MUX;
} else {
@@ -820,7 +1027,10 @@ static uint8_t build_umn_ins_config(uint8_t config_type, uint32_t* value) {
==== UMC SPI interface ====
=========================*/
// ASK interface
/**
* @fn headstage_umc_state_transfer_ask
*
*/
static void headstage_umc_state_transfer_ask() {
// after receive handshake , transmit handreceive
@@ -844,6 +1054,7 @@ static void headstage_umc_state_transfer_ask() {
case UMC_STATE_TRIGGER:
case UMC_STATE_CONTINUOUS:
case UMC_STATE_LIMITED:
case UMC_STATE_INTERRUPT:
break;
case UMC_STATE_WAIT_TRIGGER:
headstage_state = UMC_STATE_TRIGGER;
@@ -854,9 +1065,10 @@ static void headstage_umc_state_transfer_ask() {
}
}
/** headstage_umc_state_transfer_lsk
*
*/
static void headstage_umc_state_transfer_lsk() {
headstage_debug_buffer[0] = headstage_state;
headstage_set_debug_information();
switch (headstage_state) {
case UMC_STATE_IDLE:
headstage_state = UMC_STATE_HANDSHAKE;
@@ -878,14 +1090,10 @@ static void headstage_umc_state_transfer_lsk() {
if (umc_pass_check()) {
tx_put_u32(0, build_configure_instruction(UMC_CALIB_DONE, UMC_MODE_LSK_OUT));
headstage_cpu_delay_ms(1);
headstage_state = UMC_STATE_INITIAL;
headstage_spi_ask_transaction(4);
} else {
headstage_cpu_delay_ms(1);
headstage_spi_ask_transaction(4);
}
break;
@@ -894,11 +1102,8 @@ static void headstage_umc_state_transfer_lsk() {
if (umc_pass_check()) {
headstage_state = UMC_STATE_CONFIGURE;
headstage_cpu_delay_ms(1);
headstage_spi_ask_transaction(4);
} else {
headstage_cpu_delay_ms(1);
headstage_spi_ask_transaction(4);
}
@@ -922,13 +1127,9 @@ static void headstage_umc_state_transfer_lsk() {
headstage_state = UMC_STATE_CONFIGURE;
}
headstage_cpu_delay_ms(1);
headstage_spi_ask_transaction(4);
}
} else {
headstage_cpu_delay_ms(1);
headstage_spi_ask_transaction(4);
}
@@ -939,28 +1140,39 @@ static void headstage_umc_state_transfer_lsk() {
case UMC_STATE_WAIT_START:
if (headstage_debug_buffer[1] > 18) {
// this transaction make cause amplifier data right shift
headstage_spi_lsk_transaction(3);
switch (INSTRUCTION.mode) {
default:
headstage_state = UMC_STATE_CONTINUOUS;
UMC_STATE.trigger_times = 0;
break;
case 3:
case 0:
// continuous mode
headstage_state = UMC_STATE_CONTINUOUS;
headstage_state = UMC_STATE_TRIGGER;
UMC_STATE.trigger_times = 0;
headstage_spi_lsk_transaction(3);
break;
case 1:
// trigger mode
headstage_state = UMC_STATE_TRIGGER;
UMC_STATE.trigger_times = 0;
headstage_spi_lsk_transaction(3);
break;
case 2:
// limited mode
headstage_state = UMC_STATE_LIMITED;
UMC_STATE.trigger_times = INSTRUCTION.sti_times;
headstage_spi_lsk_transaction(3);
break;
case 3:
// continuous mode
headstage_state = UMC_STATE_CONTINUOUS;
UMC_STATE.trigger_times = 0;
headstage_spi_lsk_transaction(3);
break;
default:
headstage_state = UMC_STATE_CONTINUOUS;
UMC_STATE.trigger_times = 0;
headstage_spi_lsk_transaction(3);
break;
}
} else if (headstage_debug_buffer[1] > 10) {
@@ -993,7 +1205,8 @@ static void headstage_umc_state_transfer_lsk() {
headstage_state = UMC_STATE_WAIT_START;
}
break;
case UMC_STATE_INTERRUPT:
break;
default:
break;
}
@@ -8,7 +8,7 @@
#define HEADSTAGE_ZM_H
// product information
#define DEVICE_NAME "Elite-ZM-v1.4-re"
#define DEVICE_NAME "Elite-ZM-v1.2-30"
#define MAJOR_PRODUCT_NUMBER 0
#define MINOR_PRODUCT_NUMBER 2
#define MAJOR_VERSION_NUMBER 1
@@ -0,0 +1,5 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_ADC_H
#define HEADSTAGE_ADC_H
#endif
@@ -0,0 +1,16 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef NEULIVE_2P0
#define NEULIVE_2P0
/*============================
==== product information ====
===========================*/
#define DEVICE_NAME "Neulive-v2.0"
#define MAJOR_PRODUCT_NUMBER 1
#define MINOR_PRODUCT_NUMBER 1
#define MAJOR_VERSION_NUMBER 2
#define MINOR_VERSION_NUMBER 0
#endif
@@ -0,0 +1,61 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_NOTIFY_TDC4VC_H
#define HEADSTAGE_NOTIFY_TDC4VC_H
#ifndef HEADSTAGE_NOTIFY_H
#error "headstage/headstage_notify.h not included"
#endif
#define NOT_BUF_OFFSET_INIT 8
static uint32_t not_buf_offset = NOT_BUF_OFFSET_INIT;
static uint32_t not_time_stamp = 0;
static void headstage_notify_set_timestamp() {
not_time_stamp = headstage_time_stamp_us();
headstage_notify_buffer[2] = not_time_stamp & 0xFF;
headstage_notify_buffer[3] = (not_time_stamp >> 8) & 0xFF;
headstage_notify_buffer[4] = (not_time_stamp >> 16) & 0xFF;
headstage_notify_buffer[5] = (not_time_stamp >> 24) & 0xFF;
}
static void headstage_notify_flip_buffer() {
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 2;
headstage_notify_buffer[0] = CHIP_ID;
headstage_notify_buffer[1] = data_count;
not_buf_offset = NOT_BUF_OFFSET_INIT;
}
static uint8_t headstage_notify_append_data(uint8_t *data_value) {
if (not_buf_offset <= NOT_BUF_OFFSET_INIT) {
headstage_notify_set_timestamp();
not_buf_offset = NOT_BUF_OFFSET_INIT;
}
if (data_value == NULL) {
headstage_notify_buffer[not_buf_offset++] = 0x00;
headstage_notify_buffer[not_buf_offset++] = 0x03;
} else {
headstage_notify_buffer[not_buf_offset++] = data_value[0];
headstage_notify_buffer[not_buf_offset++] = data_value[1];
}
if (not_buf_offset == BLE_NOT_BUFF_SIZE) {
uint32_t current = headstage_time_stamp_us();
uint32_t time_delta = ((current - not_time_stamp)) & 0xFFFF;
headstage_notify_buffer[6] = time_delta & 0xFF;
headstage_notify_buffer[7] = (time_delta >> 8) & 0xFF;
}
uint8_t ret = not_buf_offset;
return ret;
}
#endif // HEADSTAGE_NOTIFY_TDC4VAF2_H
@@ -0,0 +1,84 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_PIN_NEU_H
#define HEADSTAGE_PIN_NEU_H
#if defined(CC2650_LAUNCHXL)
// clang-format off
#define PIN_RESET IOID_0 // SPI1 to receive LSK
#define PIN_EN_ADC_SPI_CLK IOID_1 // SPI1 clock
#define PIN_DC_DC IOID_2 // STI select need
#define PIN_BATT_HALF IOID_3 //
#define PIN_AMP_VCK IOID_4 //
#define PIN_LED_SDI IOID_7 //
#define PIN_LED_CLK IOID_8 //
#define PIN_STI_CLK IOID_9 //
#define PIN_SPI_MISO IOID_10 //
#define PIN_SPI_MOSI IOID_11 //
#define PIN_SPI_CS IOID_12 //
#define PIN_SPI_CLK IOID_13 //
#define PIN_SYS_CLK IOID_14 //
// clang-format on
#elif defined(BOOSTXL_CC2650MA)
// clang-format off
#define PIN_RESET IOID_0 // SPI1 to receive LSK
#define PIN_EN_ADC_SPI_CLK IOID_1 // SPI1 clock
#define PIN_DC_DC IOID_2 // STI select need
#define PIN_BATT_HALF IOID_3 //
#define PIN_AMP_VCK IOID_4 //
#define PIN_LED_SDI IOID_7 //
#define PIN_LED_CLK IOID_8 //
#define PIN_STI_CLK IOID_9 //
#define PIN_SPI_MISO IOID_10 //
#define PIN_SPI_MOSI IOID_11 //
#define PIN_SPI_CS IOID_12 //
#define PIN_SPI_CLK IOID_13 //
#define PIN_SYS_CLK IOID_14 //
// clang-format on
#endif
/*
* SPI0 interface with DBS chip 2.0
*/
#define Board_SPI0_MISO PIN_SPI_MISO
#define Board_SPI0_MOSI PIN_SPI_MOSI
#define Board_SPI0_CLK PIN_SPI_CLK
#define Board_SPI0_CSN PIN_SPI_CS
/*
* SPI1 interface work with LED
*/
#define Board_SPI1_MISO PIN_UNASSIGNED
#define Board_SPI1_MOSI PIN_LED_SDI
#define Board_SPI1_CLK PIN_LED_CLK
#define Board_SPI1_CSN PIN_UNASSIGNED
/* Power Management Board */
#define Board_SRDY Board_BP_Pin_J2_19
#define Board_MRDY Board_BP_Pin_J1_2
/* PWM outputs */
#define Board_PWMPIN0 PIN_AMP_VCK
#define Board_PWMPIN1 PIN_UNASSIGNED
#define Board_PWMPIN2 PIN_SYS_CLK
#define Board_PWMPIN3 PIN_UNASSIGNED
#define Board_PWMPIN4 PIN_UNASSIGNED
#define Board_PWMPIN5 PIN_UNASSIGNED
#define Board_PWMPIN6 PIN_UNASSIGNED
#define Board_PWMPIN7 PIN_UNASSIGNED
static PIN_Config headstage_pin_configuration[] = { //
PIN_RESET | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_EN_ADC_SPI_CLK | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_DC_DC | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_BATT_HALF | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_STI_CLK | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
//
PIN_TERMINATE};
#endif // HEADSTAGE_PIN_UNI_H
@@ -0,0 +1,37 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_PWM_H
#define HEADSTAGE_PWM_H
#include <Board.h>
#include <ti/drivers/PWM.h>
static PWM_Handle headstage_system_pwm_handle = NULL;
static PWM_Handle headstage_poly_r_pwm_handle = NULL; // poly-R adjustment clock
#define headstage_pwm_open() \
do { \
PWM_init(); \
PWM_Params headstage_system_pwm_params; \
PWM_Params_init(&headstage_system_pwm_params); \
headstage_system_pwm_params.idleLevel = PWM_IDLE_LOW; \
headstage_system_pwm_params.periodUnits = PWM_PERIOD_HZ; \
headstage_system_pwm_params.periodValue = NEU_SYS_CLK; \
headstage_system_pwm_params.dutyUnits = PWM_DUTY_FRACTION; \
headstage_system_pwm_params.dutyValue = PWM_DUTY_FRACTION_MAX / 2; \
headstage_system_pwm_handle = PWM_open(Board_PWM2, &headstage_system_pwm_params); \
PWM_Params headstage_poly_r_pwm_params; \
PWM_Params_init(&headstage_poly_r_pwm_params); \
headstage_poly_r_pwm_params.idleLevel = PWM_IDLE_LOW; \
headstage_poly_r_pwm_params.periodUnits = PWM_PERIOD_HZ; \
headstage_poly_r_pwm_params.periodValue = NEU_POLY_R_CLK; \
headstage_poly_r_pwm_params.dutyUnits = PWM_DUTY_FRACTION; \
headstage_poly_r_pwm_params.dutyValue = PWM_DUTY_FRACTION_MAX / 2; \
headstage_poly_r_pwm_handle = PWM_open(Board_PWM0, &headstage_poly_r_pwm_params); \
} while (0)
#define headstage_pwm_start(handle) PWM_start(handle)
#define headstage_pwm_stop(handle) PWM_stop(handle)
#define headstage_pwm_close(handle) PWM_close(handle)
#endif // HEADSTAGE_PWM_H
@@ -0,0 +1,73 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_SPI_H
#define HEADSTAGE_SPI_H
#if defined(BOOSTXL_CC2650MA) && !defined(HEADSTAGE_MA_USE_SPI2)
#error "put HEADSTAGE_MA_USE_SPI2 in predefined"
#endif
#include <Board.h>
#include <ti/drivers/SPI.h>
#include <ti/drivers/dma/UDMACC26XX.h>
#include <ti/drivers/spi/SPICC26XXDMA.h>
#define SPI_BUFFER_SIZE 20
static uint8_t spi_txbuf[SPI_BUFFER_SIZE] = {0};
static uint8_t spi_rxbuf[SPI_BUFFER_SIZE] = {0};
static SPI_Handle headstage_spi_handle = NULL;
static SPI_Transaction headstage_spi_transaction;
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction);
// SPI parameters initialize
#define headstage_spi_open() \
do { \
SPI_init(); \
SPI_Params spi_parameter; \
SPI_Params_init(&spi_parameter); \
spi_parameter.transferMode = SPI_MODE_CALLBACK; \
spi_parameter.mode = SPI_SLAVE; \
spi_parameter.bitRate = NEU_SPI_FREQ; \
spi_parameter.dataSize = 8; \
spi_parameter.frameFormat = SPI_POL0_PHA1; \
spi_parameter.transferCallbackFxn = headstage_spi_callback; \
headstage_spi_handle = SPI_open(Board_SPI0, &spi_parameter); \
} while (0)
#define headstage_spi_transaction(handle, length, tx, rx) \
({ \
SPI_Transaction transaction = headstage_spi_transaction ; \
transaction.count = (length); \
transaction.txBuf = (tx); \
transaction.rxBuf = (rx); \
SPI_transfer(handle, &transaction); \
})
#define headstage_spi_transaction(length) \
({ \
headstage_spi_transaction.count = (length); \
headstage_spi_transaction.txBuf = (spi_txbuf); \
headstage_spi_transaction.rxBuf = (spi_rxbuf); \
SPI_transfer(headstage_spi_handle, &headstage_spi_transaction); \
})
#define headstage_spi_close(spi_handle) \
do { \
if (spi_handle != NULL) { \
SPI_close(spi_handle); \
spi_handle = NULL; \
} \
} while (0)
#define headstage_spi_transaction_cancel(spi_handle) \
do { \
if (spi_handle != NULL) { \
SPI_transferCancel(spi_handle); \
} \
} while (0)
#endif
@@ -0,0 +1,305 @@
{
"name": "Neulive",
"version": "2.0",
"match_rule": {
"local_name_pattern": "Neulive.*",
"major_product_number": 1,
"minor_product_number": 1,
"major_version_number": 2,
"minor_version_number": 0
},
"constant": {
"REC_CHANNEL_COUNT": 16,
"STI_VOLT_CHANNEL_COUNT": 16,
"STI_AMP_CHANNEL_COUNT": 8
},
"parameters": {
"CHANNEL": {
"description": "record channels",
"record_meta": true,
"domain": {
"set": [
"REC_CHANNEL_COUNT"
]
}
},
"STI_VOLT_PCHANNEL": {
"description": "stimulation voltage mode channels",
"record_meta": true,
"domain": {
"set": [
"STI_VOLT_CHANNEL_COUNT"
]
},
"guard": "STI_VOLT_PCHANNEL != STI_VOLT_NCHANNEL"
},
"STI_VOLT_NCHANNEL": {
"description": "stimulation voltage mode channels",
"record_meta": true,
"domain": {
"set": [
"STI_VOLT_CHANNEL_COUNT"
]
},
"guard": "STI_VOLT_PCHANNEL != STI_VOLT_NCHANNEL"
},
"STI_AMP_PCHANNEL": {
"description": "stimulation ampere mode p channel",
"record_meta": true,
"domain": {
"set": [
"STI_AMP_CHANNEL_COUNT"
]
},
"guard": "STI_AMP_PCHANNEL != STI_AMP_NCHANNEL"
},
"STI_AMP_NCHANNEL": {
"description": "stimulation ampere mode n channel",
"record_meta": true,
"domain": {
"set": [
"STI_AMP_CHANNEL_COUNT"
]
},
"guard": "STI_AMP_PCHANNEL != STI_AMP_NCHANNEL"
},
"STI_TIME_DURATION_ONE": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
1024
],
"guard": "STI_TIME_DURATION_ONE < 1"
},
"STI_TIME_DURATION_TWO": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
1024
]
},
"STI_TIME_DURATION_THREE": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
1024
]
},
"STI_TIME_DURATION_FOUR": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
65536
]
},
"STI_TIME_DURATION_FIVE": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
2048
]
},
"AMP_GAIN": {
"description": "amplifier gain setting",
"record_meta": true,
"value": [
25,
100,
400,
800
]
},
"STI_MODE": {
"description": "how to execute stimulus",
"value": [
"DISABLE",
"LIMITED",
"CONTINUOUS"
]
},
"STI_AMPERE_HIGH_SIDE": {
"description": "stimulation ampere for pmos, unit: uA ",
"type": "int",
"domain": [
1024
],
"value": "VALUE * 4"
},
"STI_AMPERE_LOW_SIDE": {
"description": "stimulation ampere for nmos, unit: uA",
"type": "int",
"domain": [
1024
],
"value": "VALUE * 4"
},
"STI_VOLTAGE_AMPLITUDE": {
"description": "stimulation voltage mode, unit: Volt ",
"type": "float",
"domain": [
32
],
"value": " 2 + VALUE / 31"
},
"STI_TIMES": {
"description": "how many times will be executed",
"domain": [
256
]
},
"SYSTEM_CLOCK_RATIO": {
"description": "frequency of system clock, unit: khz",
"type": "float",
"domain": [
65536
],
"value": " 8000 / VALUE",
"guard": "SYSTEM_CLOCK_RATIO < 2"
},
"ADC_CLOCK_RATIO": {
"description": "adc sampling rate, unit: khz",
"type": "float",
"domain": [
65536
],
"value": " SYSTEM_CLOCK_RATIO / VALUE ",
"guard": "ADC_CLOCK_RATIO < 28"
},
"STI_CLOCK_RATIO": {
"description": "stimulation rate",
"type": "float",
"domain": [
65536
],
"value": "SYSTEM_CLOCK_RATIO / VALUE",
"guard": "STI_CLOCK_RATIO < 2"
},
"ARBITRARY_EN": {
"description": "arbitrary stimulation enable",
"domain": "bool"
},
"ARBITRARY_CH": {
"description": "arbitrary stimulation enable channels",
"domain": "int",
"value": " ( 1 << STI_AMP_PCHANNEL ) if (ARBITRARY_EN) else 0 "
},
"ARBITRARY_INDEX": {
"description": "define the last point of arbitrary data, from zero to arbitrary_index. ",
"domain": "INT",
"guard": "VALUE > 499"
},
"H_BRIDGE": {
"description": "whether to contruct a h bridge execute a stimulation",
"domain": "bool"
},
"STI_REF": {
"description": "bipolar or monopolar",
"domain": "bool"
},
"FAST_SETTLE": {
"description": "protect amplifier input when stimulation is executed",
"domain": "bool"
},
"UMC_TEST": {
"description": "start umc test mode",
"domain": "action",
"on_change": "umc_default"
},
"UMC_RESET": {
"description": "reset headstage to perform another setting",
"domain": "action",
"on_change": "reset"
},
"UMC_TRIGGER": {
"description": "trigger stimulation when device is in trigger mode",
"domain": "action",
"on_change": "STIMULUS"
}
},
"instruction": {
"start": [
{
"expression": "len(CHANNEL) > 0",
"raise": "no recording channel"
},
"data_format",
"_notify(True)",
"start_recording",
"umc_parameter",
"_sync(True)",
"VIS_STI"
],
"trigger stimulation": [
"umc_sti_trigger0"
],
"umc_reset": [
"VIS_RST"
],
"data_format": [
"_data_format('TDC4VAF2')"
],
"start_recording": {
"type": "RIS",
"data": [
"3b101#direct header;2b0#don't care;3b>LOW_FREQ_BAND",
"2b0#don't care;1bCHOPPER;1bFAST_SETTLE;3b>STI_WAVEFORM",
"5b>STI_AMPERE;4b>STI_PMOS",
"4b>STI_NMOS;4b>SAMPLE_RATE"
]
},
"umc_parameter": {
"type": "RIS",
"foreach-parameter": {
"parameter": "CHANNEL",
"variable": [
"a",
"b",
"c",
"d"
]
},
"data": [
"3b001#umc parameter header;3b>AMP_GAIN",
"4b>PULSE_WIDTH;6b>STI_TIMES",
"2b>STI_MODE;6b>STI_FREQ",
"1ba?;1bb?;1bc?;1bd?",
"4b>a?:0;4b>b?:0",
"4b>c?:0;4b>d?:0"
]
},
"umc_default": [
"_set('CHANNEL', 0)",
"_set('SAMPLE_RATE', 0)",
"_set('AMP_GAIN', 5)",
"_set('STI_WAVEFORM', 1)",
"_set('STI_MODE', 1)",
"_set('STI_NMOS', 0)",
"_set('STI_PMOS', 1)",
"_set('STI_AMPERE', 0)",
"_set('STI_FREQ', 0)",
"_set('STI_TIMES', 0)",
"_set('PULSE_WIDTH', 0)",
"_set('FAST_SETTLE', 1)",
"_set('CHOPPER', 0)",
"data_format",
"_notify(True)",
"umc_default0",
"_sync(True)",
"VIS_STI"
],
"umc_default0": {
"type": "RIS",
"data": [
"1B0#load umc default parameter into uni"
]
},
"umc_sti_trigger0": {
"type": "RIS",
"description": "this function is perform only in trigger mode",
"data": [
"1BC0# trigger stimulation when recording is performed"
]
}
}
}
@@ -0,0 +1,19 @@
@startuml
start
:stimulation select;
if (continuous) then (yes)
if(current mode / voltage mode) then (current mode)
:sti parameter setup;
else (voltage mode)
:sti parameter setup;
endif
else if (limited)
if(current mode / voltage mode) then (current mode)
:sti parameter setup;
else (voltage mode)
:sti parameter setup;
endif
else (disable)
endif
stop
@enduml
@@ -42,6 +42,38 @@
// clang-format on
/*
* SPI0 interface with DBS chip 2.0
*/
#define Board_SPI0_MISO PIN_UNASSIGNED
#define Board_SPI0_MOSI PIN_LSK_MOSI
#define Board_SPI0_CLK PIN_LSK_CLK
#define Board_SPI0_CSN PIN_LSK_CS
/*
* SPI1 interface work with LED
*/
#define Board_SPI1_MISO PIN_UNASSIGNED
#define Board_SPI1_MOSI PIN_ASK_MOSI
#define Board_SPI1_CLK PIN_UNASSIGNED
#define Board_SPI1_CSN PIN_ASK_CS
/* Power Management Board */
#define Board_SRDY Board_BP_Pin_J2_19
#define Board_MRDY Board_BP_Pin_J1_2
/* PWM outputs */
#define Board_PWMPIN0 PIN_AMP_VCK
#define Board_PWMPIN1 PIN_UNASSIGNED
#define Board_PWMPIN2 PIN_CLOCK_8M
#define Board_PWMPIN3 PIN_UNASSIGNED
#define Board_PWMPIN4 PIN_UNASSIGNED
#define Board_PWMPIN5 PIN_UNASSIGNED
#define Board_PWMPIN6 PIN_UNASSIGNED
#define Board_PWMPIN7 PIN_UNASSIGNED
#endif
static PIN_Config headstage_pin_configuration[] = { //
@@ -12,53 +12,53 @@
"REC_CHANNEL_COUNT": 12,
"STI_CHANNEL_COUNT": 4,
"ADC_SAMPLE_RATE_LIST": [
2000,
1000,
1900,
3800,
7600,
15200,
30400
15200
],
"STI_FREQ_LIST": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
22,
24,
26,
28,
30,
32,
34,
36,
38,
40,
100,
200,
300,
400,
500,
600,
700,
800,
1000,
1200,
1400,
1600,
1800,
2000
900,
1000
],
"STI_PULSE_WIDTH": [
80,
180,
280,
380,
480,
580,
680,
780,
880,
980
400,
900,
1400,
1900,
2400,
2900,
3400,
3900,
4400,
4900
]
},
"parameters": {
@@ -84,9 +84,6 @@
"description": "amp gain",
"record_meta": true,
"value": [
3,
14,
27,
60,
280,
540
@@ -187,10 +184,6 @@
},
"instruction": {
"start": [
{
"expression": "len(CHANNEL) > 0",
"raise": "no recording channel"
},
"data_format",
"_notify(True)",
"start_recording",
@@ -55,9 +55,6 @@ static uint16_t amp_gain_table[] = {
0b100011, // 3
0b101100, // 14
0b101001, // 27
0b000011, // 60
0b001100, // 280
0b001001, // 540
};
#endif
@@ -4,37 +4,14 @@
#define HEADSTAGE_PIN_ZM_H
// clang-format off
#define PIN_ADC_CS IOID_8
#define PIN_DAC_CS IOID_9
#define PIN_SWITCH_ON IOID_11
#define PIN_SHUTDOWN_6994 IOID_10
#define PIN_ADC_CS IOID_2
#define PIN_DAC_CS IOID_4
#define PIN_SWITCH_ON IOID_10
#define PIN_SHUTDOWN_6994 IOID_11
#define PIN_ENABLE_V10 IOID_12
#define PIN_ENABLE_V05 IOID_13
#define PIN_TURNON_200R IOID_5
#define PIN_TURNON_10K IOID_6
/* I2C */
#ifdef ELITE_I2C
#define Board_I2C0_SCL0 IOID_7
#define Board_I2C0_SDA0 IOID_1
#endif
#define PIN_ENABLE_V05 IOID_14
// clang-format on
// from Elite IV-test branch
/* SPI Board */
#define Board_SPI0_MISO PIN_UNASSIGNED
#define Board_SPI0_MOSI IOID_1
#define Board_SPI0_CLK IOID_0
#define Board_SPI0_CS PIN_UNASSIGNED
#define Board_SPI1_MISO IOID_3
#define Board_SPI1_MOSI IOID_2
#define Board_SPI1_CLK IOID_4
#define Board_SPI1_CS PIN_UNASSIGNED
// End of Elite IV-test branch
#if defined(CC2650_LAUNCHXL)
#define PIN_LED_R IOID_6
#define PIN_LED_G IOID_7
@@ -45,9 +22,6 @@ static PIN_Config headstage_pin_configuration[] = { //
PIN_ADC_CS | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_DAC_CS | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_TURNON_200R | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_TURNON_10K | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_ENABLE_V10 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_ENABLE_V05 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
@@ -36,23 +36,14 @@ static SPI_Transaction headstage_spi_adc_transaction;
#define headstage_spi_open() \
do { \
SPI_init(); \
SPI_Params spi_parameter0; \
SPI_Params_init(&spi_parameter0); \
SPI_Params spi_parameter; \
SPI_Params_init(&spi_parameter); \
spi_parameter.transferMode = SPI_MODE_BLOCKING; \
spi_parameter.mode = SPI_MASTER; \
spi_parameter.bitRate = 2000; \
spi_parameter.dataSize = 16; \
spi_parameter.frameFormat = SPI_POL0_PHA1; \
headstage_spi_dac_handle = SPI_open(Board_SPI0, &spi_parameter0);\
SPI_Params spi_parameter1; \
SPI_Params_init(&spi_parameter1); \
spi_parameter.transferMode = SPI_MODE_BLOCKING; \
spi_parameter.mode = SPI_MASTER; \
spi_parameter.bitRate = 1000000; \
spi_parameter.bitRate = 12000000; \
spi_parameter.dataSize = 8; \
spi_parameter.frameFormat = SPI_POL0_PHA1; \
headstage_spi_dac_handle = SPI_open(Board_SPI1, &spi_parameter1);\
spi_parameter.frameFormat = SPI_POL0_PHA0; \
headstage_spi_dac_handle = SPI_open(Board_SPI0, &spi_parameter); \
} while (0)
#define headstage_dac_transaction() \
@@ -115,11 +115,11 @@
#ifndef FEATURE_OAD
// Minimum connection interval (units of 1.25ms, 80=100ms) if automatic
// parameter update request is enabled
#define DEFAULT_DESIRED_MIN_CONN_INTERVAL 6
#define DEFAULT_DESIRED_MIN_CONN_INTERVAL 80
// Maximum connection interval (units of 1.25ms, 800=1000ms) if automatic
// parameter update request is enabled
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 6
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 80
#else //! FEATURE_OAD
// Minimum connection interval (units of 1.25ms, 8=10ms) if automatic
// parameter update request is enabled
@@ -153,7 +153,7 @@
#define SBP_TASK_PRIORITY 1
#ifndef SBP_TASK_STACK_SIZE
#define SBP_TASK_STACK_SIZE 1024
#define SBP_TASK_STACK_SIZE 844
#endif
// Internal Events for RTOS application
@@ -221,7 +221,6 @@ static void SimpleBLEPeripheral_sendAttRsp(void);
static void SimpleBLEPeripheral_freeAttRsp(uint8_t status);
static void SimpleBLEPeripheral_stateChangeCB(gaprole_States_t newState);
static void SimpleBLEPeripheral_enqueueMsg(uint8_t event, uint8_t state);
static void headstage_data_length_extension();
#ifndef FEATURE_OAD_ONCHIP
static void SimpleBLEPeripheral_charValueChangeCB(uint8_t paramID);
@@ -409,11 +408,7 @@ static void SimpleBLEPeripheral_init(void) {
GATT_RegisterForMsgs(self);
HCI_LE_ReadMaxDataLenCmd();
HCI_LE_WriteSuggestedDefaultDataLenCmd(251, 2120); // this is used for data length extension
uint8_t prepare_write_req = 6;
GATTServApp_SetParameter(GATT_PARAM_NUM_PREPARE_WRITES, 1, &prepare_write_req);
}
#ifndef DEVICE_NAME
@@ -556,13 +551,13 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
// ICall_signal() function is called onto the semaphore.
ICall_Errno errno = ICall_wait(ICALL_TIMEOUT_FOREVER);
// headstage_watchdog_clear();
if (EVENT_MASK > 0) {
headstage_event_handle();
}
if (errno == ICALL_ERRNO_SUCCESS) {
ICall_EntityID dest;
ICall_ServiceEnum src;
ICall_HciExtEvt * message = NULL;
if (EVENT_MASK > 0) {
headstage_event_handle();
}
if (ICall_fetchServiceMsg(&src, &dest, (void **)&message) == ICALL_ERRNO_SUCCESS) {
uint8 safeToDealloc = TRUE;
@@ -825,14 +820,13 @@ static void SimpleBLEPeripheral_processStateChangeEvt(gaprole_States_t newState)
uint8_t numActive = 0;
numActive = linkDB_NumActive();
headstage_led_spi_color(COLOR_CYAN);
uint16_t cxnHandle;
uint16_t requestedPDUSize = 251;
uint16_t requestTxTime = 2120;
GAPRole_GetParameter(GAPROLE_CONNHANDLE, &cxnHandle);
if (SUCCESS != HCI_LE_SetDataLenCmd(cxnHandle, requestedPDUSize, requestTxTime)) {
if (SUCCESS == HCI_LE_SetDataLenCmd(cxnHandle, requestedPDUSize, requestTxTime)) {
headstage_led_spi_color(COLOR_CYAN);
}
// Use numActive to determine the connection handle of the last
// connection
@@ -854,7 +848,7 @@ static void SimpleBLEPeripheral_processStateChangeEvt(gaprole_States_t newState)
// Device just timed out from a connection but is not yet advertising, is in waiting period before advertising again
// disconnected
SimpleBLEPeripheral_freeAttRsp(bleNotConnected);
headstage_led_spi_color(COLOR_RED);
headstage_led_spi_color(COLOR_RED); /** for neulive1.3 call headstage_led_spi_color ; for neulive2.0 call headstage_led_color */
CONNECT_HANDLE = 0xFFFF;
flag_notify(EVT_DISCONNECTED);
break;