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258 Commits

Author SHA1 Message Date
weiting2 a82ad36975 SPI should be phase 1 2020-02-12 11:20:57 +08:00
weiting2 2320d5b757 mimic neu1.3_12/3 version 2020-02-11 11:43:41 +08:00
weiting2 db02c38a47 mimic neu1.3_12/3 version 2020-02-11 10:35:59 +08:00
weiting2 550b3c1158 mimic neu1.3_12/3 version 2020-02-10 17:15:01 +08:00
weiting2 d6070848b6 SBP_TASK_STACK_SIZE 1024 => 844
I am not sure what will happen
2020-02-10 16:40:57 +08:00
weiting2 0eecf13936 disable data length extension 2020-02-10 16:02:50 +08:00
yichin 4dd471961a error fix 2020-02-04 14:32:24 +08:00
weiting2 3021f65838 discard illegal channel data 2020-02-04 14:22:34 +08:00
weiting2 d355defa2d fix warning 2020-01-22 16:18:30 +08:00
weiting2 9f3f3335fc test mode using ch2 2020-01-22 16:16:11 +08:00
weiting2 0c5632fe30 3PIN SPI 2020-01-21 11:12:43 +08:00
weiting2 2a4924c5b2 4PIN SPI 2020-01-20 17:38:24 +08:00
weiting2 19ec8c4d6f 8bit spi without CS 2020-01-17 17:22:00 +08:00
weiting2 a232f2d795 8bit spi without CS 2020-01-17 17:11:21 +08:00
yichin 3090e2b4ea 8bit SPI 2020-01-17 14:55:56 +08:00
weiting2 162731f640 read spi_rxbuf 2020-01-17 10:25:32 +08:00
weiting2 8a63dd49c7 read spi_rxbuf 2020-01-17 10:16:28 +08:00
weiting2 e707c0a3d9 read spi_rxbuf 2020-01-17 10:10:59 +08:00
weiting2 83fb7687bb append notify in SPI callback 2020-01-16 18:08:28 +08:00
weiting2 55d6f5c565 append notify in SPI callback 2020-01-16 17:51:02 +08:00
weiting2 d5cd66f026 append notify in SPI callback 2020-01-16 17:14:25 +08:00
weiting2 9fd7987327 append notify in SPI callback 2020-01-16 17:11:04 +08:00
weiting2 6339640eb7 notify channel send correctly? 2020-01-16 17:03:53 +08:00
weiting2 dc7c3f8e99 notify channel send correctly? 2020-01-16 16:54:57 +08:00
weiting2 bd5c75d1b1 VIS_RST/INT will reset 2650 correctly 2020-01-16 12:33:39 +08:00
weiting2 fddf3535f3 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:49:19 +08:00
weiting2 d8b4221d81 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:40:16 +08:00
weiting2 c5af1e0959 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:34:31 +08:00
weiting2 4135a823e3 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:21:15 +08:00
weiting2 507c0cd439 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:03:31 +08:00
weiting2 cc54e95b30 VIS_RST/INT will reset 2650 correctly 2020-01-15 17:49:39 +08:00
yichin c084dfd67a error fix 2020-01-15 17:20:59 +08:00
weiting2 8c7424bf5b VIS_RST/INT will reset 2650 correctly 2020-01-15 17:19:15 +08:00
weiting2 235140c10b VIS_RST/INT will reset 2650 correctly 2020-01-15 16:47:59 +08:00
weiting2 6f9b279a82 VIS_RST/INT will reset 2650 correctly 2020-01-15 16:44:59 +08:00
weiting2 512bac4f80 VIS_RST/INT will reset 2650 correctly 2020-01-15 16:19:09 +08:00
weiting2 1353e192c2 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development
# Conflicts:
#	simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_neu.h
2020-01-14 17:19:03 +08:00
weiting2 f0eb5da80e check SPI MOSI channel 2020-01-14 17:18:12 +08:00
yichin f8fb36ca26 disable sti in test mode 2020-01-14 16:57:15 +08:00
weiting2 3c2970e36f check SPI MOSI channel 2020-01-14 16:02:19 +08:00
weiting2 f829c2af1a check SPI MOSI channel 2020-01-14 15:24:36 +08:00
weiting2 7710283346 check SPI MOSI channel 2020-01-14 14:22:19 +08:00
weiting2 1aac170954 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2020-01-14 13:57:38 +08:00
weiting2 f13df95710 check SPI MOSI channel 2020-01-14 11:21:21 +08:00
yichin e97ce556dd Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2020-01-14 10:32:48 +08:00
weiting2 504088b534 check SPI MOSI channel 2020-01-14 10:30:28 +08:00
yichin 06a6010cf3 test 2020-01-13 16:08:07 +08:00
yichin f006ef75d5 change amp vck (poly r pwm) 2020-01-10 15:30:21 +08:00
yichin c5f06cd076 change amp vck (poly r pwm) 2020-01-10 11:49:44 +08:00
yichin e2f2b88e80 commit 2020-01-09 16:46:02 +08:00
yichin 7cbe888f39 error fix 2020-01-09 12:38:55 +08:00
yichin 7121a12737 error fix 2020-01-07 16:10:17 +08:00
yichin 68e395a86c error fix 2020-01-07 15:07:00 +08:00
weiting2 48eb5f0196 test NEU 2.0 instruction 2020-01-07 15:00:09 +08:00
weiting2 5fdd0a1e07 test NEU 2.0 reset 2020-01-07 14:14:59 +08:00
weiting2 157676b29d test NEU 2.0 reset 2020-01-07 13:37:01 +08:00
weiting2 53ba84d5d3 test NEU 2.0 reset 2020-01-07 11:33:13 +08:00
weiting2 50da5a1876 test NEU 2.0 reset 2020-01-07 11:20:39 +08:00
weiting2 5e42dc0056 test NEU 2.0 reset 2020-01-07 11:03:30 +08:00
weiting2 5e53b7d651 test NEU 2.0 reset 2020-01-07 10:32:56 +08:00
weiting2 b129f2b7d4 test NEU 2.0 2020-01-06 18:53:34 +08:00
weiting2 5502099315 test NEU 2.0 2020-01-06 18:47:59 +08:00
weiting2 a3670d0e9a test NEU 2.0 2020-01-06 18:11:43 +08:00
yichin 6f8479770d Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2020-01-06 17:37:18 +08:00
weiting2 d89744b1c7 ADC clock & amp gain instruction 2020-01-06 17:36:34 +08:00
yichin 224475f342 error fix 2020-01-06 11:41:23 +08:00
yichin 7164b5f6c3 error fix 2020-01-06 11:39:20 +08:00
weiting2 0406cdea67 neu2.1 pin assign 2020-01-06 10:55:38 +08:00
weiting2 91787a5bb4 neu2.0 UI work well 2019-12-19 15:11:40 +08:00
weiting2 1c074fd180 notify should include device ID QQQQQ 2019-12-19 15:08:53 +08:00
weiting2 a5051dd42b notify should include device ID QQQQQ 2019-12-19 15:02:33 +08:00
weiting2 d1583ba5e1 notify should include device ID QQQQQ 2019-12-19 14:56:04 +08:00
weiting2 cc48dab88b notify should include device ID QQQQQ 2019-12-19 14:55:23 +08:00
weiting2 82383bbfcf Slow down notify speed. Check if memory board write correctly 2019-12-18 18:01:02 +08:00
weiting2 99a45314ae Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-18 16:45:33 +08:00
weiting2 17c501b855 Slow down notify speed. Check if memory board write correctly 2019-12-18 16:45:19 +08:00
yichin 1933ccbfe7 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-18 16:09:44 +08:00
weiting2 092b848c4d Slow down notify speed. Check if memory board write correctly 2019-12-18 16:08:50 +08:00
weiting2 8597e29a8a TODO: speed up ADC clock 2019-12-16 17:47:37 +08:00
weiting2 f3b8d74f82 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-13 14:31:54 +08:00
weiting2 4d3dee1c40 DBS clk_src = 4M, spi 400K 2019-12-13 14:31:23 +08:00
weiting2 ca70cba3bf DBS clk_src = 5M, spi 500K 2019-12-13 14:30:32 +08:00
weiting2 5ec4104255 DBS clk_src = 5M, spi 500K 2019-12-13 14:27:45 +08:00
weiting2 bb1ec23e02 DBS clk_src = 6M, spi 600K 2019-12-13 14:25:14 +08:00
weiting2 1615914ce4 DBS clk_src = 6M, spi 600K 2019-12-13 14:23:20 +08:00
weiting2 7b33bb5916 DBS clk_src = 4M, spi 4K 2019-12-13 14:20:56 +08:00
weiting2 0c22389b52 test pure SPI (receive DBS SPI only 2019-12-13 14:09:26 +08:00
weiting2 067281c449 test pure SPI (receive DBS SPI only 2019-12-13 11:57:49 +08:00
weiting2 74273f1469 test pure SPI (receive DBS SPI only 2019-12-13 11:21:53 +08:00
weiting2 07d606f5a9 test pure SPI (receive DBS SPI only 2019-12-13 11:17:18 +08:00
weiting2 aac9d26052 test pure SPI (receive DBS SPI only 2019-12-13 10:44:55 +08:00
weiting2 58c398e73f test pure SPI (receive DBS SPI only 2019-12-13 10:34:38 +08:00
weiting2 b81c5eb6ce test pure SPI (receive DBS SPI only 2019-12-13 09:49:18 +08:00
weiting2 e91089016e test pure SPI (receive DBS SPI only 2019-12-12 17:57:18 +08:00
weiting2 68f1cbf030 test pure SPI (receive DBS SPI only 2019-12-12 17:40:57 +08:00
weiting2 d73dccbefe test notify 2019-12-12 12:13:44 +08:00
weiting2 75f62f2a3e test notify 2019-12-12 12:04:00 +08:00
weiting2 a28b9ffd35 test notify 2019-12-12 10:38:49 +08:00
weiting2 bd6f745033 test notify 2019-12-12 09:55:27 +08:00
weiting2 54c6d2a217 test notify 2019-12-12 09:35:44 +08:00
weiting2 06bdc3aee4 test notify 2019-12-11 17:24:17 +08:00
weiting2 4c387980c8 test notify 2019-12-11 17:14:56 +08:00
YiChin 00ee10a94a Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 13:54:02 +08:00
weiting2 7a7aaf62a7 flush timestamp register before start PeriodicEvent 2019-12-11 13:53:05 +08:00
YiChin 62e24a2323 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 13:41:42 +08:00
weiting2 eb17de7490 test read data 2019-12-11 11:40:17 +08:00
YiChin aa336be8df Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 10:45:50 +08:00
weiting2 a06d1a1849 test read data 2019-12-11 10:45:18 +08:00
YiChin d153d91e71 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 10:38:15 +08:00
weiting2 8cb6594197 test read data 2019-12-11 10:37:46 +08:00
YiChin e44e6f511d Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 10:25:02 +08:00
weiting2 f440f56b3c test read data 2019-12-11 10:21:39 +08:00
weiting2 8968967ad1 test read data 2019-12-10 19:08:17 +08:00
YiChin 6abab9fe6b Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 17:45:00 +08:00
weiting2 cf481d482a test read data 2019-12-10 17:44:39 +08:00
YiChin 91b11fe3d9 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 17:29:24 +08:00
weiting2 96a44ad200 test read data 2019-12-10 17:29:00 +08:00
weiting2 b6fd48f9d9 test read data 2019-12-10 17:22:13 +08:00
weiting2 3d9c3f4e1e test read data 2019-12-10 11:48:54 +08:00
YiChin 05561a9959 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 11:43:24 +08:00
weiting2 fcd350c0d4 test read data 2019-12-10 11:42:02 +08:00
YiChin d07f8636dd Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 11:23:36 +08:00
weiting2 91315be16f test read data 2019-12-10 11:23:17 +08:00
weiting2 898bd81599 test read data 2019-12-10 11:06:16 +08:00
YiChin 8a92a1ba8b Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 10:47:59 +08:00
weiting2 7c83a01731 test read data 2019-12-10 10:47:37 +08:00
YiChin c05a76bd6d Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 10:36:49 +08:00
weiting2 425414dd2d test read data 2019-12-10 10:36:28 +08:00
YiChin 65c85aca40 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 10:27:25 +08:00
weiting2 1664a2cabd test read data 2019-12-10 10:27:03 +08:00
YiChin c207965207 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 10:02:50 +08:00
weiting2 7680879264 test read data 2019-12-10 10:00:38 +08:00
YiChin 031600d62a Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 18:32:47 +08:00
weiting2 0ce86bb4dd test read data 2019-12-09 18:32:26 +08:00
YiChin b848182595 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 18:05:35 +08:00
weiting2 54b48ef57d test read data 2019-12-09 18:04:37 +08:00
YiChin 03cbcdce49 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 16:35:44 +08:00
weiting2 52d51de3fd test read data 2019-12-09 16:35:19 +08:00
YiChin f65817e18c Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 16:27:22 +08:00
weiting2 6f6fffa84a test read data 2019-12-09 16:26:47 +08:00
YiChin fdb667ce8c Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 16:07:37 +08:00
weiting2 808c042c5a test read data 2019-12-09 16:07:06 +08:00
YiChin 09c1b3193d Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 15:52:50 +08:00
weiting2 c39b3d83f7 test read data 2019-12-09 15:52:27 +08:00
YiChin 1b72ead038 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development
# Conflicts:
#	simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_neu.h
2019-12-09 15:42:02 +08:00
weiting2 68645bab82 test read data 2019-12-09 15:41:26 +08:00
YiChin 21e366b601 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 15:13:22 +08:00
weiting2 e129608ad0 test read data 2019-12-09 15:13:00 +08:00
YiChin 4aadcbdefe Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 11:44:03 +08:00
weiting2 bcf3442aa5 test read data 2019-12-09 11:43:19 +08:00
YiChin 8b34a9b39f Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 16:29:51 +08:00
weiting2 ce70363247 test read data 2019-12-06 16:29:32 +08:00
YiChin 0143d16b48 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 16:25:48 +08:00
weiting2 b8c00d825e test read data 2019-12-06 16:25:27 +08:00
YiChin d0ecad7862 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 15:22:25 +08:00
weiting2 d16038974c test read data 2019-12-06 15:21:51 +08:00
YiChin dd9198c548 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 14:55:56 +08:00
weiting2 371c6b1f83 test read data 2019-12-06 14:55:34 +08:00
YiChin 877642fe15 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 14:27:41 +08:00
weiting2 c7d5dc7330 test read data 2019-12-06 14:27:10 +08:00
YiChin 40a0025ffc Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 14:07:52 +08:00
weiting2 528649f909 test read data 2019-12-06 14:07:28 +08:00
YiChin 83c19f1e93 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 13:54:15 +08:00
weiting2 57ec1ad0c6 test read data 2019-12-06 13:53:47 +08:00
YiChin 555bd907fb Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 13:33:46 +08:00
weiting2 695cac4cf0 test read data 2019-12-06 13:33:09 +08:00
YiChin cf4f4627c9 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 12:25:50 +08:00
weiting2 b74451a18a test read data 2019-12-06 12:23:39 +08:00
YiChin 61be6c01fc test recording notify 2019-12-04 16:34:26 +08:00
weiting2 c1f8e263d4 test recording 2019-12-04 16:32:29 +08:00
weiting2 fe19490b23 test recording 2019-12-04 15:34:42 +08:00
YiChin e49efd8798 RIS has au unknown error 2019-12-04 15:34:08 +08:00
YiChin d1c70811b4 RIS has au unknown error 2019-12-04 14:25:06 +08:00
weiting2 03667cb36c test recording 2019-12-04 14:08:36 +08:00
weiting2 c1a2b184f6 add t1~t5 ins 2019-12-03 12:55:01 +08:00
weiting2 3f831ff84c check instruction 2019-11-29 18:31:00 +08:00
weiting2 d8c61db417 check instruction 2019-11-29 13:59:09 +08:00
weiting2 dacf0d1055 check INSTRUCTION and RIS 2019-11-28 18:30:36 +08:00
weiting2 cfc68885c8 check INSTRUCTION and RIS 2019-11-28 17:59:11 +08:00
weiting2 b841454957 [IV] default output Volt is Vin instead of Vout 2019-11-27 10:25:27 +08:00
weiting2 882b5efbd0 [Neu 2.0] give up read and send MOSI 2019-11-26 14:46:35 +08:00
weiting2 5c33c0130a [Neu 2.0] attempt to read and send MOSI 2019-11-26 14:33:56 +08:00
weiting2 46d0c4b09e [Neu 2.0] attempt to read and send MOSI 2019-11-26 14:32:08 +08:00
weiting2 48924b400b [Neu 2.0] attempt to read and send MOSI 2019-11-26 14:07:06 +08:00
weiting2 1b6aeb1f70 [Neu 2.0] attempt to read and send MOSI 2019-11-26 13:31:22 +08:00
weiting2 3fc364134a [Neu 2.0] attempt to read and send MOSI 2019-11-26 11:55:35 +08:00
weiting2 fa522254f3 [Neu 2.0] attempt to read and send MOSI 2019-11-26 11:47:52 +08:00
YiChin 8c41b0a976 read spi 2019-11-26 11:44:04 +08:00
weiting2 cf7d0616ad [Neu 2.0] attempt to read and send MOSI 2019-11-26 11:20:06 +08:00
weiting2 25d7722d93 [Neu 2.0] attempt to read and send MOSI 2019-11-26 11:16:55 +08:00
weiting2 336b325f03 [Neu 2.0] SPI callback flush SPI twice 2019-11-26 10:58:49 +08:00
weiting2 246f871ba7 [Neu 2.0] SPI callback flush SPI twice 2019-11-26 10:52:51 +08:00
weiting2 96b61d364e [Neu 2.0] SPI callback using a switch 2019-11-26 10:26:12 +08:00
weiting2 eba70d4af7 Neulive 2.0 test SPI conti trans speed 2019-11-25 18:44:04 +08:00
weiting2 b24a275019 Neulive 2.0 test SPI conti trans speed 2019-11-25 18:37:38 +08:00
weiting2 7621490d13 Neulive 2.0 fix instruction bug 2019-11-25 12:36:59 +08:00
weiting2 eb17cda0dc Neulive 2.0 comment UART 2019-11-25 11:59:42 +08:00
weiting2 cd1bc37e62 Neulive 2.0 add cb func 2019-11-25 11:43:05 +08:00
weiting2 c151eb1fab Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 18:12:45 +08:00
weiting2 4782c604c5 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 17:53:55 +08:00
weiting2 de908817c4 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 17:51:58 +08:00
YiChin e853241537 add pin define macro for 2.0 2019-11-22 17:33:00 +08:00
YiChin 097c475e5f comment R/G LED 2019-11-22 17:27:35 +08:00
YiChin 3e64d122de Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development
# Conflicts:
#	simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_neu.h
2019-11-22 17:26:18 +08:00
YiChin 466a6627ef comment R/G LED 2019-11-22 17:24:59 +08:00
weiting2 c08ea10397 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 16:52:32 +08:00
weiting2 500b9b00fd Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 16:45:30 +08:00
weiting2 b06bba4333 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 14:39:14 +08:00
weiting2 0eeb973e15 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 14:27:34 +08:00
weiting2 46f797f083 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 14:23:13 +08:00
weiting2 d24cde42b5 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 13:26:49 +08:00
weiting2 19bc7d23db Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 12:29:30 +08:00
weiting2 3849a25e7f Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 12:21:09 +08:00
weiting2 4c760ac644 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 11:25:50 +08:00
weiting2 ba990ce65f Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 10:16:53 +08:00
weiting2 0ef19c37dc Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 18:20:44 +08:00
weiting2 469c06390a Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 14:51:47 +08:00
weiting2 f09e440b45 Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 14:45:29 +08:00
weiting2 4e82451108 Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 14:39:10 +08:00
weiting2 d21613cee8 Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 13:32:47 +08:00
weiting2 b8308303fc Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 13:32:26 +08:00
weiting2 80f9d63a09 Neulive 2.0 lauchpad SPI test 2019-11-20 13:09:56 +08:00
yichin 81945184d1 data rate test for memory board 2019-11-18 13:44:13 +08:00
yichin 955c3a2e7c json parameter table renew and modification 2019-09-23 20:12:21 +08:00
yichin 664b6e56b9 framework modified 2019-09-20 19:20:13 +08:00
yichin f94e4375f3 neulive 2.0 structure modify 2019-09-19 20:49:25 +08:00
yichin 1cf1c01163 for neulive 2.0 test 2019-09-18 21:03:52 +08:00
yichin 0cd2fe0528 neulive2.0 modified 2019-09-17 20:34:09 +08:00
yichin fb34754e1f debug neulive 2.0 2019-09-17 15:29:17 +08:00
yichin 20d5804a87 neulive2.0 debug 2019-09-17 11:22:50 +08:00
yichin 5851dc9707 some bugs with system clock 2019-09-10 20:38:55 +08:00
yichin 7cc337c0fd begin to debug 2019-09-10 10:05:30 +08:00
yichin 09685951c3 check sti firmware done 2019-09-09 20:52:20 +08:00
yichin 720f6d3548 add device information 2019-09-09 16:36:30 +08:00
yichin 1393d568a0 build pass 2019-09-09 15:54:37 +08:00
YiChin2018 92b6a3a4f2 add build instruction 2019-09-06 22:09:15 +08:00
YiChin2018 becdca9dc7 add build instruction 2019-09-06 18:26:05 +08:00
YiChin2018 dc3cce9990 add build instruction 2019-09-05 20:25:48 +08:00
YiChin2018 f8d7296f76 develop 2.0 firmware 2019-09-04 21:57:53 +08:00
YiChin2018 615eba69bd develop 2.0 firmware 2019-09-04 11:18:09 +08:00
YiChin2018 aab6d49812 develop 2.0 firmware 2019-09-01 10:57:36 +08:00
YiChin2018 9bfef795e7 develop 2.0 firmware 2019-08-30 18:32:08 +08:00
YiChin2018 428808715a develop 2.0 firmware 2019-08-30 17:51:10 +08:00
YiChin2018 7dfc856318 develop 2.0 firmware 2019-08-30 11:12:10 +08:00
YiChin2018 c87fb49656 temporary version of neulive 1.2 / 1.3
porting to neulive 2.0
2019-08-29 18:00:31 +08:00
YiChin2018 df21b2021a temporary version of neulive 1.2 / 1.3
porting to neulive 2.0
2019-08-29 17:53:06 +08:00
YiChin2018 6cb386e578 temporary version of neulive 1.2 / 1.3
porting to neulive 2.0
2019-08-29 17:02:33 +08:00
YiChin2018 bd7c73f2a5 add software interrupt and documentations 2019-08-29 09:27:13 +08:00
YiChin2018 ea21075a1d add software interrupt and documentations 2019-08-28 20:08:57 +08:00
YiChin2018 71a5d93a21 add software interrupt and documentations 2019-08-28 19:57:18 +08:00
YiChin2018 c461f71cf2 add software interrupt 2019-08-27 18:14:27 +08:00
YiChin2018 9ce8ea1400 prepare to add hwi to implement our system 2019-08-26 11:54:41 +08:00
YiChin2018 b181d9273b configure file modify and add hareware interrupt 2019-08-23 19:02:27 +08:00
YiChin2018 069881f5c4 interrupt do the same thing 2019-08-23 13:43:46 +08:00
YiChin2018 ce61501d43 interrupt with bugs 2019-08-22 19:11:34 +08:00
YiChin2018 386f2940ad interrupt with bugs 2019-08-21 19:24:27 +08:00
YiChin2018 1965f6e182 there are some bugs need to be fixed 2019-08-21 10:56:20 +08:00
YiChin2018 f699ecdae9 format 2019-08-20 13:27:47 +08:00
47 changed files with 5665 additions and 539 deletions
+1
View File
@@ -3,6 +3,7 @@
# CSS package
xdctools_*/
ccsv8/
simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/app/.config/
# CSS build files
FlashROM/
+2 -2
View File
@@ -33,8 +33,8 @@ NEULIVE_PARAMETER = {
'AG': 5, # AMP GAIN
'PW': 0, # PULSE WIDTH
'TT': 9, # STIMULATION TIMES
'SB': 3, # STIMULATION BEHAVIOR
'TF': 10, # STIMULATION FREQUENCY
'SB': 2, # STIMULATION BEHAVIOR
'TF': 1, # STIMULATION FREQUENCY
'CA': 1, # AMP CHANNEL A ENABLE
'CB': 0, # AMP CHANNEL B ENABLE
'CC': 0, # AMP CHANNEL C ENABLE
@@ -335,7 +335,7 @@ def paint_fft_result(result: Result, options: Options):
plt.figure(1)
f1, pxx_den = signal.periodogram(value_seq, 1e3)
plt.semilogy(f1, pxx_den)
plt.ylim([1e-7, 1e3])
plt.ylim([1e-7, 1e7])
plt.xlabel('frequency [hz]')
plt.ylabel('PSD[v**2/Hz')
@@ -9,6 +9,6 @@
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<rts value="libc.a"/>
<createSlaveProjects value=""/>
<connection value="common/targetdb/connections/TIXDS100v3_Dot7_Connection.xml"/>
<connection value="common/targetdb/connections/TIXDS110_Connection.xml"/>
<isTargetManual value="false"/>
</projectOptions>
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@@ -12,7 +12,7 @@
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<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS110 USB Debug Probe/Cortex_M3_0" value="C:/ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\FlashROM\simple_peripheral_cc2650em_app.out"/>
<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS110 USB Debug Probe_0/Cortex_M3_0" value="C:/ti\ccsv8\ccs_base\emulation\gel\images\cc26xx\cc26x0_rtos_rom_syms.out"/>
<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS110 USB Debug Probe_0/Cortex_M3_0" value="C:/ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\FlashROM\simple_peripheral_cc2650em_app.out"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/simple_peripheral_cc2650em_app"/>
</listAttribute>
@@ -1,19 +1,20 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
<instance XML_version="1.2" desc="Texas Instruments XDS100v3 USB Debug Probe_0" href="connections/TIXDS100v3_Dot7_Connection.xml" id="Texas Instruments XDS100v3 USB Debug Probe_0" xml="TIXDS100v3_Dot7_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
<instance XML_version="1.2" href="drivers/tixds100v2icepick_c.xml" id="drivers" xml="tixds100v2icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cs_dap.xml" id="drivers" xml="tixds100v2cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cortexM.xml" id="drivers" xml="tixds100v2cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="2" id="The Converter Usage">
<choice Name="Generate 1149.7 2-pin advanced modes" value="enable">
<property Type="choicelist" Value="1" id="The Converter 1149.7 Frequency">
<choice Name="Overclock with user specified value" value="unused">
<property Type="choicelist" Value="5" id="-- Choose a value from 1.0MHz to 50.0MHz"/>
</choice>
</property>
<property Type="choicelist" Value="5" id="The Target Scan Format"/>
<configuration XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe_0" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe_0" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="1" id="Power Selection">
<choice Name="Probe supplied power" value="1">
<property Type="stringfield" Value="3.3" id="Voltage Level"/>
</choice>
</property>
<property Type="choicelist" Value="0" id="JTAG Signal Isolation"/>
<property Type="choicelist" Value="4" id="SWD Mode Settings">
<choice Name="cJTAG (1149.7) 2-pin advanced modes" value="enable">
<property Type="choicelist" Value="1" id="XDS110 Aux Port"/>
</choice>
</property>
<platform XML_version="1.2" id="platform_0">
@@ -16,11 +16,11 @@ BIOS_INC = -I"C:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/pa
TARGET_INC = -I"C:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/packages/"
INCS = $(BIOS_INC) $(TARGET_INC) --include_path="C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/include" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/icall/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/roles/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/roles" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/dev_info" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/simple_profile/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/simple_profile" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/common/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/heapmgr" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/controller/cc26xx/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/target/_common" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/target" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/target/_common/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/osal/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/services/src/sdata" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/services/src/saddr" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/icall/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/rom" --include_path="C:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/cc26xxware_2_24_03_17272" -IC:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/packages/
INCS = $(BIOS_INC) $(TARGET_INC) --include_path="C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/include" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/icall/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/roles/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/roles" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/dev_info" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/simple_profile/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/simple_profile" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/common/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/heapmgr" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/controller/cc26xx/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/target/_common" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/target" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/target/_common/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/osal/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/services/src/sdata" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/services/src/saddr" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/icall/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/rom" --include_path="C:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/cc26xxware_2_24_03_17272" -IC:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/packages/
CC = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/include
ASM = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/include
AR = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/bin/armar rq
CC = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/include
ASM = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/include
AR = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/bin/armar rq
DEL = C:/ti/xdctools_3_32_02_25_core/packages/../bin/rm -f
CP = C:/ti/xdctools_3_32_02_25_core/packages/../bin/cp -f
@@ -9,6 +9,6 @@
<linkerCommandFile value="cc26x0f128.cmd"/>
<rts value="libc.a"/>
<createSlaveProjects value=""/>
<connection value="common/targetdb/connections/TIXDS100v3_Dot7_Connection.xml"/>
<connection value="common/targetdb/connections/TIXDS110_Connection.xml"/>
<isTargetManual value="false"/>
</projectOptions>
@@ -14,130 +14,246 @@
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.TMS470.Default.1209999684" name="FlashROM" parent="com.ti.ccstudio.buildDefinitions.TMS470.Default" postannouncebuildStep="" postbuildStep="${CG_TOOL_HEX} -order MS --memwidth=8 --romwidth=8 --intel -o ${ProjName}.hex ${ProjName}.out;${TOOLS_BLE}/frontier/frontier.exe ccs ${PROJECT_LOC}/${ConfigName}/${ProjName}_linkInfo.xml ${ORG_PROJ_DIR}/../../ccs/config/ccs_compiler_defines.bcfg ${ORG_PROJ_DIR}/../../ccs/config/ccs_linker_defines.cmd" preannouncebuildStep="" prebuildStep="&quot;${TOOLS_BLE}/lib_search/lib_search.exe&quot; ${ORG_PROJ_DIR}/build_config.opt &quot;${TOOLS_BLE}/lib_search/params_split_cc2640.xml&quot; ${SRC_BLE_CORE}/../blelib &quot;${ORG_PROJ_DIR}/../../ccs/config/lib_linker.cmd&quot;">
<folderInfo id="com.ti.ccstudio.buildDefinitions.TMS470.Default.1209999684." name="/" resourcePath="">
<toolChain id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.exe.DebugToolchain.929750171" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.TMS470_18.1.exe.linkerDebug.1008890994">
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1479696404" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=Cortex M.CC2650F128"/>
<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
<listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.5.0"/>
<listOptionValue builtIn="false" value="LINK_ORDER=TOOLS/ccs_linker_defines.cmd;TOOLS/cc26xx_ble_stack.cmd;"/>
<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.201372544" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="18.1.4.LTS" valueType="string"/>
<targetPlatform id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.exe.targetPlatformDebug.1951196199" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.exe.targetPlatformDebug"/>
<builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.exe.builderDebug.20903631" keepEnvironmentInBuildfile="false" name="GNU Make" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.exe.builderDebug"/>
<tool id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.exe.compilerDebug.1176131016" name="ARM Compiler" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.exe.compilerDebug">
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<option id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.CODE_STATE.1443871767" name="Designate code state, 16-bit (thumb) or 32-bit (--code_state)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.CODE_STATE" value="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.CODE_STATE.16" valueType="enumerated"/>
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<option id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.LITTLE_ENDIAN.784155377" name="Little endian code [See 'General' page to edit] (--little_endian, -me)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.LITTLE_ENDIAN" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.OPT_LEVEL.494285153" name="Optimization level (--opt_level, -O)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.OPT_LEVEL" value="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.OPT_LEVEL.4" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.OPT_FOR_SPEED.581550859" name="Speed vs. size trade-offs (--opt_for_speed, -mf)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.OPT_FOR_SPEED" value="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.OPT_FOR_SPEED.0" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.INCLUDE_PATH.1288777730" name="Add dir to #include search path (--include_path, -I)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.1.compilerID.INCLUDE_PATH" valueType="includePath">
<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
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<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
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<listOptionValue builtIn="false" value="${SRC_COMMON}/services/src/aes/cc26xx"/>
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@@ -12,6 +12,7 @@
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<listEntry value="/simple_peripheral_cc2650em_stack"/>
</listAttribute>
@@ -1,19 +1,20 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
<instance XML_version="1.2" desc="Texas Instruments XDS100v3 USB Debug Probe_0" href="connections/TIXDS100v3_Dot7_Connection.xml" id="Texas Instruments XDS100v3 USB Debug Probe_0" xml="TIXDS100v3_Dot7_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
<instance XML_version="1.2" href="drivers/tixds100v2icepick_c.xml" id="drivers" xml="tixds100v2icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cs_dap.xml" id="drivers" xml="tixds100v2cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cortexM.xml" id="drivers" xml="tixds100v2cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="2" id="The Converter Usage">
<choice Name="Generate 1149.7 2-pin advanced modes" value="enable">
<property Type="choicelist" Value="1" id="The Converter 1149.7 Frequency">
<choice Name="Overclock with user specified value" value="unused">
<property Type="choicelist" Value="5" id="-- Choose a value from 1.0MHz to 50.0MHz"/>
</choice>
</property>
<property Type="choicelist" Value="5" id="The Target Scan Format"/>
<configuration XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe_0" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe_0" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="1" id="Power Selection">
<choice Name="Probe supplied power" value="1">
<property Type="stringfield" Value="3.3" id="Voltage Level"/>
</choice>
</property>
<property Type="choicelist" Value="0" id="JTAG Signal Isolation"/>
<property Type="choicelist" Value="4" id="SWD Mode Settings">
<choice Name="cJTAG (1149.7) 2-pin advanced modes" value="enable">
<property Type="choicelist" Value="1" id="XDS110 Aux Port"/>
</choice>
</property>
<platform XML_version="1.2" id="platform_0">
@@ -116,46 +116,46 @@ const PowerCC26XX_Config PowerCC26XX_config = {
* ============================= UART begin ===================================
*/
/* Place into subsections to allow the TI linker to remove items properly */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(UART_config, ".const:UART_config")
#pragma DATA_SECTION(uartCC26XXHWAttrs, ".const:uartCC26XXHWAttrs")
#endif
/* Include drivers */
#include <ti/drivers/UART.h>
#include <ti/drivers/uart/UARTCC26XX.h>
/* UART objects */
UARTCC26XX_Object uartCC26XXObjects[BOOSTXL_CC2650MA_UARTCOUNT];
/* UART hardware parameter structure, also used to assign UART pins */
const UARTCC26XX_HWAttrsV2 uartCC26XXHWAttrs[BOOSTXL_CC2650MA_UARTCOUNT] = {
//
{
.baseAddr = UART0_BASE,
.powerMngrId = PowerCC26XX_PERIPH_UART0,
.intNum = INT_UART0_COMB,
.intPriority = ~0,
.swiPriority = 0,
.txPin = Board_UART_TX,
.rxPin = Board_UART_RX,
.ctsPin = PIN_UNASSIGNED,
.rtsPin = PIN_UNASSIGNED
//
}
//
};
/* UART configuration structure */
const UART_Config UART_config[] = { //
{
//
.fxnTablePtr = &UARTCC26XX_fxnTable,
.object = &uartCC26XXObjects[0],
.hwAttrs = &uartCC26XXHWAttrs[0]
//
},
{NULL, NULL, NULL}};
//#if defined(__TI_COMPILER_VERSION__)
//#pragma DATA_SECTION(UART_config, ".const:UART_config")
//#pragma DATA_SECTION(uartCC26XXHWAttrs, ".const:uartCC26XXHWAttrs")
//#endif
//
///* Include drivers */
//#include <ti/drivers/UART.h>
//#include <ti/drivers/uart/UARTCC26XX.h>
//
///* UART objects */
//UARTCC26XX_Object uartCC26XXObjects[BOOSTXL_CC2650MA_UARTCOUNT];
//
///* UART hardware parameter structure, also used to assign UART pins */
//const UARTCC26XX_HWAttrsV2 uartCC26XXHWAttrs[BOOSTXL_CC2650MA_UARTCOUNT] = {
// //
// {
// .baseAddr = UART0_BASE,
// .powerMngrId = PowerCC26XX_PERIPH_UART0,
// .intNum = INT_UART0_COMB,
// .intPriority = ~0,
// .swiPriority = 0,
// .txPin = Board_UART_TX,
// .rxPin = Board_UART_RX,
// .ctsPin = PIN_UNASSIGNED,
// .rtsPin = PIN_UNASSIGNED
// //
// }
// //
//};
//
///* UART configuration structure */
//const UART_Config UART_config[] = { //
// {
// //
// .fxnTablePtr = &UARTCC26XX_fxnTable,
// .object = &uartCC26XXObjects[0],
// .hwAttrs = &uartCC26XXHWAttrs[0]
// //
// },
// {NULL, NULL, NULL}};
/*
* ============================= UART end =====================================
*/
@@ -233,7 +233,7 @@ const SPICC26XXDMA_HWAttrsV1 spiCC26XXDMAHWAttrs[BOOSTXL_CC2650MA_SPICOUNT] = {
.mosiPin = Board_SPI0_MOSI,
.misoPin = Board_SPI0_MISO,
.clkPin = Board_SPI0_CLK,
.csnPin = Board_SPI0_CS
.csnPin = Board_SPI0_CSN
//
},
#ifdef HEADSTAGE_MA_USE_SPI2
@@ -250,7 +250,7 @@ const SPICC26XXDMA_HWAttrsV1 spiCC26XXDMAHWAttrs[BOOSTXL_CC2650MA_SPICOUNT] = {
.mosiPin = Board_SPI1_MOSI,
.misoPin = Board_SPI1_MISO,
.clkPin = Board_SPI1_CLK,
.csnPin = Board_SPI1_CS //
.csnPin = Board_SPI1_CSN //
},
#endif
};
@@ -51,6 +51,12 @@ extern "C" {
#include <ti/drivers/PIN.h>
#include <driverlib/ioc.h>
#define HEADSTAGE_UNI_2_0
#ifdef HEADSTAGE_UNI_2_0
#include "neu/headstage_pin.h"
#else
#include "uni/headstage_pin.h"
#endif
/** ============================================================================
* Externs
* ==========================================================================*/
@@ -144,36 +150,36 @@ extern const PIN_Config BoardGpioInitTable[];
#define Board_UART_TX Board_BP_UART_Rx /* RXD */
#define Board_UART_RX Board_BP_UART_Tx /* TXD */
/*
* SPI0 is LSK interface
*/
#define Board_SPI0_MISO PIN_UNASSIGNED
#define Board_SPI0_MOSI IOID_0
#define Board_SPI0_CLK IOID_1
#define Board_SPI0_CS IOID_3
/*
* SPI1 is ASK interface
*/
#define Board_SPI1_MISO PIN_UNASSIGNED
#define Board_SPI1_MOSI IOID_13
#define Board_SPI1_CLK PIN_UNASSIGNED
#define Board_SPI1_CS IOID_4
/* Power Management Board */
#define Board_SRDY Board_BP_Pin_J2_19
#define Board_MRDY Board_BP_Pin_J1_2
/* PWM outputs */
#define Board_PWMPIN0 IOID_6
#define Board_PWMPIN1 PIN_UNASSIGNED
#define Board_PWMPIN2 IOID_8
#define Board_PWMPIN3 PIN_UNASSIGNED
#define Board_PWMPIN4 PIN_UNASSIGNED
#define Board_PWMPIN5 PIN_UNASSIGNED
#define Board_PWMPIN6 PIN_UNASSIGNED
#define Board_PWMPIN7 PIN_UNASSIGNED
///*
// * SPI0 interface with DBS chip 2.0
// */
//#define Board_SPI0_MISO PIN_UNASSIGNED
//#define Board_SPI0_MOSI PIN_UNASSIGNED
//#define Board_SPI0_CLK PIN_UNASSIGNED
//#define Board_SPI0_CS PIN_UNASSIGNED
//
///*
// * SPI1 interface work with LED
// */
//
//#define Board_SPI1_MISO PIN_UNASSIGNED
//#define Board_SPI1_MOSI PIN_UNASSIGNED
//#define Board_SPI1_CLK PIN_UNASSIGNED
//#define Board_SPI1_CS PIN_UNASSIGNED
//
///* Power Management Board */
//#define Board_SRDY Board_BP_Pin_J2_19
//#define Board_MRDY Board_BP_Pin_J1_2
//
///* PWM outputs */
//#define Board_PWMPIN0 PIN_UNASSIGNED
//#define Board_PWMPIN1 PIN_UNASSIGNED
//#define Board_PWMPIN2 PIN_UNASSIGNED
//#define Board_PWMPIN3 PIN_UNASSIGNED
//#define Board_PWMPIN4 PIN_UNASSIGNED
//#define Board_PWMPIN5 PIN_UNASSIGNED
//#define Board_PWMPIN6 PIN_UNASSIGNED
//#define Board_PWMPIN7 PIN_UNASSIGNED
/** ============================================================================
@@ -51,6 +51,8 @@ extern "C" {
#include <ti/drivers/PIN.h>
#include <driverlib/ioc.h>
#include "neu/headstage_pin.h"
/** ============================================================================
* Externs
* ==========================================================================*/
@@ -68,34 +70,34 @@ extern const PIN_Config BoardGpioInitTable[];
*/
/* Discrete outputs */
#define Board_RLED IOID_6
#define Board_GLED IOID_7
#define Board_RLED PIN_UNASSIGNED
#define Board_GLED PIN_UNASSIGNED
#define Board_LED_ON 1
#define Board_LED_OFF 0
/* Discrete inputs */
#define Board_BTN1 IOID_13
#define Board_BTN2 IOID_14
#define Board_BTN1 PIN_UNASSIGNED
#define Board_BTN2 PIN_UNASSIGNED
/* UART Board */
#define Board_UART_RX IOID_1 /* RXD */
#define Board_UART_TX IOID_2 /* TXD */
#define Board_UART_RX PIN_UNASSIGNED /* RXD */
#define Board_UART_TX PIN_UNASSIGNED /* TXD */
#define Board_UART_CTS PIN_UNASSIGNED /* CTS */
#define Board_UART_RTS PIN_UNASSIGNED /* RTS */
/* SPI Board */
#define Board_SPI0_MISO PIN_UNASSIGNED /* RF1.20 */
#define Board_SPI0_MOSI IOID_12 /* RF1.18 */
#define Board_SPI0_CLK PIN_UNASSIGNED /* RF1.16 */
#define Board_SPI0_CSN IOID_4
#define Board_SPI1_MISO PIN_UNASSIGNED
#define Board_SPI1_MOSI IOID_10
#define Board_SPI1_CLK IOID_9
#define Board_SPI1_CSN IOID_3
//#define Board_SPI0_MISO PIN_UNASSIGNED /* RF1.20 */
//#define Board_SPI0_MOSI PIN_UNASSIGNED /* RF1.18 */
//#define Board_SPI0_CLK PIN_UNASSIGNED /* RF1.16 */
//#define Board_SPI0_CSN PIN_UNASSIGNED
//#define Board_SPI1_MISO PIN_UNASSIGNED
//#define Board_SPI1_MOSI PIN_UNASSIGNED
//#define Board_SPI1_CLK PIN_UNASSIGNED
//#define Board_SPI1_CSN PIN_UNASSIGNED
/* I2C */
#define Board_I2C0_SCL0 IOID_4
#define Board_I2C0_SDA0 IOID_5
#define Board_I2C0_SCL0 PIN_UNASSIGNED
#define Board_I2C0_SDA0 PIN_UNASSIGNED
/* SPI */
#define Board_SPI_FLASH_CS IOID_20
@@ -123,21 +125,21 @@ extern const PIN_Config BoardGpioInitTable[];
/* Booster pack LCD (430BOOST - Sharp96 Rev 1.1) */
#define Board_LCD_CS IOID_24 // SPI chip select
#define Board_LCD_EXTCOMIN IOID_12 // External COM inversion
#define Board_LCD_EXTCOMIN PIN_UNASSIGNED // External COM inversion
#define Board_LCD_ENABLE IOID_22 // LCD enable
#define Board_LCD_POWER IOID_23 // LCD power control
#define Board_LCD_CS_ON 1
#define Board_LCD_CS_OFF 0
/* PWM outputs */
#define Board_PWMPIN0 Board_RLED
#define Board_PWMPIN1 Board_GLED
#define Board_PWMPIN2 IOID_5
#define Board_PWMPIN3 IOID_11
#define Board_PWMPIN4 PIN_UNASSIGNED
#define Board_PWMPIN5 PIN_UNASSIGNED
#define Board_PWMPIN6 PIN_UNASSIGNED
#define Board_PWMPIN7 PIN_UNASSIGNED
//#define Board_PWMPIN0 PIN_UNASSIGNED
//#define Board_PWMPIN1 PIN_UNASSIGNED
//#define Board_PWMPIN2 PIN_UNASSIGNED
//#define Board_PWMPIN3 PIN_UNASSIGNED
//#define Board_PWMPIN4 PIN_UNASSIGNED
//#define Board_PWMPIN5 PIN_UNASSIGNED
//#define Board_PWMPIN6 PIN_UNASSIGNED
//#define Board_PWMPIN7 PIN_UNASSIGNED
/** ============================================================================
* Instance identifiers
@@ -205,6 +205,7 @@ Error.maxDepth = 2;
/* ================ Hwi configuration ================ */
var halHwi = xdc.useModule('ti.sysbios.hal.Hwi');
var m3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
/*
* Checks for Hwi (system) stack overruns while in the Idle loop.
*
@@ -218,6 +219,7 @@ var m3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
*/
//halHwi.checkStackFlag = true;
halHwi.checkStackFlag = false;
//C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\.config\xconfig_app_ble
/*
* The following options alter the system's behavior when a hardware exception
@@ -287,6 +287,11 @@ static uint8_t CHIP_ID = 0;
*/
static uint16_t CONNECT_HANDLE = 0;
/**
* command instruction buffer
*/
static uint8_t cdr_buf[BLE_CDR_BUFF_SIZE] = {0};
/*====================
==== event table ====
====================*/
@@ -311,7 +316,7 @@ typedef struct {
==== device implement implement header ====
=========================================*/
#include "headstage_uni.h"
#include "headstage_neu.h"
/*======================
==== main function ====
@@ -329,6 +334,9 @@ static EventTableEntry EVENT_TABLE[] = { //
#endif
#ifdef HEADSTAGE_STI_H
{EVT_ALL, &headstage_sti_event},
#endif
#ifdef HEADSTAGE_NEU_H
{EVT_ALL, &headstage_neu_event},
#endif
// terminated
{0, NULL}};
@@ -352,8 +360,6 @@ static void headstage_event_handle() {
* system handle for instruction input.
*/
static void headstage_update_instruction(uint8_t *instruction) {
static uint8_t cdr_buf[BLE_CDR_BUFF_SIZE] = {0};
uint8_t ins_type = instruction[0] & 0xF0;
CHIP_ID = instruction[0] & 0x0F;
uint8_t ins_oper = instruction[1] & 0xF0;
@@ -369,45 +375,8 @@ static void headstage_update_instruction(uint8_t *instruction) {
break;
}
case INS_TYPE_CIS: {
switch (ins_oper) {
case CIS_NOP: {
// nothing
cdr_buf[0] = _B_4b4b(CIS_NOP, CHIP_ID);
cdr_buf[1] = _B_4b4b(CDR_SUCCESS, 0);
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, 2, cdr_buf);
break;
}
#ifdef HEADSTAGE_CIS_VOLT_H
case CIS_VOLT: {
uint8_t status = headstage_update_vis_volt(ins_len, instruction + 2, cdr_buf + 2);
cdr_buf[0] = _B_4b4b(CIS_VOLT, CHIP_ID);
cdr_buf[1] = status;
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
#endif
#ifdef HEADSTAGE_CIS_LED_H
case CIS_LED: {
uint8_t status = headstage_update_vis_led(ins_len, instruction + 2, cdr_buf + 2);
cdr_buf[0] = _B_4b4b(CIS_LED, CHIP_ID);
cdr_buf[1] = status;
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
#endif
default: {
cdr_buf[0] = _B_4b4b(ins_oper, CHIP_ID);
cdr_buf[1] = _B_4b4b(CDR_FAILURE, 0);
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
}
headstage_update_cis_instruction(ins_oper);
break;
}
}
}
@@ -3,9 +3,9 @@
#ifndef HEADSTAGE_ARM_H
#define HEADSTAGE_ARM_H
static uint16_t headstage_ramp_data_counter = 0;
static void headstage_arm_append_ramp_data(uint8_t *buff) {
static uint16_t headstage_ramp_data_counter = 0;
uint16_t v = headstage_ramp_data_counter++;
@@ -25,8 +25,8 @@ static void headstage_cis_led_enable(uint8_t enable);
static uint8_t headstage_cis_led_set_pattern(uint8_t pattern);
/**
* @para pattern: pattern number
* @para parameter: led parameter, NULL to unset
* @param pattern: pattern number
* @param parameter: led parameter, NULL to unset
* @return: CDR_SUCCESS
*/
static uint8_t headstage_cis_led_set_value(uint8_t pattern, //
@@ -0,0 +1,85 @@
#ifndef NEU_INSTRUCTION
#define NEU_INSTRUCTION
struct HEADSTAGE_PARAMETER_TABLE {
uint8_t current_sti_cycle[NEU_STI_CHANNEL_COUNTS]; /** stimulation times will be executed. */
// sti_tx[0~7] is current stimulate
// sti_tx[8] assign to voltage mode channel. */
uint16_t sti_t1[NEU_STI_CHANNEL_COUNTS]; /**< first stimulation pulse duration, it can't be 0. */
uint16_t sti_t2[NEU_STI_CHANNEL_COUNTS]; /**< interval between biphasic pulses. */
uint16_t sti_t3[NEU_STI_CHANNEL_COUNTS]; /**< second stimulation pulse duration. */
uint32_t sti_t4[NEU_STI_CHANNEL_COUNTS]; /**< discharge time per stimulation. */
uint16_t sti_t5[NEU_STI_CHANNEL_COUNTS]; /**< discharge time after final stimulation. */
bool sti_mode; /**< if true: continuous mode, else limited mode. */
bool sti_h_bridge; /**< if true: enable h bridge, else single ended. */
bool sti_ref; /**< if true: reference cell body to gnd, else single ended is used. */
uint8_t current_sti_polarity; /**<
* default : low side.
* define which channel is high side or low side.
*/
uint8_t voltage_sti_channel; /**<
* voltage_channel[7:4] represent pmos channel,
* voltage_channel[3:0] represent nmos channel
*/
uint8_t amplifier_gain; /**<
* parameter table to represent actual amplifier gain
* ----------
* | bit |mean|
* ----------
* |0b00 | 100|
* ----------
* |0b01 | 400|
* ----------
* |0b10 | 800|
* -----------
* |0b11 | 25 |
* -----------
*/
/**< these parameter define the bias voltage of amplifier. */
uint8_t vgrp;
uint8_t vgrn;
uint8_t vgr_int_old;
uint8_t vgr_intp;
uint8_t vgr_intn;
uint8_t ins_opcode; /**< check instruction opcode which is transmitted to DBS. */
uint8_t voltage_sti_amplitude; /**< voltage mode stimulation amplitude control. */
uint16_t arbitrary_index; /**< this index to keep address of arbitrary data we have already stored. */
uint16_t arbitrary_en; /**< if true: enable arbitrary mode stimulation. */
uint16_t recording_channel; /**< recording_channel[17] represent enabling channel 17. */
uint16_t sti_amplitude_h; /**< positive side amplitude. */
uint16_t sti_amplitude_l; /**< negative side amplitude. */
uint16_t sys_clk_ratio; /**< frequency divider ratio for digital core clock. */
uint16_t adc_clock_ratio; /**< frequency divider ratio for adc clock. */
uint16_t sti_clock_ratio; /**< frequency divider ratio for stimulation clock. */
uint16_t chopper_ratio; /**< freqeuncy divider for chopper. */
uint16_t sti_channel; /**<
* if stimulation[7] == true, stimulation channel 7 is enabled .
* if stimulation[4] == true. stimulation channel 4 is enabled .
*/
} INSTRUCTION = {0};
/**
* @brief:
* manage which operation to be conducted
*/
struct HEADSTAGE_STATE {
uint8_t state;
uint8_t config_type;
uint8_t index;
} NEULIVE_STATE = {0};
#endif
@@ -192,7 +192,7 @@ static void headstage_led_color(uint8_t color) {
==== LED implement (GPIO) ====
============================*/
#ifdef BOOSTXL_CC2650MA
#ifdef HEADSTAGE_UNI_H
#define HEADSTAGE_LED_USE_GPIO
#endif
@@ -208,10 +208,10 @@ static void headstage_led_spi_transmit() {
for (int8_t j = 15; j >= 0; j--) {
int16_t v = (d & (1 << j)); // why check > 0 or not
bool SET_LED = (v > 0) ? 1 : 0;
headstage_pin_output(PIN_LED_CLK, 1);
headstage_pin_output(PIN_LED_CLK, 0);
CPUdelay(16 * 400); // 2500hz
headstage_pin_output(PIN_LED_OUT, SET_LED);
headstage_pin_output(PIN_LED_CLK, 0);
headstage_pin_output(PIN_LED_CLK, 1);
CPUdelay(16 * 400); // 2500hz
}
}
@@ -31,7 +31,7 @@ optional implement
#include <xdc/runtime/Timestamp.h>
#define headstage_time_stamp_us() (Timestamp_get32() / 2)
#define headstage_time_stamp_us() (Timestamp_get32() / 2)
/*========================
==== notify function ====
@@ -66,7 +66,7 @@ static void headstage_notify_send() {
}
#else
SimpleProfile_SetParameter(BLE_NOT_BUFF_CHAR, BLE_NOT_BUFF_SIZE, headstage_notify_buffer) ;
SimpleProfile_SetParameter(BLE_NOT_BUFF_CHAR, BLE_NOT_BUFF_SIZE, headstage_notify_buffer);
#endif
}
@@ -14,6 +14,8 @@
#include "zm/headstage_pin.h"
#elif defined(HEADSTAGE_STI_H)
#include "sti/headstage_pin.h"
#elif defined(HEADSTAGE_NEU_H)
#include "neu/headstage_pin.h"
#else
#error "headstage_pin headstage_pin_configuration not defined"
@@ -28,7 +28,7 @@ static SPI_Transaction spi_transaction;
spi_parameter.bitRate = 12000000; \
spi_parameter.transferTimeout = 1000; \
spi_parameter.dataSize = 8; \
spi_parameter.frameFormat = SPI_POL0_PHA0; \
spi_parameter.frameFormat = SPI_POL0_PHA1; \
spi_handle = SPI_open(Board_SPI0, &spi_parameter); \
} while (0)
@@ -0,0 +1,30 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
/**
\file headstage_swi.h
In order to enable interrupt, hookset function need declaring.
reference:ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/docs/Bios_User_Guide.pdf
*/
#ifndef HEADSTAGE_SWI_H
#define HEADSTAGE_SWI_H
#include <ti/sysbios/knl/Swi.h>
#include <xdc/runtime/Error.h>
/*
software interrupt
*/
Swi_Handle headstage_swi;
typedef void (*headstage_swiFxn)(UArg arg0, UArg arg1);
void headstage_swi_init(headstage_swiFxn callback) {
Error_Block eb;
Error_init(&eb);
headstage_swiFxn my_swi = callback;
headstage_swi = Swi_create(my_swi, NULL, &eb);
}
#endif
@@ -1,5 +1,5 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_H
#error "headstage.h not include"
#endif
@@ -7,6 +7,72 @@
#ifndef HEADSTAGE_UNI_H
#define HEADSTAGE_UNI_H
/**
* @file headstage_uni.h
*
* Copyright (c) 2019. BioPro. Scientific.
*
* NEULIVE firmware structure:
*
* headstage_init()
* headstage_uni_event()
* headstage_umc_state_transfer_lsk()
* headstage_umc_state_transfer_ask()
*
* description:
*
* Construct corresponding headstage_uni_event to implement the communication between
* DBS and CC2650. Because finite state machine is used to build the digital core,
* a similar structure to monitor its state is needed.
*
* headstage_uni_event:
*
* 1. LSK transmit event :
* receive LSK and process raw data
*
* 2. ASK transmit event :
* transmit ASK to DBS chip
*
* 3. trigger stimulation event:
* transmit trigger flag to DBS chip
*
* 4. Disconnect :
* stop system working
*
* ...reserved
*
* protocol between DBS chip and cc2650:
*
* DBS (LSK) -> CC2650 (SPI):
* format: 9'b PREAMBLE + 4'b HEADER + 10'bit DATA
* PREAMBLE: imply the channel order, refer to rearrange channel for more detail.
*
* cc2650 (SPI) -> DBS (ASK):
* format: 4'bHEADER + ( 10'b INSTRUCTION + 4'b ID ) * 2
* INSTRUCTION: construct the instruction corresponding to DBS chip
*
* state machine:
*
* In order to control the digital core inside DBS chip, this application needs to simulate a similar structure.
* (interrupt)
* IDLE -> HANDSHAKE -> HANDSHAKE_RECEIVE -> INITIAL -> CONFIGURE -> WAIT_START --> TRIGGER -> WAIT_TRIGGER ----------------> CONFIGURE
* | |
* --> LIMITED --|
* | |
* --> CONTINUOUS --
*
* State Description:
* There are two state machines implemented in this structure.
* Different state acts differently,
* e.g., CONFIGURE and WAIT_START would transmit the same code to DBS with different meaning
* state transfer in LSK:
* After receiving LSK data, acts corresponding to current state and decide to change state or not
* state transfer in ASK:
* After receiving ASK data, acts corresponding to current state
*
*/
// TODO low frequency mode
// TODO battery record
// TODO watchdog function need implementing
@@ -15,12 +81,30 @@
/*=================
==== constant ====
=================*/
// data transmit format 9'b PREAMBLE + 4'b HEADER + 10'bit DATA
// clang-format off
/**
specific data from DBS
In order to set recording channel, arrange a set of selected channel.
The first select channel data will come with preamble.
*/
#define UMC_PREAMBLE 0b011000001
/**
header used in LSK and ASK transmission
*/
#define UMC_HEADER 0b0101
// clang-format on
/**
The data format between NEULIVE and CONTROLL BOX
Use notification to transmit data to control box through BLE.
Definition of the protocol:
4'B timestamp + 2'B time delta + (4'b channel + 10'b voltage + 2'b flag) * (N)
N: numbers of data transmitted in a transaction
*/
#define HEADSTAGE_NOTIFY_USE_TDC4VAF2
/*================
==== include ====
@@ -33,22 +117,41 @@
#include "headstage_led.h"
#include "headstage_watchdog.h"
#include "headstage_notify.h"
#include "headstage_indicate.h"
#include "headstage_swi.h"
#include "tni/headstage_notify.h"
#include "uni/headstage_spi.h"
#include "uni/headstage_pwm.h"
#include "uni/headstage_adc.h"
#include "uni/uni1.2_parameter.h"
#include "headstage_indicate.h"
#include "uni/uni1.3_parameter.h"
/*===================================
==== instruction building macro ====
==================================*/
/**
construct final instruction
Construct the final instruction transmitted to DBS chip
final instruction = Header + instruction + instruction
@param code: prebuilt instruction
@return final instruction
*/
#define build_instruction(code) \
({ \
uint32_t __x = (code)&0x3FFF; \
(UMC_HEADER << 28) | (__x << 14) | (__x); \
})
/**
construct instruction
Construct the instruction and pass it to build_instruction.
Instruction = 4'b type(opcode) + 6'b value + 4'b chip_id
@param type: the opcode is going to be transmitted
@param value: the operating value
@return final instruction
*/
#define build_configure_instruction(type, value) \
({ \
@@ -58,14 +161,11 @@
build_instruction((__t << 10) | (__v << 4) | __c); \
})
#define build_conservative_instruction(type, value) \
({ \
uint32_t __t = (type)&0xF; \
uint32_t __v = (value)&0x3F; \
uint32_t __c = (CHIP_ID)&0xFF; \
uint32_t __x = ((__t << 6) | (__v)) & 0x3FF; \
(UMC_HEADER << 28) | (__x << 18) | (__c << 10) | (__x); \
})
/**
get data from spi_rxbuf and convert it to uint16_t
@param index: getting value from the index
@return receive data casting in uint16_t
*/
#define rx_get_u16(index) \
({ \
@@ -75,6 +175,12 @@
(__a << 8) | __b; \
})
/**
get data from spi_rxbuf and convert it to uint32_t
@param index: the index of spi_rxbuf
@return receive data casting in uint32_t
*/
#define rx_get_u32(index) \
({ \
uint32_t __i = (uint32_t)(index); \
@@ -85,6 +191,12 @@
(__a << 24) | (__b << 16) | (__c << 8) | __d; \
})
/**
put uint16_t into spi_txbuf
@param index: the index of spi_txbuf
@param value: the data is going to be set
*/
#define tx_put_u16(index, value) \
do { \
uint32_t __i = (uint32_t)(index); \
@@ -93,6 +205,12 @@
spi_txbuf[__i++] = (__v)&0xFF; \
} while (0)
/**
put uint32_t into spi_txbuf
@param index: the index of spi_txbuf
@param value: the data is going to be set
*/
#define tx_put_u32(index, value) \
do { \
uint32_t __i = (uint32_t)(index); \
@@ -107,37 +225,72 @@
==== constant ====
=================*/
// data rate
/**
this part frequency is controlling the operating
*/
// clang-format off
#define UMC_LSK_FREQ 100000 // 500 khz
#define UMC_ASK_FREQ 20000 // 100 khz
#define UMC_SYS_CLK 2000000 // target is 8Mhz
#define UMC_POLY_R_CLK 1000 // poly-R switching clock
/** target LSK data rate is 50 khz */
#define UMC_LSK_FREQ 50000
/** target ASK data rate is 10 khz */
#define UMC_ASK_FREQ 10000
/** target SYSTEM clock frequency is 1Mhz */
#define UMC_SYS_CLK 1000000
/** poly-R switching clock frequency */
#define UMC_POLY_R_CLK 1000
// Neulive instruction macro
/// Neulive instruction macro
/** handshake information receive from DBS */
#define UMC_HAND_SHAKE_SEND 0b0011000011
/** handshake information send to DBS */
#define UMC_HAND_SHAKE_RECV 0b01010011000110000000110001100000
/** set the interface with DBS */
#define UMC_MODE_LSK_OUT 0b101001
#define UMC_CALIB_DONE 0b1010 // UMC_CALIB_DONE + UMC_MODE_LSK_OUT -> leave initial state and set "CHIP ID"
#define UMC_CONFIG_DONE 0b0100 // UMC_CONFIG_DONE + 6'bxxxxxx -> EXIT config state
/** UMC_CALIB_DONE + UMC_MODE_LSK_OUT : leave initial state and set "CHIP ID" */
#define UMC_CALIB_DONE 0b1010
/** UMC_CONFIG_DONE + 6 bits don't care : EXIT config state */
#define UMC_CONFIG_DONE 0b0100
/**
UMC_IRQ + UMC_IRQ_CODE + CHIP ID : go back to configure data from continuous, trigger, limited
UMC_IRQ type of interrupt
*/
#define UMC_IRQ 0b1110
#define UMC_IRQ_CODE 0b001001 // UMC_IRQ + UMC_IRQ_CODE + CHIP ID -> when we want to go back to configure data.
/** UMC_IRQ_CODE value of interrupt */
#define UMC_IRQ_CODE 0b001001
/** leave wait trigger state by this instruction */
#define UMC_GOLDEN_KEY 0b01011010010110000010100101100000 //this is important to leave wait trigger state.
// we need to check transfer data meets or not
#define UMC_TRANSMIT_S 0b101 // transmit success
/** we need to check transfer data meets or not */
#define UMC_TRANSMIT_S 0b101
// trigger stimulation by ask
/**
trigger a stimulation by ASK
UMC_TRIG + UMC_STIMULUS + CHIP ID
UMC_TRIG type of trigger a stimulus
*/
#define UMC_TRIG 0b1100
/**
UMC_STIMULUS value of trigger a stimulus
*/
#define UMC_STIMULUS 0b000011
/**
type of opcode, control box to cc2650.
*/
/** control box to cc2650:default type instruction */
#define RIS_DEFAULT 0x00
/** control box to cc2650 instruction opcode, parameter set 1 */
#define RIS_SET_PARA 0x20
/** control box to cc2650 instruction opcode, remove amplifier offset */
#define RIS_RESET_AMP 0x60
/** control box to cc2650 instruction opcode, parameter set 2 */
#define RIS_DIR 0xA0
/** control box to cc2650 instruction opcode, trigger stimulation */
#define RIS_UMC_TRIG 0xC0
/**
stimulation waveform
*/
#define STI_MODE_DISABLE 0
#define STI_MODE_POS 1
#define STI_MODE_NEG 2
@@ -146,11 +299,18 @@
#define STI_MODE_AWF 5
#define ARM_MODE_RAMP 8
/**
reserved virtual instruction
*/
#define VIS_BLE_T 0b10100000
#define VIS_SHIFT_T 0b01010000
// all the categories of instruction we can change .
/**
configuration set for DBS instruction
*/
#define CONFIG_AMP_CH 0x10 // this state is for transmit amp channel one more time
#define CONFIG_AMP_MUX 0x01
#define CONFIG_AMP_GAIN 0x02
@@ -332,12 +492,21 @@ struct HEADSTAGE_PARAMETER_TABLE {
*/
bool adc_clock_signal;
/*
/**
* amplifier reset
*/
bool amp_rst;
} INSTRUCTION = {0};
/**
@fn static void headstage_uni_delay()
@brief make some delay
*/
static void headstage_uni_delay() {
for (uint16_t i = 0; i < 1023; i++)
;
}
static void rearrange_channel_mux_table() {
uint8_t enable_channel_number = 0;
uint8_t last_enable_channel = 0;
@@ -415,6 +584,10 @@ static void rearrange_channel_mux_table() {
#define UPDATE_DONE 0xFF
// clang-format on
/**
@struct UMC_STATE
*/
struct {
uint8_t state;
@@ -485,6 +658,7 @@ static void headstage_spi_ask_callback(SPI_Handle handle, SPI_Transaction* trans
}
static void headstage_spi_lsk_callback(SPI_Handle handle, SPI_Transaction* transaction) {
if (not_buf_offset >= BLE_NOT_BUFF_SIZE) Swi_post(headstage_swi);
if (UMC_STATE.reset_flag == 0) flag_notify(EVT_UMC_LSK);
}
@@ -507,6 +681,8 @@ static void headstage_reset() {
==== function implement ====
==========================*/
static void headstage_swi_func(UArg a0, UArg a1) {}
/**
* initialize parameter and device.
*/
@@ -514,6 +690,7 @@ static void headstage_init() {
headstage_pin_open();
headstage_spi_open();
headstage_pwm_open();
headstage_swi_init(headstage_swi_func);
headstage_led_spi_color(COLOR_GREEN);
// headstage_watchdog_open();
// if(headstage_watchdog_handle == NULL)
@@ -552,22 +729,20 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
break;
}
case RIS_SET_PARA: {
uint8_t amp_gain = (instruction[0] & 0x1C) >> 2;
uint8_t pulse_width = ((instruction[0] & 0x03) << 2) | ((instruction[1] & 0xC0) >> 6);
uint8_t sti_times = (instruction[1] & 0x3F);
uint8_t sti_freq = (instruction[2] & 0x3F);
uint8_t mode = (instruction[2] & 0xC0) >> 6;
uint8_t cha = (instruction[3] & 0x0F);
uint8_t chb = (instruction[4] & 0xF0) >> 4;
uint8_t chc = (instruction[4] & 0x0F);
uint8_t chd = (instruction[5] & 0xF0) >> 4;
uint8_t amp_gain = (instruction[0] & 0x1C) >> 2;
uint8_t pulse_width = ((instruction[0] & 0x03) << 2) | ((instruction[1] & 0xC0) >> 6);
uint8_t sti_times = (instruction[1] & 0x3F);
uint8_t sti_freq = (instruction[2] & 0x3F);
uint8_t mode = (instruction[2] & 0xC0) >> 6;
uint8_t cha = (instruction[3] & 0x0F);
uint8_t chb = (instruction[4] & 0xF0) >> 4;
uint8_t chc = (instruction[4] & 0x0F);
uint8_t chd = (instruction[5] & 0xF0) >> 4;
INSTRUCTION.amp_gain = amp_gain;
INSTRUCTION.pulse_width = pulse_width;
INSTRUCTION.sti_times = sti_times;
INSTRUCTION.mode = mode;
INSTRUCTION.sti_freq = sti_freq;
INSTRUCTION.mode = mode;
if (instruction[3] & 0b10000000) INSTRUCTION.channel_table[amp_channel_table[cha] - 1] = TRUE;
if (instruction[3] & 0b01000000) INSTRUCTION.channel_table[amp_channel_table[chb] - 1] = TRUE;
if (instruction[3] & 0b00100000) INSTRUCTION.channel_table[amp_channel_table[chc] - 1] = TRUE;
@@ -581,7 +756,7 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
INSTRUCTION.amp_gain = 5; // x1000
INSTRUCTION.pulse_width = 0; // 40us
INSTRUCTION.sti_times = 0; // repeat stimulation x1
INSTRUCTION.mode = 1; // trigger mode
INSTRUCTION.mode = 3; // trigger mode
INSTRUCTION.sti_freq = 3; // 30hz
INSTRUCTION.sti_waveform = 1; // positive
INSTRUCTION.chopper = 0; // turn off chopper
@@ -598,18 +773,16 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
break;
}
case RIS_UMC_TRIG:
case RIS_UMC_TRIG: {
tx_put_u32(0, build_configure_instruction(UMC_TRIG, UMC_STIMULUS));
flag_notify(EVT_UMC_STI);
/*
load
*/
break;
case RIS_RESET_AMP:
}
case RIS_RESET_AMP:{
tx_put_u32(0, build_configure_instruction(UMC_TRIG, UMC_STIMULUS));
headstage_spi_ask_transaction(4);
break;
}
default:
break;
}
@@ -625,9 +798,10 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
break;
case VIS_STI:
if (headstage_state == UMC_STATE_INTERRUPT) {
headstage_state = UMC_STATE_CONFIGURE;
headstage_state = UMC_STATE_INITIAL;
rearrange_channel_mux_table();
UMC_STATE.config_type = CONFIG_AMP_MUX;
headstage_led_spi_color(COLOR_BLACK);
tx_put_u32(0, build_configure_instruction(UMC_IRQ, UMC_IRQ_CODE));
headstage_spi_ask_transaction(4);
} else {
@@ -645,11 +819,8 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
// interrupt
case VIS_INT:
headstage_state = UMC_STATE_INTERRUPT;
headstage_spi_transaction_cancel(headstage_spi_lsk_handle);
memset(headstage_debug_buffer, 0, BLE_NOT_BUFF_SIZE);
tx_put_u32(0, build_configure_instruction(UMC_IRQ, UMC_IRQ_CODE));
headstage_spi_ask_transaction(4);
headstage_reset();
headstage_state = UMC_STATE_HANDSHAKE;
break;
case VIS_BLE_T:
@@ -667,6 +838,52 @@ static void headstage_update_vis_instruction(uint8_t vis_oper) {
}
}
/**
* @fn headstage_update_cis_instruction
*/
static void headstage_update_cis_instruction(uint8_t cis_oper) {
switch (cis_oper) {
case CIS_NOP: {
// nothing
cdr_buf[0] = _B_4b4b(CIS_NOP, CHIP_ID);
cdr_buf[1] = _B_4b4b(CDR_SUCCESS, 0);
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, 2, cdr_buf);
break;
}
#ifdef HEADSTAGE_CIS_VOLT_H
case CIS_VOLT: {
uint8_t status = headstage_update_vis_volt(ins_len, instruction + 2, cdr_buf + 2);
cdr_buf[0] = _B_4b4b(CIS_VOLT, CHIP_ID);
cdr_buf[1] = status;
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
#endif
#ifdef HEADSTAGE_CIS_LED_H
case CIS_LED: {
uint8_t status = headstage_update_vis_led(ins_len, instruction + 2, cdr_buf + 2);
cdr_buf[0] = _B_4b4b(CIS_LED, CHIP_ID);
cdr_buf[1] = status;
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
#endif
default: {
cdr_buf[0] = _B_4b4b(cis_oper, CHIP_ID);
cdr_buf[1] = _B_4b4b(CDR_FAILURE, 0);
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, BLE_CDR_BUFF_SIZE, cdr_buf);
break;
}
}
}
/*
* todo: need to define some procedure to detect this device status
*/
@@ -689,12 +906,6 @@ static void headstage_uni_test_data_append_notify_buffer(uint8_t* dat_buf) {
headstage_notify_send();
}
// implement this function to detect
static void headstage_uni_delay() {
for (uint16_t i = 0; i < 1023; i++)
;
}
// todo: check data length extension with this function -> this function should be
static void headstage_uni_umc_data_append_notify_buffer(uint8_t* dat_buf) {
// check LSK data preamble ( 0b01100_0001 ) 58(01011000) 2c(00101100)
@@ -702,32 +913,31 @@ static void headstage_uni_umc_data_append_notify_buffer(uint8_t* dat_buf) {
// 0110_0000_1010_1xxx_xxxx_xxxX_XXXX_XXXX and
// 1100_0001_0101_xxxx_xxxx_xxXX_XXXX_XXXX
if (((spi_rxbuf[0] & 0xC1) != 0xC1) && (spi_rxbuf[0] != 0x00)) {
headstage_uni_delay();
headstage_led_spi_color(COLOR_CYAN);
headstage_uni_delay();
} else {
if ((dat_buf[1] & 0x28) == 0x28) {
dat_buf[0] = (dat_buf[0] << 1) | ((dat_buf[1] >> 7) & 0x01);
dat_buf[1] = (dat_buf[1] << 1) | ((dat_buf[2] >> 7) & 0x01);
dat_buf[2] = (dat_buf[2] << 1) | ((dat_buf[3] >> 7) & 0x01);
if ((spi_rxbuf[1] & 0x28) == 0x28) {
spi_rxbuf[0] = (spi_rxbuf[0] << 1) | ((spi_rxbuf[1] >> 7) & 0x01);
spi_rxbuf[1] = (spi_rxbuf[1] << 1) | ((spi_rxbuf[2] >> 7) & 0x01);
spi_rxbuf[2] = (spi_rxbuf[2] << 1) | ((spi_rxbuf[3] >> 7) & 0x01);
}
uint8_t channel;
if ((INSTRUCTION.enable_channel_number == 1) || (dat_buf[0] == 0xc1)) {
if ((INSTRUCTION.enable_channel_number == 1) || (spi_rxbuf[0] == 0xc1)) {
channel = reverse_channel[INSTRUCTION.last_enable_channel];
} else {
uint8_t channel_pointer = (INSTRUCTION.channel_pointer + 1) % INSTRUCTION.last_enable_channel;
INSTRUCTION.channel_pointer = channel_pointer;
channel = reverse_channel[INSTRUCTION.channel_mux[channel_pointer]];
}
// uint16_t data_value = (uint16_t)(((dat_buf[1] & 0x0F) << 6) | ((dat_buf[2] & 0xFC) >> 2));
uint8_t data_size = headstage_notify_append_data(channel, dat_buf);
// uint8_t data_size = headstage_notify_append_data(channel, spi_rxbuf);
if (data_size >= BLE_NOT_BUFF_SIZE) {
headstage_notify_send();
headstage_notify_flip_buffer();
}
}
// uint16_t data_value = (uint16_t)(((dat_buf[1] & 0x0F) << 6) | ((dat_buf[2] & 0xFC) >> 2));
headstage_spi_lsk_transaction(3);
}
@@ -820,7 +1030,10 @@ static uint8_t build_umn_ins_config(uint8_t config_type, uint32_t* value) {
==== UMC SPI interface ====
=========================*/
// ASK interface
/**
* @fn headstage_umc_state_transfer_ask
*
*/
static void headstage_umc_state_transfer_ask() {
// after receive handshake , transmit handreceive
@@ -844,6 +1057,7 @@ static void headstage_umc_state_transfer_ask() {
case UMC_STATE_TRIGGER:
case UMC_STATE_CONTINUOUS:
case UMC_STATE_LIMITED:
case UMC_STATE_INTERRUPT:
break;
case UMC_STATE_WAIT_TRIGGER:
headstage_state = UMC_STATE_TRIGGER;
@@ -854,6 +1068,9 @@ static void headstage_umc_state_transfer_ask() {
}
}
/** headstage_umc_state_transfer_lsk
*
*/
static void headstage_umc_state_transfer_lsk() {
headstage_debug_buffer[0] = headstage_state;
headstage_set_debug_information();
@@ -939,28 +1156,39 @@ static void headstage_umc_state_transfer_lsk() {
case UMC_STATE_WAIT_START:
if (headstage_debug_buffer[1] > 18) {
// this transaction make cause amplifier data right shift
headstage_spi_lsk_transaction(3);
switch (INSTRUCTION.mode) {
default:
headstage_state = UMC_STATE_CONTINUOUS;
UMC_STATE.trigger_times = 0;
break;
case 3:
case 0:
// continuous mode
headstage_state = UMC_STATE_CONTINUOUS;
headstage_state = UMC_STATE_TRIGGER;
UMC_STATE.trigger_times = 0;
headstage_spi_lsk_transaction(3);
break;
case 1:
// trigger mode
headstage_state = UMC_STATE_TRIGGER;
UMC_STATE.trigger_times = 0;
headstage_spi_lsk_transaction(3);
break;
case 2:
// limited mode
headstage_state = UMC_STATE_LIMITED;
UMC_STATE.trigger_times = INSTRUCTION.sti_times;
headstage_spi_lsk_transaction(3);
break;
case 3:
// continuous mode
headstage_state = UMC_STATE_CONTINUOUS;
UMC_STATE.trigger_times = 0;
headstage_spi_lsk_transaction(3);
break;
default:
headstage_state = UMC_STATE_CONTINUOUS;
UMC_STATE.trigger_times = 0;
headstage_spi_lsk_transaction(3);
break;
}
} else if (headstage_debug_buffer[1] > 10) {
@@ -993,7 +1221,8 @@ static void headstage_umc_state_transfer_lsk() {
headstage_state = UMC_STATE_WAIT_START;
}
break;
case UMC_STATE_INTERRUPT:
break;
default:
break;
}
@@ -0,0 +1,5 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_ADC_H
#define HEADSTAGE_ADC_H
#endif
@@ -0,0 +1,23 @@
#ifndef CHECK_MOSI
#define CHECK_MOSI
#include "headstage_led.h"
/*
* MOSI channel meet with INSTRUCTION.recording_channel ?
*/
static uint8_t CheckMOSI(uint8_t* MOSI){
uint8_t ch = MOSI[0];
uint16_t selectCh = 0x0001 << ch;
if(selectCh & INSTRUCTION.recording_channel){
return 1;
}
else{
// headstage_led_color(COLOR_RED);
// headstage_led_color(COLOR_GREEN);
return 0;
}
}
#endif
@@ -0,0 +1,16 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef NEULIVE_2P0
#define NEULIVE_2P0
/*============================
==== product information ====
===========================*/
#define DEVICE_NAME "Neulive-v2.0"
#define MAJOR_PRODUCT_NUMBER 1
#define MINOR_PRODUCT_NUMBER 1
#define MAJOR_VERSION_NUMBER 2
#define MINOR_VERSION_NUMBER 0
#endif
@@ -0,0 +1,59 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_NOTIFY_TDC4VC_H
#define HEADSTAGE_NOTIFY_TDC4VC_H
#ifndef HEADSTAGE_NOTIFY_H
#error "headstage/headstage_notify.h not included"
#endif
#define NOT_BUF_OFFSET_INIT 8
static uint8_t not_buf_offset = NOT_BUF_OFFSET_INIT;
static uint32_t not_time_stamp = 0;
static void headstage_notify_set_timestamp() {
not_time_stamp = headstage_time_stamp_us();
headstage_notify_buffer[0] = CHIP_ID;
headstage_notify_buffer[1] = 4;
headstage_notify_buffer[2] = not_time_stamp & 0xFF;
headstage_notify_buffer[3] = (not_time_stamp >> 8) & 0xFF;
headstage_notify_buffer[4] = (not_time_stamp >> 16) & 0xFF;
headstage_notify_buffer[5] = (not_time_stamp >> 24) & 0xFF;
}
static void headstage_notify_flip_buffer() {
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 2;
headstage_notify_buffer[0] = CHIP_ID;
headstage_notify_buffer[1] = data_count;
not_buf_offset = NOT_BUF_OFFSET_INIT;
}
/**
The data format between NEULIVE and CONTROL BOX
Use notification to transmit data to control box through BLE.
Definition of the protocol:
4 byte timestamp + (1 byte channel + 2 byte voltage) * (N)
N: numbers of data transmitted in a transaction
*/
static uint8_t headstage_notify_append_data(uint8_t *data_value) {
if (not_buf_offset <= NOT_BUF_OFFSET_INIT) {
headstage_notify_set_timestamp();
not_buf_offset = NOT_BUF_OFFSET_INIT;
}
headstage_notify_buffer[not_buf_offset++] = data_value[0];
headstage_notify_buffer[not_buf_offset++] = data_value[1];
headstage_notify_buffer[not_buf_offset++] = data_value[2];
uint8_t ret = not_buf_offset;
return ret;
}
#endif // HEADSTAGE_NOTIFY_TDC4VAF2_H
@@ -0,0 +1,109 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_PIN_NEU_H
#define HEADSTAGE_PIN_NEU_H
//#define NEU_2_0
#define NEU_2_1
#if defined(CC2650_LAUNCHXL)
// clang-format off
#define PIN_RESET IOID_0 // SPI1 to receive LSK
#define PIN_EN_ADC_SPI_CLK IOID_1 // SPI1 clock
#define PIN_DC_DC IOID_2 // STI select need
#define PIN_BATT_HALF IOID_3 //
#define PIN_AMP_VCK IOID_4 //
#define PIN_LED_SDI IOID_5 //
#define PIN_LED_CLK IOID_8 //
#define PIN_STI_CLK IOID_9 //
#define PIN_SPI_MISO IOID_10 //
#define PIN_SPI_MOSI IOID_11 //
#define PIN_SPI_CS IOID_12 //
#define PIN_SPI_CLK IOID_13 //
#define PIN_SYS_CLK IOID_14 //
//#define GLED IOID_7
//#define RLED IOID_6
// clang-format on
#elif defined(BOOSTXL_CC2650MA)
// clang-format off
#ifdef NEU_2_0
#define PIN_RESET IOID_0 // SPI1 to receive LSK
#define PIN_EN_ADC_SPI_CLK IOID_1 // SPI1 clock
#define PIN_DC_DC IOID_2 // STI select need
#define PIN_BATT_HALF IOID_3 //
#define PIN_AMP_VCK IOID_4 //
#define PIN_LED_SDI IOID_7 //
#define PIN_LED_CLK IOID_8 //
#define PIN_STI_CLK IOID_9 //
#define PIN_SPI_MISO IOID_10 //
#define PIN_SPI_MOSI IOID_11 //
#define PIN_SPI_CS IOID_12 //
#define PIN_SPI_CLK IOID_13 //
#define PIN_SYS_CLK IOID_14 //
#elif defined(NEU_2_1)
#define PIN_LED_SDI IOID_0 // SPI1 to receive LSK
#define PIN_LED_CLK IOID_1 // SPI1 clock
#define PIN_DC_DC IOID_2 // STI select need
#define PIN_EN_ADC_SPI_CLK IOID_3 //
#define PIN_BATT_HALF IOID_4 //
#define PIN_SPI_MISO IOID_7 //
#define PIN_SPI_MOSI IOID_8 //
#define PIN_SPI_CS IOID_9 //
#define PIN_SPI_CLK IOID_10 //
#define PIN_SYS_CLK IOID_11 //
#define PIN_RESET IOID_12 //
#define PIN_AMP_VCK IOID_13 //
#define PIN_STI_CLK IOID_14 //
#endif
// clang-format on
#endif
/*
* SPI0 interface with DBS chip 2.0
*/
#define Board_SPI0_MISO PIN_SPI_MISO
#define Board_SPI0_MOSI PIN_SPI_MOSI
#define Board_SPI0_CLK PIN_SPI_CLK
//#define Board_SPI0_CSN PIN_SPI_CS
#define Board_SPI0_CSN PIN_UNASSIGNED
/*
* SPI1 interface work with LED
*/
#define Board_SPI1_MISO PIN_UNASSIGNED
#define Board_SPI1_MOSI PIN_LED_SDI
#define Board_SPI1_CLK PIN_LED_CLK
#define Board_SPI1_CSN PIN_UNASSIGNED
/* Power Management Board */
#define Board_SRDY Board_BP_Pin_J2_19
#define Board_MRDY Board_BP_Pin_J1_2
/* PWM outputs */
#define Board_PWMPIN0 PIN_AMP_VCK
#define Board_PWMPIN1 PIN_UNASSIGNED
#define Board_PWMPIN2 PIN_SYS_CLK
#define Board_PWMPIN3 PIN_UNASSIGNED
#define Board_PWMPIN4 PIN_UNASSIGNED
#define Board_PWMPIN5 PIN_UNASSIGNED
#define Board_PWMPIN6 PIN_UNASSIGNED
#define Board_PWMPIN7 PIN_UNASSIGNED
static PIN_Config headstage_pin_configuration[] = { //
PIN_RESET | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_EN_ADC_SPI_CLK | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_DC_DC | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_BATT_HALF | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_STI_CLK | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
// RLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
// GLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
//
PIN_TERMINATE};
#endif // HEADSTAGE_PIN_UNI_H
@@ -0,0 +1,37 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_PWM_H
#define HEADSTAGE_PWM_H
#include <Board.h>
#include <ti/drivers/PWM.h>
static PWM_Handle headstage_system_pwm_handle = NULL;
static PWM_Handle headstage_poly_r_pwm_handle = NULL; // poly-R adjustment clock
#define headstage_pwm_open() \
do { \
PWM_init(); \
PWM_Params headstage_system_pwm_params; \
PWM_Params_init(&headstage_system_pwm_params); \
headstage_system_pwm_params.idleLevel = PWM_IDLE_LOW; \
headstage_system_pwm_params.periodUnits = PWM_PERIOD_HZ; \
headstage_system_pwm_params.periodValue = NEU_SYS_CLK; \
headstage_system_pwm_params.dutyUnits = PWM_DUTY_FRACTION; \
headstage_system_pwm_params.dutyValue = PWM_DUTY_FRACTION_MAX / 2; \
headstage_system_pwm_handle = PWM_open(Board_PWM2, &headstage_system_pwm_params); \
PWM_Params headstage_poly_r_pwm_params; \
PWM_Params_init(&headstage_poly_r_pwm_params); \
headstage_poly_r_pwm_params.idleLevel = PWM_IDLE_LOW; \
headstage_poly_r_pwm_params.periodUnits = PWM_PERIOD_HZ; \
headstage_poly_r_pwm_params.periodValue = NEU_POLY_R_CLK; \
headstage_poly_r_pwm_params.dutyUnits = PWM_DUTY_FRACTION; \
headstage_poly_r_pwm_params.dutyValue = PWM_DUTY_FRACTION_MAX / 2; \
headstage_poly_r_pwm_handle = PWM_open(Board_PWM0, &headstage_poly_r_pwm_params); \
} while (0)
#define headstage_pwm_start(handle) PWM_start(handle)
#define headstage_pwm_stop(handle) PWM_stop(handle)
#define headstage_pwm_close(handle) PWM_close(handle)
#endif // HEADSTAGE_PWM_H
@@ -0,0 +1,94 @@
#ifndef NEU_2_RST
#define NEU_2_RST
#include "headstage_instruction.h"
#include "neu/headstage_spi.h"
static void ResetINSTRUCTION();
static void MCUReset(){
// Reset INSTRUCTION & NEULIVE_STATE
ResetINSTRUCTION();
// SPI buffer reset
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++ ){
spi_txbuf[i] = 0;
spi_rxbuf[i] = 0;
}
SPICallBack = ONE_SHOT_SPI;
// FlushSPICounter = 0;
for(int i=0 ; i<SPI_LED_BUFF_SIZE ; i++){
headstage_spi_led_txbuf[i] = 0;
}
// CIS buffer reset
for(int i=0 ; i<BLE_CDR_BUFF_SIZE ; i++){
cdr_buf[i] = 0;
}
// Notify Buffer reset
for(int i=0 ; i<BLE_NOT_BUFF_SIZE ; i++){
headstage_notify_buffer[i] = 0;
}
not_buf_offset = NOT_BUF_OFFSET_INIT;
not_time_stamp = 0;
headstage_led_color(COLOR_GREEN); // color green
}
static void DBSReset(){
headstage_pin_output(PIN_RESET, 0);
headstage_cpu_delay_ms(10);
headstage_pin_output(PIN_DC_DC, 1);
headstage_pin_output(PIN_EN_ADC_SPI_CLK, 1);
headstage_pin_output(PIN_RESET, 1);
}
static void Neu2Reset(){
DBSReset();
MCUReset();
}
static void ResetINSTRUCTION(){
INSTRUCTION.vgrp = 16;
INSTRUCTION.vgrn = 16;
INSTRUCTION.vgr_intp = 16;
INSTRUCTION.vgr_intn = 16;
INSTRUCTION.vgr_int_old = 16;
INSTRUCTION.recording_channel = 0b0000000000000000;
INSTRUCTION.adc_clock_ratio = 100;
INSTRUCTION.sys_clk_ratio = 10;
INSTRUCTION.sti_clock_ratio = 10;
INSTRUCTION.amplifier_gain = 0;
INSTRUCTION.chopper_ratio = 2;
INSTRUCTION.sti_t1[1] = 1;
INSTRUCTION.sti_t2[1] = 0;
INSTRUCTION.sti_t3[1] = 0;
INSTRUCTION.sti_t4[1] = 0;
INSTRUCTION.sti_t5[1] = 0;
INSTRUCTION.sti_channel = 2;
INSTRUCTION.arbitrary_en = 0;
INSTRUCTION.arbitrary_index = 0;
INSTRUCTION.sti_h_bridge = 0;
INSTRUCTION.sti_mode = 0;
INSTRUCTION.sti_ref = 0;
INSTRUCTION.current_sti_polarity = 2;
INSTRUCTION.sti_amplitude_h = 0;
INSTRUCTION.sti_amplitude_l = 0;
INSTRUCTION.ins_opcode = BIAS_ONE;
uint8_t voltage_sti_channel = 0;
uint8_t voltage_sti_amplitude = 0;
for(int i=0 ; i<NEU_STI_CHANNEL_COUNTS ; i++){
INSTRUCTION.current_sti_cycle[i] = 0;
}
NEULIVE_STATE.state = NEU_IDLE;
NEULIVE_STATE.config_type = 0;
NEULIVE_STATE.index = 0;
}
#endif
@@ -0,0 +1,125 @@
/* Copyright (c) 2019. BioPro. Scientific.
*/
#ifndef HEADSTAGE_SPI_H
#define HEADSTAGE_SPI_H
#if defined(BOOSTXL_CC2650MA) && !defined(HEADSTAGE_MA_USE_SPI2)
#error "put HEADSTAGE_MA_USE_SPI2 in predefined"
#endif
#include <Board.h>
#include <ti/drivers/SPI.h>
#include <ti/drivers/dma/UDMACC26XX.h>
#include <ti/drivers/spi/SPICC26XXDMA.h>
#define SPI_BUFFER_SIZE 3
#define SPI_RX_SIZE 9
static uint8_t spi_txbuf[SPI_BUFFER_SIZE] = {0};
static uint8_t spi_rxbuf[SPI_BUFFER_SIZE] = {0};
static SPI_Handle headstage_spi_handle = NULL;
static SPI_Transaction headstage_spi_transaction;
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction);
static bool OpenSPI = false;
// SPI parameters initialize
#define headstage_spi_open() \
do { \
SPI_init(); \
SPI_Params spi_parameter; \
SPI_Params_init(&spi_parameter); \
spi_parameter.transferMode = SPI_MODE_CALLBACK; \
spi_parameter.mode = SPI_SLAVE; \
spi_parameter.bitRate = NEU_SPI_FREQ; \
spi_parameter.dataSize = 8; \
spi_parameter.frameFormat = SPI_POL0_PHA1; \
spi_parameter.transferCallbackFxn = headstage_spi_callback; \
headstage_spi_handle = SPI_open(Board_SPI0, &spi_parameter); \
} while (0)
//#define headstage_spi_transaction(handle, length, tx, rx) \
// ({ \
// SPI_Transaction transaction = headstage_spi_transaction ; \
// transaction.count = (length); \
// transaction.txBuf = (tx); \
// transaction.rxBuf = (rx); \
// SPI_transfer(handle, &transaction); \
// })
#define headstage_spi_transaction(length) \
({ \
headstage_spi_transaction.count = (length); \
headstage_spi_transaction.txBuf = (spi_txbuf); \
headstage_spi_transaction.rxBuf = (spi_rxbuf); \
SPI_transfer(headstage_spi_handle, &headstage_spi_transaction); \
})
#define headstage_spi_close(spi_handle) \
do { \
if (spi_handle != NULL) { \
SPI_close(spi_handle); \
spi_handle = NULL; \
} \
} while (0)
#define headstage_spi_transaction_cancel(spi_handle) \
do { \
if (spi_handle != NULL) { \
SPI_transferCancel(spi_handle); \
} \
} while (0)
static void ReopenSPI(){
SPI_init();
SPI_Params spi_parameter;
SPI_Params_init(&spi_parameter);
spi_parameter.transferMode = SPI_MODE_CALLBACK;
spi_parameter.mode = SPI_SLAVE;
spi_parameter.bitRate = NEU_SPI_FREQ;
spi_parameter.dataSize = 8;
spi_parameter.frameFormat = SPI_POL0_PHA1;
spi_parameter.transferCallbackFxn = headstage_spi_callback;
headstage_spi_handle = SPI_open(Board_SPI0, &spi_parameter);
}
static void WriteSPI(uint8_t length){
if(OpenSPI){
ReopenSPI();
}
for(int i=length ; i<SPI_BUFFER_SIZE ; i++){
spi_rxbuf[i] = 0x00;
}
SPICallBack = FLUSH_BUFFER;
headstage_spi_transaction.count = 3;
headstage_spi_transaction.txBuf = spi_txbuf;
headstage_spi_transaction.rxBuf = spi_rxbuf;
SPI_transfer(headstage_spi_handle, &headstage_spi_transaction);
}
static void ReadSPI(){
if(OpenSPI){
ReopenSPI();
}
SPICallBack = READ_REG;
headstage_spi_transaction.count = 3;
headstage_spi_transaction.txBuf = spi_txbuf;
headstage_spi_transaction.rxBuf = spi_rxbuf;
SPI_transfer(headstage_spi_handle, &headstage_spi_transaction);
}
static void AppendSPITX(uint8_t index, uint32_t value){
tx_put_u24(index, value);
for(int i=3 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0;
}
}
#endif
@@ -0,0 +1,305 @@
{
"name": "Neulive",
"version": "2.0",
"match_rule": {
"local_name_pattern": "Neulive.*",
"major_product_number": 1,
"minor_product_number": 1,
"major_version_number": 2,
"minor_version_number": 0
},
"constant": {
"REC_CHANNEL_COUNT": 16,
"STI_VOLT_CHANNEL_COUNT": 16,
"STI_AMP_CHANNEL_COUNT": 8
},
"parameters": {
"CHANNEL": {
"description": "record channels",
"record_meta": true,
"domain": {
"set": [
"REC_CHANNEL_COUNT"
]
}
},
"STI_VOLT_PCHANNEL": {
"description": "stimulation voltage mode channels",
"record_meta": true,
"domain": {
"set": [
"STI_VOLT_CHANNEL_COUNT"
]
},
"guard": "STI_VOLT_PCHANNEL != STI_VOLT_NCHANNEL"
},
"STI_VOLT_NCHANNEL": {
"description": "stimulation voltage mode channels",
"record_meta": true,
"domain": {
"set": [
"STI_VOLT_CHANNEL_COUNT"
]
},
"guard": "STI_VOLT_PCHANNEL != STI_VOLT_NCHANNEL"
},
"STI_AMP_PCHANNEL": {
"description": "stimulation ampere mode p channel",
"record_meta": true,
"domain": {
"set": [
"STI_AMP_CHANNEL_COUNT"
]
},
"guard": "STI_AMP_PCHANNEL != STI_AMP_NCHANNEL"
},
"STI_AMP_NCHANNEL": {
"description": "stimulation ampere mode n channel",
"record_meta": true,
"domain": {
"set": [
"STI_AMP_CHANNEL_COUNT"
]
},
"guard": "STI_AMP_PCHANNEL != STI_AMP_NCHANNEL"
},
"STI_TIME_DURATION_ONE": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
1024
],
"guard": "STI_TIME_DURATION_ONE < 1"
},
"STI_TIME_DURATION_TWO": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
1024
]
},
"STI_TIME_DURATION_THREE": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
1024
]
},
"STI_TIME_DURATION_FOUR": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
65536
]
},
"STI_TIME_DURATION_FIVE": {
"description": "stimulation pattern",
"record_meta": false,
"domain": [
2048
]
},
"AMP_GAIN": {
"description": "amplifier gain setting",
"record_meta": true,
"value": [
25,
100,
400,
800
]
},
"STI_MODE": {
"description": "how to execute stimulus",
"value": [
"DISABLE",
"LIMITED",
"CONTINUOUS"
]
},
"STI_AMPERE_HIGH_SIDE": {
"description": "stimulation ampere for pmos, unit: uA ",
"type": "int",
"domain": [
1024
],
"value": "VALUE * 4"
},
"STI_AMPERE_LOW_SIDE": {
"description": "stimulation ampere for nmos, unit: uA",
"type": "int",
"domain": [
1024
],
"value": "VALUE * 4"
},
"STI_VOLTAGE_AMPLITUDE": {
"description": "stimulation voltage mode, unit: Volt ",
"type": "float",
"domain": [
32
],
"value": " 2 + VALUE / 31"
},
"STI_TIMES": {
"description": "how many times will be executed",
"domain": [
256
]
},
"SYSTEM_CLOCK_RATIO": {
"description": "frequency of system clock, unit: khz",
"type": "float",
"domain": [
65536
],
"value": " 8000 / VALUE",
"guard": "SYSTEM_CLOCK_RATIO < 2"
},
"ADC_CLOCK_RATIO": {
"description": "adc sampling rate, unit: khz",
"type": "float",
"domain": [
65536
],
"value": " SYSTEM_CLOCK_RATIO / VALUE ",
"guard": "ADC_CLOCK_RATIO < 28"
},
"STI_CLOCK_RATIO": {
"description": "stimulation rate",
"type": "float",
"domain": [
65536
],
"value": "SYSTEM_CLOCK_RATIO / VALUE",
"guard": "STI_CLOCK_RATIO < 2"
},
"ARBITRARY_EN": {
"description": "arbitrary stimulation enable",
"domain": "bool"
},
"ARBITRARY_CH": {
"description": "arbitrary stimulation enable channels",
"domain": "int",
"value": " ( 1 << STI_AMP_PCHANNEL ) if (ARBITRARY_EN) else 0 "
},
"ARBITRARY_INDEX": {
"description": "define the last point of arbitrary data, from zero to arbitrary_index. ",
"domain": "INT",
"guard": "VALUE > 499"
},
"H_BRIDGE": {
"description": "whether to contruct a h bridge execute a stimulation",
"domain": "bool"
},
"STI_REF": {
"description": "bipolar or monopolar",
"domain": "bool"
},
"FAST_SETTLE": {
"description": "protect amplifier input when stimulation is executed",
"domain": "bool"
},
"UMC_TEST": {
"description": "start umc test mode",
"domain": "action",
"on_change": "umc_default"
},
"UMC_RESET": {
"description": "reset headstage to perform another setting",
"domain": "action",
"on_change": "reset"
},
"UMC_TRIGGER": {
"description": "trigger stimulation when device is in trigger mode",
"domain": "action",
"on_change": "STIMULUS"
}
},
"instruction": {
"start": [
{
"expression": "len(CHANNEL) > 0",
"raise": "no recording channel"
},
"data_format",
"_notify(True)",
"start_recording",
"umc_parameter",
"_sync(True)",
"VIS_STI"
],
"trigger stimulation": [
"umc_sti_trigger0"
],
"umc_reset": [
"VIS_RST"
],
"data_format": [
"_data_format('TDC4VAF2')"
],
"start_recording": {
"type": "RIS",
"data": [
"3b101#direct header;2b0#don't care;3b>LOW_FREQ_BAND",
"2b0#don't care;1bCHOPPER;1bFAST_SETTLE;3b>STI_WAVEFORM",
"5b>STI_AMPERE;4b>STI_PMOS",
"4b>STI_NMOS;4b>SAMPLE_RATE"
]
},
"umc_parameter": {
"type": "RIS",
"foreach-parameter": {
"parameter": "CHANNEL",
"variable": [
"a",
"b",
"c",
"d"
]
},
"data": [
"3b001#umc parameter header;3b>AMP_GAIN",
"4b>PULSE_WIDTH;6b>STI_TIMES",
"2b>STI_MODE;6b>STI_FREQ",
"1ba?;1bb?;1bc?;1bd?",
"4b>a?:0;4b>b?:0",
"4b>c?:0;4b>d?:0"
]
},
"umc_default": [
"_set('CHANNEL', 0)",
"_set('SAMPLE_RATE', 0)",
"_set('AMP_GAIN', 5)",
"_set('STI_WAVEFORM', 1)",
"_set('STI_MODE', 1)",
"_set('STI_NMOS', 0)",
"_set('STI_PMOS', 1)",
"_set('STI_AMPERE', 0)",
"_set('STI_FREQ', 0)",
"_set('STI_TIMES', 0)",
"_set('PULSE_WIDTH', 0)",
"_set('FAST_SETTLE', 1)",
"_set('CHOPPER', 0)",
"data_format",
"_notify(True)",
"umc_default0",
"_sync(True)",
"VIS_STI"
],
"umc_default0": {
"type": "RIS",
"data": [
"1B0#load umc default parameter into uni"
]
},
"umc_sti_trigger0": {
"type": "RIS",
"description": "this function is perform only in trigger mode",
"data": [
"1BC0# trigger stimulation when recording is performed"
]
}
}
}
@@ -0,0 +1,19 @@
@startuml
start
:stimulation select;
if (continuous) then (yes)
if(current mode / voltage mode) then (current mode)
:sti parameter setup;
else (voltage mode)
:sti parameter setup;
endif
else if (limited)
if(current mode / voltage mode) then (current mode)
:sti parameter setup;
else (voltage mode)
:sti parameter setup;
endif
else (disable)
endif
stop
@enduml
@@ -42,6 +42,38 @@
// clang-format on
/*
* SPI0 interface with DBS chip 2.0
*/
#define Board_SPI0_MISO PIN_UNASSIGNED
#define Board_SPI0_MOSI PIN_LSK_MOSI
#define Board_SPI0_CLK PIN_LSK_CLK
#define Board_SPI0_CS PIN_LSK_CS
/*
* SPI1 interface work with LED
*/
#define Board_SPI1_MISO PIN_UNASSIGNED
#define Board_SPI1_MOSI PIN_ASK_MOSI
#define Board_SPI1_CLK PIN_UNASSIGNED
#define Board_SPI1_CS PIN_ASK_CS
/* Power Management Board */
#define Board_SRDY Board_BP_Pin_J2_19
#define Board_MRDY Board_BP_Pin_J1_2
/* PWM outputs */
#define Board_PWMPIN0 PIN_AMP_VCK
#define Board_PWMPIN1 PIN_UNASSIGNED
#define Board_PWMPIN2 PIN_CLOCK_8M
#define Board_PWMPIN3 PIN_UNASSIGNED
#define Board_PWMPIN4 PIN_UNASSIGNED
#define Board_PWMPIN5 PIN_UNASSIGNED
#define Board_PWMPIN6 PIN_UNASSIGNED
#define Board_PWMPIN7 PIN_UNASSIGNED
#endif
static PIN_Config headstage_pin_configuration[] = { //
@@ -153,7 +153,7 @@
#define SBP_TASK_PRIORITY 1
#ifndef SBP_TASK_STACK_SIZE
#define SBP_TASK_STACK_SIZE 1024
#define SBP_TASK_STACK_SIZE 844
#endif
// Internal Events for RTOS application
@@ -408,12 +408,10 @@ static void SimpleBLEPeripheral_init(void) {
// Register for GATT local events and ATT Responses pending for transmission
GATT_RegisterForMsgs(self);
HCI_LE_ReadMaxDataLenCmd();
// HCI_LE_ReadMaxDataLenCmd();
//
// HCI_LE_WriteSuggestedDefaultDataLenCmd(251, 2120); // this is used for data length extension
HCI_LE_WriteSuggestedDefaultDataLenCmd(251, 2120); // this is used for data length extension
uint8_t prepare_write_req = 6;
GATTServApp_SetParameter(GATT_PARAM_NUM_PREPARE_WRITES, 1, &prepare_write_req);
}
#ifndef DEVICE_NAME
@@ -560,9 +558,6 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
ICall_EntityID dest;
ICall_ServiceEnum src;
ICall_HciExtEvt * message = NULL;
if (EVENT_MASK > 0) {
headstage_event_handle();
}
if (ICall_fetchServiceMsg(&src, &dest, (void **)&message) == ICALL_ERRNO_SUCCESS) {
uint8 safeToDealloc = TRUE;
@@ -586,20 +581,23 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
ICall_freeMsg(message);
}
}
}
// If RTOS queue is not empty, process app message.
while (!Queue_empty(application_message_queue)) {
sbpEvt_t *message = (sbpEvt_t *)Util_dequeueMsg(application_message_queue);
if (message) {
// Process message.
SimpleBLEPeripheral_processAppMsg(message);
// If RTOS queue is not empty, process app message.
while (!Queue_empty(application_message_queue)) {
sbpEvt_t *message = (sbpEvt_t *)Util_dequeueMsg(application_message_queue);
if (message) {
// Process message.
SimpleBLEPeripheral_processAppMsg(message);
// Free the space from the message.
ICall_free(message);
}
// Free the space from the message.
ICall_free(message);
}
}
if (EVENT_MASK > 0) {
headstage_event_handle();
}
#ifdef FEATURE_OAD
while (!Queue_empty(oad_queue_handle)) {
oadTargetWrite_t *oadWriteEvt = Queue_get(oad_queue_handle);
@@ -678,8 +676,8 @@ static uint8_t SimpleBLEPeripheral_processGATTMsg(gattMsgEvent_t *message) {
} else if (message->method == ATT_MTU_UPDATED_EVENT) {
// MTU size updated
headstage_debug_buffer[10] = 0xff;
headstage_set_debug_information();
// headstage_debug_buffer[10] = 0xff;
// headstage_set_debug_information();
} else if (message->method == ATT_HANDLE_VALUE_CFM) {
// quick pass
}
@@ -825,11 +823,11 @@ static void SimpleBLEPeripheral_processStateChangeEvt(gaprole_States_t newState)
uint8_t numActive = 0;
numActive = linkDB_NumActive();
headstage_led_spi_color(COLOR_CYAN);
headstage_led_color(COLOR_RED);
uint16_t cxnHandle;
uint16_t requestedPDUSize = 251;
uint16_t requestTxTime = 2120;
uint16_t requestedPDUSize = 251; // payload = 251 - 7 = 244 byte
uint16_t requestTxTime = 2120; // 2 ms
GAPRole_GetParameter(GAPROLE_CONNHANDLE, &cxnHandle);
if (SUCCESS != HCI_LE_SetDataLenCmd(cxnHandle, requestedPDUSize, requestTxTime)) {
@@ -841,7 +839,6 @@ static void SimpleBLEPeripheral_processStateChangeEvt(gaprole_States_t newState)
uint8_t peerAddress[B_ADDR_LEN];
GAPRole_GetParameter(GAPROLE_CONN_BD_ADDR, peerAddress);
}
flag_notify(EVT_CONNECTED);
break;
}
@@ -854,12 +851,12 @@ static void SimpleBLEPeripheral_processStateChangeEvt(gaprole_States_t newState)
// Device just timed out from a connection but is not yet advertising, is in waiting period before advertising again
// disconnected
SimpleBLEPeripheral_freeAttRsp(bleNotConnected);
headstage_led_spi_color(COLOR_RED);
headstage_led_color(COLOR_RED);
CONNECT_HANDLE = 0xFFFF;
flag_notify(EVT_DISCONNECTED);
break;
case GAPROLE_ERROR: // Error occurred - invalid state
headstage_led_spi_color(COLOR_RED);
headstage_led_color(COLOR_RED);
break;
case GAPROLE_INIT: // Waiting to be started
case GAPROLE_ADVERTISING: // Currently Advertising
@@ -84,7 +84,8 @@ extern "C" {
#define SIMPLEPROFILE_CHAR1_LEN 2
#define SIMPLEPROFILE_CHAR2_LEN 10
#define SIMPLEPROFILE_CHAR3_LEN 20
#define SIMPLEPROFILE_CHAR4_LEN 200
#define SIMPLEPROFILE_CHAR4_LEN 193
#define SIMPLEPROFILE_CHAR4_LEN 20 // 8 header + 3n data, n=3
#define SIMPLEPROFILE_CHAR5_LEN 20
/*********************************************************************