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merge into: wisetop/past-project-past_code_cc2650:neulive2_E7DA_special_version
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wisetop/past-project-past_code_cc2650:master wisetop/past-project-past_code_cc2650:EliteEIS_AutoCali wisetop/past-project-past_code_cc2650:Elite_1.5_Taylor_061721 wisetop/past-project-past_code_cc2650:Elite1.5_AutoCali wisetop/past-project-past_code_cc2650:simple_central_ma_pin wisetop/past-project-past_code_cc2650:Elite1.5 wisetop/past-project-past_code_cc2650:release/elite_211202-2 wisetop/past-project-past_code_cc2650:release/elite_211216 wisetop/past-project-past_code_cc2650:e_Elite15_ccmode_1124 wisetop/past-project-past_code_cc2650:Elite_TRIG01_20210922 wisetop/past-project-past_code_cc2650:simple_central_ma_pin_one_four wisetop/past-project-past_code_cc2650:Elite1.5_Vout_in_RT_0628 wisetop/past-project-past_code_cc2650:central_separate_c_file wisetop/past-project-past_code_cc2650:Elite1.5-re_calibration wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv wisetop/past-project-past_code_cc2650:EliteEIS_Taylor wisetop/past-project-past_code_cc2650:Elite_TRIG01_development wisetop/past-project-past_code_cc2650:simple_central_ma_pin_0513_2 wisetop/past-project-past_code_cc2650:EliteEIS_developement_Roy wisetop/past-project-past_code_cc2650:neulive20_onchange_multiStageSTI wisetop/past-project-past_code_cc2650:Elite1.5_sps wisetop/past-project-past_code_cc2650:Offline_BS wisetop/past-project-past_code_cc2650:Elite_NueLive_FFT wisetop/past-project-past_code_cc2650:Elite1.5_dev_module wisetop/past-project-past_code_cc2650:Elite_TRIG_mega_0217 wisetop/past-project-past_code_cc2650:neulive2_E7DA_special_version wisetop/past-project-past_code_cc2650:simple_central_ma_pin_linux wisetop/past-project-past_code_cc2650:EliteEIS_developement wisetop/past-project-past_code_cc2650:EliteEIS_developement_jim wisetop/past-project-past_code_cc2650:neulive20_development_onchange_central wisetop/past-project-past_code_cc2650:Elite1.5_development_cali_mode wisetop/past-project-past_code_cc2650:Elite1.5_developement_magafly wisetop/past-project-past_code_cc2650:central_BS_triangle_wave wisetop/past-project-past_code_cc2650:central_borshin wisetop/past-project-past_code_cc2650:Neulive20_hostTest wisetop/past-project-past_code_cc2650:neulive_onchange_central_debug wisetop/past-project-past_code_cc2650:animal_experience wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_release_1103 wisetop/past-project-past_code_cc2650:neulive20_borshin_fft wisetop/past-project-past_code_cc2650:neulive20_stable_non_central wisetop/past-project-past_code_cc2650:Neulive2.0_developement wisetop/past-project-past_code_cc2650:neulive20_development_without_central wisetop/past-project-past_code_cc2650:Elite1.5_developement_EventHandle wisetop/past-project-past_code_cc2650:neulive20_nordic_testing wisetop/past-project-past_code_cc2650:Neulive20_developement_linux wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_calibration_CHAO-I_BAT01 wisetop/past-project-past_code_cc2650:neulive20_linux_debug wisetop/past-project-past_code_cc2650:release/elite1.4-0720_2 wisetop/past-project-past_code_cc2650:simple_central_ma_linux wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_test_connect_interval wisetop/past-project-past_code_cc2650:host_test_KIN_linux wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_BAT01 wisetop/past-project-past_code_cc2650:Elite_BAT wisetop/past-project-past_code_cc2650:Neulive2_close_loop_BS wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_calibration_CHAO-I wisetop/past-project-past_code_cc2650:Neulive2_closeLoop wisetop/past-project-past_code_cc2650:CentralDataRateTest_neulive2 wisetop/past-project-past_code_cc2650:Elite_OBJ_calibration wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_addCV3_15 wisetop/past-project-past_code_cc2650:MemBoard_simple_central wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_release_0602 wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mV_addCV3_modify_shift wisetop/past-project-past_code_cc2650:central_pseudo_controller wisetop/past-project-past_code_cc2650:simple_central_lp_pin wisetop/past-project-past_code_cc2650:neulive20_blastData wisetop/past-project-past_code_cc2650:neu_data_rate_test wisetop/past-project-past_code_cc2650:Elite15_by_BENNY wisetop/past-project-past_code_cc2650:Debug_channel_mux wisetop/past-project-past_code_cc2650:Modify_Pramble_Header_Detection wisetop/past-project-past_code_cc2650:neuliveSTI/1210 wisetop/past-project-past_code_cc2650:host_test/master wisetop/past-project-past_code_cc2650:HostTest_developement wisetop/past-project-past_code_cc2650:elite_0.2_ship_dead_tabby_Cat wisetop/past-project-past_code_cc2650:Elite_OBJ_Version wisetop/past-project-past_code_cc2650:fix_channel_pointer wisetop/past-project-past_code_cc2650:Elite14_battery wisetop/past-project-past_code_cc2650:Neulive20_MergeWith13 wisetop/past-project-past_code_cc2650:neulive13_cali_new_0218 wisetop/past-project-past_code_cc2650:refix2 wisetop/past-project-past_code_cc2650:refix_channel_pointer wisetop/past-project-past_code_cc2650:modify_header_detection wisetop/past-project-past_code_cc2650:add_HCI wisetop/past-project-past_code_cc2650:Neulive20_8bitSPI wisetop/past-project-past_code_cc2650:neulive13_cali_new_0206 wisetop/past-project-past_code_cc2650:neulive13_cdr_cali wisetop/past-project-past_code_cc2650:Test_HCI wisetop/past-project-past_code_cc2650:Neulive13_YC_12/3 wisetop/past-project-past_code_cc2650:neulive2.0_16bit_SPI wisetop/past-project-past_code_cc2650:Neulive20_CHC wisetop/past-project-past_code_cc2650:Elite_Square_current wisetop/past-project-past_code_cc2650:neulive/development wisetop/past-project-past_code_cc2650:Neulive13_YC wisetop/past-project-past_code_cc2650:Memory_Board_KIM wisetop/past-project-past_code_cc2650:Elite_PSCurve wisetop/past-project-past_code_cc2650:Elite_CC_TempBranch wisetop/past-project-past_code_cc2650:Elite_master wisetop/past-project-past_code_cc2650:Elite_Earth_calibration wisetop/past-project-past_code_cc2650:Elite_calibration wisetop/past-project-past_code_cc2650:Elite_SmallZTcurve wisetop/past-project-past_code_cc2650:release/neulive wisetop/past-project-past_code_cc2650:EliteNewFormatNotify wisetop/past-project-past_code_cc2650:Elite_development wisetop/past-project-past_code_cc2650:origin/Elite_14re_demo wisetop/past-project-past_code_cc2650:elite_zm/alan wisetop/past-project-past_code_cc2650:neulive2.0/master wisetop/past-project-past_code_cc2650:Elite_LaunchPadTest wisetop/past-project-past_code_cc2650:neuliveSTI/master wisetop/past-project-past_code_cc2650:release/host_test-0.5.0 wisetop/past-project-past_code_cc2650:release/neulive1.2-demo-0.1 wisetop/past-project-past_code_cc2650:release/neulive1.2-demo-0.2 wisetop/past-project-past_code_cc2650:release/neulive1.2-30m
wisetop/past-project-past_code_cc2650:release-2.0 wisetop/past-project-past_code_cc2650:host-test-v0.5.0 wisetop/past-project-past_code_cc2650:neulive-1.2-demo-0.1 wisetop/past-project-past_code_cc2650:neulive-1.2-30m wisetop/past-project-past_code_cc2650:host-test-v0.4.0 wisetop/past-project-past_code_cc2650:host-test-v0.3.0 wisetop/past-project-past_code_cc2650:host-test-v0.2.0
...
pull from: wisetop/past-project-past_code_cc2650:Neulive20_8bitSPI
Branches Tags
wisetop/past-project-past_code_cc2650:EliteEIS_AutoCali wisetop/past-project-past_code_cc2650:Elite_1.5_Taylor_061721 wisetop/past-project-past_code_cc2650:Elite1.5_AutoCali wisetop/past-project-past_code_cc2650:simple_central_ma_pin wisetop/past-project-past_code_cc2650:Elite1.5 wisetop/past-project-past_code_cc2650:release/elite_211202-2 wisetop/past-project-past_code_cc2650:release/elite_211216 wisetop/past-project-past_code_cc2650:e_Elite15_ccmode_1124 wisetop/past-project-past_code_cc2650:Elite_TRIG01_20210922 wisetop/past-project-past_code_cc2650:simple_central_ma_pin_one_four wisetop/past-project-past_code_cc2650:Elite1.5_Vout_in_RT_0628 wisetop/past-project-past_code_cc2650:central_separate_c_file wisetop/past-project-past_code_cc2650:Elite1.5-re_calibration wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv wisetop/past-project-past_code_cc2650:EliteEIS_Taylor wisetop/past-project-past_code_cc2650:Elite_TRIG01_development wisetop/past-project-past_code_cc2650:simple_central_ma_pin_0513_2 wisetop/past-project-past_code_cc2650:EliteEIS_developement_Roy wisetop/past-project-past_code_cc2650:neulive20_onchange_multiStageSTI wisetop/past-project-past_code_cc2650:Elite1.5_sps wisetop/past-project-past_code_cc2650:Offline_BS wisetop/past-project-past_code_cc2650:Elite_NueLive_FFT wisetop/past-project-past_code_cc2650:Elite1.5_dev_module wisetop/past-project-past_code_cc2650:Elite_TRIG_mega_0217 wisetop/past-project-past_code_cc2650:neulive2_E7DA_special_version wisetop/past-project-past_code_cc2650:simple_central_ma_pin_linux wisetop/past-project-past_code_cc2650:EliteEIS_developement wisetop/past-project-past_code_cc2650:EliteEIS_developement_jim wisetop/past-project-past_code_cc2650:neulive20_development_onchange_central wisetop/past-project-past_code_cc2650:Elite1.5_development_cali_mode wisetop/past-project-past_code_cc2650:Elite1.5_developement_magafly wisetop/past-project-past_code_cc2650:central_BS_triangle_wave wisetop/past-project-past_code_cc2650:central_borshin wisetop/past-project-past_code_cc2650:Neulive20_hostTest wisetop/past-project-past_code_cc2650:neulive_onchange_central_debug wisetop/past-project-past_code_cc2650:animal_experience wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_release_1103 wisetop/past-project-past_code_cc2650:neulive20_borshin_fft wisetop/past-project-past_code_cc2650:neulive20_stable_non_central wisetop/past-project-past_code_cc2650:Neulive2.0_developement wisetop/past-project-past_code_cc2650:neulive20_development_without_central wisetop/past-project-past_code_cc2650:Elite1.5_developement_EventHandle wisetop/past-project-past_code_cc2650:neulive20_nordic_testing wisetop/past-project-past_code_cc2650:Neulive20_developement_linux wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_calibration_CHAO-I_BAT01 wisetop/past-project-past_code_cc2650:neulive20_linux_debug wisetop/past-project-past_code_cc2650:release/elite1.4-0720_2 wisetop/past-project-past_code_cc2650:simple_central_ma_linux wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_test_connect_interval wisetop/past-project-past_code_cc2650:host_test_KIN_linux wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_BAT01 wisetop/past-project-past_code_cc2650:Elite_BAT wisetop/past-project-past_code_cc2650:Neulive2_close_loop_BS wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_calibration_CHAO-I wisetop/past-project-past_code_cc2650:Neulive2_closeLoop wisetop/past-project-past_code_cc2650:CentralDataRateTest_neulive2 wisetop/past-project-past_code_cc2650:Elite_OBJ_calibration wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_addCV3_15 wisetop/past-project-past_code_cc2650:MemBoard_simple_central wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mv_release_0602 wisetop/past-project-past_code_cc2650:Elite_OBJ_0.2mV_addCV3_modify_shift wisetop/past-project-past_code_cc2650:central_pseudo_controller wisetop/past-project-past_code_cc2650:simple_central_lp_pin wisetop/past-project-past_code_cc2650:neulive20_blastData wisetop/past-project-past_code_cc2650:neu_data_rate_test wisetop/past-project-past_code_cc2650:Elite15_by_BENNY wisetop/past-project-past_code_cc2650:Debug_channel_mux wisetop/past-project-past_code_cc2650:Modify_Pramble_Header_Detection wisetop/past-project-past_code_cc2650:neuliveSTI/1210 wisetop/past-project-past_code_cc2650:host_test/master wisetop/past-project-past_code_cc2650:HostTest_developement wisetop/past-project-past_code_cc2650:elite_0.2_ship_dead_tabby_Cat wisetop/past-project-past_code_cc2650:Elite_OBJ_Version wisetop/past-project-past_code_cc2650:fix_channel_pointer wisetop/past-project-past_code_cc2650:Elite14_battery wisetop/past-project-past_code_cc2650:Neulive20_MergeWith13 wisetop/past-project-past_code_cc2650:neulive13_cali_new_0218 wisetop/past-project-past_code_cc2650:refix2 wisetop/past-project-past_code_cc2650:refix_channel_pointer wisetop/past-project-past_code_cc2650:modify_header_detection wisetop/past-project-past_code_cc2650:add_HCI wisetop/past-project-past_code_cc2650:Neulive20_8bitSPI wisetop/past-project-past_code_cc2650:neulive13_cali_new_0206 wisetop/past-project-past_code_cc2650:neulive13_cdr_cali wisetop/past-project-past_code_cc2650:Test_HCI wisetop/past-project-past_code_cc2650:Neulive13_YC_12/3 wisetop/past-project-past_code_cc2650:neulive2.0_16bit_SPI wisetop/past-project-past_code_cc2650:Neulive20_CHC wisetop/past-project-past_code_cc2650:Elite_Square_current wisetop/past-project-past_code_cc2650:neulive/development wisetop/past-project-past_code_cc2650:Neulive13_YC wisetop/past-project-past_code_cc2650:Memory_Board_KIM wisetop/past-project-past_code_cc2650:Elite_PSCurve wisetop/past-project-past_code_cc2650:Elite_CC_TempBranch wisetop/past-project-past_code_cc2650:Elite_master wisetop/past-project-past_code_cc2650:Elite_Earth_calibration wisetop/past-project-past_code_cc2650:Elite_calibration wisetop/past-project-past_code_cc2650:Elite_SmallZTcurve wisetop/past-project-past_code_cc2650:release/neulive wisetop/past-project-past_code_cc2650:master wisetop/past-project-past_code_cc2650:EliteNewFormatNotify wisetop/past-project-past_code_cc2650:Elite_development wisetop/past-project-past_code_cc2650:origin/Elite_14re_demo wisetop/past-project-past_code_cc2650:elite_zm/alan wisetop/past-project-past_code_cc2650:neulive2.0/master wisetop/past-project-past_code_cc2650:Elite_LaunchPadTest wisetop/past-project-past_code_cc2650:neuliveSTI/master wisetop/past-project-past_code_cc2650:release/host_test-0.5.0 wisetop/past-project-past_code_cc2650:release/neulive1.2-demo-0.1 wisetop/past-project-past_code_cc2650:release/neulive1.2-demo-0.2 wisetop/past-project-past_code_cc2650:release/neulive1.2-30m
wisetop/past-project-past_code_cc2650:release-2.0 wisetop/past-project-past_code_cc2650:host-test-v0.5.0 wisetop/past-project-past_code_cc2650:neulive-1.2-demo-0.1 wisetop/past-project-past_code_cc2650:neulive-1.2-30m wisetop/past-project-past_code_cc2650:host-test-v0.4.0 wisetop/past-project-past_code_cc2650:host-test-v0.3.0 wisetop/past-project-past_code_cc2650:host-test-v0.2.0

223 Commits
neulive2_E7DA_special_version ... Neulive20_8bitSPI

Author SHA1 Message Date
weiting2 a82ad36975 SPI should be phase 1 2020-02-12 11:20:57 +08:00
weiting2 2320d5b757 mimic neu1.3_12/3 version 2020-02-11 11:43:41 +08:00
weiting2 db02c38a47 mimic neu1.3_12/3 version 2020-02-11 10:35:59 +08:00
weiting2 550b3c1158 mimic neu1.3_12/3 version 2020-02-10 17:15:01 +08:00
weiting2 d6070848b6 SBP_TASK_STACK_SIZE 1024 => 844 
I am not sure what will happen
 2020-02-10 16:40:57 +08:00
weiting2 0eecf13936 disable data length extension 2020-02-10 16:02:50 +08:00
yichin 4dd471961a error fix 2020-02-04 14:32:24 +08:00
weiting2 3021f65838 discard illegal channel data 2020-02-04 14:22:34 +08:00
weiting2 d355defa2d fix warning 2020-01-22 16:18:30 +08:00
weiting2 9f3f3335fc test mode using ch2 2020-01-22 16:16:11 +08:00
weiting2 0c5632fe30 3PIN SPI 2020-01-21 11:12:43 +08:00
weiting2 2a4924c5b2 4PIN SPI 2020-01-20 17:38:24 +08:00
weiting2 19ec8c4d6f 8bit spi without CS 2020-01-17 17:22:00 +08:00
weiting2 a232f2d795 8bit spi without CS 2020-01-17 17:11:21 +08:00
yichin 3090e2b4ea 8bit SPI 2020-01-17 14:55:56 +08:00
weiting2 162731f640 read spi_rxbuf 2020-01-17 10:25:32 +08:00
weiting2 8a63dd49c7 read spi_rxbuf 2020-01-17 10:16:28 +08:00
weiting2 e707c0a3d9 read spi_rxbuf 2020-01-17 10:10:59 +08:00
weiting2 83fb7687bb append notify in SPI callback 2020-01-16 18:08:28 +08:00
weiting2 55d6f5c565 append notify in SPI callback 2020-01-16 17:51:02 +08:00
weiting2 d5cd66f026 append notify in SPI callback 2020-01-16 17:14:25 +08:00
weiting2 9fd7987327 append notify in SPI callback 2020-01-16 17:11:04 +08:00
weiting2 6339640eb7 notify channel send correctly? 2020-01-16 17:03:53 +08:00
weiting2 dc7c3f8e99 notify channel send correctly? 2020-01-16 16:54:57 +08:00
weiting2 bd5c75d1b1 VIS_RST/INT will reset 2650 correctly 2020-01-16 12:33:39 +08:00
weiting2 fddf3535f3 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:49:19 +08:00
weiting2 d8b4221d81 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:40:16 +08:00
weiting2 c5af1e0959 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:34:31 +08:00
weiting2 4135a823e3 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:21:15 +08:00
weiting2 507c0cd439 VIS_RST/INT will reset 2650 correctly 2020-01-15 18:03:31 +08:00
weiting2 cc54e95b30 VIS_RST/INT will reset 2650 correctly 2020-01-15 17:49:39 +08:00
yichin c084dfd67a error fix 2020-01-15 17:20:59 +08:00
weiting2 8c7424bf5b VIS_RST/INT will reset 2650 correctly 2020-01-15 17:19:15 +08:00
weiting2 235140c10b VIS_RST/INT will reset 2650 correctly 2020-01-15 16:47:59 +08:00
weiting2 6f9b279a82 VIS_RST/INT will reset 2650 correctly 2020-01-15 16:44:59 +08:00
weiting2 512bac4f80 VIS_RST/INT will reset 2650 correctly 2020-01-15 16:19:09 +08:00
weiting2 1353e192c2 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 
# Conflicts:
#	simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_neu.h
 2020-01-14 17:19:03 +08:00
weiting2 f0eb5da80e check SPI MOSI channel 2020-01-14 17:18:12 +08:00
yichin f8fb36ca26 disable sti in test mode 2020-01-14 16:57:15 +08:00
weiting2 3c2970e36f check SPI MOSI channel 2020-01-14 16:02:19 +08:00
weiting2 f829c2af1a check SPI MOSI channel 2020-01-14 15:24:36 +08:00
weiting2 7710283346 check SPI MOSI channel 2020-01-14 14:22:19 +08:00
weiting2 1aac170954 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2020-01-14 13:57:38 +08:00
weiting2 f13df95710 check SPI MOSI channel 2020-01-14 11:21:21 +08:00
yichin e97ce556dd Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2020-01-14 10:32:48 +08:00
weiting2 504088b534 check SPI MOSI channel 2020-01-14 10:30:28 +08:00
yichin 06a6010cf3 test 2020-01-13 16:08:07 +08:00
yichin f006ef75d5 change amp vck (poly r pwm) 2020-01-10 15:30:21 +08:00
yichin c5f06cd076 change amp vck (poly r pwm) 2020-01-10 11:49:44 +08:00
yichin e2f2b88e80 commit 2020-01-09 16:46:02 +08:00
yichin 7cbe888f39 error fix 2020-01-09 12:38:55 +08:00
yichin 7121a12737 error fix 2020-01-07 16:10:17 +08:00
yichin 68e395a86c error fix 2020-01-07 15:07:00 +08:00
weiting2 48eb5f0196 test NEU 2.0 instruction 2020-01-07 15:00:09 +08:00
weiting2 5fdd0a1e07 test NEU 2.0 reset 2020-01-07 14:14:59 +08:00
weiting2 157676b29d test NEU 2.0 reset 2020-01-07 13:37:01 +08:00
weiting2 53ba84d5d3 test NEU 2.0 reset 2020-01-07 11:33:13 +08:00
weiting2 50da5a1876 test NEU 2.0 reset 2020-01-07 11:20:39 +08:00
weiting2 5e42dc0056 test NEU 2.0 reset 2020-01-07 11:03:30 +08:00
weiting2 5e53b7d651 test NEU 2.0 reset 2020-01-07 10:32:56 +08:00
weiting2 b129f2b7d4 test NEU 2.0 2020-01-06 18:53:34 +08:00
weiting2 5502099315 test NEU 2.0 2020-01-06 18:47:59 +08:00
weiting2 a3670d0e9a test NEU 2.0 2020-01-06 18:11:43 +08:00
yichin 6f8479770d Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2020-01-06 17:37:18 +08:00
weiting2 d89744b1c7 ADC clock & amp gain instruction 2020-01-06 17:36:34 +08:00
yichin 224475f342 error fix 2020-01-06 11:41:23 +08:00
yichin 7164b5f6c3 error fix 2020-01-06 11:39:20 +08:00
weiting2 0406cdea67 neu2.1 pin assign 2020-01-06 10:55:38 +08:00
weiting2 91787a5bb4 neu2.0 UI work well 2019-12-19 15:11:40 +08:00
weiting2 1c074fd180 notify should include device ID QQQQQ 2019-12-19 15:08:53 +08:00
weiting2 a5051dd42b notify should include device ID QQQQQ 2019-12-19 15:02:33 +08:00
weiting2 d1583ba5e1 notify should include device ID QQQQQ 2019-12-19 14:56:04 +08:00
weiting2 cc48dab88b notify should include device ID QQQQQ 2019-12-19 14:55:23 +08:00
weiting2 82383bbfcf Slow down notify speed. Check if memory board write correctly 2019-12-18 18:01:02 +08:00
weiting2 99a45314ae Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-18 16:45:33 +08:00
weiting2 17c501b855 Slow down notify speed. Check if memory board write correctly 2019-12-18 16:45:19 +08:00
yichin 1933ccbfe7 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-18 16:09:44 +08:00
weiting2 092b848c4d Slow down notify speed. Check if memory board write correctly 2019-12-18 16:08:50 +08:00
weiting2 8597e29a8a TODO: speed up ADC clock 2019-12-16 17:47:37 +08:00
weiting2 f3b8d74f82 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-13 14:31:54 +08:00
weiting2 4d3dee1c40 DBS clk_src = 4M, spi 400K 2019-12-13 14:31:23 +08:00
weiting2 ca70cba3bf DBS clk_src = 5M, spi 500K 2019-12-13 14:30:32 +08:00
weiting2 5ec4104255 DBS clk_src = 5M, spi 500K 2019-12-13 14:27:45 +08:00
weiting2 bb1ec23e02 DBS clk_src = 6M, spi 600K 2019-12-13 14:25:14 +08:00
weiting2 1615914ce4 DBS clk_src = 6M, spi 600K 2019-12-13 14:23:20 +08:00
weiting2 7b33bb5916 DBS clk_src = 4M, spi 4K 2019-12-13 14:20:56 +08:00
weiting2 0c22389b52 test pure SPI (receive DBS SPI only 2019-12-13 14:09:26 +08:00
weiting2 067281c449 test pure SPI (receive DBS SPI only 2019-12-13 11:57:49 +08:00
weiting2 74273f1469 test pure SPI (receive DBS SPI only 2019-12-13 11:21:53 +08:00
weiting2 07d606f5a9 test pure SPI (receive DBS SPI only 2019-12-13 11:17:18 +08:00
weiting2 aac9d26052 test pure SPI (receive DBS SPI only 2019-12-13 10:44:55 +08:00
weiting2 58c398e73f test pure SPI (receive DBS SPI only 2019-12-13 10:34:38 +08:00
weiting2 b81c5eb6ce test pure SPI (receive DBS SPI only 2019-12-13 09:49:18 +08:00
weiting2 e91089016e test pure SPI (receive DBS SPI only 2019-12-12 17:57:18 +08:00
weiting2 68f1cbf030 test pure SPI (receive DBS SPI only 2019-12-12 17:40:57 +08:00
weiting2 d73dccbefe test notify 2019-12-12 12:13:44 +08:00
weiting2 75f62f2a3e test notify 2019-12-12 12:04:00 +08:00
weiting2 a28b9ffd35 test notify 2019-12-12 10:38:49 +08:00
weiting2 bd6f745033 test notify 2019-12-12 09:55:27 +08:00
weiting2 54c6d2a217 test notify 2019-12-12 09:35:44 +08:00
weiting2 06bdc3aee4 test notify 2019-12-11 17:24:17 +08:00
weiting2 4c387980c8 test notify 2019-12-11 17:14:56 +08:00
YiChin 00ee10a94a Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 13:54:02 +08:00
weiting2 7a7aaf62a7 flush timestamp register before start PeriodicEvent 2019-12-11 13:53:05 +08:00
YiChin 62e24a2323 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 13:41:42 +08:00
weiting2 eb17de7490 test read data 2019-12-11 11:40:17 +08:00
YiChin aa336be8df Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 10:45:50 +08:00
weiting2 a06d1a1849 test read data 2019-12-11 10:45:18 +08:00
YiChin d153d91e71 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 10:38:15 +08:00
weiting2 8cb6594197 test read data 2019-12-11 10:37:46 +08:00
YiChin e44e6f511d Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-11 10:25:02 +08:00
weiting2 f440f56b3c test read data 2019-12-11 10:21:39 +08:00
weiting2 8968967ad1 test read data 2019-12-10 19:08:17 +08:00
YiChin 6abab9fe6b Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 17:45:00 +08:00
weiting2 cf481d482a test read data 2019-12-10 17:44:39 +08:00
YiChin 91b11fe3d9 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 17:29:24 +08:00
weiting2 96a44ad200 test read data 2019-12-10 17:29:00 +08:00
weiting2 b6fd48f9d9 test read data 2019-12-10 17:22:13 +08:00
weiting2 3d9c3f4e1e test read data 2019-12-10 11:48:54 +08:00
YiChin 05561a9959 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 11:43:24 +08:00
weiting2 fcd350c0d4 test read data 2019-12-10 11:42:02 +08:00
YiChin d07f8636dd Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 11:23:36 +08:00
weiting2 91315be16f test read data 2019-12-10 11:23:17 +08:00
weiting2 898bd81599 test read data 2019-12-10 11:06:16 +08:00
YiChin 8a92a1ba8b Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 10:47:59 +08:00
weiting2 7c83a01731 test read data 2019-12-10 10:47:37 +08:00
YiChin c05a76bd6d Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 10:36:49 +08:00
weiting2 425414dd2d test read data 2019-12-10 10:36:28 +08:00
YiChin 65c85aca40 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 10:27:25 +08:00
weiting2 1664a2cabd test read data 2019-12-10 10:27:03 +08:00
YiChin c207965207 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-10 10:02:50 +08:00
weiting2 7680879264 test read data 2019-12-10 10:00:38 +08:00
YiChin 031600d62a Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 18:32:47 +08:00
weiting2 0ce86bb4dd test read data 2019-12-09 18:32:26 +08:00
YiChin b848182595 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 18:05:35 +08:00
weiting2 54b48ef57d test read data 2019-12-09 18:04:37 +08:00
YiChin 03cbcdce49 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 16:35:44 +08:00
weiting2 52d51de3fd test read data 2019-12-09 16:35:19 +08:00
YiChin f65817e18c Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 16:27:22 +08:00
weiting2 6f6fffa84a test read data 2019-12-09 16:26:47 +08:00
YiChin fdb667ce8c Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 16:07:37 +08:00
weiting2 808c042c5a test read data 2019-12-09 16:07:06 +08:00
YiChin 09c1b3193d Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 15:52:50 +08:00
weiting2 c39b3d83f7 test read data 2019-12-09 15:52:27 +08:00
YiChin 1b72ead038 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 
# Conflicts:
#	simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_neu.h
 2019-12-09 15:42:02 +08:00
weiting2 68645bab82 test read data 2019-12-09 15:41:26 +08:00
YiChin 21e366b601 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 15:13:22 +08:00
weiting2 e129608ad0 test read data 2019-12-09 15:13:00 +08:00
YiChin 4aadcbdefe Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-09 11:44:03 +08:00
weiting2 bcf3442aa5 test read data 2019-12-09 11:43:19 +08:00
YiChin 8b34a9b39f Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 16:29:51 +08:00
weiting2 ce70363247 test read data 2019-12-06 16:29:32 +08:00
YiChin 0143d16b48 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 16:25:48 +08:00
weiting2 b8c00d825e test read data 2019-12-06 16:25:27 +08:00
YiChin d0ecad7862 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 15:22:25 +08:00
weiting2 d16038974c test read data 2019-12-06 15:21:51 +08:00
YiChin dd9198c548 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 14:55:56 +08:00
weiting2 371c6b1f83 test read data 2019-12-06 14:55:34 +08:00
YiChin 877642fe15 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 14:27:41 +08:00
weiting2 c7d5dc7330 test read data 2019-12-06 14:27:10 +08:00
YiChin 40a0025ffc Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 14:07:52 +08:00
weiting2 528649f909 test read data 2019-12-06 14:07:28 +08:00
YiChin 83c19f1e93 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 13:54:15 +08:00
weiting2 57ec1ad0c6 test read data 2019-12-06 13:53:47 +08:00
YiChin 555bd907fb Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 13:33:46 +08:00
weiting2 695cac4cf0 test read data 2019-12-06 13:33:09 +08:00
YiChin cf4f4627c9 Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 2019-12-06 12:25:50 +08:00
weiting2 b74451a18a test read data 2019-12-06 12:23:39 +08:00
YiChin 61be6c01fc test recording notify 2019-12-04 16:34:26 +08:00
weiting2 c1f8e263d4 test recording 2019-12-04 16:32:29 +08:00
weiting2 fe19490b23 test recording 2019-12-04 15:34:42 +08:00
YiChin e49efd8798 RIS has au unknown error 2019-12-04 15:34:08 +08:00
YiChin d1c70811b4 RIS has au unknown error 2019-12-04 14:25:06 +08:00
weiting2 03667cb36c test recording 2019-12-04 14:08:36 +08:00
weiting2 c1a2b184f6 add t1~t5 ins 2019-12-03 12:55:01 +08:00
weiting2 3f831ff84c check instruction 2019-11-29 18:31:00 +08:00
weiting2 d8c61db417 check instruction 2019-11-29 13:59:09 +08:00
weiting2 dacf0d1055 check INSTRUCTION and RIS 2019-11-28 18:30:36 +08:00
weiting2 cfc68885c8 check INSTRUCTION and RIS 2019-11-28 17:59:11 +08:00
weiting2 b841454957 [IV] default output Volt is Vin instead of Vout 2019-11-27 10:25:27 +08:00
weiting2 882b5efbd0 [Neu 2.0] give up read and send MOSI 2019-11-26 14:46:35 +08:00
weiting2 5c33c0130a [Neu 2.0] attempt to read and send MOSI 2019-11-26 14:33:56 +08:00
weiting2 46d0c4b09e [Neu 2.0] attempt to read and send MOSI 2019-11-26 14:32:08 +08:00
weiting2 48924b400b [Neu 2.0] attempt to read and send MOSI 2019-11-26 14:07:06 +08:00
weiting2 1b6aeb1f70 [Neu 2.0] attempt to read and send MOSI 2019-11-26 13:31:22 +08:00
weiting2 3fc364134a [Neu 2.0] attempt to read and send MOSI 2019-11-26 11:55:35 +08:00
weiting2 fa522254f3 [Neu 2.0] attempt to read and send MOSI 2019-11-26 11:47:52 +08:00
YiChin 8c41b0a976 read spi 2019-11-26 11:44:04 +08:00
weiting2 cf7d0616ad [Neu 2.0] attempt to read and send MOSI 2019-11-26 11:20:06 +08:00
weiting2 25d7722d93 [Neu 2.0] attempt to read and send MOSI 2019-11-26 11:16:55 +08:00
weiting2 336b325f03 [Neu 2.0] SPI callback flush SPI twice 2019-11-26 10:58:49 +08:00
weiting2 246f871ba7 [Neu 2.0] SPI callback flush SPI twice 2019-11-26 10:52:51 +08:00
weiting2 96b61d364e [Neu 2.0] SPI callback using a switch 2019-11-26 10:26:12 +08:00
weiting2 eba70d4af7 Neulive 2.0 test SPI conti trans speed 2019-11-25 18:44:04 +08:00
weiting2 b24a275019 Neulive 2.0 test SPI conti trans speed 2019-11-25 18:37:38 +08:00
weiting2 7621490d13 Neulive 2.0 fix instruction bug 2019-11-25 12:36:59 +08:00
weiting2 eb17cda0dc Neulive 2.0 comment UART 2019-11-25 11:59:42 +08:00
weiting2 cd1bc37e62 Neulive 2.0 add cb func 2019-11-25 11:43:05 +08:00
weiting2 c151eb1fab Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 18:12:45 +08:00
weiting2 4782c604c5 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 17:53:55 +08:00
weiting2 de908817c4 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 17:51:58 +08:00
YiChin e853241537 add pin define macro for 2.0 2019-11-22 17:33:00 +08:00
YiChin 097c475e5f comment R/G LED 2019-11-22 17:27:35 +08:00
YiChin 3e64d122de Merge remote-tracking branch 'origin/neulive2.0/development' into neulive2.0/development 
# Conflicts:
#	simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_neu.h
 2019-11-22 17:26:18 +08:00
YiChin 466a6627ef comment R/G LED 2019-11-22 17:24:59 +08:00
weiting2 c08ea10397 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 16:52:32 +08:00
weiting2 500b9b00fd Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 16:45:30 +08:00
weiting2 b06bba4333 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 14:39:14 +08:00
weiting2 0eeb973e15 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 14:27:34 +08:00
weiting2 46f797f083 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 14:23:13 +08:00
weiting2 d24cde42b5 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 13:26:49 +08:00
weiting2 19bc7d23db Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 12:29:30 +08:00
weiting2 3849a25e7f Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 12:21:09 +08:00
weiting2 4c760ac644 Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 11:25:50 +08:00
weiting2 ba990ce65f Neulive 2.0 lauchpad SPI test add LED test 2019-11-22 10:16:53 +08:00
weiting2 0ef19c37dc Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 18:20:44 +08:00
weiting2 469c06390a Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 14:51:47 +08:00
weiting2 f09e440b45 Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 14:45:29 +08:00
weiting2 4e82451108 Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 14:39:10 +08:00
weiting2 d21613cee8 Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 13:32:47 +08:00
weiting2 b8308303fc Neulive 2.0 lauchpad SPI test add LED test 2019-11-21 13:32:26 +08:00
weiting2 80f9d63a09 Neulive 2.0 lauchpad SPI test 2019-11-20 13:09:56 +08:00
yichin 81945184d1 data rate test for memory board 2019-11-18 13:44:13 +08:00
27 changed files with 1246 additions and 562 deletions
Expand all files Collapse all files
simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/app/.ccsproject
+1 -1
View File
@@ -9,6 +9,6 @@
<linkerCommandFile value="cc26x0f128.cmd"/>
<rts value="libc.a"/>
<createSlaveProjects value=""/>
<connection value="common/targetdb/connections/TIXDS100v3_Dot7_Connection.xml"/>
<connection value="common/targetdb/connections/TIXDS110_Connection.xml"/>
<isTargetManual value="false"/>
</projectOptions>
simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/app/.cproject
+268 -130
View File
@@ -18,141 +18,279 @@
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<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.TIRTOSCC13XX_CC26XX:2.21.01.08;"/>
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<listOptionValue builtIn="false" value="LINK_ORDER=TOOLS/ccs_linker_defines.cmd;TOOLS/cc26xx_app.cmd;"/>
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/app/.launches/simple_peripheral_cc2650em_app.launch
+1 -1
View File
@@ -12,7 +12,7 @@
<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_TARGET_CONFIG" value="${target_config_active_default:simple_peripheral_cc2650em_app}"/>
<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS100v3 USB Debug Probe_0/Cortex_M3_0" value="C:/ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\FlashROM\simple_peripheral_cc2650em_app.out"/>
<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS110 USB Debug Probe/Cortex_M3_0" value="C:/ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\FlashROM\simple_peripheral_cc2650em_app.out"/>
<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS110 USB Debug Probe_0/Cortex_M3_0" value="C:/ti\ccsv8\ccs_base\emulation\gel\images\cc26xx\cc26x0_rtos_rom_syms.out"/>
<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS110 USB Debug Probe_0/Cortex_M3_0" value="C:/ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\app\FlashROM\simple_peripheral_cc2650em_app.out"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/simple_peripheral_cc2650em_app"/>
</listAttribute>
simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/app/targetConfigs/CC2650F128.ccxml
+15 -14
View File
@@ -1,19 +1,20 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
<instance XML_version="1.2" desc="Texas Instruments XDS100v3 USB Debug Probe_0" href="connections/TIXDS100v3_Dot7_Connection.xml" id="Texas Instruments XDS100v3 USB Debug Probe_0" xml="TIXDS100v3_Dot7_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
<instance XML_version="1.2" href="drivers/tixds100v2icepick_c.xml" id="drivers" xml="tixds100v2icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cs_dap.xml" id="drivers" xml="tixds100v2cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cortexM.xml" id="drivers" xml="tixds100v2cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="2" id="The Converter Usage">
<choice Name="Generate 1149.7 2-pin advanced modes" value="enable">
<property Type="choicelist" Value="1" id="The Converter 1149.7 Frequency">
<choice Name="Overclock with user specified value" value="unused">
<property Type="choicelist" Value="5" id="-- Choose a value from 1.0MHz to 50.0MHz"/>
</choice>
</property>
<property Type="choicelist" Value="5" id="The Target Scan Format"/>
<configuration XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe_0" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe_0" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="1" id="Power Selection">
<choice Name="Probe supplied power" value="1">
<property Type="stringfield" Value="3.3" id="Voltage Level"/>
</choice>
</property>
<property Type="choicelist" Value="0" id="JTAG Signal Isolation"/>
<property Type="choicelist" Value="4" id="SWD Mode Settings">
<choice Name="cJTAG (1149.7) 2-pin advanced modes" value="enable">
<property Type="choicelist" Value="1" id="XDS110 Aux Port"/>
</choice>
</property>
<platform XML_version="1.2" id="platform_0">
simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/config/src/sysbios/m3_Hwi_asm.obj
BIN
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/config/src/sysbios/m3_Hwi_asm_switch.obj
BIN
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/config/src/sysbios/m3_IntrinsicsSupport_asm.obj
BIN
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/config/src/sysbios/m3_TaskSupport_asm.obj
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/config/src/sysbios/makefile
+4 -4
View File
@@ -16,11 +16,11 @@ BIOS_INC = -I"C:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/pa
TARGET_INC = -I"C:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/packages/"
INCS = $(BIOS_INC) $(TARGET_INC) --include_path="C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/include" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/icall/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/roles/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/roles" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/dev_info" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/simple_profile/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/simple_profile" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/common/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/heapmgr" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/controller/cc26xx/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/target/_common" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/target" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/target/_common/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/osal/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/services/src/sdata" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/services/src/saddr" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/icall/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/rom" --include_path="C:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/cc26xxware_2_24_03_17272" -IC:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/packages/
INCS = $(BIOS_INC) $(TARGET_INC) --include_path="C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/include" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/icall/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/roles/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/roles" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/dev_info" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/simple_profile/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/profiles/simple_profile" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/common/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/heapmgr" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/controller/cc26xx/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/target/_common" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/target" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/target/_common/cc26xx" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/hal/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/osal/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/services/src/sdata" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/services/src/saddr" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/components/icall/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/inc" --include_path="C:/ti/simplelink/ble_sdk_2_02_02_25/src/rom" --include_path="C:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/cc26xxware_2_24_03_17272" -IC:/ti/tirtos_cc13xx_cc26xx_2_21_01_08/products/bios_6_46_01_38/packages/
CC = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/include
ASM = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/include
AR = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS/bin/armar rq
CC = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/include
ASM = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/include
AR = C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.5.LTS/bin/armar rq
DEL = C:/ti/xdctools_3_32_02_25_core/packages/../bin/rm -f
CP = C:/ti/xdctools_3_32_02_25_core/packages/../bin/cp -f
simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/config/src/sysbios/rom_sysbios.aem3
BIN
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/config/src/sysbios/rom_sysbios.obj
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/stack/.ccsproject
+1 -1
View File
@@ -9,6 +9,6 @@
<linkerCommandFile value="cc26x0f128.cmd"/>
<rts value="libc.a"/>
<createSlaveProjects value=""/>
<connection value="common/targetdb/connections/TIXDS100v3_Dot7_Connection.xml"/>
<connection value="common/targetdb/connections/TIXDS110_Connection.xml"/>
<isTargetManual value="false"/>
</projectOptions>
simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/stack/.cproject
+236 -120
View File
@@ -14,130 +14,246 @@
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/stack/.launches/simple_peripheral_cc2650em_stack.launch
+1
View File
@@ -12,6 +12,7 @@
<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_TARGET_CONFIG" value="${target_config_active_default:simple_peripheral_cc2650em_stack}"/>
<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\stack\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS100v3 USB Debug Probe_0/Cortex_M3_0" value="C:/ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\stack\FlashROM\simple_peripheral_cc2650em_stack.out"/>
<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\stack\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS110 USB Debug Probe/Cortex_M3_0" value="C:/ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\stack\FlashROM\simple_peripheral_cc2650em_stack.out"/>
<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM.C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\stack\targetConfigs\CC2650F128.ccxml.Texas Instruments XDS110 USB Debug Probe_0/Cortex_M3_0" value="C:/ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650em\simple_peripheral\ccs\stack\FlashROM\simple_peripheral_cc2650em_stack.out"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/simple_peripheral_cc2650em_stack"/>
</listAttribute>
simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/stack/targetConfigs/CC2650F128.ccxml
+15 -14
View File
@@ -1,19 +1,20 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
<instance XML_version="1.2" desc="Texas Instruments XDS100v3 USB Debug Probe_0" href="connections/TIXDS100v3_Dot7_Connection.xml" id="Texas Instruments XDS100v3 USB Debug Probe_0" xml="TIXDS100v3_Dot7_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
<instance XML_version="1.2" href="drivers/tixds100v2icepick_c.xml" id="drivers" xml="tixds100v2icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cs_dap.xml" id="drivers" xml="tixds100v2cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cortexM.xml" id="drivers" xml="tixds100v2cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="2" id="The Converter Usage">
<choice Name="Generate 1149.7 2-pin advanced modes" value="enable">
<property Type="choicelist" Value="1" id="The Converter 1149.7 Frequency">
<choice Name="Overclock with user specified value" value="unused">
<property Type="choicelist" Value="5" id="-- Choose a value from 1.0MHz to 50.0MHz"/>
</choice>
</property>
<property Type="choicelist" Value="5" id="The Target Scan Format"/>
<configuration XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe_0" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe_0" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="1" id="Power Selection">
<choice Name="Probe supplied power" value="1">
<property Type="stringfield" Value="3.3" id="Voltage Level"/>
</choice>
</property>
<property Type="choicelist" Value="0" id="JTAG Signal Isolation"/>
<property Type="choicelist" Value="4" id="SWD Mode Settings">
<choice Name="cJTAG (1149.7) 2-pin advanced modes" value="enable">
<property Type="choicelist" Value="1" id="XDS110 Aux Port"/>
</choice>
</property>
<platform XML_version="1.2" id="platform_0">
simplelink/ble_sdk_2_02_02_25/src/boards/BOOSTXL_CC2650MA/BOOSTXL_CC2650MA.c
+40 -40
View File
@@ -116,46 +116,46 @@ const PowerCC26XX_Config PowerCC26XX_config = {
* ============================= UART begin ===================================
*/
/* Place into subsections to allow the TI linker to remove items properly */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(UART_config, ".const:UART_config")
#pragma DATA_SECTION(uartCC26XXHWAttrs, ".const:uartCC26XXHWAttrs")
#endif
/* Include drivers */
#include <ti/drivers/UART.h>
#include <ti/drivers/uart/UARTCC26XX.h>
/* UART objects */
UARTCC26XX_Object uartCC26XXObjects[BOOSTXL_CC2650MA_UARTCOUNT];
/* UART hardware parameter structure, also used to assign UART pins */
const UARTCC26XX_HWAttrsV2 uartCC26XXHWAttrs[BOOSTXL_CC2650MA_UARTCOUNT] = {
//
{
.baseAddr = UART0_BASE,
.powerMngrId = PowerCC26XX_PERIPH_UART0,
.intNum = INT_UART0_COMB,
.intPriority = ~0,
.swiPriority = 0,
.txPin = Board_UART_TX,
.rxPin = Board_UART_RX,
.ctsPin = PIN_UNASSIGNED,
.rtsPin = PIN_UNASSIGNED
//
}
//
};
/* UART configuration structure */
const UART_Config UART_config[] = { //
{
//
.fxnTablePtr = &UARTCC26XX_fxnTable,
.object = &uartCC26XXObjects[0],
.hwAttrs = &uartCC26XXHWAttrs[0]
//
},
{NULL, NULL, NULL}};
//#if defined(__TI_COMPILER_VERSION__)
//#pragma DATA_SECTION(UART_config, ".const:UART_config")
//#pragma DATA_SECTION(uartCC26XXHWAttrs, ".const:uartCC26XXHWAttrs")
//#endif
//
///* Include drivers */
//#include <ti/drivers/UART.h>
//#include <ti/drivers/uart/UARTCC26XX.h>
//
///* UART objects */
//UARTCC26XX_Object uartCC26XXObjects[BOOSTXL_CC2650MA_UARTCOUNT];
//
///* UART hardware parameter structure, also used to assign UART pins */
//const UARTCC26XX_HWAttrsV2 uartCC26XXHWAttrs[BOOSTXL_CC2650MA_UARTCOUNT] = {
// //
// {
// .baseAddr = UART0_BASE,
// .powerMngrId = PowerCC26XX_PERIPH_UART0,
// .intNum = INT_UART0_COMB,
// .intPriority = ~0,
// .swiPriority = 0,
// .txPin = Board_UART_TX,
// .rxPin = Board_UART_RX,
// .ctsPin = PIN_UNASSIGNED,
// .rtsPin = PIN_UNASSIGNED
// //
// }
// //
//};
//
///* UART configuration structure */
//const UART_Config UART_config[] = { //
// {
// //
// .fxnTablePtr = &UARTCC26XX_fxnTable,
// .object = &uartCC26XXObjects[0],
// .hwAttrs = &uartCC26XXHWAttrs[0]
// //
// },
// {NULL, NULL, NULL}};
/*
* ============================= UART end =====================================
*/
simplelink/ble_sdk_2_02_02_25/src/boards/BOOSTXL_CC2650MA/BOOSTXL_CC2650MA.h
+1
View File
@@ -51,6 +51,7 @@ extern "C" {
#include <ti/drivers/PIN.h>
#include <driverlib/ioc.h>
#define HEADSTAGE_UNI_2_0
#ifdef HEADSTAGE_UNI_2_0
#include "neu/headstage_pin.h"
#else
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_instruction.h
+85
View File
@@ -0,0 +1,85 @@
#ifndef NEU_INSTRUCTION
#define NEU_INSTRUCTION
struct HEADSTAGE_PARAMETER_TABLE {
uint8_t current_sti_cycle[NEU_STI_CHANNEL_COUNTS]; /** stimulation times will be executed. */
// sti_tx[0~7] is current stimulate
// sti_tx[8] assign to voltage mode channel. */
uint16_t sti_t1[NEU_STI_CHANNEL_COUNTS]; /**< first stimulation pulse duration, it can't be 0. */
uint16_t sti_t2[NEU_STI_CHANNEL_COUNTS]; /**< interval between biphasic pulses. */
uint16_t sti_t3[NEU_STI_CHANNEL_COUNTS]; /**< second stimulation pulse duration. */
uint32_t sti_t4[NEU_STI_CHANNEL_COUNTS]; /**< discharge time per stimulation. */
uint16_t sti_t5[NEU_STI_CHANNEL_COUNTS]; /**< discharge time after final stimulation. */
bool sti_mode; /**< if true: continuous mode, else limited mode. */
bool sti_h_bridge; /**< if true: enable h bridge, else single ended. */
bool sti_ref; /**< if true: reference cell body to gnd, else single ended is used. */
uint8_t current_sti_polarity; /**<
* default : low side.
* define which channel is high side or low side.
*/
uint8_t voltage_sti_channel; /**<
* voltage_channel[7:4] represent pmos channel,
* voltage_channel[3:0] represent nmos channel
*/
uint8_t amplifier_gain; /**<
* parameter table to represent actual amplifier gain
* ----------
* | bit |mean|
* ----------
* |0b00 | 100|
* ----------
* |0b01 | 400|
* ----------
* |0b10 | 800|
* -----------
* |0b11 | 25 |
* -----------
*/
/**< these parameter define the bias voltage of amplifier. */
uint8_t vgrp;
uint8_t vgrn;
uint8_t vgr_int_old;
uint8_t vgr_intp;
uint8_t vgr_intn;
uint8_t ins_opcode; /**< check instruction opcode which is transmitted to DBS. */
uint8_t voltage_sti_amplitude; /**< voltage mode stimulation amplitude control. */
uint16_t arbitrary_index; /**< this index to keep address of arbitrary data we have already stored. */
uint16_t arbitrary_en; /**< if true: enable arbitrary mode stimulation. */
uint16_t recording_channel; /**< recording_channel[17] represent enabling channel 17. */
uint16_t sti_amplitude_h; /**< positive side amplitude. */
uint16_t sti_amplitude_l; /**< negative side amplitude. */
uint16_t sys_clk_ratio; /**< frequency divider ratio for digital core clock. */
uint16_t adc_clock_ratio; /**< frequency divider ratio for adc clock. */
uint16_t sti_clock_ratio; /**< frequency divider ratio for stimulation clock. */
uint16_t chopper_ratio; /**< freqeuncy divider for chopper. */
uint16_t sti_channel; /**<
* if stimulation[7] == true, stimulation channel 7 is enabled .
* if stimulation[4] == true. stimulation channel 4 is enabled .
*/
} INSTRUCTION = {0};
/**
* @brief:
* manage which operation to be conducted
*/
struct HEADSTAGE_STATE {
uint8_t state;
uint8_t config_type;
uint8_t index;
} NEULIVE_STATE = {0};
#endif
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_neu.h
+335 -184
View File
@@ -129,9 +129,9 @@
do { \
uint32_t __i = (uint32_t)(index); \
uint32_t __v = (uint32_t)(value); \
spi_txbuf[__i++] = (__v >> 16) & 0xff; \
spi_txbuf[__i++] = (__v >> 8) & 0xff; \
spi_txbuf[__i++] = (__v)&0xff; \
spi_txbuf[__i++] = (__v >> 16) & 0xFF; \
spi_txbuf[__i++] = (__v >> 8) & 0xFF; \
spi_txbuf[__i++] = (__v)&0xFF; \
} while (0)
/**
@@ -163,34 +163,51 @@
#define NEU_REC_PARAM 0x20
#define NEU_ARB_PARAM 0x40
#define NEU_TEST_INS 0x60
#define NEU_STI_TIME 0x80
#define NEU_WRITE_REG 0xE0
#define NEU_READ_REG 0xF0
/** event */
#define EVT_NEU_SPI 0x0001 /**< spi transaction event */
#define EVT_NEU_LED 0x0002 /**< set led event */
#define EVT_NEU_CHECK 0x0003 /**< check neulive single instruction */
#define EVT_NEU_CHECK 0x0004 /**< check neulive single instruction */
#define EVT_NEU_REG_SPI 0x0008 /** register spi event */
/** clock setting */
#define NEU_SYS_CLK 8000000 /**< 10Mhz */
#define NEU_POLY_R_CLK 1000 /**< 1khz */
#define NEU_SPI_FREQ 800000 /**< 1Mhz */
#define NEU_LED_FREQ 1000000 /**< 1Mhz */
#define NEU_SYS_CLK 4000000 /**< 10Mhz */
#define NEU_POLY_R_CLK 1000 /**< 1khz */
#define NEU_SPI_FREQ NEU_SYS_CLK/10 /**< 1Mhz */ // should be NEU_SYS_CLK/10
#define NEU_LED_FREQ 1000000 /**< 1Mhz */
/** amounts of channel */
#define NEU_STI_CHANNEL_COUNTS 9 /**< voltage mode channel counts and current mode channel counts */
#define NEU_STI_CHANNEL_COUNTS 8 /**< voltage mode channel counts and current mode channel counts */
#define NEU_REC_CHANNEL_COUNTS 16 /**< recording channel counts */
/** State for SPI (SPI callback to do task) **/
static uint8_t SPICallBack = 0;
#define CLOSE_SPI 0x01 // close SPI after MISO transmit
#define CONTINUOUS_TRANS 0x02 // transmit DBS data
#define FLUSH_BUFFER 0x03 // clean SPI buffer, used after a "write" SPI instruction (MISO)
#define FLUSH_BUFFER2 0x04 // clean SPI buffer twice
#define READ_REG 0x05 // read DBS register value, used after a "read" SPI instruction (MISO)
#define READ_REG2 0x06 // read DBS register value, used after a "read" SPI instruction (MISO)
#define END_TRANSMIT 0x07 // end spi instruction
#define ONE_SHOT_SPI 0x08
#define READ_MOSI 0x09
/** state for CC2650 to control DBS */
#define NEU_WRITE_INSTRUCTION 0 /**< write instruction into register table by spi interface */
#define NEU_READ_DATA 1 /**< read amplifier data by spi interface */
#define NEU_SINGLE_INS_READ 2
#define NEU_CHECK_REGISTER 3
#define NEU_RECEIVE_PARAM 4
#define NEU_PREPARE_READ 5
#define NEU_IDLE 15
/** macros for build up DBS instruction */
#define NEU_LNA_BIAS_ONE 0x0210 /**< vgrp(1_0000) left shift 5bits | vgrn(1_0000) */
#define NEU_LNA_BIAS_TWO 0x4210 /**< vgr_int_old(1_0000) left shift 10bits | vgr_intp(1_0000) left shift 5bits | vgr_intn(1_0000) */
#define NEU_GENERAL_EN 0x40f0 /**<
#define NEU_GENERAL_EN 0x40F2 /**<
* | 15| 14| 13| 12| 11| 10| 9| 8|
* |en_ook|en_lsk|en_tg_10k|en_tg_10M|en_mux_10k|en_mux_10M|FSK_SEL|LNA_CLOCK_SEL|
*
@@ -237,6 +254,7 @@
* include *
*****************/
#include "time.h"
#include "headstage_instruction.h"
#include "headstage_pin.h"
#include "headstage_arm.h"
#include "headstage_debug.h"
@@ -249,6 +267,8 @@
#include "neu/headstage_pwm.h"
#include "neu/headstage_spi.h"
#include "neu/headstage_notify.h"
#include "neu/headstage_reset.h"
#include "neu/headstage_checkMOSI.h"
/******************
* variable *
@@ -261,84 +281,7 @@
* need to check default value of each parameter
*/
struct HEADSTAGE_PARAMETER_TABLE {
uint8_t current_sti_cycle[NEU_STI_CHANNEL_COUNTS]; /** stimulation times will be executed. */
/**< channel[8] assign to voltage mode channel. */
uint16_t sti_t1[NEU_STI_CHANNEL_COUNTS]; /**< first stimulation pulse duration, it can't be 0. */
uint16_t sti_t2[NEU_STI_CHANNEL_COUNTS]; /**< interval between biphasic pulses. */
uint16_t sti_t3[NEU_STI_CHANNEL_COUNTS]; /**< second stimulation pulse duration. */
uint32_t sti_t4[NEU_STI_CHANNEL_COUNTS]; /**< discharge time per stimulation. */
uint16_t sti_t5[NEU_STI_CHANNEL_COUNTS]; /**< discharge time after final stimulation. */
bool sti_mode; /**< if true: continuous mode, else limited mode. */
bool sti_h_bridge; /**< if true: enable h bridge, else single ended. */
bool sti_ref; /**< if true: reference cell body to gnd, else single ended is used. */
uint8_t current_sti_polarity; /**<
* default : low side.
* define which channel is high side or low side.
*/
uint8_t voltage_sti_channel; /**<
* voltage_channel[7:4] represent pmos channel,
* voltage_channel[3:0] represent nmos channel
*/
uint8_t amplifier_gain; /**<
* parameter table to represent actual amplifier gain
* ----------
* | bit |mean|
* ----------
* |0b00 | 100|
* ----------
* |0b01 | 400|
* ----------
* |0b10 | 800|
* -----------
* |0b11 | 25 |
* -----------
*/
/**< these parameter define the bias voltage of amplifier. */
uint8_t vgrp;
uint8_t vgrn;
uint8_t vgr_int_old;
uint8_t vgr_intp;
uint8_t vgr_intn;
uint8_t ins_opcode; /**< check instruction opcode which is transmitted to DBS. */
uint8_t voltage_sti_amplitude; /**< voltage mode stimulation amplitude control. */
uint16_t arbitrary_index; /**< this index to keep address of arbitrary data we have already stored. */
uint16_t arbitrary_en; /**< if true: enable arbitrary mode stimulation. */
uint16_t recording_channel; /**< recording_channel[17] represent enabling channel 17. */
uint16_t sti_amplitude_h; /**< positive side amplitude. */
uint16_t sti_amplitude_l; /**< negative side amplitude. */
uint16_t sys_clk_ratio; /**< frequency divider ratio for digital core clock. */
uint16_t adc_clock_ratio; /**< frequency divider ratio for adc clock. */
uint16_t sti_clock_ratio; /**< frequency divider ratio for stimulation clock. */
uint16_t chopper_ratio; /**< freqeuncy divider for chopper. */
uint16_t sti_channel; /**<
* if stimulation[7] == true, stimulation channel 7 is enabled .
* if stimulation[4] == true. stimulation channel 4 is enabled .
*/
} INSTRUCTION = {0};
/**
* @brief:
* manage which operation to be conducted
*/
struct HEADSTAGE_STATE {
uint8_t state;
uint8_t config_type;
uint8_t index;
} NEULIVE_STATE = {0};
/*
* todo: need to define some procedure to detect this device status
@@ -349,9 +292,11 @@ static uint8_t headstage_debug_instruction(uint8_t* ins_buf) {
/**
* @fn get_sti_channel
* this is a binary to decimal function
* return the decimal value for input number < 8
* return 0xFF if input >= 8
*/
static uint8_t get_sti_channel(uint8_t sti_channel) {
static uint8_t get_sti_channel(uint16_t sti_channel) {
uint8_t sti_ch;
for (uint8_t i = 0; i < 8; i++) {
if ((0x01 << i) & sti_channel) {
@@ -359,7 +304,7 @@ static uint8_t get_sti_channel(uint8_t sti_channel) {
return sti_ch;
}
}
return 0xff;
return 0xFF;
}
/**
@@ -371,25 +316,25 @@ static bool build_sti_cur_instruction(uint8_t sti_channel, uint32_t* value) {
switch (ins_opcode) {
case T_ST: {
op_neu = sti_channel * 4 + 1;
*value = (0x01 << 23) | (op_neu << 16) | (INSTRUCTION.sti_t2[sti_channel] & 0x3f << 10) | (INSTRUCTION.sti_t1[sti_channel]);
*value = (0x01 << 23) | (op_neu << 16) | (INSTRUCTION.sti_t2[sti_channel] & 0x3F << 10) | (INSTRUCTION.sti_t1[sti_channel]);
INSTRUCTION.ins_opcode = T_ND;
return false;
}
case T_ND: {
op_neu = sti_channel * 4 + 2;
*value = (0x01 << 23) | (op_neu << 16) | (INSTRUCTION.sti_t4[sti_channel] & 0x03 << 14) | (INSTRUCTION.sti_t3[sti_channel] << 6) | (INSTRUCTION.sti_t2[sti_channel] & 0x03c);
*value = (0x01 << 23) | (op_neu << 16) | (INSTRUCTION.sti_t4[sti_channel] & 0x03 << 14) | (INSTRUCTION.sti_t3[sti_channel] << 6) | (INSTRUCTION.sti_t2[sti_channel] & 0x03C0);
INSTRUCTION.ins_opcode = T_RD;
return false;
}
case T_RD: {
op_neu = sti_channel * 4 + 3;
*value = (0x01 << 23) | (op_neu << 16) | (INSTRUCTION.sti_t4[sti_channel] >> 2) & 0xffff;
*value = (0x01 << 23) | (op_neu << 16) | (INSTRUCTION.sti_t4[sti_channel] >> 2) & 0x7FFF;
INSTRUCTION.ins_opcode = T_FT;
return false;
}
case T_FT: {
op_neu = sti_channel * 4 + 4;
*value = (0x01 << 23) | (op_neu << 16) | (INSTRUCTION.sti_t5[sti_channel]) & 0x03ff;
*value = (0x01 << 23) | (op_neu << 16) | (INSTRUCTION.sti_t5[sti_channel]) & 0x03FF;
INSTRUCTION.ins_opcode = STI_CYCLE;
return false;
}
@@ -397,7 +342,6 @@ static bool build_sti_cur_instruction(uint8_t sti_channel, uint32_t* value) {
op_neu = (sti_channel / 2) + 42;
uint8_t odd_even = sti_channel % 2;
INSTRUCTION.ins_opcode = HIGH_SIDE;
if (NEULIVE_STATE.config_type == NEU_SET_STI_VOLT) INSTRUCTION.ins_opcode = HIGH_SIDE;
if (odd_even)
*value = (0x01 << 23) | (op_neu << 16) | (INSTRUCTION.current_sti_cycle[sti_channel] << 8) | (INSTRUCTION.current_sti_cycle[sti_channel - 1]);
else
@@ -488,20 +432,49 @@ static void headstage_init() {
/**
* @fn headstage_neu_append_notify_data
*/
#define CHANNEL_VALID (INSTRUCTION.recording_channel & (0x0001 << channel))
static void headstage_neu_append_notify_data() {
uint8_t not_buf[2];
not_buf[0] = (spi_rxbuf[0] << 4) | spi_rxbuf[1];
not_buf[1] = spi_rxbuf[2];
uint8_t channel = spi_rxbuf[0];
if(!CHANNEL_VALID || (channel > 15)){
// illegal channel
return;
}
uint8_t not_buf[3];
not_buf[0] = channel; // ch
not_buf[1] = spi_rxbuf[1];
not_buf[2] = spi_rxbuf[2];
// not_buf[1] = (INSTRUCTION.recording_channel | 0xFF00) >> 8;
// not_buf[2] = (INSTRUCTION.recording_channel | 0x00FF);
uint8_t data_size = headstage_notify_append_data(not_buf);
if (data_size >= BLE_NOT_BUFF_SIZE) {
headstage_notify_send();
headstage_notify_flip_buffer();
uint32_t current = headstage_time_stamp_us();
uint32_t time_delta = ((current - not_time_stamp)) & 0xFFFF;
headstage_notify_buffer[6] = time_delta & 0xFF;
headstage_notify_buffer[7] = (time_delta >> 8) & 0xFF;
// headstage_led_color(COLOR_GREEN);
// headstage_notify_buffer[6] = 0;
// headstage_notify_buffer[7] = 0;
//
// headstage_notify_send();
SimpleProfile_SetParameter(BLE_NOT_BUFF_CHAR, BLE_NOT_BUFF_SIZE, headstage_notify_buffer);
not_buf_offset = NOT_BUF_OFFSET_INIT;
}
}
static void headstage_neu_state_spi();
static void headstage_neu_register_spi();
#define MODE_IDLE 0x00
#define MODE_REGISTER_WRITE 0x01
#define MODE_REGISTER_READ 0x02
struct _NeuliveTwoControl{
uint8_t mode;
}NeuliveTwoControl = {0};
/**
* @fn headstage_neu_event
@@ -511,14 +484,19 @@ static void headstage_neu_state_spi();
static void headstage_neu_event() {
if (flag_mask(EVT_NEU_SPI)) {
headstage_neu_state_spi();
flag_disable(EVT_NEU_SPI);
headstage_neu_state_spi();
}
if (flag_mask(EVT_NEU_LED)) {
flag_disable(EVT_NEU_LED); /** reserved to set led power and set color manually */
}
if(flag_mask(EVT_NEU_REG_SPI)){
headstage_neu_register_spi();
flag_disable(EVT_NEU_REG_SPI);
}
if (EVENT_MASK == 0) {
// fast return
}
@@ -535,7 +513,67 @@ static void headstage_neu_event() {
*/
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction) {
flag_notify(EVT_NEU_SPI);
switch(SPICallBack){
case CONTINUOUS_TRANS:{
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
}
flag_notify(EVT_NEU_SPI);
break;
}
case FLUSH_BUFFER:{
SPICallBack = FLUSH_BUFFER2;
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
}
headstage_spi_transaction(SPI_BUFFER_SIZE);
break;
}
case FLUSH_BUFFER2:{
SPICallBack = ONE_SHOT_SPI;
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
}
flag_notify(EVT_NEU_SPI);
// headstage_spi_transaction(SPI_BUFFER_SIZE);
break;
}
case ONE_SHOT_SPI:{
SPICallBack = FLUSH_BUFFER;
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
}
headstage_spi_transaction(SPI_BUFFER_SIZE);
break;
}
case READ_MOSI:{
flag_notify(EVT_NEU_SPI);
break;
}
case READ_REG:{
SPICallBack = CLOSE_SPI;
headstage_spi_transaction(3);
break;
}
case CLOSE_SPI:{
SPICallBack = ONE_SHOT_SPI;
OpenSPI = true;
SPI_close(headstage_spi_handle);
break;
}
case END_TRANSMIT:{
tx_put_u24(0, 0);
SPICallBack = CONTINUOUS_TRANS;
break;
}
default:{
break;
}
}
}
/**
@@ -543,35 +581,36 @@ static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transacti
*
* description: decode real instruction to set corresponding parameter
*/
static bool STI = false; // user using STI?
static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instruction) {
switch (instruction[0] & 0xE0) {
case NEU_STI_PARAM: {
STI = true;
/** this is for test */
bool sti_volt_curr_sel = (instruction[0] & 0b00001000);
bool sti_mode = (instruction[0] & 0b00000100);
bool sti_h_bridge = (instruction[0] & 0b00000010);
bool sti_ref = (instruction[0] & 0b00000001);
uint8_t p_ch = (instruction[1] & 0xf0) >> 4;
uint8_t n_ch = (instruction[1] & 0x0f);
uint8_t p_ch = (instruction[1] & 0xF0) >> 4;
uint8_t n_ch = (instruction[1] & 0x0F);
uint8_t sti_cycles = instruction[2];
uint16_t sti_amplitude_h = (instruction[3] << 2) | ((instruction[4] & 0xc0) >> 6);
uint16_t sti_amplitude_l = ((instruction[4] & 0x3f) << 4) | ((instruction[5] & 0xf0) >> 4);
uint16_t sti_t1 = ((instruction[5] & 0x0f) << 6) | ((instruction[6] & 0xfc) >> 2);
uint16_t sti_amplitude_h = (instruction[3] << 2) | ((instruction[4] & 0xC0) >> 6);
uint16_t sti_amplitude_l = ((instruction[4] & 0x3F) << 4) | ((instruction[5] & 0xF0) >> 4);
uint16_t sti_t1 = ((instruction[5] & 0x0F) << 6) | ((instruction[6] & 0xFC) >> 2);
uint16_t sti_t2 = ((instruction[6] & 0x03) << 8) | instruction[7];
uint16_t sti_t3 = (instruction[8] << 2) | ((instruction[9] & 0xc0) >> 6);
uint16_t sti_t4 = ((instruction[9] & 0x3f) << 4) | ((instruction[10] & 0xf0) >> 4);
uint16_t sti_t5 = ((instruction[10] & 0x0f) << 6) | ((instruction[11] & 0xfc) >> 2);
uint16_t sti_clock_ratio = ((instruction[11] & 0x03) << 14) | (instruction[12] << 6) | ((instruction[13] & 0xfc) >> 2);
uint16_t sti_t3 = (instruction[8] << 2) | ((instruction[9] & 0xC0) >> 6);
uint32_t sti_t4 = ((instruction[9] & 0x3F) << 11) | (instruction[10] << 2) | ((instruction[11] & 0xE0) >> 6);
uint16_t sti_t5 = ((instruction[11] & 0x1F) << 5) | ((instruction[12] & 0xF8) >> 3);
uint16_t sti_clock_ratio = ((instruction[12] & 0x07) << 13) | (instruction[13] << 5) | ((instruction[14] & 0xF8) >> 3);
INSTRUCTION.arbitrary_en = (0x01 << p_ch) | (0x01 << n_ch);
INSTRUCTION.sti_mode = sti_mode;
INSTRUCTION.sti_h_bridge = sti_h_bridge;
INSTRUCTION.sti_ref = sti_ref;
INSTRUCTION.current_sti_polarity = (0x01) << (7 - p_ch);
INSTRUCTION.current_sti_polarity = (0x01) << (p_ch + 8);
INSTRUCTION.sti_amplitude_h = sti_amplitude_h;
INSTRUCTION.sti_amplitude_l = sti_amplitude_l;
if (sti_volt_curr_sel) {
if (!sti_volt_curr_sel) {
INSTRUCTION.sti_t1[p_ch] = sti_t1;
INSTRUCTION.sti_t1[n_ch] = sti_t1;
INSTRUCTION.sti_t2[p_ch] = sti_t2;
@@ -583,30 +622,34 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
INSTRUCTION.sti_t5[p_ch] = sti_t5;
INSTRUCTION.sti_t5[n_ch] = sti_t5;
INSTRUCTION.current_sti_cycle[p_ch] = sti_cycles;
INSTRUCTION.sti_channel = ((0x01) << p_ch) | ((0x01) << n_ch);
if(sti_h_bridge){
INSTRUCTION.sti_channel = ((0x01) << p_ch) | ((0x01) << n_ch);
}else{
INSTRUCTION.sti_channel = 0x01 << p_ch;
}
} else {
INSTRUCTION.sti_t1[8] = sti_t1;
INSTRUCTION.sti_t2[8] = sti_t2;
INSTRUCTION.sti_t3[8] = sti_t3;
INSTRUCTION.sti_t4[8] = sti_t4;
INSTRUCTION.sti_t5[8] = sti_t5;
INSTRUCTION.current_sti_cycle[8] = sti_cycles;
INSTRUCTION.sti_channel = (0x01 << 8);
INSTRUCTION.sti_t1[NEU_STI_CHANNEL_COUNTS-1] = sti_t1;
INSTRUCTION.sti_t2[NEU_STI_CHANNEL_COUNTS-1] = sti_t2;
INSTRUCTION.sti_t3[NEU_STI_CHANNEL_COUNTS-1] = sti_t3;
INSTRUCTION.sti_t4[NEU_STI_CHANNEL_COUNTS-1] = sti_t4;
INSTRUCTION.sti_t5[NEU_STI_CHANNEL_COUNTS-1] = sti_t5;
INSTRUCTION.current_sti_cycle[NEU_STI_CHANNEL_COUNTS-1] = sti_cycles;
INSTRUCTION.sti_channel = (0x01 << (NEU_STI_CHANNEL_COUNTS-1)) ;
}
INSTRUCTION.sti_clock_ratio = sti_clock_ratio;
INSTRUCTION.ins_opcode = T_FT;
break;
}
case NEU_REC_PARAM: {
uint8_t vgrp = instruction[0] & 0x1f;
uint8_t vgrn = (instruction[1] & 0xf8) >> 3;
uint8_t vgr_int_old = ((instruction[1] & 0x07) << 2) | ((instruction[2] & 0xc0) >> 6);
uint8_t vgrp = instruction[0] & 0x1F;
uint8_t vgrn = (instruction[1] & 0xF8) >> 3;
uint8_t vgr_int_old = ((instruction[1] & 0x07) << 2) | ((instruction[2] & 0xC0) >> 6);
uint8_t vgr_intp = ((instruction[2] & 0x3E) >> 1);
uint8_t vgr_intn = ((instruction[2] & 0x01) << 4) | ((instruction[3] & 0xf0) >> 4);
uint16_t recording_channel = ((instruction[3] & 0x0f) << 12) | (instruction[4] << 4) | ((instruction[5] & 0xf0) >> 4);
uint16_t adc_clock_ratio = ((instruction[5] & 0x0f) << 12) | (instruction[6] << 4) | ((instruction[7] & 0xf0) >> 4);
uint16_t sys_clk_ratio = ((instruction[7] & 0x0f) << 12) | (instruction[8] << 4) | ((instruction[9] & 0xf0) >> 4);
uint8_t amplifier_gain = ((instruction[9] & 0x0c) >> 2);
uint8_t vgr_intn = ((instruction[2] & 0x01) << 4) | ((instruction[3] & 0xF0) >> 4);
uint16_t recording_channel = ((instruction[3] & 0x0F) << 12) | (instruction[4] << 4) | ((instruction[5] & 0xF0) >> 4);
uint16_t adc_clock_ratio = ((instruction[5] & 0x0F) << 12) | (instruction[6] << 4) | ((instruction[7] & 0xF0) >> 4);
uint16_t sys_clk_ratio = ((instruction[7] & 0x0F) << 12) | (instruction[8] << 4) | ((instruction[9] & 0xF0) >> 4);
uint8_t amplifier_gain = ((instruction[9] & 0x0C) >> 2);
uint16_t chopper_ratio = (instruction[10] << 8) | instruction[11];
INSTRUCTION.vgrp = vgrp;
@@ -617,9 +660,27 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
INSTRUCTION.recording_channel = recording_channel;
INSTRUCTION.adc_clock_ratio = adc_clock_ratio;
INSTRUCTION.sys_clk_ratio = sys_clk_ratio;
INSTRUCTION.amplifier_gain = (amplifier_gain == 0) ?3 :amplifier_gain-1 ; /**< control shift*/
INSTRUCTION.amplifier_gain = amplifier_gain; /**< control shift*/
INSTRUCTION.chopper_ratio = chopper_ratio;
INSTRUCTION.ins_opcode = T_FT;
if(STI){
INSTRUCTION.ins_opcode = T_FT;
}
else{
INSTRUCTION.ins_opcode = BIAS_ONE;
}
break;
}
case NEU_STI_TIME:{
// 4b>PMOS_CH;10b>STI_T1;10b>STI_T2;10b>STI_T3;17b>STI_T4;10b>STI_T5
uint8_t StiChPos = instruction[0] & 0x0F;
if(StiChPos < 9){
INSTRUCTION.sti_t1[StiChPos] = instruction[1] << 2 | (instruction[2] & 0xC0) >> 6;
INSTRUCTION.sti_t2[StiChPos] = (instruction[2] & 0x3F) << 4 | (instruction[3] & 0xF0) >> 4;
INSTRUCTION.sti_t3[StiChPos] = (instruction[3] & 0x0F) << 6 | (instruction[4] & 0xFC) >> 2;
INSTRUCTION.sti_t4[StiChPos] = (instruction[4] & 0x03) << 15 | (instruction[5] << 7) | (instruction[6] & 0x80) >> 15;
INSTRUCTION.sti_t5[StiChPos] = instruction[6];
}
break;
}
case NEU_ARB_PARAM: {
@@ -632,7 +693,7 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
INSTRUCTION.vgr_intp = 16;
INSTRUCTION.vgr_intn = 16;
INSTRUCTION.vgr_int_old = 16;
INSTRUCTION.recording_channel = 2 ^ 7;
INSTRUCTION.recording_channel = 0b0000000000000010;
INSTRUCTION.adc_clock_ratio = 200;
INSTRUCTION.sys_clk_ratio = 10;
INSTRUCTION.sti_clock_ratio = 10;
@@ -653,7 +714,26 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
INSTRUCTION.current_sti_polarity = 2;
INSTRUCTION.sti_amplitude_h = 0;
INSTRUCTION.sti_amplitude_l = 0;
INSTRUCTION.ins_opcode = T_FT;
INSTRUCTION.ins_opcode = BIAS_ONE;
break;
}
case NEU_WRITE_REG:{
NeuliveTwoControl.mode = MODE_REGISTER_WRITE;
uint8_t address = instruction[1];
uint16_t data = instruction[2] << 8 | instruction[3];
uint32_t value = address << 16 | data;
tx_put_u24(0, value);
break;
}
case NEU_READ_REG:{
NeuliveTwoControl.mode = MODE_REGISTER_READ;
uint8_t address = instruction[1];
uint16_t data = instruction[2] << 8 | instruction[3];
uint32_t value = address << 16 | data;
tx_put_u24(0, value);
break;
}
default: {
@@ -671,20 +751,28 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
static void headstage_update_vis_instruction(uint8_t vis_oper) {
switch (vis_oper) {
case VIS_RST: {
headstage_pin_output(PIN_RESET, 0);
headstage_cpu_delay_ms(1);
headstage_pin_output(PIN_RESET, 1);
Neu2Reset();
/**< stop spi transaction */
break; /**< reset all the parameter */
}
case VIS_STI: {
NEULIVE_STATE.state = NEU_WRITE_INSTRUCTION;
NEULIVE_STATE.config_type = NEU_SET_STI_CUR;
// NEULIVE_STATE.state = NEU_READ_DATA;
SPICallBack = ONE_SHOT_SPI;
flag_notify(EVT_NEU_SPI);
// if(NeuliveTwoControl.mode == MODE_REGISTER_READ || NeuliveTwoControl.mode == MODE_REGISTER_WRITE){
// flag_notify(EVT_NEU_REG_SPI);
// }
break; /**< start to operate */
}
case VIS_INT: {
NEULIVE_STATE.state = NEU_IDLE;
headstage_spi_transaction_cancel(headstage_spi_handle);
SPICallBack = ONE_SHOT_SPI;
NEULIVE_STATE.state = NEU_IDLE;
Neu2Reset();
/**< stop stimulation and recording */
break; /**< interrupt the operation */
}
@@ -862,10 +950,14 @@ static uint8_t build_neu_ins_config(uint8_t config_type, uint32_t* value) {
bool done;
switch (config_type) {
case NEU_SET_STI_CUR: {
if(!STI){
// go to recording setting if no stimulate
return NEU_SET_GENERAL_EN;
}
uint8_t sti_channel = get_sti_channel(INSTRUCTION.sti_channel);
done = build_sti_cur_instruction(sti_channel, value);
if (done) {
if (sti_channel == 0xff) {
if (sti_channel == 0xFF) {
return NEU_SET_STI_VOLT;
} else {
INSTRUCTION.sti_channel ^= (0x01 << sti_channel);
@@ -885,57 +977,72 @@ static uint8_t build_neu_ins_config(uint8_t config_type, uint32_t* value) {
}
case NEU_SET_POLARITY: {
*value = (0x01 << 23) | (0x28 << 16) | INSTRUCTION.current_sti_polarity;
return NEU_SET_GENERAL_EN;
}
case NEU_SET_STI_CHANNEL: {
*value = (0x01 << 23) | (0x2E << 16) | INSTRUCTION.sti_channel;
return NEU_SET_STI_CUR;
}
case NEU_SET_GENERAL_EN: {
*value = (0x01 << 23) | (0x2F << 16) | NEU_GENERAL_EN;
return NEU_SET_REC_CHANNEL;
}
case NEU_SET_REC_CHANNEL: {
*value = (0x01 << 23) | (0x30 << 16) | INSTRUCTION.recording_channel;
return NEU_SET_AMP_GAIN;
}
case NEU_SET_AMP_GAIN: {
*value = (0x01 << 23) | (0x31 << 16) | INSTRUCTION.amplifier_gain;
return NEU_SET_SYS_CLK;
}
case NEU_SET_SYS_CLK: {
*value = (0x01 << 23) | (0x32 << 16) | INSTRUCTION.sys_clk_ratio;
return NEU_SET_ADC_CLK;
}
case NEU_SET_ADC_CLK: {
*value = (0x01 << 23) | (0x33 << 16) | INSTRUCTION.adc_clock_ratio;
return NEU_SET_STI_CLK;
}
case NEU_SET_STI_CLK: {
*value = (0x01 << 23) | (0x34 << 16) | INSTRUCTION.sti_clock_ratio;
return NEU_SET_STI_MODE;
}
case NEU_SET_ARBITRARY: {
*value = (0x01 << 23) | (0x36 << 16) | INSTRUCTION.arbitrary_en;
return NEU_SET_ARB_INDEX;
}
case NEU_SET_ARB_INDEX: {
*value = (0x01 << 23) | (0x37 << 16) | INSTRUCTION.arbitrary_index;
return NEU_SET_STI_MODE;
}
// case NEU_SET_ARBITRARY: {
// *value = (0x01 << 23) | (0x36 << 16) | INSTRUCTION.arbitrary_en;
// return NEU_SET_ARB_INDEX;
// }
// case NEU_SET_ARB_INDEX: {
// *value = (0x01 << 23) | (0x37 << 16) | INSTRUCTION.arbitrary_index;
// return NEU_SET_STI_MODE;
// }
case NEU_SET_STI_MODE: {
*value = (0x01 << 23) | (0x38 << 16) | (INSTRUCTION.sti_mode << 2) | (INSTRUCTION.sti_h_bridge << 1) | (INSTRUCTION.sti_ref);
return NEU_SET_GENERAL_EN;
}
/* These are recording parameter */
case NEU_SET_GENERAL_EN: {
*value = (0x01 << 23) | (0x2F << 16) | NEU_GENERAL_EN;
return NEU_SET_REC_CHANNEL;
}
case NEU_SET_REC_CHANNEL: {
*value = (0x01 << 23) | (0x30 << 16) | INSTRUCTION.recording_channel;
// *value = (0x01 << 23) | (0x30 << 16) | 0b0000000001000000;
return NEU_SET_AMP_GAIN;
}
case NEU_SET_AMP_GAIN: {
*value = (0x01 << 23) | (0x31 << 16) | INSTRUCTION.amplifier_gain;
return NEU_SET_ADC_CLK;
}
// case NEU_SET_SYS_CLK: {
// *value = (0x01 << 23) | (0x32 << 16) | INSTRUCTION.sys_clk_ratio;
// return NEU_SET_ADC_CLK;
// }
case NEU_SET_ADC_CLK: {
if(INSTRUCTION.adc_clock_ratio < 28){
INSTRUCTION.adc_clock_ratio = 28;
}
*value = (0x01 << 23) | (0x33 << 16) | INSTRUCTION.adc_clock_ratio;
// *value = (0x01 << 23) | (0x33 << 16) | 0x00C8;
return NEU_SET_AMP_BIAS;
}
case NEU_SET_AMP_BIAS: {
done = build_amp_bias(value);
if (done)
return NEU_SET_CHOPPER;
else
if (done){
if(STI){
return NEU_SET_STI_CHANNEL;
}
else{
return NEU_SETUP_DONE;
}
}
else{
return NEU_SET_AMP_BIAS;
}
}
case NEU_SET_CHOPPER: {
*value = (0x01 << 23) | (0x3B << 16) | INSTRUCTION.chopper_ratio;
// case NEU_SET_CHOPPER: {
// *value = (0x01 << 23) | (0x3B << 16) | INSTRUCTION.chopper_ratio;
// return NEU_SETUP_DONE;
// }
// enable stimulate
case NEU_SET_STI_CHANNEL: {
*value = (0x01 << 23) | (0x2E << 16) | INSTRUCTION.sti_channel;
return NEU_SETUP_DONE;
}
default: {
@@ -949,26 +1056,52 @@ static uint8_t build_neu_ins_config(uint8_t config_type, uint32_t* value) {
*
* @brief spi transaction
*/
static uint8_t FlushSPICounter = 0;
static void headstage_neu_state_spi() {
uint32_t value;
uint8_t nxt_ins;
uint32_t value = 0;
uint8_t nxt_ins = 0;
switch (NEULIVE_STATE.state) {
case NEU_WRITE_INSTRUCTION: {
SPICallBack = ONE_SHOT_SPI;
nxt_ins = build_neu_ins_config(NEULIVE_STATE.config_type, &value); /**< set instruction one by one in order to set all the parameter.*/
NEULIVE_STATE.config_type = nxt_ins;
tx_put_u24(0, value);
headstage_spi_transaction(3);
if (nxt_ins == NEU_SETUP_DONE) {
NEULIVE_STATE.state = NEU_READ_DATA;
// setting done, reset STI flag
STI = false;
// go to read ADC data
NEULIVE_STATE.state = NEU_PREPARE_READ;
} else {
NEULIVE_STATE.state = NEU_WRITE_INSTRUCTION;
}
AppendSPITX(0, value);
headstage_spi_transaction(3);
break;
}
case NEU_PREPARE_READ:{
if(FlushSPICounter < 6){
SPICallBack = ONE_SHOT_SPI;
NEULIVE_STATE.state = NEU_PREPARE_READ;
FlushSPICounter ++;
AppendSPITX(0, 0);
headstage_spi_transaction(SPI_BUFFER_SIZE);
}
else{
SPICallBack = READ_MOSI;
NEULIVE_STATE.state = NEU_READ_DATA;
headstage_led_color(COLOR_CYAN);
FlushSPICounter = 0;
AppendSPITX(0, 0);
headstage_spi_transaction(SPI_BUFFER_SIZE);
}
break;
}
case NEU_READ_DATA: {
headstage_neu_append_notify_data();
headstage_spi_transaction(3);
// SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, SPI_BUFFER_SIZE, spi_rxbuf);
headstage_spi_transaction(SPI_BUFFER_SIZE);
break;
}
case NEU_SINGLE_INS_READ: {
@@ -1000,4 +1133,22 @@ static void headstage_neu_state_spi() {
}
}
static void headstage_neu_register_spi(){
switch(NeuliveTwoControl.mode){
case MODE_REGISTER_WRITE:{
WriteSPI(3);
break;
}
case MODE_REGISTER_READ:{
ReadSPI();
break;
}
default:{
break;
}
}
}
#endif
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_spi.h
+1 -1
View File
@@ -28,7 +28,7 @@ static SPI_Transaction spi_transaction;
spi_parameter.bitRate = 12000000; \
spi_parameter.transferTimeout = 1000; \
spi_parameter.dataSize = 8; \
spi_parameter.frameFormat = SPI_POL0_PHA0; \
spi_parameter.frameFormat = SPI_POL0_PHA1; \
spi_handle = SPI_open(Board_SPI0, &spi_parameter); \
} while (0)
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_checkMOSI.h
+23
View File
@@ -0,0 +1,23 @@
#ifndef CHECK_MOSI
#define CHECK_MOSI
#include "headstage_led.h"
/*
* MOSI channel meet with INSTRUCTION.recording_channel ?
*/
static uint8_t CheckMOSI(uint8_t* MOSI){
uint8_t ch = MOSI[0];
uint16_t selectCh = 0x0001 << ch;
if(selectCh & INSTRUCTION.recording_channel){
return 1;
}
else{
// headstage_led_color(COLOR_RED);
// headstage_led_color(COLOR_GREEN);
return 0;
}
}
#endif
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_notify.h
+14 -16
View File
@@ -10,12 +10,14 @@
#define NOT_BUF_OFFSET_INIT 8
static uint32_t not_buf_offset = NOT_BUF_OFFSET_INIT;
static uint8_t not_buf_offset = NOT_BUF_OFFSET_INIT;
static uint32_t not_time_stamp = 0;
static void headstage_notify_set_timestamp() {
not_time_stamp = headstage_time_stamp_us();
headstage_notify_buffer[0] = CHIP_ID;
headstage_notify_buffer[1] = 4;
headstage_notify_buffer[2] = not_time_stamp & 0xFF;
headstage_notify_buffer[3] = (not_time_stamp >> 8) & 0xFF;
headstage_notify_buffer[4] = (not_time_stamp >> 16) & 0xFF;
@@ -31,27 +33,23 @@ static void headstage_notify_flip_buffer() {
not_buf_offset = NOT_BUF_OFFSET_INIT;
}
/**
The data format between NEULIVE and CONTROL BOX
Use notification to transmit data to control box through BLE.
Definition of the protocol:
4 byte timestamp + (1 byte channel + 2 byte voltage) * (N)
N: numbers of data transmitted in a transaction
*/
static uint8_t headstage_notify_append_data(uint8_t *data_value) {
if (not_buf_offset <= NOT_BUF_OFFSET_INIT) {
headstage_notify_set_timestamp();
not_buf_offset = NOT_BUF_OFFSET_INIT;
}
if (data_value == NULL) {
headstage_notify_buffer[not_buf_offset++] = 0x00;
headstage_notify_buffer[not_buf_offset++] = 0x03;
} else {
headstage_notify_buffer[not_buf_offset++] = data_value[0];
headstage_notify_buffer[not_buf_offset++] = data_value[1];
}
if (not_buf_offset == BLE_NOT_BUFF_SIZE) {
uint32_t current = headstage_time_stamp_us();
uint32_t time_delta = ((current - not_time_stamp)) & 0xFFFF;
headstage_notify_buffer[6] = time_delta & 0xFF;
headstage_notify_buffer[7] = (time_delta >> 8) & 0xFF;
}
headstage_notify_buffer[not_buf_offset++] = data_value[0];
headstage_notify_buffer[not_buf_offset++] = data_value[1];
headstage_notify_buffer[not_buf_offset++] = data_value[2];
uint8_t ret = not_buf_offset;
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_pin.h
+28 -3
View File
@@ -3,6 +3,9 @@
#ifndef HEADSTAGE_PIN_NEU_H
#define HEADSTAGE_PIN_NEU_H
//#define NEU_2_0
#define NEU_2_1
#if defined(CC2650_LAUNCHXL)
// clang-format off
@@ -11,7 +14,7 @@
#define PIN_DC_DC IOID_2 // STI select need
#define PIN_BATT_HALF IOID_3 //
#define PIN_AMP_VCK IOID_4 //
#define PIN_LED_SDI IOID_7 //
#define PIN_LED_SDI IOID_5 //
#define PIN_LED_CLK IOID_8 //
#define PIN_STI_CLK IOID_9 //
#define PIN_SPI_MISO IOID_10 //
@@ -19,12 +22,15 @@
#define PIN_SPI_CS IOID_12 //
#define PIN_SPI_CLK IOID_13 //
#define PIN_SYS_CLK IOID_14 //
//#define GLED IOID_7
//#define RLED IOID_6
// clang-format on
#elif defined(BOOSTXL_CC2650MA)
// clang-format off
#ifdef NEU_2_0
#define PIN_RESET IOID_0 // SPI1 to receive LSK
#define PIN_EN_ADC_SPI_CLK IOID_1 // SPI1 clock
#define PIN_DC_DC IOID_2 // STI select need
@@ -39,6 +45,22 @@
#define PIN_SPI_CLK IOID_13 //
#define PIN_SYS_CLK IOID_14 //
#elif defined(NEU_2_1)
#define PIN_LED_SDI IOID_0 // SPI1 to receive LSK
#define PIN_LED_CLK IOID_1 // SPI1 clock
#define PIN_DC_DC IOID_2 // STI select need
#define PIN_EN_ADC_SPI_CLK IOID_3 //
#define PIN_BATT_HALF IOID_4 //
#define PIN_SPI_MISO IOID_7 //
#define PIN_SPI_MOSI IOID_8 //
#define PIN_SPI_CS IOID_9 //
#define PIN_SPI_CLK IOID_10 //
#define PIN_SYS_CLK IOID_11 //
#define PIN_RESET IOID_12 //
#define PIN_AMP_VCK IOID_13 //
#define PIN_STI_CLK IOID_14 //
#endif
// clang-format on
#endif
/*
@@ -47,7 +69,8 @@
#define Board_SPI0_MISO PIN_SPI_MISO
#define Board_SPI0_MOSI PIN_SPI_MOSI
#define Board_SPI0_CLK PIN_SPI_CLK
#define Board_SPI0_CSN PIN_SPI_CS
//#define Board_SPI0_CSN PIN_SPI_CS
#define Board_SPI0_CSN PIN_UNASSIGNED
/*
* SPI1 interface work with LED
@@ -78,6 +101,8 @@ static PIN_Config headstage_pin_configuration[] = { //
PIN_DC_DC | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_BATT_HALF | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
PIN_STI_CLK | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
// RLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
// GLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL,
//
PIN_TERMINATE};
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_reset.h
+94
View File
@@ -0,0 +1,94 @@
#ifndef NEU_2_RST
#define NEU_2_RST
#include "headstage_instruction.h"
#include "neu/headstage_spi.h"
static void ResetINSTRUCTION();
static void MCUReset(){
// Reset INSTRUCTION & NEULIVE_STATE
ResetINSTRUCTION();
// SPI buffer reset
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++ ){
spi_txbuf[i] = 0;
spi_rxbuf[i] = 0;
}
SPICallBack = ONE_SHOT_SPI;
// FlushSPICounter = 0;
for(int i=0 ; i<SPI_LED_BUFF_SIZE ; i++){
headstage_spi_led_txbuf[i] = 0;
}
// CIS buffer reset
for(int i=0 ; i<BLE_CDR_BUFF_SIZE ; i++){
cdr_buf[i] = 0;
}
// Notify Buffer reset
for(int i=0 ; i<BLE_NOT_BUFF_SIZE ; i++){
headstage_notify_buffer[i] = 0;
}
not_buf_offset = NOT_BUF_OFFSET_INIT;
not_time_stamp = 0;
headstage_led_color(COLOR_GREEN); // color green
}
static void DBSReset(){
headstage_pin_output(PIN_RESET, 0);
headstage_cpu_delay_ms(10);
headstage_pin_output(PIN_DC_DC, 1);
headstage_pin_output(PIN_EN_ADC_SPI_CLK, 1);
headstage_pin_output(PIN_RESET, 1);
}
static void Neu2Reset(){
DBSReset();
MCUReset();
}
static void ResetINSTRUCTION(){
INSTRUCTION.vgrp = 16;
INSTRUCTION.vgrn = 16;
INSTRUCTION.vgr_intp = 16;
INSTRUCTION.vgr_intn = 16;
INSTRUCTION.vgr_int_old = 16;
INSTRUCTION.recording_channel = 0b0000000000000000;
INSTRUCTION.adc_clock_ratio = 100;
INSTRUCTION.sys_clk_ratio = 10;
INSTRUCTION.sti_clock_ratio = 10;
INSTRUCTION.amplifier_gain = 0;
INSTRUCTION.chopper_ratio = 2;
INSTRUCTION.sti_t1[1] = 1;
INSTRUCTION.sti_t2[1] = 0;
INSTRUCTION.sti_t3[1] = 0;
INSTRUCTION.sti_t4[1] = 0;
INSTRUCTION.sti_t5[1] = 0;
INSTRUCTION.sti_channel = 2;
INSTRUCTION.arbitrary_en = 0;
INSTRUCTION.arbitrary_index = 0;
INSTRUCTION.sti_h_bridge = 0;
INSTRUCTION.sti_mode = 0;
INSTRUCTION.sti_ref = 0;
INSTRUCTION.current_sti_polarity = 2;
INSTRUCTION.sti_amplitude_h = 0;
INSTRUCTION.sti_amplitude_l = 0;
INSTRUCTION.ins_opcode = BIAS_ONE;
uint8_t voltage_sti_channel = 0;
uint8_t voltage_sti_amplitude = 0;
for(int i=0 ; i<NEU_STI_CHANNEL_COUNTS ; i++){
INSTRUCTION.current_sti_cycle[i] = 0;
}
NEULIVE_STATE.state = NEU_IDLE;
NEULIVE_STATE.config_type = 0;
NEULIVE_STATE.index = 0;
}
#endif
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_spi.h
+62 -10
View File
@@ -12,7 +12,8 @@
#include <ti/drivers/dma/UDMACC26XX.h>
#include <ti/drivers/spi/SPICC26XXDMA.h>
#define SPI_BUFFER_SIZE 20
#define SPI_BUFFER_SIZE 3
#define SPI_RX_SIZE 9
static uint8_t spi_txbuf[SPI_BUFFER_SIZE] = {0};
static uint8_t spi_rxbuf[SPI_BUFFER_SIZE] = {0};
@@ -22,6 +23,7 @@ static SPI_Handle headstage_spi_handle = NULL;
static SPI_Transaction headstage_spi_transaction;
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction);
static bool OpenSPI = false;
// SPI parameters initialize
#define headstage_spi_open() \
@@ -38,14 +40,14 @@ static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transacti
headstage_spi_handle = SPI_open(Board_SPI0, &spi_parameter); \
} while (0)
#define headstage_spi_transaction(handle, length, tx, rx) \
({ \
SPI_Transaction transaction = headstage_spi_transaction ; \
transaction.count = (length); \
transaction.txBuf = (tx); \
transaction.rxBuf = (rx); \
SPI_transfer(handle, &transaction); \
})
//#define headstage_spi_transaction(handle, length, tx, rx) \
// ({ \
// SPI_Transaction transaction = headstage_spi_transaction ; \
// transaction.count = (length); \
// transaction.txBuf = (tx); \
// transaction.rxBuf = (rx); \
// SPI_transfer(handle, &transaction); \
// })
#define headstage_spi_transaction(length) \
({ \
@@ -70,4 +72,54 @@ static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transacti
} \
} while (0)
#endif
static void ReopenSPI(){
SPI_init();
SPI_Params spi_parameter;
SPI_Params_init(&spi_parameter);
spi_parameter.transferMode = SPI_MODE_CALLBACK;
spi_parameter.mode = SPI_SLAVE;
spi_parameter.bitRate = NEU_SPI_FREQ;
spi_parameter.dataSize = 8;
spi_parameter.frameFormat = SPI_POL0_PHA1;
spi_parameter.transferCallbackFxn = headstage_spi_callback;
headstage_spi_handle = SPI_open(Board_SPI0, &spi_parameter);
}
static void WriteSPI(uint8_t length){
if(OpenSPI){
ReopenSPI();
}
for(int i=length ; i<SPI_BUFFER_SIZE ; i++){
spi_rxbuf[i] = 0x00;
}
SPICallBack = FLUSH_BUFFER;
headstage_spi_transaction.count = 3;
headstage_spi_transaction.txBuf = spi_txbuf;
headstage_spi_transaction.rxBuf = spi_rxbuf;
SPI_transfer(headstage_spi_handle, &headstage_spi_transaction);
}
static void ReadSPI(){
if(OpenSPI){
ReopenSPI();
}
SPICallBack = READ_REG;
headstage_spi_transaction.count = 3;
headstage_spi_transaction.txBuf = spi_txbuf;
headstage_spi_transaction.rxBuf = spi_rxbuf;
SPI_transfer(headstage_spi_handle, &headstage_spi_transaction);
}
static void AppendSPITX(uint8_t index, uint32_t value){
tx_put_u24(index, value);
for(int i=3 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0;
}
}
#endif
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/simple_peripheral.c
+19 -22
View File
@@ -153,7 +153,7 @@
#define SBP_TASK_PRIORITY 1
#ifndef SBP_TASK_STACK_SIZE
#define SBP_TASK_STACK_SIZE 1024
#define SBP_TASK_STACK_SIZE 844
#endif
// Internal Events for RTOS application
@@ -408,12 +408,10 @@ static void SimpleBLEPeripheral_init(void) {
// Register for GATT local events and ATT Responses pending for transmission
GATT_RegisterForMsgs(self);
HCI_LE_ReadMaxDataLenCmd();
// HCI_LE_ReadMaxDataLenCmd();
//
// HCI_LE_WriteSuggestedDefaultDataLenCmd(251, 2120); // this is used for data length extension
HCI_LE_WriteSuggestedDefaultDataLenCmd(251, 2120); // this is used for data length extension
uint8_t prepare_write_req = 6;
GATTServApp_SetParameter(GATT_PARAM_NUM_PREPARE_WRITES, 1, &prepare_write_req);
}
#ifndef DEVICE_NAME
@@ -583,19 +581,19 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
ICall_freeMsg(message);
}
}
}
// If RTOS queue is not empty, process app message.
while (!Queue_empty(application_message_queue)) {
sbpEvt_t *message = (sbpEvt_t *)Util_dequeueMsg(application_message_queue);
if (message) {
// Process message.
SimpleBLEPeripheral_processAppMsg(message);
// If RTOS queue is not empty, process app message.
while (!Queue_empty(application_message_queue)) {
sbpEvt_t *message = (sbpEvt_t *)Util_dequeueMsg(application_message_queue);
if (message) {
// Process message.
SimpleBLEPeripheral_processAppMsg(message);
// Free the space from the message.
ICall_free(message);
}
// Free the space from the message.
ICall_free(message);
}
}
if (EVENT_MASK > 0) {
headstage_event_handle();
}
@@ -678,8 +676,8 @@ static uint8_t SimpleBLEPeripheral_processGATTMsg(gattMsgEvent_t *message) {
} else if (message->method == ATT_MTU_UPDATED_EVENT) {
// MTU size updated
headstage_debug_buffer[10] = 0xff;
headstage_set_debug_information();
// headstage_debug_buffer[10] = 0xff;
// headstage_set_debug_information();
} else if (message->method == ATT_HANDLE_VALUE_CFM) {
// quick pass
}
@@ -825,11 +823,11 @@ static void SimpleBLEPeripheral_processStateChangeEvt(gaprole_States_t newState)
uint8_t numActive = 0;
numActive = linkDB_NumActive();
headstage_led_color(COLOR_CYAN);
headstage_led_color(COLOR_RED);
uint16_t cxnHandle;
uint16_t requestedPDUSize = 251;
uint16_t requestTxTime = 2120;
uint16_t requestedPDUSize = 251; // payload = 251 - 7 = 244 byte
uint16_t requestTxTime = 2120; // 2 ms
GAPRole_GetParameter(GAPROLE_CONNHANDLE, &cxnHandle);
if (SUCCESS != HCI_LE_SetDataLenCmd(cxnHandle, requestedPDUSize, requestTxTime)) {
@@ -841,7 +839,6 @@ static void SimpleBLEPeripheral_processStateChangeEvt(gaprole_States_t newState)
uint8_t peerAddress[B_ADDR_LEN];
GAPRole_GetParameter(GAPROLE_CONN_BD_ADDR, peerAddress);
}
flag_notify(EVT_CONNECTED);
break;
}
simplelink/ble_sdk_2_02_02_25/src/profiles/simple_profile/simple_gatt_profile.h
+2 -1
View File
@@ -84,7 +84,8 @@ extern "C" {
#define SIMPLEPROFILE_CHAR1_LEN 2
#define SIMPLEPROFILE_CHAR2_LEN 10
#define SIMPLEPROFILE_CHAR3_LEN 20
#define SIMPLEPROFILE_CHAR4_LEN 200
#define SIMPLEPROFILE_CHAR4_LEN 193
#define SIMPLEPROFILE_CHAR4_LEN 20 // 8 header + 3n data, n=3
#define SIMPLEPROFILE_CHAR5_LEN 20
/*********************************************************************