updated: idle訊號改成highZ訊號

2. fix anode and cathode ilde time: 1ms

app_config.h

@@ -18,6 +18,7 @@ extern "C"
 #define NRF_LOG_DEFERRED                            0
 #define NRF_LOG_USES_TIMESTAMP                      0
 #define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 0
+#define NRF_LOG_MSGPOOL_ELEMENT_COUNT               31
 
 // SEGGER-RTT
 #define SEGGER_RTT_SECTION                          ".segger_rtt"
@@ -103,10 +104,10 @@ extern "C"
 
 // BLE device name
 #define DEF_ELITE_DEV                               0x00000000
-#define DEF_ELITE_EDC_20                            0x00020109
-#define DEF_PULSE_E_LOAD_10                         0x00070000
-#define DEF_CURRENT_PULSE_GANERATOR_10              0x00080000
-#define DEF_ELITE_MODEL                             DEF_ELITE_DEV
+#define DEF_ELITE_EDC_V2_0                          0x00020109
+#define DEF_ELITE_PEL_V2_0                          0x00070001
+#define DEF_ELITE_CPG_V1_1                          0x00080001
+#define DEF_ELITE_MODEL                             DEF_ELITE_CPG_V1_1
 
 #if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
 #define ELITE_DEVICE_NAME       "Elite-Dev"
@@ -115,6 +116,8 @@ extern "C"
 #define MAJOR_VERSION_NUMBER    0
 #define MINOR_VERSION_NUMBER    0
 
+#define DEF_TW1508_ENABLED      0
+
 #define DEF_LED_COUNT           0
 #define DEF_LED_DRV_ENABLED     0
 #define DEF_APA102_2020_ENABLED 0
@@ -127,6 +130,7 @@ extern "C"
 #define DEF_MAX5136_ENABLED     0
 
 #define DEF_SW_DRV_ENABLED      0
+#define DEF_MAX14802_ENABLED    0
 #define DEF_ADGS1412_ENABLED    0
 
 #define DEF_FS_ENABLED          0
@@ -137,13 +141,15 @@ extern "C"
 
 #define DEF_RTT_JSCOP_ENABLED   0
 
-#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
 #define ELITE_DEVICE_NAME       "Elite-EDC"
 #define MAJOR_PRODUCT_NUMBER    0
 #define MINOR_PRODUCT_NUMBER    2
 #define MAJOR_VERSION_NUMBER    1
 #define MINOR_VERSION_NUMBER    9
 
+#define DEF_TW1508_ENABLED      0
+
 #define DEF_LED_COUNT           12
 #define DEF_LED_DRV_ENABLED     1
 #define DEF_APA102_2020_ENABLED 1
@@ -156,6 +162,7 @@ extern "C"
 #define DEF_MAX5136_ENABLED     1
 
 #define DEF_SW_DRV_ENABLED      1
+#define DEF_MAX14802_ENABLED    0
 #define DEF_ADGS1412_ENABLED    1
 
 #define DEF_FS_ENABLED          0
@@ -166,12 +173,14 @@ extern "C"
 
 #define DEF_RTT_JSCOP_ENABLED   0
 
-#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
 #define ELITE_DEVICE_NAME       "Elite-PEL"
 #define MAJOR_PRODUCT_NUMBER    0
-#define MINOR_PRODUCT_NUMBER    2
-#define MAJOR_VERSION_NUMBER    1
-#define MINOR_VERSION_NUMBER    9
+#define MINOR_PRODUCT_NUMBER    7
+#define MAJOR_VERSION_NUMBER    0
+#define MINOR_VERSION_NUMBER    1
+
+#define DEF_TW1508_ENABLED      0
 
 #define DEF_LED_COUNT           0
 #define DEF_LED_DRV_ENABLED     0
@@ -185,6 +194,7 @@ extern "C"
 #define DEF_MAX5136_ENABLED     0
 
 #define DEF_SW_DRV_ENABLED      0
+#define DEF_MAX14802_ENABLED    0
 #define DEF_ADGS1412_ENABLED    0
 
 #define DEF_FS_ENABLED          0
@@ -195,12 +205,14 @@ extern "C"
 
 #define DEF_RTT_JSCOP_ENABLED   0
 
-#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
 #define ELITE_DEVICE_NAME       "Elite-CPG"
 #define MAJOR_PRODUCT_NUMBER    0
-#define MINOR_PRODUCT_NUMBER    2
-#define MAJOR_VERSION_NUMBER    1
-#define MINOR_VERSION_NUMBER    9
+#define MINOR_PRODUCT_NUMBER    8
+#define MAJOR_VERSION_NUMBER    0
+#define MINOR_VERSION_NUMBER    1
+
+#define DEF_TW1508_ENABLED      1
 
 #define DEF_LED_COUNT           0
 #define DEF_LED_DRV_ENABLED     0
@@ -213,7 +225,8 @@ extern "C"
 #define DEF_DAC_DRV_ENABLED     0
 #define DEF_MAX5136_ENABLED     0
 
-#define DEF_SW_DRV_ENABLED      0
+#define DEF_SW_DRV_ENABLED      1
+#define DEF_MAX14802_ENABLED    1
 #define DEF_ADGS1412_ENABLED    0
 
 #define DEF_FS_ENABLED          0
@@ -282,6 +295,7 @@ extern "C"
 
 #define COUNT_ARRAY_SIZE(x)                        (sizeof(x) / sizeof(x[0]))
 #define COUNTOF(x)                                 (sizeof(x) / sizeof(x[0]))
+#define UNCONNECTED_PIN                            0xFFFFFFFF
 
 #ifdef __cplusplus
 }

bmd380_peripheral-Debug.vgdbsettings

@@ -25,7 +25,6 @@
     <ProjectFile>bmd380_peripheral.vcxproj</ProjectFile>
     <RemoteBuildEnvironment>
       <Records />
-      <EnvironmentSetupFiles />
     </RemoteBuildEnvironment>
     <ParallelJobCount>1</ParallelJobCount>
     <SuppressDirectoryChangeMessages>true</SuppressDirectoryChangeMessages>
@@ -111,12 +110,9 @@
       <MaxBreakpointLimit>0</MaxBreakpointLimit>
       <EnableVerboseMode>true</EnableVerboseMode>
       <EnablePrettyPrinters>false</EnablePrettyPrinters>
-      <EnableAbsolutePathReporting>true</EnableAbsolutePathReporting>
     </AdditionalGDBSettings>
     <DebugMethod>
       <ID>jlink-jtag</ID>
-      <InterfaceID>com.sysprogs.debug.jlink.jlinksw</InterfaceID>
-      <InterfaceSerialNumber>000801018887</InterfaceSerialNumber>
       <Configuration xsi:type="com.visualgdb.edp.segger.settings">
         <CommandLine>-select USB -device $$SYS:MCU_ID$$ -speed auto -if SWD</CommandLine>
         <ProgramMode>Enabled</ProgramMode>
@@ -145,13 +141,6 @@
     <TimestampProviderTicksPerSecond>64000000</TimestampProviderTicksPerSecond>
     <KeepConsoleAfterExit>false</KeepConsoleAfterExit>
     <UnusedStackFillPattern xsi:nil="true" />
-    <RelatedExecutables>
-      <RelatedExecutable>
-        <Program>false</Program>
-        <LoadSymbols>false</LoadSymbols>
-        <ShowInLiveWatch>false</ShowInLiveWatch>
-      </RelatedExecutable>
-    </RelatedExecutables>
     <CheckInterfaceDrivers>true</CheckInterfaceDrivers>
   </Debug>
 </VisualGDBProjectSettings2>

bmd380_peripheral.vcxproj

@@ -32,13 +32,13 @@
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|VisualGDB'">
     <GNUConfigurationType>Debug</GNUConfigurationType>
     <ToolchainID>com.visualgdb.arm-eabi</ToolchainID>
-    <ToolchainVersion>12.3.1/13.2/r1</ToolchainVersion>
+    <ToolchainVersion>13.3.1/15.1/r2</ToolchainVersion>
     <GenerateHexFile>true</GenerateHexFile>
     <MCUPropertyListFile>$(ProjectDir)nrf5x.props</MCUPropertyListFile>
   </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|VisualGDB'">
     <ToolchainID>com.visualgdb.arm-eabi</ToolchainID>
-    <ToolchainVersion>12.3.1/13.2/r1</ToolchainVersion>
+    <ToolchainVersion>13.3.1/15.1/r2</ToolchainVersion>
     <GenerateHexFile>true</GenerateHexFile>
     <MCUPropertyListFile>$(ProjectDir)nrf5x.props</MCUPropertyListFile>
   </PropertyGroup>
@@ -46,7 +46,7 @@
     <ClCompile>
       <CLanguageStandard>GNU99</CLanguageStandard>
       <AdditionalIncludeDirectories>.;../bmd380_sdk/components/softdevice/s140/headers;../bmd380_sdk/components/softdevice/s140/headers/nrf52;../bmd380_sdk/external/segger_rtt;../bmd380_sdk/components/libraries/log;../bmd380_sdk/components/libraries/log/src;../bmd380_sdk/components/libraries/memobj;../bmd380_sdk/components/libraries/ringbuf;../bmd380_sdk/components/libraries/atomic;../bmd380_sdk/components/libraries/balloc;../bmd380_sdk/external/freertos/portable/CMSIS/nrf52;../bmd380_sdk/external/freertos/portable/GCC/nrf52;../bmd380_sdk/integration/nrfx;../bmd380_sdk/integration/nrfx/legacy;../bmd380_sdk/components/libraries/experimental_section_vars;../bmd380_sdk/components/libraries/strerror;../bmd380_sdk/external/freertos/source/include;../bmd380_sdk/components/softdevice/common;../bmd380_sdk/components/ble/common;../bmd380_sdk/components/ble/ble_advertising;../bmd380_sdk/components/libraries/atomic_flags;../bmd380_sdk/components/ble/ble_db_discovery;../bmd380_sdk/components/ble/ble_dtm;../bmd380_sdk/components/ble/ble_link_ctx_manager;../bmd380_sdk/components/ble/ble_racp;../bmd380_sdk/components/ble/ble_radio_notification;../bmd380_sdk/components/ble/ble_services/ble_ancs_c;../bmd380_sdk/components/ble/ble_services/ble_ans_c;../bmd380_sdk/components/ble/ble_services/ble_bas;../bmd380_sdk/components/ble/ble_services/ble_bas_c;../bmd380_sdk/components/ble/ble_services/ble_bps;../bmd380_sdk/components/ble/ble_services/ble_cscs;../bmd380_sdk/components/ble/ble_services/ble_cts_c;../bmd380_sdk/components/ble/ble_services/ble_dfu;../bmd380_sdk/components/ble/ble_services/ble_dis;../bmd380_sdk/components/ble/ble_services/ble_dis_c;../bmd380_sdk/components/ble/ble_services/ble_escs;../bmd380_sdk/components/ble/ble_services/ble_gls;../bmd380_sdk/components/ble/ble_services/ble_hids;../bmd380_sdk/components/ble/ble_services/ble_hrs;../bmd380_sdk/components/ble/ble_services/ble_hrs_c;../bmd380_sdk/components/ble/ble_services/ble_hts;../bmd380_sdk/components/ble/ble_services/ble_ias;../bmd380_sdk/components/ble/ble_services/ble_ias_c;../bmd380_sdk/components/ble/ble_services/ble_ipsp;../bmd380_sdk/components/ble/ble_services/ble_lbs;../bmd380_sdk/components/ble/ble_services/ble_lbs_c;../bmd380_sdk/components/ble/ble_services/ble_lls;../bmd380_sdk/components/ble/ble_services/ble_nus;../bmd380_sdk/components/ble/ble_services/ble_nus_c;../bmd380_sdk/components/ble/ble_services/ble_rscs;../bmd380_sdk/components/ble/ble_services/ble_rscs_c;../bmd380_sdk/components/ble/ble_services/ble_tps;../bmd380_sdk/components/ble/ble_services/eddystone;../bmd380_sdk/components/ble/ble_services/experimental_ble_lns;../bmd380_sdk/components/ble/ble_services/experimental_ble_ots;../bmd380_sdk/components/ble/ble_services/experimental_gatts_c;../bmd380_sdk/components/ble/ble_services/experimental_nrf_ble_cgms;../bmd380_sdk/components/ble/ble_services/experimental_nrf_ble_ots_c;../bmd380_sdk/components/ble/ble_services/nrf_ble_bms;../bmd380_sdk/components/ble/nrf_ble_gatt;../bmd380_sdk/components/ble/nrf_ble_gq;../bmd380_sdk/components/ble/nrf_ble_qwr;../bmd380_sdk/components/ble/nrf_ble_scan;../bmd380_sdk/components/ble/peer_manager;../bmd380_sdk/components/libraries/pwr_mgmt;littlefs;%(ClCompile.AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
-      <PreprocessorDefinitions>DEBUG=1;USE_APP_CONFIG=1;LFS_THREADSAFE=1;%(ClCompile.PreprocessorDefinitions)</PreprocessorDefinitions>
+      <PreprocessorDefinitions>DEBUG=1;USE_APP_CONFIG=1;LFS_THREADSAFE=1;CONFIG_NFCT_PINS_AS_GPIOS;%(ClCompile.PreprocessorDefinitions)</PreprocessorDefinitions>
       <AdditionalOptions />
       <CPPLanguageStandard />
       <Optimization>O0</Optimization>
@@ -198,14 +198,15 @@
     <ClCompile Include="btn.c" />
     <ClCompile Include="builtin_saadc.c" />
     <ClCompile Include="cpg.c" />
-    <ClCompile Include="cpg10_dev_mode.c" />
-    <ClCompile Include="cpg10_io.c" />
+    <ClCompile Include="cpg11_dev_mode.c" />
+    <ClCompile Include="cpg11_io.c" />
     <ClCompile Include="elite_board.c" />
     <ClCompile Include="dac_drv.c" />
     <ClCompile Include="elite_dev.c" />
     <ClCompile Include="edc20_cycle_iv_mode.c" />
     <ClCompile Include="fs.c" />
     <ClCompile Include="gd25d10c.c" />
+    <ClCompile Include="max14802.c" />
     <ClCompile Include="max5136.c" />
     <ClCompile Include="edc20_io.c" />
     <ClCompile Include="edc20.c" />
@@ -223,9 +224,13 @@
     <ClCompile Include="main.c" />
     <ClCompile Include="j_scop.c" />
     <ClCompile Include="pel.c" />
-    <ClCompile Include="pel10_io.c" />
+    <ClCompile Include="pel20_io.c" />
     <ClCompile Include="sw_drv.c" />
     <ClCompile Include="syscalls.c" />
+    <ClCompile Include="tw1508.c" />
+    <ClInclude Include="max14802.h" />
+    <ClInclude Include="pel20_io.h" />
+    <ClInclude Include="tw1508.h" />
     <None Include="nRF52811_XXAA_s140.lds" />
     <None Include="nRF52840_XXAA_S140_reserve.lds" />
     <None Include="nrf5x.props" />
@@ -377,8 +382,8 @@
     <ClInclude Include="block_dev_drv_if.h" />
     <ClInclude Include="btn.h" />
     <ClInclude Include="cpg.h" />
-    <ClInclude Include="cpg10_dev_mode.h" />
-    <ClInclude Include="cpg10_io.h" />
+    <ClInclude Include="cpg11_dev_mode.h" />
+    <ClInclude Include="cpg11_io.h" />
     <ClInclude Include="dac_drv.h" />
     <ClInclude Include="dac_drv_if.h" />
     <ClInclude Include="edc.h" />
@@ -399,7 +404,6 @@
     <ClInclude Include="led_drv_if.h" />
     <ClInclude Include="max5136.h" />
     <ClInclude Include="pel.h" />
-    <ClInclude Include="pel10_io.h" />
     <ClInclude Include="sw_drv.h" />
     <ClInclude Include="sw_drv_if.h" />
     <ClInclude Include="sdk_config.h" />

bmd380_peripheral.vcxproj.filters

@@ -1380,9 +1380,6 @@
     <ClCompile Include="adgs1412.c">
       <Filter>Source files</Filter>
     </ClCompile>
-    <ClCompile Include="builtin_saadc.c.c">
-      <Filter>Source files</Filter>
-    </ClCompile>
     <ClCompile Include="sw_drv.c">
       <Filter>Source files</Filter>
     </ClCompile>
@@ -1428,9 +1425,6 @@
     <ClCompile Include="elite_dac.c">
       <Filter>Source files</Filter>
     </ClCompile>
-    <ClCompile Include="pel10_io.c">
-      <Filter>Source files</Filter>
-    </ClCompile>
     <ClCompile Include="btn.c">
       <Filter>Source files</Filter>
     </ClCompile>
@@ -1443,6 +1437,27 @@
     <ClCompile Include="edc20_cycle_iv_mode.c">
       <Filter>Source files</Filter>
     </ClCompile>
+    <ClCompile Include="builtin_saadc.c">
+      <Filter>Source files</Filter>
+    </ClCompile>
+    <ClCompile Include="cpg.c">
+      <Filter>Source files</Filter>
+    </ClCompile>
+    <ClCompile Include="cpg11_dev_mode.c">
+      <Filter>Source files</Filter>
+    </ClCompile>
+    <ClCompile Include="cpg11_io.c">
+      <Filter>Source files</Filter>
+    </ClCompile>
+    <ClCompile Include="tw1508.c">
+      <Filter>Source files</Filter>
+    </ClCompile>
+    <ClCompile Include="max14802.c">
+      <Filter>Source files</Filter>
+    </ClCompile>
+    <ClCompile Include="pel20_io.c">
+      <Filter>Source files</Filter>
+    </ClCompile>
   </ItemGroup>
   <ItemGroup>
     <None Include="nRF52840_XXAA_S140_reserve.lds">
@@ -1756,9 +1771,6 @@
     <ClInclude Include="fs.h">
       <Filter>Header files</Filter>
     </ClInclude>
-    <ClInclude Include="board_pulse_e_load01.h">
-      <Filter>Header files</Filter>
-    </ClInclude>
     <ClInclude Include="edc.h">
       <Filter>Header files</Filter>
     </ClInclude>
@@ -1786,9 +1798,6 @@
     <ClInclude Include="elite_def.h">
       <Filter>Header files</Filter>
     </ClInclude>
-    <ClInclude Include="pel10_io.h">
-      <Filter>Header files</Filter>
-    </ClInclude>
     <ClInclude Include="btn.h">
       <Filter>Header files</Filter>
     </ClInclude>
@@ -1798,6 +1807,24 @@
     <ClInclude Include="pel.h">
       <Filter>Header files</Filter>
     </ClInclude>
+    <ClInclude Include="tw1508.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="cpg.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="cpg11_dev_mode.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="cpg11_io.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="max14802.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
+    <ClInclude Include="pel20_io.h">
+      <Filter>Header files</Filter>
+    </ClInclude>
   </ItemGroup>
   <ItemGroup>
     <Text Include="..\bmd380_sdk\external\segger_rtt\license\license.txt">

cpg.c

@@ -1,6 +1,6 @@
-#include "cpg10_dev_mode.h"
+#include "cpg11_dev_mode.h"
 #include "pel.h"
-#include "pel10_io.h"
+#include "elite_board.h"
 
 #include "elite_def.h"
 
@@ -8,13 +8,15 @@
 #include "nrf_gpio.h"
 #include "nrf_log.h"
 
-#if (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+#include "tw1508.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
 
 #define VERSION_DATE_YEAR   24
-#define VERSION_DATE_MONTH  5
-#define VERSION_DATE_DAY    21
-#define VERSION_DATE_HOUR   18
-#define VERSION_DATE_MINUTE 39
+#define VERSION_DATE_MONTH  9
+#define VERSION_DATE_DAY    26
+#define VERSION_DATE_HOUR   11
+#define VERSION_DATE_MINUTE 04
 static void cis_version(uint8_t *ins, uint16_t size)
 {
     NRF_LOG_INFO("%s", __FUNCTION__);
@@ -44,19 +46,32 @@ void dev_mode(uint8_t *ins, uint16_t size)
         uint8_t id     : 4;
         uint8_t        : 4;
         uint16_t magic : 16;
-        uint8_t dev_opcode;
-        uint8_t function_opcode;
+        uint8_t func_id;
+        uint8_t opcode;
         uint8_t param[];
     } *p_ins = (void *)ins;
 
-    switch (p_ins->dev_opcode)
+    switch (p_ins->func_id)
     {
-        case 0x90:
-            dev_mode_set_cpg10_electrodes(ins);
+        case 0x00:
+            dev_mode_electrode_switch(ins);
             break;
 
+        case 0x01:
+            dev_mode_tw1508(ins);
+            break;
+
+        case 0x02:
+            dev_mode_ctrl_cpg11_electrodes_task(ins);
+            break;
+
+        case 0x03:
+            dev_mode_adapter_block_switch(ins);
+            break;
+
+        // 0xA0 to 0xBF are reserved for controlling the BMD380
         case 0xA0:
-            dev_mode_gpio_function(ins);
+            dev_mode_gpio(ins);
             break;
 
         case 0xA1:
@@ -67,6 +82,11 @@ void dev_mode(uint8_t *ins, uint16_t size)
             // i2c
             break;
 
+        // 0xF0 to 0xFF are reserved for calibration
+        case 0xF0:
+            // cali
+            break;
+
         default:
             break;
     }
@@ -86,6 +106,8 @@ const elite_instance_t cpg_elite_instance = {
 
 const elite_instance_t *cpg_init(void)
 {
+    tw1508_init();
+    tw1508_set(5, 5); // 5*0.13= 0.65mA, formula:value*0.13=mA
     return &cpg_elite_instance;
 }
 

cpg10_dev_mode.c

@@ -1,264 +0,0 @@
-#include "cpg10_dev_mode.h"
-
-#include "nrf_gpio.h"
-#include "nrf_log.h"
-
-#if (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
-
-// The GPIO corresponding to the pin
-const uint32_t pin_to_gpio_table[] = {
-    [6]  = NRF_GPIO_PIN_MAP(0, 22),
-    [8]  = NRF_GPIO_PIN_MAP(0, 25),
-    [9]  = NRF_GPIO_PIN_MAP(0, 19),
-    [10] = NRF_GPIO_PIN_MAP(0, 21),
-    [11] = NRF_GPIO_PIN_MAP(1, 00),
-    [12] = NRF_GPIO_PIN_MAP(0, 18),
-    [13] = NRF_GPIO_PIN_MAP(0, 17),
-    [14] = NRF_GPIO_PIN_MAP(0, 20),
-    [16] = NRF_GPIO_PIN_MAP(0, 14),
-    [17] = NRF_GPIO_PIN_MAP(0, 13),
-    [18] = NRF_GPIO_PIN_MAP(0, 11),
-    [20] = NRF_GPIO_PIN_MAP(0, 15),
-    [25] = NRF_GPIO_PIN_MAP(1, 8),
-    [26] = NRF_GPIO_PIN_MAP(0, 12),
-    [27] = NRF_GPIO_PIN_MAP(0, 7),
-    [28] = NRF_GPIO_PIN_MAP(1, 9),
-    [29] = NRF_GPIO_PIN_MAP(0, 8),
-    [30] = NRF_GPIO_PIN_MAP(0, 6),
-    [31] = NRF_GPIO_PIN_MAP(0, 5),
-    [32] = NRF_GPIO_PIN_MAP(0, 27),
-    [33] = NRF_GPIO_PIN_MAP(0, 26),
-    [34] = NRF_GPIO_PIN_MAP(0, 4),
-    [36] = NRF_GPIO_PIN_MAP(0, 1),
-    [37] = NRF_GPIO_PIN_MAP(0, 29),
-    [38] = NRF_GPIO_PIN_MAP(0, 0),
-    [39] = NRF_GPIO_PIN_MAP(0, 31),
-    [40] = NRF_GPIO_PIN_MAP(1, 15),
-    [41] = NRF_GPIO_PIN_MAP(0, 2),
-    [42] = NRF_GPIO_PIN_MAP(0, 30),
-    [43] = NRF_GPIO_PIN_MAP(0, 28),
-    [44] = NRF_GPIO_PIN_MAP(1, 12),
-    [45] = NRF_GPIO_PIN_MAP(1, 14),
-    [46] = NRF_GPIO_PIN_MAP(0, 3),
-    [47] = NRF_GPIO_PIN_MAP(1, 13),
-    [48] = NRF_GPIO_PIN_MAP(1, 3),
-    [49] = NRF_GPIO_PIN_MAP(1, 10),
-    [50] = NRF_GPIO_PIN_MAP(1, 6),
-    [51] = NRF_GPIO_PIN_MAP(1, 11),
-    [52] = NRF_GPIO_PIN_MAP(0, 10),
-    [53] = NRF_GPIO_PIN_MAP(0, 9),
-    [59] = NRF_GPIO_PIN_MAP(1, 2),
-    [60] = NRF_GPIO_PIN_MAP(0, 24),
-    [61] = NRF_GPIO_PIN_MAP(0, 23),
-    [62] = NRF_GPIO_PIN_MAP(0, 16),
-};
-
-static uint32_t bmd380pins_convert_to_gpio(uint32_t pin)
-{
-    uint32_t gpio;
-
-    switch (pin)
-    {
-        case 6:
-        case 8:
-        case 9:
-        case 10:
-        case 11:
-        case 12:
-        case 13:
-        case 14:
-        case 16:
-        case 17:
-        case 18:
-        case 20:
-        case 25:
-        case 26:
-        case 27:
-        case 28:
-        case 29:
-        case 30:
-        case 31:
-        case 32:
-        case 33:
-        case 34:
-        case 36:
-        case 37:
-        case 38:
-        case 39:
-        case 40:
-        case 41:
-        case 42:
-        case 43:
-        case 44:
-        case 45:
-        case 46:
-        case 47:
-        case 48:
-        case 49:
-        case 50:
-        case 51:
-        case 52:
-        case 53:
-        case 59:
-        case 60:
-        case 61:
-        case 62:
-            gpio = pin_to_gpio_table[pin];
-            break;
-        default:
-            gpio = UNDEF_GPIO;
-            NRF_LOG_INFO("UNDEF_GPIO: pin %d can't convert to gpio number", pin);
-            break;
-    }
-
-    return gpio;
-}
-
-static void set_bmd380_pin_signal(uint32_t pin, uint32_t high_low)
-{
-    uint32_t gpio = bmd380pins_convert_to_gpio(pin);
-
-    if (gpio != UNDEF_GPIO)
-    {
-        nrf_gpio_pin_write(gpio, high_low);
-        NRF_LOG_INFO("set pin %d (gpio %d) = %d", pin, gpio, high_low);
-    }
-}
-
-/*
-    dev_mode_gpio_function
-    (1)0x3000FFA000ppss
-            -func: set_bmd380_pin_signal
-            -pp: pin number     06h-3Fh
-                06h: P0.22_GPIO
-                08h: P0.25_GPIO
-                ......
-                3Eh:P0.16_GPIO
-            -ss: signal         00h-01h
-                00h: low
-                01h: high
-*/
-void dev_mode_gpio_function(uint8_t *ins)
-{
-    struct __PACKED
-    {
-        uint8_t id     : 4;
-        uint8_t        : 4;
-        uint16_t magic : 16;
-        uint8_t dev_opcode;
-        uint8_t gpio_function_opcode;
-        uint8_t param[];
-    } *p_ins = (void *)ins;
-
-    switch (p_ins->gpio_function_opcode)
-    {
-        case 0x00: {
-            uint32_t pin      = p_ins->param[0];
-            uint32_t high_low = p_ins->param[1];
-            set_bmd380_pin_signal(pin, high_low);
-            break;
-        }
-    }
-}
-
-#define ELECTRODES_A1HB1L 0
-#define ELECTRODES_A1LB1H 1
-#define ELECTRODES_A2HB2L 2
-#define ELECTRODES_A2LB2H 3
-#define ELECTRODES_A3HB3L 4
-#define ELECTRODES_A3LB3H 5
-#define ELECTRODES_A4HB4L 6
-#define ELECTRODES_A4LB4H 7
-static void cpg10_electrodes(uint32_t electrodes_mode)
-{
-    switch (electrodes_mode)
-    {
-        case ELECTRODES_A1HB1L:
-            nrf_gpio_pin_write(VB1H_PIN, 1);
-            nrf_gpio_pin_write(VA1L_PIN, 0);
-            nrf_gpio_pin_write(VA1H_PIN, 0);
-            nrf_gpio_pin_write(VB1L_PIN, 1);
-            break;
-
-        case ELECTRODES_A1LB1H:
-            nrf_gpio_pin_write(VA1H_PIN, 1);
-            nrf_gpio_pin_write(VB1L_PIN, 0);
-            nrf_gpio_pin_write(VB1H_PIN, 0);
-            nrf_gpio_pin_write(VA1L_PIN, 1);
-            break;
-
-        case ELECTRODES_A2HB2L:
-            nrf_gpio_pin_write(VB2H_PIN, 1);
-            nrf_gpio_pin_write(VA2L_PIN, 0);
-            nrf_gpio_pin_write(VA2H_PIN, 0);
-            nrf_gpio_pin_write(VB2L_PIN, 1);
-            break;
-
-        case ELECTRODES_A2LB2H:
-            nrf_gpio_pin_write(VA2H_PIN, 1);
-            nrf_gpio_pin_write(VB2L_PIN, 0);
-            nrf_gpio_pin_write(VB2H_PIN, 0);
-            nrf_gpio_pin_write(VA2L_PIN, 1);
-            break;
-
-        case ELECTRODES_A3HB3L:
-            nrf_gpio_pin_write(VB3H_PIN, 1);
-            nrf_gpio_pin_write(VA3L_PIN, 0);
-            nrf_gpio_pin_write(VA3H_PIN, 0);
-            nrf_gpio_pin_write(VB3L_PIN, 1);
-            break;
-
-        case ELECTRODES_A3LB3H:
-            nrf_gpio_pin_write(VA3H_PIN, 1);
-            nrf_gpio_pin_write(VB3L_PIN, 0);
-            nrf_gpio_pin_write(VB3H_PIN, 0);
-            nrf_gpio_pin_write(VA3L_PIN, 1);
-            break;
-
-        case ELECTRODES_A4HB4L:
-            nrf_gpio_pin_write(VB4H_PIN, 1);
-            nrf_gpio_pin_write(VA4L_PIN, 0);
-            nrf_gpio_pin_write(VA4H_PIN, 0);
-            nrf_gpio_pin_write(VB4L_PIN, 1);
-            break;
-
-        case ELECTRODES_A4LB4H:
-            nrf_gpio_pin_write(VA4H_PIN, 1);
-            nrf_gpio_pin_write(VB4L_PIN, 0);
-            nrf_gpio_pin_write(VB4H_PIN, 0);
-            nrf_gpio_pin_write(VA4L_PIN, 1);
-            break;
-    }
-}
-
-/*
-    dev_mode_set_cpg10_electrodes
-    (1)0x3000FF90nn
-            -func: dev_mode_set_cpg10_electrodes
-            -nn: electrodes mode     01h-09h
-                01h: ELECTRODES_A1HB1L
-                02h: ELECTRODES_A1HB1L
-                03h: ELECTRODES_A1LB1H
-                04h: ELECTRODES_A2HB2L
-                05h: ELECTRODES_A2LB2H
-                06h: ELECTRODES_A3HB3L
-                07h: ELECTRODES_A3LB3H
-                08h: ELECTRODES_A4HB4L
-                09h: ELECTRODES_A4LB4H
-*/
-void dev_mode_set_cpg10_electrodes(uint8_t *ins)
-{
-    struct __PACKED
-    {
-        uint8_t id     : 4;
-        uint8_t        : 4;
-        uint16_t magic : 16;
-        uint8_t dev_opcode;
-        uint8_t electrodes_opcode;
-        uint8_t param[];
-    } *p_ins = (void *)ins;
-
-    cpg10_electrodes(p_ins->electrodes_opcode);
-}
-
-#endif

cpg10_dev_mode.h

@@ -1,21 +0,0 @@
-#ifndef __CPG10_DEV_MODE_H__
-#define __CPG10_DEV_MODE_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "app_button.h"
-#include "elite_board.h"
-
-#if (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
-    void dev_mode_set_cpg10_electrodes(uint8_t *ins);
-    void dev_mode_gpio_function(uint8_t *ins);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! __CPG10_DEV_MODE_H__ */

cpg10_io.c

@@ -1,146 +0,0 @@
-#include "elite_board.h"
-
-#include "nrf_spim.h"
-
-#include "FreeRTOS.h"
-#include "semphr.h"
-#include "task.h"
-
-#if (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
-
-void spim_xfer(uint32_t cs_pin,
-               nrf_spim_mode_t spi_mode,
-               uint8_t *p_tx_buffer,
-               uint16_t tx_buffer_length,
-               uint8_t *p_rx_buf,
-               uint16_t rx_buffer_length)
-{
-    __disable_irq();
-
-    NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
-
-    switch (spi_mode)
-    {
-        default:
-        case NRF_SPIM_MODE_0:
-            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
-                                (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
-                                (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
-            break;
-
-        case NRF_SPIM_MODE_1:
-            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
-                                (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
-                                (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
-            break;
-
-        case NRF_SPIM_MODE_2:
-            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
-                                (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
-                                (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
-            break;
-
-        case NRF_SPIM_MODE_3:
-            NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
-                                (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
-                                (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
-            break;
-    }
-
-    NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
-
-    NRF_SPIM3->TXD.MAXCNT = tx_buffer_length;
-    NRF_SPIM3->TXD.PTR    = (uint32_t)p_tx_buffer;
-
-    NRF_SPIM3->RXD.MAXCNT = rx_buffer_length;
-    NRF_SPIM3->RXD.PTR    = (uint32_t)p_rx_buf;
-
-    nrf_gpio_pin_clear(cs_pin);
-
-    NRF_SPIM3->EVENTS_END  = 0;
-    NRF_SPIM3->TASKS_START = 1;
-    do {
-    } while (NRF_SPIM3->EVENTS_END == 0);
-
-    nrf_gpio_pin_set(cs_pin);
-
-    __enable_irq();
-}
-
-void cpg10_io_init(void)
-{
-    const uint32_t pel_pins_default_high[] = {
-        VA1H_PIN,
-        VA2H_PIN,
-        VA3H_PIN,
-        VA4H_PIN,
-        VB1H_PIN,
-        VB2H_PIN,
-        VB3H_PIN,
-        VB4H_PIN,
-        LED_R_PIN,
-        LED_G_PIN,
-        LED_B_PIN
-    };
-
-    const uint32_t pel_pins_default_low[] = {
-        ADPT0_S4_PIN,
-        ADPT0_S3_PIN,
-        ADPT0_S2_PIN,
-        ADPT0_S1_PIN,
-        ADPT_LE_PIN,
-        ADPT_CLR_PIN,
-        TW_SCKI_0_PIN,
-        TW_SCKI_1_PIN,
-        HV_EN_PIN,
-        ADPT1_S1_PIN,
-        VA1L_PIN,
-        VA2L_PIN,
-        VA3L_PIN,
-        VA4L_PIN,
-        VB1L_PIN,
-        VB2L_PIN,
-        VB3L_PIN,
-        VB4L_PIN,
-        ADPT1_S4_PIN,
-        ADPT1_S3_PIN,
-        ADPT1_S2_PIN
-    };
-
-    for (int i = 0; i < COUNTOF(pel_pins_default_high); i++)
-    {
-        nrf_gpio_pin_set(pel_pins_default_high[i]);
-        nrf_gpio_cfg_output(pel_pins_default_high[i]);
-    }
-
-    for (int i = 0; i < COUNTOF(pel_pins_default_low); i++)
-    {
-        nrf_gpio_pin_clear(pel_pins_default_low[i]);
-        nrf_gpio_cfg_output(pel_pins_default_low[i]);
-    }
-
-    nrf_gpio_cfg_input(AIN0_PIN, NRF_GPIO_PIN_NOPULL);
-    nrf_gpio_cfg_input(AIN1_PIN, NRF_GPIO_PIN_NOPULL);
-
-    // Config spi module
-    nrf_gpio_pin_set(CS_MEM_PIN);
-    nrf_gpio_cfg_output(CS_MEM_PIN);
-    nrf_gpio_pin_clear(SPIM_MOSI_PIN);
-    nrf_gpio_cfg_output(SPIM_MOSI_PIN);
-    nrf_gpio_pin_clear(SPIM_CLK_PIN);
-    nrf_gpio_cfg_output(SPIM_CLK_PIN);
-    nrf_gpio_cfg_input(SPIM_MISO_PIN, NRF_GPIO_PIN_NOPULL);
-
-    NRF_SPIM3->ENABLE          = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
-    NRF_SPIM3->ORC             = 0x00000000;
-    NRF_SPIM3->FREQUENCY       = SPIM_FREQUENCY_FREQUENCY_M32;
-    NRF_SPIM3->CSNPOL          = SPIM_CSNPOL_CSNPOL_LOW;
-    NRF_SPIM3->IFTIMING.CSNDUR = 8;
-    NRF_SPIM3->PSEL.CSN        = CS_MEM_PIN;
-    NRF_SPIM3->PSEL.SCK        = SPIM_CLK_PIN;
-    NRF_SPIM3->PSEL.MOSI       = SPIM_MOSI_PIN;
-    NRF_SPIM3->PSEL.MISO       = SPIM_MISO_PIN;
-    NRF_SPIM3->ENABLE          = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
-}
-
-#endif

cpg10_io.h

@@ -1,71 +0,0 @@
-#ifndef __CPG10_IO_H__
-#define __CPG10_IO_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "app_config.h"
-#include "elite_board.h"
-#include "nrf_gpio.h"
-#include "nrf_spim.h"
-
-#if (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
-
-#define UNDEF_GPIO    0xFFFFFFFF
-#define ADPT0_S4_PIN  NRF_GPIO_PIN_MAP(0, 22)
-#define ADPT0_S3_PIN  NRF_GPIO_PIN_MAP(0, 25)
-#define ADPT0_S2_PIN  NRF_GPIO_PIN_MAP(0, 19)
-#define ADPT0_S1_PIN  NRF_GPIO_PIN_MAP(0, 21)
-#define ADPT_LE_PIN   NRF_GPIO_PIN_MAP(0, 17)
-#define ADPT_CLR_PIN  NRF_GPIO_PIN_MAP(0, 20)
-#define TW_SCKI_0_PIN NRF_GPIO_PIN_MAP(0, 14)
-#define TW_SCKI_1_PIN NRF_GPIO_PIN_MAP(0, 13)
-#define HV_EN_PIN     NRF_GPIO_PIN_MAP(0, 11)
-#define SPIM_CLK_PIN  NRF_GPIO_PIN_MAP(0, 12)
-#define SPIM_MOSI_PIN NRF_GPIO_PIN_MAP(0, 7)
-#define SPIM_MISO_PIN NRF_GPIO_PIN_MAP(1, 9)
-#define ADPT1_S1_PIN  NRF_GPIO_PIN_MAP(0, 6)
-#define CS_MEM_PIN    NRF_GPIO_PIN_MAP(0, 27)
-#define VA1H_PIN      NRF_GPIO_PIN_MAP(0, 26)
-#define VA1L_PIN      NRF_GPIO_PIN_MAP(0, 4)
-#define VA2H_PIN      NRF_GPIO_PIN_MAP(0, 1)
-#define VA2L_PIN      NRF_GPIO_PIN_MAP(0, 29)
-#define VA3H_PIN      NRF_GPIO_PIN_MAP(0, 0)
-#define VA3L_PIN      NRF_GPIO_PIN_MAP(0, 31)
-#define VA4H_PIN      NRF_GPIO_PIN_MAP(1, 15)
-#define VA4L_PIN      NRF_GPIO_PIN_MAP(0, 2)
-#define AIN0_PIN      NRF_GPIO_PIN_MAP(0, 30)
-#define AIN1_PIN      NRF_GPIO_PIN_MAP(0, 28)
-#define VB1H_PIN      NRF_GPIO_PIN_MAP(1, 12)
-#define VB1L_PIN      NRF_GPIO_PIN_MAP(1, 14)
-#define VB2H_PIN      NRF_GPIO_PIN_MAP(0, 3)
-#define VB2L_PIN      NRF_GPIO_PIN_MAP(1, 13)
-#define VB3H_PIN      NRF_GPIO_PIN_MAP(1, 3)
-#define VB3L_PIN      NRF_GPIO_PIN_MAP(1, 10)
-#define VB4H_PIN      NRF_GPIO_PIN_MAP(1, 6)
-#define VB4L_PIN      NRF_GPIO_PIN_MAP(1, 11)
-#define LED_R_PIN     NRF_GPIO_PIN_MAP(0, 10)
-#define LED_G_PIN     NRF_GPIO_PIN_MAP(0, 9)
-#define LED_B_PIN     NRF_GPIO_PIN_MAP(1, 2)
-#define ADPT1_S4_PIN  NRF_GPIO_PIN_MAP(0, 24)
-#define ADPT1_S3_PIN  NRF_GPIO_PIN_MAP(0, 23)
-#define ADPT1_S2_PIN  NRF_GPIO_PIN_MAP(0, 16)
-
-    void spim_xfer(uint32_t cs_pin,
-                   nrf_spim_mode_t spi_mode,
-                   uint8_t *p_tx_buffer,
-                   uint16_t tx_buffer_length,
-                   uint8_t *p_rx_buf,
-                   uint16_t rx_buffer_length);
-
-    void cpg10_io_init(void);
-
-#endif /* ! DEF_ELITE_MODEL */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! __CPG10_IO_H__ */

cpg11_dev_mode.h

@@ -0,0 +1,24 @@
+#ifndef __CPG11_DEV_MODE_H__
+#define __CPG11_DEV_MODE_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_button.h"
+#include "elite_board.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+    void dev_mode_electrode_switch(uint8_t *ins);
+    void dev_mode_tw1508(uint8_t *ins);
+    void dev_mode_ctrl_cpg11_electrodes_task(uint8_t *ins);
+    void dev_mode_adapter_block_switch(uint8_t *ins);
+    void dev_mode_gpio(uint8_t *ins);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __CPG11_DEV_MODE_H__ */

cpg11_io.c

@@ -0,0 +1,489 @@
+#include "elite_board.h"
+
+#include "nrf_gpio.h"
+#include "nrf_gpiote.h"
+#include "nrf_log.h"
+#include "nrf_spim.h"
+#include "nrf_timer.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+#pragma GCC optimize("O2")
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+
+typedef struct
+{
+    const uint32_t gpiote_idx[4];
+    NRF_TIMER_Type *TMR_A;
+    NRF_TIMER_Type *TMR_B;
+    uint32_t IRQn;
+    pulse_gen_t *p_pulse_gen;
+    struct
+    {
+        pulse_gen_t *p_pulse_gen;
+        uint32_t len;
+        uint32_t select;
+    } private;
+} pulse_gen_hw_t;
+
+pulse_gen_hw_t pulse_gen_hw[] = {
+    {.gpiote_idx  = { 0, 1, 2, 3 },
+     .TMR_A       = NRF_TIMER1,
+     .TMR_B       = NRF_TIMER3,
+     .IRQn        = TIMER3_IRQn,
+     .p_pulse_gen = NULL,
+     .private     = { NULL, 0, 0 }},
+    {.gpiote_idx  = { 4, 5, 6, 7 },
+     .TMR_A       = NRF_TIMER2,
+     .TMR_B       = NRF_TIMER4,
+     .IRQn        = TIMER4_IRQn,
+     .p_pulse_gen = NULL,
+     .private     = { NULL, 0, 0 }},
+};
+
+__STATIC_INLINE void cpg11_tmr_cb(uint32_t hw_idx)
+{
+    if (pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[4])
+    {
+        pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[4] = 0;
+
+        uint32_t sel = pulse_gen_hw[hw_idx].private.select;
+
+        if (pulse_gen_hw[hw_idx].private.p_pulse_gen[sel].pulse_cnt > 0)
+        {
+            pulse_gen_hw[hw_idx].private.p_pulse_gen[sel].pulse_cnt--;
+        }
+
+        for (uint32_t i = 0; i < pulse_gen_hw[hw_idx].private.len; i++)
+        {
+            sel = (sel + 1) % pulse_gen_hw[hw_idx].private.len;
+            if (pulse_gen_hw[hw_idx].private.p_pulse_gen[sel].pulse_cnt > 0)
+            {
+                pulse_gen_hw[hw_idx].private.select = sel;
+                cpg11_pulse_start(hw_idx, &pulse_gen_hw[hw_idx].private.p_pulse_gen[sel]);
+                return;
+            }
+        }
+    }
+}
+
+void TIMER3_IRQHandler(void)
+{
+    cpg11_tmr_cb(0);
+}
+
+void TIMER4_IRQHandler(void)
+{
+    cpg11_tmr_cb(1);
+}
+
+void cpg11_pulse_suspend_by_pulse_id(uint32_t pulse_id)
+{
+    for (uint32_t i = 0; i < COUNTOF(pulse_gen_hw); i++)
+    {
+        for (uint32_t j = 0; j < pulse_gen_hw[i].private.len; j++)
+        {
+            if (pulse_gen_hw[i].private.p_pulse_gen[j].pulse_id == pulse_id)
+            {
+                taskENTER_CRITICAL();
+                pulse_gen_hw[i].private.p_pulse_gen[j].VAxH = 0xFFFFFFFF;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VBxH = 0xFFFFFFFF;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VAxL = 0xFFFFFFFF;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VBxL = 0xFFFFFFFF;
+                taskEXIT_CRITICAL();
+            }
+        }
+    }
+}
+
+void cpg11_pulse_resume_by_pulse_id(uint32_t pulse_id)
+{
+    for (uint32_t i = 0; i < COUNTOF(pulse_gen_hw); i++)
+    {
+        for (uint32_t j = 0; j < pulse_gen_hw[i].private.len; j++)
+        {
+            if (pulse_gen_hw[i].private.p_pulse_gen[j].pulse_id == pulse_id)
+            {
+                taskENTER_CRITICAL();
+                pulse_gen_hw[i].private.p_pulse_gen[j].VAxH = pulse_gen_hw[i].p_pulse_gen[j].VAxH;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VBxH = pulse_gen_hw[i].p_pulse_gen[j].VBxH;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VAxL = pulse_gen_hw[i].p_pulse_gen[j].VAxL;
+                pulse_gen_hw[i].private.p_pulse_gen[j].VBxL = pulse_gen_hw[i].p_pulse_gen[j].VBxL;
+                taskEXIT_CRITICAL();
+            }
+        }
+    }
+}
+
+void cpg11_pulse_stop(uint32_t hw_idx)
+{
+    pulse_gen_hw[hw_idx].TMR_B->TASKS_STOP = 1;
+    pulse_gen_hw[hw_idx].TMR_A->TASKS_STOP = 1;
+
+    sd_nvic_DisableIRQ(pulse_gen_hw[hw_idx].IRQn);
+    sd_nvic_ClearPendingIRQ(pulse_gen_hw[hw_idx].IRQn);
+
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+}
+
+void cpg11_pulse_start(uint32_t hw_idx, pulse_gen_t *p_pulse_gen)
+{
+    pulse_gen_hw[hw_idx].TMR_B->TASKS_STOP = 1;
+    pulse_gen_hw[hw_idx].TMR_A->TASKS_STOP = 1;
+
+    sd_nvic_DisableIRQ(pulse_gen_hw[hw_idx].IRQn);
+    sd_nvic_ClearPendingIRQ(pulse_gen_hw[hw_idx].IRQn);
+
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+    nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[0], p_pulse_gen->VAxH, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[1], p_pulse_gen->VBxL, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[2], p_pulse_gen->VBxH, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+    nrf_gpiote_task_configure(pulse_gen_hw[hw_idx].gpiote_idx[3], p_pulse_gen->VAxL, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+    nrf_gpiote_task_enable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+
+    uint32_t offs = 8 * hw_idx;
+
+    NRF_PPI->CH[offs + 0].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[0];
+    NRF_PPI->CH[offs + 0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[0]];
+    NRF_PPI->CHENSET          = (1 << (offs + 0));
+
+    NRF_PPI->CH[offs + 1].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[1];
+    NRF_PPI->CH[offs + 1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[1]];
+    NRF_PPI->CHENSET          = (1 << (offs + 1));
+
+    NRF_PPI->CH[offs + 2].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[2];
+    NRF_PPI->CH[offs + 2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[1]];
+    NRF_PPI->CHENSET          = (1 << (offs + 2));
+
+    NRF_PPI->CH[offs + 3].EEP   = (uint32_t)&pulse_gen_hw[hw_idx].TMR_A->EVENTS_COMPARE[3];
+    NRF_PPI->CH[offs + 3].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[0]];
+    NRF_PPI->FORK[offs + 3].TEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->TASKS_START;
+    NRF_PPI->CHENSET            = (1 << (offs + 3));
+
+    NRF_PPI->CH[offs + 4].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[0];
+    NRF_PPI->CH[offs + 4].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[2]];
+    NRF_PPI->CHENSET          = (1 << (offs + 4));
+
+    NRF_PPI->CH[offs + 5].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[1];
+    NRF_PPI->CH[offs + 5].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[3]];
+    NRF_PPI->CHENSET          = (1 << (offs + 5));
+
+    NRF_PPI->CH[offs + 6].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[2];
+    NRF_PPI->CH[offs + 6].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[3]];
+    NRF_PPI->CHENSET          = (1 << (offs + 6));
+
+    NRF_PPI->CH[offs + 7].EEP = (uint32_t)&pulse_gen_hw[hw_idx].TMR_B->EVENTS_COMPARE[3];
+    NRF_PPI->CH[offs + 7].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw[hw_idx].gpiote_idx[2]];
+    NRF_PPI->CHENSET          = (1 << (offs + 7));
+
+    pulse_gen_hw[hw_idx].TMR_B->TASKS_CLEAR = 1;
+    pulse_gen_hw[hw_idx].TMR_A->TASKS_CLEAR = 1;
+
+    pulse_gen_hw[hw_idx].TMR_B->CC[0]    = 1 + p_pulse_gen->point_us[3] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[1]    = pulse_gen_hw[hw_idx].TMR_B->CC[0] + p_pulse_gen->point_us[4] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[2]    = pulse_gen_hw[hw_idx].TMR_B->CC[1] + p_pulse_gen->point_us[5] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[3]    = pulse_gen_hw[hw_idx].TMR_B->CC[2] + p_pulse_gen->point_us[6] * 16;
+    pulse_gen_hw[hw_idx].TMR_B->CC[4]    = pulse_gen_hw[hw_idx].TMR_B->CC[3] + p_pulse_gen->idle_us * 16;
+    pulse_gen_hw[hw_idx].TMR_B->SHORTS   = NRF_TIMER_SHORT_COMPARE4_STOP_MASK | NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK;
+    pulse_gen_hw[hw_idx].TMR_B->INTENSET = NRF_TIMER_INT_COMPARE4_MASK;
+
+    pulse_gen_hw[hw_idx].TMR_A->CC[0]  = 1;
+    pulse_gen_hw[hw_idx].TMR_A->CC[1]  = pulse_gen_hw[hw_idx].TMR_A->CC[0] + p_pulse_gen->point_us[0] * 16;
+    pulse_gen_hw[hw_idx].TMR_A->CC[2]  = pulse_gen_hw[hw_idx].TMR_A->CC[1] + p_pulse_gen->point_us[1] * 16;
+    pulse_gen_hw[hw_idx].TMR_A->CC[3]  = pulse_gen_hw[hw_idx].TMR_A->CC[2] + p_pulse_gen->point_us[2] * 16;
+    pulse_gen_hw[hw_idx].TMR_A->SHORTS = NRF_TIMER_SHORT_COMPARE3_STOP_MASK | NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK;
+
+    sd_nvic_EnableIRQ(pulse_gen_hw[hw_idx].IRQn);
+
+    pulse_gen_hw[hw_idx].TMR_A->TASKS_START = 1;
+}
+
+void cpg11_pulse_init(uint32_t hw_idx, pulse_gen_t *p_pulse_gen, uint32_t len)
+{
+    taskENTER_CRITICAL();
+
+    if (pulse_gen_hw[hw_idx].private.p_pulse_gen != NULL)
+    {
+        pulse_gen_hw[hw_idx].TMR_B->TASKS_STOP = 1;
+        pulse_gen_hw[hw_idx].TMR_A->TASKS_STOP = 1;
+
+        sd_nvic_DisableIRQ(pulse_gen_hw[hw_idx].IRQn);
+        sd_nvic_ClearPendingIRQ(pulse_gen_hw[hw_idx].IRQn);
+
+        nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[0]);
+        nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[1]);
+        nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[2]);
+        nrf_gpiote_task_disable(pulse_gen_hw[hw_idx].gpiote_idx[3]);
+
+        vPortFree(pulse_gen_hw[hw_idx].private.p_pulse_gen);
+    }
+
+    pulse_gen_hw[hw_idx].p_pulse_gen    = p_pulse_gen;
+    pulse_gen_hw[hw_idx].private.len    = len;
+    pulse_gen_hw[hw_idx].private.select = 0;
+
+    pulse_gen_hw[hw_idx].private.p_pulse_gen = pvPortMalloc(sizeof(pulse_gen_t) * len);
+    memcpy(pulse_gen_hw[hw_idx].private.p_pulse_gen, pulse_gen_hw[hw_idx].p_pulse_gen, sizeof(*p_pulse_gen) * len);
+
+    taskEXIT_CRITICAL();
+};
+
+void cpg_pulse_default_demo_ext(void)
+{
+    bool e1 = 1;
+    bool e2 = 1;
+    bool e3 = 1;
+    bool e4 = 1;
+    pulse_gen_t p_pulse_genA[2];
+    pulse_gen_t p_pulse_genB[2];
+
+    p_pulse_genA[0] = (pulse_gen_t) {
+        .VBxH        = VB1H_PIN,
+        .VBxL        = VB1L_PIN,
+        .VAxH        = VA1H_PIN,
+        .VAxL        = VA1L_PIN,
+        .point_us[0] = 1,
+        .point_us[1] = 50,
+        .point_us[2] = 1,
+        .point_us[3] = 0,
+        .point_us[4] = 1,
+        .point_us[5] = 50,
+        .point_us[6] = 1,
+        .idle_us     = 1000,
+        .pulse_cnt   = UINT32_MAX,
+        .pulse_id    = PULSE_ID_A,
+    };
+
+    p_pulse_genA[1] = (pulse_gen_t) {
+        .VBxH        = VB2H_PIN,
+        .VBxL        = VB2L_PIN,
+        .VAxH        = VA2H_PIN,
+        .VAxL        = VA2L_PIN,
+        .point_us[0] = 1,
+        .point_us[1] = 50,
+        .point_us[2] = 1,
+        .point_us[3] = 0,
+        .point_us[4] = 1,
+        .point_us[5] = 50,
+        .point_us[6] = 1,
+        .idle_us     = 1000,
+        .pulse_cnt   = UINT32_MAX,
+        .pulse_id    = PULSE_ID_B,
+    };
+
+    p_pulse_genB[0] = (pulse_gen_t) {
+        .VBxH        = VB3H_PIN,
+        .VBxL        = VB3L_PIN,
+        .VAxH        = VA3H_PIN,
+        .VAxL        = VA3L_PIN,
+        .point_us[0] = 1,
+        .point_us[1] = 50,
+        .point_us[2] = 1,
+        .point_us[3] = 0,
+        .point_us[4] = 1,
+        .point_us[5] = 50,
+        .point_us[6] = 1,
+        .idle_us     = 1000,
+        .pulse_cnt   = UINT32_MAX,
+        .pulse_id    = PULSE_ID_C,
+    };
+
+    p_pulse_genB[1] = (pulse_gen_t) {
+        .VBxH        = VB4H_PIN,
+        .VBxL        = VB4L_PIN,
+        .VAxH        = VA4H_PIN,
+        .VAxL        = VA4L_PIN,
+        .point_us[0] = 1,
+        .point_us[1] = 50,
+        .point_us[2] = 1,
+        .point_us[3] = 0,
+        .point_us[4] = 1,
+        .point_us[5] = 50,
+        .point_us[6] = 1,
+        .idle_us     = 1000,
+        .pulse_cnt   = UINT32_MAX,
+        .pulse_id    = PULSE_ID_B,
+    };
+
+    if(e1)
+    {
+        nrf_gpio_pin_clear(p_pulse_genA[0].VBxL);
+        nrf_gpio_pin_clear(p_pulse_genA[0].VBxH);
+        nrf_gpio_pin_clear(p_pulse_genA[0].VAxL);
+        nrf_gpio_pin_clear(p_pulse_genA[0].VAxH);
+    }
+
+    if(e2)
+    {
+        nrf_gpio_pin_clear(p_pulse_genA[1].VBxL);
+        nrf_gpio_pin_clear(p_pulse_genA[1].VBxH);
+        nrf_gpio_pin_clear(p_pulse_genA[1].VAxL);
+        nrf_gpio_pin_clear(p_pulse_genA[1].VAxH);
+    }
+
+    if(e3)
+    {
+        nrf_gpio_pin_clear(p_pulse_genB[0].VBxL);
+        nrf_gpio_pin_clear(p_pulse_genB[0].VBxH);
+        nrf_gpio_pin_clear(p_pulse_genB[0].VAxL);
+        nrf_gpio_pin_clear(p_pulse_genB[0].VAxH);
+    }
+
+    if(e4)
+    {
+        nrf_gpio_pin_clear(p_pulse_genB[1].VBxL);
+        nrf_gpio_pin_clear(p_pulse_genB[1].VBxH);
+        nrf_gpio_pin_clear(p_pulse_genB[1].VAxL);
+        nrf_gpio_pin_clear(p_pulse_genB[1].VAxH);
+    }
+
+
+    if (e1 && e2)
+    {
+        cpg11_pulse_init(0, p_pulse_genA, 2);
+        cpg11_pulse_start(0, p_pulse_genA);
+    }
+    else if (e1 && e2==0)
+    {
+        cpg11_pulse_init(0, p_pulse_genA, 1);
+        cpg11_pulse_start(0, p_pulse_genA);
+    }
+    else if (e2 && e1==0)
+    {
+        cpg11_pulse_init(0, &p_pulse_genA[1], 1);
+        cpg11_pulse_start(0, &p_pulse_genA[1]);
+    }
+
+    if (e3 && e4)
+    {
+        cpg11_pulse_init(1, p_pulse_genB, 2);
+        cpg11_pulse_start(1, p_pulse_genB);
+    }
+    else if (e3 && e4==0)
+    {
+        cpg11_pulse_init(1, p_pulse_genB, 1);
+        cpg11_pulse_start(1, p_pulse_genB);
+    }
+    else if (e4 && e3==0)
+    {
+        cpg11_pulse_init(1, &p_pulse_genB[1], 1);
+        cpg11_pulse_start(1, &p_pulse_genB[1]);
+    }
+
+}
+
+void cpg11_io_init(void)
+{
+    const uint32_t pel_pins_default_high[] = {
+        LED_R_PIN,
+        LED_G_PIN,
+        CS_MEM_PIN,
+        ADPT_CLR_PIN
+    };
+
+    const uint32_t pel_pins_default_low[] = {
+        LED_B_PIN,
+        TW_SCKI_0_PIN,
+        TW_SCKI_1_PIN,
+        ADPT_CLK_PIN,
+        HV_EN_PIN,
+        SPIM_CLK_PIN,
+        SPIM_MOSI_PIN,
+        SPIM_MISO_PIN,
+        ADPT_LE_PIN,
+        ADPT0_S4_PIN,
+        ADPT0_S3_PIN,
+        ADPT0_S2_PIN,
+        ADPT0_S1_PIN,
+        ADPT1_S4_PIN,
+        ADPT1_S3_PIN,
+        ADPT1_S2_PIN,
+        ADPT1_S1_PIN,
+
+        VB1L_PIN,
+        VB1H_PIN,
+        VA1L_PIN,
+        VA1H_PIN,
+
+        VB2L_PIN,
+        VB2H_PIN,
+        VA2L_PIN,
+        VA2H_PIN,
+
+        VB3L_PIN,
+        VB3H_PIN,
+        VA3L_PIN,
+        VA3H_PIN,
+
+        VB4L_PIN,
+        VB4H_PIN,
+        VA4L_PIN,
+        VA4H_PIN,
+    };
+
+    for (int i = 0; i < COUNTOF(pel_pins_default_high); i++)
+    {
+        nrf_gpio_cfg_output(pel_pins_default_high[i]);
+        nrf_gpio_pin_set(pel_pins_default_high[i]);
+    }
+
+    for (int i = 0; i < COUNTOF(pel_pins_default_low); i++)
+    {
+        nrf_gpio_cfg_output(pel_pins_default_low[i]);
+        nrf_gpio_pin_clear(pel_pins_default_low[i]);
+    }
+
+    nrf_gpio_cfg_input(AIN0_PIN, NRF_GPIO_PIN_NOPULL);
+    nrf_gpio_cfg_input(AIN1_PIN, NRF_GPIO_PIN_NOPULL);
+
+    for (uint32_t i = 0; i < COUNTOF(pulse_gen_hw); i++)
+    {
+        pulse_gen_hw[i].TMR_B->PRESCALER = NRF_TIMER_FREQ_16MHz;
+        pulse_gen_hw[i].TMR_B->MODE      = NRF_TIMER_MODE_TIMER;
+        pulse_gen_hw[i].TMR_B->BITMODE   = NRF_TIMER_BIT_WIDTH_32;
+
+        pulse_gen_hw[i].TMR_A->PRESCALER = NRF_TIMER_FREQ_16MHz;
+        pulse_gen_hw[i].TMR_A->MODE      = NRF_TIMER_MODE_TIMER;
+        pulse_gen_hw[i].TMR_A->BITMODE   = NRF_TIMER_BIT_WIDTH_32;
+
+        sd_nvic_SetPriority(pulse_gen_hw[i].IRQn, _PRIO_APP_HIGH);
+    }
+
+    for (int i = 0; i < 2; i++)
+    {
+        pulse_gen_hw[i].p_pulse_gen[0].VAxH         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[0].VBxH         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[0].VAxL         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[0].VBxL         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[1].VAxH         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[1].VBxH         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[1].VAxL         = 0xFFFFFFFF;
+        pulse_gen_hw[i].p_pulse_gen[1].VBxL         = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[0].VAxH = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[0].VBxH = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[0].VAxL = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[0].VBxL = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[1].VAxH = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[1].VBxH = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[1].VAxL = 0xFFFFFFFF;
+        pulse_gen_hw[i].private.p_pulse_gen[1].VBxL = 0xFFFFFFFF;
+    }
+
+    cpg_pulse_default_demo_ext();
+}
+
+#endif

cpg11_io.h

@@ -0,0 +1,97 @@
+#ifndef __CPG10_IO_H__
+#define __CPG10_IO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite_board.h"
+#include "nrf_gpio.h"
+#include "nrf_spim.h"
+
+#if (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+
+#define UNDEF_GPIO    0xFFFFFFFF
+#define VA1H_PIN      NRF_GPIO_PIN_MAP(0, 22)
+#define VA1L_PIN      NRF_GPIO_PIN_MAP(0, 25)
+#define VB1H_PIN      NRF_GPIO_PIN_MAP(0, 19)
+#define VB1L_PIN      NRF_GPIO_PIN_MAP(0, 21)
+#define VA2H_PIN      NRF_GPIO_PIN_MAP(0, 17)
+#define VA2L_PIN      NRF_GPIO_PIN_MAP(0, 20)
+#define TW_SCKI_0_PIN NRF_GPIO_PIN_MAP(0, 14)
+#define TW_SCKI_1_PIN NRF_GPIO_PIN_MAP(0, 13)
+#define ADPT_CLK_PIN  NRF_GPIO_PIN_MAP(0, 11)
+#define HV_EN_PIN     NRF_GPIO_PIN_MAP(1, 8)
+#define SPIM_CLK_PIN  NRF_GPIO_PIN_MAP(0, 12)
+#define SPIM_MISO_PIN NRF_GPIO_PIN_MAP(1, 9)
+#define VB2H_PIN      NRF_GPIO_PIN_MAP(0, 8)
+#define VB2L_PIN      NRF_GPIO_PIN_MAP(0, 6)
+#define VA3H_PIN      NRF_GPIO_PIN_MAP(0, 5)
+#define VA3L_PIN      NRF_GPIO_PIN_MAP(0, 27)
+#define VB3H_PIN      NRF_GPIO_PIN_MAP(0, 26)
+#define VB3L_PIN      NRF_GPIO_PIN_MAP(0, 4)
+#define VA4H_PIN      NRF_GPIO_PIN_MAP(0, 1)
+#define VA4L_PIN      NRF_GPIO_PIN_MAP(0, 0)
+#define ADPT_LE_PIN   NRF_GPIO_PIN_MAP(0, 31)
+#define ADPT_CLR_PIN  NRF_GPIO_PIN_MAP(1, 15)
+#define CS_MEM_PIN    NRF_GPIO_PIN_MAP(0, 2)
+#define AIN0_PIN      NRF_GPIO_PIN_MAP(0, 30)
+#define AIN1_PIN      NRF_GPIO_PIN_MAP(0, 28)
+#define ADPT0_S4_PIN  NRF_GPIO_PIN_MAP(1, 12)
+#define ADPT0_S3_PIN  NRF_GPIO_PIN_MAP(1, 14)
+#define ADPT0_S2_PIN  NRF_GPIO_PIN_MAP(0, 3)
+#define ADPT0_S1_PIN  NRF_GPIO_PIN_MAP(1, 13)
+#define ADPT1_S4_PIN  NRF_GPIO_PIN_MAP(1, 3)
+#define ADPT1_S3_PIN  NRF_GPIO_PIN_MAP(1, 10)
+#define ADPT1_S2_PIN  NRF_GPIO_PIN_MAP(1, 6)
+#define ADPT1_S1_PIN  NRF_GPIO_PIN_MAP(1, 11)
+#define LED_R_PIN     NRF_GPIO_PIN_MAP(0, 10)
+#define LED_G_PIN     NRF_GPIO_PIN_MAP(0, 9)
+#define LED_B_PIN     NRF_GPIO_PIN_MAP(1, 2)
+#define VB4H_PIN      NRF_GPIO_PIN_MAP(0, 24)
+#define VB4L_PIN      NRF_GPIO_PIN_MAP(0, 23)
+#define SPIM_MOSI_PIN NRF_GPIO_PIN_MAP(0, 7)
+#define TW_SDI_PIN    NRF_GPIO_PIN_MAP(0, 7)
+#define ADPT_DIN_PIN  NRF_GPIO_PIN_MAP(0, 7)
+
+#define PULSE_ID_NULL 0
+#define PULSE_ID_A    1
+#define PULSE_ID_B    2
+#define PULSE_ID_C    3
+#define PULSE_ID_D    4
+
+    typedef struct
+    {
+        uint32_t VAxH;
+        uint32_t VAxL;
+        uint32_t VBxH;
+        uint32_t VBxL;
+        uint32_t idle_us;     // min: 500us, max: 60sec
+        uint32_t point_us[7]; // toggle point timestamp
+        uint32_t pulse_cnt;   // min: 1, max: 0xFFFFFFFF
+        uint32_t pulse_id;    // NO_USE_IRQ / USE_TIMER1_IRQ / USE_TIMER2_IRQ
+    } pulse_gen_t;
+
+    void spim_xfer(uint32_t cs_pin,
+                   nrf_spim_mode_t spi_mode,
+                   uint8_t *p_tx_buffer,
+                   uint16_t tx_buffer_length,
+                   uint8_t *p_rx_buf,
+                   uint16_t rx_buffer_length);
+
+    void cpg11_io_init(void);
+    void cpg11_pulse_init(uint32_t hw_idx, pulse_gen_t *p_pulse_gen, uint32_t len);
+    void cpg11_pulse_start(uint32_t idx, pulse_gen_t *p_pulse_gen);
+    void cpg11_pulse_stop(uint32_t hw_idx);
+    void cpg11_pulse_suspend_by_pulse_id(uint32_t pulse_id);
+    void cpg11_pulse_resume_by_pulse_id(uint32_t pulse_id);
+
+#endif /* ! DEF_ELITE_MODEL */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __CPG10_IO_H__ */

edc20.c

@@ -14,7 +14,7 @@
 
 #include "nrf_log.h"
 
-#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
 
 extern ret_code_t le_event_upadate(uint8_t *p_value, uint16_t len);
 

edc20_cycle_iv_mode.c

@@ -16,7 +16,7 @@
 #include <stdlib.h>
 #include <string.h>
 
-#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
 
 #define OUT_0 DAC0
 #define OUT_1 DAC1

edc20_io.c

@@ -14,7 +14,7 @@
 #include "dac_drv.h"
 #include "sw_drv.h"
 
-#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
 
 //==========================================================
 // gpio

elite.c

@@ -2,11 +2,11 @@
 
 #if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
 #include "elite_dev.h"
-#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
 #include "edc.h"
-#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
 #include "pel.h"
-#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
 #include "cpg.h"
 #else
 #error "Unknown DEF_ELITE_MODEL"
@@ -102,12 +102,12 @@ void elite_init(void)
 {
 #if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
     p_instance = dev_init();
-#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
     edc.init();
     p_instance = edc.p_elite_instance;
-#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
     p_instance = pel_init();
-#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
     p_instance = cpg_init();
 #else
 #error "Unknown DEF_ELITE_MODEL"

elite_board.c

@@ -2,21 +2,21 @@
 
 void elite_board_init(void)
 {
-#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
     edc20_io_init();
-#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
-    pel10_io_init();
-#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
-    cpg10_io_init();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+    pel20_io_init();
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+    cpg11_io_init();
 #endif
 }
 
 void elite_board_power_off(void)
 {
-#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
+#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
     edc20_io_power_off();
-#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
-#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
 #endif
 }
 

elite_board.h

@@ -15,12 +15,12 @@ extern "C"
 #include "sw_drv.h"
 
 #if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
-#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
+#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
 #include "edc20_io.h"
-#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
-#include "pel10_io.h"
-#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
-#include "cpg10_io.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
+#include "pel20_io.h"
+#elif (DEF_ELITE_MODEL == DEF_ELITE_CPG_V1_1)
+#include "cpg11_io.h"
 #else
 #error "Not implemented xxx_io.h"
 #endif

main.c

@@ -123,6 +123,7 @@ int main(void)
     NRF_LOG_INIT(NULL, 0);
     NRF_LOG_DEFAULT_BACKENDS_INIT();
     NRF_LOG_INFO("%s Build: %s %s", ELITE_DEVICE_NAME, __TIME__, __DATE__);
+    NRF_LOG_INFO("Elite hw ver(%d.%d.%d.%d)", MAJOR_PRODUCT_NUMBER, MINOR_PRODUCT_NUMBER, MAJOR_VERSION_NUMBER, MINOR_VERSION_NUMBER);
 
     nrf_sdh_freertos_init(nrf_sdh_freertos_task_hook, NULL); // create event: softdevice_task - wireless protocal stack
 

max14802.c

@@ -0,0 +1,187 @@
+#include "max14802.h"
+#include "elite_board.h"
+
+#include "nrf_delay.h"
+#include "nrf_gpio.h"
+
+#include "string.h"
+
+#pragma GCC optimize("O2")
+
+#if (DEF_MAX14802_ENABLED)
+
+static sw_t m_sw = { .val = UINT64_MAX };
+
+#define EXCLUDE_IO_ENABLE  1
+#define EXCLUDE_IO_DISABLE 0
+
+static const uint32_t exclude_io[64] = {
+    ADPT0_S1_PIN,
+    ADPT0_S2_PIN,
+    ADPT0_S3_PIN,
+    ADPT0_S4_PIN,
+    ADPT1_S1_PIN,
+    ADPT1_S2_PIN,
+    ADPT1_S3_PIN,
+    ADPT1_S4_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+    UNCONNECTED_PIN,
+};
+
+static void shift_out(uint8_t *p, uint32_t len)
+{
+    nrf_gpio_pin_clear(ADPT_LE_PIN);
+
+    for (int32_t j = len; j > 0; j--)
+    {
+        uint32_t val = p[j - 1];
+        for (uint32_t i = 0x01 << (SW_PER_BYTE - 1); i > 0; i >>= 1)
+        {
+            nrf_gpio_pin_clear(ADPT_CLK_PIN);
+            nrf_gpio_pin_write(ADPT_DIN_PIN, val & i);
+            nrf_gpio_pin_set(ADPT_CLK_PIN);
+            nrf_gpio_pin_write(ADPT_DIN_PIN, val & i);
+        }
+    }
+
+    nrf_gpio_pin_clear(ADPT_CLK_PIN);
+    nrf_gpio_pin_clear(ADPT_DIN_PIN);
+    nrf_gpio_pin_set(ADPT_LE_PIN);
+    nrf_gpio_pin_clear(ADPT_LE_PIN);
+}
+
+int max14802_reset(void)
+{
+    m_sw.val = 0;
+    shift_out((uint8_t *)&m_sw.val, SW_TOTAL_COUNT / SW_PER_BYTE);
+    return 0;
+}
+
+int max14802_write(sw_t sw_mask)
+{
+    if (m_sw.val != sw_mask.val)
+    {
+        m_sw = sw_mask;
+
+        // Disable A1_AOUT,A2_AOUT,B1_AOUT, .... B3_AOUT, B4_AOUT
+
+        for (uint32_t i = 0; i < SW_TOTAL_COUNT; i++)
+        {
+            nrf_gpio_pin_write(exclude_io[i], EXCLUDE_IO_DISABLE);
+        }
+
+        // Set max14082
+        shift_out((uint8_t *)&m_sw.val, SW_TOTAL_COUNT / SW_PER_BYTE);
+
+        // Enable A1_AOUT,A2_AOUT,B1_AOUT, .... B3_AOUT, B4_AOUT are all disable when all max14082 off
+
+        if (m_sw.val == 0)
+        {
+            for (uint32_t i = 0; i < SW_TOTAL_COUNT; i++)
+            {
+                nrf_gpio_pin_write(exclude_io[i], EXCLUDE_IO_ENABLE);
+            }
+        }
+    }
+
+    return 0;
+}
+
+int max14802_read(sw_t *p_sw_mask)
+{
+    *p_sw_mask = m_sw;
+    return 0;
+}
+int max14802_get_sw_count(uint32_t *p_sw_count)
+{
+    *p_sw_count = SW_TOTAL_COUNT;
+    return 0;
+}
+
+int max14802_init(void)
+{
+    nrf_gpio_pin_set(ADPT_CLR_PIN);
+    nrf_gpio_pin_clear(ADPT_LE_PIN);
+    nrf_gpio_pin_clear(ADPT_CLK_PIN);
+    nrf_gpio_pin_clear(ADPT_DIN_PIN);
+
+    nrf_gpio_cfg_output(ADPT_CLR_PIN);
+    nrf_gpio_cfg_output(ADPT_LE_PIN);
+    nrf_gpio_cfg_output(ADPT_CLK_PIN);
+    nrf_gpio_cfg_output(ADPT_DIN_PIN);
+
+    for (uint32_t i = 0; i < COUNTOF(exclude_io); i++)
+    {
+        nrf_gpio_pin_write(exclude_io[i], EXCLUDE_IO_DISABLE);
+    }
+
+    max14802_write((sw_t) { .val = 0 });
+
+    nrf_gpio_pin_clear(ADPT_CLR_PIN);
+
+    return 0;
+}
+
+const sw_drv_if_t max14802 = {
+    .init         = max14802_init,
+    .reset        = max14802_reset,
+    .write        = max14802_write,
+    .read         = max14802_read,
+    .get_sw_count = max14802_get_sw_count,
+};
+
+#endif

max14802.h

@@ -0,0 +1,31 @@
+#ifndef __MAX14802_H__
+#define __MAX14802_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "sw_drv_if.h"
+
+#if (DEF_MAX14802_ENABLED)
+
+#define MAX14802_COUNT  1
+#define SW_PER_MAX14802 16
+#define SW_TOTAL_COUNT  (SW_PER_MAX14802 * MAX14802_COUNT)
+#define SW_PER_BYTE     8
+
+#if (SW_TOTAL_COUNT > 64)
+#error "unsupport"
+#endif /* ! SW_TOTAL_COUNT */
+
+extern const sw_drv_if_t max14802;
+
+#endif /* ! DEF_MAX14802_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !__MAX14802_H__

nrf5x.xml

@@ -2,9 +2,9 @@
 <EmbeddedProfile xmlns:xsd="http://www.w3.org/2001/XMLSchema" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
   <ToolchainID>com.visualgdb.arm-eabi</ToolchainID>
   <ToolchainVersion>
-    <GCC>12.3.1</GCC>
-    <GDB>13.2</GDB>
-    <Revision>1</Revision>
+    <GCC>13.3.1</GCC>
+    <GDB>15.1</GDB>
+    <Revision>2</Revision>
   </ToolchainVersion>
   <BspID>com.sysprogs.arm.nordic.nrf5x</BspID>
   <BspVersion>17.0</BspVersion>

pel.c

@@ -1,5 +1,5 @@
 #include "pel.h"
-#include "pel10_io.h"
+#include "elite_board.h"
 
 #include "elite_def.h"
 
@@ -9,7 +9,7 @@
 
 #include "adc_drv.h"
 
-#if (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
+#if (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
 
 typedef struct
 {
@@ -40,7 +40,7 @@ const input_pin_t input_pin_tab[] = {
 static float _load_set(uint32_t mask)
 {
     float ohms = 0;
-    for (uint32_t i = 0; i < COUNTOF(input_pin_tab); i++)
+    for (int32_t i = COUNTOF(input_pin_tab) - 1; i >= 0; i--)
     {
         if (input_pin_tab[i].mask & mask)
         {
@@ -55,6 +55,13 @@ static float _load_set(uint32_t mask)
     return ohms;
 }
 
+static void set_resistor_to_default(void)
+{
+    const uint32_t resistor_to_default = 0b000000000000;
+
+    _load_set(resistor_to_default);
+}
+
 static float _load_set_by_ohms(float ohms)
 {
     // TODO...
@@ -133,6 +140,7 @@ pel_output_t pel_smaple_and_convt_all(uint32_t measure_out, uint32_t load_mask)
     int32_t results[COUNTOF(ch_list)];
     float f_results[COUNTOF(ch_list)];
     /* config E-load */
+    set_resistor_to_default();
     _load_set(load_mask);
     /* send a pulse to sample and then read ADC channels */
     if (measure_out)
@@ -168,10 +176,10 @@ pel_output_t pel_smaple_and_convt_all(uint32_t measure_out, uint32_t load_mask)
 }
 
 #define VERSION_DATE_YEAR   24
-#define VERSION_DATE_MONTH  5
-#define VERSION_DATE_DAY    21
-#define VERSION_DATE_HOUR   18
-#define VERSION_DATE_MINUTE 39
+#define VERSION_DATE_MONTH  10
+#define VERSION_DATE_DAY    8
+#define VERSION_DATE_HOUR   12
+#define VERSION_DATE_MINUTE 31
 static void cis_version(uint8_t *ins, uint16_t size)
 {
     NRF_LOG_INFO("%s", __FUNCTION__);
@@ -248,6 +256,165 @@ void test_gpio_task(void *pArg)
     }
 }
 
+void set_a_specific_resistor_combination(uint16_t resistor_combination)
+{
+    typedef struct
+    {
+        uint16_t val;
+        uint32_t mask;
+    } resistor_combination_t;
+
+    const resistor_combination_t resis_combination_tab[] = {
+        { 1,      0b111},
+        { 2,      0b011},
+        { 3,      0b101},
+        { 4,      0b001},
+        { 5, 0b111 << 1},
+        { 6, 0b011 << 1},
+        { 7, 0b101 << 1},
+        { 8, 0b001 << 1},
+        { 9, 0b111 << 2},
+        {10, 0b011 << 2},
+        {11, 0b101 << 2},
+        {12, 0b001 << 2},
+        {13, 0b111 << 3},
+        {14, 0b011 << 3},
+        {15, 0b101 << 3},
+        {16, 0b001 << 3},
+        {17, 0b111 << 4},
+        {18, 0b011 << 4},
+        {19, 0b101 << 4},
+        {20, 0b001 << 4},
+        {21, 0b111 << 5},
+        {22, 0b011 << 5},
+        {23, 0b101 << 5},
+        {24, 0b001 << 5},
+        {25, 0b111 << 6},
+        {26, 0b011 << 6},
+        {27, 0b101 << 6},
+        {28, 0b001 << 6},
+        {29, 0b111 << 7},
+        {30, 0b011 << 7},
+        {31, 0b101 << 7},
+        {32, 0b001 << 7},
+        {33, 0b111 << 8},
+        {34, 0b011 << 8},
+        {35, 0b101 << 8},
+        {36, 0b001 << 8},
+        {37, 0b111 << 9},
+        {38, 0b011 << 9},
+        {39, 0b101 << 9},
+        {40, 0b001 << 9},
+        {41, 0b11 << 10},
+        {42, 0b01 << 10},
+        {43,  0b1 << 11},
+    };
+
+    for (int32_t i = 0; i < COUNTOF(resis_combination_tab); i++)
+    {
+        if (resis_combination_tab[i].val == resistor_combination)
+        {
+            NRF_LOG_INFO("No.%d resistor_combination: 0x%03X(FW) ", resis_combination_tab[i].val, resis_combination_tab[i].mask);
+            NRF_LOG_INFO("Input | 1 | 2 | 3 | 4 | 5 | 6 |");
+            NRF_LOG_INFO("      | %d | %d | %d | %d | %d | %d |",
+                         (resis_combination_tab[i].mask & 1 << 0),
+                         (resis_combination_tab[i].mask & 1 << 1) >> 1,
+                         (resis_combination_tab[i].mask & 1 << 2) >> 2,
+                         (resis_combination_tab[i].mask & 1 << 3) >> 3,
+                         (resis_combination_tab[i].mask & 1 << 4) >> 4,
+                         (resis_combination_tab[i].mask & 1 << 5) >> 5);
+
+            NRF_LOG_INFO("Input | 7 | 8 | 9 | 10 | 11 | 12 |");
+            NRF_LOG_INFO("      | %d | %d | %d |  %d |  %d |  %d |",
+                         (resis_combination_tab[i].mask & 1 << 6) >> 6,
+                         (resis_combination_tab[i].mask & 1 << 7) >> 7,
+                         (resis_combination_tab[i].mask & 1 << 8) >> 8,
+                         (resis_combination_tab[i].mask & 1 << 9) >> 9,
+                         (resis_combination_tab[i].mask & 1 << 10) >> 10,
+                         (resis_combination_tab[i].mask & 1 << 11) >> 11);
+            set_resistor_to_default();
+            _load_set(resis_combination_tab[i].mask);
+        }
+    }
+}
+
+void pel_select_resistor_combinations_mode(uint8_t *ins)
+{
+#define SET_A_SPECIFIC_RESISTOR_COMBINATION 0x00
+#define SET_ALL_RESISTORS_AT_ONCE           0x01
+
+    uint16_t set_resistor_type = (ins[4] & 0xF0) >> 4;
+    uint16_t val               = ((ins[4] & 0x0F) << 8) | ins[5];
+
+    if (set_resistor_type == 0)
+    {
+        set_a_specific_resistor_combination(val);
+    }
+    else if (set_resistor_type == 1)
+    {
+        typedef union
+        {
+            struct
+            {
+                uint32_t input1  : 1;
+                uint32_t input2  : 1;
+                uint32_t input3  : 1;
+                uint32_t input4  : 1;
+                uint32_t input5  : 1;
+                uint32_t input6  : 1;
+                uint32_t input7  : 1;
+                uint32_t input8  : 1;
+                uint32_t input9  : 1;
+                uint32_t input10 : 1;
+                uint32_t input11 : 1;
+                uint32_t input12 : 1;
+            };
+            uint32_t val;
+        } resis_t;
+
+        resis_t resis;
+
+        resis.input1  = (val & 0b0000100000000000) >> 11;
+        resis.input2  = (val & 0b0000010000000000) >> 10;
+        resis.input3  = (val & 0b0000001000000000) >> 9;
+        resis.input4  = (val & 0b0000000100000000) >> 8;
+        resis.input5  = (val & 0b0000000010000000) >> 7;
+        resis.input6  = (val & 0b0000000001000000) >> 6;
+        resis.input7  = (val & 0b0000000000100000) >> 5;
+        resis.input8  = (val & 0b0000000000010000) >> 4;
+        resis.input9  = (val & 0b0000000000001000) >> 3;
+        resis.input10 = (val & 0b0000000000000100) >> 2;
+        resis.input11 = (val & 0b0000000000000010) >> 1;
+        resis.input12 = (val & 0b0000000000000001) >> 0;
+
+        NRF_LOG_INFO("Set_all_resistors_at_once: 0x%03X(FW) ", resis.val);
+        NRF_LOG_INFO("Input | 1 | 2 | 3 | 4 | 5 | 6 |");
+        NRF_LOG_INFO("      | %d | %d | %d | %d | %d | %d |",
+                     (resis.val & 1 << 0),
+                     (resis.val & 1 << 1) >> 1,
+                     (resis.val & 1 << 2) >> 2,
+                     (resis.val & 1 << 3) >> 3,
+                     (resis.val & 1 << 4) >> 4,
+                     (resis.val & 1 << 5) >> 5);
+
+        NRF_LOG_INFO("Input | 7 | 8 | 9 | 10 | 11 | 12 |");
+        NRF_LOG_INFO("      | %d | %d | %d |  %d |  %d |  %d |",
+                     (resis.val & 1 << 6) >> 6,
+                     (resis.val & 1 << 7) >> 7,
+                     (resis.val & 1 << 8) >> 8,
+                     (resis.val & 1 << 9) >> 9,
+                     (resis.val & 1 << 10) >> 10,
+                     (resis.val & 1 << 11) >> 11);
+
+        set_resistor_to_default();
+        _load_set(resis.val);
+    }
+    else
+    {
+        printf("No this cmd...");
+    }
+}
+
 #define MAGIC_NUM 0xFF00
 static pel_output_t dev_mode_pel_output;
 static void dev_mode(uint8_t *ins, uint16_t size)
@@ -315,8 +482,13 @@ static void dev_mode(uint8_t *ins, uint16_t size)
             break;
         }
 
+        case 0x62: {
+            pel_select_resistor_combinations_mode(ins);
+            break;
+        }
+
         case 0xF0: {
-            pel10_io_init();
+            pel20_io_init();
             break;
         }
 
@@ -346,6 +518,80 @@ static void dev_mode(uint8_t *ins, uint16_t size)
             break;
         }
 
+        case 0xF2: {
+            struct
+            {
+                uint8_t input_n;
+                uint8_t status;
+            } __PACKED *p_param = (void *)p_ins->param;
+
+            uint32_t high_low = p_param->status;
+
+            switch (p_param->input_n)
+            {
+                case 0x01:
+                    nrf_gpio_pin_write(INPUT_1_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_1_PIN = %d", high_low);
+                    break;
+
+                case 0x02:
+                    nrf_gpio_pin_write(INPUT_2_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_2_PIN = %d", high_low);
+                    break;
+
+                case 0x03:
+                    nrf_gpio_pin_write(INPUT_3_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_3_PIN = %d", high_low);
+                    break;
+
+                case 0x04:
+                    nrf_gpio_pin_write(INPUT_4_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_4_PIN = %d", high_low);
+                    break;
+
+                case 0x05:
+                    nrf_gpio_pin_write(INPUT_5_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_5_PIN = %d", high_low);
+                    break;
+
+                case 0x06:
+                    nrf_gpio_pin_write(INPUT_6_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_6_PIN = %d", high_low);
+                    break;
+
+                case 0x07:
+                    nrf_gpio_pin_write(INPUT_7_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_7_PIN = %d", high_low);
+                    break;
+
+                case 0x08:
+                    nrf_gpio_pin_write(INPUT_8_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_8_PIN = %d", high_low);
+                    break;
+
+                case 0x09:
+                    nrf_gpio_pin_write(INPUT_9_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_9_PIN = %d", high_low);
+                    break;
+
+                case 0x0A:
+                    nrf_gpio_pin_write(INPUT_10_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_10_PIN = %d", high_low);
+                    break;
+
+                case 0x0B:
+                    nrf_gpio_pin_write(INPUT_11_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_11_PIN = %d", high_low);
+                    break;
+
+                case 0x0C:
+                    nrf_gpio_pin_write(INPUT_12_PIN, high_low);
+                    NRF_LOG_INFO("set INPUT_12_PIN = %d", high_low);
+                    break;
+            }
+            break;
+        }
+
         default: {
             break;
         }

pel20_io.c

@@ -1,12 +1,15 @@
 #include "elite_board.h"
 
+#include "nrf_gpio.h"
+#include "nrf_gpiote.h"
 #include "nrf_spim.h"
+#include "nrf_timer.h"
 
 #include "FreeRTOS.h"
 #include "semphr.h"
 #include "task.h"
 
-#if (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
+#if (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
 
 void spim_xfer(uint32_t cs_pin,
                nrf_spim_mode_t spi_mode,
@@ -67,7 +70,118 @@ void spim_xfer(uint32_t cs_pin,
     __enable_irq();
 }
 
-void pel10_io_init(void)
+#define MIN_PULSE_WIDTH 2
+#define MIN_PULSE_IDLE  2
+#define MAX_PULSE_WIDTH INT16_MAX
+#define MAX_PULSE_IDLE  INT16_MAX
+
+typedef struct
+{
+    uint32_t anode_pin;
+    uint32_t cathode_pin;
+    uint32_t pulse_idle;  // min: 2, max: 32767, unit: us
+    uint32_t pulse_width; // min: 2, max: 32767, unit: us,
+    uint32_t pulse_cnt;   // min: 1, max: 0xFFFFFFFF
+} pulse_gen_t;
+
+typedef struct
+{
+    uint32_t gpiote_idx[2];
+    NRF_TIMER_Type *pulse_tmr;
+    uint32_t pulse_irq_n;
+    uint32_t pulse_cnt;
+} pulse_gen_hw_t;
+
+pulse_gen_hw_t pulse_gen_hw = {
+    .gpiote_idx  = {0, 1},
+    .pulse_tmr   = NRF_TIMER3,
+    .pulse_irq_n = TIMER3_IRQn,
+    .pulse_cnt   = 0,
+};
+
+void TIMER3_IRQHandler(void)
+{
+    if (pulse_gen_hw.pulse_tmr->EVENTS_COMPARE[1])
+    {
+        pulse_gen_hw.pulse_tmr->EVENTS_COMPARE[1] = 0;
+        pulse_gen_hw.pulse_cnt--;
+        if (pulse_gen_hw.pulse_cnt == 1)
+        {
+            pulse_gen_hw.pulse_tmr->SHORTS |= NRF_TIMER_SHORT_COMPARE1_STOP_MASK;
+        }
+    }
+}
+
+bool pel_pulse_gen(pulse_gen_t *p_pulse_gen)
+{
+    /* hardware limitation */
+    if (p_pulse_gen->pulse_cnt == 0 ||
+        p_pulse_gen->pulse_idle < MIN_PULSE_IDLE ||
+        p_pulse_gen->pulse_width < MIN_PULSE_WIDTH ||
+        p_pulse_gen->pulse_idle > MAX_PULSE_IDLE ||
+        p_pulse_gen->pulse_width > MAX_PULSE_WIDTH)
+    {
+        return false;
+    }
+
+    pulse_gen_hw.pulse_cnt = p_pulse_gen->pulse_cnt;
+
+    pulse_gen_hw.pulse_tmr->TASKS_STOP = 1;
+
+    sd_nvic_DisableIRQ(pulse_gen_hw.pulse_irq_n);
+    sd_nvic_ClearPendingIRQ(pulse_gen_hw.pulse_irq_n);
+
+    nrf_gpiote_task_configure(pulse_gen_hw.gpiote_idx[0], p_pulse_gen->anode_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_HIGH);
+    nrf_gpiote_task_configure(pulse_gen_hw.gpiote_idx[1], p_pulse_gen->cathode_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
+
+    nrf_gpiote_task_enable(pulse_gen_hw.gpiote_idx[0]);
+    nrf_gpiote_task_enable(pulse_gen_hw.gpiote_idx[1]);
+
+    NRF_PPI->CH[0].EEP   = (uint32_t)&pulse_gen_hw.pulse_tmr->EVENTS_COMPARE[0];
+    NRF_PPI->CH[0].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw.gpiote_idx[0]];
+    NRF_PPI->FORK[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw.gpiote_idx[1]];
+    NRF_PPI->CHENSET     = (1 << (0));
+
+    NRF_PPI->CH[1].EEP   = (uint32_t)&pulse_gen_hw.pulse_tmr->EVENTS_COMPARE[1];
+    NRF_PPI->CH[1].TEP   = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw.gpiote_idx[0]];
+    NRF_PPI->FORK[1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pulse_gen_hw.gpiote_idx[1]];
+    NRF_PPI->CHENSET     = (1 << (1));
+
+    pulse_gen_hw.pulse_tmr->TASKS_CLEAR = 1;
+
+    pulse_gen_hw.pulse_tmr->PRESCALER = NRF_TIMER_FREQ_16MHz;
+    pulse_gen_hw.pulse_tmr->MODE      = NRF_TIMER_MODE_TIMER;
+    pulse_gen_hw.pulse_tmr->BITMODE   = NRF_TIMER_BIT_WIDTH_32;
+    pulse_gen_hw.pulse_tmr->CC[0]     = p_pulse_gen->pulse_idle * 16;
+    pulse_gen_hw.pulse_tmr->CC[1]     = pulse_gen_hw.pulse_tmr->CC[0] + p_pulse_gen->pulse_width * 16;
+    pulse_gen_hw.pulse_tmr->SHORTS    = pulse_gen_hw.pulse_cnt > 1 ? NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK : NRF_TIMER_SHORT_COMPARE1_STOP_MASK;
+    pulse_gen_hw.pulse_tmr->INTENSET  = NRF_TIMER_INT_COMPARE1_MASK;
+
+    sd_nvic_SetPriority(pulse_gen_hw.pulse_irq_n, _PRIO_APP_HIGH);
+    sd_nvic_EnableIRQ(pulse_gen_hw.pulse_irq_n);
+
+    pulse_gen_hw.pulse_tmr->TASKS_START = 1;
+
+    return true;
+}
+
+void pel_pulse_gen_demo(void)
+{
+    pulse_gen_t pulse_gen = {
+        .anode_pin   = ANODE_PIN,
+        .cathode_pin = CATHODE_PIN,
+        .pulse_width = 10,
+        .pulse_idle  = 1000,
+        .pulse_cnt   = 0xFFFFFFFF
+    };
+
+    if (pel_pulse_gen(&pulse_gen) == false)
+    {
+        // fail handling
+    }
+}
+
+void pel20_io_init(void)
 {
     const uint32_t pel_pins_default_high[] = {
         INPUT_1_PIN,
@@ -127,6 +241,8 @@ void pel10_io_init(void)
     NRF_SPIM3->PSEL.MOSI       = SPIM_MOSI_PIN;
     NRF_SPIM3->PSEL.MISO       = SPIM_MISO_PIN;
     NRF_SPIM3->ENABLE          = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+
+    pel_pulse_gen_demo();
 }
 
 #endif

pel20_io.h

@@ -1,8 +1,9 @@
-#ifndef __PEL10_IO_H__
-#define __PEL10_IO_H__
+#ifndef __PEL20_IO_H__
+#define __PEL20_IO_H__
 
 #ifdef __cplusplus
-extern "C" {
+extern "C"
+{
 #endif
 
 #include "app_config.h"
@@ -10,7 +11,7 @@ extern "C" {
 #include "nrf_gpio.h"
 #include "nrf_spim.h"
 
-#if (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
+#if (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
 
 #define RELAY1_PIN        NRF_GPIO_PIN_MAP(1, 10)
 #define RELAY2_PIN        NRF_GPIO_PIN_MAP(1, 15)
@@ -18,20 +19,20 @@ extern "C" {
 #define SAMPLE_R_PIN      NRF_GPIO_PIN_MAP(1, 11)
 #define SAMPLE_V_PIN      NRF_GPIO_PIN_MAP(1, 6)
 
-#define CATHODE_PIN       NRF_GPIO_PIN_MAP(0, 7)
-#define ANODE_PIN         NRF_GPIO_PIN_MAP(0, 8)
+#define CATHODE_PIN       NRF_GPIO_PIN_MAP(0, 8)
+#define ANODE_PIN         NRF_GPIO_PIN_MAP(0, 7)
 
 #define OUTPUT_R1_PIN     NRF_GPIO_PIN_MAP(0, 31)
 #define OUTPUT_R2_PIN     NRF_GPIO_PIN_MAP(0, 28)
 #define OUTPUT_VO_PIN     NRF_GPIO_PIN_MAP(0, 29)
-#define OUTPUT_VC_PIN     NRF_GPIO_PIN_MAP(0, 3)
-#define OUTPUT_VE_PIN     NRF_GPIO_PIN_MAP(0, 2)
+#define OUTPUT_VC_PIN     NRF_GPIO_PIN_MAP(0, 2)
+#define OUTPUT_VE_PIN     NRF_GPIO_PIN_MAP(0, 3)
 
 #define OUTPUT_R1_CHANNEL 7
 #define OUTPUT_R2_CHANNEL 4
 #define OUTPUT_VO_CHANNEL 5
-#define OUTPUT_VC_CHANNEL 1
-#define OUTPUT_VE_CHANNEL 0
+#define OUTPUT_VC_CHANNEL 0
+#define OUTPUT_VE_CHANNEL 1
 
 #define OUTPUT_R1_IDX     0
 #define OUTPUT_R2_IDX     1
@@ -58,14 +59,14 @@ extern "C" {
 #define SPIM_CLK_PIN      NRF_GPIO_PIN_MAP(0, 4)
 #define SPIM_MISO_PIN     NRF_GPIO_PIN_MAP(1, 9)
 
-void spim_xfer(uint32_t cs_pin,
-               nrf_spim_mode_t spi_mode,
-               uint8_t *p_tx_buffer,
-               uint16_t tx_buffer_length,
-               uint8_t *p_rx_buf,
-               uint16_t rx_buffer_length);
+    void spim_xfer(uint32_t cs_pin,
+                   nrf_spim_mode_t spi_mode,
+                   uint8_t *p_tx_buffer,
+                   uint16_t tx_buffer_length,
+                   uint8_t *p_rx_buf,
+                   uint16_t rx_buffer_length);
 
-void pel10_io_init(void);
+    void pel20_io_init(void);
 
 #endif /* ! DEF_ELITE_MODEL */
 
@@ -73,4 +74,4 @@ void pel10_io_init(void);
 }
 #endif
 
-#endif /* ! __PEL10_IO_H__ */
+#endif /* ! __PEL20_IO_H__ */

sw_drv.c

@@ -5,6 +5,11 @@
 #include "adgs1412.h"
 const sw_drv_if_t *p_inst = &adgs1412;
 
+#elif (DEF_MAX14802_ENABLED)
+
+#include "max14802.h"
+const sw_drv_if_t *p_inst = &max14802;
+
 #else
 
 const sw_drv_if_t *p_inst = NULL;

tw1508.c

@@ -0,0 +1,48 @@
+#include "tw1508.h"
+
+#include "nrf_delay.h"
+#include "nrf_log.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if (DEF_TW1508_ENABLED)
+
+void tw1508_set(uint16_t out_0, uint16_t out_1)
+{
+    typedef struct
+    {
+        uint32_t scki_pin;
+        uint32_t sdi_pin;
+        uint32_t val;
+    } tw1805_t;
+
+    tw1805_t tw1508[2] = {
+        {TW_SCKI_0_PIN, TW_SDI_PIN, out_0},
+        {TW_SCKI_1_PIN, TW_SDI_PIN, out_1},
+    };
+
+    nrf_gpio_pin_write(tw1508[0].scki_pin, 0);
+    nrf_gpio_pin_write(tw1508[1].scki_pin, 0);
+
+    for (uint32_t i = 0; i < COUNTOF(tw1508); i++)
+    {
+        for (uint16_t j = 0b1000000000; j > 0; j >>= 1)
+        {
+            nrf_delay_us(1);
+            nrf_gpio_pin_write(tw1508[i].sdi_pin, j & tw1508[i].val);
+            nrf_delay_us(1);
+            nrf_gpio_pin_write(tw1508[i].scki_pin, 1);
+            nrf_delay_us(1);
+            nrf_gpio_pin_write(tw1508[i].scki_pin, 0);
+        }
+    }
+    nrf_delay_us(256);
+}
+
+void tw1508_init(void)
+{
+    tw1508_set(0, 0);
+}
+
+#endif /* ! DEF_TW1508_ENABLED */

tw1508.h

@@ -0,0 +1,21 @@
+#ifndef __TW1508_H__
+#define __TW1508_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite_board.h"
+
+#if (DEF_TW1508_ENABLED)
+    void tw1508_set(uint16_t out_0, uint16_t out_1);
+    void tw1508_init(void);
+#endif /* ! DEF_TW1508_ENABLED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __CPG_H__ */