Merge branch 'sdk' into main
This commit is contained in:
Roy_01
@@ -1,3 +0,0 @@
|
||||
[submodule "BitFiles"]
|
||||
path = BitFiles
|
||||
url = https://60.248.80.176:28080/wlhsu/fpga_bit_file.git
|
||||
@@ -0,0 +1,298 @@
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||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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<externalSettings/>
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<extension id="org.eclipse.cdt.core.RV_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<listOptionValue builtIn="false" value="CONFIG_USE_PEC930"/>
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|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.212671820" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.1206119075" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide.625905344" name="Wide lines (--wide|-w)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.1552514466" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1158424346" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="Project.ilg.gnumcueclipse.managedbuild.cross.riscv.target.rvelf.1157615279" name="Executable" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.rvelf"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.926872659;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.926872659.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.991594434;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1843576227">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.16434552;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.16434552.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1901433257;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.868354821">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
<configuration configurationName="Debug">
|
||||
<resource resourceType="PROJECT" workspacePath="/Project"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Release">
|
||||
<resource resourceType="PROJECT" workspacePath="/Project"/>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
|
||||
</cproject>
|
||||
@@ -42,7 +42,7 @@
|
||||
</linkedResources>
|
||||
<filteredResources>
|
||||
<filter>
|
||||
<id>0</id>
|
||||
<id>1762843010815</id>
|
||||
<name></name>
|
||||
<type>6</type>
|
||||
<matcher>
|
||||
@@ -1,10 +1,8 @@
|
||||
demo_project
|
||||
---
|
||||
|
||||
This example is a demo project to descript
|
||||
> + How to log message
|
||||
This example is a demo project to descript `how to log message`
|
||||
|
||||
## Log
|
||||
|
||||
Use serial port with baudrate 115200, 8bit, no parity check.
|
||||
|
||||
@@ -52,7 +52,7 @@ int main(void)
|
||||
|
||||
syslog_init();
|
||||
|
||||
info("This is a demo project\n");
|
||||
info("This is a app demo project\n");
|
||||
msg("log debug message: $pc= x%08X\n", __get_pc());
|
||||
log_color(SLOG_GREEN, "color green\n");
|
||||
log_color(SLOG_YELLOW, "color yellow\n");
|
||||
@@ -1,10 +0,0 @@
|
||||
demo_project
|
||||
---
|
||||
|
||||
This example is a demo project to descript
|
||||
> + How to log message
|
||||
|
||||
## Log
|
||||
|
||||
Use serial port with baudrate 115200, 8bit, no parity check.
|
||||
|
||||
+16
-5
@@ -16,7 +16,11 @@
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
#define CONFIG_LOG_MSG_DEVICE UART0
|
||||
#define CONFIG_LOG_MSG_DEVICE UART0
|
||||
#define CONFIG_LOG_DEVICE_TX_IO_PORTx GPIOA
|
||||
#define CONFIG_LOG_DEVICE_TX_IO_PINx GPIO_Pin_15
|
||||
#define CONFIG_LOG_DEVICE_TX_IO_AF GPIO_AF_1
|
||||
#define CONFIG_LOG_DEVICE_RESET() __HAL_SYSCFG_RESET_UART0()
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
@@ -47,11 +51,11 @@ void syslog_init(void)
|
||||
GPIO_InitTypeDef gpio_init = {0};
|
||||
UART_InitTypeDef uart_init = {0};
|
||||
|
||||
/* configure GPIO Pin mux of UART (Tx through PA15) */
|
||||
gpio_init.GPIO_Pin = GPIO_Pin_15;
|
||||
/* configure GPIO Pin mux of UART Tx */
|
||||
gpio_init.GPIO_Pin = CONFIG_LOG_DEVICE_TX_IO_PINx;
|
||||
gpio_init.GPIO_AF_Mode = CONFIG_LOG_DEVICE_TX_IO_AF;
|
||||
gpio_init.GPIO_Mode = GPIO_Mode_AF;
|
||||
gpio_init.GPIO_AF_Mode = GPIO_AF_1;
|
||||
GPIO_Init(GPIOA, &gpio_init);
|
||||
GPIO_Init(CONFIG_LOG_DEVICE_TX_IO_PORTx, &gpio_init);
|
||||
|
||||
uart_init.BaudRate = SLOG_SERIAL_BPS;
|
||||
uart_init.WordLength = UART_WordLength_8b;
|
||||
@@ -64,6 +68,13 @@ void syslog_init(void)
|
||||
return;
|
||||
}
|
||||
|
||||
void syslog_deinit(void)
|
||||
{
|
||||
GPIO_DeInit(CONFIG_LOG_DEVICE_TX_IO_PORTx, CONFIG_LOG_DEVICE_TX_IO_PINx);
|
||||
CONFIG_LOG_DEVICE_RESET();
|
||||
return;
|
||||
}
|
||||
|
||||
void
|
||||
syslog_dump_mem(
|
||||
char *prefix,
|
||||
|
||||
@@ -82,6 +82,7 @@ extern "C" {
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
void syslog_init(void);
|
||||
void syslog_deinit(void);
|
||||
|
||||
/**
|
||||
* \brief Dump memory data through system log
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,161 +0,0 @@
|
||||
# Commit Rule
|
||||
---
|
||||
|
||||
當共同合作開發時, 能藉由瀏覽 Commit Message 內容快速進入狀況, 瞭解程式異動的原因, 如此也利於後續的維護.
|
||||
|
||||
良好的 Commit Message 在 release 時, 可大幅減少整理 Change Log 的時間.
|
||||
|
||||
+ 何謂好的 Commit Message ?
|
||||
> 一個好的 Commit Message 必須兼具 What & Why & How, 能幫助開發者瞭解這個提交版本:
|
||||
|
||||
- 這個提交版本做了什麼事情(What)
|
||||
> 這個版本修正了什麼 bug, 新增了什麼 feature, 或是優化了什麼效能, 也可能只是簡單的文字修正.
|
||||
這是一個 GCM 最重要的一部分, 必須要簡潔明瞭地告訴開發者這個提交版本的目的
|
||||
|
||||
- 為什麼要做這件事情(Why)
|
||||
> 說明更動的`動機`與`原因`是什麼, 並補充說明 `What` 所描述的項目
|
||||
|
||||
- 用什麼方法做到的(How)
|
||||
> 用什麼方法做到提交版本的目的. </br>
|
||||
在大部分簡單的提交版本中, 是不需要特別詳註的.
|
||||
> 建議是有需要特別補充的才紀錄在訊息中, 並且應該是提供 High-level 的方法與概念的敘述, 例如用了什麼演算法, 設計模式等, 而不是方法的實際細節.
|
||||
>> 方法細節應當透過更動的程式碼本身, 以及程式碼註解來自行解釋.
|
||||
|
||||
|
||||
# 設定 Git
|
||||
|
||||
|
||||
```
|
||||
$ git config --global user.name "your-name"
|
||||
$ git config --global user.email "your-email"
|
||||
```
|
||||
|
||||
+ Name
|
||||
> 在公司中使用的名字 (不要用暱稱, 要明確知道是誰)
|
||||
|
||||
+ E-mail
|
||||
> 限制使用公司的 e-mail
|
||||
|
||||
# Message Format
|
||||
|
||||
|
||||
一個 Commit Message 主要由 `Header (what)` + `Body(why)` + `Footer` 組成
|
||||
> 各部分以空行區隔, 為了讓 `git log` 顯示乾淨
|
||||
|
||||
```
|
||||
Message Header
|
||||
---> 空行
|
||||
Message Body
|
||||
---> 空行
|
||||
Message Footer
|
||||
```
|
||||
|
||||
### Message Header
|
||||
|
||||
```
|
||||
<type>(scope): <Chip ID><Module> <subject>
|
||||
```
|
||||
|
||||
+ type(必要): commit 的類別
|
||||
> 用來告訴進行 Code Review 的人應該以什麼態度來檢視 Commit 內容.
|
||||
> 利用不同的 Type 來決定進行 Code Review 檢視的角度, 可以提升 Code Review 的速度
|
||||
> + 看到 Type 為 `fix`, 進行 Code Review 的人就可以用**觀察 Commit 如何解決錯誤**的角度來閱讀程式碼
|
||||
> + 若是 `refactor`, 則可以放輕鬆閱讀程式碼如何被重構, 因為重構的本質是不會影響既有的功能
|
||||
|
||||
- `feat`: 新功能、新特性
|
||||
- `fix`: 修改 bug
|
||||
> 如果修復的這個BUG只影響當前修改的文件, 可不加範圍.
|
||||
如果影響的範圍比較大, 要加上範圍描述.
|
||||
例如這次 BUG 修復影響到全局, 可以加個 global. 如果影響的是某個目錄或某個功能, 可以加上該目錄的路徑, 或者對應的功能名稱.
|
||||
|
||||
```js
|
||||
fix(global): 修復checkbox不能復選的問題
|
||||
```
|
||||
|
||||
```
|
||||
# 下面圓括號裡的 common 為通用管理的名稱
|
||||
fix(common): 修復字體過小的BUG, 將通用管理下所有頁面的默認字體大小修改為 14px
|
||||
```
|
||||
|
||||
```
|
||||
fix: value.length -> values.length
|
||||
```
|
||||
|
||||
- `perf`: 更改代碼, 以提高性能(在不影響代碼內部行為的前提下, 對程序性能進行優化)
|
||||
- `refactor`: 代碼重構 (重構, 在不影響代碼內部行為, 功能下的代碼修改)
|
||||
- `docs`: 文檔修改
|
||||
- `style`: 代碼格式修改 (例如分號修改)
|
||||
- `test`: 測試用例新增, 修改
|
||||
- `build`: 影響項目構建或依賴項修改
|
||||
- `revert`: 恢復上一次提交
|
||||
- `ci`: 持續集成相關文件修改
|
||||
- `chore`: 其他修改(不在上述類型中的修改)
|
||||
> chore 的中文翻譯為日常事務、例行工作, 顧名思義, 即不在其他 commit 類型中的修改, 都可以用 chore 表示.
|
||||
- `release`: 發佈新版本
|
||||
|
||||
+ Chip ID(必要)
|
||||
> 註明 target ID, e.g. `F103`, `F100/F103`, `All`
|
||||
|
||||
+ Module
|
||||
> 註明目標的 module, e.g. peripheral name (I2C, Uart), Tool, ...等
|
||||
|
||||
+ subject(必要): commit 的簡短描述
|
||||
|
||||
- **不超過 50 個字元**
|
||||
> describe issue
|
||||
- 結尾不加句號
|
||||
- 儘量讓 Commit 單一化, 一次只更動一個主題
|
||||
|
||||
### Message Body
|
||||
|
||||
+ 對本次 Commit 的詳細描述
|
||||
+ 可以分成多行, **每一行不超過 72 個字元**
|
||||
> display issue
|
||||
+ 說明程式碼變動的項目與原因, 必要時與先前行為做對比
|
||||
|
||||
### Message Footer
|
||||
|
||||
如果有 Bug tracer, 紀錄 Issue ID
|
||||
|
||||
|
||||
### Example
|
||||
|
||||
```
|
||||
fix: [F103][I2C] Fix an error handling path in mtk_i2c_probe()
|
||||
|
||||
The clsk are prepared, enabled, then disabled. So if an error occurs after
|
||||
the disable step, they are still prepared.
|
||||
|
||||
Add an error handling path to unprepare the clks in such a case, as already
|
||||
done in the .remove function.
|
||||
|
||||
bug1234
|
||||
```
|
||||
|
||||
## Change Log
|
||||
|
||||
+ [Basic example](https://github.com/Mokkapps/changelog-generator-demo/blob/master/CHANGELOG.md)
|
||||
|
||||
+ [Angular- CHANGELOG](https://github.com/angular/angular/blob/22b96b96902e1a42ee8c5e807720424abad3082a/CHANGELOG.md)
|
||||
|
||||
|
||||
## Reference
|
||||
+ [約定式提交](https://www.conventionalcommits.org/zh-hans/v1.0.0-beta.4/)
|
||||
|
||||
|
||||
# Setup environment
|
||||
---
|
||||
|
||||
+ Install [Official Git](https://git-scm.com/downloads)
|
||||
|
||||
+ Verify git configuration
|
||||
|
||||
- [Right key] -> [Git Bash Here]
|
||||
> System MUST be installed official git tool.
|
||||
|
||||
- Execute `z_git_config.sh`
|
||||
> verify git configuration
|
||||
|
||||
```bash
|
||||
$ z_git_config.sh
|
||||
```
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 100 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 87 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 103 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 40 KiB |
@@ -1,10 +0,0 @@
|
||||
flash-loader
|
||||
---
|
||||
|
||||
## flash-loader for eFlash
|
||||
|
||||
`loader.bin` is used to download data (on Host) to DUT eFlash
|
||||
> OpenOCD should use `pb5700.cfg` to setup environment
|
||||
|
||||
+ flash-loader will be put at `0x2000_0A00` of DUT
|
||||
> It uses 1.5KB (?) as executing area
|
||||
@@ -1,204 +0,0 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file hal_comp.h
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/10/17
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
#ifndef __hal_comp_H_wqqzibVO_lvKI_HWdK_sROD_uhjcZz7SHMtL__
|
||||
#define __hal_comp_H_wqqzibVO_lvKI_HWdK_sROD_uhjcZz7SHMtL__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#include "hal_def.h"
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
/**
|
||||
* the voltige input_n of Comparer
|
||||
*/
|
||||
typedef enum COMP_Vin
|
||||
{
|
||||
COMP_Vin_IO = (COMP_CTRL_VIN_SEL_IO << COMP_CTRL_VIN_SEL_Pos),
|
||||
COMP_Vin_DAC = (COMP_CTRL_VIN_SEL_DAC << COMP_CTRL_VIN_SEL_Pos),
|
||||
|
||||
} COMP_VinTypeDef;
|
||||
|
||||
typedef enum COMP_Filter
|
||||
{
|
||||
COMP_Filter_Bypass = (COMP_CTRL_FIL_CTRL_BYPASS << COMP_CTRL_FIL_CTRL_Pos),
|
||||
COMP_Filter_Sample_2 = (COMP_CTRL_FIL_CTRL_SAMPLE_2 << COMP_CTRL_FIL_CTRL_Pos),
|
||||
COMP_Filter_Sample_4 = (COMP_CTRL_FIL_CTRL_SAMPLE_4 << COMP_CTRL_FIL_CTRL_Pos),
|
||||
COMP_Filter_Sample_8 = (COMP_CTRL_FIL_CTRL_SAMPLE_8 << COMP_CTRL_FIL_CTRL_Pos),
|
||||
COMP_Filter_Sample_16 = (COMP_CTRL_FIL_CTRL_SAMPLE_16 << COMP_CTRL_FIL_CTRL_Pos),
|
||||
COMP_Filter_Sample_32 = (COMP_CTRL_FIL_CTRL_SAMPLE_32 << COMP_CTRL_FIL_CTRL_Pos),
|
||||
COMP_Filter_Sample_64 = (COMP_CTRL_FIL_CTRL_SAMPLE_64 << COMP_CTRL_FIL_CTRL_Pos),
|
||||
COMP_Filter_Sample_128 = (COMP_CTRL_FIL_CTRL_SAMPLE_128 << COMP_CTRL_FIL_CTRL_Pos),
|
||||
COMP_Filter_Sample_256 = (COMP_CTRL_FIL_CTRL_SAMPLE_256 << COMP_CTRL_FIL_CTRL_Pos),
|
||||
|
||||
} COMP_FilterTypeDef;
|
||||
|
||||
/**
|
||||
* the voltige input_p of Comparer
|
||||
*/
|
||||
typedef enum COMP_Vip
|
||||
{
|
||||
COMP_Vip_PGA = (COMP_VIPSEL_VIP_SEL_PGA << COMP_VIPSEL_VIP_SEL_Pos),
|
||||
COMP_Vip_IO0 = (COMP_VIPSEL_VIP_SEL_IO0 << COMP_VIPSEL_VIP_SEL_Pos),
|
||||
COMP_Vip_IO1 = (COMP_VIPSEL_VIP_SEL_IO1 << COMP_VIPSEL_VIP_SEL_Pos),
|
||||
COMP_Vip_IO2 = (COMP_VIPSEL_VIP_SEL_IO2 << COMP_VIPSEL_VIP_SEL_Pos),
|
||||
COMP_Vip_IO3 = (COMP_VIPSEL_VIP_SEL_IO3 << COMP_VIPSEL_VIP_SEL_Pos),
|
||||
|
||||
} COMP_VipTypeDef;
|
||||
|
||||
|
||||
typedef enum COMP_Polarity
|
||||
{
|
||||
COMP_Polarity_Normal = (COMP_CTRL_POL_SEL_NORMAL << COMP_CTRL_POL_SEL_Pos),
|
||||
COMP_Polarity_Invert = (COMP_CTRL_POL_SEL_INVERT << COMP_CTRL_POL_SEL_Pos),
|
||||
|
||||
} COMP_PolarityTypeDef;
|
||||
|
||||
/**
|
||||
* Interrupt type of Comparer
|
||||
*/
|
||||
typedef enum COMP_IE
|
||||
{
|
||||
COMP_IE_Rising = COMP_IR_RIE_Msk,
|
||||
COMP_IE_Falling = COMP_IR_FIE_Msk,
|
||||
COMP_IE_ALL = (COMP_IR_RIE_Msk | COMP_IR_FIE_Msk),
|
||||
|
||||
} COMP_IETypeDef;
|
||||
|
||||
/**
|
||||
* Out type of Comparer
|
||||
*/
|
||||
|
||||
typedef enum COMP_Out
|
||||
{
|
||||
COMP_Out_Disable = 0x0,
|
||||
COMP_Out_Enable = COMP_CTRL_OUT_EN_Msk,
|
||||
|
||||
} COMP_OutTypeDef;
|
||||
|
||||
typedef enum COMP_Hsy
|
||||
{
|
||||
COMP_Hsy_Disable = 0x0,
|
||||
COMP_Hsy_Enable = COMP_CTRL_HYS_EN_Msk,
|
||||
|
||||
} COMP_HsyTypeDef;
|
||||
|
||||
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
|
||||
/**
|
||||
* \brief COMP enable/disable
|
||||
*
|
||||
* \param [in] pHComp pointer to a COMP instance
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
__STATIC_INLINE void COMP_Enable(COMP_Type *pHComp)
|
||||
{
|
||||
|
||||
REG_SET_BITS(pHComp->CTRL, COMP_CTRL_EN_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
__STATIC_INLINE void COMP_Disable(COMP_Type *pHComp)
|
||||
{
|
||||
|
||||
REG_CLR_BITS(pHComp->CTRL, COMP_CTRL_EN_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief COMP get output level
|
||||
*
|
||||
* \param [in] pHComp pointer to a COMP instance
|
||||
* \return
|
||||
* 0 : COMP OUT Low
|
||||
* others: COMP OUT High
|
||||
*/
|
||||
__STATIC_INLINE uint32_t COMP_GetOutputLevel(COMP_Type *pHComp)
|
||||
{
|
||||
return REG_READ_MASK(pHComp->CTRL, COMP_CTRL_COUT_Msk);
|
||||
}
|
||||
|
||||
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
|
||||
typedef struct
|
||||
{
|
||||
COMP_VinTypeDef COMP_NegativeSel; /*!<comparer n terminal input selection,@ref COMP_VinTypeDef */
|
||||
|
||||
COMP_FilterTypeDef COMP_Filter; /*!< comparer filter, @ref COMP_FilterTypeDef */
|
||||
|
||||
COMP_PolarityTypeDef COMP_Polarity; /*!< comparer polarity, @ref COMP_PolarityTypeDef */
|
||||
|
||||
COMP_VipTypeDef COMP_PositiveSel; /*!< comparer p terminal input selection, @ref COMP_VipTypeDef */
|
||||
|
||||
COMP_IETypeDef COMP_Interrupt; /*!< comparer interrupt type, e.g. rising, falling, both, ...etc. */
|
||||
|
||||
uint32_t COMP_InitDelay; /*!< comparer initial delay counter */
|
||||
|
||||
COMP_OutTypeDef COMP_Out;
|
||||
|
||||
COMP_HsyTypeDef COMP_Hsy;
|
||||
|
||||
|
||||
} COMP_InitTypeDef;
|
||||
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP module according to
|
||||
* the specified parameters in the init_struct.
|
||||
*
|
||||
* @param pHComp: pointer to a COMP instance
|
||||
* @param pInit: pointer to a COMP_InitTypeDef structure
|
||||
* that contains the configuration information for the
|
||||
* specified COMP module.
|
||||
* @retval None.
|
||||
*/
|
||||
void COMP_Init(COMP_Type *pHComp, COMP_InitTypeDef *pInit);
|
||||
|
||||
|
||||
/**
|
||||
* \brief De-initializes the COMP module
|
||||
*
|
||||
* \param [in] pHComp pointer to a COMP instance
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void COMP_DeInit(COMP_Type *pHComp);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,152 +0,0 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file hal_i2c.h
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/09/10
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
#ifndef __hal_i2c_H_wiTQLukR_lyWI_H9X1_s634_uL7YYZQ9qyOX__
|
||||
#define __hal_i2c_H_wiTQLukR_lyWI_H9X1_s634_uL7YYZQ9qyOX__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#include "hal_def.h"
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
/*************************************************************************************************************
|
||||
* STAT_I2C_STAT) : I2C Status Register (bit[7:3]total 26 flags), 26 states can generate interrupt requests.
|
||||
**************************************************************************************************************/
|
||||
#define I2C_MASTER_START_ACK (0x01ul)
|
||||
#define I2C_MASTER_RPTSTART_ACK (0x02ul)
|
||||
#define I2C_MASTER_WRDEVADREND_ACK (0x03ul)
|
||||
#define I2C_MASTER_WRDEVADREND_NACK (0x04ul)
|
||||
#define I2C_MASTER_WRDATEND_ACK (0x05ul)
|
||||
#define I2C_MASTER_WRDATEND_NACK (0x06ul)
|
||||
#define I2C_MASTER_WR_BUSLOST (0x07ul)
|
||||
#define I2C_MASTER_WRADR_RDCMD_ACK (0x08ul)
|
||||
#define I2C_MASTER_WRADR_RDCMD_NACK (0x09ul)
|
||||
#define I2C_RXDAT_TXACK (0x0Aul)
|
||||
#define I2C_RXDAT_TXNACK (0x0Bul)
|
||||
#define I2C_SLAVE_WRCMD_ACK (0x0Cul)
|
||||
#define I2C_SLAVE_RXADR_WRCMD_ACK (0x0Dul)
|
||||
#define I2C_RX_BROADCASTADR_ACK (0x0Eul)
|
||||
#define I2C_SLAVE_RXBROADCASTADR_ACK (0x0Ful)
|
||||
#define I2C_SLAVE_RXNEXTDAT_ACK (0x10ul)
|
||||
#define I2C_SLAVE_RXNEXTDAT_NACK (0x11ul)
|
||||
#define I2C_BROADCAST_RXNEXTDAT_ACK (0x12ul)
|
||||
#define I2C_BROADCAST_RXNEXTDAT_NACK (0x13ul)
|
||||
#define I2C_SLAVE_RXSTOP_OR_RPTSTAT (0x14ul)
|
||||
#define I2C_SLAVE_RXADR_RXCMD_ACK (0x15ul)
|
||||
#define I2C_BUSLOST_SLAVE_RXADR_RXCMD_ACK (0x16ul)
|
||||
#define I2C_SLAVE_TXDAT_ACK (0x17ul)
|
||||
#define I2C_SLAVE_TXDAT_NACK (0x18ul)
|
||||
#define I2C_SLAVE_TXLASTDAT_ACK (0x19ul)
|
||||
#define I2C_BUS_FREE (0x1Ful)
|
||||
|
||||
/**
|
||||
* @brief I2C mode definition
|
||||
*/
|
||||
#define I2C_Own_Address 0x55
|
||||
|
||||
#define I2C_Mode_Master 0x01
|
||||
#define I2C_Mode_Slave 0x00
|
||||
|
||||
typedef enum I2C_Clk_Div
|
||||
{
|
||||
I2C_CLK_Div60 = 0,
|
||||
I2C_CLK_Div120,
|
||||
I2C_CLK_Div160,
|
||||
I2C_CLK_Div192,
|
||||
I2C_CLK_Div244,
|
||||
I2C_CLK_Div256,
|
||||
I2C_CLK_Div960
|
||||
|
||||
} I2C_Clk_DivTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_STA_RESET = 0,
|
||||
I2C_STA_SET
|
||||
|
||||
} I2C_StartFlagTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_STO_RESET = 0,
|
||||
I2C_STO_SET
|
||||
} I2C_StopStaTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_SI_RESET = 0,
|
||||
I2C_SI_SET
|
||||
} I2C_SiStaTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_AA_RESET = 0,
|
||||
I2C_AA_SET
|
||||
} I2C_AckStaTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t I2C_Mode; /*!< Specifies the I2C mode. This parameter can be a value of I2C_mode. */
|
||||
uint16_t I2C_OwnAddress; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */
|
||||
I2C_Clk_DivTypeDef I2C_ClockDiv;
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
void I2C_DeInit(I2C_Type *i2c);
|
||||
void I2C_Cmd(I2C_Type *i2c, FunctionalState state);
|
||||
void I2C_Init(I2C_Type *i2c, I2C_InitTypeDef *init_struct);
|
||||
void I2C_StructInit(I2C_InitTypeDef *init_struct);
|
||||
void I2C_ClkDivConfig(I2C_Type *i2c, uint32_t I2C_ClockDivCr0,uint32_t I2C_ClockDivCr1,uint32_t I2C_ClockDivCr2);
|
||||
void I2C_GenerateSTART(I2C_Type *i2c, FunctionalState state);
|
||||
void I2C_GenerateSTOP(I2C_Type *i2c, FunctionalState state);
|
||||
void I2C_TargetAddressConfig(I2C_Type *i2c, uint8_t addr);
|
||||
void I2C_GeneralCallCmd(I2C_Type *i2c, FunctionalState state);
|
||||
void I2C_ITConfig(I2C_Type *i2c, FunctionalState state);
|
||||
void I2C_SendData(I2C_Type *i2c, uint8_t dat);
|
||||
void I2C_ReadCmd(I2C_Type *i2c);
|
||||
void I2C_StaFlagConfig(I2C_Type *i2c, I2C_StartFlagTypeDef sta,I2C_StopStaTypeDef sto,I2C_SiStaTypeDef si,I2C_AckStaTypeDef aa);
|
||||
void I2C_GenerateRESTART(I2C_Type *i2c, FunctionalState state);
|
||||
uint8_t I2C_ReceiveData(I2C_Type *i2c);
|
||||
uint32_t I2C_GetLastEvent(I2C_Type *i2c);
|
||||
ErrorStatus I2C_CheckEvent(I2C_Type *i2c, uint32_t event);
|
||||
FlagStatus I2C_GetFlagStatus(I2C_Type *i2c, uint32_t flag);
|
||||
uint32_t I2C_GetSlaveReceivedAddr(I2C_Type *i2c);
|
||||
ITStatus I2C_GetITStatus(I2C_Type *i2c, uint32_t it);
|
||||
uint32_t I2C_GetSta(I2C_Type *i2c);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,86 +0,0 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file hal_vcmp.c
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/10/17
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
|
||||
#include "hal_device.h"
|
||||
|
||||
#if defined(CONFIG_ENABLE_HAL_COMP)
|
||||
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
void COMP_Init(COMP_Type *pHComp, COMP_InitTypeDef *pInit)
|
||||
{
|
||||
if( pHComp == COMP0 )
|
||||
{
|
||||
__HAL_SYSCFG_COMP0_CLK_ENABLE();
|
||||
__HAL_SYSCFG_RESET_COMP0();
|
||||
}
|
||||
else if( pHComp == COMP1 )
|
||||
{
|
||||
__HAL_SYSCFG_COMP1_CLK_ENABLE();
|
||||
__HAL_SYSCFG_RESET_COMP1();
|
||||
}
|
||||
|
||||
REG_WRITE_MASK(pHComp->CTRL,
|
||||
COMP_CTRL_VIN_SEL_Msk | COMP_CTRL_FIL_CTRL_Msk | COMP_CTRL_POL_SEL_Msk |
|
||||
COMP_CTRL_OUT_EN_Msk | COMP_CTRL_HYS_EN_Msk ,
|
||||
pInit->COMP_NegativeSel | pInit->COMP_Filter | pInit->COMP_Polarity |
|
||||
pInit->COMP_Out | pInit->COMP_Hsy);
|
||||
|
||||
REG_WRITE_MASK(pHComp->VIPSEL, COMP_VIPSEL_VIP_SEL_Msk, pInit->COMP_PositiveSel);
|
||||
|
||||
REG_WRITE_MASK(pHComp->IR,
|
||||
COMP_IR_RIE_Msk | COMP_IR_FIE_Msk,
|
||||
pInit->COMP_Interrupt);
|
||||
|
||||
REG_WRITE_MASK(pHComp->INITCNT,
|
||||
COMP_INITCNT_INIT_DELAY_Msk,
|
||||
pInit->COMP_InitDelay);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void COMP_DeInit(COMP_Type *pHComp)
|
||||
{
|
||||
if( pHComp == COMP0 )
|
||||
{
|
||||
__HAL_SYSCFG_COMP0_CLK_DISABLE();
|
||||
}
|
||||
else if( pHComp == COMP1 )
|
||||
{
|
||||
__HAL_SYSCFG_COMP1_CLK_DISABLE();
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ENABLE_HAL_VCMP */
|
||||
@@ -1,288 +0,0 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file hal_i2c.c
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/09/10
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
|
||||
#include "hal_device.h"
|
||||
|
||||
#if defined(CONFIG_ENABLE_HAL_I2C)
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the i2c peripheral registers to their default
|
||||
* reset values.
|
||||
* @param i2c1.
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_DeInit(I2C_Type *i2c)
|
||||
{
|
||||
__HAL_SYSCFG_RESET_I2C();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the i2c peripheral according to the specified
|
||||
* parameters in the init_struct.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param init_struct: pointer to a I2C_InitTypeDef structure that
|
||||
* contains the configuration information for the specified
|
||||
* I2C peripheral.
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_Init(I2C_Type *i2c, I2C_InitTypeDef *init_struct)
|
||||
{
|
||||
__HAL_SYSCFG_I2C_CLK_ENABLE() ;
|
||||
REG_WRITE_MASK(i2c->ADDR, I2C_ADDR_ADDR_Msk, init_struct->I2C_OwnAddress);
|
||||
switch(init_struct->I2C_ClockDiv)
|
||||
{
|
||||
case (I2C_CLK_Div60):
|
||||
I2C_ClkDivConfig(i2c,0,1,1);
|
||||
break;
|
||||
case (I2C_CLK_Div120):
|
||||
I2C_ClkDivConfig(i2c,1,0,1);
|
||||
break;
|
||||
case (I2C_CLK_Div160):
|
||||
I2C_ClkDivConfig(i2c,1,1,0);
|
||||
break;
|
||||
case (I2C_CLK_Div192):
|
||||
I2C_ClkDivConfig(i2c,0,1,0);
|
||||
break;
|
||||
case (I2C_CLK_Div244):
|
||||
I2C_ClkDivConfig(i2c,1,0,0);
|
||||
break;
|
||||
case (I2C_CLK_Div256):
|
||||
I2C_ClkDivConfig(i2c,0,0,0);
|
||||
break;
|
||||
case (I2C_CLK_Div960):
|
||||
I2C_ClkDivConfig(i2c,0,0,1);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
void I2C_ClkDivConfig(I2C_Type *i2c, uint32_t I2C_ClockDivCr0,uint32_t I2C_ClockDivCr1,uint32_t I2C_ClockDivCr2)
|
||||
{
|
||||
(I2C_ClockDivCr0) ? \
|
||||
(REG_WRITE_MASK(i2c->CTLSET, I2C_CTLSET_CR0_Msk, 1 << I2C_CTLSET_CR0_Pos)) : \
|
||||
(REG_WRITE_MASK(i2c->CTLCLR, I2C_CTLCLR_CR0_Msk, 1 << I2C_CTLCLR_CR0_Pos));
|
||||
(I2C_ClockDivCr1) ? \
|
||||
(REG_WRITE_MASK(i2c->CTLSET, I2C_CTLSET_CR1_Msk, 1 << I2C_CTLSET_CR1_Pos)) : \
|
||||
(REG_WRITE_MASK(i2c->CTLCLR, I2C_CTLCLR_CR1_Msk, 1 << I2C_CTLCLR_CR1_Pos));
|
||||
(I2C_ClockDivCr2) ? \
|
||||
(REG_WRITE_MASK(i2c->CTLSET, I2C_CTLSET_CR2_Msk, 1 << I2C_CTLSET_CR2_Pos)) : \
|
||||
(REG_WRITE_MASK(i2c->CTLCLR, I2C_CTLCLR_CR2_Msk, 1 << I2C_CTLCLR_CR2_Pos));
|
||||
}
|
||||
/**
|
||||
* @brief Fills each init_struct member with its default value.
|
||||
* @param init_struct: pointer to an I2C_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_StructInit(I2C_InitTypeDef *init_struct)
|
||||
{
|
||||
init_struct->I2C_Mode = I2C_Mode_Master;
|
||||
init_struct->I2C_OwnAddress = I2C_Own_Address;
|
||||
init_struct->I2C_ClockDiv = I2C_CLK_Div256;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified I2C peripheral.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param state: new state of the i2c peripheral. This parameter
|
||||
* can be: ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_Cmd(I2C_Type *i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? \
|
||||
(i2c->CTLSET |= (0x01U << I2C_CTLSET_EN_Pos)) : \
|
||||
(i2c->CTLCLR |= (0x01U << I2C_CTLCLR_EN_Pos)) ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates i2c communication START condition.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param state: new state of the I2C START condition generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_GenerateSTART(I2C_Type *i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? \
|
||||
(i2c->CTLSET |= (0x01U << I2C_CTLSET_STA_Pos)) : \
|
||||
(i2c->CTLCLR |= (0x01U << I2C_CTLCLR_STA_Pos));
|
||||
}
|
||||
|
||||
void I2C_GenerateRESTART(I2C_Type *i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? \
|
||||
(i2c->CTLSET |= (0x01U << I2C_CTLSET_STA_Pos)) : \
|
||||
(i2c->CTLCLR |= (0x01U << I2C_CTLCLR_STA_Pos));
|
||||
}
|
||||
/**
|
||||
* @brief Generates i2c communication STOP condition.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param state: new state of the I2C STOP condition generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_GenerateSTOP(I2C_Type *i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? \
|
||||
(i2c->CTLSET |= (0x01U << I2C_CTLSET_STO_Pos)) : \
|
||||
(i2c->CTLCLR |= (0x01U << I2C_CTLCLR_STO_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the specified I2C Target Address.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param addr: specifies the 7bit I2C Target Address.
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_TargetAddressConfig(I2C_Type *i2c, uint8_t addr)
|
||||
{
|
||||
REG_WRITE_MASK(i2c->ADDR, I2C_ADDR_ADDR_Msk, addr << 1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified I2C interrupts.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param it: specifies the I2C interrupts sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg :
|
||||
* @param state: new state of the specified I2C interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_ITConfig(I2C_Type *i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? \
|
||||
(i2c->CTLSET |= (0x01U << I2C_CTLSET_SI_Pos)) : \
|
||||
(i2c->CTLCLR |= (0x01U << I2C_CTLCLR_SI_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sends a data byte through the i2c peripheral.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param dat: Byte to be transmitted..
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_SendData(I2C_Type *i2c, uint8_t dat)
|
||||
{
|
||||
i2c->DATA_b.DATA = dat;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the most recent received data by the i2c peripheral.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @retval The value of the received data.
|
||||
*/
|
||||
uint8_t I2C_ReceiveData(I2C_Type *i2c)
|
||||
{
|
||||
return ((uint8_t)i2c->DATA_b.DATA );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified I2C flag is set or not.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param flag: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg :
|
||||
* @retval The new state of I2C_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_Type *i2c, uint32_t flag)
|
||||
{
|
||||
return ((i2c->STAT_b.STAT == flag) ? SET : RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the i2c's pending flags.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param flag: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg I2C_START_RESET : Rx Buffer is empty flag
|
||||
* @arg I2C_START_SET : RX Buffer Overrun flag
|
||||
* @arg I2C_STO_RESET : Rx buffer full flag
|
||||
* @arg I2C_STO_SET : TX Buffer Overrun flag
|
||||
* @arg I2C_SI_RESET : TX_FIFO empty flag
|
||||
* @arg I2C_SI_SET : I2C work as slave or master flag
|
||||
* @arg I2C_AA_RESET : TX error flag(Master mode)
|
||||
* @arg I2C_AA_SET : Master not ack flag(slave mode)
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_ClearFlag(I2C_Type *i2c, uint32_t flag)
|
||||
{
|
||||
|
||||
}
|
||||
/**
|
||||
* @brief Config the i2c's flags.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @param flag: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg :
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_StaFlagConfig(I2C_Type *i2c, I2C_StartFlagTypeDef sta,I2C_StopStaTypeDef sto,I2C_SiStaTypeDef si,I2C_AckStaTypeDef aa)
|
||||
{
|
||||
(sta) ? \
|
||||
(REG_WRITE_MASK(i2c->CTLSET, I2C_CTLSET_STA_Msk, 1 << I2C_CTLSET_STA_Pos)) : \
|
||||
(REG_WRITE_MASK(i2c->CTLCLR, I2C_CTLCLR_STA_Msk, 1 << I2C_CTLCLR_STA_Pos));
|
||||
(sto) ? \
|
||||
(REG_WRITE_MASK(i2c->CTLSET, I2C_CTLSET_STO_Msk, 1 << I2C_CTLSET_STO_Pos)) : \
|
||||
(REG_WRITE_MASK(i2c->CTLCLR, I2C_CTLCLR_STO_Msk, 1 << I2C_CTLCLR_STO_Pos));
|
||||
(aa) ? \
|
||||
(REG_WRITE_MASK(i2c->CTLSET, I2C_CTLSET_AA_Msk, 1 << I2C_CTLSET_AA_Pos)) : \
|
||||
(REG_WRITE_MASK(i2c->CTLCLR, I2C_CTLCLR_AA_Msk, 1 << I2C_CTLCLR_AA_Pos));
|
||||
(si) ? \
|
||||
(REG_WRITE_MASK(i2c->CTLSET, I2C_CTLSET_SI_Msk, 1 << I2C_CTLSET_SI_Pos)) : \
|
||||
(REG_WRITE_MASK(i2c->CTLCLR, I2C_CTLCLR_SI_Msk, 1 << I2C_CTLCLR_SI_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last i2c Event.
|
||||
* @param i2c: select the I2C peripheral.
|
||||
* @retval The last event
|
||||
*/
|
||||
uint32_t I2C_GetSlaveReceivedAddr(I2C_Type *i2c)
|
||||
{
|
||||
return ((uint32_t)i2c->ADDR);
|
||||
}
|
||||
|
||||
uint32_t I2C_GetSta(I2C_Type *i2c)
|
||||
{
|
||||
return ((uint32_t)i2c->STAT_b.STAT);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ENABLE_HAL_I2C */
|
||||
@@ -1,92 +0,0 @@
|
||||
#
|
||||
# component Makefile
|
||||
#
|
||||
|
||||
|
||||
#=======================================
|
||||
# Configurations
|
||||
#=======================================
|
||||
|
||||
#
|
||||
# Drivers of MCU
|
||||
#
|
||||
|
||||
SOC_CPU_NAME = n203e
|
||||
|
||||
#=======================================
|
||||
# system
|
||||
#=======================================
|
||||
ifeq ("$(SOC)","pb5700")
|
||||
C_DEFS += -DCONFIG_USE_PB5700
|
||||
else
|
||||
$(error "Unknown SoC !!!")
|
||||
endif
|
||||
|
||||
#
|
||||
# cpu
|
||||
#
|
||||
C_DEFS += -DCONFIG_CPU_N203E -DCONFIG_HAS_BPU
|
||||
|
||||
CPU_FLAGS = -mabi=ilp32e -mcmodel=medlow
|
||||
CPU_FLAGS += -march=rv32emc_zba_zbb_zbs_zca_zcb_zcmp_zcmt_zicond
|
||||
|
||||
|
||||
#
|
||||
# Source
|
||||
#
|
||||
ASM_SOURCES := \
|
||||
$(srctree)/Drivers/PB5700/Device/src/Startup/startup.S \
|
||||
$(srctree)/Drivers/PB5700/Device/src/Startup/trap.S
|
||||
|
||||
C_SOURCES += \
|
||||
$(srctree)/Drivers/PB5700/Device/src/interrupt.c \
|
||||
$(srctree)/Drivers/PB5700/Device/src/syscalls.c \
|
||||
$(srctree)/Drivers/PB5700/Device/src/system_dev.c
|
||||
|
||||
C_INCLUDES += \
|
||||
-I$(srctree)/Drivers/PB5700/Device/inc \
|
||||
-I$(srctree)/Drivers/PB5700/NMSIS/Core/Include \
|
||||
-I$(srctree)/Drivers/PB5700/
|
||||
|
||||
|
||||
|
||||
#=======================================
|
||||
# peripheral hal driver
|
||||
#=======================================
|
||||
C_SOURCES += \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_adc.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_amisc.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_comp.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_opamp.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_crc.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_dsp.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_flash.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_gpio.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_i2c.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_lptim.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_pwr.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_spi.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_syscfg.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_tim.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_uart.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_wdg.c \
|
||||
$(srctree)/Drivers/PB5700/HAL_Lib/src/hal_device.c
|
||||
|
||||
C_INCLUDES += \
|
||||
-I$(srctree)/Drivers/PB5700/HAL_Lib/inc
|
||||
|
||||
#=======================================
|
||||
# BSP
|
||||
#=======================================
|
||||
C_SOURCES += $(srctree)/Drivers/PB5700/BSP/StarterKit/starterkit.c
|
||||
|
||||
C_INCLUDES += \
|
||||
-I$(srctree)/Drivers/PB5700/BSP/StarterKit
|
||||
|
||||
#=======================================
|
||||
# Flags
|
||||
#=======================================
|
||||
CFLAGS += $(CPU_FLAGS)
|
||||
CXXFLAGS +=
|
||||
LDFLAGS += $(CPU_FLAGS)
|
||||
LIBDIR +=
|
||||
+270
-6
@@ -1,9 +1,9 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
|
||||
<vendor>Padauk-tech</vendor>
|
||||
<name>PB5700</name>
|
||||
<name>PEC930</name>
|
||||
<version>1.0</version>
|
||||
<description>PB5700 uses 32-bits RISC-V CPU</description>
|
||||
<description>RISC-V 32-bits CPU</description>
|
||||
<addressUnitBits>8</addressUnitBits>
|
||||
<width>32</width>
|
||||
<size>32</size>
|
||||
@@ -139,7 +139,7 @@
|
||||
<peripheral>
|
||||
<name>UID</name>
|
||||
<description>Universally Unique Identifier</description>
|
||||
<baseAddress>0x00201EB0</baseAddress>
|
||||
<baseAddress>0x00201F00</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0xC</size>
|
||||
@@ -7993,6 +7993,25 @@
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<access>read-write</access>
|
||||
<fields>
|
||||
<field>
|
||||
<name>LDO_SEL</name>
|
||||
<description>HSI power source selection</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>16</bitWidth>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>LDO</name>
|
||||
<description>ldo_oschf Disable abd vddl_oschf from ldo</description>
|
||||
<value>0x8080</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Normal</name>
|
||||
<description>do_oschf Enable and vddl_oschf from ldo_oschf</description>
|
||||
<value>0x0101</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>HSI_EN</name>
|
||||
<description>HSI enable, set 0x80(disable), set 0x1(enable)</description>
|
||||
@@ -8040,6 +8059,163 @@
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>HWTRIM</name>
|
||||
<description>H/w configure trim values</description>
|
||||
<baseAddress>0x40005860</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x20</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<!-- CRC_CTL Register -->
|
||||
<register>
|
||||
<name>LDO_TRIM</name>
|
||||
<description>LDO trim value</description>
|
||||
<addressOffset>0x00</addressOffset>
|
||||
<size>32</size>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<access>read-only</access>
|
||||
<fields>
|
||||
<field>
|
||||
<name>LDO_TRIM</name>
|
||||
<description>LDO trim value</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>5</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>LDO_LP_TRIM</name>
|
||||
<description>LDO lower power trim value</description>
|
||||
<bitOffset>5</bitOffset>
|
||||
<bitWidth>5</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>LDO_TUNE</name>
|
||||
<description>Ldo high temp leakage current compensation</description>
|
||||
<bitOffset>10</bitOffset>
|
||||
<bitWidth>2</bitWidth>
|
||||
<access>read-only</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>STRENGTH</name>
|
||||
<description>strength</description>
|
||||
<value>0x0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>WEAK</name>
|
||||
<description>weak</description>
|
||||
<value>0x1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>MIDDLEddle</name>
|
||||
<description>middle</description>
|
||||
<value>0x2</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>OFF</name>
|
||||
<description>off</description>
|
||||
<value>0x3</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<!-- CRC_SEED Register -->
|
||||
<register>
|
||||
<name>VBUF_TRIM</name>
|
||||
<description>Vbuf trim value</description>
|
||||
<addressOffset>0x04</addressOffset>
|
||||
<size>32</size>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<access>read-only</access>
|
||||
<fields>
|
||||
<field>
|
||||
<name>VBUF_TRIM</name>
|
||||
<description>VBUF voltage trim value</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>7</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>HSI_TRIM</name>
|
||||
<description>High Speed Internal clock (OSCHF) trim value</description>
|
||||
<addressOffset>0x08</addressOffset>
|
||||
<size>32</size>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<access>read-only</access>
|
||||
<fields>
|
||||
<field>
|
||||
<name>HSI_D_CFG</name>
|
||||
<description>HSI low trim config</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>9</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>HSI_FSEL_CFG</name>
|
||||
<description>HSI high trim config</description>
|
||||
<bitOffset>9</bitOffset>
|
||||
<bitWidth>7</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>HSI_TC</name>
|
||||
<description>The TC of HSI trim value</description>
|
||||
<bitOffset>16</bitOffset>
|
||||
<bitWidth>2</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<!-- CRC_POLY Register -->
|
||||
<register>
|
||||
<name>LSI_TRIM</name>
|
||||
<description>Low Speed Internal clock (OSCLF) trim value</description>
|
||||
<addressOffset>0x0C</addressOffset>
|
||||
<size>32</size>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<access>read-only</access>
|
||||
<fields>
|
||||
<field>
|
||||
<name>LSI_TRIM</name>
|
||||
<description>The LSI trim value, 0xB3= 32KHz</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>8</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>MISC_CFG</name>
|
||||
<description>The miscellaneous configuration</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<access>read-only</access>
|
||||
<fields>
|
||||
<field>
|
||||
<name>EXT_nRST_EN</name>
|
||||
<description>External reset pin enable</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<!-- CRC_DIN Register -->
|
||||
<!-- CRC_DOUT Register -->
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>CRC</name>
|
||||
<description>Cyclic redundancy check</description>
|
||||
@@ -9161,6 +9337,42 @@
|
||||
<bitOffset>7</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>CCD1IE</name>
|
||||
<description>Capture/Compare 1 interrupt enable</description>
|
||||
<bitOffset>8</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>CCD2IE</name>
|
||||
<description>Capture/Compare 2 interrupt enable</description>
|
||||
<bitOffset>9</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>CCD3IE</name>
|
||||
<description>Capture/Compare 3 interrupt enable</description>
|
||||
<bitOffset>10</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>OVIE</name>
|
||||
<description>Overflow interrupt enable</description>
|
||||
<bitOffset>11</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>UDIE</name>
|
||||
<description>Underflow interrupt enable</description>
|
||||
<bitOffset>12</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>CCD4IE</name>
|
||||
<description>Capture/Compare 4 interrupt enable</description>
|
||||
<bitOffset>13</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
@@ -9247,6 +9459,42 @@
|
||||
<bitWidth>1</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CCD1IF</name>
|
||||
<description>Capture/Compare 1 interrupt flag</description>
|
||||
<bitOffset>13</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>CCD2IF</name>
|
||||
<description>Capture/Compare 2 interrupt flag</description>
|
||||
<bitOffset>14</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>CCD3IF</name>
|
||||
<description>Capture/Compare 3 interrupt flag</description>
|
||||
<bitOffset>15</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>OVIF</name>
|
||||
<description>Overflow interrupt flag</description>
|
||||
<bitOffset>16</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>UDIF</name>
|
||||
<description>Underflow interrupt flag</description>
|
||||
<bitOffset>17</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
<field>
|
||||
<name>CCD4IF</name>
|
||||
<description>Break interrupt flag</description>
|
||||
<bitOffset>18</bitOffset>
|
||||
<bitWidth>1</bitWidth>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
@@ -9854,7 +10102,7 @@
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>CCR1</name>
|
||||
<name>CCDR1</name>
|
||||
<description>Down Capture/Compare 1 value</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>20</bitWidth>
|
||||
@@ -9870,7 +10118,7 @@
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>CCR2</name>
|
||||
<name>CCDR2</name>
|
||||
<description>Down Capture/Compare 2 value</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>20</bitWidth>
|
||||
@@ -9886,13 +10134,29 @@
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>CCR3</name>
|
||||
<name>CCDR3</name>
|
||||
<description>Down Capture/Compare 3 value</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>20</bitWidth>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CCDR4</name>
|
||||
<description>CR4 down capture or compare value</description>
|
||||
<addressOffset>0X5C</addressOffset>
|
||||
<size>32</size>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xFFFFFFFF</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>CCDR4</name>
|
||||
<description>Down Capture/Compare 4 value</description>
|
||||
<bitOffset>0</bitOffset>
|
||||
<bitWidth>20</bitWidth>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral derivedFrom="TIM">
|
||||
@@ -1,7 +1,7 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file pb57xx.h
|
||||
/** @file device.h
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
@@ -10,15 +10,15 @@
|
||||
* @description
|
||||
*/
|
||||
|
||||
#ifndef __pb57xx_H_wqIH3HdS_l3C8_Hgh6_syur_ubmEVDiPX8aR__
|
||||
#define __pb57xx_H_wqIH3HdS_l3C8_Hgh6_syur_ubmEVDiPX8aR__
|
||||
#ifndef __device_H_wqIH3HdS_l3C8_Hgh6_syur_ubmEVDiPX8aR__
|
||||
#define __device_H_wqIH3HdS_l3C8_Hgh6_syur_ubmEVDiPX8aR__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USE_PB5700)
|
||||
#include "pb5700.h"
|
||||
#if defined(CONFIG_USE_PEC930)
|
||||
#include "pec930.h"
|
||||
#else
|
||||
#error "Please select first the target device !"
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Paduak-Tech. All rights reserved.
|
||||
* Copyright (c) 2024-2025 Paduak-Tech. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -15,13 +15,13 @@
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* @file PB5700.h
|
||||
* @file PEC930.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1.0
|
||||
* @date 23. September 2025
|
||||
* @note Generated by SVDConv V3.3.38 on Tuesday, 23.09.2025 12:30:25
|
||||
* from File './PB5700.svd',
|
||||
* last modified on Tuesday, 23.09.2025 04:19:56
|
||||
* @date 27. November 2025
|
||||
* @note Generated by SVDConv V3.3.38 on Thursday, 27.11.2025 08:40:32
|
||||
* from File './PEC930.svd',
|
||||
* last modified on Wednesday, 26.11.2025 09:47:40
|
||||
*/
|
||||
|
||||
|
||||
@@ -31,13 +31,13 @@
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PB5700
|
||||
/** @addtogroup PEC930
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#ifndef PB5700_H
|
||||
#define PB5700_H
|
||||
#ifndef PEC930_H
|
||||
#define PEC930_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@@ -55,7 +55,7 @@ extern "C" {
|
||||
/* =========================================================================================================================== */
|
||||
|
||||
typedef enum {
|
||||
/* =========================================== PB5700 Specific Interrupt Numbers =========================================== */
|
||||
/* =========================================== PEC930 Specific Interrupt Numbers =========================================== */
|
||||
SysSW_IRQn = 3, /*!< 3 System Software interrupt */
|
||||
SysTimer_IRQn = 7, /*!< 7 System Timer interrupt */
|
||||
BusError_IRQn = 17, /*!< 17 Bus error interrupt */
|
||||
@@ -302,7 +302,7 @@ typedef struct { /*!< (@ 0x18000000) CORET Struct
|
||||
* @brief Universally Unique Identifier (UID)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x00201EB0) UID Structure */
|
||||
typedef struct { /*!< (@ 0x00201F00) UID Structure */
|
||||
__IM uint32_t UID1; /*!< (@ 0x00000000) Unique Identifier 1 */
|
||||
__IM uint32_t UID2; /*!< (@ 0x00000004) Unique Identifier 2 */
|
||||
__IM uint32_t UID3; /*!< (@ 0x00000008) Unique Identifier 3 */
|
||||
@@ -2065,7 +2065,8 @@ typedef struct { /*!< (@ 0x40005800) AMISC Struct
|
||||
__IOM uint32_t HSI_CR; /*!< (@ 0x00000020) HSI (OSCHF) Control Register */
|
||||
|
||||
struct {
|
||||
uint32_t : 24;
|
||||
__IOM uint32_t LDO_SEL : 16; /*!< [15..0] HSI power source selection */
|
||||
uint32_t : 8;
|
||||
__IOM uint32_t HSI_EN : 8; /*!< [31..24] HSI enable, set 0x80(disable), set 0x1(enable) */
|
||||
} HSI_CR_b;
|
||||
} ;
|
||||
@@ -2092,6 +2093,69 @@ typedef struct { /*!< (@ 0x40005800) AMISC Struct
|
||||
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ HWTRIM ================ */
|
||||
/* =========================================================================================================================== */
|
||||
|
||||
|
||||
/**
|
||||
* @brief H/w configure trim values (HWTRIM)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40005860) HWTRIM Structure */
|
||||
|
||||
union {
|
||||
__IM uint32_t LDO_TRIM; /*!< (@ 0x00000000) LDO trim value */
|
||||
|
||||
struct {
|
||||
__IM uint32_t LDO_TRIM : 5; /*!< [4..0] LDO trim value */
|
||||
__IM uint32_t LDO_LP_TRIM : 5; /*!< [9..5] LDO lower power trim value */
|
||||
__IM uint32_t LDO_TUNE : 2; /*!< [11..10] Ldo high temp leakage current compensation */
|
||||
uint32_t : 20;
|
||||
} LDO_TRIM_b;
|
||||
} ;
|
||||
|
||||
union {
|
||||
__IM uint32_t VBUF_TRIM; /*!< (@ 0x00000004) Vbuf trim value */
|
||||
|
||||
struct {
|
||||
__IM uint32_t VBUF_TRIM : 7; /*!< [6..0] VBUF voltage trim value */
|
||||
uint32_t : 25;
|
||||
} VBUF_TRIM_b;
|
||||
} ;
|
||||
|
||||
union {
|
||||
__IM uint32_t HSI_TRIM; /*!< (@ 0x00000008) High Speed Internal clock (OSCHF) trim value */
|
||||
|
||||
struct {
|
||||
__IM uint32_t HSI_D_CFG : 9; /*!< [8..0] HSI low trim config */
|
||||
__IM uint32_t HSI_FSEL_CFG : 7; /*!< [15..9] HSI high trim config */
|
||||
__IM uint32_t HSI_TC : 2; /*!< [17..16] The TC of HSI trim value */
|
||||
uint32_t : 14;
|
||||
} HSI_TRIM_b;
|
||||
} ;
|
||||
|
||||
union {
|
||||
__IM uint32_t LSI_TRIM; /*!< (@ 0x0000000C) Low Speed Internal clock (OSCLF) trim value */
|
||||
|
||||
struct {
|
||||
__IM uint32_t LSI_TRIM : 8; /*!< [7..0] The LSI trim value, 0xB3= 32KHz */
|
||||
uint32_t : 24;
|
||||
} LSI_TRIM_b;
|
||||
} ;
|
||||
|
||||
union {
|
||||
__IM uint32_t MISC_CFG; /*!< (@ 0x00000010) The miscellaneous configuration */
|
||||
|
||||
struct {
|
||||
__IM uint32_t EXT_nRST_EN : 1; /*!< [0..0] External reset pin enable */
|
||||
uint32_t : 31;
|
||||
} MISC_CFG_b;
|
||||
} ;
|
||||
} HWTRIM_Type; /*!< Size = 20 (0x14) */
|
||||
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ CRC ================ */
|
||||
/* =========================================================================================================================== */
|
||||
@@ -2344,7 +2408,13 @@ typedef struct { /*!< (@ 0x4000C000) TIM Structur
|
||||
__IOM uint32_t COMIE : 1; /*!< [5..5] COM interrupt enable */
|
||||
__IOM uint32_t TIE : 1; /*!< [6..6] Trigger interrupt enable */
|
||||
__IOM uint32_t BIE : 1; /*!< [7..7] Break interrupt enable */
|
||||
uint32_t : 24;
|
||||
__IOM uint32_t CCD1IE : 1; /*!< [8..8] Capture/Compare 1 interrupt enable */
|
||||
__IOM uint32_t CCD2IE : 1; /*!< [9..9] Capture/Compare 2 interrupt enable */
|
||||
__IOM uint32_t CCD3IE : 1; /*!< [10..10] Capture/Compare 3 interrupt enable */
|
||||
__IOM uint32_t OVIE : 1; /*!< [11..11] Overflow interrupt enable */
|
||||
__IOM uint32_t UDIE : 1; /*!< [12..12] Underflow interrupt enable */
|
||||
__IOM uint32_t CCD4IE : 1; /*!< [13..13] Capture/Compare 4 interrupt enable */
|
||||
uint32_t : 18;
|
||||
} DIER_b;
|
||||
} ;
|
||||
|
||||
@@ -2365,7 +2435,13 @@ typedef struct { /*!< (@ 0x4000C000) TIM Structur
|
||||
__IOM uint32_t CC2OF : 1; /*!< [10..10] CC2OF */
|
||||
__IOM uint32_t CC3OF : 1; /*!< [11..11] CC3OF */
|
||||
__IOM uint32_t CC4OF : 1; /*!< [12..12] CC4OF */
|
||||
uint32_t : 19;
|
||||
__IOM uint32_t CCD1IF : 1; /*!< [13..13] Capture/Compare 1 interrupt flag */
|
||||
__IOM uint32_t CCD2IF : 1; /*!< [14..14] Capture/Compare 2 interrupt flag */
|
||||
__IOM uint32_t CCD3IF : 1; /*!< [15..15] Capture/Compare 3 interrupt flag */
|
||||
__IOM uint32_t OVIF : 1; /*!< [16..16] Overflow interrupt flag */
|
||||
__IOM uint32_t UDIF : 1; /*!< [17..17] Underflow interrupt flag */
|
||||
__IOM uint32_t CCD4IF : 1; /*!< [18..18] Break interrupt flag */
|
||||
uint32_t : 13;
|
||||
} SR_b;
|
||||
} ;
|
||||
|
||||
@@ -2570,7 +2646,7 @@ typedef struct { /*!< (@ 0x4000C000) TIM Structur
|
||||
__IOM uint32_t CCDR1; /*!< (@ 0x00000050) CR1 down capture or compare value */
|
||||
|
||||
struct {
|
||||
__IOM uint32_t CCR1 : 20; /*!< [19..0] Down Capture/Compare 1 value */
|
||||
__IOM uint32_t CCDR1 : 20; /*!< [19..0] Down Capture/Compare 1 value */
|
||||
uint32_t : 12;
|
||||
} CCDR1_b;
|
||||
} ;
|
||||
@@ -2579,7 +2655,7 @@ typedef struct { /*!< (@ 0x4000C000) TIM Structur
|
||||
__IOM uint32_t CCDR2; /*!< (@ 0x00000054) CR2 down capture or compare value */
|
||||
|
||||
struct {
|
||||
__IOM uint32_t CCR2 : 20; /*!< [19..0] Down Capture/Compare 2 value */
|
||||
__IOM uint32_t CCDR2 : 20; /*!< [19..0] Down Capture/Compare 2 value */
|
||||
uint32_t : 12;
|
||||
} CCDR2_b;
|
||||
} ;
|
||||
@@ -2588,11 +2664,20 @@ typedef struct { /*!< (@ 0x4000C000) TIM Structur
|
||||
__IOM uint32_t CCDR3; /*!< (@ 0x00000058) CR3 down capture or compare value */
|
||||
|
||||
struct {
|
||||
__IOM uint32_t CCR3 : 20; /*!< [19..0] Down Capture/Compare 3 value */
|
||||
__IOM uint32_t CCDR3 : 20; /*!< [19..0] Down Capture/Compare 3 value */
|
||||
uint32_t : 12;
|
||||
} CCDR3_b;
|
||||
} ;
|
||||
} TIM_Type; /*!< Size = 92 (0x5c) */
|
||||
|
||||
union {
|
||||
__IOM uint32_t CCDR4; /*!< (@ 0x0000005C) CR4 down capture or compare value */
|
||||
|
||||
struct {
|
||||
__IOM uint32_t CCDR4 : 20; /*!< [19..0] Down Capture/Compare 4 value */
|
||||
uint32_t : 12;
|
||||
} CCDR4_b;
|
||||
} ;
|
||||
} TIM_Type; /*!< Size = 96 (0x60) */
|
||||
|
||||
|
||||
|
||||
@@ -2693,7 +2778,7 @@ typedef struct { /*!< (@ 0x4000C800) LPTIM Struct
|
||||
#define SRAM_MEM_BASE 0x20000000UL
|
||||
#define NVR_MEM_BASE 0x00200000UL
|
||||
#define CORET_BASE 0x18000000UL
|
||||
#define UID_BASE 0x00201EB0UL
|
||||
#define UID_BASE 0x00201F00UL
|
||||
#define FLASH_BASE 0x4000F800UL
|
||||
#define GPIO_BASE 0x40011000UL
|
||||
#define GPIOA_BASE 0x40011000UL
|
||||
@@ -2710,6 +2795,7 @@ typedef struct { /*!< (@ 0x4000C800) LPTIM Struct
|
||||
#define ADC_BASE 0x40004800UL
|
||||
#define ADC0_BASE 0x40004800UL
|
||||
#define AMISC_BASE 0x40005800UL
|
||||
#define HWTRIM_BASE 0x40005860UL
|
||||
#define CRC_BASE 0x4001E000UL
|
||||
#define DSP_BASE 0x40008000UL
|
||||
#define OPAMP_BASE 0x40005880UL
|
||||
@@ -2758,6 +2844,7 @@ typedef struct { /*!< (@ 0x4000C800) LPTIM Struct
|
||||
#define ADC ((ADC_Type*) ADC_BASE)
|
||||
#define ADC0 ((ADC_Type*) ADC0_BASE)
|
||||
#define AMISC ((AMISC_Type*) AMISC_BASE)
|
||||
#define HWTRIM ((HWTRIM_Type*) HWTRIM_BASE)
|
||||
#define CRC ((CRC_Type*) CRC_BASE)
|
||||
#define DSP ((DSP_Type*) DSP_BASE)
|
||||
#define OPAMP ((OPAMP_Type*) OPAMP_BASE)
|
||||
@@ -4515,6 +4602,8 @@ typedef struct { /*!< (@ 0x4000C800) LPTIM Struct
|
||||
#define AMISC_DAC_CR_DAC1_EN_Pos (21UL) /*!< DAC1_EN (Bit 21) */
|
||||
#define AMISC_DAC_CR_DAC1_EN_Msk (0x200000UL) /*!< DAC1_EN (Bitfield-Mask: 0x01) */
|
||||
/* ======================================================== HSI_CR ========================================================= */
|
||||
#define AMISC_HSI_CR_LDO_SEL_Pos (0UL) /*!< LDO_SEL (Bit 0) */
|
||||
#define AMISC_HSI_CR_LDO_SEL_Msk (0xffffUL) /*!< LDO_SEL (Bitfield-Mask: 0xffff) */
|
||||
#define AMISC_HSI_CR_HSI_EN_Pos (24UL) /*!< HSI_EN (Bit 24) */
|
||||
#define AMISC_HSI_CR_HSI_EN_Msk (0xff000000UL) /*!< HSI_EN (Bitfield-Mask: 0xff) */
|
||||
/* ======================================================== LSI_CR ========================================================= */
|
||||
@@ -4525,6 +4614,35 @@ typedef struct { /*!< (@ 0x4000C800) LPTIM Struct
|
||||
#define AMISC_ADC_AIN_CR_ANA2ADC_EN_Msk (0x1UL) /*!< ANA2ADC_EN (Bitfield-Mask: 0x01) */
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ HWTRIM ================ */
|
||||
/* =========================================================================================================================== */
|
||||
|
||||
/* ======================================================= LDO_TRIM ======================================================== */
|
||||
#define HWTRIM_LDO_TRIM_LDO_TRIM_Pos (0UL) /*!< LDO_TRIM (Bit 0) */
|
||||
#define HWTRIM_LDO_TRIM_LDO_TRIM_Msk (0x1fUL) /*!< LDO_TRIM (Bitfield-Mask: 0x1f) */
|
||||
#define HWTRIM_LDO_TRIM_LDO_LP_TRIM_Pos (5UL) /*!< LDO_LP_TRIM (Bit 5) */
|
||||
#define HWTRIM_LDO_TRIM_LDO_LP_TRIM_Msk (0x3e0UL) /*!< LDO_LP_TRIM (Bitfield-Mask: 0x1f) */
|
||||
#define HWTRIM_LDO_TRIM_LDO_TUNE_Pos (10UL) /*!< LDO_TUNE (Bit 10) */
|
||||
#define HWTRIM_LDO_TRIM_LDO_TUNE_Msk (0xc00UL) /*!< LDO_TUNE (Bitfield-Mask: 0x03) */
|
||||
/* ======================================================= VBUF_TRIM ======================================================= */
|
||||
#define HWTRIM_VBUF_TRIM_VBUF_TRIM_Pos (0UL) /*!< VBUF_TRIM (Bit 0) */
|
||||
#define HWTRIM_VBUF_TRIM_VBUF_TRIM_Msk (0x7fUL) /*!< VBUF_TRIM (Bitfield-Mask: 0x7f) */
|
||||
/* ======================================================= HSI_TRIM ======================================================== */
|
||||
#define HWTRIM_HSI_TRIM_HSI_D_CFG_Pos (0UL) /*!< HSI_D_CFG (Bit 0) */
|
||||
#define HWTRIM_HSI_TRIM_HSI_D_CFG_Msk (0x1ffUL) /*!< HSI_D_CFG (Bitfield-Mask: 0x1ff) */
|
||||
#define HWTRIM_HSI_TRIM_HSI_FSEL_CFG_Pos (9UL) /*!< HSI_FSEL_CFG (Bit 9) */
|
||||
#define HWTRIM_HSI_TRIM_HSI_FSEL_CFG_Msk (0xfe00UL) /*!< HSI_FSEL_CFG (Bitfield-Mask: 0x7f) */
|
||||
#define HWTRIM_HSI_TRIM_HSI_TC_Pos (16UL) /*!< HSI_TC (Bit 16) */
|
||||
#define HWTRIM_HSI_TRIM_HSI_TC_Msk (0x30000UL) /*!< HSI_TC (Bitfield-Mask: 0x03) */
|
||||
/* ======================================================= LSI_TRIM ======================================================== */
|
||||
#define HWTRIM_LSI_TRIM_LSI_TRIM_Pos (0UL) /*!< LSI_TRIM (Bit 0) */
|
||||
#define HWTRIM_LSI_TRIM_LSI_TRIM_Msk (0xffUL) /*!< LSI_TRIM (Bitfield-Mask: 0xff) */
|
||||
/* ======================================================= MISC_CFG ======================================================== */
|
||||
#define HWTRIM_MISC_CFG_EXT_nRST_EN_Pos (0UL) /*!< EXT_nRST_EN (Bit 0) */
|
||||
#define HWTRIM_MISC_CFG_EXT_nRST_EN_Msk (0x1UL) /*!< EXT_nRST_EN (Bitfield-Mask: 0x01) */
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ CRC ================ */
|
||||
/* =========================================================================================================================== */
|
||||
@@ -4690,6 +4808,18 @@ typedef struct { /*!< (@ 0x4000C800) LPTIM Struct
|
||||
#define TIM_DIER_TIE_Msk (0x40UL) /*!< TIE (Bitfield-Mask: 0x01) */
|
||||
#define TIM_DIER_BIE_Pos (7UL) /*!< BIE (Bit 7) */
|
||||
#define TIM_DIER_BIE_Msk (0x80UL) /*!< BIE (Bitfield-Mask: 0x01) */
|
||||
#define TIM_DIER_CCD1IE_Pos (8UL) /*!< CCD1IE (Bit 8) */
|
||||
#define TIM_DIER_CCD1IE_Msk (0x100UL) /*!< CCD1IE (Bitfield-Mask: 0x01) */
|
||||
#define TIM_DIER_CCD2IE_Pos (9UL) /*!< CCD2IE (Bit 9) */
|
||||
#define TIM_DIER_CCD2IE_Msk (0x200UL) /*!< CCD2IE (Bitfield-Mask: 0x01) */
|
||||
#define TIM_DIER_CCD3IE_Pos (10UL) /*!< CCD3IE (Bit 10) */
|
||||
#define TIM_DIER_CCD3IE_Msk (0x400UL) /*!< CCD3IE (Bitfield-Mask: 0x01) */
|
||||
#define TIM_DIER_OVIE_Pos (11UL) /*!< OVIE (Bit 11) */
|
||||
#define TIM_DIER_OVIE_Msk (0x800UL) /*!< OVIE (Bitfield-Mask: 0x01) */
|
||||
#define TIM_DIER_UDIE_Pos (12UL) /*!< UDIE (Bit 12) */
|
||||
#define TIM_DIER_UDIE_Msk (0x1000UL) /*!< UDIE (Bitfield-Mask: 0x01) */
|
||||
#define TIM_DIER_CCD4IE_Pos (13UL) /*!< CCD4IE (Bit 13) */
|
||||
#define TIM_DIER_CCD4IE_Msk (0x2000UL) /*!< CCD4IE (Bitfield-Mask: 0x01) */
|
||||
/* ========================================================== SR =========================================================== */
|
||||
#define TIM_SR_UIF_Pos (0UL) /*!< UIF (Bit 0) */
|
||||
#define TIM_SR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */
|
||||
@@ -4715,6 +4845,18 @@ typedef struct { /*!< (@ 0x4000C800) LPTIM Struct
|
||||
#define TIM_SR_CC3OF_Msk (0x800UL) /*!< CC3OF (Bitfield-Mask: 0x01) */
|
||||
#define TIM_SR_CC4OF_Pos (12UL) /*!< CC4OF (Bit 12) */
|
||||
#define TIM_SR_CC4OF_Msk (0x1000UL) /*!< CC4OF (Bitfield-Mask: 0x01) */
|
||||
#define TIM_SR_CCD1IF_Pos (13UL) /*!< CCD1IF (Bit 13) */
|
||||
#define TIM_SR_CCD1IF_Msk (0x2000UL) /*!< CCD1IF (Bitfield-Mask: 0x01) */
|
||||
#define TIM_SR_CCD2IF_Pos (14UL) /*!< CCD2IF (Bit 14) */
|
||||
#define TIM_SR_CCD2IF_Msk (0x4000UL) /*!< CCD2IF (Bitfield-Mask: 0x01) */
|
||||
#define TIM_SR_CCD3IF_Pos (15UL) /*!< CCD3IF (Bit 15) */
|
||||
#define TIM_SR_CCD3IF_Msk (0x8000UL) /*!< CCD3IF (Bitfield-Mask: 0x01) */
|
||||
#define TIM_SR_OVIF_Pos (16UL) /*!< OVIF (Bit 16) */
|
||||
#define TIM_SR_OVIF_Msk (0x10000UL) /*!< OVIF (Bitfield-Mask: 0x01) */
|
||||
#define TIM_SR_UDIF_Pos (17UL) /*!< UDIF (Bit 17) */
|
||||
#define TIM_SR_UDIF_Msk (0x20000UL) /*!< UDIF (Bitfield-Mask: 0x01) */
|
||||
#define TIM_SR_CCD4IF_Pos (18UL) /*!< CCD4IF (Bit 18) */
|
||||
#define TIM_SR_CCD4IF_Msk (0x40000UL) /*!< CCD4IF (Bitfield-Mask: 0x01) */
|
||||
/* ========================================================== EGR ========================================================== */
|
||||
#define TIM_EGR_UG_Pos (0UL) /*!< UG (Bit 0) */
|
||||
#define TIM_EGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
|
||||
@@ -4875,14 +5017,17 @@ typedef struct { /*!< (@ 0x4000C800) LPTIM Struct
|
||||
#define TIM_BDTR_DTAE_Pos (24UL) /*!< DTAE (Bit 24) */
|
||||
#define TIM_BDTR_DTAE_Msk (0x1000000UL) /*!< DTAE (Bitfield-Mask: 0x01) */
|
||||
/* ========================================================= CCDR1 ========================================================= */
|
||||
#define TIM_CCDR1_CCR1_Pos (0UL) /*!< CCR1 (Bit 0) */
|
||||
#define TIM_CCDR1_CCR1_Msk (0xfffffUL) /*!< CCR1 (Bitfield-Mask: 0xfffff) */
|
||||
#define TIM_CCDR1_CCDR1_Pos (0UL) /*!< CCDR1 (Bit 0) */
|
||||
#define TIM_CCDR1_CCDR1_Msk (0xfffffUL) /*!< CCDR1 (Bitfield-Mask: 0xfffff) */
|
||||
/* ========================================================= CCDR2 ========================================================= */
|
||||
#define TIM_CCDR2_CCR2_Pos (0UL) /*!< CCR2 (Bit 0) */
|
||||
#define TIM_CCDR2_CCR2_Msk (0xfffffUL) /*!< CCR2 (Bitfield-Mask: 0xfffff) */
|
||||
#define TIM_CCDR2_CCDR2_Pos (0UL) /*!< CCDR2 (Bit 0) */
|
||||
#define TIM_CCDR2_CCDR2_Msk (0xfffffUL) /*!< CCDR2 (Bitfield-Mask: 0xfffff) */
|
||||
/* ========================================================= CCDR3 ========================================================= */
|
||||
#define TIM_CCDR3_CCR3_Pos (0UL) /*!< CCR3 (Bit 0) */
|
||||
#define TIM_CCDR3_CCR3_Msk (0xfffffUL) /*!< CCR3 (Bitfield-Mask: 0xfffff) */
|
||||
#define TIM_CCDR3_CCDR3_Pos (0UL) /*!< CCDR3 (Bit 0) */
|
||||
#define TIM_CCDR3_CCDR3_Msk (0xfffffUL) /*!< CCDR3 (Bitfield-Mask: 0xfffff) */
|
||||
/* ========================================================= CCDR4 ========================================================= */
|
||||
#define TIM_CCDR4_CCDR4_Pos (0UL) /*!< CCDR4 (Bit 0) */
|
||||
#define TIM_CCDR4_CCDR4_Msk (0xfffffUL) /*!< CCDR4 (Bitfield-Mask: 0xfffff) */
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
@@ -5642,10 +5787,35 @@ typedef enum { /*!< AMISC_VBUF_CR_ANA_SEL
|
||||
|
||||
/* ======================================================== DAC_CR ========================================================= */
|
||||
/* ======================================================== HSI_CR ========================================================= */
|
||||
/* ============================================= AMISC HSI_CR LDO_SEL [0..15] ============================================== */
|
||||
typedef enum { /*!< AMISC_HSI_CR_LDO_SEL */
|
||||
AMISC_HSI_CR_LDO_SEL_LDO = 32896, /*!< LDO : ldo_oschf Disable abd vddl_oschf from ldo */
|
||||
AMISC_HSI_CR_LDO_SEL_Normal = 257, /*!< Normal : do_oschf Enable and vddl_oschf from ldo_oschf */
|
||||
} AMISC_HSI_CR_LDO_SEL_Enum;
|
||||
|
||||
/* ======================================================== LSI_CR ========================================================= */
|
||||
/* ====================================================== ADC_AIN_CR ======================================================= */
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ HWTRIM ================ */
|
||||
/* =========================================================================================================================== */
|
||||
|
||||
/* ======================================================= LDO_TRIM ======================================================== */
|
||||
/* =========================================== HWTRIM LDO_TRIM LDO_TUNE [10..11] =========================================== */
|
||||
typedef enum { /*!< HWTRIM_LDO_TRIM_LDO_TUNE */
|
||||
HWTRIM_LDO_TRIM_LDO_TUNE_STRENGTH = 0, /*!< STRENGTH : strength */
|
||||
HWTRIM_LDO_TRIM_LDO_TUNE_WEAK = 1, /*!< WEAK : weak */
|
||||
HWTRIM_LDO_TRIM_LDO_TUNE_MIDDLEddle = 2, /*!< MIDDLEddle : middle */
|
||||
HWTRIM_LDO_TRIM_LDO_TUNE_OFF = 3, /*!< OFF : off */
|
||||
} HWTRIM_LDO_TRIM_LDO_TUNE_Enum;
|
||||
|
||||
/* ======================================================= VBUF_TRIM ======================================================= */
|
||||
/* ======================================================= HSI_TRIM ======================================================== */
|
||||
/* ======================================================= LSI_TRIM ======================================================== */
|
||||
/* ======================================================= MISC_CFG ======================================================== */
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ CRC ================ */
|
||||
/* =========================================================================================================================== */
|
||||
@@ -5858,6 +6028,7 @@ typedef enum { /*!< TIM_SMCR_ETF
|
||||
/* ========================================================= CCDR1 ========================================================= */
|
||||
/* ========================================================= CCDR2 ========================================================= */
|
||||
/* ========================================================= CCDR3 ========================================================= */
|
||||
/* ========================================================= CCDR4 ========================================================= */
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
@@ -5896,9 +6067,9 @@ typedef enum { /*!< LPTIM_TCR_TRIGSEL
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PB5700_H */
|
||||
#endif /* PEC930_H */
|
||||
|
||||
|
||||
/** @} */ /* End of group PB5700 */
|
||||
/** @} */ /* End of group PEC930 */
|
||||
|
||||
/** @} */ /* End of group Padauk-tech */
|
||||
@@ -154,14 +154,6 @@ typedef struct excp_frame
|
||||
uint32_t cause; /* cause: machine cause csr register */
|
||||
uint32_t epc; /* epc: machine exception program counter csr register */
|
||||
uint32_t msubm; /* msubm: machine sub-mode csr register, nuclei customized */
|
||||
#ifndef __riscv_32e
|
||||
uint32_t a6; /* a6: x16, function argument 6 */
|
||||
uint32_t a7; /* a7: x17, function argument 7 */
|
||||
uint32_t t3; /* t3: x28, temporary register 3 */
|
||||
uint32_t t4; /* t4: x29, temporary register 4 */
|
||||
uint32_t t5; /* t5: x30, temporary register 5 */
|
||||
uint32_t t6; /* t6: x31, temporary register 6 */
|
||||
#endif
|
||||
} excp_frame_t;
|
||||
|
||||
typedef struct sys_irq_attr
|
||||
+1
-5
@@ -50,6 +50,7 @@ _start:
|
||||
la sp, _sp
|
||||
|
||||
#if 0
|
||||
/* Disable/Enable ICE I/O */
|
||||
li a0, 0x00001C28
|
||||
li a1, 0x4000F804
|
||||
li a2, 0x80000000
|
||||
@@ -69,11 +70,6 @@ _start:
|
||||
2:
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Set the the NMI base mnvec to share
|
||||
* with mtvec by setting CSR_MMISC_CTL
|
||||
* bit 9 NMI_CAUSE_FFF to 1
|
||||
*/
|
||||
li t0, MMISC_CTL_NMI_CAUSE_FFF
|
||||
csrs CSR_MMISC_CTL, t0
|
||||
|
||||
@@ -11,7 +11,7 @@
|
||||
*/
|
||||
|
||||
|
||||
#include "pb57xx.h"
|
||||
#include "device.h"
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
@@ -116,22 +116,4 @@ const fp_isr_t __Vectors[__ECLIC_INTNUM] __USED __attribute__((section (".mintve
|
||||
default_handler, /* 31: ext_irq Reserved */
|
||||
default_handler, /* 32: ext_irq Reserved */
|
||||
default_handler, /* 33: ext_irq Reserved */
|
||||
#if 0
|
||||
default_handler, /* 34: ext_irq Reserved */
|
||||
default_handler, /* 35: ext_irq Reserved */
|
||||
default_handler, /* 36: ext_irq Reserved */
|
||||
default_handler, /* 37: ext_irq Reserved */
|
||||
default_handler, /* 38: ext_irq Reserved */
|
||||
default_handler, /* 39: ext_irq Reserved */
|
||||
default_handler, /* 40: ext_irq Reserved */
|
||||
default_handler, /* 41: ext_irq Reserved */
|
||||
default_handler, /* 42: ext_irq Reserved */
|
||||
default_handler, /* 43: ext_irq Reserved */
|
||||
default_handler, /* 44: ext_irq Reserved */
|
||||
default_handler, /* 45: ext_irq Reserved */
|
||||
default_handler, /* 46: ext_irq Reserved */
|
||||
default_handler, /* 47: ext_irq Reserved */
|
||||
default_handler, /* 48: ext_irq Reserved */
|
||||
default_handler, /* 49: ext_irq Reserved */
|
||||
#endif
|
||||
};
|
||||
@@ -197,18 +197,5 @@ __WEAK clock_t _times(struct tms *buf)
|
||||
|
||||
__WEAK void *_sbrk(ptrdiff_t incr)
|
||||
{
|
||||
#if 0
|
||||
extern char _end[];
|
||||
extern char _heap_end[];
|
||||
static char *curbrk = _end;
|
||||
|
||||
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) {
|
||||
return (void *)(-1);
|
||||
}
|
||||
|
||||
curbrk += incr;
|
||||
return (void *)(curbrk - incr);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
@@ -10,7 +10,7 @@
|
||||
* @description
|
||||
*/
|
||||
|
||||
#include "pb57xx.h"
|
||||
#include "device.h"
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
@@ -60,14 +60,14 @@ typedef enum ADC_Channels
|
||||
*/
|
||||
typedef enum ADC_SubChannel
|
||||
{
|
||||
ADC_SubChannel_NONE = AMISC_VBUF_CR_ANA_SEL_NONE,
|
||||
ADC_SubChannel_TEMP = AMISC_VBUF_CR_ANA_SEL_TEMP,
|
||||
ADC_SubChannel_DAC0 = AMISC_VBUF_CR_ANA_SEL_DAC0,
|
||||
ADC_SubChannel_DAC1 = AMISC_VBUF_CR_ANA_SEL_DAC1,
|
||||
ADC_SubChannel_VBuf_1_5 = AMISC_VBUF_CR_ANA_SEL_VBuf_1p5v,
|
||||
ADC_SubChannel_VDDL = AMISC_VBUF_CR_ANA_SEL_VDDL,
|
||||
ADC_SubChannel_VSS = AMISC_VBUF_CR_ANA_SEL_VSS,
|
||||
ADC_SubChannel_VDD = AMISC_VBUF_CR_ANA_SEL_VDD,
|
||||
ADC_SubChannel_NONE = (AMISC_VBUF_CR_ANA_SEL_NONE << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
ADC_SubChannel_TEMP = (AMISC_VBUF_CR_ANA_SEL_TEMP << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
ADC_SubChannel_DAC0 = (AMISC_VBUF_CR_ANA_SEL_DAC0 << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
ADC_SubChannel_DAC1 = (AMISC_VBUF_CR_ANA_SEL_DAC1 << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
ADC_SubChannel_VBuf_1_5 = (AMISC_VBUF_CR_ANA_SEL_VBuf_1p5v << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
ADC_SubChannel_VDDL = (AMISC_VBUF_CR_ANA_SEL_VDDL << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
ADC_SubChannel_VSS = (AMISC_VBUF_CR_ANA_SEL_VSS << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
ADC_SubChannel_VDD = (AMISC_VBUF_CR_ANA_SEL_VDD << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
} ADC_SubChannelTypeDef;
|
||||
|
||||
/**
|
||||
@@ -132,8 +132,8 @@ typedef enum ADC_ExtTrigSource
|
||||
ADC_ExtTrigSource_EPWM_CH2F = ADC_ExtTrigSource_04, /*!< ADC external source trigger from EPWM CH2 Falling */
|
||||
ADC_ExtTrigSource_EPWM_CH3F = ADC_ExtTrigSource_05, /*!< ADC external source trigger from EPWM CH3 Falling */
|
||||
ADC_ExtTrigSource_COMP0_Rise = ADC_ExtTrigSource_06, /*!< ADC external source trigger from COMP0 Rising */
|
||||
ADC_ExtTrigSource_COMP1_Rise = ADC_ExtTrigSource_07, /*!< ADC external source trigger from COMP1 Rising */
|
||||
ADC_ExtTrigSource_COMP0_Fall = ADC_ExtTrigSource_08, /*!< ADC external source trigger from COMP0 Falling */
|
||||
ADC_ExtTrigSource_COMP1_Rise = ADC_ExtTrigSource_08, /*!< ADC external source trigger from COMP1 Rising */
|
||||
ADC_ExtTrigSource_COMP0_Fall = ADC_ExtTrigSource_07, /*!< ADC external source trigger from COMP0 Falling */
|
||||
ADC_ExtTrigSource_COMP1_Fall = ADC_ExtTrigSource_09, /*!< ADC external source trigger from COMP1 Falling */
|
||||
ADC_ExtTrigSource_EPWM_UDF = ADC_ExtTrigSource_10, /*!< ADC external source trigger from EPWM Counter UDF */
|
||||
ADC_ExtTrigSource_EPWM_OVF = ADC_ExtTrigSource_11, /*!< ADC external source trigger from EPWM Counter OVF */
|
||||
@@ -182,6 +182,7 @@ typedef enum ADC_IT
|
||||
*/
|
||||
typedef enum ADC_ITStatus
|
||||
{
|
||||
ADC_ITStatus_None = (ADC_STAT_COMP_RESULT_NONE << ADC_STAT_COMP_RESULT_Pos),
|
||||
ADC_ITStatus_LowerThreshold = (ADC_STAT_COMP_RESULT_LT_THR << ADC_STAT_COMP_RESULT_Pos),
|
||||
ADC_ITStatus_HigherThreshold = (ADC_STAT_COMP_RESULT_GT_THR << ADC_STAT_COMP_RESULT_Pos),
|
||||
ADC_ITStatus_EqualThreshold = (ADC_STAT_COMP_RESULT_EQ_THR << ADC_STAT_COMP_RESULT_Pos),
|
||||
@@ -247,7 +248,7 @@ __STATIC_FORCEINLINE void ADC_Start(ADC_Type *pHADC)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t ADC_IsIdle(ADC_Type *pHADC)
|
||||
{
|
||||
return REG_READ_MASK(pHADC->CON0, ADC_STAT_DONE_Msk);
|
||||
return REG_READ_MASK(pHADC->STAT, ADC_STAT_DONE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -286,7 +287,7 @@ __STATIC_FORCEINLINE void ADC_ClearITFlag(ADC_Type *pHADC)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void ADC_DiscMode_SetGroupSubsetNum(ADC_Type *pHADC, uint8_t subset_ch_num)
|
||||
{
|
||||
REG_WRITE_MASK(pHADC->CHSEL, ADC_CHSEL_DISCNUM_Msk, subset_ch_num - 1);
|
||||
REG_WRITE_MASK(pHADC->CHSEL, ADC_CHSEL_DISCNUM_Msk, (subset_ch_num - 1) << ADC_CHSEL_DISCNUM_Pos);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -333,19 +334,22 @@ __STATIC_FORCEINLINE uint16_t ADC_GetBakcupValue(ADC_Type *pHADC)
|
||||
return (uint16_t)pHADC->BAKDAT_b.BAKDAT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Select the sub-channel of the ADC Channel-15
|
||||
* \brief Set the sample-period of an ADC
|
||||
*
|
||||
* \param [in] subchannel The selected sub-channel of ADC channel-15, @ref ADC_SubChannelTypeDef
|
||||
* \param [in] pHADC Pointer to an ADC handler
|
||||
* \param [in] cycles extern cycles (range: 0 ~ 31, default: 3)
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void ADC_SelSubChannel(ADC_SubChannelTypeDef subchannel)
|
||||
__STATIC_FORCEINLINE void ADC_SetSampleCycles(ADC_Type *pHADC, uint8_t cycles)
|
||||
{
|
||||
REG_WRITE_MASK(AMISC->VBUF_CR, AMISC_VBUF_CR_ANA_SEL_Msk, subchannel);
|
||||
pHADC->STAT_b.TS_SET = cycles;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Get the conversion value of the ADC in ISR
|
||||
*
|
||||
@@ -364,6 +368,19 @@ __STATIC_FORCEINLINE uint16_t ADC_ITGetConvValue(ADC_Type *pHADC, ADC_ChannelsTy
|
||||
return (uint16_t)((*pData) & 0xFFFFul);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable interrupt of ADC
|
||||
*
|
||||
* \param [in] pHADC Pointer to an ADC handler
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void ADC_ITDisable(ADC_Type *pHADC)
|
||||
{
|
||||
REG_WRITE_MASK(pHADC->CON0, ADC_CON0_INT_EN_Msk, ADC_IT_DISABLE);
|
||||
return;
|
||||
}
|
||||
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
@@ -442,6 +459,15 @@ void ADC_StructInit(ADC_InitTypeDef *pInit);
|
||||
*/
|
||||
void ADC_ExtTrigConfig(ADC_Type *pHADC, ADC_ExtTrigSourceTypeDef ext_src, ADC_ExtTrigModeTypeDef trig_mode);
|
||||
|
||||
/**
|
||||
* \brief Select the sub-channel of the ADC Channel-15
|
||||
*
|
||||
* \param [in] subchannel The selected sub-channel of ADC channel-15, @ref ADC_SubChannelTypeDef
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void ADC_SelSubChannel(ADC_SubChannelTypeDef subchannel);
|
||||
|
||||
/**
|
||||
* \brief Get the conversion value of an ADC channel
|
||||
*
|
||||
@@ -65,31 +65,22 @@ typedef enum
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AMISC_Ana2IO_Disable = 0x0, //AMISC_Ana2IO_En
|
||||
AMISC_Ana2IO_En = AMISC_VBUF_CR_ANA2IO_EN_Msk,
|
||||
|
||||
} AMISC_Ana2IOTypeDef;
|
||||
AMISC_InternalSrc_NONE = (AMISC_VBUF_CR_ANA_SEL_NONE << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
AMISC_InternalSrc_TEMP = (AMISC_VBUF_CR_ANA_SEL_TEMP << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
AMISC_InternalSrc_DAC0 = (AMISC_VBUF_CR_ANA_SEL_DAC0 << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
AMISC_InternalSrc_DAC1 = (AMISC_VBUF_CR_ANA_SEL_DAC1 << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
AMISC_InternalSrc_VBuf_1P5V = (AMISC_VBUF_CR_ANA_SEL_VBuf_1p5v << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
AMISC_InternalSrc_VDDL = (AMISC_VBUF_CR_ANA_SEL_VDDL << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
AMISC_InternalSrc_VSS = (AMISC_VBUF_CR_ANA_SEL_VSS << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
AMISC_InternalSrc_VDD = (AMISC_VBUF_CR_ANA_SEL_VDD << AMISC_VBUF_CR_ANA_SEL_Pos),
|
||||
} AMISC_InternalSrcTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AMISC_Ana2PGA_Disable = 0x0, // AMISC_Ana2PGA_En
|
||||
AMISC_Ana2PGA_Ene = AMISC_VBUF_CR_ANA2PGA_EN_Msk ,
|
||||
|
||||
} AMISC_Ana2PGATypeDef ;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AMISC_AnaSel_temp = 0x1 << AMISC_VBUF_CR_ANA_SEL_Pos,
|
||||
AMISC_AnaSel_dac0 = 0x2 << AMISC_VBUF_CR_ANA_SEL_Pos,
|
||||
AMISC_AnaSel_dac1 = 0x4 << AMISC_VBUF_CR_ANA_SEL_Pos,
|
||||
AMISC_AnaSel_1p5v = 0x8 << AMISC_VBUF_CR_ANA_SEL_Pos,
|
||||
AMISC_AnaSel_vddl = 0x10 << AMISC_VBUF_CR_ANA_SEL_Pos,
|
||||
AMISC_AnaSel_vss = 0x20 << AMISC_VBUF_CR_ANA_SEL_Pos,
|
||||
AMISC_AnaSel_v = 0x40 << AMISC_VBUF_CR_ANA_SEL_Pos,
|
||||
|
||||
} AMISC_AnaSelTypeDef ;
|
||||
|
||||
AMISC_HSIPwrSrc_Normal = (AMISC_HSI_CR_LDO_SEL_Normal << AMISC_HSI_CR_LDO_SEL_Pos),
|
||||
AMISC_HSIPwrSrc_LowPower = (AMISC_HSI_CR_LDO_SEL_LDO << AMISC_HSI_CR_LDO_SEL_Pos),
|
||||
|
||||
} AMISC_HSIPwrSrcTypeDef;
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
@@ -244,6 +235,17 @@ __STATIC_FORCEINLINE void AMISC_LVD_ITDisable(void)
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get the status of LVD
|
||||
*
|
||||
* \return
|
||||
* The new state of flags (SET or RESET)
|
||||
*/
|
||||
__STATIC_FORCEINLINE FlagStatus AMISC_LVD_GetFlagStatus(void)
|
||||
{
|
||||
return REG_READ_MASK(AMISC->LVD_LVR_CR, AMISC_LVD_LVR_CR_LVD_STATE_Msk) ? SET : RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable VBUF
|
||||
*
|
||||
@@ -270,8 +272,18 @@ __STATIC_FORCEINLINE void AMISC_Vbuf_Disable(void)
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Set the power source of HSI
|
||||
*
|
||||
* \param [in] pwr_src The target power source, @ref AMISC_HSIPwrSrcTypeDef
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void AMISC_SetHSIPwrSrc(AMISC_HSIPwrSrcTypeDef pwr_src)
|
||||
{
|
||||
REG_WRITE_MASK(AMISC->HSI_CR, AMISC_HSI_CR_LDO_SEL_Msk, pwr_src);
|
||||
return;
|
||||
}
|
||||
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
@@ -283,16 +295,6 @@ typedef struct
|
||||
AMISC_LVDFuncTypeDef LVD_FuncModes;
|
||||
|
||||
} AMISC_LVDRInitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
AMISC_Ana2IOTypeDef Ana2IOT;
|
||||
AMISC_Ana2PGATypeDef Ana2PGA;
|
||||
AMISC_AnaSelTypeDef AnaSel;
|
||||
|
||||
} AMISC_VBUFConfigTypeDef;
|
||||
|
||||
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
@@ -373,12 +375,25 @@ void AMISC_LSI_Disable(void);
|
||||
*/
|
||||
void AMISC_LSI_Enable(void);
|
||||
|
||||
|
||||
void AMISC_VBUF_Config(AMISC_VBUFConfigTypeDef *pInit);
|
||||
|
||||
|
||||
/**
|
||||
* \brief Select the VinP internal source of PGA
|
||||
*
|
||||
* \param [in] src_type the target VinP internal source
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void AMISC_Sel_PGA_VinP_Src(AMISC_InternalSrcTypeDef src_type);
|
||||
|
||||
|
||||
/**
|
||||
* \brief Output the internal signals to I/O Pin
|
||||
*
|
||||
* \param [in] src_type The target internal signal, @ref AMISC_InternalSrcTypeDef
|
||||
* \param [in] has_output Enable output or not
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void AMISC_OutInternalSignalToIO(AMISC_InternalSrcTypeDef src_type, int has_output);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
@@ -1,27 +1,29 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file isr.h
|
||||
/** @file hal_comp.h
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/09/16
|
||||
* @date 2024/10/17
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
#ifndef __isr_H_wuraIpBA_lTJm_HvJw_sNDo_uEd5JnucTReY__
|
||||
#define __isr_H_wuraIpBA_lTJm_HvJw_sNDo_uEd5JnucTReY__
|
||||
#ifndef __hal_comp_H_wqqzibVO_lvKI_HWdK_sROD_uhjcZz7SHMtL__
|
||||
#define __hal_comp_H_wqqzibVO_lvKI_HWdK_sROD_uhjcZz7SHMtL__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "main.h"
|
||||
|
||||
#include "hal_def.h"
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
|
||||
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
@@ -43,7 +45,6 @@ extern "C" {
|
||||
//=============================================================================
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -18,7 +18,7 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#include "pb57xx.h"
|
||||
#include "device.h"
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
@@ -80,6 +80,24 @@ __STATIC_FORCEINLINE uint32_t HAL_GetUID3(void)
|
||||
{
|
||||
return REG_READ(UID->UID3);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initialize the peripherals of this device
|
||||
*
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void HAL_DeviceInit(void)
|
||||
{
|
||||
REG_WRITE(SYSCFG->PRSTEN1, 0xFFFFFFFFul);
|
||||
REG_WRITE(SYSCFG->PRSTEN, 0xFFFFFFFFul);
|
||||
REG_WRITE(SYSCFG->PRSTEN1, 0x0ul);
|
||||
REG_WRITE(SYSCFG->PRSTEN, 0x0ul);
|
||||
return;
|
||||
}
|
||||
|
||||
#define HAL_SetBits(_val_, _bit_mak_) REG_SET_BITS(_val_, _bit_mak_)
|
||||
#define HAL_ClearBits(_val_, _bit_mak_) REG_CLR_BITS(_val_, _bit_mak_)
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
@@ -112,6 +130,7 @@ void HAL_SRand(uint32_t seed);
|
||||
*/
|
||||
uint32_t HAL_Rand(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -33,10 +33,11 @@ typedef enum
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_ANAL, /*!< GPIO Analog In/Out Mode */
|
||||
GPIO_Mode_AF, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_ANAL, /*!< GPIO Analog In/Out Mode */
|
||||
GPIO_Mode_AF, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_PWR_Saving, /*!< GPIO Power-Saving Mode */
|
||||
|
||||
} GPIO_ModeTypeDef;
|
||||
|
||||
@@ -377,6 +378,17 @@ typedef struct GPIO_Init
|
||||
*/
|
||||
int GPIO_Init(GPIO_Type *pHGpio, GPIO_InitTypeDef *pInit);
|
||||
|
||||
/**
|
||||
* \brief De-initializes the gpio peripheral according to the specified parameters.
|
||||
*
|
||||
* \param [in] pHGpio Pointer to a GPIO handler
|
||||
* \param [in] pins The target pin, @ref GPIO_PinTypeDef
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_Type *pHGpio, uint32_t pins);
|
||||
|
||||
|
||||
/**
|
||||
* \brief Set Pin configuration of Peripheral IP with the specific Alternate Function
|
||||
*
|
||||
@@ -0,0 +1,333 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file hal_i2c.h
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/09/10
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
#ifndef __hal_i2c_H_wiTQLukR_lyWI_H9X1_s634_uL7YYZQ9qyOX__
|
||||
#define __hal_i2c_H_wiTQLukR_lyWI_H9X1_s634_uL7YYZQ9qyOX__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#include "hal_def.h"
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
#define I2C_BLOCKING 0xFFFF
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_Err_OK = 0,
|
||||
I2C_Err_Fail,
|
||||
I2C_Err_WrongParams,
|
||||
I2C_Err_TimeOut,
|
||||
|
||||
} I2C_ErrTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/* Misc */
|
||||
I2C_State_ERROR = 0x00u,
|
||||
I2C_State_BUS_IDLE = 0xF8u,
|
||||
I2C_State_SLAVE_STOP_RESTART = 0xA0u,
|
||||
|
||||
/* Master Transmit */
|
||||
I2C_State_MASTER_TX_START = 0x08u,
|
||||
I2C_State_MASTER_TX_RESTART = 0x10u,
|
||||
I2C_State_MASTER_TX_SLAW_ACK = 0x18u, // Master sent (SlaveAddress + W-bit) and received ACK
|
||||
I2C_State_MASTER_TX_SLAW_NOACK = 0x20u,
|
||||
I2C_State_MASTER_TX_DATA_ACK = 0x28u, // Master sent data and received ACK
|
||||
I2C_State_MASTER_TX_DATA_NOACK = 0x30u,
|
||||
I2C_State_MASTER_TX_LOST_BUS = 0x38u,
|
||||
|
||||
/* Master Receive */
|
||||
I2C_State_MASTER_RX_START = I2C_State_MASTER_TX_START,
|
||||
I2C_State_MASTER_RX_RESTART = I2C_State_MASTER_TX_RESTART,
|
||||
I2C_State_MASTER_RX_SLAR_ACK = 0x40u, // Master sent (SlaveAddress + R-bit) and received ACK
|
||||
I2C_State_MASTER_RX_SLAR_NOACK = 0x48u,
|
||||
I2C_State_MASTER_RX_DATA_ACK = 0x50u, // Master received data and received ACK
|
||||
I2C_State_MASTER_RX_DATA_NOACK = 0x58u,
|
||||
I2C_State_MASTER_RX_LOST_BUS = I2C_State_MASTER_TX_LOST_BUS,
|
||||
|
||||
/* Slave Receive */
|
||||
I2C_State_SLAVE_RX_SLAW_ACK = 0x60u,
|
||||
I2C_State_SLAVE_RX_SLAW_LOST_BUS = 0x68u,
|
||||
I2C_State_SLAVE_RX_BROAD_ACK = 0x70u, // received broad address and sent ACK
|
||||
I2C_State_SLAVE_RX_BADDR_LOST_BUS = 0x78u,
|
||||
I2C_State_SLAVE_RX_DATA_ACK = 0x80u, // received data and sent ACK
|
||||
I2C_State_SLAVE_RX_DATA_NOACK = 0x88u,
|
||||
I2C_State_SLAVE_RX_BDATA_ACK = 0x90u, // received data (with broad address) and sent ACK
|
||||
I2C_State_SLAVE_RX_BDATA_NOACK = 0x98u,
|
||||
|
||||
/* Slave Transmit */
|
||||
I2C_State_SLAVE_RX_SLAR_ACK = 0xA8u,
|
||||
I2C_State_SLAVE_TX_LOST_BUS = 0xB0u,
|
||||
I2C_State_SLAVE_TX_DATA_ACK = 0xB8u,
|
||||
I2C_State_SLAVE_TX_DATA_NOACK = 0xC0u,
|
||||
I2C_State_SLAVE_TX_LAST_DATA = 0xC8u,
|
||||
|
||||
} I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* I2C role mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_Mode_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
I2C_Mode_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
I2C_Mode_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
} I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* The divide of I2C Clock
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_CLK_Div60 = 60,
|
||||
I2C_CLK_Div120 = 120,
|
||||
I2C_CLK_Div160 = 160,
|
||||
I2C_CLK_Div192 = 192,
|
||||
I2C_CLK_Div244 = 244,
|
||||
I2C_CLK_Div256 = 256,
|
||||
I2C_CLK_Div960 = 960,
|
||||
|
||||
} I2C_Clk_DivTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_BroadAck_Disable = 0x0ul,
|
||||
I2C_BroadAck_Enable = I2C_ADDR_GC_Msk,
|
||||
} I2C_BroadAckTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_XferMode_Idle = 0,
|
||||
I2C_XferMode_Transmite,
|
||||
I2C_XferMode_Recevie,
|
||||
} I2C_XferModeTypeDef;
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
/**
|
||||
* \brief Get the Hardware state of an I2C
|
||||
*
|
||||
* \param [in] pHI2C The handle of I2C
|
||||
* \return
|
||||
* Hardware state
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t I2C_GetHwState(I2C_Type *pHI2C)
|
||||
{
|
||||
return pHI2C->STAT_b.STAT;
|
||||
}
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
/**
|
||||
* I2C Initial Configuration
|
||||
*/
|
||||
typedef struct I2C_Init
|
||||
{
|
||||
I2C_Clk_DivTypeDef ClockDiv;
|
||||
I2C_ModeTypeDef Mode; /*!< Specifies the I2C mode. This parameter can be a value of I2C_mode. */
|
||||
uint8_t OwnAddress; /*!< Specifies the first device own address. This parameter can be a 7-bit address. */
|
||||
I2C_BroadAckTypeDef BroadAck; /*!< ACK enable or disable when as slave.
|
||||
This parameter can be a value of @ref I2C_BroadAckTypeDef */
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
typedef struct I2C_IT_Handle
|
||||
{
|
||||
I2C_Type *pHI2C;
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to I2C Tx transfer Buffer */
|
||||
__IO uint16_t TxXferCount; /*!< I2C Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to I2C Rx transfer Buffer */
|
||||
__IO uint16_t RxXferCount; /*!< I2C Rx Transfer Counter */
|
||||
|
||||
I2C_XferModeTypeDef XferMode;
|
||||
__IO uint16_t DevAddress; /*!< I2C Target device address */
|
||||
|
||||
} I2C_IT_HandleTypeDef;
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
/**
|
||||
* \brief Fills each init_struct member with its default value.
|
||||
*
|
||||
* \param [in] pInit Pointer to an I2C_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void I2C_StructInit(I2C_InitTypeDef *pInit);
|
||||
|
||||
/**
|
||||
* \brief Initializes the I2C module
|
||||
*
|
||||
* \param [in] pHI2C Pointer to an I2C handler
|
||||
* \param [in] pInit Pointer to an I2C_InitTypeDef structure that
|
||||
* contains the configuration information for the specified
|
||||
* I2C peripheral
|
||||
* \return
|
||||
* error code, @ref I2C_ErrTypeDef
|
||||
*/
|
||||
I2C_ErrTypeDef I2C_Init(I2C_Type *pHI2C, I2C_InitTypeDef *pInit);
|
||||
|
||||
/**
|
||||
* \brief De-Initializes the I2C peripheral registers to their default values.
|
||||
*
|
||||
* \param [in] pHI2C Pointer to an I2C handler
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void I2C_DeInit(I2C_Type *pHI2C);
|
||||
|
||||
/**
|
||||
* \brief I2C-Master transmits an amount of data in blocking mode.
|
||||
*
|
||||
* \param [in] pHI2C Pointer to an I2C handler
|
||||
* \param [in] DevAddr Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* \param [in] pData Pointer to data buffer
|
||||
* \param [in] Size Amount of data to be sent
|
||||
* \return
|
||||
* error code, @ref I2C_ErrTypeDef
|
||||
*/
|
||||
I2C_ErrTypeDef I2C_Master_Transmit(I2C_Type *pHI2C, uint16_t DevAddr, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/**
|
||||
* \brief I2C-Master receives an amount of data in blocking mode.
|
||||
*
|
||||
* \param [in] pHI2C Pointer to an I2C handler
|
||||
* \param [in] DevAddr Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* \param [in] pData Pointer to data buffer
|
||||
* \param [in] pSize Amount of data to be received
|
||||
* \param [in] Timeout_ms Timeout with mseconds. If Timeout_ms == I2C_BLOCKING, slave transmit with blocking mode
|
||||
* \return
|
||||
* error code, @ref I2C_ErrTypeDef
|
||||
*/
|
||||
I2C_ErrTypeDef I2C_Master_Receive(I2C_Type *pHI2C, uint8_t DevAddr, uint8_t *pData, uint16_t *pSize, uint16_t Timeout_ms);
|
||||
|
||||
|
||||
/**
|
||||
* \brief I2C-Slave Transmit data in blocking mode
|
||||
*
|
||||
* \param [in] pHI2C Pointer to an I2C handler
|
||||
* \param [in] pData Pointer to data buffer
|
||||
* \param [in] Size Amount of data to be sent
|
||||
* \param [in] Timeout_ms Timeout with mseconds. If Timeout_ms == I2C_BLOCKING, slave transmit with blocking mode
|
||||
* \return
|
||||
* error code, @ref I2C_ErrTypeDef
|
||||
*/
|
||||
I2C_ErrTypeDef I2C_Slave_Transmit(I2C_Type *pHI2C, uint8_t *pData, uint16_t Size, uint16_t Timeout_ms);
|
||||
|
||||
/**
|
||||
* \brief I2C-Slave Receive data in blocking mode
|
||||
*
|
||||
* \param [in] pHI2C Pointer to an I2C handler
|
||||
* \param [in] pData Pointer to data buffer
|
||||
* \param [in] pSize Amount of data to be received
|
||||
* \param [in] Timeout_ms Timeout with mseconds. If Timeout_ms == I2C_BLOCKING, slave transmit with blocking mode
|
||||
* \return
|
||||
* error code, @ref I2C_ErrTypeDef
|
||||
*/
|
||||
I2C_ErrTypeDef I2C_Slave_Receive(I2C_Type *pHI2C, uint8_t *pData, uint16_t *pSize, uint16_t Timeout_ms);
|
||||
|
||||
/**
|
||||
* \brief I2C-Master transmits an amount of data in interrupt mode.
|
||||
*
|
||||
* \param [in] pHITI2C Pointer to an I2C IT handler, @ref I2C_IT_HandleTypeDef
|
||||
* \param [in] DevAddr Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* \param [in] pData Pointer to data buffer
|
||||
* \param [in] Size Amount of data to be sent
|
||||
* \return
|
||||
* error code, @ref I2C_ErrTypeDef
|
||||
*/
|
||||
I2C_ErrTypeDef I2C_Master_Transmit_IT(I2C_IT_HandleTypeDef *pHITI2C, uint16_t DevAddr, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/**
|
||||
* \brief I2C-Master receives an amount of data in interrupt mode.
|
||||
*
|
||||
* \param [in] pHITI2C Pointer to an I2C IT handler, @ref I2C_IT_HandleTypeDef
|
||||
* \param [in] DevAddr Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* \param [in] pData Pointer to data buffer
|
||||
* \param [in] Size Amount of data to be received
|
||||
* \return
|
||||
* error code, @ref I2C_ErrTypeDef
|
||||
*/
|
||||
I2C_ErrTypeDef I2C_Master_Receive_IT(I2C_IT_HandleTypeDef *pHITI2C, uint8_t DevAddr, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/**
|
||||
* \brief I2C-Slave Transmit data in interrupt mode
|
||||
*
|
||||
* \param [in] pHITI2C Pointer to an I2C IT handler, @ref I2C_IT_HandleTypeDef
|
||||
* \param [in] pData Pointer to data buffer
|
||||
* \param [in] Size Amount of data to be sent
|
||||
* \return
|
||||
* error code, @ref I2C_ErrTypeDef
|
||||
*/
|
||||
I2C_ErrTypeDef I2C_Slave_Transmit_IT(I2C_IT_HandleTypeDef *pHITI2C, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/**
|
||||
* \brief I2C-Slave Receive data in interrupt mode
|
||||
*
|
||||
* \param [in] pHITI2C Pointer to an I2C IT handler, @ref I2C_IT_HandleTypeDef
|
||||
* \param [in] pData Pointer to data buffer
|
||||
* \param [in] Size Amount of data to be received
|
||||
* \return
|
||||
* error code, @ref I2C_ErrTypeDef
|
||||
*/
|
||||
I2C_ErrTypeDef I2C_Slave_Receive_IT(I2C_IT_HandleTypeDef *pHITI2C, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/**
|
||||
* \brief This function handles I2C-Master interrupt request.
|
||||
*
|
||||
* \param [in] pHITI2C Pointer to an I2C IT Handler, @ref I2C_IT_HandleTypeDef
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void I2C_Master_IRQHandler(I2C_IT_HandleTypeDef *pHITI2C);
|
||||
|
||||
/**
|
||||
* \brief This function handles I2C-Slave interrupt request.
|
||||
*
|
||||
* \param [in] pHITI2C Pointer to an I2C IT Handler, @ref I2C_IT_HandleTypeDef
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void I2C_Slave_IRQHandler(I2C_IT_HandleTypeDef *pHITI2C);
|
||||
|
||||
#if 0
|
||||
/* Callback when xfer completion with interrupt */
|
||||
void I2C_MasterTxCmpltCallback(I2C_IT_HandleTypeDef *pHITI2C);
|
||||
void I2C_SlaveTxCmpltCallback(I2C_IT_HandleTypeDef *pHITI2C);
|
||||
void I2C_MasterRxCmpltCallback(I2C_IT_HandleTypeDef *pHITI2C);
|
||||
void I2C_SlaveRxCmpltCallback(I2C_IT_HandleTypeDef *pHITI2C);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -27,6 +27,7 @@ extern "C" {
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
OPAMP_PGAGain_Ext = (0x00 << OPAMP_PGA_CR_PGA_GAIN_Pos),
|
||||
OPAMP_PGAGain_1 = (OPAMP_PGA_CR_PGA_GAIN_x1 << OPAMP_PGA_CR_PGA_GAIN_Pos),
|
||||
OPAMP_PGAGain_2 = (OPAMP_PGA_CR_PGA_GAIN_x2 << OPAMP_PGA_CR_PGA_GAIN_Pos),
|
||||
OPAMP_PGAGain_3 = (OPAMP_PGA_CR_PGA_GAIN_x3 << OPAMP_PGA_CR_PGA_GAIN_Pos),
|
||||
@@ -22,6 +22,9 @@ extern "C" {
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
/**
|
||||
* Power mode type
|
||||
*/
|
||||
typedef enum PWR_Mode
|
||||
{
|
||||
PWR_Mode_Sleep = 0,
|
||||
@@ -29,18 +32,36 @@ typedef enum PWR_Mode
|
||||
|
||||
} PWR_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* The wake-up type of power mode
|
||||
*/
|
||||
typedef enum PWR_Wakeup
|
||||
{
|
||||
PWR_Wakeup_IO_PORT_A = (0x1ul << 0),
|
||||
PWR_Wakeup_IO_PORT_B = (0x1ul << 1),
|
||||
PWR_Wakeup_LpTIM = (0x1ul << 2),
|
||||
PWR_Wakeup_WDG = (0x1ul << 3),
|
||||
|
||||
} PWR_WakeupTypeDef;
|
||||
|
||||
/**
|
||||
* \brief Set a peripheral before entering deep-sleep
|
||||
* \brief Set the peripheral before entering power mode
|
||||
*
|
||||
* \param [in] pwr_mode the target power mode, @ref PWR_ModeTypeDef
|
||||
* \param [in] pWakeup_type provide the target wake-up module from App level
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
typedef void (*CallbaskPreDeepsleepTypeDef)(void);
|
||||
typedef void (*CallbaskPreSleepTypeDef)(PWR_ModeTypeDef pwr_mode, PWR_WakeupTypeDef *pWakeup_type);
|
||||
|
||||
/**
|
||||
* \brief Set a peripheral after deep-sleep wake-up
|
||||
* ps. This callback function ONLY supports to set ONE peripheral
|
||||
* \brief Set the peripheral after power mode wake-up
|
||||
*
|
||||
* \param [in] pwr_mode the target power mode, @ref PWR_ModeTypeDef
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
typedef void (*CallbaskPostDeepsleepTypeDef)(void);
|
||||
typedef void (*CallbaskPostSleepTypeDef)(PWR_ModeTypeDef pwr_mode);
|
||||
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
@@ -61,25 +82,16 @@ typedef void (*CallbaskPostDeepsleepTypeDef)(void);
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
/**
|
||||
* @brief Set duration of auto wake-up
|
||||
*
|
||||
* @param [in] msec the duration of auto wakeup from sleep/deepsleep mode
|
||||
* @return
|
||||
* None
|
||||
*/
|
||||
void PWR_SetAutoWakeUp(uint32_t msec);
|
||||
|
||||
/**
|
||||
* \brief Enters Sleep mode
|
||||
*
|
||||
* @param [in] cb_pre_set_clk Set peripheral BEFORE entering deepsleep
|
||||
* @param [in] cb_post_set_clk Set peripheral AFTER wake-up from deepsleep
|
||||
* @param [in] cb_pre_set_clk Set peripheral BEFORE entering sleep
|
||||
* @param [in] cb_post_set_clk Set peripheral AFTER wake-up from sleep
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void PWR_EnterSleepMode(CallbaskPreDeepsleepTypeDef cb_pre_set,
|
||||
CallbaskPostDeepsleepTypeDef cb_post_set);
|
||||
void PWR_EnterSleepMode(CallbaskPreSleepTypeDef cb_pre_set,
|
||||
CallbaskPostSleepTypeDef cb_post_set);
|
||||
|
||||
|
||||
/**
|
||||
@@ -90,8 +102,8 @@ void PWR_EnterSleepMode(CallbaskPreDeepsleepTypeDef cb_pre_set,
|
||||
* @return
|
||||
* None
|
||||
*/
|
||||
void PWR_EnterDeepSleepMode(CallbaskPreDeepsleepTypeDef cb_pre_set,
|
||||
CallbaskPostDeepsleepTypeDef cb_post_set);
|
||||
void PWR_EnterDeepSleepMode(CallbaskPreSleepTypeDef cb_pre_set,
|
||||
CallbaskPostSleepTypeDef cb_post_set);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
@@ -364,17 +364,17 @@ __STATIC_FORCEINLINE uint32_t SYSCFG_GetChipID(void)
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Configure the Alternate Function mode of Reset-Pin
|
||||
* \brief Configure Reset-Pin to normal I/O or not
|
||||
*
|
||||
* \param [in] has_rst_pin Enable Reset-Pin function or not
|
||||
* \param [in] is_enable Set Reset-Pin to normal I/O or not
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SYSCFG_SetRstPinAF(int has_rst_pin)
|
||||
__STATIC_FORCEINLINE void SYSCFG_SetRstPin2NormalIO(int is_enable)
|
||||
{
|
||||
(has_rst_pin)
|
||||
? REG_WRITE_MASK(SYSCFG->RSTPINCR, SYSCFG_RSTPINCR_RSTPINAF_Msk, SYSCFG_RSTPINCR_RSTPINAF_ON << SYSCFG_RSTPINCR_RSTPINAF_Pos)
|
||||
: REG_WRITE_MASK(SYSCFG->RSTPINCR, SYSCFG_RSTPINCR_RSTPINAF_Msk, SYSCFG_RSTPINCR_RSTPINAF_OFF << SYSCFG_RSTPINCR_RSTPINAF_Pos);
|
||||
(is_enable)
|
||||
? REG_WRITE_MASK(SYSCFG->RSTPINCR, SYSCFG_RSTPINCR_RSTPINAF_Msk, SYSCFG_RSTPINCR_RSTPINAF_OFF << SYSCFG_RSTPINCR_RSTPINAF_Pos)
|
||||
: REG_WRITE_MASK(SYSCFG->RSTPINCR, SYSCFG_RSTPINCR_RSTPINAF_Msk, SYSCFG_RSTPINCR_RSTPINAF_ON << SYSCFG_RSTPINCR_RSTPINAF_Pos);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -73,6 +73,8 @@ typedef struct
|
||||
uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. */
|
||||
uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. */
|
||||
uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. */
|
||||
uint16_t TIM_DTGFTime; /*!< Specifies the delay time between the switching-off and */
|
||||
uint32_t TIM_DTAEState; /*!< Specifies the delay time between the switching-off and */
|
||||
} TIM_BDTRInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
@@ -227,6 +229,11 @@ typedef struct
|
||||
#define TIM_DirectOutput_Disable (0x00U << TIM_BDTR_DOE_Pos) /*!< Direct output disable, output waiting for dead time */
|
||||
#define TIM_DirectOutput_Enable (0x01U << TIM_BDTR_DOE_Pos) /*!< Direct output enable, no longer waiting for output after dead time */
|
||||
|
||||
/**
|
||||
* @brief DATE_State_Selection_for_Idle_mode_state
|
||||
*/
|
||||
#define TIM_DTAEState_Disable (0x00U << TIM_BDTR_DTAE_Pos)
|
||||
#define TIM_DTAEState_Enable (0x01U << TIM_BDTR_DTAE_Pos)
|
||||
/**
|
||||
* @brief TIM_interrupt_sources
|
||||
*/
|
||||
@@ -238,6 +245,12 @@ typedef struct
|
||||
#define TIM_IT_COM (0x01U << TIM_DIER_COMIE_Pos) /*!< TIM Commutation Interrupt source */
|
||||
#define TIM_IT_Trigger (0x01U << TIM_DIER_TIE_Pos) /*!< TIM Trigger Interrupt source */
|
||||
#define TIM_IT_Break (0x01U << TIM_DIER_BIE_Pos) /*!< TIM Break Interrupt source */
|
||||
#define TIM_IT_CCD1 (0x01U << TIM_DIER_CCD1IE_Pos) /*!< TIM Capture Compare 1 Interrupt source */
|
||||
#define TIM_IT_CCD2 (0x01U << TIM_DIER_CCD2IE_Pos) /*!< TIM Capture Compare 2 Interrupt source */
|
||||
#define TIM_IT_CCD3 (0x01U << TIM_DIER_CCD3IE_Pos) /*!< TIM Capture Compare 3 Interrupt source */
|
||||
#define TIM_IT_OV (0x01U << TIM_DIER_OVIE_Pos) /*!< TIM Trigger Interrupt source */
|
||||
#define TIM_IT_UD (0x01U << TIM_DIER_UDIE_Pos) /*!< TIM Break Interrupt source */
|
||||
#define TIM_IT_CCD4 (0x01U << TIM_DIER_CCD4IE_Pos) /*!< TIM Capture Compare 4 Interrupt source */
|
||||
|
||||
|
||||
/**
|
||||
@@ -291,13 +304,13 @@ typedef struct
|
||||
/**
|
||||
* @brief TIM_Output_Compare_Clear_State
|
||||
*/
|
||||
#define TIM_OCClear_Disable (0x01U << TIM_CCMR1_OUTPUT_OC1CE_Pos) /*!< TIM Output clear disable */
|
||||
#define TIM_OCClear_Disable (0x00U << TIM_CCMR1_OUTPUT_OC1CE_Pos) /*!< TIM Output clear disable */
|
||||
#define TIM_OCClear_Enable (0x01U << TIM_CCMR1_OUTPUT_OC1CE_Pos) /*!< TIM Output clear enable */
|
||||
|
||||
/**
|
||||
* @brief TIM_Output_Compare_Fast_State
|
||||
*/
|
||||
#define TIM_OCFast_Disable (0x01U << TIM_CCMR1_OUTPUT_OC1FE_Pos) /*!< TIM output compare fast disable */
|
||||
#define TIM_OCFast_Disable (0x00U << TIM_CCMR1_OUTPUT_OC1FE_Pos) /*!< TIM output compare fast disable */
|
||||
#define TIM_OCFast_Enable (0x01U << TIM_CCMR1_OUTPUT_OC1FE_Pos) /*!< TIM output compare fast enable */
|
||||
|
||||
/**
|
||||
@@ -388,16 +401,16 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
|
||||
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
|
||||
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
||||
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
||||
#define TIM_ExtTRGPSC_OFF (0x00U << TIM_SMCR_ETPS_Pos)
|
||||
#define TIM_ExtTRGPSC_DIV2 (0x01U << TIM_SMCR_ETPS_Pos)
|
||||
#define TIM_ExtTRGPSC_DIV4 (0x02U << TIM_SMCR_ETPS_Pos)
|
||||
#define TIM_ExtTRGPSC_DIV8 (0x03U << TIM_SMCR_ETPS_Pos)
|
||||
|
||||
/** @defgroup TIM_External_Trigger_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
||||
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
||||
#define TIM_ExtTRGPolarity_Inverted (0x01U << TIM_SMCR_ETP_Pos)
|
||||
#define TIM_ExtTRGPolarity_NonInverted (0x00U << TIM_SMCR_ETP_Pos)
|
||||
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
@@ -459,6 +472,11 @@ void TIM_ForcedOC2Config(TIM_Type *tim, uint32_t forced_action);
|
||||
void TIM_ForcedOC3Config(TIM_Type *tim, uint32_t forced_action);
|
||||
void TIM_ForcedOC4Config(TIM_Type *tim, uint32_t forced_action);
|
||||
|
||||
void TIM_ClearOC1Ref(TIM_Type *tim, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC2Ref(TIM_Type *tim, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC3Ref(TIM_Type *tim, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC4Ref(TIM_Type *tim, uint16_t TIM_OCClear);
|
||||
|
||||
void TIM_ARRPreloadConfig(TIM_Type *tim, FunctionalState state);
|
||||
void TIM_SelectCOM(TIM_Type *tim, FunctionalState state);
|
||||
void TIM_SelectCCDMA(TIM_Type *tim, FunctionalState state);
|
||||
@@ -468,11 +486,12 @@ void TIM_OC1PreloadConfig(TIM_Type *tim, uint32_t preload);
|
||||
void TIM_OC2PreloadConfig(TIM_Type *tim, uint32_t preload);
|
||||
void TIM_OC3PreloadConfig(TIM_Type *tim, uint32_t preload);
|
||||
void TIM_OC4PreloadConfig(TIM_Type *tim, uint32_t preload);
|
||||
void TIM_OC5PreloadConfig(TIM_Type *tim, uint32_t preload);
|
||||
|
||||
void TIM_OC1FastConfig(TIM_Type *tim, uint32_t fast);
|
||||
void TIM_OC2FastConfig(TIM_Type *tim, uint32_t fast);
|
||||
void TIM_OC3FastConfig(TIM_Type *tim, uint32_t fast);
|
||||
void TIM_OC4FastConfig(TIM_Type *tim, uint32_t fast);
|
||||
|
||||
void TIM_OC1PolarityConfig(TIM_Type *tim, uint32_t polarity);
|
||||
void TIM_OC1NPolarityConfig(TIM_Type *tim, uint32_t polarity);
|
||||
void TIM_OC2PolarityConfig(TIM_Type *tim, uint32_t polarity);
|
||||
@@ -481,6 +500,7 @@ void TIM_OC3PolarityConfig(TIM_Type *tim, uint32_t polarity);
|
||||
void TIM_OC3NPolarityConfig(TIM_Type *tim, uint32_t polarity);
|
||||
void TIM_OC4PolarityConfig(TIM_Type *tim, uint32_t polarity);
|
||||
void TIM_OC4NPolarityConfig(TIM_Type *tim, uint32_t polarity);
|
||||
|
||||
void TIM_CCxCmd(TIM_Type *tim, uint16_t channel, uint32_t ccx_en);
|
||||
void TIM_CCxNCmd(TIM_Type *tim, uint16_t channel, uint32_t ccxn_en);
|
||||
|
||||
@@ -489,7 +509,12 @@ void TIM_SetCompare1(TIM_Type *tim, uint32_t compare);
|
||||
void TIM_SetCompare2(TIM_Type *tim, uint32_t compare);
|
||||
void TIM_SetCompare3(TIM_Type *tim, uint32_t compare);
|
||||
void TIM_SetCompare4(TIM_Type *tim, uint32_t compare);
|
||||
void TIM_SetCompare5(TIM_Type *tim, uint32_t compare);
|
||||
|
||||
void TIM_ASYMEN_Cmd(TIM_Type *tim, FunctionalState state);
|
||||
void TIM_SetDownCompare1(TIM_Type *tim, uint32_t compare);
|
||||
void TIM_SetDownCompare2(TIM_Type *tim, uint32_t compare);
|
||||
void TIM_SetDownCompare3(TIM_Type *tim, uint32_t compare);
|
||||
void TIM_SetDownCompare4(TIM_Type *tim, uint32_t compare);
|
||||
|
||||
void TIM_UpdateDisableConfig(TIM_Type *tim, FunctionalState state);
|
||||
void TIM_UpdateRequestConfig(TIM_Type *tim, uint32_t source);
|
||||
@@ -509,7 +534,6 @@ uint32_t TIM_GetCapture1(TIM_Type *tim);
|
||||
uint32_t TIM_GetCapture2(TIM_Type *tim);
|
||||
uint32_t TIM_GetCapture3(TIM_Type *tim);
|
||||
uint32_t TIM_GetCapture4(TIM_Type *tim);
|
||||
uint32_t TIM_GetCapture5(TIM_Type *tim);
|
||||
|
||||
uint32_t TIM_GetCounter(TIM_Type *tim);
|
||||
uint16_t TIM_GetPrescaler(TIM_Type *tim);
|
||||
@@ -524,12 +548,14 @@ void TIM_SetCCR1FALL(TIM_Type *tim, uint32_t shift);
|
||||
void TIM_SetCCR2FALL(TIM_Type *tim, uint32_t shift);
|
||||
void TIM_SetCCR3FALL(TIM_Type *tim, uint32_t shift);
|
||||
void TIM_SetCCR4FALL(TIM_Type *tim, uint32_t shift);
|
||||
void TIM_SetCCR5FALL(TIM_Type *tim, uint32_t shift);
|
||||
FlagStatus TIM_GetCountDirection(TIM_Type *tim);
|
||||
|
||||
FlagStatus TIM_GetCountDirection(TIM_Type *tim);
|
||||
uint32_t TIM_GetTIMxClock(TIM_Type *tim);
|
||||
|
||||
void TIM_ETRClockMode1Config(TIM_Type *tim, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
||||
void TIM_ETRClockMode2Config(TIM_Type* TIMx, uint16_t TIM_ExtTRGPrescaler,uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
||||
void TIM_TIxExternalClockConfig(TIM_Type *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter);
|
||||
void TIM_ETRConfig(TIM_Type *tim, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,uint16_t ExtTRGFilter);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
@@ -131,7 +131,7 @@ typedef enum
|
||||
*/
|
||||
__STATIC_FORCEINLINE void UART_ResetRxFIFO(UART_Type *pHUart)
|
||||
{
|
||||
REG_WRITE(pHUart->RXFR, 0x5700);
|
||||
REG_WRITE(pHUart->RXFR, 0xe930);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -144,7 +144,7 @@ __STATIC_FORCEINLINE void UART_ResetRxFIFO(UART_Type *pHUart)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void UART_ResetTxFIFO(UART_Type *pHUart)
|
||||
{
|
||||
REG_WRITE(pHUart->TXFR, 0x5700);
|
||||
REG_WRITE(pHUart->TXFR, 0xe930);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -277,21 +277,6 @@ uint16_t UART_ReceiveData(UART_Type *pHUart);
|
||||
UART_ErrTypeDef UART_ITConfig(UART_Type *pHUart, uint32_t flags, uint32_t is_enable);
|
||||
|
||||
|
||||
/**
|
||||
* @brief UART_Interrupt_definition
|
||||
*/
|
||||
#define UART_IT_RXNE (0x01U << UART_IE_RXNEE_Pos) /*!< RXNE interrupt enable */
|
||||
#define UART_IT_TXE (0x01U << UART_IE_TXEE_Pos) /*!< TXE interrupt enable */
|
||||
#define UART_IT_TXHE (0x01U << UART_IE_TXHEE_Pos) /*!< TXHE interrupt enable */
|
||||
#define UART_IT_PERR (0x01U << UART_IE_PERRE_Pos) /*!< PERR interrupt enable */
|
||||
#define UART_IT_FERR (0x01U << UART_IE_FERRE_Pos) /*!< FERR interrupt enable */
|
||||
#define UART_IT_OVERR (0x01U << UART_IE_OVERRE_Pos) /*!< OVERR interrupt enable */
|
||||
#define UART_IT_TONE (0x01U << UART_IE_TONEE_Pos) /*!< TONE Interrupt enable */
|
||||
#define UART_IT_TOIDLE (0x01U << UART_IE_TOIDLEE_Pos) /*!< TOIDLE interrupt enable */
|
||||
#define UART_IT_RXHF (0x01U << UART_IE_RXHFE_Pos) /*!< RXHF interrupt enable */
|
||||
#define UART_IT_RXF (0x01U << UART_IE_RXFE_Pos) /*!< RXF interrupt enable */
|
||||
#define UART_IT_TXEND (0x01U << UART_IE_TXENDE_Pos) /*!< TXEND interrupt enable */
|
||||
#define UART_IT_TXF (0x01U << UART_IE_TXFE_Pos) /*!< TXF interrupt enable */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
@@ -44,17 +44,17 @@ extern "C" {
|
||||
//=============================================================================
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Relaod;
|
||||
uint32_t Reset;
|
||||
uint32_t Debug;
|
||||
uint32_t Relaod;
|
||||
uint32_t Reset;
|
||||
uint32_t Debug;
|
||||
} WDG_BaseInitTypeDef;
|
||||
|
||||
|
||||
#define WDG_Reset_En (0x1U << WDG_CR_RSTE_Pos)
|
||||
#define WDG_Reset_Dis (0x0U << WDG_CR_RSTE_Pos)
|
||||
#define WDG_Reset_En (0x1U << WDG_CR_RSTE_Pos)
|
||||
#define WDG_Reset_Dis (0x0U << WDG_CR_RSTE_Pos)
|
||||
|
||||
#define WDG_Debug_En (0x1U << WDG_CR_DBGE_Pos)
|
||||
#define WDG_Debug_Dis (0x0U << WDG_CR_DBGE_Pos)
|
||||
#define WDG_Debug_En (0x1U << WDG_CR_DBGE_Pos)
|
||||
#define WDG_Debug_Dis (0x0U << WDG_CR_DBGE_Pos)
|
||||
|
||||
|
||||
|
||||
@@ -17,7 +17,7 @@
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
#define ADC_TIMEOUT_CNT 1000
|
||||
#define ADC_TIMEOUT_CNT (60*1000*10)
|
||||
|
||||
#define ADC_ALL_CHANNELS_Msk (0xFFFF)
|
||||
|
||||
@@ -133,6 +133,7 @@ void ADC_Init(ADC_Type *pHADC, ADC_InitTypeDef *pInit)
|
||||
pInit->DataAlign);
|
||||
|
||||
REG_SET_BITS(pHADC->STAT, ADC_STAT_EOC_CHECK_DIS_Msk);
|
||||
REG_WRITE_MASK(pHADC->CHSEL, ADC_CHSEL_CH_SEL_Msk, pInit->SelChannels);
|
||||
break;
|
||||
|
||||
case ADC_Mode_Scan:
|
||||
@@ -181,7 +182,7 @@ void ADC_Init(ADC_Type *pHADC, ADC_InitTypeDef *pInit)
|
||||
|
||||
void ADC_StructInit(ADC_InitTypeDef *pInit)
|
||||
{
|
||||
pInit->SelChannels = ADC_Channel_15;
|
||||
pInit->SelChannels = ADC_Channel_AVSS;
|
||||
pInit->ClkPrescaler = ADC_ClkDiv_Auto;
|
||||
pInit->DataAlign = ADC_DataAlign_Right;
|
||||
pInit->Mode = ADC_Mode_SingleConv;
|
||||
@@ -204,7 +205,6 @@ void ADC_ExtTrigConfig(ADC_Type *pHADC, ADC_ExtTrigSourceTypeDef ext_src, ADC_Ex
|
||||
|
||||
if( ext_src & 0x10 )
|
||||
{
|
||||
|
||||
uint32_t pin_sel = 0;
|
||||
|
||||
/* TRIG_SEL17 rising/falling configuraion */
|
||||
@@ -222,20 +222,44 @@ void ADC_ExtTrigConfig(ADC_Type *pHADC, ADC_ExtTrigSourceTypeDef ext_src, ADC_Ex
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Select the sub-channel of the ADC Channel-15
|
||||
*
|
||||
* \param [in] subchannel The selected sub-channel of ADC channel-15, @ref ADC_SubChannelTypeDef
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
void ADC_SelSubChannel(ADC_SubChannelTypeDef subchannel)
|
||||
{
|
||||
AMISC_InternalSrcTypeDef src_type = AMISC_InternalSrc_NONE;
|
||||
|
||||
src_type = (subchannel == ADC_SubChannel_TEMP) ? AMISC_InternalSrc_TEMP :
|
||||
(subchannel == ADC_SubChannel_DAC0) ? AMISC_InternalSrc_DAC0 :
|
||||
(subchannel == ADC_SubChannel_DAC1) ? AMISC_InternalSrc_DAC1 :
|
||||
(subchannel == ADC_SubChannel_VBuf_1_5) ? AMISC_InternalSrc_VBuf_1P5V :
|
||||
(subchannel == ADC_SubChannel_VDDL) ? AMISC_InternalSrc_VDDL :
|
||||
(subchannel == ADC_SubChannel_VSS) ? AMISC_InternalSrc_VSS :
|
||||
(subchannel == ADC_SubChannel_VDD) ? AMISC_InternalSrc_VDD :
|
||||
AMISC_InternalSrc_NONE;
|
||||
|
||||
AMISC_OutInternalSignalToIO(src_type, false);
|
||||
|
||||
REG_SET_BITS(AMISC->ADC_AIN_CR, AMISC_ADC_AIN_CR_ANA2ADC_EN_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
uint16_t ADC_GetChannelConvValue(ADC_Type *pHADC, ADC_ChannelsTypeDef channel)
|
||||
{
|
||||
volatile uint32_t *pData = (volatile uint32_t*)&pHADC->DAT0;
|
||||
int timeout = 0;
|
||||
uint32_t chnnl_id = (31ul - HAL_CLZ(channel));
|
||||
|
||||
#if 0
|
||||
while( REG_READ_MASK(pHADC->CON0, ADC_CON0_ENCONT_Msk) == 0 &&
|
||||
REG_READ_MASK(pHADC->STAT, ADC_STAT_DONE_Msk) == 0 )
|
||||
{
|
||||
if( timeout++ > ADC_TIMEOUT_CNT )
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
pData += (chnnl_id & 0xFul);
|
||||
return (uint16_t)((*pData) & 0xFFFFul);
|
||||
@@ -85,15 +85,6 @@ AMISC_StatusTypeDef AMISC_LVD_LVR_Config(AMISC_LVDRInitTypeDef *pInit)
|
||||
return AMISC_Status_OK;
|
||||
}
|
||||
|
||||
|
||||
void AMISC_VBUF_Config(AMISC_VBUFConfigTypeDef *pInit)
|
||||
{
|
||||
REG_WRITE_MASK(AMISC->VBUF_CR,
|
||||
AMISC_VBUF_CR_ANA2IO_EN_Msk | AMISC_VBUF_CR_ANA2PGA_EN_Msk | \
|
||||
AMISC_VBUF_CR_ANA_SEL_Msk ,
|
||||
pInit->Ana2IOT | pInit->Ana2PGA | pInit->AnaSel);
|
||||
}
|
||||
|
||||
void AMISC_HSI_Disable(void)
|
||||
{
|
||||
if( SYSCFG_GetSysClkType() == SYSCFG_ClkSrc_LSI )
|
||||
@@ -124,6 +115,85 @@ void AMISC_LSI_Enable(void)
|
||||
return;
|
||||
}
|
||||
|
||||
void AMISC_Sel_PGA_VinP_Src(AMISC_InternalSrcTypeDef src_type)
|
||||
{
|
||||
AMISC_InternalSrcTypeDef VinP_Src = AMISC_InternalSrc_NONE;
|
||||
|
||||
/* AMISC clock enable */
|
||||
__HAL_SYSCFG_AMISC_CLK_ENABLE();
|
||||
|
||||
VinP_Src = (src_type == AMISC_InternalSrc_NONE)
|
||||
? src_type : (AMISC_VBUF_CR_ANA2PGA_EN_Msk | src_type);
|
||||
|
||||
switch( src_type )
|
||||
{
|
||||
default:
|
||||
break;
|
||||
|
||||
case AMISC_InternalSrc_NONE:
|
||||
break;
|
||||
|
||||
case AMISC_InternalSrc_TEMP:
|
||||
REG_SET_BITS(AMISC->LVD_LVR_CR, AMISC_LVD_LVR_CR_TEMP_EN_Msk);
|
||||
break;
|
||||
|
||||
case AMISC_InternalSrc_DAC0:
|
||||
AMISC_DAC0_Enable();
|
||||
break;
|
||||
case AMISC_InternalSrc_DAC1:
|
||||
AMISC_DAC1_Enable();
|
||||
break;
|
||||
case AMISC_InternalSrc_VBuf_1P5V:
|
||||
REG_SET_BITS(VinP_Src, AMISC_VBUF_CR_VBUF_EN_Msk);
|
||||
break;
|
||||
}
|
||||
|
||||
REG_WRITE_MASK(AMISC->VBUF_CR,
|
||||
AMISC_VBUF_CR_ANA_SEL_Msk | AMISC_VBUF_CR_ANA2PGA_EN_Msk,
|
||||
VinP_Src);
|
||||
|
||||
sys_busy_wait(60*1000);
|
||||
return;
|
||||
}
|
||||
|
||||
void AMISC_OutInternalSignalToIO(AMISC_InternalSrcTypeDef src_type, int has_output)
|
||||
{
|
||||
uint32_t value = (has_output)
|
||||
? (src_type | AMISC_VBUF_CR_ANA2IO_EN_Msk) : src_type;
|
||||
|
||||
/* AMISC clock enable */
|
||||
__HAL_SYSCFG_AMISC_CLK_ENABLE();
|
||||
|
||||
switch( src_type )
|
||||
{
|
||||
default:
|
||||
break;
|
||||
|
||||
case AMISC_InternalSrc_NONE:
|
||||
break;
|
||||
|
||||
case AMISC_InternalSrc_TEMP:
|
||||
REG_SET_BITS(AMISC->LVD_LVR_CR, AMISC_LVD_LVR_CR_TEMP_EN_Msk);
|
||||
break;
|
||||
|
||||
case AMISC_InternalSrc_DAC0:
|
||||
AMISC_DAC0_Enable();
|
||||
break;
|
||||
case AMISC_InternalSrc_DAC1:
|
||||
AMISC_DAC1_Enable();
|
||||
break;
|
||||
case AMISC_InternalSrc_VBuf_1P5V:
|
||||
REG_SET_BITS(value, AMISC_VBUF_CR_VBUF_EN_Msk);
|
||||
break;
|
||||
}
|
||||
|
||||
REG_WRITE_MASK(AMISC->VBUF_CR,
|
||||
AMISC_VBUF_CR_ANA_SEL_Msk | AMISC_VBUF_CR_ANA2IO_EN_Msk | AMISC_VBUF_CR_VBUF_EN_Msk,
|
||||
value);
|
||||
|
||||
sys_busy_wait(60*1000);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
#endif /* CONFIG_ENABLE_HAL_AMISC */
|
||||
@@ -1,17 +1,19 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file isr.c
|
||||
/** @file hal_vcmp.c
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/09/16
|
||||
* @date 2024/10/17
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
|
||||
#include "isr.h"
|
||||
#include "hal_device.h"
|
||||
|
||||
#if defined(CONFIG_ENABLE_HAL_COMP)
|
||||
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
@@ -37,3 +39,5 @@
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
|
||||
|
||||
#endif /* CONFIG_ENABLE_HAL_VCMP */
|
||||
@@ -18,6 +18,7 @@
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
#define CONFIG_FLASH_TIMEOUT 0xFFFFFFFFul
|
||||
#define FLASH_PE_CLK_MAX (1ul*1000*1000)
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
@@ -33,7 +34,15 @@
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
static void
|
||||
_FLASH_SetDivider(void)
|
||||
{
|
||||
uint32_t div = 0;
|
||||
div = sys_get_cpu_freq() / FLASH_PE_CLK_MAX;
|
||||
|
||||
REG_WRITE(FLASH->DIV, div | (0x1ul << 8));
|
||||
return;
|
||||
}
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
@@ -63,7 +72,7 @@ FLASH_ErasePage(uint32_t page_addr)
|
||||
{
|
||||
flash_state_t rval = FLASH_STATE_OK;
|
||||
|
||||
REG_WRITE(FLASH->DIV, SYS_HIRC_MHZ | (0x1ul << 8)); // move to system init ???
|
||||
_FLASH_SetDivider();
|
||||
|
||||
do {
|
||||
REG_WRITE(FLASH->SR, 0xFFFFFFFFul); // clean interrutp flags
|
||||
@@ -104,6 +113,8 @@ FLASH_ProgWord(uint32_t addr, uint32_t value)
|
||||
break;
|
||||
}
|
||||
|
||||
_FLASH_SetDivider();
|
||||
|
||||
REG_WRITE(FLASH->SR, 0xFFFFFFFFul); // clean interrutp flags
|
||||
|
||||
FLASH->AR = addr;
|
||||
@@ -145,6 +156,7 @@ FLASH_ProgHWord(uint32_t addr, uint16_t value)
|
||||
break;
|
||||
}
|
||||
|
||||
_FLASH_SetDivider();
|
||||
REG_WRITE(FLASH->SR, 0xFFFFFFFFul); // clean interrutp flags
|
||||
|
||||
#if 0
|
||||
@@ -188,6 +200,7 @@ FLASH_ProgByte(uint32_t addr, uint8_t value)
|
||||
uint32_t word;
|
||||
} u;
|
||||
|
||||
_FLASH_SetDivider();
|
||||
REG_WRITE(FLASH->SR, 0xFFFFFFFFul); // clean interrutp flags
|
||||
|
||||
#if 0
|
||||
@@ -232,6 +245,7 @@ FLASH_ProgData(uint32_t addr, uint32_t *pData, int length)
|
||||
break;
|
||||
}
|
||||
|
||||
_FLASH_SetDivider();
|
||||
REG_WRITE(FLASH->SR, 0xFFFFFFFFul); // clean interrutp flags
|
||||
|
||||
FLASH->AR = addr;
|
||||
@@ -63,9 +63,12 @@ int GPIO_Init(GPIO_Type *pHGpio, GPIO_InitTypeDef *pInit)
|
||||
continue;
|
||||
|
||||
// enable Schmitt-Trigger
|
||||
REG_CLR_BITS(pHGpio->CTC, pin_cur);
|
||||
REG_SET_BITS(pHGpio->CTS, pin_cur);
|
||||
|
||||
(pInit->GPIO_OType == GPIO_OType_OD)
|
||||
? REG_SET_BITS(pHGpio->ODS, pin_cur)
|
||||
: REG_SET_BITS(pHGpio->ODC, pin_cur);
|
||||
|
||||
switch( pInit->GPIO_Mode )
|
||||
{
|
||||
default:
|
||||
@@ -95,36 +98,33 @@ int GPIO_Init(GPIO_Type *pHGpio, GPIO_InitTypeDef *pInit)
|
||||
case GPIO_Mode_OUT: /* Output mode */
|
||||
REG_SET_BITS(pHGpio->INEC, pin_cur);
|
||||
REG_SET_BITS(pHGpio->OES, pin_cur);
|
||||
(pInit->GPIO_OType == GPIO_OType_OD)
|
||||
? REG_SET_BITS(pHGpio->ODS, pin_cur)
|
||||
: REG_SET_BITS(pHGpio->ODC, pin_cur);
|
||||
|
||||
if( pInit->GPIO_PuPd == GPIO_PuPd_UP )
|
||||
{
|
||||
REG_SET_BITS(pHGpio->PUS, pin_cur);
|
||||
REG_SET_BITS(pHGpio->PDC, pin_cur);
|
||||
REG_SET_BITS(pHGpio->LAT, pin_cur);
|
||||
}
|
||||
else if( pInit->GPIO_PuPd == GPIO_PuPd_DOWN )
|
||||
{
|
||||
REG_SET_BITS(pHGpio->PDS, pin_cur);
|
||||
REG_SET_BITS(pHGpio->PUC, pin_cur);
|
||||
REG_CLR_BITS(pHGpio->LAT, pin_cur);
|
||||
}
|
||||
else
|
||||
{ /* NOPULL */
|
||||
REG_SET_BITS(pHGpio->PDC, pin_cur);
|
||||
REG_SET_BITS(pHGpio->PUC, pin_cur);
|
||||
{
|
||||
/* NOPULL, H/w not support */
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case GPIO_Mode_ANAL: /* Analog mode */
|
||||
REG_SET_BITS(pHGpio->INEC, pin_cur);
|
||||
|
||||
// disable Schmitt-Trigger
|
||||
REG_CLR_BITS(pHGpio->CTS, pin_cur);
|
||||
REG_SET_BITS(pHGpio->CTC, pin_cur);
|
||||
break;
|
||||
|
||||
case GPIO_Mode_PWR_Saving:
|
||||
REG_SET_BITS(pHGpio->INEC, pin_cur);
|
||||
REG_SET_BITS(pHGpio->OEC, pin_cur);
|
||||
break;
|
||||
|
||||
case GPIO_Mode_AF: /* Alternate mode */
|
||||
if( pHGpio == GPIOA && (pin_cur & GPIO_PORTA_AF_PINS) )
|
||||
{
|
||||
@@ -151,6 +151,44 @@ int GPIO_Init(GPIO_Type *pHGpio, GPIO_InitTypeDef *pInit)
|
||||
return rval;
|
||||
}
|
||||
|
||||
void GPIO_DeInit(GPIO_Type *pHGpio, uint32_t pins)
|
||||
{
|
||||
while( pins )
|
||||
{
|
||||
int shift = 31 - HAL_CLZ(pins);
|
||||
uint32_t pin_cur = 0x0;
|
||||
|
||||
pin_cur = 0x1ul << shift;
|
||||
REG_CLR_BITS(pins, pin_cur);
|
||||
|
||||
REG_SET_BITS(pHGpio->IEC, pin_cur); // disable interrupt
|
||||
|
||||
REG_SET_BITS(pHGpio->INEC, pin_cur);
|
||||
REG_SET_BITS(pHGpio->OEC, pin_cur);
|
||||
|
||||
REG_SET_BITS(pHGpio->ODC, pin_cur);
|
||||
|
||||
REG_SET_BITS(pHGpio->ITC0, pin_cur);
|
||||
REG_SET_BITS(pHGpio->ITC1, pin_cur);
|
||||
REG_SET_BITS(pHGpio->PLC, pin_cur);
|
||||
REG_SET_BITS(pHGpio->IST, pin_cur);
|
||||
|
||||
REG_SET_BITS(pHGpio->CTS, pin_cur);
|
||||
|
||||
if( pHGpio == GPIOA && (pin_cur & GPIO_PORTA_AF_PINS) )
|
||||
{
|
||||
shift = (shift > 5) ? (shift - 8) : shift;
|
||||
REG_WRITE_MASK(AFIO->PAAFR, (AFIO_PAAFR_PA0_Msk << 3*shift), GPIO_AF_0 << 3*shift);
|
||||
}
|
||||
else if( pHGpio == GPIOB && (pin_cur & GPIO_PORTB_AF_PINS) )
|
||||
{
|
||||
REG_WRITE_MASK(AFIO->PBAFR, (AFIO_PBAFR_PB0_Msk << 3*shift), GPIO_AF_0 << 3*shift);
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void GPIO_PeriAFConfig(GPIO_Type *pHGpio, GPIO_PeriTypeDef peri_type, GPIO_PeriAFTypeDef af_mode)
|
||||
{
|
||||
if( peri_type < GPIO_Peri_Fn2 )
|
||||
@@ -0,0 +1,870 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file hal_i2c.c
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/09/10
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
|
||||
#include "hal_device.h"
|
||||
|
||||
#if defined(CONFIG_ENABLE_HAL_I2C)
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
#define CONFIG_I2C_TIMEOUT 20U /*!< Timeout 20 ms */
|
||||
#define I2C_CLOCK_FREQ_MAX (400ul*1000)
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_SwState_SUCCESS = 0, /*!< Waited i2c status flag */
|
||||
I2C_SwState_ERROR = 1, /*!< No i2c status flag */
|
||||
I2C_SwState_WAITING = 2, /*!< Waiting i2c status flag */
|
||||
I2C_SwState_HOLD_DATA = 3, /*!< I2C hold data flag */
|
||||
I2C_SwState_FORCE_STOP = 4, /*!< I2C force stop flag */
|
||||
I2C_SwState_RESTART = 5, /*!< I2C restart flag */
|
||||
} I2C_SwState;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_TxStage_START_BIT = 0,
|
||||
I2C_TxStage_ADDRESS,
|
||||
I2C_TxStage_DATA,
|
||||
|
||||
} I2C_TxStage;
|
||||
|
||||
#define I2C_START_BIT_H I2C_CTLSET_STA_Msk
|
||||
#define I2C_START_BIT_L 0x0u
|
||||
|
||||
#define I2C_STOP_BIT_H I2C_CTLSET_STO_Msk
|
||||
#define I2C_STOP_BIT_L 0x0u
|
||||
|
||||
#define I2C_ACK_BIT_H I2C_CTLSET_AA_Msk
|
||||
#define I2C_ACK_BIT_L 0x0u
|
||||
|
||||
|
||||
#define I2C_CLK_DIVIDER_60 (I2C_CTLSET_CR1_Msk | I2C_CTLSET_CR2_Msk)
|
||||
#define I2C_CLK_DIVIDER_120 (I2C_CTLSET_CR0_Msk | I2C_CTLSET_CR2_Msk)
|
||||
#define I2C_CLK_DIVIDER_160 (I2C_CTLSET_CR0_Msk | I2C_CTLSET_CR1_Msk)
|
||||
#define I2C_CLK_DIVIDER_192 I2C_CTLSET_CR1_Msk
|
||||
#define I2C_CLK_DIVIDER_244 I2C_CTLSET_CR0_Msk
|
||||
#define I2C_CLK_DIVIDER_256 0x0ul
|
||||
#define I2C_CLK_DIVIDER_960 I2C_CTLSET_CR2_Msk
|
||||
#define I2C_CLK_DIVIDER_Msk (I2C_CTLSET_CR0_Msk | I2C_CTLSET_CR1_Msk | I2C_CTLSET_CR2_Msk)
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
/**
|
||||
* \brief Set/Clear Ack bit
|
||||
*
|
||||
* \param [in] pHI2C The handle of I2C
|
||||
* \return None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void _I2C_SET_ACK_FLAG(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_SET_BITS(pHI2C->CTLSET, I2C_CTLSET_AA_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE void _I2C_CLR_ACK_FLAG(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_SET_BITS(pHI2C->CTLCLR, I2C_CTLCLR_AA_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set/Clear Start bit
|
||||
*
|
||||
* \param [in] pHI2C The handle of I2C
|
||||
* \return None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void _I2C_SET_START_FLAG(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_SET_BITS(pHI2C->CTLSET, I2C_CTLSET_STA_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE void _I2C_CLR_START_FLAG(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_SET_BITS(pHI2C->CTLCLR, I2C_CTLCLR_STA_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Check Interrupt flag of an I2C
|
||||
*
|
||||
* \param [in] __HANDLE__ The handle of I2C
|
||||
* \return
|
||||
* 0 : no interrupt
|
||||
* others: get interrupt
|
||||
*/
|
||||
#define __I2C_GET_SI_FLAG(__HANDLE__) REG_READ_MASK((__HANDLE__)->CTLSET, I2C_CTLSET_SI_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* \brief Set/Clear the I2C interrupt set-flag
|
||||
*
|
||||
* \param [in] pHI2C The handle of I2C
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void _I2C_SET_SI_FLAG(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_SET_BITS(pHI2C->CTLSET, I2C_CTLSET_SI_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE void _I2C_CLR_SI_FLAG(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_SET_BITS(pHI2C->CTLCLR, I2C_CTLCLR_SI_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable/Disable General Call
|
||||
*
|
||||
* \param [in] pHI2C The handle of I2C
|
||||
* \return None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void _I2C_GC_ENABLE(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_SET_BITS(pHI2C->ADDR, I2C_ADDR_GC_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE void _I2C_GC_DISABLE(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_CLR_BITS(pHI2C->ADDR, I2C_ADDR_GC_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable/Disable I2C module
|
||||
*
|
||||
* \param [in] pHI2C The handle of I2C
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void _I2C_ENABLE(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_SET_BITS(pHI2C->CTLSET, I2C_CTLSET_EN_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE void _I2C_DISABLE(I2C_Type *pHI2C)
|
||||
{
|
||||
REG_SET_BITS(pHI2C->CTLCLR, I2C_CTLSET_EN_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Configure the Start/Stop/ACK flag
|
||||
*
|
||||
* \param [in] pHI2C The handle of I2C
|
||||
* \param [in] start_bit The target state of start_bit
|
||||
* \param [in] stop_bit The target state of stop_bit
|
||||
* \param [in] ack_bit The target state of ack_bit
|
||||
* \return
|
||||
* None
|
||||
*/
|
||||
__STATIC_FORCEINLINE void _I2C_Config(I2C_Type *pHI2C, uint32_t start_bit, uint32_t stop_bit, uint32_t ack_bit)
|
||||
{
|
||||
REG_WRITE_MASK(pHI2C->CTLCLR,
|
||||
I2C_CTLCLR_STA_Msk | I2C_CTLCLR_STO_Msk | I2C_CTLCLR_AA_Msk,
|
||||
I2C_CTLCLR_STA_Msk | I2C_CTLCLR_STO_Msk | I2C_CTLCLR_AA_Msk);
|
||||
|
||||
REG_WRITE_MASK(pHI2C->CTLSET,
|
||||
I2C_CTLSET_STA_Msk | I2C_CTLSET_STO_Msk | I2C_CTLSET_AA_Msk,
|
||||
(start_bit) | (stop_bit) | (ack_bit));
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
static I2C_ErrTypeDef
|
||||
_I2C_Wait_SI_Flag(I2C_Type *pHI2C, uint32_t timeout_ms)
|
||||
{
|
||||
uint32_t start_ticks = 0;
|
||||
|
||||
start_ticks = sys_get_tick();
|
||||
|
||||
while( !REG_READ_MASK(pHI2C->CTLSET, I2C_CTLSET_SI_Msk) )
|
||||
{
|
||||
if( (sys_get_tick() - start_ticks) > timeout_ms )
|
||||
{
|
||||
return I2C_Err_TimeOut;
|
||||
}
|
||||
}
|
||||
|
||||
return I2C_Err_OK;
|
||||
}
|
||||
|
||||
static I2C_SwState
|
||||
_I2C_Master_Send_Byte(I2C_Type *pHI2C, uint8_t **ppData, bool is_end)
|
||||
{
|
||||
__IO uint32_t *pData_reg = &pHI2C->DATA;
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
|
||||
switch( REG_READ(pHI2C->STAT) )
|
||||
{
|
||||
default:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_H, I2C_ACK_BIT_L);
|
||||
rval = I2C_SwState_ERROR;
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_TX_START:
|
||||
case I2C_State_MASTER_TX_RESTART:
|
||||
case I2C_State_MASTER_TX_SLAW_ACK:
|
||||
*((__IO uint8_t*)pData_reg) = *((__IO uint8_t*)(*ppData));
|
||||
*ppData = *ppData + 1;
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_L, I2C_ACK_BIT_L);
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_TX_SLAW_NOACK:
|
||||
case I2C_State_MASTER_TX_DATA_NOACK:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_H, I2C_ACK_BIT_L);
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_TX_DATA_ACK:
|
||||
if( is_end )
|
||||
{
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_H, I2C_ACK_BIT_L);
|
||||
break;
|
||||
}
|
||||
|
||||
*((__IO uint8_t*)pData_reg) = *((__IO uint8_t*)(*ppData));
|
||||
*ppData = *ppData + 1;
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_TX_LOST_BUS:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_H, I2C_STOP_BIT_L, I2C_ACK_BIT_L);
|
||||
break;
|
||||
}
|
||||
|
||||
_I2C_CLR_SI_FLAG(pHI2C);
|
||||
|
||||
return rval;
|
||||
}
|
||||
|
||||
static I2C_SwState
|
||||
_I2C_Master_Recv_Byte(I2C_Type *pHI2C, uint8_t **ppData, uint32_t is_end)
|
||||
{
|
||||
__IO uint32_t *pData_reg = &pHI2C->DATA;
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
|
||||
switch( REG_READ(pHI2C->STAT) )
|
||||
{
|
||||
default:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_H, I2C_ACK_BIT_L);
|
||||
rval = I2C_SwState_ERROR;
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_TX_DATA_ACK:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_H, I2C_STOP_BIT_L, I2C_ACK_BIT_L);
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_RX_START:
|
||||
case I2C_State_MASTER_RX_RESTART:
|
||||
*((__IO uint8_t*)pData_reg) = *((__IO uint8_t*)(*ppData));
|
||||
*ppData = *ppData + 1;
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_L, I2C_ACK_BIT_L);
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_RX_SLAR_ACK:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L,
|
||||
I2C_STOP_BIT_L,
|
||||
(is_end)? I2C_ACK_BIT_L : I2C_ACK_BIT_H);
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_RX_DATA_ACK:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L,
|
||||
I2C_STOP_BIT_L,
|
||||
(is_end) ? I2C_ACK_BIT_L : I2C_ACK_BIT_H);
|
||||
|
||||
*(__IO uint8_t*)(*ppData) = *((__IO uint8_t*)pData_reg);
|
||||
*ppData = *ppData + 1;
|
||||
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_RX_DATA_NOACK:
|
||||
*(__IO uint8_t*)(*ppData) = *((__IO uint8_t*)pData_reg);
|
||||
*ppData = *ppData + 1;
|
||||
|
||||
case I2C_State_MASTER_RX_SLAR_NOACK:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_H, I2C_ACK_BIT_H);
|
||||
break;
|
||||
|
||||
case I2C_State_MASTER_RX_LOST_BUS:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_H, I2C_STOP_BIT_L, I2C_ACK_BIT_H);
|
||||
break;
|
||||
}
|
||||
|
||||
_I2C_CLR_SI_FLAG(pHI2C);
|
||||
|
||||
return rval;
|
||||
}
|
||||
|
||||
static I2C_SwState
|
||||
_I2C_Slave_Send_Byte(I2C_Type *pHI2C, uint8_t **ppData, bool *pHasRxAddr, bool is_end)
|
||||
{
|
||||
__IO uint32_t *pData_reg = &pHI2C->DATA;
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
|
||||
switch( REG_READ(pHI2C->STAT) )
|
||||
{
|
||||
default:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_H, I2C_ACK_BIT_H);
|
||||
rval = I2C_SwState_ERROR;
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_RX_SLAR_ACK:
|
||||
*pHasRxAddr = true;
|
||||
case I2C_State_SLAVE_TX_DATA_ACK:
|
||||
if( is_end )
|
||||
{
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_H, I2C_ACK_BIT_H);
|
||||
break;
|
||||
}
|
||||
|
||||
*((__IO uint8_t*)pData_reg) = *((__IO uint8_t*)(*ppData));
|
||||
*ppData = *ppData + 1;
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_L, I2C_ACK_BIT_H);
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_TX_LOST_BUS:
|
||||
*((__IO uint8_t*)pData_reg) = *((__IO uint8_t*)(*ppData));
|
||||
*ppData = *ppData + 1;
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_H, I2C_STOP_BIT_L, I2C_ACK_BIT_H);
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_TX_DATA_NOACK:
|
||||
case I2C_State_SLAVE_TX_LAST_DATA:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_L, I2C_ACK_BIT_H);
|
||||
rval = I2C_SwState_SUCCESS;
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_STOP_RESTART: // master force stop
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_L, I2C_ACK_BIT_H);
|
||||
rval = (*pHasRxAddr) ? I2C_SwState_FORCE_STOP : I2C_SwState_RESTART;
|
||||
break;
|
||||
}
|
||||
|
||||
_I2C_CLR_SI_FLAG(pHI2C);
|
||||
|
||||
return rval;
|
||||
}
|
||||
|
||||
static I2C_SwState
|
||||
_I2C_Slave_Recv_Byte(I2C_Type *pHI2C, uint8_t **ppData, uint32_t is_end)
|
||||
{
|
||||
__IO uint32_t *pData_reg = &pHI2C->DATA;
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
|
||||
switch( REG_READ(pHI2C->STAT) )
|
||||
{
|
||||
default:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_H, I2C_ACK_BIT_H);
|
||||
rval = I2C_SwState_ERROR;
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_RX_SLAW_LOST_BUS:
|
||||
case I2C_State_SLAVE_RX_BADDR_LOST_BUS:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_H, I2C_STOP_BIT_L, I2C_ACK_BIT_H);
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_RX_SLAW_ACK:
|
||||
case I2C_State_SLAVE_RX_BDATA_NOACK:
|
||||
case I2C_State_SLAVE_RX_BROAD_ACK:
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L,
|
||||
I2C_STOP_BIT_L,
|
||||
(is_end) ? I2C_ACK_BIT_L : I2C_ACK_BIT_H);
|
||||
|
||||
rval = I2C_SwState_HOLD_DATA;
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_RX_DATA_ACK:
|
||||
*(__IO uint8_t*)(*ppData) = *((__IO uint8_t*)pData_reg);
|
||||
*ppData = *ppData + 1;
|
||||
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L,
|
||||
I2C_STOP_BIT_L,
|
||||
(is_end) ? I2C_ACK_BIT_L : I2C_ACK_BIT_H);
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_RX_DATA_NOACK:
|
||||
*(__IO uint8_t*)(*ppData) = *((__IO uint8_t*)pData_reg);
|
||||
*ppData = *ppData + 1;
|
||||
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L,
|
||||
(is_end) ? I2C_STOP_BIT_H : I2C_STOP_BIT_L,
|
||||
I2C_ACK_BIT_H);
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_RX_BDATA_ACK:
|
||||
*(__IO uint8_t*)(*ppData) = *((__IO uint8_t*)pData_reg);
|
||||
*ppData = *ppData + 1;
|
||||
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_L, I2C_ACK_BIT_H);
|
||||
break;
|
||||
|
||||
case I2C_State_SLAVE_STOP_RESTART: // master force stop
|
||||
_I2C_Config(pHI2C, I2C_START_BIT_L, I2C_STOP_BIT_L, I2C_ACK_BIT_H);
|
||||
rval = I2C_SwState_FORCE_STOP;
|
||||
break;
|
||||
}
|
||||
|
||||
_I2C_CLR_SI_FLAG(pHI2C);
|
||||
|
||||
return rval;
|
||||
}
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
void I2C_StructInit(I2C_InitTypeDef *pInit)
|
||||
{
|
||||
int divider = 0;
|
||||
|
||||
pInit->Mode = I2C_Mode_MASTER;
|
||||
pInit->OwnAddress = 0x0;
|
||||
pInit->BroadAck = I2C_BroadAck_Disable;
|
||||
|
||||
divider = (g_SystemCoreClock / I2C_CLOCK_FREQ_MAX);
|
||||
pInit->ClockDiv = (divider <= I2C_CLK_Div60) ? I2C_CLK_Div60 :
|
||||
(divider <= I2C_CLK_Div120) ? I2C_CLK_Div120 :
|
||||
(divider <= I2C_CLK_Div160) ? I2C_CLK_Div160 :
|
||||
(divider <= I2C_CLK_Div192) ? I2C_CLK_Div192 :
|
||||
(divider <= I2C_CLK_Div244) ? I2C_CLK_Div244 :
|
||||
(divider <= I2C_CLK_Div256) ? I2C_CLK_Div256 :
|
||||
I2C_CLK_Div960;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the i2c peripheral registers to their default
|
||||
* reset values.
|
||||
* @param i2c1.
|
||||
* @retval None.
|
||||
*/
|
||||
void I2C_DeInit(I2C_Type *pHI2C)
|
||||
{
|
||||
_I2C_DISABLE(pHI2C);
|
||||
|
||||
__HAL_SYSCFG_RESET_I2C();
|
||||
__HAL_SYSCFG_I2C_CLK_DISABLE();
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
I2C_ErrTypeDef I2C_Init(I2C_Type *pHI2C, I2C_InitTypeDef *pInit)
|
||||
{
|
||||
__HAL_SYSCFG_I2C_CLK_ENABLE();
|
||||
__HAL_SYSCFG_RESET_I2C();
|
||||
|
||||
if( pInit->Mode == I2C_Mode_MASTER )
|
||||
{
|
||||
uint32_t divider = 0ul;
|
||||
|
||||
/**
|
||||
* I2C clock freq should less than I2C_CLOCK_FREQ_MAX
|
||||
*/
|
||||
// if( (g_SystemCoreClock / pInit->ClockDiv) > I2C_CLOCK_FREQ_MAX )
|
||||
// return I2C_Err_WrongParams;
|
||||
|
||||
divider = (pInit->ClockDiv == I2C_CLK_Div960) ? I2C_CLK_DIVIDER_960 :
|
||||
(pInit->ClockDiv == I2C_CLK_Div256) ? I2C_CLK_DIVIDER_256 :
|
||||
(pInit->ClockDiv == I2C_CLK_Div244) ? I2C_CLK_DIVIDER_244 :
|
||||
(pInit->ClockDiv == I2C_CLK_Div192) ? I2C_CLK_DIVIDER_192 :
|
||||
(pInit->ClockDiv == I2C_CLK_Div160) ? I2C_CLK_DIVIDER_160 :
|
||||
(pInit->ClockDiv == I2C_CLK_Div120) ? I2C_CLK_DIVIDER_120 :
|
||||
I2C_CLK_DIVIDER_60;
|
||||
|
||||
/* Set divider */
|
||||
REG_WRITE_MASK(pHI2C->CTLSET, I2C_CLK_DIVIDER_Msk, divider);
|
||||
|
||||
/* clear ack flag */
|
||||
_I2C_CLR_ACK_FLAG(pHI2C);
|
||||
}
|
||||
else if( pInit->Mode == I2C_Mode_SLAVE )
|
||||
{
|
||||
/* Configure Slave Address */
|
||||
REG_WRITE_MASK(pHI2C->ADDR,
|
||||
I2C_ADDR_ADDR_Msk | I2C_ADDR_GC_Msk,
|
||||
(pInit->OwnAddress << I2C_ADDR_ADDR_Pos) | pInit->BroadAck);
|
||||
|
||||
REG_WRITE_MASK(pHI2C->CTLSET, I2C_CLK_DIVIDER_Msk, pInit->ClockDiv);
|
||||
|
||||
_I2C_SET_ACK_FLAG(pHI2C);
|
||||
}
|
||||
else
|
||||
return I2C_Err_WrongParams;
|
||||
|
||||
|
||||
_I2C_ENABLE(pHI2C);
|
||||
_I2C_CLR_SI_FLAG(pHI2C);
|
||||
|
||||
return I2C_Err_OK;
|
||||
}
|
||||
|
||||
I2C_ErrTypeDef I2C_Master_Transmit(I2C_Type *pHI2C, uint16_t DevAddr, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
I2C_TxStage stage = I2C_TxStage_START_BIT;
|
||||
uint16_t tx_nbytes = 0;
|
||||
|
||||
if( (int)pHI2C == (int)I2C0 )
|
||||
sys_close_IRQ(I2C0_IRQn);
|
||||
|
||||
_I2C_SET_START_FLAG(pHI2C);
|
||||
stage = I2C_TxStage_ADDRESS;
|
||||
|
||||
while( tx_nbytes < Size )
|
||||
{
|
||||
if( _I2C_Wait_SI_Flag(pHI2C, CONFIG_I2C_TIMEOUT) != I2C_Err_OK )
|
||||
break;
|
||||
|
||||
if( stage == I2C_TxStage_ADDRESS )
|
||||
{
|
||||
uint8_t addr = (uint8_t)DevAddr & ~0x1u; // write mode
|
||||
uint8_t *pAddr = 0;
|
||||
|
||||
pAddr = &addr;
|
||||
rval = _I2C_Master_Send_Byte(pHI2C, &pAddr, false);
|
||||
if( rval == I2C_SwState_ERROR )
|
||||
break;
|
||||
|
||||
stage = I2C_TxStage_DATA;
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
rval = _I2C_Master_Send_Byte(pHI2C, &pData, false);
|
||||
if( rval == I2C_SwState_ERROR )
|
||||
break;
|
||||
}
|
||||
|
||||
tx_nbytes = (rval == I2C_SwState_SUCCESS) ? tx_nbytes + 1 : tx_nbytes;
|
||||
}
|
||||
|
||||
if( rval == I2C_SwState_SUCCESS )
|
||||
{
|
||||
// send STOP-bit
|
||||
_I2C_Wait_SI_Flag(pHI2C, CONFIG_I2C_TIMEOUT);
|
||||
_I2C_Master_Send_Byte(pHI2C, &pData, true);
|
||||
}
|
||||
|
||||
return (rval == I2C_SwState_SUCCESS) ? I2C_Err_OK : I2C_Err_Fail;
|
||||
}
|
||||
|
||||
I2C_ErrTypeDef I2C_Master_Receive(I2C_Type *pHI2C, uint8_t DevAddr, uint8_t *pData, uint16_t *pSize, uint16_t Timeout_ms)
|
||||
{
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
I2C_TxStage stage = I2C_TxStage_START_BIT;
|
||||
uint16_t buf_size = *pSize;
|
||||
int rx_nbytes = 0;
|
||||
|
||||
if( (int)pHI2C == (int)I2C0 )
|
||||
sys_close_IRQ(I2C0_IRQn);
|
||||
|
||||
_I2C_SET_START_FLAG(pHI2C);
|
||||
stage = I2C_TxStage_ADDRESS;
|
||||
|
||||
if( pSize ) *pSize = 0;
|
||||
|
||||
while( rx_nbytes < buf_size )
|
||||
{
|
||||
if( _I2C_Wait_SI_Flag(pHI2C, Timeout_ms) != I2C_Err_OK )
|
||||
{
|
||||
if( Timeout_ms == I2C_BLOCKING )
|
||||
continue;
|
||||
|
||||
return I2C_Err_TimeOut;
|
||||
}
|
||||
|
||||
if( stage == I2C_TxStage_ADDRESS )
|
||||
{
|
||||
uint8_t addr = (uint8_t)DevAddr | 0x1u; // read mode
|
||||
uint8_t *pAddr = 0;
|
||||
|
||||
pAddr = &addr;
|
||||
rval = _I2C_Master_Recv_Byte(pHI2C, &pAddr, (buf_size == 1));
|
||||
if( rval == I2C_SwState_ERROR )
|
||||
break;
|
||||
|
||||
/**
|
||||
* send DevAddr+R and then receive data
|
||||
* ps. Decrease the DevAddr+R byte
|
||||
*/
|
||||
rx_nbytes = -1;
|
||||
stage = I2C_TxStage_DATA;
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
rval = _I2C_Master_Recv_Byte(pHI2C, &pData, ((rx_nbytes + 1) == (buf_size-1)));
|
||||
if( rval == I2C_SwState_ERROR )
|
||||
break;
|
||||
}
|
||||
|
||||
rx_nbytes = (rval == I2C_SwState_SUCCESS) ? rx_nbytes + 1 : rx_nbytes;
|
||||
}
|
||||
|
||||
if( pSize ) *pSize = rx_nbytes;
|
||||
|
||||
return (rval == I2C_SwState_SUCCESS) ? I2C_Err_OK : I2C_Err_Fail;
|
||||
}
|
||||
|
||||
I2C_ErrTypeDef I2C_Slave_Transmit(I2C_Type *pHI2C, uint8_t *pData, uint16_t Size, uint16_t Timeout_ms)
|
||||
{
|
||||
__IO uint16_t tx_nbytes = 0;
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
bool HasRecvAddr = false;
|
||||
|
||||
if( (int)pHI2C == (int)I2C0 )
|
||||
sys_close_IRQ(I2C0_IRQn);
|
||||
|
||||
while( tx_nbytes < Size )
|
||||
{
|
||||
if( _I2C_Wait_SI_Flag(pHI2C, Timeout_ms) != I2C_Err_OK )
|
||||
{
|
||||
if( Timeout_ms == I2C_BLOCKING )
|
||||
continue;
|
||||
|
||||
return I2C_Err_TimeOut;
|
||||
}
|
||||
|
||||
rval = _I2C_Slave_Send_Byte(pHI2C, &pData, &HasRecvAddr, false);
|
||||
if( rval == I2C_SwState_ERROR || rval == I2C_SwState_FORCE_STOP )
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
tx_nbytes = (rval == I2C_SwState_SUCCESS) ? tx_nbytes + 1 : tx_nbytes;
|
||||
}
|
||||
|
||||
if( rval == I2C_SwState_SUCCESS )
|
||||
{
|
||||
// send STOP-bit
|
||||
_I2C_Wait_SI_Flag(pHI2C, CONFIG_I2C_TIMEOUT);
|
||||
_I2C_Slave_Send_Byte(pHI2C, &pData, &HasRecvAddr, true);
|
||||
}
|
||||
|
||||
return (rval == I2C_SwState_SUCCESS) ? I2C_Err_OK : I2C_Err_Fail;
|
||||
}
|
||||
|
||||
I2C_ErrTypeDef I2C_Slave_Receive(I2C_Type *pHI2C, uint8_t *pData, uint16_t *pSize, uint16_t Timeout_ms)
|
||||
{
|
||||
uint16_t rx_nbytes = 0;
|
||||
uint16_t buf_size = *pSize;
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
|
||||
if( (int)pHI2C == (int)I2C0 )
|
||||
sys_close_IRQ(I2C0_IRQn);
|
||||
|
||||
if( pSize ) *pSize = 0;
|
||||
|
||||
while( rx_nbytes < buf_size )
|
||||
{
|
||||
if( _I2C_Wait_SI_Flag(pHI2C, Timeout_ms) != I2C_Err_OK )
|
||||
{
|
||||
if( Timeout_ms == I2C_BLOCKING )
|
||||
continue;
|
||||
|
||||
return I2C_Err_TimeOut;
|
||||
}
|
||||
|
||||
rval = _I2C_Slave_Recv_Byte(pHI2C, &pData, ((rx_nbytes + 1) == buf_size));
|
||||
if( rval == I2C_SwState_ERROR || rval == I2C_SwState_FORCE_STOP )
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
rx_nbytes = (rval == I2C_SwState_SUCCESS) ? rx_nbytes + 1 : rx_nbytes;
|
||||
}
|
||||
|
||||
if( pSize ) *pSize = rx_nbytes;
|
||||
|
||||
return (rval == I2C_SwState_SUCCESS) ? I2C_Err_OK : I2C_Err_Fail;
|
||||
}
|
||||
|
||||
I2C_ErrTypeDef I2C_Master_Transmit_IT(I2C_IT_HandleTypeDef *pHITI2C, uint16_t DevAddr, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
pHITI2C->XferMode = I2C_XferMode_Transmite;
|
||||
pHITI2C->DevAddress = (uint8_t)DevAddr;
|
||||
pHITI2C->pTxBuffPtr = pData;
|
||||
pHITI2C->TxXferCount = Size;
|
||||
|
||||
if( (int)pHITI2C->pHI2C == (int)I2C0 )
|
||||
sys_open_IRQ(I2C0_IRQn);
|
||||
|
||||
REG_WRITE_MASK(pHITI2C->pHI2C->CTLSET,
|
||||
I2C_CTLSET_STA_Msk | I2C_CTLSET_SI_Msk,
|
||||
I2C_CTLSET_STA_Msk | I2C_CTLSET_SI_Msk);
|
||||
|
||||
return I2C_Err_OK;
|
||||
}
|
||||
|
||||
I2C_ErrTypeDef I2C_Master_Receive_IT(I2C_IT_HandleTypeDef *pHITI2C, uint8_t DevAddr, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
pHITI2C->XferMode = I2C_XferMode_Recevie;
|
||||
pHITI2C->DevAddress = (uint8_t)DevAddr;
|
||||
pHITI2C->pRxBuffPtr = pData;
|
||||
pHITI2C->RxXferCount = Size;
|
||||
|
||||
if( (int)pHITI2C->pHI2C == (int)I2C0 )
|
||||
sys_open_IRQ(I2C0_IRQn);
|
||||
|
||||
REG_WRITE_MASK(pHITI2C->pHI2C->CTLSET,
|
||||
I2C_CTLSET_STA_Msk | I2C_CTLSET_SI_Msk,
|
||||
I2C_CTLSET_STA_Msk | I2C_CTLSET_SI_Msk);
|
||||
|
||||
return I2C_Err_OK;
|
||||
}
|
||||
|
||||
I2C_ErrTypeDef I2C_Slave_Transmit_IT(I2C_IT_HandleTypeDef *pHITI2C, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
pHITI2C->XferMode = I2C_XferMode_Transmite;
|
||||
pHITI2C->pTxBuffPtr = pData;
|
||||
pHITI2C->TxXferCount = Size;
|
||||
|
||||
_I2C_SET_SI_FLAG(pHITI2C->pHI2C);
|
||||
if( (int)pHITI2C->pHI2C == (int)I2C0 )
|
||||
sys_open_IRQ(I2C0_IRQn);
|
||||
|
||||
return I2C_Err_OK;
|
||||
}
|
||||
|
||||
I2C_ErrTypeDef I2C_Slave_Receive_IT(I2C_IT_HandleTypeDef *pHITI2C, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
pHITI2C->XferMode = I2C_XferMode_Recevie;
|
||||
pHITI2C->pRxBuffPtr = pData;
|
||||
pHITI2C->RxXferCount = Size;
|
||||
|
||||
_I2C_SET_SI_FLAG(pHITI2C->pHI2C);
|
||||
if( (int)pHITI2C->pHI2C == (int)I2C0 )
|
||||
sys_open_IRQ(I2C0_IRQn);
|
||||
|
||||
return I2C_Err_OK;
|
||||
}
|
||||
|
||||
void I2C_Master_IRQHandler(I2C_IT_HandleTypeDef *pHITI2C)
|
||||
{
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
|
||||
if( pHITI2C->XferMode == I2C_XferMode_Transmite )
|
||||
{
|
||||
if( pHITI2C->DevAddress & 0x8000 )
|
||||
{
|
||||
// xfer data stage, if pHITI2C->TxXferCount == 0, I2C should send STOP-bit
|
||||
rval = _I2C_Master_Send_Byte(pHITI2C->pHI2C, &pHITI2C->pTxBuffPtr, (pHITI2C->TxXferCount) ? false : true);
|
||||
if( rval == I2C_SwState_SUCCESS )
|
||||
pHITI2C->TxXferCount--;
|
||||
|
||||
if( pHITI2C->TxXferCount == 0xFFFF )
|
||||
{
|
||||
pHITI2C->XferMode = I2C_XferMode_Idle;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
uint8_t *pAddr = 0;
|
||||
|
||||
pHITI2C->DevAddress &= ~0x1u; // write mode
|
||||
|
||||
pAddr = (uint8_t*)&pHITI2C->DevAddress;
|
||||
rval = _I2C_Master_Send_Byte(pHITI2C->pHI2C, &pAddr, false);
|
||||
if( rval == I2C_SwState_SUCCESS )
|
||||
pHITI2C->DevAddress |= 0x8000;
|
||||
}
|
||||
}
|
||||
else if( pHITI2C->XferMode == I2C_XferMode_Recevie )
|
||||
{
|
||||
if( pHITI2C->DevAddress & 0x8000 )
|
||||
{
|
||||
rval = _I2C_Master_Recv_Byte(pHITI2C->pHI2C, &pHITI2C->pRxBuffPtr, (pHITI2C->RxXferCount - 2) ? false : true);
|
||||
if( rval == I2C_SwState_SUCCESS )
|
||||
pHITI2C->RxXferCount--;
|
||||
|
||||
if( pHITI2C->RxXferCount == 0 )
|
||||
{
|
||||
pHITI2C->XferMode = I2C_XferMode_Idle;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
uint8_t *pAddr = 0;
|
||||
|
||||
pHITI2C->DevAddress |= 0x1u; // read mode
|
||||
|
||||
pAddr = (uint8_t*)&pHITI2C->DevAddress;
|
||||
rval = _I2C_Master_Recv_Byte(pHITI2C->pHI2C, &pAddr, false);
|
||||
if( rval == I2C_SwState_SUCCESS )
|
||||
{
|
||||
pHITI2C->DevAddress |= 0x8000;
|
||||
|
||||
/**
|
||||
* send DevAddr+R and then receive data
|
||||
* ps. Decrease the DevAddr+R byte
|
||||
*/
|
||||
pHITI2C->RxXferCount++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void I2C_Slave_IRQHandler(I2C_IT_HandleTypeDef *pHITI2C)
|
||||
{
|
||||
I2C_SwState rval = I2C_SwState_SUCCESS;
|
||||
|
||||
if( pHITI2C->XferMode == I2C_XferMode_Transmite )
|
||||
{
|
||||
bool HasRecvAddr = false;
|
||||
|
||||
// xfer data stage, if pHITI2C->TxXferCount == 0, I2C should send STOP-bit
|
||||
rval = _I2C_Slave_Send_Byte(pHITI2C->pHI2C, &pHITI2C->pTxBuffPtr, &HasRecvAddr, (pHITI2C->TxXferCount) ? false : true);
|
||||
pHITI2C->TxXferCount = (rval == I2C_SwState_SUCCESS) ? pHITI2C->TxXferCount - 1 :
|
||||
(rval == I2C_SwState_FORCE_STOP) ? 0xFFFF :
|
||||
pHITI2C->TxXferCount;
|
||||
|
||||
if( pHITI2C->TxXferCount == 0xFFFF )
|
||||
{
|
||||
pHITI2C->XferMode = I2C_XferMode_Idle;
|
||||
}
|
||||
}
|
||||
else if( pHITI2C->XferMode == I2C_XferMode_Recevie )
|
||||
{
|
||||
rval = _I2C_Slave_Recv_Byte(pHITI2C->pHI2C, &pHITI2C->pRxBuffPtr, (pHITI2C->RxXferCount == 2));
|
||||
|
||||
pHITI2C->RxXferCount = (rval == I2C_SwState_SUCCESS) ? pHITI2C->RxXferCount - 1 :
|
||||
(rval == I2C_SwState_FORCE_STOP) ? 0 :
|
||||
pHITI2C->RxXferCount;
|
||||
|
||||
if( pHITI2C->RxXferCount == 0 )
|
||||
{
|
||||
pHITI2C->XferMode = I2C_XferMode_Idle;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ENABLE_HAL_I2C */
|
||||
@@ -53,18 +53,18 @@ void LPTIM_Init(LPTIM_Type *pHLpTim, LPTIM_InitTypeDef *pInit)
|
||||
{
|
||||
if( pHLpTim == LPTIM )
|
||||
{
|
||||
// ToDo: reset module
|
||||
__HAL_SYSCFG_RESET_LPTIM();
|
||||
__HAL_SYSCFG_LPTIM_CLK_ENABLE();
|
||||
REG_WRITE_MASK(pHLpTim->TCR, LPTIM_TCR_CLKS_Msk, pInit->LPTIM_ClockSource);
|
||||
}
|
||||
else if( pHLpTim == TIM0 )
|
||||
{
|
||||
// ToDo: reset module
|
||||
__HAL_SYSCFG_RESET_TIM0();
|
||||
__HAL_SYSCFG_TIM0_CLK_ENABLE();
|
||||
}
|
||||
else if( pHLpTim == TIM1 )
|
||||
{
|
||||
// ToDo: reset module
|
||||
__HAL_SYSCFG_RESET_TIM1();
|
||||
__HAL_SYSCFG_TIM1_CLK_ENABLE();
|
||||
}
|
||||
|
||||
@@ -18,8 +18,12 @@
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
#define __PWR_WAIT_RECHARGE() do{ __NOP(); __NOP(); __NOP(); __NOP(); \
|
||||
}while(0)
|
||||
#if 1
|
||||
#define __PWR_WAIT_RECHARGE() do{ __NOP(); __NOP(); __NOP(); __NOP(); \
|
||||
}while(0)
|
||||
#else
|
||||
#define __PWR_WAIT_RECHARGE()
|
||||
#endif
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
@@ -39,31 +43,31 @@
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
void PWR_SetAutoWakeUp(uint32_t msec)
|
||||
void PWR_EnterSleepMode(CallbaskPreSleepTypeDef cb_pre_set,
|
||||
CallbaskPostSleepTypeDef cb_post_set)
|
||||
{
|
||||
sys_config_systick(msec * SYS_TICK_1_MS);
|
||||
return;
|
||||
}
|
||||
int wakeup_type = 0;
|
||||
|
||||
void PWR_EnterSleepMode(CallbaskPreDeepsleepTypeDef cb_pre_set,
|
||||
CallbaskPostDeepsleepTypeDef cb_post_set)
|
||||
{
|
||||
sys_disable_girq();
|
||||
|
||||
if( cb_pre_set )
|
||||
cb_pre_set();
|
||||
cb_pre_set(PWR_Mode_Sleep, (PWR_WakeupTypeDef*)&wakeup_type);
|
||||
|
||||
__HAL_SYSCFG_AMISC_CLK_ENABLE();
|
||||
|
||||
AMISC_SetHSIPwrSrc(AMISC_HSIPwrSrc_LowPower);
|
||||
|
||||
REG_WRITE(AMISC->DAC_CR, 0x0ul); // Off DAC leakage
|
||||
|
||||
__set_wfi_sleepmode(WFI_SHALLOW_SLEEP);
|
||||
|
||||
SYSCFG_SetLowPower(true);
|
||||
|
||||
__WFI();
|
||||
__PWR_WAIT_RECHARGE();
|
||||
/* __PWR_WAIT_RECHARGE(); */
|
||||
|
||||
if( cb_post_set )
|
||||
cb_post_set();
|
||||
cb_post_set(PWR_Mode_Sleep);
|
||||
|
||||
SYSCFG_SetLowPower(false);
|
||||
AMISC_SetHSIPwrSrc(AMISC_HSIPwrSrc_Normal);
|
||||
|
||||
sys_enable_girq();
|
||||
|
||||
@@ -71,26 +75,55 @@ void PWR_EnterSleepMode(CallbaskPreDeepsleepTypeDef cb_pre_set,
|
||||
}
|
||||
|
||||
|
||||
void PWR_EnterDeepSleepMode(CallbaskPreDeepsleepTypeDef cb_pre_set,
|
||||
CallbaskPostDeepsleepTypeDef cb_post_set)
|
||||
void PWR_EnterDeepSleepMode(CallbaskPreSleepTypeDef cb_pre_set,
|
||||
CallbaskPostSleepTypeDef cb_post_set)
|
||||
{
|
||||
uint32_t value = 0;
|
||||
int wakeup_type = 0;
|
||||
|
||||
sys_disable_girq();
|
||||
|
||||
if( cb_pre_set )
|
||||
cb_pre_set();
|
||||
cb_pre_set(PWR_Mode_DeepSleep, (PWR_WakeupTypeDef*)&wakeup_type);
|
||||
|
||||
__set_wfi_sleepmode(WFI_DEEP_SLEEP);
|
||||
__HAL_SYSCFG_AMISC_CLK_ENABLE();
|
||||
|
||||
AMISC_SetHSIPwrSrc(AMISC_HSIPwrSrc_LowPower);
|
||||
|
||||
REG_WRITE(AMISC->DAC_CR, 0x0ul); // Off DAC leakage
|
||||
|
||||
SYSCFG_SetLowPower(true);
|
||||
|
||||
/* Close the clocks of all peripheral */
|
||||
value = 0x0ul;
|
||||
if( wakeup_type & PWR_Wakeup_LpTIM )
|
||||
{
|
||||
value |= SYSCFG_PCLKEN_LPTIM_Msk;
|
||||
}
|
||||
|
||||
if( wakeup_type & PWR_Wakeup_WDG )
|
||||
{
|
||||
value |= SYSCFG_PCLKEN_WDG_Msk;
|
||||
}
|
||||
|
||||
REG_WRITE(SYSCFG->PCLKEN, value);
|
||||
|
||||
REG_WRITE(SYSCFG->HCLKEN, SYSCFG_HCLKEN_GPIOB_Msk | SYSCFG_HCLKEN_GPIOA_Msk);
|
||||
|
||||
__set_wfi_sleepmode(WFI_DEEP_SLEEP);
|
||||
|
||||
__WFI();
|
||||
__PWR_WAIT_RECHARGE();
|
||||
|
||||
if( cb_post_set )
|
||||
cb_post_set();
|
||||
|
||||
SYSCFG_SetLowPower(false);
|
||||
|
||||
__HAL_SYSCFG_AMISC_CLK_ENABLE();
|
||||
AMISC_SetHSIPwrSrc(AMISC_HSIPwrSrc_Normal);
|
||||
__HAL_SYSCFG_AMISC_CLK_DISABLE();
|
||||
|
||||
if( cb_post_set )
|
||||
cb_post_set(PWR_Mode_DeepSleep);
|
||||
|
||||
sys_enable_girq();
|
||||
|
||||
return;
|
||||
@@ -494,6 +494,20 @@ void TIM_Cmd(TIM_Type *tim, FunctionalState state)
|
||||
(tim->CR1 &= ~(0x01U << TIM_CR1_CEN_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Asymmetric Mode.
|
||||
* @param tim: select the TIM peripheral.
|
||||
* @param state: new state of the tim peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void TIM_ASYMEN_Cmd(TIM_Type *tim, FunctionalState state)
|
||||
{
|
||||
(state) ? \
|
||||
(tim->CR1 |= (0x01U << TIM_CR1_ASYMEN_Pos)) : \
|
||||
(tim->CR1 &= ~(0x01U << TIM_CR1_ASYMEN_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the TIM peripheral Main Outputs.
|
||||
* @param tim: select the TIM peripheral.
|
||||
@@ -622,10 +636,38 @@ void TIM_PrescalerConfig(TIM_Type *tim, uint16_t prescaler, uint16_t reloadMode)
|
||||
tim->EGR = reloadMode;
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
||||
/**
|
||||
* @brief Configures the External clock Mode1
|
||||
* @param TIMx: where x can be 2, EPWM to select the TIM peripheral.
|
||||
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
||||
* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
|
||||
* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
|
||||
* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
|
||||
* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
|
||||
* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
|
||||
* @param ExtTRGFilter: External Trigger Filter.
|
||||
* This parameter must be a value between 0x00 and 0x0F
|
||||
* @retval None
|
||||
*/
|
||||
void TIM_ETRClockMode1Config(TIM_Type *tim, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
|
||||
{
|
||||
/* Configure the ETR Clock source */
|
||||
TIM_ETRConfig(tim, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
|
||||
|
||||
/* Select the External clock mode1 . Select the Trigger selection : ETRF */
|
||||
REG_WRITE_MASK(tim->SMCR, TIM_SMCR_SMS_Msk | TIM_SMCR_TS_Msk , TIM_SlaveMode_External1 | TIM_TS_ETRF );
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the TIMx Trigger as External Clock
|
||||
* @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
|
||||
* @param TIMx: where x can be 2, EPWM to select the TIM peripheral.
|
||||
* @param TIM_TIxExternalCLKSource: Trigger source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
|
||||
@@ -639,8 +681,7 @@ void TIM_PrescalerConfig(TIM_Type *tim, uint16_t prescaler, uint16_t reloadMode)
|
||||
* This parameter must be a value between 0x0 and 0xF.
|
||||
* @retval None
|
||||
*/
|
||||
void TIM_TIxExternalClockConfig(TIM_Type *TIMx, uint16_t TIM_TIxExternalCLKSource,
|
||||
uint16_t TIM_ICPolarity, uint16_t ICFilter)
|
||||
void TIM_TIxExternalClockConfig(TIM_Type *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
|
||||
{
|
||||
/* Configure the Timer Input Clock Source */
|
||||
|
||||
@@ -650,46 +691,9 @@ void TIM_TIxExternalClockConfig(TIM_Type *TIMx, uint16_t TIM_TIxExternalCLKSourc
|
||||
TIMx->SMCR |= TIM_SlaveMode_External1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the External clock Mode1
|
||||
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
||||
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
||||
* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
|
||||
* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
|
||||
* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
|
||||
* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
|
||||
* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
|
||||
* @param ExtTRGFilter: External Trigger Filter.
|
||||
* This parameter must be a value between 0x00 and 0x0F
|
||||
* @retval None
|
||||
*/
|
||||
void TIM_ETRClockMode1Config(TIM_Type *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter)
|
||||
{
|
||||
uint16_t tmpsmcr = 0;
|
||||
/* Configure the ETR Clock source */
|
||||
TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
|
||||
|
||||
/* Get the TIMx SMCR register value */
|
||||
tmpsmcr = TIMx->SMCR;
|
||||
/* Reset the SMS Bits */
|
||||
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS_Msk));
|
||||
/* Select the External clock mode1 */
|
||||
tmpsmcr |= TIM_SlaveMode_External1;
|
||||
/* Select the Trigger selection : ETRF */
|
||||
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS_Msk));
|
||||
tmpsmcr |= TIM_TS_ETRF;
|
||||
/* Write to TIMx SMCR */
|
||||
TIMx->SMCR = tmpsmcr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the External clock Mode2
|
||||
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
||||
* @param TIMx: where x can be 2, EPWM to select the TIM peripheral.
|
||||
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
||||
@@ -704,18 +708,17 @@ void TIM_ETRClockMode1Config(TIM_Type *TIMx, uint16_t TIM_ExtTRGPrescaler, uint1
|
||||
* This parameter must be a value between 0x00 and 0x0F
|
||||
* @retval None
|
||||
*/
|
||||
void TIM_ETRClockMode2Config(TIM_Type *TIMx, uint16_t TIM_ExtTRGPrescaler,
|
||||
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
|
||||
void TIM_ETRClockMode2Config(TIM_Type *tim, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
|
||||
{
|
||||
/* Configure the ETR Clock source */
|
||||
TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
|
||||
TIM_ETRConfig(tim, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
|
||||
/* Enable the External clock mode2 */
|
||||
TIMx->SMCR |= TIM_SMCR_ECE_Msk;
|
||||
tim->SMCR |= TIM_SMCR_ECE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the TIMx External Trigger (ETR).
|
||||
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
||||
* @param TIMx: where x can be 2, EPWM to select the TIM peripheral.
|
||||
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
||||
@@ -730,19 +733,10 @@ void TIM_ETRClockMode2Config(TIM_Type *TIMx, uint16_t TIM_ExtTRGPrescaler,
|
||||
* This parameter must be a value between 0x00 and 0x0F
|
||||
* @retval None
|
||||
*/
|
||||
void TIM_ETRConfig(TIM_Type *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter)
|
||||
void TIM_ETRConfig(TIM_Type *tim, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,uint16_t ExtTRGFilter)
|
||||
{
|
||||
uint16_t tmpsmcr = 0;
|
||||
tmpsmcr = TIMx->SMCR;
|
||||
/* Reset the ETR Bits */
|
||||
tmpsmcr &= SMCR_ETR_Mask;
|
||||
/* Set the Prescaler, the Filter value and the Polarity */
|
||||
tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
|
||||
/* Write to TIMx SMCR */
|
||||
TIMx->SMCR = tmpsmcr;
|
||||
REG_WRITE_MASK(tim->SMCR, TIM_SMCR_ETPS_Msk | TIM_SMCR_ETP_Msk | TIM_SMCR_ETF_Msk,TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | ExtTRGFilter << TIM_SMCR_ETF_Pos);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Specifies the tim Counter Mode to be used.
|
||||
@@ -1386,6 +1380,49 @@ void TIM_SetCompare4(TIM_Type *tim, uint32_t compare)
|
||||
tim->CCR4 = (uint16_t)compare;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the tim Downwards Compare1 Register value
|
||||
* @param tim: select the TIM peripheral.
|
||||
* @param compare: specifies the Capture Compare1 register new value.
|
||||
* @retval None.
|
||||
*/
|
||||
void TIM_SetDownCompare1(TIM_Type *tim, uint32_t compare)
|
||||
{
|
||||
tim->CCDR1 = (uint16_t)compare;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the tim Downwards Compare2 Register value
|
||||
* @param tim: select the TIM peripheral.
|
||||
* @param compare: specifies the Capture Compare2 register new value.
|
||||
* @retval None.
|
||||
*/
|
||||
void TIM_SetDownCompare2(TIM_Type *tim, uint32_t compare)
|
||||
{
|
||||
tim->CCDR2 = (uint16_t)compare;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the tim Downwards Compare3 Register value
|
||||
* @param tim: select the TIM peripheral.
|
||||
* @param compare: specifies the Capture Compare3 register new value.
|
||||
* @retval None.
|
||||
*/
|
||||
void TIM_SetDownCompare3(TIM_Type *tim, uint32_t compare)
|
||||
{
|
||||
tim->CCDR3 = (uint16_t)compare;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the tim Downwards Compare4 Register value
|
||||
* @param tim: select the TIM peripheral.
|
||||
* @param compare: specifies the Capture Compare4 register new value.
|
||||
* @retval None.
|
||||
*/
|
||||
void TIM_SetDownCompare4(TIM_Type *tim, uint32_t compare)
|
||||
{
|
||||
tim->CCDR4 = (uint16_t)compare;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the tim Input Capture 1 value.
|
||||
@@ -1541,9 +1578,6 @@ void TIM_ClearITPendingBit(TIM_Type *tim, uint32_t it)
|
||||
tim->SR &= ~it;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified TIM flag is set or not.
|
||||
* @param tim: select the TIM peripheral.
|
||||
@@ -1554,4 +1588,60 @@ FlagStatus TIM_GetCountDirection(TIM_Type *tim)
|
||||
return ((tim->CR1 &TIM_CR1_DIR_Msk) ? SET : RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears or safeguards the OCREF1 signal on an external event
|
||||
* @param tim: where tim can be 2,EPWM to select the TIM peripheral.
|
||||
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
||||
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
||||
* @retval None
|
||||
*/
|
||||
void TIM_ClearOC1Ref(TIM_Type *tim, uint16_t TIM_OCClear)
|
||||
{
|
||||
REG_WRITE_MASK(TIM->CCMR1_OUTPUT, TIM_CCMR1_OUTPUT_OC1CE_Msk, TIM_OCClear);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears or safeguards the OCREF2 signal on an external event
|
||||
* @param tim: where tim can be 2,EPWM to select the TIM peripheral.
|
||||
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
||||
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
||||
* @retval None
|
||||
*/
|
||||
void TIM_ClearOC2Ref(TIM_Type *tim, uint16_t TIM_OCClear)
|
||||
{
|
||||
REG_WRITE_MASK(TIM->CCMR1_OUTPUT, TIM_CCMR1_OUTPUT_OC2CE_Msk, TIM_OCClear << 8);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears or safeguards the OCREF3 signal on an external event
|
||||
* @param tim: where tim can be 2,EPWM to select the TIM peripheral.
|
||||
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
||||
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
||||
* @retval None
|
||||
*/
|
||||
void TIM_ClearOC3Ref(TIM_Type *tim, uint16_t TIM_OCClear)
|
||||
{
|
||||
REG_WRITE_MASK(TIM->CCMR2_OUTPUT, TIM_CCMR2_OUTPUT_OC3CE_Msk, TIM_OCClear);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears or safeguards the OCREF4 signal on an external event
|
||||
* @param tim: where tim can be 2,EPWM to select the TIM peripheral.
|
||||
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
||||
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
||||
* @retval None
|
||||
*/
|
||||
void TIM_ClearOC4Ref(TIM_Type *tim, uint16_t TIM_OCClear)
|
||||
{
|
||||
REG_WRITE_MASK(TIM->CCMR2_OUTPUT, TIM_CCMR2_OUTPUT_OC4CE_Msk, TIM_OCClear << 8);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ENABLE_HAL_TIM2 || CONFIG_ENABLE_HAL_EPWM */
|
||||
@@ -62,15 +62,16 @@ void WDG_BaseStructInit(WDG_BaseInitTypeDef *init_struct)
|
||||
*/
|
||||
void WDG_BaseInit( WDG_BaseInitTypeDef *init_struct)
|
||||
{
|
||||
__HAL_SYSCFG_WDG_CLK_ENABLE();
|
||||
__HAL_SYSCFG_RESET_WDG();
|
||||
__HAL_SYSCFG_WDG_CLK_ENABLE();
|
||||
|
||||
WDG_Unlock();
|
||||
WDG_Unlock();
|
||||
|
||||
WDG->LOAD = init_struct->Relaod;
|
||||
REG_WRITE_MASK(WDG->CR, WDG_CR_RSTE_Msk, init_struct->Reset);
|
||||
REG_WRITE_MASK(WDG->CR, WDG_CR_DBGE_Msk, init_struct->Debug);
|
||||
WDG->LOAD = init_struct->Relaod;
|
||||
REG_WRITE_MASK(WDG->CR, WDG_CR_RSTE_Msk, init_struct->Reset);
|
||||
REG_WRITE_MASK(WDG->CR, WDG_CR_DBGE_Msk, init_struct->Debug);
|
||||
|
||||
WDG_Clear();
|
||||
WDG_Clear();
|
||||
|
||||
}
|
||||
|
||||
@@ -94,7 +95,7 @@ void WDG_SetReload(uint32_t reload)
|
||||
*/
|
||||
void WDG_Enable(void)
|
||||
{
|
||||
REG_SET_BITS(WDG->CR, WDG_CR_INTE_Msk);
|
||||
REG_SET_BITS(WDG->CR, WDG_CR_INTE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -104,7 +105,7 @@ void WDG_Enable(void)
|
||||
*/
|
||||
void WDG_Disable(void)
|
||||
{
|
||||
REG_CLR_BITS(WDG->CR, WDG_CR_INTE_Msk);
|
||||
REG_CLR_BITS(WDG->CR, WDG_CR_INTE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -161,7 +162,7 @@ uint32_t WDG_GetMIF(uint32_t mif_bit_mask)
|
||||
*/
|
||||
void WDG_Unlock(void)
|
||||
{
|
||||
WDG->LOCK = 0x1ACCE551;
|
||||
WDG->LOCK = 0x1ACCE551;
|
||||
}
|
||||
/**
|
||||
* @brief Lock the WDG so thatit cannot be overwritten
|
||||
@@ -170,7 +171,7 @@ void WDG_Unlock(void)
|
||||
*/
|
||||
void WDG_Lock(void)
|
||||
{
|
||||
WDG->LOCK = 0;
|
||||
WDG->LOCK = 0;
|
||||
}
|
||||
/**
|
||||
* @brief Get WDG lock status. This Value is only read.
|
||||
+3
-3
@@ -19569,7 +19569,7 @@ __STATIC_FORCEINLINE unsigned long __RV_DREDAS16(unsigned long long a)
|
||||
* Do halfs reduced subtraction and halfs reduced addition from a register. The result is written to Rd.
|
||||
*
|
||||
* **Description**:\n
|
||||
* For the `DREDSA16` instruction, add the top 16-bit Q15 element from the bottom 16-bit Q15 element of the bottom 32-bit Q31 content of 64-bit chunks in Rs1. At the same time, subtract the the top16-bit Q15 element with the bottom16-bit Q15 element of the top 32-bit Q31 content of 64-bit chunks in Rs1. The two Q15 results are then written into Rd.
|
||||
* For the `DREDSA16` instruction, add the top 16-bit Q15 element from the bottom 16-bit Q15 element of the bottom 32-bit Q31 content of 64-bit chunks in Rs1. At the same time, subtract the the top16-bit Q15 element with the bottom16-bit Q15 element of the top 32-bit Q31 content of 64-bit chunks in Rs1. The two Q15 results are then written into Rd.
|
||||
*
|
||||
* **Operations**:\n
|
||||
* ~~~
|
||||
@@ -20445,7 +20445,7 @@ __STATIC_FORCEINLINE unsigned long long __RV_DPKBT16(unsigned long long a, unsig
|
||||
*
|
||||
* **Purpose**:\n
|
||||
* Pack 16-bit data from 32-bit chunks in two registers.
|
||||
* * PKTT16 top.top
|
||||
* * PKTT16 top.top
|
||||
*
|
||||
* **Description**:\n
|
||||
* This instruction moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
|
||||
@@ -23979,7 +23979,7 @@ __STATIC_FORCEINLINE long __RV_DMADA32(long long t, unsigned long long a, unsign
|
||||
*
|
||||
* **Purpose**:\n
|
||||
* Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit content of the corresponding 32-bit
|
||||
* elements of another register and add the results with a 64-bit value of an even/odd pair of registers. The addition result
|
||||
* elements of another register and add the results with a 64-bit value of an even/odd pair of registers. The addition result
|
||||
* is written back to the register-pair.
|
||||
* * DSMALBB: rt pair + bottom*bottom (all 32-bit elements)
|
||||
*
|
||||
@@ -0,0 +1,92 @@
|
||||
#
|
||||
# component Makefile
|
||||
#
|
||||
|
||||
|
||||
#=======================================
|
||||
# Configurations
|
||||
#=======================================
|
||||
|
||||
#
|
||||
# Drivers of MCU
|
||||
#
|
||||
|
||||
SOC_CPU_NAME = n203e
|
||||
|
||||
#=======================================
|
||||
# system
|
||||
#=======================================
|
||||
ifeq ("$(SOC)","pec930")
|
||||
C_DEFS += -DCONFIG_USE_PEC930
|
||||
else
|
||||
$(error "Unknown SoC !!!")
|
||||
endif
|
||||
|
||||
#
|
||||
# cpu
|
||||
#
|
||||
C_DEFS += -DCONFIG_CPU_N203E -DCONFIG_HAS_BPU
|
||||
|
||||
CPU_FLAGS = -mabi=ilp32e -mcmodel=medlow
|
||||
CPU_FLAGS += -march=rv32emc_zba_zbb_zbs_zca_zcb_zcmp_zcmt_zicond
|
||||
|
||||
|
||||
#
|
||||
# Source
|
||||
#
|
||||
ASM_SOURCES := \
|
||||
$(srctree)/Drivers/PEC930/Device/src/Startup/startup.S \
|
||||
$(srctree)/Drivers/PEC930/Device/src/Startup/trap.S
|
||||
|
||||
C_SOURCES += \
|
||||
$(srctree)/Drivers/PEC930/Device/src/interrupt.c \
|
||||
$(srctree)/Drivers/PEC930/Device/src/syscalls.c \
|
||||
$(srctree)/Drivers/PEC930/Device/src/system_dev.c
|
||||
|
||||
C_INCLUDES += \
|
||||
-I$(srctree)/Drivers/PEC930/Device/inc \
|
||||
-I$(srctree)/Drivers/PEC930/NMSIS/Core/Include \
|
||||
-I$(srctree)/Drivers/PEC930/
|
||||
|
||||
|
||||
|
||||
#=======================================
|
||||
# peripheral hal driver
|
||||
#=======================================
|
||||
C_SOURCES += \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_adc.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_amisc.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_comp.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_opamp.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_crc.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_dsp.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_flash.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_gpio.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_i2c.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_lptim.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_pwr.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_spi.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_syscfg.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_tim.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_uart.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_wdg.c \
|
||||
$(srctree)/Drivers/PEC930/HAL_Lib/src/hal_device.c
|
||||
|
||||
C_INCLUDES += \
|
||||
-I$(srctree)/Drivers/PEC930/HAL_Lib/inc
|
||||
|
||||
#=======================================
|
||||
# BSP
|
||||
#=======================================
|
||||
C_SOURCES += $(srctree)/Drivers/PEC930/BSP/StarterKit/starterkit.c
|
||||
|
||||
C_INCLUDES += \
|
||||
-I$(srctree)/Drivers/PEC930/BSP/StarterKit
|
||||
|
||||
#=======================================
|
||||
# Flags
|
||||
#=======================================
|
||||
CFLAGS += $(CPU_FLAGS)
|
||||
CXXFLAGS +=
|
||||
LDFLAGS += $(CPU_FLAGS)
|
||||
LIBDIR +=
|
||||
@@ -1,59 +0,0 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file isr.h
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/09/16
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
#ifndef __isr_H_wuraIpBA_lTJm_HvJw_sNDo_uEd5JnucTReY__
|
||||
#define __isr_H_wuraIpBA_lTJm_HvJw_sNDo_uEd5JnucTReY__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
/**
|
||||
* ISRs of Internal Interrupt of IRQC
|
||||
*/
|
||||
void irqc_mtip_handler(void);
|
||||
void irqc_msip_handler(void);
|
||||
|
||||
/**
|
||||
* ISRs of External Interrupt of IRQC
|
||||
*/
|
||||
void irqc_uart_handler(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,50 +0,0 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file isr.c
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/09/16
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
|
||||
#include "main.h"
|
||||
#include "isr.h"
|
||||
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
/**
|
||||
* \brief System Software ISR
|
||||
*
|
||||
* \return None
|
||||
*/
|
||||
__INTERRUPT void irqc_msip_handler(void)
|
||||
{
|
||||
sys_clear_swi();
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -1,401 +0,0 @@
|
||||
/**
|
||||
* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
|
||||
*/
|
||||
/** @file main.c
|
||||
*
|
||||
* @author Wei-Lun Hsu
|
||||
* @version 0.1
|
||||
* @date 2024/08/29
|
||||
* @license
|
||||
* @description
|
||||
*/
|
||||
|
||||
|
||||
#include "main.h"
|
||||
#include "isr.h"
|
||||
//=============================================================================
|
||||
// Constant Definition
|
||||
//=============================================================================
|
||||
//#define ENABLE_IIC_INT
|
||||
//=============================================================================
|
||||
// Macro Definition
|
||||
//=============================================================================
|
||||
#define EEPROM_I2C_ADDRESS 0xA0
|
||||
uint32_t testFlasg = 0;
|
||||
uint32_t errCounter = 0;
|
||||
uint32_t delay = 0;
|
||||
uint8_t i = 0;
|
||||
uint8_t ReadBuffer[20], WriteBuffer[20];
|
||||
//=============================================================================
|
||||
// Structure Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Global Data Definition
|
||||
//=============================================================================
|
||||
|
||||
//=============================================================================
|
||||
// Private Function Definition
|
||||
//=============================================================================
|
||||
void I2C_Configure(void);
|
||||
void I2C_Handler(void);
|
||||
void I2C_TxData_Polling(uint8_t *Buffer, uint8_t Length);
|
||||
void EEPROM_WriteData(uint8_t Address, uint8_t *Buffer, uint8_t Length);
|
||||
void EEPROM_WritePage(uint8_t Address, uint8_t *Buffer, uint8_t Length);
|
||||
void I2C_RxData_Polling(uint8_t *Buffer, uint16_t Length);
|
||||
void EEPROM_ReadData(uint8_t Address, uint8_t *Buffer, uint8_t Length);
|
||||
void I2C_Send_WriteAddr(I2C_Type *i2c,uint8_t address);
|
||||
void I2C_Send_ReadAddr(I2C_Type *i2c,uint8_t address);
|
||||
|
||||
void EEPROM_GenerateSTART(I2C_Type *i2c, FunctionalState state);
|
||||
void EEPROM_GenerateRESTART(I2C_Type *i2c, FunctionalState state);
|
||||
void EEPROM_Send_WriteAddr(I2C_Type *i2c, uint8_t address);
|
||||
void I2C_Send_ReadAddr(I2C_Type *i2c,uint8_t address);
|
||||
void EEPROM_Send_Data(I2C_Type *i2c, uint8_t data);
|
||||
void EEPROM_GenerateSTOP(I2C_Type *i2c, FunctionalState state);
|
||||
|
||||
|
||||
void I2C_Master_EEPROM_Polling_Sample(void);
|
||||
//=============================================================================
|
||||
// Public Function Definition
|
||||
//=============================================================================
|
||||
int main(void)
|
||||
{
|
||||
SYSCFG_ClkInitTypeDef SysClkInit = {0};
|
||||
|
||||
SysClkInit.ClkSource = SYSCFG_ClkSrc_HSI;
|
||||
SYSCFG_SysClkConfig(&SysClkInit);
|
||||
|
||||
sys_config_systick(SYS_TICK_1_MS);
|
||||
|
||||
I2C_Master_EEPROM_Polling_Sample();
|
||||
|
||||
while(1)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void I2C_Master_EEPROM_Polling_Sample(void)
|
||||
{
|
||||
I2C_Configure();
|
||||
|
||||
for (i = 0; i < 20; i++)
|
||||
{
|
||||
ReadBuffer[i] = 0;
|
||||
WriteBuffer[i] = i + 0x10;
|
||||
}
|
||||
|
||||
EEPROM_GenerateSTART(I2C,ENABLE);
|
||||
EEPROM_Send_WriteAddr(I2C,0xA0);
|
||||
EEPROM_Send_Data(I2C,0x00);
|
||||
EEPROM_Send_Data(I2C,0x00);
|
||||
|
||||
I2C_TxData_Polling((uint8_t *)WriteBuffer, 20);
|
||||
EEPROM_GenerateSTOP(I2C,ENABLE);
|
||||
|
||||
for(delay = 0;delay <0x1000; delay ++);
|
||||
|
||||
EEPROM_GenerateSTART(I2C,ENABLE);
|
||||
EEPROM_Send_WriteAddr(I2C,0xA0);
|
||||
EEPROM_Send_Data(I2C,0x00);
|
||||
EEPROM_Send_Data(I2C,0x00);
|
||||
|
||||
EEPROM_GenerateRESTART(I2C,ENABLE);
|
||||
I2C_Send_ReadAddr(I2C,0xA1);
|
||||
|
||||
I2C_RxData_Polling((uint8_t *)ReadBuffer, 20);
|
||||
EEPROM_GenerateSTOP(I2C,ENABLE);
|
||||
|
||||
for (i = 0; i < 20; i++)
|
||||
{
|
||||
if(WriteBuffer[i] != ReadBuffer[i])
|
||||
{
|
||||
errCounter ++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void I2C_Configure(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
I2C_InitTypeDef I2C_InitStruct;
|
||||
|
||||
I2C_StructInit(&I2C_InitStruct);
|
||||
I2C_InitStruct.I2C_Mode = I2C_Mode_Master;
|
||||
I2C_InitStruct.I2C_OwnAddress = 0x00;
|
||||
I2C_InitStruct.I2C_ClockDiv = I2C_CLK_Div960;
|
||||
I2C_Init(I2C,&I2C_InitStruct);
|
||||
|
||||
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_00 | GPIO_Pin_01;
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStruct.GPIO_AF_Mode = GPIO_AF_3;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
I2C_TargetAddressConfig(I2C,EEPROM_I2C_ADDRESS);
|
||||
#ifdef ENABLE_IIC_INT
|
||||
I2C_ITConfig(I2C, ENABLE);
|
||||
sys_irq_attr_t irq_attr = { .trig_mode = SYS_IRQ_TRIGGER_LEVEL, };
|
||||
sys_register_IRQ(I2C0_IRQn, I2C_Handler, &irq_attr);
|
||||
__enable_irq();
|
||||
# endif
|
||||
I2C_Cmd(I2C, ENABLE);
|
||||
}
|
||||
|
||||
void EEPROM_WriteData(uint8_t Address, uint8_t *Buffer, uint8_t Length)
|
||||
{
|
||||
/****************SEND_START****************/
|
||||
I2C_GenerateSTART(I2C,ENABLE);
|
||||
while (RESET == I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK))
|
||||
{
|
||||
|
||||
}
|
||||
EEPROM_WritePage(Address, Buffer, EEPROM_PAGE_SIZE);
|
||||
}
|
||||
|
||||
void EEPROM_WritePage(uint8_t Address, uint8_t *Buffer, uint8_t Length)
|
||||
{
|
||||
I2C_Send_WriteAddr(I2C,Address);
|
||||
|
||||
I2C_TxData_Polling((uint8_t *)Buffer, Length);
|
||||
|
||||
I2C_GenerateSTOP(I2C, ENABLE);
|
||||
I2C_ITConfig(I2C, DISABLE);
|
||||
while (!I2C_GetFlagStatus(I2C, I2C_BUS_FREE))
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void I2C_TxData_Polling(uint8_t *Buffer, uint8_t Length)
|
||||
{
|
||||
uint8_t i = 0;
|
||||
|
||||
for (i = 0; i < Length; i++)
|
||||
{
|
||||
I2C_SendData(I2C, Buffer[i]);
|
||||
I2C_StaFlagConfig(I2C,I2C_STA_RESET,I2C_STO_RESET,I2C_SI_RESET,I2C_AA_RESET);
|
||||
while (RESET == I2C_GetFlagStatus(I2C, I2C_MASTER_WRDATEND_ACK));
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void I2C_Send_WriteAddr(I2C_Type *i2c,uint8_t address)
|
||||
{
|
||||
I2C_SendData(i2c, address);
|
||||
REG_WRITE_MASK(i2c->CTLCLR, I2C_CTLCLR_SI_Msk, 1 << I2C_CTLCLR_SI_Pos);
|
||||
while (RESET == I2C_GetFlagStatus(i2c, I2C_MASTER_WRDEVADREND_ACK));
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void EEPROM_ReadData(uint8_t Address, uint8_t *Buffer, uint8_t Length)
|
||||
{
|
||||
|
||||
|
||||
|
||||
I2C_GenerateSTART(I2C,ENABLE);
|
||||
I2C_ITConfig(I2C, DISABLE);
|
||||
// I2C_StaFlagConfig(I2C,I2C_STA_SET,I2C_STO_RESET,I2C_SI_RESET,I2C_AA_RESET);
|
||||
while (RESET == I2C_GetFlagStatus(I2C, I2C_MASTER_RPTSTART_ACK))
|
||||
{
|
||||
|
||||
}
|
||||
I2C_Send_ReadAddr(I2C,0xA1);
|
||||
|
||||
I2C_RxData_Polling((uint8_t *)Buffer, Length);
|
||||
|
||||
I2C_GenerateSTOP(I2C, ENABLE);
|
||||
|
||||
while (!I2C_GetITStatus(I2C, I2C_BUS_FREE))
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void I2C_RxData_Polling(uint8_t *Buffer, uint16_t Length)
|
||||
{
|
||||
uint8_t i = 0;
|
||||
I2C_StaFlagConfig(I2C,I2C_STA_RESET,I2C_STO_RESET,I2C_SI_RESET,I2C_AA_SET);
|
||||
for (i = 0; i < Length; i++)
|
||||
{
|
||||
REG_WRITE_MASK(I2C->CTLCLR, I2C_CTLCLR_SI_Msk, 1 << I2C_CTLCLR_SI_Pos);
|
||||
while (RESET == I2C_GetFlagStatus(I2C, I2C_RXDAT_TXACK));
|
||||
{
|
||||
|
||||
}
|
||||
Buffer[i] = I2C_ReceiveData(I2C);
|
||||
}
|
||||
}
|
||||
|
||||
void EEPROM_GenerateSTART(I2C_Type *i2c, FunctionalState state)
|
||||
{
|
||||
I2C_GenerateSTART(I2C,ENABLE);
|
||||
while (RESET == I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK))
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void EEPROM_GenerateRESTART(I2C_Type *i2c, FunctionalState state)
|
||||
{
|
||||
I2C_GenerateSTART(I2C,ENABLE);
|
||||
I2C_ITConfig(I2C,DISABLE );
|
||||
while (RESET == I2C_GetFlagStatus(I2C, I2C_MASTER_RPTSTART_ACK))
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void EEPROM_Send_WriteAddr(I2C_Type *i2c, uint8_t address)
|
||||
{
|
||||
I2C_Send_WriteAddr(i2c,address);
|
||||
|
||||
I2C_SendData(I2C, 0x00);
|
||||
I2C_StaFlagConfig(I2C,I2C_STA_RESET,I2C_STO_RESET,I2C_SI_RESET,I2C_AA_RESET);
|
||||
while (RESET == I2C_GetFlagStatus(I2C, I2C_MASTER_WRDATEND_ACK));
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void EEPROM_Send_Data(I2C_Type *i2c, uint8_t data)
|
||||
{
|
||||
I2C_SendData(i2c, data);
|
||||
I2C_StaFlagConfig(I2C,I2C_STA_RESET,I2C_STO_RESET,I2C_SI_RESET,I2C_AA_RESET);
|
||||
while (RESET == I2C_GetFlagStatus(I2C, I2C_MASTER_WRDATEND_ACK));
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
void I2C_Send_ReadAddr(I2C_Type *i2c,uint8_t address)
|
||||
{
|
||||
I2C_SendData(i2c, address);
|
||||
REG_WRITE_MASK(i2c->CTLCLR, I2C_CTLCLR_SI_Msk, 1 << I2C_CTLCLR_SI_Pos);
|
||||
while (RESET == I2C_GetFlagStatus(i2c, I2C_MASTER_WRADR_RDCMD_ACK));
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void EEPROM_GenerateSTOP(I2C_Type *i2c, FunctionalState state)
|
||||
{
|
||||
I2C_GenerateSTOP(i2c,ENABLE);
|
||||
I2C_ITConfig(i2c, DISABLE);
|
||||
while (RESET == I2C_GetFlagStatus(I2C, I2C_BUS_FREE))
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
/**********IRQ Number 17**********/
|
||||
__INTERRUPT void I2C_Handler(void)
|
||||
{
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x01,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_RPTSTART_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_RPTSTART_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_WRDEVADREND_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_WRDEVADREND_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_WRDEVADREND_NACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_WRDEVADREND_NACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_WRDATEND_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_WRDATEND_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
if(I2C_GetFlagStatus(I2C, I2C_MASTER_START_ACK) == 1)
|
||||
{
|
||||
printf("I2C_STAT = 0x02,I2C_MASTER_START_ACK Interrupt Successful!/r/n");
|
||||
}
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user