Roy_01
565 lines
29 KiB
C
565 lines
29 KiB
C
/**
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* Copyright (c) 2024 Wei-Lun Hsu. All Rights Reserved.
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*/
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/** @file hal_timer.h
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*
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* @author Wei-Lun Hsu
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* @version 0.1
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* @date 2024/10/17
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* @license
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* @description
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*/
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#ifndef __hal_timer_H_wP2TyFFu_lfcA_HOTx_s6ox_udtPYlP5WVqK__
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#define __hal_timer_H_wP2TyFFu_lfcA_HOTx_s6ox_udtPYlP5WVqK__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "hal_def.h"
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//=============================================================================
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// Constant Definition
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//=============================================================================
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/**
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* @brief TIM Time Base Init structure definition
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*/
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typedef struct
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{
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uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. */
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uint32_t TIM_CounterMode; /*!< Specifies the counter mode. */
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uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active */
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uint32_t TIM_ClockDivision; /*!< Specifies the clock division. */
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uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter */
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} TIM_TimeBaseInitTypeDef;
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/**
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* @brief TIM Output Compare Init structure definition
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*/
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typedef struct
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{
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uint32_t TIM_OCMode; /*!< Specifies the TIM mode. */
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uint32_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. */
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uint32_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. */
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uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. */
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uint32_t TIM_OCPolarity; /*!< Specifies the output polarity. */
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uint32_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. */
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uint32_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. */
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uint32_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. */
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} TIM_OCInitTypeDef;
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/**
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* @brief TIM Input Capture Init structure definition
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*/
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typedef struct
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{
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uint16_t TIM_Channel; /*!< Specifies the TIM channel. */
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uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. */
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uint16_t TIM_ICSelection; /*!< Specifies the input. */
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uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. */
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uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. */
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} TIM_ICInitTypeDef;
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/**
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* @brief BDTR structure definition
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*/
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typedef struct
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{
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uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. */
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uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. */
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uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. */
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uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and */
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uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. */
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uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. */
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uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. */
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uint16_t TIM_DTGFTime; /*!< Specifies the delay time between the switching-off and */
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uint32_t TIM_DTAEState; /*!< Specifies the delay time between the switching-off and */
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} TIM_BDTRInitTypeDef;
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/**
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* @}
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*/
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/** @defgroup TIM_Exported_Constants
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* @{
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*/
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/**
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* @brief TIM_Clock_Division_CKD
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*/
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#define TIM_CKD_Div1 (0x00U << TIM_CR1_CKD_Pos) /*!< TDTS = Tck_tim */
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#define TIM_CKD_Div2 (0x01U << TIM_CR1_CKD_Pos) /*!< TDTS = 2 * Tck_tim */
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#define TIM_CKD_Div4 (0x02U << TIM_CR1_CKD_Pos) /*!< TDTS = 4 * Tck_tim */
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/**
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* @brief TIM_Counter_Mode
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*/
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#define TIM_CounterMode_Up (0x00U << TIM_CR1_DIR_Pos) /*!< TIM Up Counting Mode */
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#define TIM_CounterMode_Down (0x01U << TIM_CR1_DIR_Pos) /*!< TIM Down Counting Mode */
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#define TIM_CounterMode_CenterAligned1 (0x01U << TIM_CR1_CMS_Pos) /*!< TIM Center Aligned Mode1 */
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#define TIM_CounterMode_CenterAligned2 (0x02U << TIM_CR1_CMS_Pos) /*!< TIM Center Aligned Mode2 */
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#define TIM_CounterMode_CenterAligned3 (0x03U << TIM_CR1_CMS_Pos) /*!< TIM Center Aligned Mode3 */
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/**
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* @brief TIM_Prescaler_Reload_Mode
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*/
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#define TIM_PSCReloadMode_Update (0x00U << TIM_EGR_UG_Pos) /*!< The Prescaler is loaded at the update event */
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#define TIM_PSCReloadMode_Immediate (0x01U << TIM_EGR_UG_Pos) /*!< The Prescaler is loaded immediately */
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/**
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* @brief TIM_Output_Compare_and_PWM_modes_and_Forced_Action
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*/
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#define TIM_OCMode_Timing 0x00U /*!< Output compare mode: Timing */
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#define TIM_OCMode_Active 0x01U /*!< Output compare mode: Active */
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#define TIM_OCMode_Inactive 0x02U /*!< Output compare mode: Inactive */
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#define TIM_OCMode_Toggle 0x03U /*!< Output compare mode: Toggle */
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#define TIM_ForcedAction_Inactive 0x04U /*!< Force inactive level on OCnREF */
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#define TIM_ForcedAction_Active 0x05U /*!< Force active level on OCnREF */
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#define TIM_OCMode_PWM1 0x06U /*!< Output compare mode: PWM1 */
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#define TIM_OCMode_PWM2 0x07U /*!< Output compare mode: PWM2 */
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/**
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* @brief TIM_Output_Compare_Polarity
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*/
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#define TIM_OCPolarity_High 0x00U /*!< Output Compare active high */
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#define TIM_OCPolarity_Low 0x01U /*!< Output Compare active low */
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/**
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* @brief TIM_Output_Compare_N_Polarity
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*/
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#define TIM_OCNPolarity_High 0x00U /*!< Output Compare active high */
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#define TIM_OCNPolarity_Low 0x01U /*!< Output Compare active low */
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/**
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* @brief TIM_Output_Compare_state
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*/
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#define TIM_OutputState_Disable 0x00U /*!< Output Compare Disable */
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#define TIM_OutputState_Enable 0x01U /*!< Output Compare Enable */
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/**
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* @brief TIM_Output_Compare_N_state
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*/
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#define TIM_OutputNState_Disable 0x00U /*!< Output Compare N Disable */
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#define TIM_OutputNState_Enable 0x01U /*!< Output Compare N Enable */
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/**
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* @brief TIM_Output_Compare_Idle_State
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*/
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#define TIM_OCIdleState_Reset 0x00U /*!< OCn=0 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4) */
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#define TIM_OCIdleState_Set 0x01U /*!< OCn=1 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4) */
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/**
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* @brief TIM_Output_Compare_N_Idle_State
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*/
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#define TIM_OCNIdleState_Reset 0x00U /*!< OCnN=0 after a dead-time when MOE=0.(n= 0 : 4) */
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#define TIM_OCNIdleState_Set 0x01U /*!< OCnN=1 after a dead-time when MOE=0.(n= 0 : 4) */
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/**
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* @brief TIM_Channel
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*/
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#define TIM_Channel_1 0x0000 /*!< TIM Channel 1 */
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#define TIM_Channel_2 0x0004 /*!< TIM Channel 2 */
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#define TIM_Channel_3 0x0008 /*!< TIM Channel 3 */
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#define TIM_Channel_4 0x000C /*!< TIM Channel 4 */
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/**
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* @brief TIM_Input_Capture_Polarity
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*/
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#define TIM_ICPolarity_Rising (0x00 << TIM_CCER_CC1P_Pos) /*!< IC Rising edge */
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#define TIM_ICPolarity_Falling (0x01 << TIM_CCER_CC1P_Pos) /*!< IC Falling edge */
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//#define TIM_ICPolarity_BothEdge ((0x01 << TIM_CCER_CC1P_Pos) | (0x01 << TIM_CCER_CC1NP_Pos))
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/**
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* @brief TIM_Input_Capture_Selection
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*/
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#define TIM_ICSelection_DirectTI 0x01U
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#define TIM_ICSelection_IndirectTI 0x02U
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#define TIM_ICSelection_TRC 0x03U
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/**
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* @brief TIM_Input_Capture_Prescaler
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*/
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#define TIM_ICPSC_Div1 0x0000 /*!< no prescaler */
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#define TIM_ICPSC_Div2 0x0004 /*!< capture is done once every 2 events */
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#define TIM_ICPSC_Div4 0x0008 /*!< capture is done once every 4 events */
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#define TIM_ICPSC_Div8 0x000C /*!< capture is done once every 8 events */
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/**
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* @brief OSSR_Off_State_Selection_for_Run_mode_state
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*/
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#define TIM_OSSRState_Disable (0x00U << TIM_BDTR_OSSR_Pos)
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#define TIM_OSSRState_Enable (0x01U << TIM_BDTR_OSSR_Pos)
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/**
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* @brief OSSI_Off_State_Selection_for_Idle_mode_state
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*/
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#define TIM_OSSIState_Disable (0x00U << TIM_BDTR_OSSI_Pos)
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#define TIM_OSSIState_Enable (0x01U << TIM_BDTR_OSSI_Pos)
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/**
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* @brief Lock_level
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*/
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#define TIM_LockLevel_OFF (0x00U << TIM_BDTR_LOCK_Pos)//svd should LOOK -> LOCK
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#define TIM_LockLevel_1 (0x01U << TIM_BDTR_LOCK_Pos)
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#define TIM_LockLevel_2 (0x02U << TIM_BDTR_LOCK_Pos)
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#define TIM_LockLevel_3 (0x03U << TIM_BDTR_LOCK_Pos)
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/**
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* @brief Break_Input_enable_disable
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*/
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#define TIM_Break_Disable (0x00U << TIM_BDTR_BKE_Pos) /*!< Break inputs (BRK and CSS clock failure event) disabled */
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#define TIM_Break_Enable (0x01U << TIM_BDTR_BKE_Pos) /*!< Break inputs (BRK and CSS clock failure event) enabled */
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/**
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* @brief Break_Polarity
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*/
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#define TIM_BreakPolarity_Low (0x00U << TIM_BDTR_BKP_Pos) /*!< Break input BRK is active low */
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#define TIM_BreakPolarity_High (0x01U << TIM_BDTR_BKP_Pos) /*!< Break input BRK is active high */
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/**
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* @brief TIM_AOE_Bit_Set_Reset
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*/
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#define TIM_AutomaticOutput_Disable (0x00U << TIM_BDTR_AOE_Pos) /*!< MOE can be set only by software. */
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#define TIM_AutomaticOutput_Enable (0x01U << TIM_BDTR_AOE_Pos) /*!< MOE can be set by software or automatically at the next
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update event (if the break input is not be active). */
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/**
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* @brief TIM_DOE_Bit_Set_Reset
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*/
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#define TIM_DirectOutput_Disable (0x00U << TIM_BDTR_DOE_Pos) /*!< Direct output disable, output waiting for dead time */
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#define TIM_DirectOutput_Enable (0x01U << TIM_BDTR_DOE_Pos) /*!< Direct output enable, no longer waiting for output after dead time */
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/**
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* @brief DATE_State_Selection_for_Idle_mode_state
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*/
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#define TIM_DTAEState_Disable (0x00U << TIM_BDTR_DTAE_Pos)
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#define TIM_DTAEState_Enable (0x01U << TIM_BDTR_DTAE_Pos)
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/**
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* @brief TIM_interrupt_sources
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*/
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#define TIM_IT_Update (0x01U << TIM_DIER_UIE_Pos) /*!< TIM update Interrupt source */
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#define TIM_IT_CC1 (0x01U << TIM_DIER_CC1IE_Pos) /*!< TIM Capture Compare 1 Interrupt source */
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#define TIM_IT_CC2 (0x01U << TIM_DIER_CC2IE_Pos) /*!< TIM Capture Compare 2 Interrupt source */
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#define TIM_IT_CC3 (0x01U << TIM_DIER_CC3IE_Pos) /*!< TIM Capture Compare 3 Interrupt source */
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#define TIM_IT_CC4 (0x01U << TIM_DIER_CC4IE_Pos) /*!< TIM Capture Compare 4 Interrupt source */
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#define TIM_IT_COM (0x01U << TIM_DIER_COMIE_Pos) /*!< TIM Commutation Interrupt source */
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#define TIM_IT_Trigger (0x01U << TIM_DIER_TIE_Pos) /*!< TIM Trigger Interrupt source */
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#define TIM_IT_Break (0x01U << TIM_DIER_BIE_Pos) /*!< TIM Break Interrupt source */
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#define TIM_IT_CCD1 (0x01U << TIM_DIER_CCD1IE_Pos) /*!< TIM Capture Compare 1 Interrupt source */
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#define TIM_IT_CCD2 (0x01U << TIM_DIER_CCD2IE_Pos) /*!< TIM Capture Compare 2 Interrupt source */
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#define TIM_IT_CCD3 (0x01U << TIM_DIER_CCD3IE_Pos) /*!< TIM Capture Compare 3 Interrupt source */
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#define TIM_IT_OV (0x01U << TIM_DIER_OVIE_Pos) /*!< TIM Trigger Interrupt source */
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#define TIM_IT_UD (0x01U << TIM_DIER_UDIE_Pos) /*!< TIM Break Interrupt source */
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#define TIM_IT_CCD4 (0x01U << TIM_DIER_CCD4IE_Pos) /*!< TIM Capture Compare 4 Interrupt source */
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/**
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* @brief TIM_Event_Source
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*/
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#define TIM_EventSource_Update (0x01U << TIM_EGR_UG_Pos) /*!< Timer update Event source */
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#define TIM_EventSource_CC1 (0x01U << TIM_EGR_CC1G_Pos) /*!< Timer Capture Compare 1 Event source */
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#define TIM_EventSource_CC2 (0x01U << TIM_EGR_CC2G_Pos) /*!< Timer Capture Compare 2 Event source */
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#define TIM_EventSource_CC3 (0x01U << TIM_EGR_CC3G_Pos) /*!< Timer Capture Compare 3 Event source */
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#define TIM_EventSource_CC4 (0x01U << TIM_EGR_CC4G_Pos) /*!< Timer Capture Compare 4 Event source */
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#define TIM_EventSource_COM (0x01U << TIM_EGR_COMG_Pos) /*!< Timer COM event source */
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#define TIM_EventSource_Trigger (0x01U << TIM_EGR_TG_Pos) /*!< Timer Trigger Event source */
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#define TIM_EventSource_Break (0x01U << TIM_EGR_BG_Pos) /*!< Timer Break event source */
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/**
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* @brief TIM_Internal_Trigger_Selection
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*/
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#define TIM_TS_ITR0 (0x00U << TIM_SMCR_TS_Pos) /*!< Internal Trigger 0 */
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#define TIM_TS_ITR1 (0x01U << TIM_SMCR_TS_Pos) /*!< Internal Trigger 1 */
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#define TIM_TS_ITR2 (0x02U << TIM_SMCR_TS_Pos) /*!< Internal Trigger 2 */
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#define TIM_TS_ITR3 (0x03U << TIM_SMCR_TS_Pos) /*!< Internal Trigger 3 */
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#define TIM_TS_TI1F_ED (0x04U << TIM_SMCR_TS_Pos) /*!< TI1 Edge Detector */
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#define TIM_TS_TI1FP1 (0x05U << TIM_SMCR_TS_Pos) /*!< Filtered Timer Input 1 */
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#define TIM_TS_TI2FP2 (0x06U << TIM_SMCR_TS_Pos) /*!< Filtered Timer Input 2 */
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#define TIM_TS_ETRF (0x07U << TIM_SMCR_TS_Pos) /*!< TI1 Edge Detector */
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/**
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* @brief TIM_Encoder_Mode
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*/
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#define TIM_EncoderMode_TI1 (0x01U << TIM_SMCR_SMS_Pos) /*!< Counter counts on TI1FP1 edge depending on TI2FP2 level. */
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#define TIM_EncoderMode_TI2 (0x02U << TIM_SMCR_SMS_Pos) /*!< Counter counts on TI2FP2 edge depending on TI1FP1 level. */
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#define TIM_EncoderMode_TI12 (0x03U << TIM_SMCR_SMS_Pos) /*!< Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
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#define TIM_CCMR1_CC1S_OC (0x00U << TIM_CCMR1_OUTPUT_CC1S_Pos)
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#define TIM_CCMR1_CC1S_DirectTI (0x01U << TIM_CCMR1_OUTPUT_CC1S_Pos)
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#define TIM_CCMR1_CC1S_IndirectTI (0x02U << TIM_CCMR1_OUTPUT_CC1S_Pos)
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#define TIM_CCMR1_CC1S_TRC (0x03U << TIM_CCMR1_OUTPUT_CC1S_Pos)
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#define TIM_CCMR1_CC2S_OC (0x00U << TIM_CCMR1_OUTPUT_CC2S_Pos)
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#define TIM_CCMR1_CC2S_DirectTI (0x01U << TIM_CCMR1_OUTPUT_CC2S_Pos)
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#define TIM_CCMR1_CC2S_IndirectTI (0x02U << TIM_CCMR1_OUTPUT_CC2S_Pos)
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#define TIM_CCMR1_CC2S_TRC (0x03U << TIM_CCMR1_OUTPUT_CC2S_Pos)
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/**
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* @brief TIM_Output_Compare_Preload_State
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*/
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#define TIM_OCPreload_Disable (0x00U << TIM_CCMR1_OUTPUT_OC1PE_Pos) /*!< TIM output compare preload disable */
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#define TIM_OCPreload_Enable (0x01U << TIM_CCMR1_OUTPUT_OC1PE_Pos) /*!< TIM output compare preload enable */
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/**
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* @brief TIM_Output_Compare_Clear_State
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*/
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#define TIM_OCClear_Disable (0x00U << TIM_CCMR1_OUTPUT_OC1CE_Pos) /*!< TIM Output clear disable */
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#define TIM_OCClear_Enable (0x01U << TIM_CCMR1_OUTPUT_OC1CE_Pos) /*!< TIM Output clear enable */
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/**
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* @brief TIM_Output_Compare_Fast_State
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*/
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#define TIM_OCFast_Disable (0x00U << TIM_CCMR1_OUTPUT_OC1FE_Pos) /*!< TIM output compare fast disable */
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#define TIM_OCFast_Enable (0x01U << TIM_CCMR1_OUTPUT_OC1FE_Pos) /*!< TIM output compare fast enable */
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/**
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* @brief TIM_Capture_Compare_state
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*/
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#define TIM_CCx_Disable (0x00U << TIM_CCER_CC1E_Pos) /*!< Capture/Compare Enable */
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#define TIM_CCx_Enable (0x01U << TIM_CCER_CC1E_Pos) /*!< Capture/Compare Enable */
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/**
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* @brief TIM_Capture_Compare_N_state
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*/
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#define TIM_CCxN_Disable (0x00U << TIM_CCER_CC1NE_Pos) /*!< Capture/Compare N Enable */
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#define TIM_CCxN_Enable (0x01U << TIM_CCER_CC1NE_Pos) /*!< Capture/Compare N Enable */
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/**
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* @brief TIM_Update_Source
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*/
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#define TIM_UpdateSource_Global (0x00U << TIM_CR1_URS_Pos) /*!< Source of update is counter overflow/underflow. */
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#define TIM_UpdateSource_Regular (0x01U << TIM_CR1_URS_Pos) /*!< Source of update is the counter overflow/underflow
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or the setting of UG bit, or an update generation
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through the slave mode controller. */
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/**
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* @brief TIM_One_Pulse_Mode
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*/
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#define TIM_OPMode_Repetitive (0x00U << TIM_CR1_OPM_Pos) /*!< Counter is not stopped at update event */
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#define TIM_OPMode_Single (0x01U << TIM_CR1_OPM_Pos) /*!< Counter stops counting at the next update event (clearing the bit CEN) */
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/**
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* @brief TIM_Trigger_Output_Source
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*/
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#define TIM_TRIGSource_Reset (0x00U << TIM_CR2_MMS_Pos) /*!< The UG bit in the TIM_EGR register is used as the trigger output (TRIG). */
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#define TIM_TRIGSource_Enable (0x01U << TIM_CR2_MMS_Pos) /*!< The Counter Enable CEN is used as the trigger output (TRIG). */
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#define TIM_TRIGSource_Update (0x02U << TIM_CR2_MMS_Pos) /*!< The update event is used as the trigger output (TRIG). */
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#define TIM_TRIGSource_OC1 (0x03U << TIM_CR2_MMS_Pos) /*!< The trigger output sends a positive pulse when the CC1IF flag */
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#define TIM_TRIGSource_OC1REF (0x04U << TIM_CR2_MMS_Pos) /*!< OC1REF signal is used as the trigger output (TRIG). */
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#define TIM_TRIGSource_OC2REF (0x05U << TIM_CR2_MMS_Pos) /*!< OC2REF signal is used as the trigger output (TRIG). */
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#define TIM_TRIGSource_OC3REF (0x06U << TIM_CR2_MMS_Pos) /*!< OC3REF signal is used as the trigger output (TRIG). */
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#define TIM_TRIGSource_OC4REF (0x07U << TIM_CR2_MMS_Pos) /*!< OC4REF signal is used as the trigger output (TRIG). */
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/**
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* @brief TIM_Slave_Mode
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*/
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#define TIM_SlaveMode_Reset (0x04U << TIM_SMCR_SMS_Pos) /*!< Rising edge of the selected trigger signal (TRGI) re-initializes */
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#define TIM_SlaveMode_Gated (0x05U << TIM_SMCR_SMS_Pos) /*!< The counter clock is enabled when the trigger signal (TRGI) is high. */
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#define TIM_SlaveMode_Trigger (0x06U << TIM_SMCR_SMS_Pos) /*!< The counter starts at a rising edge of the trigger TRGI. */
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#define TIM_SlaveMode_External1 (0x07U << TIM_SMCR_SMS_Pos) /*!< Rising edges of the selected trigger (TRGI) clock the counter. */
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/**
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* @brief TIM_Master_Slave_Mode
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*/
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#define TIM_MasterSlaveMode_Disable (0x00U << TIM_SMCR_MSM_Pos) /*!< No action */
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#define TIM_MasterSlaveMode_Enable (0x01U << TIM_SMCR_MSM_Pos) /*!< synchronization between the current timer and its slaves (through TRIG) */
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/**
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* @brief TIM_Flags
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*/
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#define TIM_FLAG_Update (0x01U << TIM_SR_UIF_Pos) /*!< TIM update Flag */
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#define TIM_FLAG_CC1 (0x01U << TIM_SR_CC1IF_Pos) /*!< TIM Capture Compare 1 Flag */
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#define TIM_FLAG_CC2 (0x01U << TIM_SR_CC2IF_Pos) /*!< TIM Capture Compare 2 Flag */
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#define TIM_FLAG_CC3 (0x01U << TIM_SR_CC3IF_Pos) /*!< TIM Capture Compare 3 Flag */
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#define TIM_FLAG_CC4 (0x01U << TIM_SR_CC4IF_Pos) /*!< TIM Capture Compare 4 Flag */
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#define TIM_FLAG_COM (0x01U << TIM_SR_COMIF_Pos) /*!< TIM Commutation Flag */
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#define TIM_FLAG_Trigger (0x01U << TIM_SR_TIF_Pos) /*!< TIM Trigger Flag */
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#define TIM_FLAG_Break (0x01U << TIM_SR_BIF_Pos) /*!< TIM Break Flag */
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#define TIM_FLAG_CC1OF (0x01U << TIM_SR_CC1OF_Pos) /*!< TIM Capture Compare 1 overcapture Flag */
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#define TIM_FLAG_CC2OF (0x01U << TIM_SR_CC2OF_Pos) /*!< TIM Capture Compare 2 overcapture Flag */
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#define TIM_FLAG_CC3OF (0x01U << TIM_SR_CC3OF_Pos) /*!< TIM Capture Compare 3 overcapture Flag */
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#define TIM_FLAG_CC4OF (0x01U << TIM_SR_CC4OF_Pos) /*!< TIM Capture Compare 4 overcapture Flag */
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/**
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* @brief PWM phase shift and DMA repeat update
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*/
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#define TIM_PDER_CCR1SHIFTEN (0x01U << TIM_PDER_CCR1_SHIFT_EN_Pos) /*!< TIM Channel 1 output PWM phase shift enable bit */
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#define TIM_PDER_CCR2SHIFTEN (0x01U << TIM_PDER_CCR2_SHIFT_EN_Pos) /*!< TIM Channel 2 output PWM phase shift enable bit */
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#define TIM_PDER_CCR3SHIFTEN (0x01U << TIM_PDER_CCR3_SHIFT_EN_Pos) /*!< TIM Channel 3 output PWM phase shift enable bit */
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#define TIM_PDER_CCR4SHIFTEN (0x01U << TIM_PDER_CCR4_SHIFT_EN_Pos) /*!< TIM Channel 4 output PWM phase shift enable bit */
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#define TIM_PDER_CCR5SHIFTEN (0x01U << TIM_PDER_CCR5_SHIFT_EN_Pos) /*!< TIM Channel 5 output PWM phase shift enable bit */
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/** @defgroup TIM_TIx_External_Clock_Source
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* @{
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*/
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#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
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#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
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#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
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/** @defgroup TIM_External_Trigger_Prescaler
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* @{
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*/
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#define TIM_ExtTRGPSC_OFF (0x00U << TIM_SMCR_ETPS_Pos)
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#define TIM_ExtTRGPSC_DIV2 (0x01U << TIM_SMCR_ETPS_Pos)
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#define TIM_ExtTRGPSC_DIV4 (0x02U << TIM_SMCR_ETPS_Pos)
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#define TIM_ExtTRGPSC_DIV8 (0x03U << TIM_SMCR_ETPS_Pos)
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/** @defgroup TIM_External_Trigger_Polarity
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* @{
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*/
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#define TIM_ExtTRGPolarity_Inverted (0x01U << TIM_SMCR_ETP_Pos)
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#define TIM_ExtTRGPolarity_NonInverted (0x00U << TIM_SMCR_ETP_Pos)
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//=============================================================================
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// Macro Definition
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//=============================================================================
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//=============================================================================
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// Structure Definition
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//=============================================================================
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//=============================================================================
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// Global Data Definition
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//=============================================================================
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//=============================================================================
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// Private Function Definition
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//=============================================================================
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//=============================================================================
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// Public Function Definition
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//=============================================================================
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void TIM_DeInit(TIM_Type *tim);
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void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *init_struct);
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void TIM_TimeBaseInit(TIM_Type *tim, TIM_TimeBaseInitTypeDef *init_struct);
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void TIM_OCStructInit(TIM_OCInitTypeDef *init_struct);
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void TIM_OC1Init(TIM_Type *tim, TIM_OCInitTypeDef *init_struct);
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void TIM_OC2Init(TIM_Type *tim, TIM_OCInitTypeDef *init_struct);
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void TIM_OC3Init(TIM_Type *tim, TIM_OCInitTypeDef *init_struct);
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void TIM_OC4Init(TIM_Type *tim, TIM_OCInitTypeDef *init_struct);
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void TIM_SetIC1Prescaler(TIM_Type *tim, uint32_t psc);
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void TIM_SetIC2Prescaler(TIM_Type *tim, uint32_t psc);
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void TIM_SetIC3Prescaler(TIM_Type *tim, uint32_t psc);
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void TIM_SetIC4Prescaler(TIM_Type *tim, uint32_t psc);
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void TIM_ICStructInit(TIM_ICInitTypeDef *init_struct);
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void TIM_ICInit(TIM_Type *tim, TIM_ICInitTypeDef *init_struct);
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void TIM_PWMIConfig(TIM_Type *tim, TIM_ICInitTypeDef *init_struct);
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void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *init_struct);
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void TIM_BDTRConfig(TIM_Type *tim, TIM_BDTRInitTypeDef *init_struct);
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void TIM_CtrlPWMOutputs(TIM_Type *tim, FunctionalState state);
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void TIM_Cmd(TIM_Type *tim, FunctionalState state);
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void TIM_ITConfig(TIM_Type *tim, uint32_t it, FunctionalState state);
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void TIM_GenerateEvent(TIM_Type *tim, uint32_t source);
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void TIM_InternalClockConfig(TIM_Type *tim);
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void TIM_ITRxExternalClockConfig(TIM_Type *tim, uint32_t source);
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void TIM_SelectInputTrigger(TIM_Type *tim, uint16_t source);
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void TIM_PrescalerConfig(TIM_Type *tim, uint16_t prescaler, uint16_t reloadMode);
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void TIM_CounterModeConfig(TIM_Type *tim, uint32_t counter_mode);
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void TIM_EncoderInterfaceConfig(TIM_Type *tim, uint32_t encoder_mode, uint32_t ic1_polarity, uint32_t ic2_polarity);
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void TIM_ForcedOC1Config(TIM_Type *tim, uint32_t forced_action);
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void TIM_ForcedOC2Config(TIM_Type *tim, uint32_t forced_action);
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void TIM_ForcedOC3Config(TIM_Type *tim, uint32_t forced_action);
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void TIM_ForcedOC4Config(TIM_Type *tim, uint32_t forced_action);
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void TIM_ClearOC1Ref(TIM_Type *tim, uint16_t TIM_OCClear);
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void TIM_ClearOC2Ref(TIM_Type *tim, uint16_t TIM_OCClear);
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void TIM_ClearOC3Ref(TIM_Type *tim, uint16_t TIM_OCClear);
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void TIM_ClearOC4Ref(TIM_Type *tim, uint16_t TIM_OCClear);
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void TIM_ARRPreloadConfig(TIM_Type *tim, FunctionalState state);
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void TIM_SelectCOM(TIM_Type *tim, FunctionalState state);
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void TIM_SelectCCDMA(TIM_Type *tim, FunctionalState state);
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void TIM_CCPreloadControl(TIM_Type *tim, FunctionalState state);
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void TIM_OC1PreloadConfig(TIM_Type *tim, uint32_t preload);
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void TIM_OC2PreloadConfig(TIM_Type *tim, uint32_t preload);
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void TIM_OC3PreloadConfig(TIM_Type *tim, uint32_t preload);
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void TIM_OC4PreloadConfig(TIM_Type *tim, uint32_t preload);
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void TIM_OC1FastConfig(TIM_Type *tim, uint32_t fast);
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void TIM_OC2FastConfig(TIM_Type *tim, uint32_t fast);
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void TIM_OC3FastConfig(TIM_Type *tim, uint32_t fast);
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void TIM_OC4FastConfig(TIM_Type *tim, uint32_t fast);
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void TIM_OC1PolarityConfig(TIM_Type *tim, uint32_t polarity);
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void TIM_OC1NPolarityConfig(TIM_Type *tim, uint32_t polarity);
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void TIM_OC2PolarityConfig(TIM_Type *tim, uint32_t polarity);
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void TIM_OC2NPolarityConfig(TIM_Type *tim, uint32_t polarity);
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void TIM_OC3PolarityConfig(TIM_Type *tim, uint32_t polarity);
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void TIM_OC3NPolarityConfig(TIM_Type *tim, uint32_t polarity);
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void TIM_OC4PolarityConfig(TIM_Type *tim, uint32_t polarity);
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void TIM_OC4NPolarityConfig(TIM_Type *tim, uint32_t polarity);
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void TIM_CCxCmd(TIM_Type *tim, uint16_t channel, uint32_t ccx_en);
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void TIM_CCxNCmd(TIM_Type *tim, uint16_t channel, uint32_t ccxn_en);
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void TIM_SelectOCxM(TIM_Type *tim, uint16_t channel, uint32_t mode);
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void TIM_SetCompare1(TIM_Type *tim, uint32_t compare);
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void TIM_SetCompare2(TIM_Type *tim, uint32_t compare);
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void TIM_SetCompare3(TIM_Type *tim, uint32_t compare);
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void TIM_SetCompare4(TIM_Type *tim, uint32_t compare);
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void TIM_ASYMEN_Cmd(TIM_Type *tim, FunctionalState state);
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void TIM_SetDownCompare1(TIM_Type *tim, uint32_t compare);
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void TIM_SetDownCompare2(TIM_Type *tim, uint32_t compare);
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void TIM_SetDownCompare3(TIM_Type *tim, uint32_t compare);
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void TIM_SetDownCompare4(TIM_Type *tim, uint32_t compare);
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void TIM_UpdateDisableConfig(TIM_Type *tim, FunctionalState state);
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void TIM_UpdateRequestConfig(TIM_Type *tim, uint32_t source);
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void TIM_SelectHallSensor(TIM_Type *tim, FunctionalState state);
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void TIM_SelectOnePulseMode(TIM_Type *tim, uint32_t mode);
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void TIM_SelectOutputTrigger(TIM_Type *tim, uint32_t source);
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void TIM_SelectSlaveMode(TIM_Type *tim, uint32_t mode);
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void TIM_SelectMasterSlaveMode(TIM_Type *tim, uint32_t mode);
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void TIM_SetAutoreload(TIM_Type *tim, uint16_t auto_reload);
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void TIM_SetCounter(TIM_Type *tim, uint32_t counter);
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void TIM_SetClockDivision(TIM_Type *tim, uint32_t clock_div);
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uint32_t TIM_GetCapture1(TIM_Type *tim);
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uint32_t TIM_GetCapture2(TIM_Type *tim);
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uint32_t TIM_GetCapture3(TIM_Type *tim);
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uint32_t TIM_GetCapture4(TIM_Type *tim);
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uint32_t TIM_GetCounter(TIM_Type *tim);
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uint16_t TIM_GetPrescaler(TIM_Type *tim);
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FlagStatus TIM_GetFlagStatus(TIM_Type *tim, uint32_t flag);
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void TIM_ClearFlag(TIM_Type *tim, uint32_t flag);
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ITStatus TIM_GetITStatus(TIM_Type *tim, uint32_t it);
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void TIM_ClearITPendingBit(TIM_Type *tim, uint32_t it);
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void TIM_PWMShiftConfig(TIM_Type *tim, uint32_t it, FunctionalState state);
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void TIM_SetCCR1FALL(TIM_Type *tim, uint32_t shift);
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void TIM_SetCCR2FALL(TIM_Type *tim, uint32_t shift);
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void TIM_SetCCR3FALL(TIM_Type *tim, uint32_t shift);
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void TIM_SetCCR4FALL(TIM_Type *tim, uint32_t shift);
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FlagStatus TIM_GetCountDirection(TIM_Type *tim);
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uint32_t TIM_GetTIMxClock(TIM_Type *tim);
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void TIM_ETRClockMode1Config(TIM_Type *tim, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
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void TIM_ETRClockMode2Config(TIM_Type* TIMx, uint16_t TIM_ExtTRGPrescaler,uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
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void TIM_TIxExternalClockConfig(TIM_Type *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter);
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void TIM_ETRConfig(TIM_Type *tim, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,uint16_t ExtTRGFilter);
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#ifdef __cplusplus
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}
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#endif
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#endif
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