Compare commits
1 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 weiting2
|
f03a0e6e7a |
@@ -1,14 +1,14 @@
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no device y=ax+b MAC a+ b+ a- b- avg
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1 c6be c6be 1804ED37C6BE 2270 -7040 2259 -14129 4.15063496100114
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2 8cd0 8cd0 0081F9E48CD0 2199 -4616 2162 -16396 4.67288597901671
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3 c694 c694 1804ED37C694 2354 -12824 2354 -11216 4.34663132771076
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4 c6c7 c6c7 1804ED37C6C7 2199 -7238 2221 -15702 4.63164432837751
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5 9b97 9b97 0081F9E49B97 2227 -9846 2151 -26609 4.75015860006776
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6 c6df c6df 1804ED37C6DF 2132 -3844 2054 -21545 4.89066238118665
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1 c6be c6be 18:04:ED:37:C6:BE 2270 -7040 2259 -14129 4.15063496100114
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2 8cd0 8cd0 00:81:F9:E4:8C:D0 2199 -4616 2162 -16396 4.67288597901671
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3 c694 c694 18:04:ED:37:C6:94 2354 -12824 2354 -11216 4.34663132771076
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4 c6c7 c6c7 18:04:ED:37:C6:C7 2199 -7238 2221 -15702 4.63164432837751
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5 9b97 9b97 00:81:F9:E4:9B:97 2227 -9846 2151 -26609 4.75015860006776
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6 c6df c6df 18:04:ED:37:C6:DF 2132 -3844 2054 -21545 4.89066238118665
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7 c652 c652 18:04:ED:37:C6:52 2024 -7687 2086 -11283 4.88850143182858
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8 c5ed c5ed 18:04:ED:37:C5:ED 2231 -1711 2353 -70845 4.45265043545859
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9 9bef 9bef 0081F9E49BEF 2383 -8585 2415 -20347 4.2758539244186
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10 8b50 8b50 00:81:F9:E4:8B:50 2369 -11005 2360 -11797 4.30475635707671
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9 9bef 9bef 00:81:F9:E4:9B:EF 2383 -8585 2415 -20347 4.2758539244186
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10 8b50 8b50 00:81:F9:E4:8B:50 2366 -15223 2402 -24971 4.35162291666667
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11 c641 c641 18:04:ED:37:C6:41 2090 4616 1997 -40665 5.07591391714942
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12 E8E6 E8E6 A4:DA:32:D4:E8:E6 2306 -88454 2418 -15140 4.2686494968089
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13 E73B E73B A4:DA:32:D4:E7:3B 2262 -564 2298 44746 4.35551198222141
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BIN
Binary file not shown.
BIN
Binary file not shown.
+4
-4
@@ -64,10 +64,10 @@ struct _StiCaliStiTable{
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#elif defined(BOARD_00_81_F9_E4_8B_50)
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{
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.p_ch.coefficient = 2369,
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.p_ch.offset = -11004,
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.n_ch.coefficient = 2360,
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.n_ch.offset = -11796
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.p_ch.coefficient = 2366,
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.p_ch.offset = -15223,
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.n_ch.coefficient = 2402,
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.n_ch.offset = -24971
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};
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#elif defined(BOARD_00_81_F9_E4_9B_97)
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-138
@@ -1,138 +0,0 @@
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#ifndef DBS_OBJECT_H
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#define DBS_OBJECT_H
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#include "neu/headstage_spi.h"
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#define SYS_RESERVED_INDEX 0
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#define SYS_GENERAL_ENABLE_INDEX 1
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#define SYS_LNA_BIOS1_INDEX 2
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#define SYS_LNA_BIOS2_INDEX 3
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#define REC_CHANNEL_INDEX 0
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#define REC_GAIN_INDEX 1
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#define REC_ADC_CLOCK_INDEX 2
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#define STI_ENABLE_INDEX 0
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#define STI_DURATION0_INDEX 1
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#define STI_DURATION1_INDEX 2
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#define STI_DURATION2_INDEX 3
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#define STI_DURATION3_INDEX 4
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#define STI_AMP_POS_INDEX 5
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#define STI_AMP_NEG_INDEX 6
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#define STI_POLARITY_INDEX 7
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#define STI_CYCLE_CH01_INDEX 8
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#define STI_CYCLE_CH23_INDEX 9
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#define STI_CYCLE_CH45_INDEX 10
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#define STI_CYCLE_CH67_INDEX 11
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#define STI_CLK_RATIO_INDEX 12
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#define STI_ARBITRARY_EN_INDEX 13
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#define STI_MODE_INDEX 14
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//#define DBS_REGISTER \
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// uint8_t address; \
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// void (*write_reg) (DBSRegister *self, uint32_t reg_value); \
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// uint32_t (*read_reg) (DBSRegister *self)
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typedef struct _DBSRegister{
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uint8_t address;
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bool WriteRegister, CheckRegister;
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void (*write_reg) (struct _DBSRegister *self, uint16_t reg_value);
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void (*read_reg) (struct _DBSRegister *self);
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}DBSRegister;
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void write_reg(DBSRegister *self, uint16_t reg_value){
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spi_txbuf[0] = 0x80 | self->address;
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spi_txbuf[1] = (reg_value >> 8) & 0xFF ;
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spi_txbuf[2] = reg_value & 0xFF;
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SPICallBack = ONE_SHOT_SPI;
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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void read_reg(DBSRegister *self){
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spi_txbuf[0] = 0x7F & self->address;
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spi_txbuf[1] = 0x7F & self->address; // it's don't care actually
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spi_txbuf[2] = 0x7F & self->address; // it's don't care actually
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SPICallBack = READ_REG;
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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}
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static uint16_t sys_register_default_value[4] = {
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0x0000,
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0x40F2,
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0x0210,
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0x4210
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};
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static uint16_t rec_register_value[3];
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static uint16_t sti_register_value[15];
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static DBSRegister sys_register[4];
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static DBSRegister rec_register[3];
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static DBSRegister sti_register[15];
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static void InitSysRegister(){
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sys_register[SYS_RESERVED_INDEX].address = 0x00;
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sys_register[SYS_GENERAL_ENABLE_INDEX].address = 47; // general enable
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sys_register[SYS_LNA_BIOS1_INDEX].address = 57;
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sys_register[SYS_LNA_BIOS2_INDEX].address = 58;
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for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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sys_register[i].WriteRegister = false;
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sys_register[i].CheckRegister = false;
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sys_register[i].write_reg = &write_reg;
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sys_register[i].read_reg = &read_reg;
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}
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}
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static void InitRecRegister(){
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rec_register[REC_CHANNEL_INDEX].address = 48;
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rec_register[REC_GAIN_INDEX].address = 49;
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rec_register[REC_ADC_CLOCK_INDEX].address = 51; // sampling rate
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for(int i=0 ; i<sizeof(rec_register)/sizeof(DBSRegister) ; i++){
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rec_register[i].WriteRegister = false;
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rec_register[i].CheckRegister = false;
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rec_register[i].write_reg = &write_reg;
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rec_register[i].read_reg = &read_reg;
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}
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}
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static void InitStiRegister(){
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sti_register[STI_ENABLE_INDEX].address = 46;
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sti_register[STI_DURATION0_INDEX].address = 1;
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sti_register[STI_DURATION1_INDEX].address = 2;
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sti_register[STI_DURATION2_INDEX].address = 3;
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sti_register[STI_DURATION3_INDEX].address = 4;
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sti_register[STI_AMP_POS_INDEX].address = 37;
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sti_register[STI_AMP_NEG_INDEX].address = 38;
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sti_register[STI_POLARITY_INDEX].address = 40;
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sti_register[STI_CYCLE_CH01_INDEX].address = 42;
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sti_register[STI_CYCLE_CH23_INDEX].address = 43;
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sti_register[STI_CYCLE_CH45_INDEX].address = 44;
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sti_register[STI_CYCLE_CH67_INDEX].address = 45;
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sti_register[STI_CLK_RATIO_INDEX].address = 52;
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sti_register[STI_ARBITRARY_EN_INDEX].address = 54;
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sti_register[STI_MODE_INDEX].address = 56;
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for(int i=0 ; i<sizeof(sti_register)/sizeof(DBSRegister) ; i++){
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sti_register[i].WriteRegister = false;
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sti_register[i].CheckRegister = false;
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sti_register[i].write_reg = &write_reg;
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sti_register[i].read_reg = &read_reg;
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}
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}
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static void InitDBSRegister(){
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InitSysRegister();
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InitRecRegister();
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InitStiRegister();
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// for(int i=1 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
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for(int i=1 ; i<4 ; i++){
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sys_register[i].WriteRegister = true;
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}
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flag_notify(EVT_NEU_SPI);
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}
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#endif
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+124
-185
@@ -160,17 +160,13 @@ static void FlushNotify();
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#define NEU_REC_PARAM 0x20
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#define NEU_MULTI_STI 0x40
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#define NEU_TEST_INS 0x60
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#define RIS_REC_ON_CHANGE 0x80
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#define RIS_STI_ON_CHANGE 0xA0
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#define RIS_STOP_STI 0x80
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/** event */
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#define EVT_NEU_SPI 0x0001 /**< spi transaction event */
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#define EVT_NEU_LED 0x0002 /**< set led event */
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#define EVT_NEU_CHECK 0x0004 /**< check neulive single instruction */
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#define EVT_NEU_REG_SPI 0x0008 /** register spi event */
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#define EVT_NEU_PREPARE 0x0010 /** prepare to record or stimulate **/
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#define EVT_NEU_REC 0x0020
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#define EVT_NEU_STI 0x0040
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/** clock setting */
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#define NEU_SYS_CLK 2000000 /**< 10Mhz */
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@@ -302,7 +298,7 @@ typedef enum{
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#include "string.h"
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#include "headstage_rec_ins.h"
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#include "headstage_sti_ins.h"
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#include "headstage_dbs_object.h"
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/*
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* todo: need to define some procedure to detect this device status
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@@ -342,8 +338,53 @@ static void headstage_init() {
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#undef THREE_POINT_THREE_VOLT
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}
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/**
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* @fn headstage_neu_append_notify_data
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*/
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#define CHANNEL_VALID (INSTRUCTION.recording_channel & (0x0001 << channel))
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static void headstage_neu_append_notify_data() {
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uint8_t channel = spi_rxbuf[0];
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// close-reopen SPI, if the first channel received is invalid
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if(IsFirstData){
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// start record
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if((INSTRUCTION.recording_channel & (0x0001 << channel)) && (channel < 16)){
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IsFirstData = false;
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}
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// restart SPI
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else{
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SPI_close(headstage_spi_handle);
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ReopenSPI();
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IsFirstData = true;
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return;
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}
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}
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// discard illegal channel
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// uint16_t valid_channel = INSTRUCTION.recording_channel & (0x0001 << channel);
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if(!(INSTRUCTION.recording_channel & (0x0001 << channel)) || (channel > 15)){
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// illegal channel
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return;
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}
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uint8_t not_buf[3];
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not_buf[0] = channel; // ch
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not_buf[1] = spi_rxbuf[1];
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not_buf[2] = spi_rxbuf[2];
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// not_buf[1] = (INSTRUCTION.recording_channel | 0xFF00) >> 8;
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// not_buf[2] = (INSTRUCTION.recording_channel | 0x00FF);
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uint8_t data_size = headstage_notify_append_data(not_buf);
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if (data_size >= BLE_NOT_BUFF_SIZE) {
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headstage_notify_flip_buffer();
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headstage_notify_send();
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}
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}
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static void headstage_neu_state_spi();
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static void headstage_neu_spi();
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/**
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* @fn headstage_neu_event
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@@ -352,27 +393,93 @@ static void headstage_neu_spi();
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*/
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static void headstage_neu_event() {
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if (EVENT_MASK == 0) {
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// fast return
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return;
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}
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if (flag_mask(EVT_NEU_SPI)) {
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flag_disable(EVT_NEU_SPI);
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// headstage_neu_state_spi();
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headstage_neu_spi();
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headstage_neu_state_spi();
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}
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if (flag_mask(EVT_NEU_LED)) {
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flag_disable(EVT_NEU_LED); /** reserved to set led power and set color manually */
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}
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if (EVENT_MASK == 0) {
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// fast return
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}
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if (flag_mask(EVT_DISCONNECTED)) {
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ConnectState = false;
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headstage_update_vis_instruction(VIS_INT);
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}
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}
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/**
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* @fn headstage_spi_callback
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*
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* description: callback function to deal with data transmission between DBS and CC2650
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*/
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static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction) {
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switch(SPICallBack){
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case CONTINUOUS_TRANS:{
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for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
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spi_txbuf[i] = 0x00;
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}
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flag_notify(EVT_NEU_SPI);
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break;
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}
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case FLUSH_BUFFER:{
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SPICallBack = FLUSH_BUFFER2;
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for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
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spi_txbuf[i] = 0x00;
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}
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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break;
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}
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case FLUSH_BUFFER2:{
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SPICallBack = ONE_SHOT_SPI;
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for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
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spi_txbuf[i] = 0x00;
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}
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||||
flag_notify(EVT_NEU_SPI);
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// headstage_spi_transaction(SPI_BUFFER_SIZE);
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break;
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}
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case ONE_SHOT_SPI:{
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SPICallBack = FLUSH_BUFFER;
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for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
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spi_txbuf[i] = 0x00;
|
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}
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headstage_spi_transaction(SPI_BUFFER_SIZE);
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break;
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}
|
||||
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case READ_MOSI:{
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flag_notify(EVT_NEU_SPI);
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break;
|
||||
}
|
||||
|
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case READ_REG:{
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check_reg_counter ++;
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break;
|
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}
|
||||
|
||||
case CLOSE_SPI:{
|
||||
SPICallBack = ONE_SHOT_SPI;
|
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SPI_close(headstage_spi_handle);
|
||||
break;
|
||||
}
|
||||
|
||||
case END_TRANSMIT:{
|
||||
tx_put_u24(0, 0);
|
||||
SPICallBack = CONTINUOUS_TRANS;
|
||||
break;
|
||||
}
|
||||
default:{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn headstage_update_ris_instruction
|
||||
*
|
||||
@@ -507,37 +614,6 @@ static void headstage_update_ris_instruction(uint8_t ins_len, uint8_t* instructi
|
||||
break;
|
||||
}
|
||||
|
||||
case RIS_REC_ON_CHANGE:{
|
||||
uint16_t reg_value = instruction[2] << 8 | instruction[3];
|
||||
switch(instruction[1]){
|
||||
case REC_CHANNEL_INDEX:{
|
||||
rec_register[REC_CHANNEL_INDEX].WriteRegister = true;
|
||||
rec_register_value[REC_CHANNEL_INDEX] = reg_value;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case REC_GAIN_INDEX:{
|
||||
rec_register[REC_GAIN_INDEX].WriteRegister = true;
|
||||
rec_register_value[REC_GAIN_INDEX] = reg_value;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case REC_ADC_CLOCK_INDEX:{
|
||||
rec_register[REC_ADC_CLOCK_INDEX].WriteRegister = true;
|
||||
rec_register_value[REC_ADC_CLOCK_INDEX] = reg_value;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
default:{
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default: {
|
||||
break;
|
||||
}
|
||||
@@ -959,7 +1035,7 @@ static void headstage_neu_state_spi() {
|
||||
}
|
||||
case NEU_READ_DATA: {
|
||||
|
||||
// sti enable command
|
||||
// recv sti enable command
|
||||
if( (rec_sti_command & ENABLE_STI) && !(rec_sti_command & STATUS_STI) ){
|
||||
// go to send sti instruction
|
||||
NEULIVE_STATE.state = NEU_WRITE_STI_INS;
|
||||
@@ -971,7 +1047,7 @@ static void headstage_neu_state_spi() {
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
|
||||
// disable stimulation
|
||||
// recv disable stimulation
|
||||
else if( !(rec_sti_command & ENABLE_STI) && (rec_sti_command & STATUS_STI) ){
|
||||
NEULIVE_STATE.state = NEU_STI_INT;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
@@ -983,6 +1059,7 @@ static void headstage_neu_state_spi() {
|
||||
// recv disable recording
|
||||
else if( !(rec_sti_command & ENABLE_REC) ){
|
||||
rec_sti_command &= ~STATUS_REC;
|
||||
headstage_led_color(COLOR_WHITE);
|
||||
headstage_led_control();
|
||||
|
||||
if(rec_sti_command & STATUS_STI){
|
||||
@@ -1197,142 +1274,4 @@ static void headstage_neu_state_spi() {
|
||||
}
|
||||
}
|
||||
|
||||
static uint8_t check_register_value(DBSRegister *dbs_register, uint8_t reg_size, uint16_t *value_to_fit);
|
||||
static uint8_t write_register(DBSRegister *dbs_register, uint8_t reg_size, uint16_t *value_to_write);
|
||||
|
||||
typedef enum{
|
||||
dbs_idle = 0x00,
|
||||
dbs_prepare = 0x01,
|
||||
dbs_recording = 0x02,
|
||||
dbs_stimulate = 0x04
|
||||
}dbs_status;
|
||||
|
||||
static void headstage_neu_spi(){
|
||||
static dbs_status status;
|
||||
|
||||
// check system register if we have written it before
|
||||
if( check_register_value(sys_register, sizeof(sys_register)/sizeof(DBSRegister), sys_register_default_value) ){
|
||||
return;
|
||||
}
|
||||
// write system register
|
||||
if (write_register(sys_register, sizeof(sys_register)/sizeof(DBSRegister), sys_register_default_value)){
|
||||
return;
|
||||
}
|
||||
|
||||
if(check_register_value(rec_register, sizeof(rec_register)/sizeof(DBSRegister), rec_register_value)){
|
||||
return;
|
||||
}
|
||||
if(write_register(rec_register, sizeof(rec_register)/sizeof(DBSRegister), rec_register_value)){
|
||||
return;
|
||||
}
|
||||
|
||||
if(check_register_value(sti_register, sizeof(sti_register)/sizeof(DBSRegister), sti_register_value)){
|
||||
return;
|
||||
}
|
||||
if(write_register(sti_register, sizeof(sti_register)/sizeof(DBSRegister), sti_register_value)){
|
||||
return;
|
||||
}
|
||||
|
||||
// enable recording channel
|
||||
if(rec_register[REC_CHANNEL_INDEX].WriteRegister){
|
||||
status |= dbs_prepare;
|
||||
rec_register[REC_CHANNEL_INDEX].WriteRegister = false;
|
||||
rec_register[REC_CHANNEL_INDEX].CheckRegister = true;
|
||||
rec_register[REC_CHANNEL_INDEX].write_reg(rec_register+REC_CHANNEL_INDEX, rec_register_value[REC_CHANNEL_INDEX]);
|
||||
return;
|
||||
}
|
||||
|
||||
if(status & dbs_prepare){
|
||||
status &= ~dbs_prepare;
|
||||
|
||||
if(rec_sti_command & ENABLE_REC){
|
||||
status |= dbs_recording;
|
||||
rec_sti_command |= STATUS_REC; // neu is recording now
|
||||
}
|
||||
|
||||
// change LED base on working status
|
||||
headstage_led_control();
|
||||
|
||||
AppendSPITX(0, 0);
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
return;
|
||||
}
|
||||
|
||||
if(rec_sti_command & STATUS_REC){
|
||||
if(!(rec_sti_command & ENABLE_REC)){
|
||||
// terminate record
|
||||
}
|
||||
else{
|
||||
headstage_neu_append_notify_data();
|
||||
AppendSPITX(0, 0);
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// // it's recording
|
||||
// if(rec_sti_command & STATUS_REC){
|
||||
// if(!(rec_sti_command & ENABLE_REC)){
|
||||
// // stop recording
|
||||
// rec_register[REC_CHANNEL_INDEX].WriteRegister = false;
|
||||
// rec_register[REC_CHANNEL_INDEX].CheckRegister = true;
|
||||
// rec_register[REC_CHANNEL_INDEX].write_reg(rec_register+REC_CHANNEL_INDEX, value_to_write[REC_CHANNEL_INDEX]);
|
||||
// }
|
||||
// else{
|
||||
// // keep recording
|
||||
// headstage_neu_append_notify_data();
|
||||
// AppendSPITX(0, 0);
|
||||
// headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
// }
|
||||
// }
|
||||
}
|
||||
|
||||
#define RESEND_SPI_READ_NUMBER 3
|
||||
static uint8_t check_register_value(DBSRegister *dbs_register, uint8_t reg_size, uint16_t *value_to_fit){
|
||||
for(int i=0 ; i<reg_size ; i++){
|
||||
if(dbs_register[i].CheckRegister){
|
||||
if(check_reg_counter < RESEND_SPI_READ_NUMBER){
|
||||
dbs_register[i].read_reg(dbs_register+i);
|
||||
}
|
||||
else{
|
||||
// check register value
|
||||
check_reg_counter = 0;
|
||||
dbs_register[i].CheckRegister = false;
|
||||
|
||||
uint16_t ins_to_fit = value_to_fit[i];
|
||||
uint16_t ins_recv = spi_rxbuf[1] << 8 | spi_rxbuf[2];
|
||||
|
||||
if(ins_recv != ins_to_fit){
|
||||
SPI_close(headstage_spi_handle);
|
||||
dbs_register[i].WriteRegister = true;
|
||||
ReopenSPI();
|
||||
dbs_register[i].write_reg(dbs_register+i, value_to_fit[i]);
|
||||
}
|
||||
else{
|
||||
AppendSPITX(0, 0);
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint8_t write_register(DBSRegister *dbs_register, uint8_t reg_size, uint16_t *value_to_write){
|
||||
|
||||
// start from index 1, since 0 is rec/sti enable
|
||||
for(int i=1 ; i<reg_size ; i++){
|
||||
if(dbs_register[i].WriteRegister){
|
||||
dbs_register[i].WriteRegister = false;
|
||||
dbs_register[i].CheckRegister = true;
|
||||
dbs_register[i].write_reg(dbs_register+i, value_to_write[i]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
+6
-6
@@ -3,15 +3,15 @@
|
||||
#define VERSION_DATE
|
||||
|
||||
#define VERSION_DATE_YEAR 20
|
||||
#define VERSION_DATE_MONTH 9
|
||||
#define VERSION_DATE_DAY 9
|
||||
#define VERSION_DATE_HOUR 10
|
||||
#define VERSION_DATE_MINUTE 26
|
||||
#define VERSION_DATE_MONTH 10
|
||||
#define VERSION_DATE_DAY 26
|
||||
#define VERSION_DATE_HOUR 17
|
||||
#define VERSION_DATE_MINUTE 47
|
||||
|
||||
// this is NOT the version hash !!
|
||||
// it's the last version hash
|
||||
#define VERSION_HASH b9c9cc0bbcdb1ad375f9f5966577ca34ef3fd6d1
|
||||
#define VERSION_GIT_BRANCH neulive20_development_without_central
|
||||
#define VERSION_HASH 6e9acfda78f14e9c532360e9267b053392f53659
|
||||
#define VERSION_GIT_BRANCH neulive20_stable_non_central
|
||||
|
||||
static void get_board_name(char *board_name_ch, uint8 *board_name_int, uint8 name_size){
|
||||
uint8 name_offset = 18;
|
||||
|
||||
-51
@@ -13,57 +13,6 @@
|
||||
static uint8_t not_buf_offset = NOT_BUF_OFFSET_INIT;
|
||||
static uint32_t not_time_stamp = 0;
|
||||
|
||||
static void headstage_notify_set_timestamp();
|
||||
static void headstage_notify_flip_buffer();
|
||||
static uint8_t headstage_notify_append_data(uint8_t *data_value);
|
||||
|
||||
/**
|
||||
* @fn headstage_neu_append_notify_data
|
||||
*/
|
||||
#define CHANNEL_VALID (INSTRUCTION.recording_channel & (0x0001 << channel))
|
||||
static void headstage_neu_append_notify_data() {
|
||||
|
||||
uint8_t channel = spi_rxbuf[0];
|
||||
|
||||
// close-reopen SPI, if the first channel received is invalid
|
||||
if(IsFirstData){
|
||||
// start record
|
||||
if((INSTRUCTION.recording_channel & (0x0001 << channel)) && (channel < 16)){
|
||||
IsFirstData = false;
|
||||
}
|
||||
// restart SPI
|
||||
else{
|
||||
SPI_close(headstage_spi_handle);
|
||||
ReopenSPI();
|
||||
IsFirstData = true;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// discard illegal channel
|
||||
// uint16_t valid_channel = INSTRUCTION.recording_channel & (0x0001 << channel);
|
||||
if(!(INSTRUCTION.recording_channel & (0x0001 << channel)) || (channel > 15)){
|
||||
// illegal channel
|
||||
return;
|
||||
}
|
||||
|
||||
uint8_t not_buf[3];
|
||||
not_buf[0] = channel; // ch
|
||||
not_buf[1] = spi_rxbuf[1];
|
||||
not_buf[2] = spi_rxbuf[2];
|
||||
|
||||
// not_buf[1] = (INSTRUCTION.recording_channel | 0xFF00) >> 8;
|
||||
// not_buf[2] = (INSTRUCTION.recording_channel | 0x00FF);
|
||||
|
||||
uint8_t data_size = headstage_notify_append_data(not_buf);
|
||||
|
||||
if (data_size >= BLE_NOT_BUFF_SIZE) {
|
||||
headstage_notify_flip_buffer();
|
||||
headstage_notify_send();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void headstage_notify_set_timestamp() {
|
||||
not_time_stamp = headstage_time_stamp_us();
|
||||
|
||||
|
||||
-68
@@ -120,72 +120,4 @@ static void AppendSPITX(uint8_t index, uint32_t value){
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn headstage_spi_callback
|
||||
*
|
||||
* description: callback function to deal with data transmission between DBS and CC2650
|
||||
*/
|
||||
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction) {
|
||||
switch(SPICallBack){
|
||||
case CONTINUOUS_TRANS:{
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER:{
|
||||
SPICallBack = FLUSH_BUFFER2;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER2:{
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
// headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case ONE_SHOT_SPI:{
|
||||
SPICallBack = FLUSH_BUFFER;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_MOSI:{
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_REG:{
|
||||
check_reg_counter ++;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case CLOSE_SPI:{
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPI_close(headstage_spi_handle);
|
||||
break;
|
||||
}
|
||||
|
||||
case END_TRANSMIT:{
|
||||
tx_put_u24(0, 0);
|
||||
SPICallBack = CONTINUOUS_TRANS;
|
||||
break;
|
||||
}
|
||||
default:{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
-1
@@ -561,7 +561,6 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
|
||||
headstage_init_device_info();
|
||||
|
||||
headstage_init();
|
||||
InitDBSRegister();
|
||||
|
||||
for (;;) {
|
||||
// Waits for a signal to the semaphore associated with the calling thread.
|
||||
|
||||
+5
-3
@@ -2,19 +2,21 @@
|
||||
|
||||
folder=$(basename "$(pwd)")
|
||||
|
||||
if [ "$folder" == "bioprocc2650" ]; then
|
||||
if [ "$folder" == "ti" ]; then
|
||||
|
||||
input="./Neulive_sti_cali.txt"
|
||||
output="./simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage_cali_sti.h"
|
||||
|
||||
#variable
|
||||
declare -i current_line=96
|
||||
declare -i current_line=232
|
||||
declare -i col_index=0
|
||||
declare -i row_index=0
|
||||
|
||||
#constant
|
||||
declare -i COL_MAX=8
|
||||
declare -i START_ROW=27
|
||||
|
||||
#this is number of Neulive_sti_cali.txt
|
||||
declare -i START_ROW=29
|
||||
declare -i UN_USED_ROW=$START_ROW-1
|
||||
|
||||
MAC="MAC"
|
||||
|
||||
Reference in New Issue
Block a user