Compare commits
59 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
| 9f33098b52 | |||
| dd9f64662e | |||
| a80ab9a72f | |||
| a348b9553d | |||
| 2937fa6a11 | |||
| 4a973421df | |||
| 521e241978 | |||
| d1ba348ea0 | |||
| 8686220e28 | |||
| 91e62474d1 | |||
| 734da9a27e | |||
| bd48ac8d49 | |||
| 9f68a07d31 | |||
| 87cac38444 | |||
| 7f163e85c3 | |||
| 7880fce151 | |||
| abf67f5dd4 | |||
| cf9766c786 | |||
| 7063a2460a | |||
| 11a6389a83 | |||
| 9dde948902 | |||
| 9209d9dff7 | |||
| acd0080929 | |||
| 8ae43d0628 | |||
| 1cde4cfe02 | |||
| 764bd9364d | |||
| b5e0026f2e | |||
| 823016d4b7 | |||
| bee57486e0 | |||
| 214222cb1e | |||
| 38572e128d | |||
| 9e19642081 | |||
| 5f2a258f49 | |||
| d5158775b8 | |||
| 282b8077a7 | |||
| 5b6430cec9 | |||
| 9484008d1e | |||
| bd0c282d25 | |||
| acd590de44 | |||
| b8d96c32b0 | |||
| c3ab78e16a | |||
| fde824ee34 | |||
| fc3adb450c | |||
| 747752640a | |||
| 7a73097666 | |||
| 8a95874b0b | |||
| 9db0984a92 | |||
| b9c9cc0bbc | |||
| cd44c2ecaa | |||
| 3bb5cee129 | |||
| 2480d7775f | |||
| 3b9e972397 | |||
| 36df3abed1 | |||
| 918584c915 | |||
| cc0a21c364 | |||
| 388c06efe7 | |||
| 8bcb4cd27e | |||
| 5d88871e58 | |||
| 8635b1b878 |
@@ -8,7 +8,7 @@ no device y=ax+b MAC a+ b+ a- b- avg
|
||||
7 c652 c652 18:04:ED:37:C6:52 2024 -7687 2086 -11283 4.88850143182858
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8 c5ed c5ed 18:04:ED:37:C5:ED 2231 -1711 2353 -70845 4.45265043545859
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||||
9 9bef 9bef 0081F9E49BEF 2383 -8585 2415 -20347 4.2758539244186
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10 8b50 8b50 00:81:F9:E4:8B:50 2369 -11005 2360 -11797 4.30475635707671
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10 8b50 8b50 00:81:F9:E4:8B:50 2366 -5223 2402 -14971 4.35162291666667
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11 c641 c641 18:04:ED:37:C6:41 2090 4616 1997 -40665 5.07591391714942
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12 E8E6 E8E6 A4:DA:32:D4:E8:E6 2306 -88454 2418 -15140 4.2686494968089
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13 E73B E73B A4:DA:32:D4:E7:3B 2262 -564 2298 44746 4.35551198222141
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@@ -16,8 +16,8 @@ no device y=ax+b MAC a+ b+ a- b- avg
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15 E871 E871 A4:DA:32:D4:E8:71 2175 -4549 2220 31468 4.60684608395208
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16 EFC4 EFC4 A4:DA:32:D4:EF:C4 2348 -4371 2374 -26606 4.45106768611704
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17 EF85 EF85 A4:DA:32:D4:EF:85 2136 -3339 2189 -30040 4.61909624778354
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18 E7DA E7DA A4:DA:32:D4:E7:DA 2081 -3015 2122 -21543 4.79766509652981
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19 E6EA E6EA A4:DA:32:D4:E6:EA 2039 -262 2127 -47259 4.79384458739747
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18 E7DA E7DA A4:DA:32:D4:E7:DA 2096 -10653 2054 -14255 3.73011080492424
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19 E6EA E6EA A4:DA:32:D4:E6:EA 2074 -13075 2031 -13585 3.77641447962488
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20 EEDB EEDB A4:DA:32:D4:EE:DB 2214 -1170 2351 -24636 4.44485358085645
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21 E73A E73A A4:DA:32:D4:E7:3A 2210 -4855 2339 -16434 4.47776494604746
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22 E6CF E6CF A4:DA:32:D4:E6:CF 2135 -5206 2193 -30885 4.73462680884304
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BIN
Binary file not shown.
BIN
Binary file not shown.
+6
-4
@@ -102,8 +102,8 @@ typedef enum {
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FLUSH_BUFFER2, // clean SPI buffer twice
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READ_REG, // read DBS register value, used after a "read" SPI instruction (MISO)
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READ_REG2, // read DBS register value, used after a "read" SPI instruction (MISO)
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END_TRANSMIT, // read DBS register value, used after a "read" SPI instruction (MISO)
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ONE_SHOT_SPI, // end spi instruction
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ONE_SHOT_FLUSH, // read DBS register value, used after a "read" SPI instruction (MISO)
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CONTI_SPI_WITH_FLUSH, // end spi instruction
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READ_MOSI
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} SPI_CB_MODE;
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@@ -119,6 +119,8 @@ static bool ConnectState = false;
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static bool ErrorRestart = false;
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static SPI_CB_MODE SPICallBack;
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static uint8 adc_spi_en_switch = 1;
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static bool rewrite_rec_en = false;
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static bool rewrite_sti_en = false;
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/*
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* Let C = command, S = status;
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@@ -214,7 +216,7 @@ extern ICall_Semaphore semaphore;
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// command return characteristic
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#define BLE_CDR_BUFF_CHAR SIMPLEPROFILE_CHAR2
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#define BLE_CDR_BUFF_SIZE SIMPLEPROFILE_CHAR2_LEN
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#define BLE_CDR_SAMLL_SIZE 10
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#define BLE_CDR_SMALL_SIZE 10
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// instruction input characteristic
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#define BLE_INS_BUFF_CHAR SIMPLEPROFILE_CHAR3
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@@ -356,7 +358,7 @@ static uint16_t CONNECT_HANDLE = 0;
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/**
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* command instruction buffer
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*/
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static uint8_t cdr_buf[BLE_CDR_SAMLL_SIZE] = {0};
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static uint8_t cdr_buf[BLE_CDR_SMALL_SIZE] = {0};
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/*====================
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==== event table ====
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+4
-5
@@ -27,14 +27,14 @@ static void SendCaliValue(uint8_t CaliNumber){
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// ch = 2 * (CaliNumber % 4);
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// uint8_t gain_level = CaliNumber / 4; // 0:gain, 1:offset
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uint8_t channel_number = 8, index = 1;
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uint8_t channel_number = 8, index = 2;
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uint8_t gain_level = 0;
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if(CaliNumber < 4){
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gain_level = CaliNumber;
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}
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cali_buf[0] = CHIP_ID;
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cali_buf[1] = CHIP_ID;
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for(int i=0 ; i<channel_number ; i++){
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cali_buf[index++] = (uint8_t) (CaliTable.Ch[i].Gain[gain_level] >> 8) & 0xFF;
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cali_buf[index++] = (uint8_t) CaliTable.Ch[i].Gain[gain_level] & 0x00FF;
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@@ -42,9 +42,8 @@ static void SendCaliValue(uint8_t CaliNumber){
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cali_buf[index++] = (uint8_t) CaliTable.Ch[i].Offset[gain_level] & 0x00FF;
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}
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// for(int i=1 ; i<BLE_CDR_BUFF_SIZE ; i++){
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// cali_buf[i] = i;
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// }
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cali_buf[0] = index - 1;
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SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, index, cali_buf);
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}
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+8
-8
@@ -192,18 +192,18 @@ struct _StiCaliStiTable{
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||||
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#elif defined(BOARD_A4_DA_32_D4_E7_DA)
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{
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.p_ch.coefficient = 2081,
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||||
.p_ch.offset = -3015,
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.n_ch.coefficient = 2122,
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.n_ch.offset = -21543
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.p_ch.coefficient = 4834,
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||||
.p_ch.offset = -10653,
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.n_ch.coefficient = 4628,
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.n_ch.offset = -14255
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};
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#elif defined(BOARD_A4_DA_32_D4_E6_EA)
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{
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.p_ch.coefficient = 2039,
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.p_ch.offset = -262,
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.n_ch.coefficient = 2127,
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||||
.n_ch.offset = -47259
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.p_ch.coefficient = 4980,
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.p_ch.offset = -13075,
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.n_ch.coefficient = 4660,
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.n_ch.offset = -13585
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};
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#elif defined(BOARD_A4_DA_32_D4_EE_DB)
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+60
-60
@@ -2,7 +2,7 @@
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#ifndef NEU_CALI_TABLE
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#define NEU_CALI_TABLE
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#define BOARD_TEST
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#define BOARD_A4_DA_32_D4_E7_DA
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typedef struct _SingleChannelCali{
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uint16_t Gain[4];
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@@ -1673,70 +1673,70 @@ struct _CaliTable{
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#elif defined(BOARD_A4_DA_32_D4_E7_DA)
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{
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.DeviceName = "BOARD_A4_DA_32_D4_E7_DA",
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.Ch[0].Gain[0] = 49,
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.Ch[0].Offset[0] = -13,
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.Ch[1].Gain[0] = 49,
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.Ch[0].Gain[0] = 48,
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.Ch[0].Offset[0] = -14,
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.Ch[1].Gain[0] = 48,
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.Ch[1].Offset[0] = 26,
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.Ch[2].Gain[0] = 49,
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.Ch[2].Offset[0] = -14,
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.Ch[3].Gain[0] = 49,
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.Ch[2].Gain[0] = 48,
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.Ch[2].Offset[0] = -15,
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.Ch[3].Gain[0] = 48,
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.Ch[3].Offset[0] = 17,
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.Ch[4].Gain[0] = 49,
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.Ch[4].Offset[0] = 5,
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.Ch[5].Gain[0] = 49,
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.Ch[5].Offset[0] = -2,
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.Ch[6].Gain[0] = 47,
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.Ch[6].Offset[0] = -8,
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.Ch[7].Gain[0] = 47,
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.Ch[7].Offset[0] = -11,
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.Ch[0].Gain[1] = 359,
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.Ch[0].Offset[1] = -54,
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.Ch[1].Gain[1] = 359,
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.Ch[4].Gain[0] = 48,
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.Ch[4].Offset[0] = 4,
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.Ch[5].Gain[0] = 48,
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||||
.Ch[5].Offset[0] = -3,
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.Ch[6].Gain[0] = 46,
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||||
.Ch[6].Offset[0] = -9,
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||||
.Ch[7].Gain[0] = 46,
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||||
.Ch[7].Offset[0] = -12,
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.Ch[0].Gain[1] = 354,
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.Ch[0].Offset[1] = -55,
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.Ch[1].Gain[1] = 355,
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||||
.Ch[1].Offset[1] = 230,
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.Ch[2].Gain[1] = 362,
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||||
.Ch[2].Offset[1] = -70,
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||||
.Ch[3].Gain[1] = 361,
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||||
.Ch[3].Offset[1] = 164,
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||||
.Ch[4].Gain[1] = 361,
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||||
.Ch[4].Offset[1] = 72,
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||||
.Ch[5].Gain[1] = 360,
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||||
.Ch[2].Gain[1] = 356,
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||||
.Ch[2].Offset[1] = -71,
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.Ch[3].Gain[1] = 355,
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.Ch[3].Offset[1] = 163,
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.Ch[4].Gain[1] = 356,
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||||
.Ch[4].Offset[1] = 73,
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||||
.Ch[5].Gain[1] = 355,
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||||
.Ch[5].Offset[1] = 22,
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||||
.Ch[6].Gain[1] = 345,
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||||
.Ch[6].Offset[1] = -23,
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||||
.Ch[7].Gain[1] = 345,
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.Ch[7].Offset[1] = -39,
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||||
.Ch[0].Gain[2] = 1482,
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||||
.Ch[0].Offset[2] = -197,
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||||
.Ch[1].Gain[2] = 1372,
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.Ch[1].Offset[2] = 946,
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.Ch[2].Gain[2] = 1473,
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.Ch[2].Offset[2] = -275,
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||||
.Ch[3].Gain[2] = 1443,
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||||
.Ch[3].Offset[2] = 686,
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||||
.Ch[4].Gain[2] = 1477,
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||||
.Ch[4].Offset[2] = 313,
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||||
.Ch[5].Gain[2] = 1479,
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||||
.Ch[5].Offset[2] = 104,
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||||
.Ch[6].Gain[2] = 1424,
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.Ch[6].Offset[2] = -75,
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.Ch[7].Gain[2] = 1436,
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.Ch[6].Gain[1] = 336,
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.Ch[6].Offset[1] = -21,
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||||
.Ch[7].Gain[1] = 335,
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||||
.Ch[7].Offset[1] = -37,
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||||
.Ch[0].Gain[2] = 1458,
|
||||
.Ch[0].Offset[2] = -198,
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||||
.Ch[1].Gain[2] = 1347,
|
||||
.Ch[1].Offset[2] = 944,
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||||
.Ch[2].Gain[2] = 1455,
|
||||
.Ch[2].Offset[2] = -271,
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||||
.Ch[3].Gain[2] = 1423,
|
||||
.Ch[3].Offset[2] = 677,
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||||
.Ch[4].Gain[2] = 1454,
|
||||
.Ch[4].Offset[2] = 320,
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||||
.Ch[5].Gain[2] = 1454,
|
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.Ch[5].Offset[2] = 106,
|
||||
.Ch[6].Gain[2] = 1369,
|
||||
.Ch[6].Offset[2] = -65,
|
||||
.Ch[7].Gain[2] = 1381,
|
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.Ch[7].Offset[2] = -134,
|
||||
.Ch[0].Gain[3] = 2821,
|
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.Ch[0].Offset[3] = -357,
|
||||
.Ch[1].Gain[3] = 1262,
|
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.Ch[1].Offset[3] = 1440,
|
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.Ch[2].Gain[3] = 2746,
|
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.Ch[2].Offset[3] = -506,
|
||||
.Ch[3].Gain[3] = 1934,
|
||||
.Ch[3].Offset[3] = 1131,
|
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.Ch[4].Gain[3] = 2659,
|
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.Ch[4].Offset[3] = 576,
|
||||
.Ch[5].Gain[3] = 2873,
|
||||
.Ch[5].Offset[3] = 212,
|
||||
.Ch[6].Gain[3] = 2770,
|
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.Ch[6].Offset[3] = -142,
|
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.Ch[7].Gain[3] = 2764,
|
||||
.Ch[7].Offset[3] = -239
|
||||
.Ch[0].Gain[3] = 2775,
|
||||
.Ch[0].Offset[3] = -362,
|
||||
.Ch[1].Gain[3] = 1257,
|
||||
.Ch[1].Offset[3] = 1442,
|
||||
.Ch[2].Gain[3] = 2713,
|
||||
.Ch[2].Offset[3] = -503,
|
||||
.Ch[3].Gain[3] = 1929,
|
||||
.Ch[3].Offset[3] = 1125,
|
||||
.Ch[4].Gain[3] = 2621,
|
||||
.Ch[4].Offset[3] = 580,
|
||||
.Ch[5].Gain[3] = 2834,
|
||||
.Ch[5].Offset[3] = 206,
|
||||
.Ch[6].Gain[3] = 2698,
|
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.Ch[6].Offset[3] = -115,
|
||||
.Ch[7].Gain[3] = 2690,
|
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.Ch[7].Offset[3] = -250
|
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};
|
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|
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#elif defined(BOARD_A4_DA_32_D4_E6_EA)
|
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|
||||
+3
-3
@@ -27,7 +27,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
|
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check_reg_counter = 0;
|
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if(check_ins(instruction_to_fit)){
|
||||
NEULIVE_STATE.state = next_state;
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
|
||||
// update rec_sti_command
|
||||
if(!(rec_sti_command & ENABLE_STI)){
|
||||
@@ -70,7 +70,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
|
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IsFirstData = true;
|
||||
}
|
||||
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
ReopenSPI();
|
||||
}
|
||||
headstage_spi_transaction(3);
|
||||
@@ -167,7 +167,7 @@ static void check_sti_t1_t5(NEU_WORK_STATE next_state){
|
||||
else{
|
||||
NEULIVE_STATE.state = next_state;
|
||||
}
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
headstage_spi_transaction(3);
|
||||
}
|
||||
|
||||
|
||||
+214
@@ -0,0 +1,214 @@
|
||||
|
||||
#ifndef DBS_OBJECT_H
|
||||
#define DBS_OBJECT_H
|
||||
|
||||
#include "neu/headstage_spi.h"
|
||||
|
||||
#define SYS_RESERVED_INDEX 0
|
||||
#define SYS_GENERAL_ENABLE_INDEX 1
|
||||
#define SYS_LNA_BIOS1_INDEX 2
|
||||
#define SYS_LNA_BIOS2_INDEX 3
|
||||
#define SYS_STI_CLK_RATIO_INDEX 4
|
||||
|
||||
#define REC_CHANNEL_INDEX 0
|
||||
#define REC_GAIN_INDEX 1
|
||||
#define REC_ADC_CLOCK_INDEX 2
|
||||
|
||||
#define STI_ENABLE_INDEX 0
|
||||
#define STI_AMP_POS_INDEX 1
|
||||
#define STI_AMP_NEG_INDEX 2
|
||||
#define STI_POLARITY_INDEX 3
|
||||
#define STI_CYCLE_CH01_INDEX 4
|
||||
#define STI_CYCLE_CH23_INDEX 5
|
||||
#define STI_CYCLE_CH45_INDEX 6
|
||||
#define STI_CYCLE_CH67_INDEX 7
|
||||
#define STI_CLK_RATIO_INDEX 8
|
||||
#define STI_ARBITRARY_EN_INDEX 9
|
||||
#define STI_MODE_INDEX 10
|
||||
#define STI_DURATION0_INDEX 11
|
||||
#define STI_DURATION1_INDEX 12
|
||||
#define STI_DURATION2_INDEX 13
|
||||
#define STI_DURATION3_INDEX 14
|
||||
|
||||
//#define DBS_REGISTER \
|
||||
// uint8_t address; \
|
||||
// void (*write_reg) (DBSRegister *self, uint32_t reg_value); \
|
||||
// uint32_t (*read_reg) (DBSRegister *self)
|
||||
|
||||
typedef struct _DBSRegister{
|
||||
uint8_t address;
|
||||
bool WriteRegister, CheckRegister;
|
||||
void (*write_reg) (uint8_t self_address, uint16_t reg_value);
|
||||
void (*read_reg) (struct _DBSRegister *self);
|
||||
}DBSRegister;
|
||||
|
||||
void write_reg(uint8_t self_address, uint16_t reg_value){
|
||||
spi_txbuf[0] = 0x80 | self_address;
|
||||
spi_txbuf[1] = (reg_value >> 8) & 0xFF ;
|
||||
spi_txbuf[2] = reg_value & 0xFF;
|
||||
|
||||
// self->WriteRegister = false;
|
||||
// self->CheckRegister = true;
|
||||
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
|
||||
void read_reg(DBSRegister *self){
|
||||
spi_txbuf[0] = 0x7F & self->address;
|
||||
spi_txbuf[1] = 0; // it's don't care actually
|
||||
spi_txbuf[2] = 0; // it's don't care actually
|
||||
SPICallBack = READ_REG;
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
}
|
||||
|
||||
static uint16_t sys_register_default_value[5] = {
|
||||
0x0000,
|
||||
0x40F2,
|
||||
0x0210,
|
||||
0x4210,
|
||||
0x0002
|
||||
};
|
||||
|
||||
static uint16_t rec_register_value[3];
|
||||
static uint16_t sti_register_value[43];
|
||||
static uint16_t fast_settle_param[43];
|
||||
static void init_fast_settle();
|
||||
|
||||
static DBSRegister sys_register[5];
|
||||
static DBSRegister rec_register[3];
|
||||
static DBSRegister sti_register[43];
|
||||
|
||||
static void InitSysRegister(){
|
||||
sys_register[SYS_RESERVED_INDEX].address = 0x00;
|
||||
sys_register[SYS_GENERAL_ENABLE_INDEX].address = 47; // general enable
|
||||
sys_register[SYS_LNA_BIOS1_INDEX].address = 57;
|
||||
sys_register[SYS_LNA_BIOS2_INDEX].address = 58;
|
||||
sys_register[SYS_STI_CLK_RATIO_INDEX].address = 52;
|
||||
|
||||
for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
|
||||
sys_register[i].WriteRegister = false;
|
||||
sys_register[i].CheckRegister = false;
|
||||
sys_register[i].write_reg = &write_reg;
|
||||
sys_register[i].read_reg = &read_reg;
|
||||
}
|
||||
}
|
||||
|
||||
static void InitRecRegister(){
|
||||
rec_register[REC_CHANNEL_INDEX].address = 48;
|
||||
rec_register[REC_GAIN_INDEX].address = 49;
|
||||
rec_register[REC_ADC_CLOCK_INDEX].address = 51; // sampling rate
|
||||
|
||||
for(int i=0 ; i<sizeof(rec_register)/sizeof(DBSRegister) ; i++){
|
||||
rec_register[i].WriteRegister = false;
|
||||
rec_register[i].CheckRegister = false;
|
||||
rec_register[i].write_reg = &write_reg;
|
||||
rec_register[i].read_reg = &read_reg;
|
||||
}
|
||||
|
||||
rec_register_value[REC_CHANNEL_INDEX] = 0;
|
||||
rec_register_value[REC_GAIN_INDEX] = 1;
|
||||
rec_register_value[REC_ADC_CLOCK_INDEX] = 100;
|
||||
}
|
||||
|
||||
static void InitStiRegister(){
|
||||
sti_register[STI_ENABLE_INDEX].address = 46;
|
||||
sti_register[STI_AMP_POS_INDEX].address = 37;
|
||||
sti_register[STI_AMP_NEG_INDEX].address = 38;
|
||||
sti_register[STI_POLARITY_INDEX].address = 40;
|
||||
sti_register[STI_CYCLE_CH01_INDEX].address = 42;
|
||||
sti_register[STI_CYCLE_CH23_INDEX].address = 43;
|
||||
sti_register[STI_CYCLE_CH45_INDEX].address = 44;
|
||||
sti_register[STI_CYCLE_CH67_INDEX].address = 45;
|
||||
sti_register[STI_CLK_RATIO_INDEX].address = 52;
|
||||
sti_register[STI_ARBITRARY_EN_INDEX].address = 54;
|
||||
sti_register[STI_MODE_INDEX].address = 56;
|
||||
|
||||
for(int ch=0 ; ch<8 ; ch++){
|
||||
sti_register[ch*4 + STI_DURATION0_INDEX].address = ch*4 + 1;
|
||||
sti_register[ch*4 + STI_DURATION1_INDEX].address = ch*4 + 2;
|
||||
sti_register[ch*4 + STI_DURATION2_INDEX].address = ch*4 + 3;
|
||||
sti_register[ch*4 + STI_DURATION3_INDEX].address = ch*4 + 4;
|
||||
}
|
||||
|
||||
for(int i=0 ; i<sizeof(sti_register)/sizeof(DBSRegister) ; i++){
|
||||
sti_register[i].WriteRegister = false;
|
||||
sti_register[i].CheckRegister = false;
|
||||
sti_register[i].write_reg = &write_reg;
|
||||
sti_register[i].read_reg = &read_reg;
|
||||
}
|
||||
|
||||
sti_register_value[STI_AMP_POS_INDEX] = 1;
|
||||
sti_register_value[STI_AMP_NEG_INDEX] = 1;
|
||||
}
|
||||
|
||||
static void InitDBSRegister(){
|
||||
InitSysRegister();
|
||||
InitRecRegister();
|
||||
InitStiRegister();
|
||||
init_fast_settle();
|
||||
|
||||
for(int i=1 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
|
||||
sys_register[i].WriteRegister = true;
|
||||
}
|
||||
|
||||
sys_register[0].CheckRegister = true;
|
||||
sys_register[0].write_reg(sys_register[0].address, sys_register_default_value[0]);
|
||||
// flag_notify(EVT_NEU_SPI);
|
||||
}
|
||||
|
||||
static void ResetDBSRegister(){
|
||||
for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
|
||||
sys_register[i].WriteRegister = false;
|
||||
sys_register[i].CheckRegister = false;
|
||||
sys_register[i].write_reg = &write_reg;
|
||||
sys_register[i].read_reg = &read_reg;
|
||||
}
|
||||
|
||||
for(int i=0 ; i<sizeof(rec_register)/sizeof(DBSRegister) ; i++){
|
||||
rec_register[i].WriteRegister = false;
|
||||
rec_register[i].CheckRegister = false;
|
||||
rec_register[i].write_reg = &write_reg;
|
||||
rec_register[i].read_reg = &read_reg;
|
||||
}
|
||||
|
||||
for(int i=0 ; i<sizeof(sti_register)/sizeof(DBSRegister) ; i++){
|
||||
sti_register[i].WriteRegister = false;
|
||||
sti_register[i].CheckRegister = false;
|
||||
sti_register[i].write_reg = &write_reg;
|
||||
sti_register[i].read_reg = &read_reg;
|
||||
}
|
||||
}
|
||||
|
||||
static uint16_t fast_settle_param[43];
|
||||
static void init_fast_settle(){
|
||||
uint8_t ch = 7;
|
||||
uint8_t t1=25, t2=0, t3=25 , t4=0, t5=0;
|
||||
|
||||
// setting t1~t5
|
||||
fast_settle_param[ch*4 + STI_DURATION0_INDEX] = (t2 & 0x003F) << 10 | (t1 & 0x03FF);
|
||||
fast_settle_param[ch*4 + STI_DURATION1_INDEX] = (t4 & 0x0003) << 14 | (t3 & 0x03FF) << 4 | (t2 & 0x03C0) >> 6;
|
||||
fast_settle_param[ch*4 + STI_DURATION2_INDEX] = (t4 & 0x0007FFFC) >> 2;
|
||||
fast_settle_param[ch*4 + STI_DURATION3_INDEX] = t5;
|
||||
|
||||
// cycle number
|
||||
fast_settle_param[STI_CYCLE_CH67_INDEX] = 10 << 8 | 0;
|
||||
|
||||
// set polarity, it's don't care in fast settle
|
||||
fast_settle_param[STI_POLARITY_INDEX] = 0;
|
||||
|
||||
// set stimulate mode
|
||||
fast_settle_param[STI_MODE_INDEX] = 0;
|
||||
// INSTRUCTION.sti_mode = 0; // 1 = continuous mode; 0 = limit mode
|
||||
// INSTRUCTION.sti_h_bridge = 0; // voltage sti must use H-bridge
|
||||
// INSTRUCTION.sti_ref = 0; // 1 = GND; 0 = Vref
|
||||
|
||||
// using minimum amplitude
|
||||
fast_settle_param[STI_AMP_POS_INDEX] = 0;
|
||||
fast_settle_param[STI_AMP_NEG_INDEX] = 0;
|
||||
|
||||
// using ch8 to fast settle
|
||||
fast_settle_param[STI_ENABLE_INDEX] = 0b0000000010000000; // 0bxxxx_xxxv_cccc_cccc, c = current; v = volt, x = don't care
|
||||
}
|
||||
|
||||
#endif
|
||||
+745
-251
File diff suppressed because it is too large
Load Diff
+20
-6
@@ -6,7 +6,7 @@
|
||||
|
||||
static uint16_t UserCode2StiCode(uint16_t amp, uint8_t positive_ch){
|
||||
// get real current value (uA)
|
||||
uint32_t sti_code, real_amp = amp * 5;
|
||||
int32_t sti_code, real_amp = amp * 5;
|
||||
|
||||
if(StiCaliTable.p_ch.coefficient == 10000 && StiCaliTable.p_ch.offset == 0){
|
||||
return amp;
|
||||
@@ -15,15 +15,29 @@ static uint16_t UserCode2StiCode(uint16_t amp, uint8_t positive_ch){
|
||||
return amp;
|
||||
}
|
||||
|
||||
// trans into sti code
|
||||
if(positive_ch){
|
||||
sti_code = StiCaliTable.p_ch.coefficient * real_amp + StiCaliTable.p_ch.offset;
|
||||
if(real_amp < 200){
|
||||
sti_code = 2023 * real_amp -4170;
|
||||
}
|
||||
else if(real_amp <500){
|
||||
sti_code = 2077 * real_amp - 11729;
|
||||
}
|
||||
else{
|
||||
sti_code = StiCaliTable.n_ch.coefficient * real_amp + StiCaliTable.n_ch.offset;
|
||||
sti_code = 2096 * real_amp - 45970;
|
||||
}
|
||||
|
||||
sti_code = sti_code / 10000;
|
||||
// trans into sti code
|
||||
// if(positive_ch){
|
||||
// sti_code = StiCaliTable.p_ch.coefficient * real_amp + StiCaliTable.p_ch.offset;
|
||||
// }
|
||||
// else{
|
||||
// sti_code = StiCaliTable.n_ch.coefficient * real_amp + StiCaliTable.n_ch.offset;
|
||||
// }
|
||||
|
||||
if(sti_code <= 10000){
|
||||
sti_code = 10000;
|
||||
}
|
||||
|
||||
sti_code = (sti_code+5000) / 10000;
|
||||
return (uint16_t) (sti_code);
|
||||
}
|
||||
|
||||
|
||||
+6
-6
@@ -2,16 +2,16 @@
|
||||
#ifndef VERSION_DATE
|
||||
#define VERSION_DATE
|
||||
|
||||
#define VERSION_DATE_YEAR 20
|
||||
#define VERSION_DATE_MONTH 7
|
||||
#define VERSION_DATE_DAY 20
|
||||
#define VERSION_DATE_YEAR 21
|
||||
#define VERSION_DATE_MONTH 1
|
||||
#define VERSION_DATE_DAY 21
|
||||
#define VERSION_DATE_HOUR 17
|
||||
#define VERSION_DATE_MINUTE 48
|
||||
#define VERSION_DATE_MINUTE 39
|
||||
|
||||
// this is NOT the version hash !!
|
||||
// it's the last version hash
|
||||
#define VERSION_HASH 81d5d86890d1da5dfb3ccc7e1756261c3ecbf485
|
||||
#define VERSION_GIT_BRANCH Neulive20_developement_linux
|
||||
#define VERSION_HASH dd9f64662e1a9a993a1c28c18256d230f429f8ac
|
||||
#define VERSION_GIT_BRANCH neulive2_E7DA_special_version
|
||||
|
||||
static void get_board_name(char *board_name_ch, uint8 *board_name_int, uint8 name_size){
|
||||
uint8 name_offset = 18;
|
||||
|
||||
+50
-3
@@ -8,11 +8,60 @@
|
||||
#error "headstage/headstage_notify.h not included"
|
||||
#endif
|
||||
|
||||
#include "headstage_dbs_object.h"
|
||||
|
||||
#define NOT_BUF_OFFSET_INIT 8
|
||||
|
||||
static uint8_t not_buf_offset = NOT_BUF_OFFSET_INIT;
|
||||
static uint32_t not_time_stamp = 0;
|
||||
|
||||
static void headstage_notify_set_timestamp();
|
||||
static void headstage_notify_flip_buffer();
|
||||
static uint8_t headstage_notify_append_data(uint8_t *data_value);
|
||||
|
||||
/**
|
||||
* @fn headstage_neu_append_notify_data
|
||||
*/
|
||||
#define CHANNEL_VALID (INSTRUCTION.recording_channel & (0x0001 << channel))
|
||||
static void headstage_neu_append_notify_data() {
|
||||
|
||||
uint8_t channel = spi_rxbuf[0];
|
||||
|
||||
// close-reopen SPI, if the first channel received is invalid
|
||||
if(IsFirstData){
|
||||
// start record
|
||||
if((INSTRUCTION.recording_channel & (0x0001 << channel)) && (channel < 16)){
|
||||
IsFirstData = false;
|
||||
}
|
||||
// restart SPI
|
||||
else{
|
||||
SPI_close(headstage_spi_handle);
|
||||
ReopenSPI();
|
||||
IsFirstData = true;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// discard illegal channel
|
||||
uint16_t valid_channel = INSTRUCTION.recording_channel & (0x0001 << channel);
|
||||
if(!(INSTRUCTION.recording_channel & (0x0001 << channel)) || (channel > 15)){
|
||||
// illegal channel
|
||||
return;
|
||||
}
|
||||
|
||||
uint8_t not_buf[2];
|
||||
not_buf[0] = (channel & 0x0F) << 4 | (spi_rxbuf[1] & 0x0F);
|
||||
not_buf[1] = spi_rxbuf[2];
|
||||
|
||||
uint8_t data_size = headstage_notify_append_data(not_buf);
|
||||
|
||||
if (data_size >= BLE_NOT_BUFF_SIZE) {
|
||||
headstage_notify_flip_buffer();
|
||||
headstage_notify_send();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void headstage_notify_set_timestamp() {
|
||||
not_time_stamp = headstage_time_stamp_us();
|
||||
|
||||
@@ -23,7 +72,7 @@ static void headstage_notify_set_timestamp() {
|
||||
}
|
||||
|
||||
static void headstage_notify_flip_buffer() {
|
||||
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 3;
|
||||
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 2;
|
||||
|
||||
headstage_notify_buffer[0] = CHIP_ID;
|
||||
headstage_notify_buffer[1] = data_count;
|
||||
@@ -40,11 +89,9 @@ static uint8_t headstage_notify_append_data(uint8_t *data_value) {
|
||||
if (data_value == NULL) {
|
||||
headstage_notify_buffer[not_buf_offset++] = 0x00;
|
||||
headstage_notify_buffer[not_buf_offset++] = 0x00;
|
||||
headstage_notify_buffer[not_buf_offset++] = 0x00;
|
||||
} else {
|
||||
headstage_notify_buffer[not_buf_offset++] = data_value[0];
|
||||
headstage_notify_buffer[not_buf_offset++] = data_value[1];
|
||||
headstage_notify_buffer[not_buf_offset++] = data_value[2];
|
||||
}
|
||||
|
||||
if (not_buf_offset >= BLE_NOT_BUFF_SIZE - 1) {
|
||||
|
||||
+4
-2
@@ -4,6 +4,7 @@
|
||||
|
||||
#include "headstage_instruction.h"
|
||||
#include "neu/headstage_spi.h"
|
||||
#include "headstage_dbs_object.h"
|
||||
|
||||
static void ResetINSTRUCTION();
|
||||
|
||||
@@ -25,7 +26,7 @@ static void MCUReset(){
|
||||
spi_txbuf[i] = 0;
|
||||
spi_rxbuf[i] = 0;
|
||||
}
|
||||
SPICallBack = ONE_SHOT_SPI;
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
ReopenSPI();
|
||||
|
||||
for(int i=0 ; i<SPI_LED_BUFF_SIZE ; i++){
|
||||
@@ -33,7 +34,7 @@ static void MCUReset(){
|
||||
}
|
||||
|
||||
// CIS buffer reset
|
||||
for(int i=0 ; i<BLE_CDR_SAMLL_SIZE ; i++){
|
||||
for(int i=0 ; i<BLE_CDR_SMALL_SIZE ; i++){
|
||||
cdr_buf[i] = 0;
|
||||
}
|
||||
|
||||
@@ -70,6 +71,7 @@ static void DBSReset(){
|
||||
static void Neu2Reset(){
|
||||
DBSReset();
|
||||
MCUReset();
|
||||
InitDBSRegister();
|
||||
}
|
||||
|
||||
static void ResetINSTRUCTION(){
|
||||
|
||||
+67
@@ -120,4 +120,71 @@ static void AppendSPITX(uint8_t index, uint32_t value){
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn headstage_spi_callback
|
||||
*
|
||||
* description: callback function to deal with data transmission between DBS and CC2650
|
||||
*/
|
||||
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction) {
|
||||
switch(SPICallBack){
|
||||
case CONTINUOUS_TRANS:{
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER:{
|
||||
SPICallBack = FLUSH_BUFFER2;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case FLUSH_BUFFER2:{
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
// headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
case CONTI_SPI_WITH_FLUSH:{
|
||||
SPICallBack = FLUSH_BUFFER;
|
||||
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
|
||||
spi_txbuf[i] = 0x00;
|
||||
}
|
||||
headstage_spi_transaction(SPI_BUFFER_SIZE);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_MOSI:{
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case READ_REG:{
|
||||
check_reg_counter ++;
|
||||
flag_notify(EVT_NEU_SPI);
|
||||
break;
|
||||
}
|
||||
|
||||
case CLOSE_SPI:{
|
||||
SPICallBack = CONTI_SPI_WITH_FLUSH;
|
||||
SPI_close(headstage_spi_handle);
|
||||
break;
|
||||
}
|
||||
|
||||
case ONE_SHOT_FLUSH:{
|
||||
tx_put_u24(0, 0);
|
||||
break;
|
||||
}
|
||||
default:{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
+1
@@ -561,6 +561,7 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
|
||||
headstage_init_device_info();
|
||||
|
||||
headstage_init();
|
||||
InitDBSRegister();
|
||||
|
||||
for (;;) {
|
||||
// Waits for a signal to the semaphore associated with the calling thread.
|
||||
|
||||
@@ -82,7 +82,8 @@ extern "C" {
|
||||
|
||||
// Length of Characteristic 5 in bytes
|
||||
#define SIMPLEPROFILE_CHAR1_LEN 2
|
||||
#define SIMPLEPROFILE_CHAR2_LEN 50
|
||||
//#define SIMPLEPROFILE_CHAR2_LEN 50
|
||||
#define SIMPLEPROFILE_CHAR2_LEN 34
|
||||
#define SIMPLEPROFILE_CHAR3_LEN 20
|
||||
#define SIMPLEPROFILE_CHAR4_LEN 200
|
||||
//#define SIMPLEPROFILE_CHAR4_LEN 20
|
||||
|
||||
Reference in New Issue
Block a user