 yichin
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3d7c0be8f3
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data rate test
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2019-11-25 19:12:28 +08:00 |
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yichin
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5283d905b7
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debug channel swap
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2019-10-04 16:11:23 +08:00 |
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yichin
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1d33c05ca3
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debug neulive1.3
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2019-09-27 13:39:35 +08:00 |
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YiChin2018
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ce61501d43
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interrupt with bugs
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2019-08-22 19:11:34 +08:00 |
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YiChin2018
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f699ecdae9
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format
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2019-08-20 13:27:47 +08:00 |
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YiChin2018
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72ecd7e39f
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temporary test timestamp
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2019-07-31 18:39:42 +08:00 |
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YiChin2018
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00e35e4042
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temporary test timestamp
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2019-07-31 14:04:27 +08:00 |
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YiChin2018
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1d3d8e0836
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trigger mode complete and need more tests
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2019-07-30 19:18:01 +08:00 |
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YiChin2018
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db61e6b3ad
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modify firmware structure and add trigger mode
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2019-07-30 18:10:25 +08:00 |
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YiChin2018
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b5d76a99b2
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stimulation begin to test
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2019-07-25 18:57:06 +08:00 |
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YiChin2018
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0d8f2fe522
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channel information done
channel table modify
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2019-07-19 16:23:44 +08:00 |
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YiChin2018
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7647186154
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default and self-define instruction can operate equivalently
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2019-07-15 19:13:11 +08:00 |
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YiChin2018
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71a5e874f7
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data arrange bug
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2019-06-25 16:36:28 +08:00 |
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|
Ta-Shun Su
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5103ad1d5c
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add instruction eval
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2019-05-24 12:29:49 +08:00 |
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