 yichin
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3cb98ed6bb
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Merge remote-tracking branch 'origin/neulive/development' into neulive/development
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2020-01-02 11:23:30 +08:00 |
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weiting2
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e9c8175e91
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check LSK to decide restart or not
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2020-01-02 11:12:40 +08:00 |
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yichin
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1347d89577
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Merge remote-tracking branch 'origin/neulive/development' into neulive/development
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2019-12-31 13:46:55 +08:00 |
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weiting2
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6e2a275f31
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send recording para only
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2019-12-31 13:44:42 +08:00 |
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yichin
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f869c1ae3c
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Merge remote-tracking branch 'origin/neulive/development' into neulive/development
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2019-12-31 11:50:31 +08:00 |
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weiting2
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6e9d4685fc
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go to config done directly
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2019-12-31 11:49:37 +08:00 |
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yichin
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cc55716b6e
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Merge remote-tracking branch 'origin/neulive/development' into neulive/development
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2019-12-31 11:44:09 +08:00 |
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weiting2
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7a469c3231
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go to config done directly
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2019-12-31 11:42:18 +08:00 |
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yichin
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f6400ee6c6
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change ADC level timeOK
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2019-12-31 11:28:35 +08:00 |
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weiting2
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7dd490adc1
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go to config done directly
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2019-12-31 11:25:10 +08:00 |
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weiting2
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224c2494c0
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2650 send recording (amp) parameter only
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2019-12-31 10:41:44 +08:00 |
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weiting2
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eff7e84dd7
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2650 send recording (amp) parameter only
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2019-12-30 11:07:37 +08:00 |
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weiting2
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c159b8b0d6
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Merge remote-tracking branch 'origin/neulive/development' into neulive/development
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2019-12-27 18:43:33 +08:00 |
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weiting2
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7918644b08
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DBS using VIS break "start" instruction
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2019-12-27 18:43:20 +08:00 |
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|
YiChin
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5a2b9a0061
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error fix
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2019-12-27 18:40:51 +08:00 |
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|
YiChin
|
3292c9bcec
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error fix
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2019-12-27 18:39:09 +08:00 |
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weiting2
|
3effed2d65
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DBS using VIS break "start" instruction
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2019-12-27 18:37:11 +08:00 |
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weiting2
|
f2d07eea76
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DBS using VIS break "start" instruction
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2019-12-27 16:42:29 +08:00 |
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weiting2
|
0005e654c1
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DBS interrupt & restart testing
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2019-12-27 12:38:28 +08:00 |
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weiting2
|
7a7f848930
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DBS interrupt & restart testing
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2019-12-27 12:28:13 +08:00 |
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weiting2
|
e4e08ffbdc
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DBS interrupt & restart testing
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2019-12-27 12:27:43 +08:00 |
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weiting2
|
8774bad1b1
|
DBS interrupt & restart testing
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2019-12-27 11:47:29 +08:00 |
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weiting2
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618e3ad01a
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DBS interrupt & restart testing
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2019-12-27 10:33:59 +08:00 |
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weiting2
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8ed8201c0c
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VIS_FUH call DBS interrupt
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2019-12-26 15:10:07 +08:00 |
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|
YiChin
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c8f6ec239d
|
error fix
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2019-12-26 14:45:17 +08:00 |
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weiting2
|
4930e8845b
|
VIS_FUH call DBS interrupt
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2019-12-26 14:38:51 +08:00 |
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|
YiChin
|
5549d07208
|
error fix
|
2019-12-26 11:57:01 +08:00 |
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weiting2
|
9380ecacec
|
VIS_FUH call DBS interrupt
|
2019-12-26 11:51:52 +08:00 |
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|
weiting2
|
e4a25a6225
|
DBS interrupt => back to configure => check if MUX configure correctly
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2019-12-26 11:01:02 +08:00 |
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|
weiting2
|
338b21fd65
|
read LSK directly to check restart issue
|
2019-12-25 17:16:15 +08:00 |
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|
weiting2
|
b5762c0f65
|
FlushSPIrx(); make sure lsk pass check correct
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2019-12-25 16:52:18 +08:00 |
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|
weiting2
|
5799223d69
|
check configure instruction work well
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2019-12-25 15:15:46 +08:00 |
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weiting2
|
e72463b60a
|
check configure instruction work well
|
2019-12-25 15:06:53 +08:00 |
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weiting2
|
634f2fbd47
|
check configure instruction work well
|
2019-12-25 15:05:00 +08:00 |
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|
weiting2
|
9aa508c6cf
|
check configure instruction work well
|
2019-12-25 14:37:54 +08:00 |
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|
weiting2
|
65a380cbca
|
check configure instruction work well
|
2019-12-25 11:52:46 +08:00 |
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|
weiting2
|
f1eb0dd727
|
check configure instruction work well
|
2019-12-25 11:19:21 +08:00 |
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weiting2
|
a190f3212e
|
add debug state in lsk; check every MISO SPI
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2019-12-25 10:24:56 +08:00 |
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|
weiting2
|
c5e55c4e96
|
add debug state in lsk; check every MISO SPI
|
2019-12-24 15:39:15 +08:00 |
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|
weiting2
|
2a321cbd0e
|
start PWM after turn on; add debug state in lsk
|
2019-12-24 15:23:47 +08:00 |
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|
weiting2
|
468e4c491a
|
test PWM (system clk)
|
2019-12-23 17:04:12 +08:00 |
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|
weiting2
|
828f96c96c
|
test PWM (system clk)
|
2019-12-23 16:49:35 +08:00 |
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|
yichin
|
6bb6678e07
|
add documentation
|
2019-12-03 20:08:51 +08:00 |
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|
yichin
|
21cae3841d
|
data rate test modified
|
2019-11-27 18:41:57 +08:00 |
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|
yichin
|
332f134542
|
data rate test
|
2019-11-26 20:02:09 +08:00 |
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|
yichin
|
3d7c0be8f3
|
data rate test
|
2019-11-25 19:12:28 +08:00 |
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|
yichin
|
3a80c00cc5
|
data rate test for memory board
|
2019-11-14 18:16:15 +08:00 |
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|
yichin
|
4811d4fb7b
|
data rate test for memory board
|
2019-11-14 15:23:17 +08:00 |
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|
yichin
|
866c569afb
|
data rate test for memory board
|
2019-11-13 20:24:26 +08:00 |
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|
yichin
|
c02f13773a
|
modify data rate
|
2019-11-13 14:02:57 +08:00 |
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