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Merge remote-tracking branch 'origin/Elite_1.5_Taylor_061721' into Elite_1.5_Taylor_061721

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# Conflicts:
#	simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h
#	simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h
#	simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteSPI.h
This commit is contained in:
Taylor Liao
2021-07-28 22:46:09 +08:00
parent 53305aaec5 9130c9edc2
commit d379f0b5f7
13 changed files with 301 additions and 48 deletions
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/app/.launches/simple_peripheral_cc2650em_app.launch
+4
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@@ -2,16 +2,20 @@
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simplelink/ble_sdk_2_02_02_25/examples/cc2650em/simple_peripheral/ccs/config/src/sysbios/rom_sysbios.aem3
BIN
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simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h
+72 -7
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@@ -162,6 +162,25 @@ static void VinADCGainCtrl(uint8_t VinADCLevel){
record_flag = false;
}
static void HSTIAGainCtrl(uint8_t HSTIALevel) {
/* HSRTIACON[12:5] = CTIACON, fix at 16pF;
HSRTIACON[4] = TIASW6CON, diode in parallel with RTIA;
HSRTIACON[3:0] = RTIA */
uint32_t reg = 0;
if (HSTIALevel <= RTIAopen) {
reg = (uint32_t)(HSTIALevel) & 0x0000000F;
reg = reg & 0x0000011F;
} else {
reg = 0x0000011F;
}
select_REG(HSRTIACON);
w32_REG(reg);
record_flag = false;
}
static void ADCChannelSelect(uint8_t ADCChannel){
// set ADC parameter
// 0xC1~F1 = reading AIN0~AIN3. Using FSR+-6V, resolution = 187.5uV
@@ -236,20 +255,25 @@ static void ReadADCBat(uint8_t *buf){
ADC_read(buf);
}
static int32_t ReadRawADC() {
select_REG(ADCDAT);
return r32_REG();
}
static int32_t ReadRealZ() {
select_REG(0x2078);
select_REG(DFTREAL);
return r32_REG();
}
static int32_t ReadImagZ() {
select_REG(0x207c);
select_REG(DFTIMAG);
return r32_REG();
}
static uint32_t ReadFreq() {
static uint64_t freqDAC;
static uint32_t ret;
select_REG(0x2030);
select_REG(WGFCW);
freqDAC = r32_REG();
ret = freqDAC * 16000000 / 1073741824; //freeDAC * 16M / 2^30
@@ -294,10 +318,10 @@ static int32_t ADCCode2Volt(uint32_t code) {
/* for Elite EIS */
//RTIA Values
#define RTIA02 0 //Max 3mA
#define RTIA4 1 //Max 220uA
#define RTIA12 2 //Max 74uA
#define RTIA512 5 //Max 1.76uA
#define RTIA200R 0 //Max 3mA
#define RTIA4K 1 //Max 220uA
#define RTIA12K 2 //Max 74uA
#define RTIA512K 5 //Max 1.76uA
//AVERAGE NUMBER
#define AVG2 0
@@ -598,6 +622,47 @@ static void AutoGainChangeVin(int32_t RealVin){
}
}
static void HSTIA_cali_config() {
if(init_EIS_CaliMode) {
select_REG(AFECON);
w32_REG(0x0031CFC0);
PowerMode_CutoffFrequencyControl(cutoff_auto, HIGH_PW_MODE);
select_REG(0x0414); //CLKSEL
w32_REG(0x00000000); //ADC and system clock both internal high frequency oscillator clock
select_REG(0x0408); //16bit system clock divider
w16_REG(0x0442); //set divider = 2
select_REG(0x20BC); //HSOSCCON
w32_REG(0x00000000); //switch to 32MHz output
select_REG(ADCCON);
w32_REG(0x00000101);
select_REG(HSTIACON);
w32_REG(0x00000001);
select_REG(ADCFILTERCON);
w32_REG(0x000000D0);
select_REG(DFTCON);
w32_REG(0x000000C1);
// select_REG(SWCON);
// w32_REG(0x00008A11);
select_REG(0x200C); //SWCON
w32_REG(0x00010000); //Control individually
select_REG(0x2150); //DSWFULLCON
w32_REG(0x00000010); //D5: D to CE0
select_REG(0x2143); //NSWFULLCON
w32_REG(0x00000010); //N5: N to Rload_SE0
select_REG(0x2158); //PSWFULLCON
w32_REG(0x00002000); //P11: P to CE0
select_REG(0x215C); //TSWFULLCON
w32_REG(0x00000110); //T9 | T5: HSTIA neg input to SE0
init_EIS_CaliMode = false;
}
}
//EIS Function//
static void writeRTIA(uint8_t ret){ //ret = 0, 1, 2, 3, 4, 5
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h
+96 -10
View File
@@ -58,16 +58,7 @@ static uint16_t DAC_outputV(uint16_t voltLV) {
#endif
#ifdef ELITE_VERSION_EIS
static uint32_t DAC_outputV(uint32_t voltLV) {
//voltLV consists of 0x00000FFF --- Vbias | 0x0003F000 --- Vzero
select_REG(0x2120);
w32_REG(voltLV);
return voltLV;
}
static uint32_t DAC_outputF(uint32_t freq) {
static uint32_t DAC_outputV(uint32_t freq) {
select_REG(0x2030);
w32_REG(freq);
@@ -152,4 +143,99 @@ static void SetWGAmp(uint16_t ampcode){
w32_REG(0x00000004); //0x4: Sinusoid
}
static void AD_HSDAC_GainControl(uint8_t G_EXA_PGA, uint8_t DACRate) {
/* Set the Gain value of PGA and Excitation amp */
uint32_t reg = 0;
// uint8_t DACUpdateRate = DACRate;
uint8_t DACUpdateRate = 0x07;
switch (G_EXA_PGA) {
case 0x00:{
reg = 0x00000000;
break;
}
case 0x01:{
reg = 0x00000001;
break;
}
case 0x10:{
reg = 0x00001000;
break;
}
case 0x11:{
reg = 0x00001001;
break;
}
default:{
reg = 0x0000000E; // Default update rate = 7
break;
}
}
reg = reg | ((uint32_t)(DACUpdateRate) << 1);
select_REG(HSDACCON); // HSDACCON address
w32_REG(reg);
}
static void HSDAC_output(uint16_t amp) {
/* Set and write the amplitude of HSDAC. Full scale: 0x0200 ~ 0x0E00, 0x0800 = 0V */
/* Set and write the amplitude of HSDAC. Full scale: 512 ~ 3584, 2048 = 0V */
uint32_t amplitude = 0;
if (amp > 0x0E00) {
amplitude = 0x00000E00;
} else if (amp < 0x0200) {
amplitude = 0x00000200;
} else {
amplitude = (uint32_t) (amp & 0x0FFF);
}
select_REG(HSDACDAT); // HSDACDAT address
w32_REG(amplitude);
}
static void PowerMode_CutoffFrequencyControl (uint8_t bandwidth, uint8_t PowerMode) {
uint32_t reg = 0;
switch (bandwidth) {
case cutoff_auto :{
reg = (((uint32_t)(cutoff_auto)) & 0x0000000F) << 2;
break;
}
case cutoff_50k :{
reg = (((uint32_t)(cutoff_50k)) & 0x0000000F) << 2;
break;
}
case cutoff_100k :{
reg = (((uint32_t)(cutoff_100k)) & 0x0000000F) << 2;
break;
}
case cutoff_250k :{
reg = (((uint32_t)(cutoff_250k)) & 0x0000000F) << 2;
break;
}
default :{
reg = (((uint32_t)(cutoff_auto)) & 0x0000000F) << 2;
break;
}
}
switch (PowerMode) {
case LOW_PW_MODE :{
reg = reg | ((uint32_t)(LOW_PW_MODE) & 0x00000000F);
break;
}
case HIGH_PW_MODE :{
reg = reg | ((uint32_t)(HIGH_PW_MODE) & 0x00000000F);
break;
}
default :{
break;
}
}
select_REG(PMWB);
w32_REG(reg);
}
#endif
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteInstruction.h
+34 -1
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@@ -82,6 +82,16 @@ struct HEADSTAGE_INSTRUCTION {
uint8_t AdcChannel;
/* EIS HSDAC parameter */
uint8_t EXA_gain; // Excitation Amplifier
uint8_t PGA_gain; // Programmable Gain Amplifier
uint16_t VAmpSet; // DAC Voltage Amplitude
uint8_t HSDAC_UpRate; // DAC Update Rate
/* EIS HSTIA parameter */
uint8_t TIAGainLv;
uint8_t EISAutoGainEnable;
} instru = {0};
/** Iin, Vin, Vout **/
@@ -89,7 +99,8 @@ struct HEADSTAGE_INSTRUCTION {
#define VIN_ADC 0x01
#define VOUT_DAC 0x02
#define HIGH_Z 0x03
#define VOUT_VIN_ADC 0x04
#define EIS_HSDAC 0x04
#define EIS_HSTIA 0x05
/** ADC Iin gain level **/
#define I_GAIN_3M 0x07 // largest gain
@@ -117,12 +128,24 @@ struct HEADSTAGE_INSTRUCTION {
/* DAC reset parameter */
#define DAC_ZERO 25000
#define EIS_HSDAC_ZERO 0x0800
// Step time macro
#define STEPTIME_HALF_SEC 5000
#define STEPTIME_ONE_SEC 10000
#define STEPTIME_TWO_SEC 20000
/* HSTIA gain level (feedback R value) */
#define RTIA0 0x00 // 200R
#define RTIA1 0x01 // 1k
#define RTIA2 0x02 // 5k
#define RTIA3 0x03 // 10k
#define RTIA4 0x04 // 20k
#define RTIA5 0x05 // 40k
#define RTIA6 0x06 // 80k
#define RTIA7 0x07 // 160k
#define RTIAopen 0x08 // RTIA is open
#define RTIA_GAIN_AUTO 0xFF
/*********************************************************************
* @fn InitEliteInstruction
*
@@ -195,6 +218,16 @@ static void InitEliteInstruction(){
instru.sti_v7 = DAC_ZERO;
instru.sti_loop = 1;
instru.sti_cy = 0;
// EIS DAC
instru.EXA_gain = 0;
instru.PGA_gain = 0;
instru.VAmpSet = EIS_HSDAC_ZERO;
instru.HSDAC_UpRate = 7;
// EIS ADC
instru.TIAGainLv = 0;
instru.EISAutoGainEnable = 1;
}
#ifdef __cpulsplus
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteLED.h
+4
View File
@@ -178,6 +178,10 @@ static void WorkModeLED()
Elite_led_color(COLOR_ORANGE);
} else if (instru.AdcChannel == VOUT_DAC) {
Elite_led_color(COLOR_BLUE);
}else if (instru.AdcChannel == EIS_HSDAC) {
Elite_led_color(COLOR_PURPLE_DARK);
} else if (instru.AdcChannel == EIS_HSTIA) {
Elite_led_color(COLOR_GREEN_DARK);
}
break;
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteReset.h
+4
View File
@@ -13,6 +13,8 @@ static void reset() {
initINSBuf();
initDATBuf();
AD5940_init();
// PIN_setOutputValue(pin_handle, HIGH_Z_MODE, 0); // HIGH Z MODE // 1: close; 0: open;
// VinADCGainCtrl(VIN_GAIN_AUTO);
@@ -21,6 +23,7 @@ static void reset() {
// instru.VoutGainLevel = VOUT_GAIN_15K;
// VoutGainControl(instru.VoutGainLevel);
// DAC_outputV(Usercode_Correction_to_DAC(instru.VoutGainLevel, 25000));
HSDAC_output(0x0800);
for (int i = 0; i < SPI_LED_SIZE; i++) {
spi_LEDtxbuf[i] = 0;
@@ -60,6 +63,7 @@ static void Eliteinterrupt() {
// instru.VoutGainLevel = VOUT_GAIN_15K;
// VoutGainControl(instru.VoutGainLevel);
// DAC_outputV(Usercode_Correction_to_DAC(instru.VoutGainLevel, 25000));
HSDAC_output(0x0800);
for (int i = 0; i < SPI_LED_SIZE; i++) {
spi_LEDtxbuf[i] = 0;
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteSPI.h
+6 -9
View File
@@ -179,11 +179,15 @@ static void CAL_LED_SPI(uint8_t length, uint16_t *spi_txbuf, uint16_t *spi_rxbuf
#define ADCCON 0x21A8
#define DFTCON 0x20D0
#define ADCFILTERCON 0x2044
#define PWMB 0x22F0
#define PMWB 0x22F0
#define CLKSEL 0x0414
#define CLKCON0 0x0408
#define HSOSCCON 0x20BC
#define ADCBUFCON 0x238C
#define HSRTIACON 0x20F0
#define ADCDAT 0x2074
#define DFTREAL 0x2078
#define DFTIMAG 0x207C
static void select_REG(uint16_t addr){
@@ -316,19 +320,12 @@ static void rfifo_REG() {
}
*/
static void AD5940_SWReset(){
static void AD5940_sftreset(){
select_REG(0x0424);
w16_REG(0xA158);
CPUdelay(200);
}
//static void AD5940_HWReset(){
// PIN_setOutputValue(pin_handle, AD_reset, 0);
// CPUdelay(10);
// PIN_setOutputValue(pin_handle, AD_reset, 1);
// CPUdelay(10);
//}
static void AD5940_init(){
PIN_setOutputValue(pin_handle, AD_reset, 0);
PIN_setOutputValue(pin_handle, AD_reset, 1);
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite_def.h
+17 -3
View File
@@ -39,11 +39,14 @@ enum all_mode_e {
CURVE_EIS_CV = 0xD2,
CURVE_CALI_DAC = 0xF0, //0x93,
CURVE_CALI_ADC = 0xF1, // Cali ADC - test //0x92,
// CURVE_CALI_ADC = 0xF1, // Cali ADC - test //0x92,
CURVE_CALI_ADC = 0x92, // Cali ADC - test //0x92,
SET_SAMPLE_RATE = 0xE0, //0x70,
SET_ADC_DAC_GAIN = 0xE1, //0x80,
// SET_SAMPLE_RATE = 0xE0, //0x70,
SET_SAMPLE_RATE = 0x70, //0x70,
// SET_ADC_DAC_GAIN = 0xE1, //0x80,
SET_ADC_DAC_GAIN = 0x80, //0x80,
};
// CIS (control instruction)
@@ -115,5 +118,16 @@ enum all_mode_e {
#define WORKING 0x04
#define POST_WORK 0x05
/* EIS define */
// cutoff frequency of the filter in AD5940
#define cutoff_auto 0x00
#define cutoff_50k 0x01
#define cutoff_100k 0x02
#define cutoff_250k 0x03
#define LOW_PW_MODE 0x00
#define HIGH_PW_MODE 0x01
#define VALUE_ZERO_TO_ONE(_v) (_v == 0) ? 1 : _v
#endif
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite_mode_ADC_DAC.h
+9 -13
View File
@@ -734,21 +734,17 @@ static void cali_IT_plot(void) {
* 2 - read Iin and reset ADC_cnt
*/
if (ADC_cnt == 0) {
if (instru.AutoGainEnable) {
if (instru.EISAutoGainEnable) {
MEAS_CURR(wm) = 0xFFFF;
} else {
ReadADCIin(spi_ADC_rxbuf);
MEAS_CURR(wm) = (int32_t) (spi_ADC_rxbuf[0] << 8) | (int32_t) (spi_ADC_rxbuf[1]);
if (lastIinADCGainLevel != instru.ADCGainLv) {
IinADCGainControl(instru.ADCGainLv);
}
MEAS_CURR(wm) = ReadRawADC();
}
if (instru.ADCGainLv == 0) {
cali_count_max = 5000;
} else {
cali_count_max = 1000;
}
// if (instru.TIAGainLv == 0) {
// cali_count_max = 5000;
// } else {
// cali_count_max = 1000;
// }
if (record_flag == false) {
rec_cnt++;
@@ -790,14 +786,14 @@ static void cali_IT_plot(void) {
}
if (ADC_cnt == 1) {
ReadADCIin(spi_ADC_rxbuf);
ReadRawADC();
ADC_cnt++;
return;
}
if (ADC_cnt == 2) {
ReadADCIin(spi_ADC_rxbuf);
ReadRawADC();
ADC_cnt = 0;
return;
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h
+47 -4
View File
@@ -598,6 +598,7 @@ static void EliteADCBattery();
static void VinADCGainCtrl(uint8_t VinADCLevel);
static void VoutGainControl(uint8_t VOUTLevel);
static void PIN15_setOutputValue (uint32_t latch_num, uint32_t pin_num, bool highlow);
static bool init_EIS_CaliMode = false;
// Elite key detection & turn on/ shutdown function (peripheral hardware control)
static void Elite_led_color(uint16_t color);
@@ -623,6 +624,7 @@ static void volt_out();
static void freq_out();
static void vscan_volt_out(void);
static void pulse_vscan(void);
static void PowerMode_CutoffFrequencyControl (uint8_t bandwidth, uint8_t PowerMode);
//mode (notify)
static void initDATBuf();
@@ -1050,7 +1052,7 @@ static void update_ZM_instruction(uint8 *ins) {
}
break;
}
case VOUT_DAC : {
case EIS_HSDAC : {
// instru.VoutGainLevel = ins[4];
// if(instru.VoutGainLevel == VOUT_GAIN_AUTO){
// instru.VoutGainLevel = VOUT_GAIN_15K;
@@ -1075,6 +1077,28 @@ static void update_ZM_instruction(uint8 *ins) {
}
break;
}
case VOUT_DAC : {
instru.EXA_gain = ((ins[4] & 0xF0) >> 4);
instru.PGA_gain = (ins[4] & 0x0F);
// instru.HSDAC_UpRate = ins[5];
instru.HSDAC_UpRate = 0x07;
static uint8_t E_P_gain = 0;
E_P_gain = (instru.EXA_gain << 4) | (instru.PGA_gain);
AD_HSDAC_GainControl(E_P_gain, instru.HSDAC_UpRate);
break;
}
case EIS_HSTIA : {
instru.TIAGainLv = ins[4];
if (instru.TIAGainLv != RTIA_GAIN_AUTO) {
instru.EISAutoGainEnable = 0;
} else {
instru.EISAutoGainEnable = 1;
instru.TIAGainLv = RTIA0;
HSTIAGainCtrl(instru.TIAGainLv);
}
break;
}
default :{
break;
}
@@ -1111,7 +1135,7 @@ static void update_ZM_instruction(uint8 *ins) {
ModeLED(WORKING);
break;
}
case VOUT_DAC : { // 0x02
case EIS_HSDAC : { // 0x02
instru.eliteFxn = CURVE_CALI_ADC;
instru.AdcChannel = VOUT_DAC;
instru.notifyRate = 1000;
@@ -1123,6 +1147,25 @@ static void update_ZM_instruction(uint8 *ins) {
ModeLED(WORKING);
break;
}
case VOUT_DAC :{ // 0x04
instru.eliteFxn = CURVE_CALI_ADC;
instru.AdcChannel = EIS_HSDAC;
instru.notifyRate = 1000;
instru.sampleRate = 15;
instru.VAmpSet = ((uint16_t)(ins[4]) << 8) | (uint16_t)(ins[5]);
init_EIS_CaliMode = true;
// HSDAC_output(instru.VAmpSet);
ModeLED(WORKING);
break;
}
case EIS_HSTIA :{ // 0x05
instru.eliteFxn = CURVE_CALI_ADC;
instru.AdcChannel = EIS_HSTIA;
instru.notifyRate = 1000;
instru.sampleRate = 15;
break;
}
default : {
break;
}
@@ -1319,7 +1362,7 @@ static void update_ZM_instruction(uint8 *ins) {
w32_REG(0x0030CFC0);
//HIGH POWER MODE
select_REG(0x22F0); //PWMB
select_REG(0x22F0); //PMWB
w32_REG(0x0000000D); //switch to active high power mode
select_REG(0x0408); //16bit system clock divider
w16_REG(0x0442); //set divider = 2
@@ -1374,7 +1417,7 @@ static void update_ZM_instruction(uint8 *ins) {
select_REG(0x20D0); //DFTCON
w32_REG(0x001000C1); //sinc3 + average input for DFT | dftnum max
//AFE and PWMB
//AFE and PMWB
select_REG(0x2000); //AFECON
w32_REG(0x00098780); //ADC on //0b10011000011110000000
select_REG(0x22F0); //PWMB
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/impedance_meter.h
+7 -1
View File
@@ -366,7 +366,7 @@ static void SimpleBLEPeripheral_performPeriodicTask(void) {
mode_done();
}
else if (instru.eliteFxn == CURVE_CALI_DAC) {
DAC_outputV(instru.VoltConstant); //UserCode -> DAC code -> DAC out
// DAC_outputV(instru.VoltConstant); //UserCode -> DAC code -> DAC out
wm_deinit();
PeriodicEvent = false;
} else {
@@ -472,6 +472,12 @@ static void EliteADCControl(void) //CURVE_IV => CC_Plot() | CURVE_CV => Iin_Vin_
cali_VT_plot();
} else if (instru.AdcChannel == VOUT_DAC) {
cali_VT_plot();
} else if (instru.AdcChannel == EIS_HSDAC) {
HSTIA_cali_config();
HSDAC_output(instru.VAmpSet);
} else if (instru.AdcChannel == EIS_HSTIA) {
HSTIA_cali_config();
cali_IT_plot();
}
break;
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/simple_peripheral.c
+1
View File
@@ -631,6 +631,7 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
}
} else {
EliteOn = TurnOnElite(key);
// AD5940_init();
}
}
else { // if there is periodic event