 pchang718
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8caa8918d0
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feat: implement dynamic time-domain LOD zoom, locked axis multipliers, and clean 4-column CSV export
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2026-05-26 14:48:04 +08:00 |
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pchang718
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0140b0495c
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feat: 優化時域圖表X軸顯示時間單位，並新增步階訊號測試腳本
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2026-05-22 14:18:48 +08:00 |
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pchang718
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9182220c1d
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feat: implement multi-stage cascaded biquad filters support
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2026-05-21 22:35:24 +08:00 |
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pchang718
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c259f91380
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docs: update PROJECT_STATUS.md with second-phase refactoring details
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2026-05-17 14:23:51 +08:00 |
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pchang718
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e9dba45626
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chore: update branch name in project status
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2026-05-17 01:00:46 +08:00 |
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pchang718
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3c3bda7daa
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feat: complete fixed-point Rounding simulation, fix Vite proxy, and update documentation
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2026-05-17 00:58:19 +08:00 |
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pchang718
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9b504b3f8f
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Update project status with GitLab push info
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2026-05-15 17:47:23 +08:00 |
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pchang718
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8fb2a160af
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Optimize DSP interface: stacked r/delta, fixed r-drift, locked phase, and linked axes
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2026-05-15 17:45:45 +08:00 |
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