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20 Commits

Author SHA1 Message Date
Roy 51e447db3b test 1 to 8 2021-11-01 09:54:00 +08:00
Roy 80ea8a6772 r/w twice 2021-10-25 10:33:27 +08:00
Roy 08c2de8c43 debug 1 to 8 2021-10-05 16:17:48 +08:00
Roy db47c14537 set limit of writing Ram 5 times 2021-10-01 10:09:29 +08:00
Roy fc811cef35 read and write Ram twice 2021-09-27 19:12:20 +08:00
Roy eda0943fd3 spi speed 8M 2021-09-27 17:17:02 +08:00
Roy ee203f45fd use check buf 2021-09-27 14:22:45 +08:00
Roy de4ede4187 use check buf 2021-09-24 17:59:35 +08:00
Roy b5baead500 delay 10us after change mem_select 2021-09-23 11:34:12 +08:00
Roy f9c7d04647 send data and read data(spi) 2021-09-23 10:33:59 +08:00
Roy e430cd41fc send data and read data(spi) 2021-09-23 10:31:42 +08:00
Roy 8f3f44bc40 test memory board 2021-09-14 14:32:05 +08:00
Roy 3142f007b1 test memory board 2021-09-14 12:24:02 +08:00
Roy a1eb286365 look Ram data(spi) 2021-08-25 14:45:07 +08:00
Roy 7369ea8430 test 2021-08-19 17:14:09 +08:00
Roy 1540745ce5 test pin 2021-08-19 12:47:38 +08:00
Roy 9fd06428c3 check ram data 2021-08-17 13:40:32 +08:00
Roy 24b0889532 check ram data 2021-08-13 13:10:37 +08:00
Roy 853151a83a check ram data 2021-08-13 10:30:13 +08:00
Roy e51def4f9f check ram data 2021-08-12 14:33:25 +08:00
@@ -13,7 +13,7 @@
=======================*/
#define MEM_BUFFER_SIZE SPI_TX_BUFFER_SIZE
#define MEM_SWITCH_THRESHOLD 7000 //max:7K bytes
#define MEM_SWITCH_THRESHOLD 0xBB8 //max:3K bytes
#define MSM_REG_WRITE 0x01
#define MEM_INS_WRITE 0x02
@@ -71,22 +71,14 @@ void master_switch_memory();
//static void central_handle_notify(uint8_t notify_length, uint8_t *notify_value){
#define RAM_INS_LEN 3
#define RAM_RED_HEADER_LEN 3
#define RAM_RED_TAILER_LEN 8
#define ELITE_NOTIFY_LEN 120
#define RAM_RED_CTX_LEN (RAM_INS_LEN + RAM_RED_HEADER_LEN + RAM_RED_TAILER_LEN + ELITE_NOTIFY_LEN)
uint8_t spi_buffer0[256];
uint8_t spi_buffer1[256];
uint8_t recv_ins[RAM_RED_CTX_LEN] = {0};
uint8_t recv_ins[26] = {0};
static uint8_t green_wrong = 0;
static uint8_t green_retry_cnt = 0;
static void central_handle_notify()
{
static uint8_t check_buffer[RAM_RED_CTX_LEN] = {0};
static uint8_t tailer[RAM_RED_TAILER_LEN] = {0};
static void central_handle_notify(){
static uint8_t check_buffer[29] = {0};
static uint8_t spi_buffer_index = 0;
static uint8_t wrong = 0;
static uint8_t retry_cnt = 0;
@@ -98,10 +90,11 @@ static void central_handle_notify()
uint8_t counter;
// localize current buffer
if (spi_buffer_index) {
if(spi_buffer_index){
spi_buffer_index = ~spi_buffer_index;
p = spi_buffer0;
} else {
}
else{
spi_buffer_index = ~spi_buffer_index;
p = spi_buffer1;
}
@@ -111,7 +104,7 @@ static void central_handle_notify()
// update offset
uint32_t cnt_offset = not_offset;
not_offset = cnt_offset + RAM_RED_HEADER_LEN + notify_length + RAM_RED_TAILER_LEN;
not_offset = cnt_offset + 3 + notify_length;
p[0] = MEM_INS_WRITE; // instruction
p[1] = (uint8_t)((cnt_offset >> 8) & 0xFF); // address
@@ -119,19 +112,10 @@ static void central_handle_notify()
p[3] = 0xFF; // data header
p[4] = counter; // data counter
p[5] = notify_length; // data content length
memcpy(p + 6, notify_value, notify_length); // data content
tailer[0] = wrong;
tailer[1] = retry_cnt;
tailer[2] = green_wrong;
tailer[3] = green_retry_cnt;
tailer[4] = mem_sel & 0x01;
tailer[5] = 0xFF;
tailer[6] = counter;
tailer[7] = notify_length;
memcpy(p + 6 + notify_length, tailer, RAM_RED_TAILER_LEN); // tailer content
central_spi_send(p, RAM_RED_CTX_LEN);
central_spi_send(p, notify_length + 6);
// read RAM
recv_ins[0] = 0x03; //read RAM
@@ -142,7 +126,7 @@ static void central_handle_notify()
while (1) {
// compare data
for (i=3; i<RAM_RED_CTX_LEN; i++) {
for (i=3; i<26; i++) {
if (p[i]!=check_buffer[i]) {
write_again = true;
break;
@@ -155,7 +139,7 @@ static void central_handle_notify()
write_limit++;
//write RAM
central_spi_send(p, RAM_RED_CTX_LEN);
central_spi_send(p, notify_length + 6);
// read RAM
recv_ins[0] = 0x03; //read RAM
@@ -167,13 +151,13 @@ static void central_handle_notify()
break;
}
if (write_limit >= 2) {
if (write_limit >= 1) {
break;
}
}
for (i=3; i<RAM_RED_CTX_LEN; i++) {
if (p[i] != check_buffer[i]) {
for (i=3; i<26; i++) {
if (p[i]!=check_buffer[i]) {
wrong_flag = true;
break;
}
@@ -183,7 +167,7 @@ static void central_handle_notify()
wrong++;
}
memset(p, 0, RAM_RED_CTX_LEN);
memset(p,0,notify_length + 6);
notify_handle_done = true;
@@ -197,8 +181,7 @@ static void central_handle_notify()
}
}
void master_switch_memory()
{
void master_switch_memory() {
uint16_t cnt_offset = not_offset;
not_offset = MEM_META_LENGTH;
static uint8_t check_green_buffer[10] = {0};
@@ -231,7 +214,7 @@ void master_switch_memory()
while (1) {
// compare data
for (i=3; i<7; i++) {
if (p[i] != check_green_buffer[i]) {
if (p[i]!=check_green_buffer[i]) {
write_again = true;
break;
}
@@ -255,13 +238,13 @@ void master_switch_memory()
break;
}
if (write_limit >= 2) {
if (write_limit >= 1) {
break;
}
}
for (i=3; i<7; i++) {
if (p[i] != check_green_buffer[i]) {
if (p[i]!=check_green_buffer[i]) {
wrong_flag = true;
break;
}
@@ -271,7 +254,7 @@ void master_switch_memory()
green_wrong++;
}
memset(p, 0, 7);
memset(p,0,7);
// switch memory
mem_sel++;