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10 Commits

Author SHA1 Message Date
weiting2 226f38bbba RIS REC with purple led 2020-08-03 17:43:09 +08:00
weiting2 f4861bb6cb CIS version with purple led 2020-08-03 14:04:40 +08:00
weiting2 c29273f7e6 using real data format 2020-07-31 10:39:40 +08:00
weiting2 f3391fe63b 4k with data process 2020-07-22 10:16:01 +08:00
weiting2 332e8a127f 8k SR without data process or 4k with data process 2020-07-21 16:25:36 +08:00
weiting2 ab83ab2ce0 8k SR without data process or 4k with data process 2020-07-21 16:13:09 +08:00
weiting2 498a3aceb6 modify get_date script for linux version CCS 2020-07-20 17:50:32 +08:00
weiting2 41c6cb2964 testing data rate 2020-07-20 16:53:32 +08:00
weiting2 33c3db2601 linux version CCS. test central 2020-07-17 17:43:35 +08:00
weiting2 60c885a625 linux version CCS. test central 2020-07-17 17:34:00 +08:00
17 changed files with 390 additions and 1121 deletions
+3 -3
View File
@@ -8,7 +8,7 @@ no device y=ax+b MAC a+ b+ a- b- avg
7 c652 c652 18:04:ED:37:C6:52 2024 -7687 2086 -11283 4.88850143182858
8 c5ed c5ed 18:04:ED:37:C5:ED 2231 -1711 2353 -70845 4.45265043545859
9 9bef 9bef 0081F9E49BEF 2383 -8585 2415 -20347 4.2758539244186
10 8b50 8b50 00:81:F9:E4:8B:50 2366 -5223 2402 -14971 4.35162291666667
10 8b50 8b50 00:81:F9:E4:8B:50 2369 -11005 2360 -11797 4.30475635707671
11 c641 c641 18:04:ED:37:C6:41 2090 4616 1997 -40665 5.07591391714942
12 E8E6 E8E6 A4:DA:32:D4:E8:E6 2306 -88454 2418 -15140 4.2686494968089
13 E73B E73B A4:DA:32:D4:E7:3B 2262 -564 2298 44746 4.35551198222141
@@ -16,8 +16,8 @@ no device y=ax+b MAC a+ b+ a- b- avg
15 E871 E871 A4:DA:32:D4:E8:71 2175 -4549 2220 31468 4.60684608395208
16 EFC4 EFC4 A4:DA:32:D4:EF:C4 2348 -4371 2374 -26606 4.45106768611704
17 EF85 EF85 A4:DA:32:D4:EF:85 2136 -3339 2189 -30040 4.61909624778354
18 E7DA E7DA A4:DA:32:D4:E7:DA 2096 -10653 2054 -14255 3.73011080492424
19 E6EA E6EA A4:DA:32:D4:E6:EA 2074 -13075 2031 -13585 3.77641447962488
18 E7DA E7DA A4:DA:32:D4:E7:DA 2081 -3015 2122 -21543 4.79766509652981
19 E6EA E6EA A4:DA:32:D4:E6:EA 2039 -262 2127 -47259 4.79384458739747
20 EEDB EEDB A4:DA:32:D4:EE:DB 2214 -1170 2351 -24636 4.44485358085645
21 E73A E73A A4:DA:32:D4:E7:3A 2210 -4855 2339 -16434 4.47776494604746
22 E6CF E6CF A4:DA:32:D4:E6:CF 2135 -5206 2193 -30885 4.73462680884304
+1 -1
View File
@@ -4,7 +4,7 @@
#folder=$($path | awk -F"/" '{$NF}')
folder=$(basename "$(pwd)")
if [ "$folder" == "ti" ] ; then
if [ "$folder" == "ti" ]; then
year=$(date +%-y)
month=$(date +%-m)
day=$(date +%-d)
@@ -102,8 +102,8 @@ typedef enum {
FLUSH_BUFFER2, // clean SPI buffer twice
READ_REG, // read DBS register value, used after a "read" SPI instruction (MISO)
READ_REG2, // read DBS register value, used after a "read" SPI instruction (MISO)
ONE_SHOT_FLUSH, // read DBS register value, used after a "read" SPI instruction (MISO)
CONTI_SPI_WITH_FLUSH, // end spi instruction
END_TRANSMIT, // read DBS register value, used after a "read" SPI instruction (MISO)
ONE_SHOT_SPI, // end spi instruction
READ_MOSI
} SPI_CB_MODE;
@@ -119,8 +119,6 @@ static bool ConnectState = false;
static bool ErrorRestart = false;
static SPI_CB_MODE SPICallBack;
static uint8 adc_spi_en_switch = 1;
static bool rewrite_rec_en = false;
static bool rewrite_sti_en = false;
/*
* Let C = command, S = status;
@@ -216,7 +214,7 @@ extern ICall_Semaphore semaphore;
// command return characteristic
#define BLE_CDR_BUFF_CHAR SIMPLEPROFILE_CHAR2
#define BLE_CDR_BUFF_SIZE SIMPLEPROFILE_CHAR2_LEN
#define BLE_CDR_SMALL_SIZE 10
#define BLE_CDR_SAMLL_SIZE 10
// instruction input characteristic
#define BLE_INS_BUFF_CHAR SIMPLEPROFILE_CHAR3
@@ -358,7 +356,7 @@ static uint16_t CONNECT_HANDLE = 0;
/**
* command instruction buffer
*/
static uint8_t cdr_buf[BLE_CDR_SMALL_SIZE] = {0};
static uint8_t cdr_buf[BLE_CDR_SAMLL_SIZE] = {0};
/*====================
==== event table ====
@@ -27,14 +27,14 @@ static void SendCaliValue(uint8_t CaliNumber){
// ch = 2 * (CaliNumber % 4);
// uint8_t gain_level = CaliNumber / 4; // 0:gain, 1:offset
uint8_t channel_number = 8, index = 2;
uint8_t channel_number = 8, index = 1;
uint8_t gain_level = 0;
if(CaliNumber < 4){
gain_level = CaliNumber;
}
cali_buf[1] = CHIP_ID;
cali_buf[0] = CHIP_ID;
for(int i=0 ; i<channel_number ; i++){
cali_buf[index++] = (uint8_t) (CaliTable.Ch[i].Gain[gain_level] >> 8) & 0xFF;
cali_buf[index++] = (uint8_t) CaliTable.Ch[i].Gain[gain_level] & 0x00FF;
@@ -42,8 +42,9 @@ static void SendCaliValue(uint8_t CaliNumber){
cali_buf[index++] = (uint8_t) CaliTable.Ch[i].Offset[gain_level] & 0x00FF;
}
cali_buf[0] = index - 1;
// for(int i=1 ; i<BLE_CDR_BUFF_SIZE ; i++){
// cali_buf[i] = i;
// }
SimpleProfile_SetParameter(BLE_CDR_BUFF_CHAR, index, cali_buf);
}
@@ -192,18 +192,18 @@ struct _StiCaliStiTable{
#elif defined(BOARD_A4_DA_32_D4_E7_DA)
{
.p_ch.coefficient = 4834,
.p_ch.offset = -10653,
.n_ch.coefficient = 4628,
.n_ch.offset = -14255
.p_ch.coefficient = 2081,
.p_ch.offset = -3015,
.n_ch.coefficient = 2122,
.n_ch.offset = -21543
};
#elif defined(BOARD_A4_DA_32_D4_E6_EA)
{
.p_ch.coefficient = 4980,
.p_ch.offset = -13075,
.n_ch.coefficient = 4660,
.n_ch.offset = -13585
.p_ch.coefficient = 2039,
.p_ch.offset = -262,
.n_ch.coefficient = 2127,
.n_ch.offset = -47259
};
#elif defined(BOARD_A4_DA_32_D4_EE_DB)
@@ -27,7 +27,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
check_reg_counter = 0;
if(check_ins(instruction_to_fit)){
NEULIVE_STATE.state = next_state;
SPICallBack = CONTI_SPI_WITH_FLUSH;
SPICallBack = ONE_SHOT_SPI;
// update rec_sti_command
if(!(rec_sti_command & ENABLE_STI)){
@@ -70,7 +70,7 @@ static void check_register(uint8_t register_to_check, uint16_t instruction_to_fi
IsFirstData = true;
}
SPICallBack = CONTI_SPI_WITH_FLUSH;
SPICallBack = ONE_SHOT_SPI;
ReopenSPI();
}
headstage_spi_transaction(3);
@@ -167,7 +167,7 @@ static void check_sti_t1_t5(NEU_WORK_STATE next_state){
else{
NEULIVE_STATE.state = next_state;
}
SPICallBack = CONTI_SPI_WITH_FLUSH;
SPICallBack = ONE_SHOT_SPI;
headstage_spi_transaction(3);
}
@@ -1,214 +0,0 @@
#ifndef DBS_OBJECT_H
#define DBS_OBJECT_H
#include "neu/headstage_spi.h"
#define SYS_RESERVED_INDEX 0
#define SYS_GENERAL_ENABLE_INDEX 1
#define SYS_LNA_BIOS1_INDEX 2
#define SYS_LNA_BIOS2_INDEX 3
#define SYS_STI_CLK_RATIO_INDEX 4
#define REC_CHANNEL_INDEX 0
#define REC_GAIN_INDEX 1
#define REC_ADC_CLOCK_INDEX 2
#define STI_ENABLE_INDEX 0
#define STI_AMP_POS_INDEX 1
#define STI_AMP_NEG_INDEX 2
#define STI_POLARITY_INDEX 3
#define STI_CYCLE_CH01_INDEX 4
#define STI_CYCLE_CH23_INDEX 5
#define STI_CYCLE_CH45_INDEX 6
#define STI_CYCLE_CH67_INDEX 7
#define STI_CLK_RATIO_INDEX 8
#define STI_ARBITRARY_EN_INDEX 9
#define STI_MODE_INDEX 10
#define STI_DURATION0_INDEX 11
#define STI_DURATION1_INDEX 12
#define STI_DURATION2_INDEX 13
#define STI_DURATION3_INDEX 14
//#define DBS_REGISTER \
// uint8_t address; \
// void (*write_reg) (DBSRegister *self, uint32_t reg_value); \
// uint32_t (*read_reg) (DBSRegister *self)
typedef struct _DBSRegister{
uint8_t address;
bool WriteRegister, CheckRegister;
void (*write_reg) (uint8_t self_address, uint16_t reg_value);
void (*read_reg) (struct _DBSRegister *self);
}DBSRegister;
void write_reg(uint8_t self_address, uint16_t reg_value){
spi_txbuf[0] = 0x80 | self_address;
spi_txbuf[1] = (reg_value >> 8) & 0xFF ;
spi_txbuf[2] = reg_value & 0xFF;
// self->WriteRegister = false;
// self->CheckRegister = true;
SPICallBack = CONTI_SPI_WITH_FLUSH;
headstage_spi_transaction(SPI_BUFFER_SIZE);
}
void read_reg(DBSRegister *self){
spi_txbuf[0] = 0x7F & self->address;
spi_txbuf[1] = 0; // it's don't care actually
spi_txbuf[2] = 0; // it's don't care actually
SPICallBack = READ_REG;
headstage_spi_transaction(SPI_BUFFER_SIZE);
}
static uint16_t sys_register_default_value[5] = {
0x0000,
0x40F2,
0x0210,
0x4210,
0x0002
};
static uint16_t rec_register_value[3];
static uint16_t sti_register_value[43];
static uint16_t fast_settle_param[43];
static void init_fast_settle();
static DBSRegister sys_register[5];
static DBSRegister rec_register[3];
static DBSRegister sti_register[43];
static void InitSysRegister(){
sys_register[SYS_RESERVED_INDEX].address = 0x00;
sys_register[SYS_GENERAL_ENABLE_INDEX].address = 47; // general enable
sys_register[SYS_LNA_BIOS1_INDEX].address = 57;
sys_register[SYS_LNA_BIOS2_INDEX].address = 58;
sys_register[SYS_STI_CLK_RATIO_INDEX].address = 52;
for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
sys_register[i].WriteRegister = false;
sys_register[i].CheckRegister = false;
sys_register[i].write_reg = &write_reg;
sys_register[i].read_reg = &read_reg;
}
}
static void InitRecRegister(){
rec_register[REC_CHANNEL_INDEX].address = 48;
rec_register[REC_GAIN_INDEX].address = 49;
rec_register[REC_ADC_CLOCK_INDEX].address = 51; // sampling rate
for(int i=0 ; i<sizeof(rec_register)/sizeof(DBSRegister) ; i++){
rec_register[i].WriteRegister = false;
rec_register[i].CheckRegister = false;
rec_register[i].write_reg = &write_reg;
rec_register[i].read_reg = &read_reg;
}
rec_register_value[REC_CHANNEL_INDEX] = 0;
rec_register_value[REC_GAIN_INDEX] = 1;
rec_register_value[REC_ADC_CLOCK_INDEX] = 100;
}
static void InitStiRegister(){
sti_register[STI_ENABLE_INDEX].address = 46;
sti_register[STI_AMP_POS_INDEX].address = 37;
sti_register[STI_AMP_NEG_INDEX].address = 38;
sti_register[STI_POLARITY_INDEX].address = 40;
sti_register[STI_CYCLE_CH01_INDEX].address = 42;
sti_register[STI_CYCLE_CH23_INDEX].address = 43;
sti_register[STI_CYCLE_CH45_INDEX].address = 44;
sti_register[STI_CYCLE_CH67_INDEX].address = 45;
sti_register[STI_CLK_RATIO_INDEX].address = 52;
sti_register[STI_ARBITRARY_EN_INDEX].address = 54;
sti_register[STI_MODE_INDEX].address = 56;
for(int ch=0 ; ch<8 ; ch++){
sti_register[ch*4 + STI_DURATION0_INDEX].address = ch*4 + 1;
sti_register[ch*4 + STI_DURATION1_INDEX].address = ch*4 + 2;
sti_register[ch*4 + STI_DURATION2_INDEX].address = ch*4 + 3;
sti_register[ch*4 + STI_DURATION3_INDEX].address = ch*4 + 4;
}
for(int i=0 ; i<sizeof(sti_register)/sizeof(DBSRegister) ; i++){
sti_register[i].WriteRegister = false;
sti_register[i].CheckRegister = false;
sti_register[i].write_reg = &write_reg;
sti_register[i].read_reg = &read_reg;
}
sti_register_value[STI_AMP_POS_INDEX] = 1;
sti_register_value[STI_AMP_NEG_INDEX] = 1;
}
static void InitDBSRegister(){
InitSysRegister();
InitRecRegister();
InitStiRegister();
init_fast_settle();
for(int i=1 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
sys_register[i].WriteRegister = true;
}
sys_register[0].CheckRegister = true;
sys_register[0].write_reg(sys_register[0].address, sys_register_default_value[0]);
// flag_notify(EVT_NEU_SPI);
}
static void ResetDBSRegister(){
for(int i=0 ; i<sizeof(sys_register)/sizeof(DBSRegister) ; i++){
sys_register[i].WriteRegister = false;
sys_register[i].CheckRegister = false;
sys_register[i].write_reg = &write_reg;
sys_register[i].read_reg = &read_reg;
}
for(int i=0 ; i<sizeof(rec_register)/sizeof(DBSRegister) ; i++){
rec_register[i].WriteRegister = false;
rec_register[i].CheckRegister = false;
rec_register[i].write_reg = &write_reg;
rec_register[i].read_reg = &read_reg;
}
for(int i=0 ; i<sizeof(sti_register)/sizeof(DBSRegister) ; i++){
sti_register[i].WriteRegister = false;
sti_register[i].CheckRegister = false;
sti_register[i].write_reg = &write_reg;
sti_register[i].read_reg = &read_reg;
}
}
static uint16_t fast_settle_param[43];
static void init_fast_settle(){
uint8_t ch = 7;
uint8_t t1=25, t2=0, t3=25 , t4=0, t5=0;
// setting t1~t5
fast_settle_param[ch*4 + STI_DURATION0_INDEX] = (t2 & 0x003F) << 10 | (t1 & 0x03FF);
fast_settle_param[ch*4 + STI_DURATION1_INDEX] = (t4 & 0x0003) << 14 | (t3 & 0x03FF) << 4 | (t2 & 0x03C0) >> 6;
fast_settle_param[ch*4 + STI_DURATION2_INDEX] = (t4 & 0x0007FFFC) >> 2;
fast_settle_param[ch*4 + STI_DURATION3_INDEX] = t5;
// cycle number
fast_settle_param[STI_CYCLE_CH67_INDEX] = 10 << 8 | 0;
// set polarity, it's don't care in fast settle
fast_settle_param[STI_POLARITY_INDEX] = 0;
// set stimulate mode
fast_settle_param[STI_MODE_INDEX] = 0;
// INSTRUCTION.sti_mode = 0; // 1 = continuous mode; 0 = limit mode
// INSTRUCTION.sti_h_bridge = 0; // voltage sti must use H-bridge
// INSTRUCTION.sti_ref = 0; // 1 = GND; 0 = Vref
// using minimum amplitude
fast_settle_param[STI_AMP_POS_INDEX] = 0;
fast_settle_param[STI_AMP_NEG_INDEX] = 0;
// using ch8 to fast settle
fast_settle_param[STI_ENABLE_INDEX] = 0b0000000010000000; // 0bxxxx_xxxv_cccc_cccc, c = current; v = volt, x = don't care
}
#endif
@@ -6,7 +6,7 @@
static uint16_t UserCode2StiCode(uint16_t amp, uint8_t positive_ch){
// get real current value (uA)
int32_t sti_code, real_amp = amp * 5;
uint32_t sti_code, real_amp = amp * 5;
if(StiCaliTable.p_ch.coefficient == 10000 && StiCaliTable.p_ch.offset == 0){
return amp;
@@ -23,11 +23,7 @@ static uint16_t UserCode2StiCode(uint16_t amp, uint8_t positive_ch){
sti_code = StiCaliTable.n_ch.coefficient * real_amp + StiCaliTable.n_ch.offset;
}
if(sti_code <= 10000){
sti_code = 10000;
}
sti_code = (sti_code+5000) / 10000;
sti_code = sti_code / 10000;
return (uint16_t) (sti_code);
}
@@ -3,15 +3,15 @@
#define VERSION_DATE
#define VERSION_DATE_YEAR 20
#define VERSION_DATE_MONTH 12
#define VERSION_DATE_DAY 22
#define VERSION_DATE_HOUR 18
#define VERSION_DATE_MINUTE 26
#define VERSION_DATE_MONTH 8
#define VERSION_DATE_DAY 3
#define VERSION_DATE_HOUR 17
#define VERSION_DATE_MINUTE 42
// this is NOT the version hash !!
// it's the last version hash
#define VERSION_HASH 2937fa6a1124e6bac1d7726e51313a0d42c805dd
#define VERSION_GIT_BRANCH neulive20_development_onchange_central
#define VERSION_HASH f4861bb6cb427dcb36cb0cb6e8f1c962dbd89fa8
#define VERSION_GIT_BRANCH neulive20_linux_debug
static void get_board_name(char *board_name_ch, uint8 *board_name_int, uint8 name_size){
uint8 name_offset = 18;
@@ -8,60 +8,12 @@
#error "headstage/headstage_notify.h not included"
#endif
#include "headstage_dbs_object.h"
#define NOT_BUF_OFFSET_INIT 8
static uint8_t not_buf_offset = NOT_BUF_OFFSET_INIT;
static uint32_t not_time_stamp = 0;
static void headstage_notify_set_timestamp();
static void headstage_notify_flip_buffer();
static uint8_t headstage_notify_append_data(uint8_t *data_value);
/**
* @fn headstage_neu_append_notify_data
*/
#define CHANNEL_VALID (INSTRUCTION.recording_channel & (0x0001 << channel))
static void headstage_neu_append_notify_data() {
uint8_t channel = spi_rxbuf[0];
// close-reopen SPI, if the first channel received is invalid
if(IsFirstData){
// start record
if((INSTRUCTION.recording_channel & (0x0001 << channel)) && (channel < 16)){
IsFirstData = false;
}
// restart SPI
else{
SPI_close(headstage_spi_handle);
ReopenSPI();
IsFirstData = true;
return;
}
}
// discard illegal channel
uint16_t valid_channel = INSTRUCTION.recording_channel & (0x0001 << channel);
if(!(INSTRUCTION.recording_channel & (0x0001 << channel)) || (channel > 15)){
// illegal channel
return;
}
uint8_t not_buf[2];
not_buf[0] = (channel & 0x0F) << 4 | (spi_rxbuf[1] & 0x0F);
not_buf[1] = spi_rxbuf[2];
uint8_t data_size = headstage_notify_append_data(not_buf);
if (data_size >= BLE_NOT_BUFF_SIZE) {
headstage_notify_flip_buffer();
headstage_notify_send();
}
}
static uint32_t debug_counter = 0;
static void headstage_notify_set_timestamp() {
not_time_stamp = headstage_time_stamp_us();
@@ -69,12 +21,18 @@ static void headstage_notify_set_timestamp() {
headstage_notify_buffer[3] = (not_time_stamp >> 8) & 0xFF;
headstage_notify_buffer[4] = (not_time_stamp >> 16) & 0xFF;
headstage_notify_buffer[5] = (not_time_stamp >> 24) & 0xFF;
// headstage_notify_buffer[2] = (debug_counter >> 24) & 0xFF;
// headstage_notify_buffer[3] = (debug_counter >> 16) & 0xFF;
// headstage_notify_buffer[4] = (debug_counter >> 8) & 0xFF;
// headstage_notify_buffer[5] = debug_counter & 0xFF;
// debug_counter ++;
}
static void headstage_notify_flip_buffer() {
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 2;
uint8_t data_count = (not_buf_offset - NOT_BUF_OFFSET_INIT) / 3;
headstage_notify_buffer[0] = CHIP_ID;
headstage_notify_buffer[0] = 4;
headstage_notify_buffer[1] = data_count;
not_buf_offset = NOT_BUF_OFFSET_INIT;
@@ -89,9 +47,11 @@ static uint8_t headstage_notify_append_data(uint8_t *data_value) {
if (data_value == NULL) {
headstage_notify_buffer[not_buf_offset++] = 0x00;
headstage_notify_buffer[not_buf_offset++] = 0x00;
headstage_notify_buffer[not_buf_offset++] = 0x00;
} else {
headstage_notify_buffer[not_buf_offset++] = data_value[0];
headstage_notify_buffer[not_buf_offset++] = data_value[1];
headstage_notify_buffer[not_buf_offset++] = data_value[2];
}
if (not_buf_offset >= BLE_NOT_BUFF_SIZE - 1) {
@@ -4,7 +4,6 @@
#include "headstage_instruction.h"
#include "neu/headstage_spi.h"
#include "headstage_dbs_object.h"
static void ResetINSTRUCTION();
@@ -26,7 +25,7 @@ static void MCUReset(){
spi_txbuf[i] = 0;
spi_rxbuf[i] = 0;
}
SPICallBack = CONTI_SPI_WITH_FLUSH;
SPICallBack = ONE_SHOT_SPI;
ReopenSPI();
for(int i=0 ; i<SPI_LED_BUFF_SIZE ; i++){
@@ -34,7 +33,7 @@ static void MCUReset(){
}
// CIS buffer reset
for(int i=0 ; i<BLE_CDR_SMALL_SIZE ; i++){
for(int i=0 ; i<BLE_CDR_SAMLL_SIZE ; i++){
cdr_buf[i] = 0;
}
@@ -71,7 +70,6 @@ static void DBSReset(){
static void Neu2Reset(){
DBSReset();
MCUReset();
InitDBSRegister();
}
static void ResetINSTRUCTION(){
@@ -120,71 +120,4 @@ static void AppendSPITX(uint8_t index, uint32_t value){
}
}
/**
* @fn headstage_spi_callback
*
* description: callback function to deal with data transmission between DBS and CC2650
*/
static void headstage_spi_callback(SPI_Handle handle, SPI_Transaction* transaction) {
switch(SPICallBack){
case CONTINUOUS_TRANS:{
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
}
flag_notify(EVT_NEU_SPI);
break;
}
case FLUSH_BUFFER:{
SPICallBack = FLUSH_BUFFER2;
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
}
headstage_spi_transaction(SPI_BUFFER_SIZE);
break;
}
case FLUSH_BUFFER2:{
SPICallBack = CONTI_SPI_WITH_FLUSH;
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
}
flag_notify(EVT_NEU_SPI);
// headstage_spi_transaction(SPI_BUFFER_SIZE);
break;
}
case CONTI_SPI_WITH_FLUSH:{
SPICallBack = FLUSH_BUFFER;
for(int i=0 ; i<SPI_BUFFER_SIZE ; i++){
spi_txbuf[i] = 0x00;
}
headstage_spi_transaction(SPI_BUFFER_SIZE);
break;
}
case READ_MOSI:{
flag_notify(EVT_NEU_SPI);
break;
}
case READ_REG:{
check_reg_counter ++;
flag_notify(EVT_NEU_SPI);
break;
}
case CLOSE_SPI:{
SPICallBack = CONTI_SPI_WITH_FLUSH;
SPI_close(headstage_spi_handle);
break;
}
case ONE_SHOT_FLUSH:{
tx_put_u24(0, 0);
break;
}
default:{
break;
}
}
}
#endif
@@ -120,17 +120,17 @@
// Maximum connection interval (units of 1.25ms, 800=1000ms) if automatic
// parameter update request is enabled
//#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 6
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 30
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 40
#else //! FEATURE_OAD
// Minimum connection interval (units of 1.25ms, 8=10ms) if automatic
// parameter update request is enabled
#define DEFAULT_DESIRED_MIN_CONN_INTERVAL 80
#define DEFAULT_DESIRED_MIN_CONN_INTERVAL 8
//#define DEFAULT_DESIRED_MIN_CONN_INTERVAL 14
// Maximum connection interval (units of 1.25ms, 8=10ms) if automatic
// parameter update request is enabled
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 80
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 40
//#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 25
#endif // FEATURE_OAD
@@ -561,7 +561,6 @@ static void SimpleBLEPeripheral_taskFxn(UArg a0, UArg a1) {
headstage_init_device_info();
headstage_init();
InitDBSRegister();
for (;;) {
// Waits for a signal to the semaphore associated with the calling thread.
@@ -82,8 +82,7 @@ extern "C" {
// Length of Characteristic 5 in bytes
#define SIMPLEPROFILE_CHAR1_LEN 2
//#define SIMPLEPROFILE_CHAR2_LEN 50
#define SIMPLEPROFILE_CHAR2_LEN 34
#define SIMPLEPROFILE_CHAR2_LEN 50
#define SIMPLEPROFILE_CHAR3_LEN 20
#define SIMPLEPROFILE_CHAR4_LEN 200
//#define SIMPLEPROFILE_CHAR4_LEN 20