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CTL_WRT_WGAMPL added

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This commit is contained in:
frankydtai
2020-12-23 13:58:25 +08:00
parent a032346630
commit 7f51e113d6
3 changed files with 41 additions and 67 deletions
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simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteSPI.h
+12 -62
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@@ -130,10 +130,13 @@ static void CAL_LED_SPI(uint8_t length, uint16_t *spi_txbuf, uint16_t *spi_rxbuf
#define WGOFFSET 0x2038
#define WGAMPLITUDE 0x203C
#define WGCON 0x2014
#define DE0RESCON 0x20F8
#define ADCCON 0x21A8
#define HSTIACON 0x20FC
#define DFTCON 0x20D0
static void select_REG(uint16_t addr){
PIN_setOutputValue(pin_handle, AD_CS, 0);
// CPUdelay(16000);
spi_DACtxbuf[0] = SPICMD_SETADDR;
spi_DACtxbuf[1] = (uint8_t)((addr & 0xFF00) >> 8);
@@ -143,7 +146,6 @@ static void select_REG(uint16_t addr){
ADC_DAC_transaction.txBuf = spi_DACtxbuf;
ADC_DAC_transaction.rxBuf = spi_rxbuf;
SPI_transfer(spiHandle1, &ADC_DAC_transaction);
// CPUdelay(16000);
PIN_setOutputValue(pin_handle, AD_CS, 1);
}
@@ -235,39 +237,13 @@ static void AD5940_init(){
select_REG(0x22F0);
w16_REG(0x0000);
// select_REG(LPREFBUFCON);
// w32_REG(0);
// select_REG(SWMUX);
// w32_REG(0);
// select_REG(0x2110); //clock
// w32_REG(0b1);
select_REG(LPTIASW0); //20E4
// w32_REG(0b1000000100000010);
select_REG(LPTIACON0); //20EC
w32_REG(0b0000000000001);
select_REG(SWCON); //200C
w32_REG(0x402B5);
// select_REG(DSWFULLCON);
// w32_REG(0b000010000);
// select_REG(NSWFULLCON);
// w32_REG(0b000100000);
// select_REG(TSWFULLCON);
// w32_REG(0b1000000000);
// select_REG(PSWFULLCON);
// w32_REG(0b010000000000);
select_REG(HSDACCON); //2010
w32_REG(0x001A);
select_REG(HSDACDAT); //2048
w32_REG(0x800);
select_REG(WGFCW); //2030
w32_REG(0x10000);
select_REG(WGPHASE);
w32_REG(0);
select_REG(WGOFFSET);
w32_REG(0b0);
select_REG(WGAMPLITUDE); //203C
w32_REG(0b11111111111);
select_REG(WGCON); //2014
@@ -290,45 +266,19 @@ static void AD5940_init(){
w32_REG(0x31CFC0);
// w32_REG(0b1100011100111111000000);
select_REG(LPDACCON0);
w32_REG(0b0000001); //2128
select_REG(LPDACSW0); //2124
w32_REG(0b101011);
select_REG(LPDACCON0); //2128
w32_REG(0b0000001);
select_REG(LPDACDAT0); //2120
w32_REG(0x10800);
select_REG(LPDACSW0); //2124
w32_REG(0b101011);
select_REG(0x20F0); //HSRTIACON
w32_REG(0b00100);
select_REG(0x20F8); //DE0RESCON
select_REG(DE0RESCON); //20F8
w32_REG(0x58);
select_REG(0x21A8); //ADCCON
select_REG(ADCCON); //21A8
w32_REG(0x101);
select_REG(0x20FC); //HSTIACON
select_REG(HSTIACON); //20FC
w32_REG(0x0);
select_REG(0x20D0); //DFTCON
select_REG(DFTCON); //20D0
w32_REG(0x200091);
select_REG(0x2044); //ADCFILTERCON
w32_REG(0xC3D0);
}
static void EIS_LPDAC_SPI(){
// uint32_t con = 0b00001;//12 bit DAC
// uint32_t sw = 0b01010;//test mode
// uint32_t volt = 0;//2.4v
// uint32_t buf = 0;//LP reference
// uint32_t cm = 0;//common mode disabled
// select_REG(LPDACCON0);
// w32_REG(con);
// select_REG(LPDACSW0);
// w32_REG(sw);
// select_REG(LPDACDAT0);
// w32_REG(volt);
// select_REG(LPREFBUFCON);
// w32_REG(buf);
// select_REG(SWMUX);
// w32_REG(cm);
}
#endif
#endif // ELITE_SPI
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite_def.h
+4 -2
View File
@@ -46,8 +46,10 @@
#define CIS_LED_TEST 0x70
#define CTL_WRT 0x20
#define CTL_RD 0x21
#define CTL_WRT_RD_DFTR 0x78
#define CTL_WRT_RD_DFTI 0x7C
#define CTL_RD_DFTR 0x78
#define CTL_RD_DFTI 0x7C
#define CTL_WRT_WGAMPL 0x3C
// mode parameter
#define STEP_TO_VSETRATE(step) step2VsetRate(step)
#define VMAX(v1,v2) ((v1 >= v2) ? v1 : v2)
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h
+25 -3
View File
@@ -1203,7 +1203,7 @@ static void update_ZM_instruction(uint8 *ins) {
uint32_t address = ((uint16_t)(ins[2]) << 8) | (uint16_t)(ins[3]);
uint32_t data = ((uint16_t)(ins[4]) << 24) | (uint16_t)(ins[5]) << 16 | (uint16_t)(ins[6]) << 8 | (uint16_t)(ins[7]);
select_REG(address);
w32_REG(data);//configuration register
w32_REG(data);
cis_buf[0] = (uint8_t)((address & 0x0000FF00) >> 8);
cis_buf[1] = (uint8_t)(address & 0x000000FF);
@@ -1231,7 +1231,7 @@ static void update_ZM_instruction(uint8 *ins) {
break;
}
case CTL_WRT_RD_DFTR: { // 0x7022FFFFFFFF
case CTL_RD_DFTR: { // 0x7078FFFFFFFF
initCISBuf();
select_REG(0x2078);
r32_REG();
@@ -1246,7 +1246,7 @@ static void update_ZM_instruction(uint8 *ins) {
break;
}
case CTL_WRT_RD_DFTI: { // 0x7023FFFFFFFF
case CTL_RD_DFTI: { // 0x707cFFFFFFFF
initCISBuf();
select_REG(0x207C);
r32_REG();
@@ -1261,6 +1261,28 @@ static void update_ZM_instruction(uint8 *ins) {
break;
}
case CTL_WRT_WGAMPL: { // 0x703cFFFFFFFF
initCISBuf();
select_REG(0x203C);
uint32_t data = ((uint16_t)(ins[2]) << 24) | (uint16_t)(ins[3]) << 16 | (uint16_t)(ins[4]) << 8 | (uint16_t)(ins[5]);
w32_REG(data);
cis_buf[0] = (uint8_t)((0x2038 & 0x0000FF00) >> 8);
cis_buf[1] = (uint8_t)(0x2038 & 0x000000FF);
cis_buf[2] = (uint8_t)((data & 0xFF000000) >> 24);
cis_buf[3] = (uint8_t)((data & 0x00FF0000) >> 16);
cis_buf[4] = (uint8_t)((data & 0x0000FF00) >> 8);
cis_buf[5] = (uint8_t)(data & 0x000000FF);
SimpleProfile_SetParameter(BLE_CIS_BUFF_CHAR, BLE_CIS_BUFF_SIZE, cis_buf);
select_REG(0x2014);
w32_REG(0x4);
select_REG(0x21A8);
w32_REG(0x31CFC0);
break;
}
case CIS_LED_TEST: { //0x7070
if( ins[2] == 0 ){
Elite_led_color(ins[3]);