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Version 2 getting zeros up to 100Hz, not able to enable SINC2 filter.

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This commit is contained in:
Taylor Liao
2021-08-22 12:45:06 +08:00
parent 18c35e27d0
commit 780d0afa6a
7 changed files with 113 additions and 56 deletions
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simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h
+13 -13
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@@ -4,7 +4,7 @@
static void HSTIA_config (void) {
select_REG(AFECON);
w32_REG(0x0030CFC0);
w32_REG(0x0031CFC0);
PowerMode_CutoffFrequencyControl(cutoff_auto, HIGH_PW_MODE);
select_REG(CLKSEL); //CLKSEL
w32_REG(0x00000000); //ADC and system clock both internal high frequency oscillator clock
@@ -98,6 +98,14 @@ static void setEIS_EIS (void)
select_REG(HSRTIACON);
w32_REG(0x00000200); //4pF + 200R
select_REG(ADCCON); //21A8
w32_REG(0x00000101);
select_REG(DFTCON); //20D0
w32_REG(0x00300091); //takes sinc2 | DFTNUM = 8
select_REG(SWCON); //200C
w32_REG(0x00026355); //D5 | P5 | N3 | T6 | T9 0b010 0110 0011 0101 0101
// w32_REG(0x00026905); //0b010 0110 1001 0000 0101
if (instru.ADCGainLv != HSRTIA_GAIN_AUTO) {
instru.AutoGainEnable = 0;
} else {
@@ -109,17 +117,6 @@ static void setEIS_EIS (void)
DAC_outputV(instru.dcbias);
SetWGAmp(instru.acamp);
select_REG(ADCCON); //21A8
w32_REG(0x00000101);
select_REG(DFTCON); //20D0
w32_REG(0x00300091); //takes sinc2 | DFTNUM = 8
select_REG(SWCON); //200C
w32_REG(0x00026355); //D5 | P5 | N3 | T6 | T9 0b010 0110 0011 0101 0101
// w32_REG(0x00026905); //0b010 0110 1001 0000 0101
select_REG(AFECON); //2000
w32_REG(0x0031CFC0);
//HIGH POWER MODE
select_REG(0x22F0); //PWMB
w32_REG(0x0000000D); //switch to active high power mode
@@ -131,12 +128,15 @@ static void setEIS_EIS (void)
w16_REG(0x0442); //set divider = 2
select_REG(0x20BC); //HSOSCCON
w32_REG(0x00000000); //switch to 32MHz output
select_REG(ADCFILTERCON); //0x2044
select_REG(0x2044); //0x2044
w32_REG(0x00001310); //ADC data rate = 1.6MHz | SINC2 267 | SINC3 4
select_REG(0x2010); //HSDACCON
w32_REG(0x0000000E); //DAC gain = 2, > 80 kHz
select_REG(0x238C); //ADCBUFCON
w32_REG(0x005F3D0F); //recommended
select_REG(AFECON); //2000
w32_REG(0x0031CFC0);
}
static void setEIS_CV (void)
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h
+34 -29
View File
@@ -1143,15 +1143,18 @@ static void SelDFTin(uint8_t ret){ // 1: SINC3 | 2: raw | 3: SINC2
w32_REG(code);
}
static void EnSinc2(uint8_t ret){
static void EnSinc2(uint8_t ret){ // 1: enable, 0: disable
uint32_t code;
select_REG(AFECON);
code = r32_REG();
code = (code & (~(1 << 16))) | (ret << 16);
w32_REG(code);
//
// select_REG(ADCFILTERCON);
// code2 = r32_REG();
// code2 = (code2 & (~(1 << 20))) | (!ret << 20);
// w32_REG(code2);
}
static void SetSinc3OSR(uint8_t osr){ //0, 1, 2, 3
@@ -1192,76 +1195,78 @@ static uint32_t SetSamplingTime(uint32_t freq){
// 10000 Hz | 2.56ms
if (freq >= 1000000) {
EnSinc2(0);
SelDFTin(1);
SetADCDataRate(ADC1M6sps);
SetSinc3OSR(Sinc3OSR4);
EnSinc2(0);
SetDFTNUM(DFTNUM1024);
SelDFTin(1);
time = 27;
}
// 1000Hz | 3.52ms
else if (freq >= 100000) {
EnSinc2(0);
SelDFTin(1);
SetADCDataRate(ADC1M6sps);
SetSinc3OSR(Sinc3OSR4);
EnSinc2(0);
SetDFTNUM(DFTNUM128);
SelDFTin(1);
time = 35;
SetDFTNUM(DFTNUM8192);
time = 205;
}
// 100Hz | 28.16ms
// 100Hz | 51.2ms
else if (freq >= 10000) {
SetADCDataRate(ADC1M6sps);
EnSinc2(1);
SetSinc2OSR(Sinc2OSR22);
SetSinc3OSR(Sinc3OSR4);
SetDFTNUM(DFTNUM512);
SelDFTin(3);
time = 282;
EnSinc2(0);
SelDFTin(1);
SetADCDataRate(ADC800Ksps);
SetSinc3OSR(Sinc3OSR5);
SetDFTNUM(DFTNUM8192);
time = 512;
}
// 10Hz | 225ms
else if (freq >= 1000) {
SetADCDataRate(ADC1M6sps);
EnSinc2(1);
Elite_led_color(COLOR_ORANGE);
select_REG(0x2000);
w32_REG(0x0031CFC0);
// EnSinc2(1);
// SelDFTin(3);
SetADCDataRate(ADC800Ksps);
SetSinc2OSR(Sinc2OSR22);
SetSinc3OSR(Sinc3OSR4);
SetDFTNUM(DFTNUM4096);
SelDFTin(3);
time = 2250;
SetSinc3OSR(Sinc3OSR5);
SetDFTNUM(DFTNUM8192);
time = 4506;
}
// 1Hz | 2.25s
else if (freq >= 100) {
SetADCDataRate(ADC800Ksps);
EnSinc2(1);
SelDFTin(3);
SetADCDataRate(ADC800Ksps);
SetSinc2OSR(Sinc2OSR22);
SetSinc3OSR(Sinc3OSR5);
SetDFTNUM(DFTNUM16384);
SelDFTin(3);
time = 22250;
}
//0.1Hz | 26.34s
else if (freq >= 10) {
SetADCDataRate(ADC800Ksps);
EnSinc2(1);
SelDFTin(3);
SetADCDataRate(ADC800Ksps);
SetSinc2OSR(Sinc2OSR267);
SetSinc3OSR(Sinc3OSR5);
SetDFTNUM(DFTNUM16384);
SelDFTin(3);
time = 263400;
}
// 0.015Hz | 136s
else if (freq >= 1) {
SetADCDataRate(ADC800Ksps);
EnSinc2(1);
SelDFTin(3);
SetADCDataRate(ADC800Ksps);
SetSinc2OSR(Sinc2OSR1333);
SetSinc3OSR(Sinc3OSR5);
SetDFTNUM(DFTNUM16384);
SelDFTin(3);
time = 1360000;
}
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h
+39 -3
View File
@@ -133,7 +133,7 @@ static uint32_t CalcPeriod(uint32_t freq){ //One Second = 10000
}
static uint32_t CalcDelayTime(uint32_t freq, bool delayFlag){
static uint32_t delayTime;
static uint32_t delayTime, decadeSamplingTime;
delayTime = CalcPeriod(freq) * instru.delay; //get delay time
if (delayTime < 20) {
delayTime = 20;
@@ -141,10 +141,46 @@ static uint32_t CalcDelayTime(uint32_t freq, bool delayFlag){
delayTime = (delayTime + 5) / 10;
}
// 10000 Hz | 2.56ms
if (freq >= 1000000) {
decadeSamplingTime = 27;
}
// 1000Hz | 3.52ms
else if (freq >= 100000) {
decadeSamplingTime = 205;
}
// 100Hz | 28.16ms
else if (freq >= 10000) {
decadeSamplingTime = 1126;
}
// 10Hz | 225ms
else if (freq >= 1000) {
decadeSamplingTime = 2250;
}
// 1Hz | 2.25s
else if (freq >= 100) {
decadeSamplingTime = 22250;
}
//0.1Hz | 26.34s
else if (freq >= 10) {
decadeSamplingTime = 263400;
}
// 0.015Hz | 136s
else if (freq >= 1) {
decadeSamplingTime = 1360000;
}
if(delayFlag){
delayTime += 5 * CalcPeriod(freq); //delay+reading time
delayTime += 400 + decadeSamplingTime; //delay+reading time
} else {
delayTime = 5 * CalcPeriod(freq);
delayTime = 400 + decadeSamplingTime;
}
// InputNotify(NOTIFY_CURRENT, delayTime);
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteEISMode.h
+1 -3
View File
@@ -71,10 +71,8 @@ static void eis_fscan(void)
else if(instru.scale == 1) { // linear
instru.fset = eis->_fd1 - eis->_sweepIndex * ((eis->_fd1 - eis->_fd2) / (eis->_ppd - 1));
}
}
if(++eis->_sweepIndex == eis->_ppd) {
if(++eis->_sweepIndex == (eis->_ppd - 1)) {
eis->_sweepIndex = 0;
eis->_decadeIndex ++;
}
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteInstruction.h
+1 -1
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@@ -157,7 +157,7 @@ struct HEADSTAGE_INSTRUCTION {
#define Sinc3OSR5 0
#define Sinc3OSR4 1
#define Sinc3OSR3 2
#define Sinc3OSR2 2
#define Sinc2OSR22 0
#define Sinc2OSR44 1
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite_mode_ADC_DAC.h
+11 -4
View File
@@ -502,7 +502,6 @@ static void EIS_Plot(void) //real and imag impedance plot
} else {
if (ADC_cnt == 0){
Elite_led_color(COLOR_CYAN);
// read_HSTIA_Iin();
HSTIA_change_gain();
ADC_cnt ++;
@@ -517,14 +516,22 @@ static void EIS_Plot(void) //real and imag impedance plot
ADC_cnt ++;
}
else if (ADC_cnt == 3) {
read_HSTIA_Iin();
ADC_cnt ++;
}
else if (ADC_cnt == 4) {
read_HSTIA_Iin();
ADC_cnt ++;
}
else if (ADC_cnt == 5) {
notify_flag = true;
ADC_cnt = 0;
}
}
// InputNotify(NOTIFY_CURRENT, instru.imag);
// InputNotify(NOTIFY_VOLT, instru.real);
// InputNotify(NOTIFY_IMPEDANCE, instru.fset);
InputNotify(NOTIFY_CURRENT, instru.imag);
InputNotify(NOTIFY_VOLT, instru.real);
InputNotify(NOTIFY_IMPEDANCE, instru.fset);
// notify_flag = true;
return;
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h
+14 -3
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@@ -692,8 +692,8 @@ static void update_ZM_instruction(uint8 *ins) {
case CURVE_EIS: { //0xD1
if (ins[3] == PARA_1) { //3000D1 01
instru.sampleRate = CalcDelayTime(instru.f1, true); //ms //read
instru.f1 = 6711409;//((uint32_t)(ins[4]) << 24) | ((uint32_t)(ins[5]) << 16) | ((uint32_t)(ins[6]) << 8) | (uint32_t)(ins[7]); //FREQ_START
instru.f2 = 67;//((uint32_t)(ins[8]) << 24) | ((uint32_t)(ins[9]) << 16) | ((uint32_t)(ins[10]) << 8) | (uint32_t)(ins[11]); //FREQ_STOP
instru.f1 = 671;//((uint32_t)(ins[4]) << 24) | ((uint32_t)(ins[5]) << 16) | ((uint32_t)(ins[6]) << 8) | (uint32_t)(ins[7]); //FREQ_START
instru.f2 = 6711;//((uint32_t)(ins[8]) << 24) | ((uint32_t)(ins[9]) << 16) | ((uint32_t)(ins[10]) << 8) | (uint32_t)(ins[11]); //FREQ_STOP
instru.fmax = (uint32_t)VMAX(instru.f1, instru.f2);
instru.fmin = (uint32_t)VMIN(instru.f1, instru.f2);
instru.delay = 10;//((uint16_t)(ins[12]) << 8) | (uint16_t)(ins[13]); //DELAY/10 how many periods
@@ -1336,7 +1336,7 @@ static void update_ZM_instruction(uint8 *ins) {
w32_REG(0x00333333); //SINEFCW/2^30 * 16 MHz
select_REG(AFECON); //2000
w32_REG(0x0030CFC0);
w32_REG(0x0031CFC0);
//HIGH POWER MODE
select_REG(0x22F0); //PMBW
@@ -1360,6 +1360,17 @@ static void update_ZM_instruction(uint8 *ins) {
w32_REG(0x00000004);
break;
}
case 0x13: {
EnSinc2(1);
break;
}
case 0x14: {
EnSinc2(0);
break;
}
/*
case CTL_CV3: { //UI write: 13 with lpdac/lptia/dac
AD5940_init();