Merge remote-tracking branch 'origin/Elite_1.5_Taylor_061721' into Elite_1.5_Taylor_061721

This commit is contained in:
Taylor Liao
2021-08-06 11:34:29 +08:00
3 changed files with 98 additions and 83 deletions
@@ -167,14 +167,35 @@ static void HSTIAGainCtrl(uint8_t HSTIALevel) {
/* HSRTIACON[12:5] = CTIACON, fix at 16pF;
HSRTIACON[4] = TIASW6CON, diode not in parallel with RTIA;
HSRTIACON[3:0] = RTIA */
uint32_t reg = 0;
if (HSTIALevel <= RTIAopen) {
reg = (uint32_t)(HSTIALevel) & 0x0000000F;
if (HSTIALevel == HSRTIA_160K) {
// ADC gain level = 0, using 160k resister
reg = (uint32_t)(RTIA160k) & 0x0000000F;
reg = reg & 0x0000010F;
} else if (HSTIALevel == HSRTIA_20K) {
// ADC gain level = 1, using 20k resister
reg = (uint32_t)(RTIA20k) & 0x0000000F;
reg = reg & 0x0000010F;
}
else if (HSTIALevel == HSRTIA_5K) {
// ADC gain level = 2, using 5k resister
reg = (uint32_t)(RTIA5k) & 0x0000000F;
reg = reg & 0x0000010F;
}
else if (HSTIALevel == HSRTIA_200R) {
// ADC gain level = 3, using 200R resister
reg = (uint32_t)(RTIA200R) & 0x0000000F;
reg = reg & 0x0000010F;
}
else if (HSTIALevel == HSRTIA_GAIN_AUTO) {
// ADC gain level = 4, using 200R resister
reg = (uint32_t)(RTIA200R) & 0x0000000F;
reg = reg & 0x0000010F;
} else {
reg = 0x0000010F;
// default left RTIA open
reg = (uint32_t)(RTIAopen) & 0x0000000F;
reg = reg & 0x0000010F;
}
select_REG(HSRTIACON);
@@ -29,7 +29,7 @@
*/
#define BOARD_EEEF
#define BOARD_EIS
typedef struct _formula{
@@ -43,12 +43,39 @@ struct _correction{
Formula ADC_volt[3];
Formula ADC_current[4];
Formula Usercode2DAC[2];
uint16_t Gain0Boundary[2];
uint16_t Gain1Boundary[4];
uint16_t Gain2Boundary[2];
} Correction =
#ifdef BOARD_EIS // EIS
{
.ADC_volt[0].coeff = (6268),
.ADC_volt[0].offset = -101548925,
.ADC_volt[1].coeff = (215286),
.ADC_volt[1].offset = -3498610755,
.ADC_volt[2].coeff = (6248966),
.ADC_volt[2].offset = -101525581798,
.ADC_current[0].coeff = 3140113,
.ADC_current[0].offset = (-51096616915),
.ADC_current[1].coeff = 71991480,
.ADC_current[1].offset = (-1171591233910),
.ADC_current[2].coeff = 1463918055,
.ADC_current[2].offset = (-23822237948708),
.ADC_current[3].coeff = 30759517333,
.ADC_current[3].offset = (-500591140209163),
.Usercode2DAC[0].coeff = (-10508844),
.Usercode2DAC[0].offset = 581826013531,
.Usercode2DAC[1].coeff = (-178229067),
.Usercode2DAC[1].offset = 4775935828877,
};
#endif
#ifdef BOARD_C7A1 //megafly
{
.ADC_volt[0].coeff = (6256),
@@ -1002,39 +1029,6 @@ static int32_t DecodeADCValue(uint8_t ADCGain, uint8_t ADCChannel, uint8_t *ADC_
return ret;
}
// #0 board, (0x5f75 <= rawdata) && (rawdata <= 0x5fb2)
// ((0x5f97 < rawdata) && (rawdata < 0x6589)) || ((0x5999 < rawdata) && (rawdata < 0x5f93))
static void ADC_overflow(uint8_t gain, uint8_t *rawdata){
// Gain boundary defines different ADC gain level working area
// Gain0Boundary = {lowerbound, upperbound}, is the lower and upper bound of gain level 0 working area.
uint16_t U16Rawdata = 0;
U16Rawdata = (((uint16_t) (rawdata[0]))<<8) | ((uint16_t) (rawdata[1]));
if(gain == I_GAIN_3M){
if( U16Rawdata <= Correction.Gain0Boundary[0]){
rawdata[0] = Correction.Gain0Boundary[0] >> 4;
rawdata[1] = (uint8_t) (Correction.Gain0Boundary[0] & 0x00FF);
}
else if(U16Rawdata >= Correction.Gain0Boundary[1]){
rawdata[0] = (uint8_t) (Correction.Gain0Boundary[1] >> 4);
rawdata[1] = (uint8_t) (Correction.Gain0Boundary[1] & 0x00FF);
}
}
else if(gain == I_GAIN_100K){
if( U16Rawdata <= Correction.Gain1Boundary[0]){
rawdata[0] = Correction.Gain1Boundary[0] >> 4;
rawdata[1] = (uint8_t) (Correction.Gain1Boundary[0] & 0x00FF);
}
else if(U16Rawdata >= Correction.Gain1Boundary[1]){
rawdata[0] = (uint8_t) (Correction.Gain1Boundary[1] >> 4);
rawdata[1] = (uint8_t) (Correction.Gain1Boundary[1] & 0x00FF);
}
}
}
// User will enter -5V~+5V in UI.
// websever and controler use 0~50000 represent -5~+5V
// this function should turn 0~50000 into DACcode which output the exactly voltage user want
@@ -97,51 +97,52 @@ struct HEADSTAGE_INSTRUCTION {
} instru = {0};
/** Iin, Vin, Vout **/
#define EIS_HSTIA 0x00
#define VIN_ADC 0x01
#define EIS_HSDAC 0x02
#define HIGH_Z 0x03
#define VOUT_DAC 0x04
#define IIN_ADC 0x05
#define EIS_HSTIA 0x00
#define VIN_ADC 0x01
#define EIS_HSDAC 0x02
#define HIGH_Z 0x03
#define VOUT_DAC 0x04
#define IIN_ADC 0x05
/** ADC Iin gain level **/
#define I_GAIN_3M 0x07 // largest gain
#define I_GAIN_100K 0x08
#define I_GAIN_3K 0x09
#define I_GAIN_100R 0x0A // the least gain
#define I_GAIN_AUTO 0x04
#define I_GAIN_3M 0x07 // largest gain
#define I_GAIN_100K 0x08
#define I_GAIN_3K 0x09
#define I_GAIN_100R 0x0A // the least gain
#define I_GAIN_AUTO 0x04
// EIS LPTIA Iin Gain Level //
#define LPRTIA_512K 0x00
#define LPRTIA_12K 0x01
#define LPRTIA_4K 0x02
#define LPRTIA_200R 0x03
#define LPRTIA_512K 0x00
#define LPRTIA_12K 0x01
#define LPRTIA_4K 0x02
#define LPRTIA_200R 0x03
// EIS HSTIA Iin Gain Level
#define HSRTIA_160K 0x00
#define HSRTIA_20K 0x01
#define HSRTIA_5K 0x02
#define HSRTIA_200R 0x03
#define HSRTIA_160K 0x00
#define HSRTIA_20K 0x01
#define HSRTIA_5K 0x02
#define HSRTIA_200R 0x03
#define HSRTIA_GAIN_AUTO 0x04
/** ADC Vin gain level **/
#define VIN_GAIN_1M 0x00
#define VIN_GAIN_30K 0x01
#define VIN_GAIN_1K 0x02
#define VIN_GAIN_AUTO 0x03
#define VIN_GAIN_1M 0x00
#define VIN_GAIN_30K 0x01
#define VIN_GAIN_1K 0x02
#define VIN_GAIN_AUTO 0x03
/** Vout gain level **/
#define VOUT_GAIN_240K 0x00
#define VOUT_GAIN_15K 0x01
#define VOUT_GAIN_AUTO 0x02
#define VOUT_GAIN_240K 0x00
#define VOUT_GAIN_15K 0x01
#define VOUT_GAIN_AUTO 0x02
/* DAC reset parameter */
#define DAC_ZERO 25000
#define EIS_HSDAC_ZERO 0x0800
#define DAC_ZERO 25000
#define EIS_HSDAC_ZERO 0x0800
// Step time macro
#define STEPTIME_HALF_SEC 5000
#define STEPTIME_ONE_SEC 10000
#define STEPTIME_TWO_SEC 20000
#define STEPTIME_HALF_SEC 5000
#define STEPTIME_ONE_SEC 10000
#define STEPTIME_TWO_SEC 20000
/* AVG Number */
#define AVG2 0
@@ -161,16 +162,15 @@ struct HEADSTAGE_INSTRUCTION {
static uint8_t HSRTIATable[4] = {7, 4, 2, 0};
/* HSTIA gain level (feedback R value) */
#define RTIA0 0x00 // 200R
#define RTIA1 0x01 // 1k
#define RTIA2 0x02 // 5k
#define RTIA3 0x03 // 10k
#define RTIA4 0x04 // 20k
#define RTIA5 0x05 // 40k
#define RTIA6 0x06 // 80k
#define RTIA7 0x07 // 160k
#define RTIAopen 0x08 // RTIA is open
#define RTIA_GAIN_AUTO 0xFF
#define RTIA200R 0x00 // 200R
#define RTIA1k 0x01 // 1k
#define RTIA5k 0x02 // 5k
#define RTIA10k 0x03 // 10k
#define RTIA20k 0x04 // 20k
#define RTIA40k 0x05 // 40k
#define RTIA80k 0x06 // 80k
#define RTIA160k 0x07 // 160k
#define RTIAopen 0x08 // RTIA is open
/*********************************************************************
* @fn InitEliteInstruction
*