wisetop/microchip-application-cc2650-wtp_cc2650_development
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[update] note setting of eis mode

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ROY
2022-11-25 14:40:32 +08:00
parent 98a98120a2
commit f2db9cdac8
2 changed files with 43 additions and 29 deletions
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simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h
+41 -27
View File
@@ -4,15 +4,15 @@
static void setEIS_EIS (void)
{
AD5940_SPIWriteReg(LPDACCON0, 0x00000001); // DC on // LPDAC enabled
AD5940_SPIWriteReg(LPDACSW0, 0b111111); // operation // 0b101011
AD5940_SPIWriteReg(LPDACCON0, 0x00000001); // Direct from LPDACDAT0 | Vzero(6bit) & Vbias(12bit) | LP 2.5v as ref
AD5940_SPIWriteReg(LPDACSW0, 0b111111); // orverride LPDACCON0[5] | LPDACSW0[0~5] close
AD5940_SPIWriteReg(HSRTIACON, 0x00000000); //200R | 1pF
AD5940_SPIWriteReg(HSTIACON, 0x00000001); // Vzero
AD5940_SPIWriteReg(HSRTIACON, 0x00000000); // CTIA=1pF | SW6 off(open) | RTIA=200R
AD5940_SPIWriteReg(HSTIACON, 0x00000001); // Vzero
AD5940_SPIWriteReg(ADCCON, 0x00000101);
AD5940_SPIWriteReg(DFTCON, 0x00000091);
AD5940_SPIWriteReg(SWCON, 0x00026355); //D5 | P5 | N3 | T6 | T9 0b010 0110 0011 0101 0101
AD5940_SPIWriteReg(ADCCON, 0x00000101); // PGA=1 | HSTIA neg input | HSTIA pos signal
AD5940_SPIWriteReg(DFTCON, 0x00000091); // DFTNUM=2048 | enable hanning window | SINC2
AD5940_SPIWriteReg(SWCON, 0x00026355); // D5 | P5 | N3 | T6 | T9 close
if (instru.gain_lv_hstia < HSRTIA_MAX) {
instru.HSTIAAutoGainEnable = 0;
@@ -30,31 +30,38 @@ static void setEIS_EIS (void)
SetWGAmp(instru.acamp,instru.fset);
AD5940_SPIWriteReg(AFECON, 0x0031CFC0);
AD5940_SPIWriteReg(AFECON, 0x0031CFC0); // en dc DAC buf | HSDAC ref disable | LDO buf current limit enable | en SINC2 |
// DFT hardware accelerator enable | waveform generator enable | HSTIA enable |
// intru amplifier enable | excitation buf enable | ADC conversions enable |
// ADC power enable | HSDAC enable | HP ref enable
//HIGH POWER MODE
AD5940_SPIWriteReg(PMBW, 0x0000000D); //switch to active high power mode
AD5940_SPIWriteReg(PMBW, 0x0000000D); // HS mode | Set cutooff frequency to 250kHz, -3 dB bandwidth
AD5940_SPIWriteReg(CLKSEL, 0x0000);
AD5940_SPIWriteReg(CLKCON0KEY, 0xA815);
AD5940_SPIWriteReg(CLKCON0, 0x0442); //16bit system clock divider //set divider = 2
AD5940_SPIWriteReg(HSOSCCON, 0x00000000); //switch to 32MHz output
AD5940_SPIWriteReg(ADCFILTERCON, 0x00000311);
AD5940_SPIWriteReg(HSDACCON, 0x0000000E); //DAC gain = 2, > 80 kHz
AD5940_SPIWriteReg(CLKCON0KEY, 0xA815); // !!!Write 0xA815 to this register before accessing the CLKCON0 register
AD5940_SPIWriteReg(CLKCON0, 0x0442); //6bit system clock divider //set divider = 2
AD5940_SPIWriteReg(HSOSCCON, 0x00000000); // HP osc select 32MHz output
AD5940_SPIWriteReg(ADCFILTERCON, 0x00000311); // en DFT clk | en DAC wave clk | en SINC2 filter clk | 2 ADC samples used for average function |
// SINC3 filter oversampling rate is 800kSPS |
// SINC2 filter oversampling rate is 178 samples |
// disable average | SINC3 filter enable |
// Bypass 50/60Hz | ADC data rate 800kHz
AD5940_SPIWriteReg(HSDACCON, 0x0000000E); // HSDAC gain = 2, DAC update rate = ACLK/HSDACCON = 32Mhz/7
AD5940_SPIWriteReg(ADCBUFCON, 0x005F3D0F); //recommended
SetEISHIGHZ(0);
}
static void setEIS_EIS_cali(void)
{
AD5940_SPIWriteReg(LPDACCON0, 0x00000001); // DC on // LPDAC enabled
AD5940_SPIWriteReg(LPDACSW0, 0b111111); // operation // 0b101011
AD5940_SPIWriteReg(LPDACCON0, 0x00000001); // Direct from LPDACDAT0 | Vzero(6bit) & Vbias(12bit) | LP 2.5v as ref
AD5940_SPIWriteReg(LPDACSW0, 0b111111); // orverride LPDACCON0[5] | LPDACSW0[0~5] close
AD5940_SPIWriteReg(HSRTIACON, 0x00000000); //200R | 1pF
AD5940_SPIWriteReg(HSRTIACON, 0x00000000); // CTIA=1pF | SW6 off(open) | RTIA=200R
AD5940_SPIWriteReg(HSTIACON, 0x00000001); // Vzero
AD5940_SPIWriteReg(ADCCON, 0x00000101);
AD5940_SPIWriteReg(DFTCON, 0x00000091);
AD5940_SPIWriteReg(SWCON, 0x00026355); //D5 | P5 | N3 | T6 | T9 0b010 0110 0011 0101 0101
AD5940_SPIWriteReg(ADCCON, 0x00000101); // PGA=1 | HSTIA neg input | HSTIA pos signal
AD5940_SPIWriteReg(DFTCON, 0x00000091); // DFTNUM=2048 | enable hanning window | SINC2
AD5940_SPIWriteReg(SWCON, 0x00026355); // D5 | P5 | N3 | T6 | T9 close
if (instru.gain_lv_hstia < HSRTIA_MAX) {
instru.HSTIAAutoGainEnable = 0;
@@ -70,16 +77,23 @@ static void setEIS_EIS_cali(void)
DAC_outputV(LPVolt);
cali_SetWGAmp(instru.acamp);
AD5940_SPIWriteReg(AFECON, 0x0031CFC0);
AD5940_SPIWriteReg(AFECON, 0x0031CFC0); // en dc DAC buf | HSDAC ref disable | LDO buf current limit enable | en SINC2 |
// DFT hardware accelerator enable | waveform generator enable | HSTIA enable |
// intru amplifier enable | excitation buf enable | ADC conversions enable |
// ADC power enable | HSDAC enable | HP ref enable
//HIGH POWER MODE
AD5940_SPIWriteReg(PMBW, 0x0000000D); //switch to active high power mode
AD5940_SPIWriteReg(PMBW, 0x0000000D); // HS mode | Set cutooff frequency to 250kHz, -3 dB bandwidth
AD5940_SPIWriteReg(CLKSEL, 0x0000);
AD5940_SPIWriteReg(CLKCON0KEY, 0xA815);
AD5940_SPIWriteReg(CLKCON0, 0x0442); //16bit system clock divider //set divider = 2
AD5940_SPIWriteReg(HSOSCCON, 0x00000000); //switch to 32MHz output
AD5940_SPIWriteReg(ADCFILTERCON, 0x00000311);
AD5940_SPIWriteReg(HSDACCON, 0x0000000E); //DAC gain = 2, > 80 kHz
AD5940_SPIWriteReg(CLKCON0KEY, 0xA815); // !!!Write 0xA815 to this register before accessing the CLKCON0 register
AD5940_SPIWriteReg(CLKCON0, 0x0442); //6bit system clock divider //set divider = 2
AD5940_SPIWriteReg(HSOSCCON, 0x00000000); // HP osc select 32MHz output
AD5940_SPIWriteReg(ADCFILTERCON, 0x00000311); // en DFT clk | en DAC wave clk | en SINC2 filter clk | 2 ADC samples used for average function |
// SINC3 filter oversampling rate is 800kSPS |
// SINC2 filter oversampling rate is 178 samples |
// disable average | SINC3 filter enable |
// Bypass 50/60Hz | ADC data rate 800kHz
AD5940_SPIWriteReg(HSDACCON, 0x0000000E); // HSDAC gain = 2, DAC update rate = ACLK/HSDACCON = 32Mhz/7
AD5940_SPIWriteReg(ADCBUFCON, 0x005F3D0F); //recommended
SetEISHIGHZ(0);
}
simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite_version.h
+2 -2
View File
@@ -5,8 +5,8 @@
#define VERSION_DATE_YEAR 22
#define VERSION_DATE_MONTH 11
#define VERSION_DATE_DAY 25
#define VERSION_DATE_HOUR 11
#define VERSION_DATE_MINUTE 43
#define VERSION_DATE_HOUR 14
#define VERSION_DATE_MINUTE 40
// this is NOT the version hash !!
// it's the last version hash