Roy_01
147 lines
4.3 KiB
C
147 lines
4.3 KiB
C
#include "elite_board.h"
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#include "nrf_spim.h"
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "task.h"
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#if (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
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void spim_xfer(uint32_t cs_pin,
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nrf_spim_mode_t spi_mode,
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uint8_t *p_tx_buffer,
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uint16_t tx_buffer_length,
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uint8_t *p_rx_buf,
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uint16_t rx_buffer_length)
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{
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__disable_irq();
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NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
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switch (spi_mode)
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{
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default:
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case NRF_SPIM_MODE_0:
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NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
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(SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
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(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
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break;
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case NRF_SPIM_MODE_1:
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NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
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(SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
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(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
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break;
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case NRF_SPIM_MODE_2:
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NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
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(SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
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(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
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break;
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case NRF_SPIM_MODE_3:
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NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
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(SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
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(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
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break;
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}
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NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
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NRF_SPIM3->TXD.MAXCNT = tx_buffer_length;
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NRF_SPIM3->TXD.PTR = (uint32_t)p_tx_buffer;
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NRF_SPIM3->RXD.MAXCNT = rx_buffer_length;
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NRF_SPIM3->RXD.PTR = (uint32_t)p_rx_buf;
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nrf_gpio_pin_clear(cs_pin);
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NRF_SPIM3->EVENTS_END = 0;
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NRF_SPIM3->TASKS_START = 1;
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do {
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} while (NRF_SPIM3->EVENTS_END == 0);
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nrf_gpio_pin_set(cs_pin);
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__enable_irq();
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}
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void cpg10_io_init(void)
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{
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const uint32_t pel_pins_default_high[] = {
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VA1H_PIN,
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VA2H_PIN,
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VA3H_PIN,
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VA4H_PIN,
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VB1H_PIN,
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VB2H_PIN,
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VB3H_PIN,
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VB4H_PIN,
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LED_R_PIN,
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LED_G_PIN,
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LED_B_PIN
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};
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const uint32_t pel_pins_default_low[] = {
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ADPT0_S4_PIN,
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ADPT0_S3_PIN,
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ADPT0_S2_PIN,
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ADPT0_S1_PIN,
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ADPT_LE_PIN,
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ADPT_CLR_PIN,
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TW_SCKI_0_PIN,
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TW_SCKI_1_PIN,
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HV_EN_PIN,
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ADPT1_S1_PIN,
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VA1L_PIN,
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VA2L_PIN,
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VA3L_PIN,
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VA4L_PIN,
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VB1L_PIN,
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VB2L_PIN,
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VB3L_PIN,
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VB4L_PIN,
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ADPT1_S4_PIN,
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ADPT1_S3_PIN,
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ADPT1_S2_PIN
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};
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for (int i = 0; i < COUNTOF(pel_pins_default_high); i++)
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{
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nrf_gpio_pin_set(pel_pins_default_high[i]);
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nrf_gpio_cfg_output(pel_pins_default_high[i]);
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}
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for (int i = 0; i < COUNTOF(pel_pins_default_low); i++)
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{
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nrf_gpio_pin_clear(pel_pins_default_low[i]);
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nrf_gpio_cfg_output(pel_pins_default_low[i]);
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}
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nrf_gpio_cfg_input(AIN0_PIN, NRF_GPIO_PIN_NOPULL);
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nrf_gpio_cfg_input(AIN1_PIN, NRF_GPIO_PIN_NOPULL);
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// Config spi module
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nrf_gpio_pin_set(CS_MEM_PIN);
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nrf_gpio_cfg_output(CS_MEM_PIN);
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nrf_gpio_pin_clear(SPIM_MOSI_PIN);
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nrf_gpio_cfg_output(SPIM_MOSI_PIN);
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nrf_gpio_pin_clear(SPIM_CLK_PIN);
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nrf_gpio_cfg_output(SPIM_CLK_PIN);
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nrf_gpio_cfg_input(SPIM_MISO_PIN, NRF_GPIO_PIN_NOPULL);
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NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
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NRF_SPIM3->ORC = 0x00000000;
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NRF_SPIM3->FREQUENCY = SPIM_FREQUENCY_FREQUENCY_M32;
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NRF_SPIM3->CSNPOL = SPIM_CSNPOL_CSNPOL_LOW;
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NRF_SPIM3->IFTIMING.CSNDUR = 8;
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NRF_SPIM3->PSEL.CSN = CS_MEM_PIN;
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NRF_SPIM3->PSEL.SCK = SPIM_CLK_PIN;
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NRF_SPIM3->PSEL.MOSI = SPIM_MOSI_PIN;
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NRF_SPIM3->PSEL.MISO = SPIM_MISO_PIN;
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NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
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}
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#endif
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