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1 Commits
| Author | SHA1 | Date | |
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| d550536f4f |
@@ -662,7 +662,7 @@ class CC2650Device(Device):
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elif device_type == 'EISZeroOne':
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i = 0
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request_times = 0
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while i < 13:
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while i < 7:
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try:
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# send
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code = self._encode_instruction(DeviceInstruction.TYP_CIS, DeviceInstruction.CIS_CALI, i)
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@@ -1,7 +1,6 @@
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import abc
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import struct
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import math
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import numpy
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from typing import Optional, TypeVar, Generic, Tuple, Dict, List, AnyStr
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from datetime import datetime
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@@ -1381,27 +1380,12 @@ class EISZeroOneDataDecoder(RecDataDecoder):
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def _decode_cali_coeff(cali_coeff: bytes) -> Optional[List[Tuple[int, int]]]:
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if cali_coeff != b'':
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cali_table = []
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phase_para_a = []
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phase_para_b = []
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hsrtia_a = []
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hsrtia_b = []
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hsrtia_c = []
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hsrtia_d = []
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phase_coeff = []
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phase_offset = []
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# phase_coeff = [[0]*4 for i in range(4)]
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# phase_offset = [[0]*4 for i in range(4)]
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phase_coeff = numpy.zeros([4, 4], dtype = int)
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phase_offset = numpy.zeros([4, 4], dtype = int)
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########################################
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# phase_coeff
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# [[gain0, g1, g2, g3] ----->最高頻
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# [gain0, g1, g2, g3] ----->中頻
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# [gain0, g1, g2, g3] ----->低頻
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# [gain0, g1, g2, g3] ----->最低頻
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# ]
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#######################################
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# print('cali_coeff', cali_coeff)
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cutoff_freq = struct.unpack('>I', cali_coeff[1:5])[0] * 100 #4
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@@ -1412,19 +1396,15 @@ class EISZeroOneDataDecoder(RecDataDecoder):
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# hsrtia_160k = struct.unpack('>I', cali_coeff[8:12])[0] #4
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index = 20
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g = 0
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phase_coeff[0][g] = struct.unpack('>i', cali_coeff[index+1:index+5])[0]
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phase_offset[0][g] = struct.unpack('>i', cali_coeff[index+5:index+9])[0]
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phase_coeff[1][g] = struct.unpack('>i', cali_coeff[index+9:index+13])[0]
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phase_offset[1][g] = struct.unpack('>i', cali_coeff[index+13:index+17])[0]
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for i in range(index, index+16, 8):
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phase_para_a.append(struct.unpack('>i', cali_coeff[i+1:i+5])[0])
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phase_para_b.append(struct.unpack('>i', cali_coeff[i+5:i+9])[0])
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index = 40
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g = 0
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phase_coeff[2][g] = struct.unpack('>i', cali_coeff[index+1:index+5])[0]
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phase_offset[2][g] = struct.unpack('>i', cali_coeff[index+5:index+9])[0]
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phase_coeff[3][g] = struct.unpack('>i', cali_coeff[index+9:index+13])[0]
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phase_offset[3][g] = struct.unpack('>i', cali_coeff[index+13:index+17])[0]
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for i in range(index, index+16, 8):
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phase_para_a.append(struct.unpack('>i', cali_coeff[i+1:i+5])[0])
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phase_para_b.append(struct.unpack('>i', cali_coeff[i+5:i+9])[0])
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#Lv[0] 160k
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index = 60
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hsrtia_a.append(struct.unpack('>i', cali_coeff[index+1:index+5])[0]/1e8)
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@@ -1449,58 +1429,18 @@ class EISZeroOneDataDecoder(RecDataDecoder):
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hsrtia_b.append(struct.unpack('>i', cali_coeff[index+5:index+9])[0]/1e8)
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hsrtia_c.append(struct.unpack('>i', cali_coeff[index+9:index+13])[0]/1e4)
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index = 140
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g = 1
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phase_coeff[0][g] = struct.unpack('>i', cali_coeff[index+1:index+5])[0]
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phase_offset[0][g] = struct.unpack('>i', cali_coeff[index+5:index+9])[0]
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phase_coeff[1][g] = struct.unpack('>i', cali_coeff[index+9:index+13])[0]
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phase_offset[1][g] = struct.unpack('>i', cali_coeff[index+13:index+17])[0]
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index = 160
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g = 1
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phase_coeff[2][g] = struct.unpack('>i', cali_coeff[index+1:index+5])[0]
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phase_offset[2][g] = struct.unpack('>i', cali_coeff[index+5:index+9])[0]
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phase_coeff[3][g] = struct.unpack('>i', cali_coeff[index+9:index+13])[0]
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phase_offset[3][g] = struct.unpack('>i', cali_coeff[index+13:index+17])[0]
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index = 180
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g = 2
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phase_coeff[0][g] = struct.unpack('>i', cali_coeff[index+1:index+5])[0]
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phase_offset[0][g] = struct.unpack('>i', cali_coeff[index+5:index+9])[0]
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phase_coeff[1][g] = struct.unpack('>i', cali_coeff[index+9:index+13])[0]
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phase_offset[1][g] = struct.unpack('>i', cali_coeff[index+13:index+17])[0]
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index = 200
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g = 2
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phase_coeff[2][g] = struct.unpack('>i', cali_coeff[index+1:index+5])[0]
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phase_offset[2][g] = struct.unpack('>i', cali_coeff[index+5:index+9])[0]
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phase_coeff[3][g] = struct.unpack('>i', cali_coeff[index+9:index+13])[0]
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phase_offset[3][g] = struct.unpack('>i', cali_coeff[index+13:index+17])[0]
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index = 220
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g = 3
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phase_coeff[0][g] = struct.unpack('>i', cali_coeff[index+1:index+5])[0]
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phase_offset[0][g] = struct.unpack('>i', cali_coeff[index+5:index+9])[0]
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phase_coeff[1][g] = struct.unpack('>i', cali_coeff[index+9:index+13])[0]
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phase_offset[1][g] = struct.unpack('>i', cali_coeff[index+13:index+17])[0]
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index = 240
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g = 3
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phase_coeff[2][g] = struct.unpack('>i', cali_coeff[index+1:index+5])[0]
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phase_offset[2][g] = struct.unpack('>i', cali_coeff[index+5:index+9])[0]
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phase_coeff[3][g] = struct.unpack('>i', cali_coeff[index+9:index+13])[0]
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phase_offset[3][g] = struct.unpack('>i', cali_coeff[index+13:index+17])[0]
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# hsrtia_a.append(struct.unpack('>I', cali_coeff[index+1:index+5])[0])
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# hsrtia_b.append(struct.unpack('>I', cali_coeff[index+5:index+9])[0]/1e6)
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# hsrtia_c.append(struct.unpack('>I', cali_coeff[index+9:index+13])[0]/1e5)
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# print('cutoff_freq', cutoff_freq)
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# print('hsrtia_a', hsrtia_a)
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# print('hsrtia_b', hsrtia_b)
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# print('hsrtia_c', hsrtia_c)
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# print('phase_coeff')
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# print(phase_coeff)
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# print('phase_offset')
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# print(phase_offset)
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# print('phase_para_a', phase_para_a)
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# print('phase_para_b', phase_para_b)
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cali_table.append((cutoff_freq, phase_coeff, phase_offset, hsrtia_a, hsrtia_b, hsrtia_c, hsrtia_d))
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cali_table.append((cutoff_freq, phase_para_a, phase_para_b, hsrtia_a, hsrtia_b, hsrtia_c, hsrtia_d))
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return cali_table
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else:
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@@ -1550,12 +1490,13 @@ class EISZeroOneDataDecoder(RecDataDecoder):
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return None
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else:
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if self.cali_coeff is not None and self._mode == 0:
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phase_para_a = []
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phase_para_b = []
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hsrtia_a = []
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hsrtia_b = []
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hsrtia_c = []
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hsrtia_d = []
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cutoff_freq, phase_coeff, phase_offset, hsrtia_a, hsrtia_b, hsrtia_c, hsrtia_d = self.cali_coeff[0]
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cutoff_freq, phase_para_a, phase_para_b, hsrtia_a, hsrtia_b, hsrtia_c, hsrtia_d = self.cali_coeff[0]
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voltage_amp = round(self._ac_amp * 800 / 2047) # use UI value
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if (self._freq_start > self._freq_stop):
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self._freq_direction = 0
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@@ -1566,7 +1507,6 @@ class EISZeroOneDataDecoder(RecDataDecoder):
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img = ch1
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real = ch2
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freq = ch3
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fre_idx = 0
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voltage_mag = math.sqrt(img ** 2 + real ** 2) * (1 + freq ** 2 / cutoff_freq ** 2)
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@@ -1589,13 +1529,13 @@ class EISZeroOneDataDecoder(RecDataDecoder):
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raw_phase = math.atan2(img , real) * 180 / math.pi
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if (freq >= 1000000): # 10000 Hz
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fre_idx = 0
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i = 0
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elif (freq >= 10000): # 100 Hz
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fre_idx = 1
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i = 1
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elif (freq >= 1000): # 10 Hz
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fre_idx = 2
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i = 2
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elif (freq >= 1): # 0.01 Hz
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fre_idx = 3
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i = 3
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ideal_raw_phase = phase_coeff[gain][fre_idx] /1e10 * freq + phase_offset[gain][fre_idx] / 1e6
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phase = raw_phase - ideal_raw_phase
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@@ -35,7 +35,7 @@ class MultiExtMemSpiInterface(LowLevelHardwareInterface):
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'_pin_ram_sel_value', '_pin_mem_sel_value', '_pin_mem_req_value',
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'_read_green_times','_read_red_times',
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'_elite_data_len', '_mem_header_len', '_mem_tailer_len', '_single_data_len',
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'_head_wrong_cnt', '_pin_busy_value')
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'_head_wrong_cnt')
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def __init__(self,
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select: Selector,
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@@ -50,11 +50,11 @@ class MultiExtMemSpiInterface(LowLevelHardwareInterface):
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self._single_data_len = self._elite_data_len + self._mem_header_len + self._mem_tailer_len
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# buffer
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self._tx_buffer_header = [0] * 64
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self._tx_buffer_header = [0] * 19
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self._tx_buffer_data = [0] * (self._single_data_len * 10 + 3)
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# memory control pin
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self.pin_busy: Optional[InputPin] = InputPin.get_used(P3Pin.MEM_BZY)
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self.pin_busy = OutputPin.get_used(P3Pin.MEM_BZY, True)
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self.pin_mem_req = OutputPin.get_used(P3Pin.MEM_REQ, False)
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self.pin_mem_sel = OutputPin.get_used(P3Pin.MEM_RST, True) # MEM_RST -> actually which memory board is assign
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self.pin_ram_sel: Optional[InputPin] = InputPin.get_used(P3Pin.MEM_SEL) # MEM_SEL -> actually is RAM_SEL, which RAM is assign
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@@ -62,7 +62,6 @@ class MultiExtMemSpiInterface(LowLevelHardwareInterface):
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self._pin_ram_sel_value = [bool(self.pin_ram_sel) for _ in range(Selector.SIZE)]
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self._pin_mem_sel_value = [bool(self.pin_mem_sel) for _ in range(Selector.SIZE)]
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self._pin_mem_req_value = [bool(self.pin_mem_req) for _ in range(Selector.SIZE)]
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self._pin_busy_value = [bool(self.pin_busy) for _ in range(Selector.SIZE)]
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self._read_green_times = 0
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self._read_red_times = 0
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@@ -99,14 +98,6 @@ class MultiExtMemSpiInterface(LowLevelHardwareInterface):
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self._pin_ram_sel_value[channel] = True
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return self._pin_ram_sel_value[channel]
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def get_pin_busy(self):
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channel = self.select
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if self.pin_busy.input() == 0:
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self._pin_busy_value[channel] = False
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else:
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self._pin_busy_value[channel] = True
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return self._pin_busy_value[channel]
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@property
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def select(self) -> int:
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return self._selector.channel
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@@ -225,9 +216,7 @@ class MultiExtMemSpiInterface(LowLevelHardwareInterface):
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return
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def recv_memory(self, device: int) -> Optional[bytes]:
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# self.pin_busy.output(False)
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print('mem_req==ram_sel,[', self._pin_mem_req_value[device], ',', self._pin_ram_sel_value[device], ']')
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self.pin_busy.output(False)
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rx = []
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@@ -311,9 +300,6 @@ class MultiExtMemSpiInterface(LowLevelHardwareInterface):
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print("green data print:", data, device, datetime.now())
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return None
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# print('data=', list(data))
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print('Ram:', data[62])
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if (length >= 4000):
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flag_print = True
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print("green data: big length:", length)
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@@ -429,9 +415,9 @@ class MultiExtMemSpiInterface(LowLevelHardwareInterface):
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except BaseException as e:
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print(e)
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# finally:
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# # print("\n")
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# self.pin_busy.output(True)
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finally:
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# print("\n")
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self.pin_busy.output(True)
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return bytes(rx)
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@@ -646,7 +646,6 @@ class DataServer(SocketServer, DataAPI):
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def whether_to_record(self, device):
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# if user click "start", return True; if user click "stop", return False;
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if device in self._configurations.keys() and self._configurations[device] is not None:
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# print(self._configurations.keys(), ',', device, datetime.now())
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return True
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else:
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return False
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@@ -655,9 +654,6 @@ class DataServer(SocketServer, DataAPI):
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ret = False
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sync = self.get_spi_obj()
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busy = sync.get_pin_busy()
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print('pin_busy=', busy, device, datetime.now())
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if sync.get_pin_mem_req() == sync.get_pin_ram_sel():
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spi_data = sync.recv_memory(device)
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signal = sync.get_pin_mem_req()
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@@ -666,7 +662,6 @@ class DataServer(SocketServer, DataAPI):
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else:
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data = None
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print('data=None, mem_req!=ram_sel, [', sync.get_pin_mem_req(), ', ', sync.get_pin_ram_sel(), ']', device, datetime.now())
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if data is not None:
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if self._configurations.get(device, None) != None:
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@@ -71,7 +71,7 @@
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"description": "DPV current recording period start",
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"record_meta": true,
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"initial": [
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13333333,
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13422819,
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7
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],
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"domain": {
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Reference in New Issue
Block a user