From fc5cebe638e0fd65b8561caa0a9142cf60d05b4c Mon Sep 17 00:00:00 2001 From: YiChin Date: Fri, 22 Nov 2019 17:22:32 +0800 Subject: [PATCH 1/2] Merge branch 'Elite_OBJ_Version' of C:\ti with conflicts. --- .../cc26xx/app/headstage/neu/headstage_pin.h | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_pin.h diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_pin.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_pin.h new file mode 100644 index 000000000..49ee5c733 --- /dev/null +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_pin.h @@ -0,0 +1,89 @@ +/* Copyright (c) 2019. BioPro. Scientific. + */ +#ifndef HEADSTAGE_PIN_NEU_H +#define HEADSTAGE_PIN_NEU_H + +#if defined(CC2650_LAUNCHXL) + +// clang-format off +#define PIN_RESET IOID_0 // SPI1 to receive LSK +#define PIN_EN_ADC_SPI_CLK IOID_1 // SPI1 clock +#define PIN_DC_DC IOID_2 // STI select need +#define PIN_BATT_HALF IOID_3 // +#define PIN_AMP_VCK IOID_4 // +#define PIN_LED_SDI IOID_5 // +#define PIN_LED_CLK IOID_8 // +#define PIN_STI_CLK IOID_9 // +#define PIN_SPI_MISO IOID_10 // +#define PIN_SPI_MOSI IOID_11 // +#define PIN_SPI_CS IOID_12 // +#define PIN_SPI_CLK IOID_13 // +#define PIN_SYS_CLK IOID_14 // +#define GLED IOID_7 +#define RLED IOID_6 + +// clang-format on + +#elif defined(BOOSTXL_CC2650MA) + +// clang-format off + +#define PIN_RESET IOID_0 // SPI1 to receive LSK +#define PIN_EN_ADC_SPI_CLK IOID_1 // SPI1 clock +#define PIN_DC_DC IOID_2 // STI select need +#define PIN_BATT_HALF IOID_3 // +#define PIN_AMP_VCK IOID_4 // +#define PIN_LED_SDI IOID_7 // +#define PIN_LED_CLK IOID_8 // +#define PIN_STI_CLK IOID_9 // +#define PIN_SPI_MISO IOID_10 // +#define PIN_SPI_MOSI IOID_11 // +#define PIN_SPI_CS IOID_12 // +#define PIN_SPI_CLK IOID_13 // +#define PIN_SYS_CLK IOID_14 // + +// clang-format on +#endif +/* + * SPI0 interface with DBS chip 2.0 + */ +#define Board_SPI0_MISO PIN_SPI_MISO +#define Board_SPI0_MOSI PIN_SPI_MOSI +#define Board_SPI0_CLK PIN_SPI_CLK +#define Board_SPI0_CSN PIN_SPI_CS + +/* + * SPI1 interface work with LED + */ + +#define Board_SPI1_MISO PIN_UNASSIGNED +#define Board_SPI1_MOSI PIN_LED_SDI +#define Board_SPI1_CLK PIN_LED_CLK +#define Board_SPI1_CSN PIN_UNASSIGNED + +/* Power Management Board */ +#define Board_SRDY Board_BP_Pin_J2_19 +#define Board_MRDY Board_BP_Pin_J1_2 + +/* PWM outputs */ +#define Board_PWMPIN0 PIN_AMP_VCK +#define Board_PWMPIN1 PIN_UNASSIGNED +#define Board_PWMPIN2 PIN_SYS_CLK +#define Board_PWMPIN3 PIN_UNASSIGNED +#define Board_PWMPIN4 PIN_UNASSIGNED +#define Board_PWMPIN5 PIN_UNASSIGNED +#define Board_PWMPIN6 PIN_UNASSIGNED +#define Board_PWMPIN7 PIN_UNASSIGNED + +static PIN_Config headstage_pin_configuration[] = { // + PIN_RESET | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, + PIN_EN_ADC_SPI_CLK | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, + PIN_DC_DC | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, + PIN_BATT_HALF | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, + PIN_STI_CLK | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, +// RLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, +// GLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, + // + PIN_TERMINATE}; + +#endif // HEADSTAGE_PIN_UNI_H From b91fdc6d3f27dba70b6b385e5f880eddd7257bad Mon Sep 17 00:00:00 2001 From: YiChin Date: Wed, 27 Nov 2019 12:45:25 +0800 Subject: [PATCH 2/2] delete neu --- .../cc26xx/app/headstage/neu/headstage_pin.h | 89 ------------------- 1 file changed, 89 deletions(-) delete mode 100644 simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_pin.h diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_pin.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_pin.h deleted file mode 100644 index 49ee5c733..000000000 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/neu/headstage_pin.h +++ /dev/null @@ -1,89 +0,0 @@ -/* Copyright (c) 2019. BioPro. Scientific. - */ -#ifndef HEADSTAGE_PIN_NEU_H -#define HEADSTAGE_PIN_NEU_H - -#if defined(CC2650_LAUNCHXL) - -// clang-format off -#define PIN_RESET IOID_0 // SPI1 to receive LSK -#define PIN_EN_ADC_SPI_CLK IOID_1 // SPI1 clock -#define PIN_DC_DC IOID_2 // STI select need -#define PIN_BATT_HALF IOID_3 // -#define PIN_AMP_VCK IOID_4 // -#define PIN_LED_SDI IOID_5 // -#define PIN_LED_CLK IOID_8 // -#define PIN_STI_CLK IOID_9 // -#define PIN_SPI_MISO IOID_10 // -#define PIN_SPI_MOSI IOID_11 // -#define PIN_SPI_CS IOID_12 // -#define PIN_SPI_CLK IOID_13 // -#define PIN_SYS_CLK IOID_14 // -#define GLED IOID_7 -#define RLED IOID_6 - -// clang-format on - -#elif defined(BOOSTXL_CC2650MA) - -// clang-format off - -#define PIN_RESET IOID_0 // SPI1 to receive LSK -#define PIN_EN_ADC_SPI_CLK IOID_1 // SPI1 clock -#define PIN_DC_DC IOID_2 // STI select need -#define PIN_BATT_HALF IOID_3 // -#define PIN_AMP_VCK IOID_4 // -#define PIN_LED_SDI IOID_7 // -#define PIN_LED_CLK IOID_8 // -#define PIN_STI_CLK IOID_9 // -#define PIN_SPI_MISO IOID_10 // -#define PIN_SPI_MOSI IOID_11 // -#define PIN_SPI_CS IOID_12 // -#define PIN_SPI_CLK IOID_13 // -#define PIN_SYS_CLK IOID_14 // - -// clang-format on -#endif -/* - * SPI0 interface with DBS chip 2.0 - */ -#define Board_SPI0_MISO PIN_SPI_MISO -#define Board_SPI0_MOSI PIN_SPI_MOSI -#define Board_SPI0_CLK PIN_SPI_CLK -#define Board_SPI0_CSN PIN_SPI_CS - -/* - * SPI1 interface work with LED - */ - -#define Board_SPI1_MISO PIN_UNASSIGNED -#define Board_SPI1_MOSI PIN_LED_SDI -#define Board_SPI1_CLK PIN_LED_CLK -#define Board_SPI1_CSN PIN_UNASSIGNED - -/* Power Management Board */ -#define Board_SRDY Board_BP_Pin_J2_19 -#define Board_MRDY Board_BP_Pin_J1_2 - -/* PWM outputs */ -#define Board_PWMPIN0 PIN_AMP_VCK -#define Board_PWMPIN1 PIN_UNASSIGNED -#define Board_PWMPIN2 PIN_SYS_CLK -#define Board_PWMPIN3 PIN_UNASSIGNED -#define Board_PWMPIN4 PIN_UNASSIGNED -#define Board_PWMPIN5 PIN_UNASSIGNED -#define Board_PWMPIN6 PIN_UNASSIGNED -#define Board_PWMPIN7 PIN_UNASSIGNED - -static PIN_Config headstage_pin_configuration[] = { // - PIN_RESET | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, - PIN_EN_ADC_SPI_CLK | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, - PIN_DC_DC | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, - PIN_BATT_HALF | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, - PIN_STI_CLK | PIN_INPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, -// RLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, -// GLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, - // - PIN_TERMINATE}; - -#endif // HEADSTAGE_PIN_UNI_H