diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite.json b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite.json
index 2f635fe00..4465e1114 100644
--- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite.json
+++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite.json
@@ -106,7 +106,7 @@
     "ADCTEST": {
       "type": "RIS",
       "data": [
-        "2b20;4b<ADC_detect<;4b0001"
+        "2b90;4b<ADC_detect<;4b0001"
       ]
     }
   }
diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h
index 6e485b6f0..ec833e25c 100644
--- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h
+++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h
@@ -736,8 +736,9 @@ static bool TurnOnElite(uint8_t key);
  ==== instruction update function  ====
  ====================================*/
 
-#define CIS 0x01
 #define RIS 0x02
+#define CIS 0x01
+
 #define VIS 0x03
 
 // callback for headstage
@@ -813,126 +814,143 @@ static void update_ZM_instruction(uint8 *ins) {
     switch (ins_type) {
         /***  These are real instruction  ***/
 
-        case IVCurve:{
-            INSTRUCTION.eliteFxn = IVCurve;
-            PeriodicEvent = true;
+        case CIS:{
 
-            if(ins[1] | ins[2]){
-                VoltOrigin = ((uint16_t) (ins[1]) << 8) | (uint16_t) (ins[2]);
-            }
-            if(ins[3] | ins[4]){
-                VoltFinal = ((uint16_t) (ins[3]) << 8) | (uint16_t) (ins[4]);
-            }
-
-            if(ins[5]){
-                Step = ins[5];
-            }
-            if(ins[6]){
-                StepTime = ins[6];
-            }
-            break;
         }
 
-        case cyclicVoltammetry:{
-            INSTRUCTION.eliteFxn = cyclicVoltammetry;
-            PeriodicEvent = true;
-
-            if(ins[1] | ins[2]){
-                VoltOrigin = ((uint16_t) (ins[1]) << 8) | (uint16_t) (ins[2]);
-            }
-            if(ins[3] | ins[4]){
-                VoltFinal = ((uint16_t) (ins[3]) << 8) | (uint16_t) (ins[4]);
-            }
-
-            if(ins[5]){
-                Step = ins[5];
-            }
-            if(ins[6]){
-                StepTime = ins[6];
-            }
-            break;
-        }
-
-        case fxnGen:{
-            INSTRUCTION.eliteFxn = fxnGen;
-            DAC_outputV(ins[1], ins[2], ins[3]);
-            break;
-        }
-
-        // impedance test
-        case ZTCurve: {
-            INSTRUCTION.eliteFxn = ZTCurve;
-
-            break;
-        }
-
-        case VTCurve:{
-            INSTRUCTION.eliteFxn = VTCurve;
-            VT_Plot();
-            break;
-        }
-
-        case ITCurve:{
-            INSTRUCTION.eliteFxn = ITCurve;
-            IT_Plot();
-            break;
-        }
-        /*** end of real instruction ***/
-
-        /*** These are virtual instruction ***/
-        // reset all variables
-        case INS_TYPE_VIS_RST:{
-            INSTRUCTION.eliteFxn = INS_TYPE_VIS_RST;
-            reset();
-
-            break;
-        }
-            /*** end of virtual instruction ***/
-
-            /*** These are test instruction ***/
-
-        case RAMP_GENERATE:{
-            INSTRUCTION.eliteFxn = RAMP_GENERATE;
-
-
-            break;
-         }
-
-        case ADCTEST:{
-            INSTRUCTION.eliteFxn = ADCTEST;
+        case RIS:{
             switch(ins[1]){
-                //  AINp is AIN0; AINn is GND
-                case 0 :{
-                    ADC_write(0xC1);
-                    break;
-                }
 
-                //  AINp is AIN1; AINn is GND
-                case 1 :{
-                    ADC_write(0xD1);
-                    break;
-                }
-
-                //  AINp is AIN2; AINn is GND
-                case 2 :{
-                    ADC_write(0xE1);
-                    break;
-                }
-
-                //  AINp is AIN3; AINn is GND
-                case 3 :{
-                    ADC_write(0xF1);
-                    break;
-                }
-                default :{
+                default:{
+                    /** **/
                     break;
                 }
             }
-
-            CPUdelay(16000);
-            ADC_read();
-            break;
         }
+
+        case VIS:{
+
+        }
+            case IVCurve:{
+                INSTRUCTION.eliteFxn = IVCurve;
+                PeriodicEvent = true;
+
+                if(ins[1] | ins[2]){
+                    VoltOrigin = ((uint16_t) (ins[1]) << 8) | (uint16_t) (ins[2]);
+                }
+                if(ins[3] | ins[4]){
+                    VoltFinal = ((uint16_t) (ins[3]) << 8) | (uint16_t) (ins[4]);
+                }
+
+                if(ins[5]){
+                    Step = ins[5];
+                }
+                if(ins[6]){
+                    StepTime = ins[6];
+                }
+                break;
+            }
+
+            case cyclicVoltammetry:{
+                INSTRUCTION.eliteFxn = cyclicVoltammetry;
+                PeriodicEvent = true;
+
+                if(ins[1] | ins[2]){
+                    VoltOrigin = ((uint16_t) (ins[1]) << 8) | (uint16_t) (ins[2]);
+                }
+                if(ins[3] | ins[4]){
+                    VoltFinal = ((uint16_t) (ins[3]) << 8) | (uint16_t) (ins[4]);
+                }
+
+                if(ins[5]){
+                    Step = ins[5];
+                }
+                if(ins[6]){
+                    StepTime = ins[6];
+                }
+                break;
+            }
+
+            case fxnGen:{
+                INSTRUCTION.eliteFxn = fxnGen;
+                DAC_outputV(ins[1], ins[2], ins[3]);
+                break;
+            }
+
+            // impedance test
+            case ZTCurve: {
+                INSTRUCTION.eliteFxn = ZTCurve;
+
+                break;
+            }
+
+            case VTCurve:{
+                INSTRUCTION.eliteFxn = VTCurve;
+                VT_Plot();
+                break;
+            }
+
+            case ITCurve:{
+                INSTRUCTION.eliteFxn = ITCurve;
+                IT_Plot();
+                break;
+            }
+            /*** end of real instruction ***/
+
+            /*** These are virtual instruction ***/
+            // reset all variables
+            case INS_TYPE_VIS_RST:{
+                INSTRUCTION.eliteFxn = INS_TYPE_VIS_RST;
+                reset();
+
+                break;
+            }
+                /*** end of virtual instruction ***/
+
+                /*** These are test instruction ***/
+
+            case RAMP_GENERATE:{
+                INSTRUCTION.eliteFxn = RAMP_GENERATE;
+
+
+                break;
+             }
+
+            case ADCTEST:{
+                INSTRUCTION.eliteFxn = ADCTEST;
+                switch(ins[1]){
+                    //  AINp is AIN0; AINn is GND
+                    case 0 :{
+                        ADC_write(0xC1);
+                        break;
+                    }
+
+                    //  AINp is AIN1; AINn is GND
+                    case 1 :{
+                        ADC_write(0xD1);
+                        break;
+                    }
+
+                    //  AINp is AIN2; AINn is GND
+                    case 2 :{
+                        ADC_write(0xE1);
+                        break;
+                    }
+
+                    //  AINp is AIN3; AINn is GND
+                    case 3 :{
+                        ADC_write(0xF1);
+                        break;
+                    }
+                    default :{
+                        break;
+                    }
+                }
+
+                CPUdelay(16000);
+                ADC_read();
+                break;
+            }
         /*** end of test instruction ***/
         default:{
             // unknown instruction