From aeee554ac2b72ba9dc18e6dfb596f7c0e4077f8f Mon Sep 17 00:00:00 2001 From: Taylor Liao Date: Thu, 2 Sep 2021 16:36:28 +0800 Subject: [PATCH] Fixing CV --- .../cc26xx/app/headstage/AD5940.h | 177 ++++++++++-------- .../cc26xx/app/headstage/EliteADC.h | 87 ++++++--- .../cc26xx/app/headstage/EliteDAC.h | 36 ++-- .../cc26xx/app/headstage/Elite_mode_ADC_DAC.h | 10 +- .../cc26xx/app/headstage/eis_cali_table.h | 4 +- .../cc26xx/app/headstage/headstage.h | 13 +- 6 files changed, 202 insertions(+), 125 deletions(-) diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h index 5141092d8..65fe881e4 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h @@ -95,84 +95,80 @@ static void setEIS_EIS (void) select_REG(0x300C); w32_REG(0x00000002); //DFT result IRQ enable - - -// select_REG(SWCON); //200C -// w32_REG(0x00026905); //0b0100110100100000101 -// -// select_REG(LPDACCON0); //2128 //DC on -// w32_REG(0b0000001); -// select_REG(LPDACSW0); //2124 //operation -// w32_REG(0b101011); -// select_REG(LPDACDAT0); //2120 //output Vout -// w32_REG(0x00000799); // was 0x0 -// -// select_REG(DE0RESCON); //20F8 //DE0's gain -// w32_REG(0x00000068); -// -// select_REG(ADCCON); //21A8 -// w32_REG(0x00000101); -// select_REG(DFTCON); //20D0 -// w32_REG(0x000000C1); -// select_REG(ADCFILTERCON); //2044 -// w32_REG(0x000000D0); -// -// SetWGAmp(instru.acamp); -// -// select_REG(AFECON); //2000 -// w32_REG(0x0031CFC0); -// select_REG(0x22F0); //PWMB -// w32_REG(0x0000000D); //switch to active high power mode -// select_REG(0x0414); //CLKSEL -// w32_REG(0x00000000); //ADC and system clock both internal high frequency oscillator clock -// select_REG(0x0408); //16bit system clock divider -// w16_REG(0x0442); //set divider = 2 -// select_REG(0x20BC); //HSOSCCON -// w32_REG(0x00000030); //switch to 32MHz output -// select_REG(0x2044); //ADCFILTERCON -// w32_REG(0x000000D0); //ADC data rate = 1.6MHz, 50/60 Hz main rejection -// select_REG(0x2010); //HSDACCON -// w32_REG(0x0000000E); //DAC gain = 2, > 80 kHz -// select_REG(0x238C); //ADCBUFCON -// w32_REG(0x005F3D0F); //recommended } static void setEIS_CV (void) { - //Clock and Ref - select_REG(CLKSEL); //CLKSEL + //Clock and Ref + select_REG(0x0414); //CLKSEL w16_REG(0x0); - select_REG(HSOSCCON); //HSOSCCON + select_REG(0x20BC); //HSOSCCON w32_REG(0x00000004); //16 MHz output select_REG(0x2180); //BUFSENCON w32_REG(0x00000037); //0b110110 //Configure LPDAC LPTIA - select_REG(LPREFBUFCON); //LPREFBUFCON + select_REG(0x2050); //LPREFBUFCON w32_REG(0x0); //enable lpref and lp 2.5V buffer - select_REG(LPDACSW0); //LPDACSW0 + select_REG(0x2124); //LPDACSW0 w32_REG(0x0000003E); - select_REG(LPTIASW0); //LPTIASW0 + select_REG(0x20E4); //LPTIASW0 w32_REG(0x00008034); // SW2 | SW4 | SW5 - select_REG(LPTIACON0); //LPTIACON0 + select_REG(0x20EC); //LPTIACON0 w32_REG(0x00000038); //RF 0 | RTIA 200R | Rload 0 | High Current Mode - select_REG(LPDACCON0); //LPDACCON0 + select_REG(0x2128); //LPDACCON0 w32_REG(0x00000001); //Configure ADC | ADCDAT (0x2074) - select_REG(ADCCON); //ADCCON + select_REG(0x21A8); //ADCCON w32_REG(0x00001021); //PGA = 1 | VZERO | LPTIA_OUT - select_REG(ADCFILTERCON); //ADCFILTERCON - w32_REG(0x00014091); //AVR 4 | Sinc3 En | OSR 5 + select_REG(0x2044); //ADCFILTERCON + w32_REG(0x00006091); //AVR 4 | Sinc3 En | OSR 2 // w32_REG(0x00012011); //Disable avr | sinc3 enable | osr 2 - select_REG(DFTCON); //DFTCON - w32_REG(0x00100031); //sinc3 + average input for DFT | DFTNUM 32 + select_REG(0x20D0); //DFTCON + w32_REG(0x001000C1); //sinc3 + average input for DFT | dftnum max - //AFE and PMWB - select_REG(AFECON); //AFECON + //AFE and PWMB + select_REG(0x2000); //AFECON w32_REG(0x00098780); //ADC on //0b10011000011110000000 - select_REG(PMBW); //PMWB + select_REG(0x22F0); //PWMB w32_REG(0x00000005);//fc 50kHz, low power mode + + +// //Clock and Ref +// select_REG(CLKSEL); //CLKSEL +// w16_REG(0x0); +// select_REG(HSOSCCON); //HSOSCCON +// w32_REG(0x00000004); //16 MHz output +// select_REG(0x2180); //BUFSENCON +// w32_REG(0x00000037); //0b110110 +// +// //Configure LPDAC LPTIA +// select_REG(LPREFBUFCON); //LPREFBUFCON +// w32_REG(0x0); //enable lpref and lp 2.5V buffer +// select_REG(LPDACSW0); //LPDACSW0 +// w32_REG(0x0000003E); +// select_REG(LPTIASW0); //LPTIASW0 +// w32_REG(0x00008034); // SW2 | SW4 | SW5 +// select_REG(LPTIACON0); //LPTIACON0 +// w32_REG(0x00000038); //RF 0 | RTIA 200R | Rload 0 | High Current Mode +// select_REG(LPDACCON0); //LPDACCON0 +// w32_REG(0x00000001); +// +// //Configure ADC | ADCDAT (0x2074) +// select_REG(ADCCON); //ADCCON +// w32_REG(0x00001021); //PGA = 1 | VZERO | LPTIA_OUT +// select_REG(ADCFILTERCON); //ADCFILTERCON +// w32_REG(0x00014091); //AVR 4 | Sinc3 En | OSR 5 +//// w32_REG(0x00012011); //Disable avr | sinc3 enable | osr 2 +// select_REG(DFTCON); //DFTCON +// w32_REG(0x00100031); //sinc3 + average input for DFT | DFTNUM 32 +// +// //AFE and PMWB +// select_REG(AFECON); //AFECON +// w32_REG(0x00098780); //ADC on //0b10011000011110000000 +// select_REG(PMBW); //PMWB +// w32_REG(0x00000005);//fc 50kHz, low power mode } static void HS_cali_config (void) @@ -218,40 +214,75 @@ static void HS_cali_config (void) } static void LP_cali_config (void) { - //Clock and Ref - select_REG(CLKSEL); //CLKSEL + //Clock and Ref + select_REG(0x0414); //CLKSEL w16_REG(0x0); - select_REG(HSOSCCON); //HSOSCCON + select_REG(0x20BC); //HSOSCCON w32_REG(0x00000004); //16 MHz output select_REG(0x2180); //BUFSENCON w32_REG(0x00000037); //0b110110 //Configure LPDAC LPTIA -// select_REG(SWCON); -// w32_REG(0x0000FFFF); - select_REG(LPREFBUFCON); //LPREFBUFCON + select_REG(0x2050); //LPREFBUFCON w32_REG(0x0); //enable lpref and lp 2.5V buffer - select_REG(LPDACSW0); //LPDACSW0 + select_REG(0x2124); //LPDACSW0 w32_REG(0x0000003E); - select_REG(LPTIASW0); //LPTIASW0 + select_REG(0x20E4); //LPTIASW0 w32_REG(0x00008034); // SW2 | SW4 | SW5 - select_REG(LPDACCON0); //LPDACCON0 + select_REG(0x20EC); //LPTIACON0 + w32_REG(0x00000038); //RF 0 | RTIA 200R | Rload 0 | High Current Mode + select_REG(0x2128); //LPDACCON0 w32_REG(0x00000001); //Configure ADC | ADCDAT (0x2074) - select_REG(ADCCON); //ADCCON + select_REG(0x21A8); //ADCCON w32_REG(0x00001021); //PGA = 1 | VZERO | LPTIA_OUT - select_REG(ADCFILTERCON); //ADCFILTERCON - w32_REG(0x00014091); //AVR 4 | Sinc3 En | OSR 2 + select_REG(0x2044); //ADCFILTERCON + w32_REG(0x00006091); //AVR 4 | Sinc3 En | OSR 2 // w32_REG(0x00012011); //Disable avr | sinc3 enable | osr 2 - select_REG(DFTCON); //DFTCON - w32_REG(0x00100031); //sinc3 + average input for DFT | dftnum max + select_REG(0x20D0); //DFTCON + w32_REG(0x001000C1); //sinc3 + average input for DFT | dftnum max - //AFE and PMWB - select_REG(AFECON); //AFECON + //AFE and PWMB + select_REG(0x2000); //AFECON w32_REG(0x00098780); //ADC on //0b10011000011110000000 - select_REG(PMBW); //PMWB + select_REG(0x22F0); //PWMB w32_REG(0x00000005);//fc 50kHz, low power mode + +// //Clock and Ref +// select_REG(CLKSEL); //CLKSEL +// w16_REG(0x0); +// select_REG(HSOSCCON); //HSOSCCON +// w32_REG(0x00000004); //16 MHz output +// select_REG(0x2180); //BUFSENCON +// w32_REG(0x00000037); //0b110110 +// +// //Configure LPDAC LPTIA +//// select_REG(SWCON); +//// w32_REG(0x0000FFFF); +// select_REG(LPREFBUFCON); //LPREFBUFCON +// w32_REG(0x0); //enable lpref and lp 2.5V buffer +// select_REG(LPDACSW0); //LPDACSW0 +// w32_REG(0x0000003E); +// select_REG(LPTIASW0); //LPTIASW0 +// w32_REG(0x00008034); // SW2 | SW4 | SW5 +// select_REG(LPDACCON0); //LPDACCON0 +// w32_REG(0x00000001); +// +// //Configure ADC | ADCDAT (0x2074) +// select_REG(ADCCON); //ADCCON +// w32_REG(0x00001021); //PGA = 1 | VZERO | LPTIA_OUT +// select_REG(ADCFILTERCON); //ADCFILTERCON +// w32_REG(0x00014091); //AVR 4 | Sinc3 En | OSR 2 +//// w32_REG(0x00012011); //Disable avr | sinc3 enable | osr 2 +// select_REG(DFTCON); //DFTCON +// w32_REG(0x00100031); //sinc3 + average input for DFT | dftnum max +// +// //AFE and PMWB +// select_REG(AFECON); //AFECON +// w32_REG(0x00098780); //ADC on //0b10011000011110000000 +// select_REG(PMBW); //PMWB +// w32_REG(0x00000005);//fc 50kHz, low power mode } #endif diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h index 331c02e2a..cbdd1f208 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h @@ -224,29 +224,57 @@ static void LPTIAGainCtrl(uint8_t LPTIALevel){ LPTIACON0[12:10] = RLOAD, set at 0R; LPTIACON0[9:5] = RTIA; LPTIACON0[4:3] = IBOOST, High current mode; */ +// uint32_t code; +// uint8_t data; +// +// code = 0x00000038; +// +// if (LPTIALevel == LPRTIA_512K) { +// data = 0x1A; //512k +// } +// else if (LPTIALevel == LPRTIA_12K) { +// data = 0x09; //12K +// } +// else if (LPTIALevel == LPRTIA_4K) { +// data = 0x05; //4K +// } +// else if (LPTIALevel == LPRTIA_200R) { +// data = 0x01; //200R +// } +// else if (LPTIALevel == LPRTIA_GAIN_AUTO) { +// data = 0x01; +// } +// +// code = (code) | ((((uint32_t)(data)) << 5) & 0x000003E0); +// select_REG(LPTIACON0); //20EC +// w32_REG(code); uint32_t code; - uint8_t data; + uint16_t mask; + uint16_t data; - code = 0x00002018; + mask = (31 << 5); //mask bit[9:5] - if (LPTIALevel == LPRTIA_512K) { - data = 0x1A; //512k - } - else if (LPTIALevel == LPRTIA_12K) { - data = 0x09; //12K + select_REG(0x20EC); //LPTIACON0 + code = r32_REG(); + + if (LPTIALevel == LPRTIA_200R) { + data = 1; //200R } else if (LPTIALevel == LPRTIA_4K) { - data = 0x05; //4K + data = 5; //4K + } + else if (LPTIALevel == LPRTIA_12K) { + data = 9; //12K + } + else if (LPTIALevel == LPRTIA_512K) { + data = 26; //512K } else if (LPTIALevel == LPRTIA_200R) { - data = 0x01; //200R - } - else if (LPTIALevel == LPRTIA_GAIN_AUTO) { - data = 0x01; + data = 1; } - code = (code) | ((((uint32_t)(data)) << 5) & 0x000003E0); - select_REG(LPTIACON0); //LPTIACON0 + code = (code & (~mask)) | (data << 5); + select_REG(0x20EC); //LPTIACON0 w32_REG(code); record_flag = false; @@ -692,25 +720,28 @@ static void AutoGainChangeVin(int32_t RealVin){ //EIS Function// static int32_t read_LPTIA_Iin(){ static int32_t dftdat, Iin; - dftdat = neg_18bit(ReadRealZ()) + 4140; + dftdat = neg_18bit(ReadRealZ()); - if (instru.ADCGainLv == 0) { - Iin = -(0.867 * dftdat * 1000 + 256) / 512.1 / 0.033; +// if (instru.ADCGainLv == 0) { +// Iin = -(0.867 * dftdat * 1000 + 256) / 512.1 / 0.033; +// res = rawIin / 0.033; } - else if (instru.ADCGainLv == 1) { - Iin = - ((dftdat + dftdat * 0.086) * 1000 + 6)/ 12.1 / 1.75; +// else if (instru.ADCGainLv == 1) { +// Iin = - ((dftdat + dftdat * 0.086) * 1000 + 6)/ 12.1 / 1.75; +// res = rawIin / 1.75; } - else if (instru.ADCGainLv == 2) { - Iin = - ((dftdat + dftdat * 0.04) * 1000 + 2) / 4.1 / 5.43; - } - else if (instru.ADCGainLv == 3 || instru.ADCGainLv == 4) { - Iin = - (dftdat * 1000 + 105) / 210 / 0.102; +// else if (instru.ADCGainLv == 2) { +// Iin = - ((dftdat + dftdat * 0.04) * 1000 + 2) / 4.1 / 5.43; +// res = rawIin / 5.43; } +// else if (instru.ADCGainLv == 3 || instru.ADCGainLv == 4) { +// Iin = - (dftdat * 1000 + 105) / 210 / 0.102; +// Iin = rawIin / 0.102; +// } - InputNotify(NOTIFY_CURRENT, dftdat); - InputNotify(NOTIFY_VOLT, Iin); - InputNotify(NOTIFY_IMPEDANCE, instru.ADCGainLv); - return Iin; +// InputNotify(NOTIFY_CURRENT, dftdat); +// InputNotify(NOTIFY_IMPEDANCE, instru.ADCGainLv); + return dftdat; } static uint32_t read_HSTIA_Iin(){ diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h index b729b031b..6802f1ba0 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h @@ -62,30 +62,38 @@ static bool DACReset; #define VZERO_LSB 6875008 //VBIAS_LSB * 64 #define DAC12BIT_LSB 107422 -struct eis_dac_volt { - uint32_t vb; - uint32_t vz; - uint32_t vzcode; - uint32_t vbcode; - uint32_t DACOutCode; -} eis_dac_volt = {0}; +//struct eis_dac_volt { +// uint32_t vb; +// uint32_t vz; +// uint32_t vzcode; +// uint32_t vbcode; +// uint32_t DACOutCode; +//} eis_dac_volt = {0}; static void DAC_outputV(int32_t voltLV) { // LPDAC output, voltLV = Vbias-Vzero static int32_t vztemp; + static uint32_t vb, vz, vzcode, vbcode, DACOutCode = 0; + void *wm = wm_get(); - vztemp = (-0.45 * voltLV) + 249000000; + vztemp = (-45 * voltLV + 50) / 100 + 249000000; if (voltLV < 0) { vztemp -= DAC12BIT_LSB; } - eis_dac_volt.vzcode = (vztemp - 40000000 + VZERO_LSB / 2) / VZERO_LSB; - eis_dac_volt.vz = eis_dac_volt.vzcode * VZERO_LSB + 40000000; + vzcode = (vztemp - 40000000 + VZERO_LSB / 2) / VZERO_LSB; + vz = vzcode * VZERO_LSB + 40000000; - eis_dac_volt.vb = voltLV + eis_dac_volt.vz; - eis_dac_volt.vbcode = ((eis_dac_volt.vb - 40000000 + VBIAS_LSB / 2) / VBIAS_LSB); - eis_dac_volt.DACOutCode = (0x0003FFFF & ((eis_dac_volt.vzcode << 12) + eis_dac_volt.vbcode)); + vb = voltLV + vz; + vbcode = ((vb - 40000000 + VBIAS_LSB / 2) / VBIAS_LSB); + DACOutCode = (0x0003FFFF & ((vzcode << 12) + vbcode)); + + MEAS_VOUT(wm) = vb - vz; select_REG(LPDACDAT0); - w32_REG(eis_dac_volt.DACOutCode); + w32_REG(DACOutCode); + + InputNotify(NOTIFY_VOLT, vz); + InputNotify(NOTIFY_CURRENT, vb); + InputNotify(NOTIFY_IMPEDANCE, MEAS_VOUT(wm)); } static uint32_t DAC_outputF(uint32_t freq) { diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite_mode_ADC_DAC.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite_mode_ADC_DAC.h index 843f4918c..f9803f3b2 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite_mode_ADC_DAC.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/Elite_mode_ADC_DAC.h @@ -440,19 +440,21 @@ static void CV_Plot(void) void *wm = wm_get(); if (ADC_cnt == 0) { - LPTIA_change_gain(); + read_LPTIA_Iin(); +// LPTIA_change_gain(); DACenable(AFTER_READ_V); ADC_cnt++; } else if (ADC_cnt == 1) { - vscan = (int32_t)(eis_dac_volt.vb - eis_dac_volt.vz) / 200; +// vscan = (int32_t)(eis_dac_volt.vb - eis_dac_volt.vz) / 200; + read_LPTIA_Iin(); ADC_cnt++; } else if (ADC_cnt == 2) { - LPTIA_change_gain(); +// LPTIA_change_gain(); ADC_cnt = 0; } -// InputNotify(NOTIFY_VOLT, vscan); +// InputNotify(NOTIFY_VOLT, MEAS_VOUT(wm)); // InputNotify(NOTIFY_CURRENT, MEAS_CURR(wm)); // InputNotify(NOTIFY_IMPEDANCE, instru.ADCGainLv); return; diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/eis_cali_table.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/eis_cali_table.h index e23c334f5..fc43049b6 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/eis_cali_table.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/eis_cali_table.h @@ -19,7 +19,7 @@ struct _CaliTable{ uint32_t CutoffFreq; uint8_t PhaseParaA; int16_t PhaseParaB; - uint8_t HSRTIA200R; + uint8_t HSRTIA200R; uint16_t HSRTIA5K; uint16_t HSRTIA20K; uint32_t HSRTIA160K; @@ -56,7 +56,7 @@ struct _CaliTable{ .PhaseParaA = 13, //1e6 .PhaseParaB = -8490, //1e3 .HSRTIA200R = 200, - .HSRTIA5K = 5100, + .HSRTIA5K = 5000, .HSRTIA20K = 20000, .HSRTIA160K = 160000 }; diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h index de31ad127..31e8de9c1 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h @@ -694,7 +694,7 @@ static void update_ZM_instruction(uint8 *ins) { instru.sampleRate = 15;//CalcDelayTime(User2Freq(instru.f1), true); //ms //read instru.fmax = (uint32_t)VMAX(instru.f1, instru.f2); instru.fmin = (uint32_t)VMIN(instru.f1, instru.f2); - instru.delay = 1;//((uint16_t)(ins[12]) << 8) | (uint16_t)(ins[13]); //DELAY/10 how many periods + instru.delay = ((uint16_t)(ins[12]) << 8) | (uint16_t)(ins[13]); //DELAY/10 how many periods if (instru.f1 > instru.f2){ instru.directionInit = 0; //0:reverse 1:forward } else if (instru.f1 <= instru.f2){ @@ -703,9 +703,9 @@ static void update_ZM_instruction(uint8 *ins) { } else if (ins[3] == PARA_2) { //3000D1 02 instru.eliteFxn = CURVE_EIS; instru.dcbias = 0;//((uint16_t)(ins[4]) << 8) | (uint16_t)(ins[5]); - instru.acamp = 26;((uint16_t)(ins[6]) << 8) | (uint16_t)(ins[7]); - instru.avgnum = 0;//(uint8_t)(ins[8]); - instru.rtia = 0;//(uint8_t)(ins[9]); + instru.acamp = ((uint16_t)(ins[6]) << 8) | (uint16_t)(ins[7]); + instru.avgnum = (uint8_t)(ins[8]); + instru.rtia = (uint8_t)(ins[9]); instru.ppd = 10;//((uint16_t)(ins[10]) << 8) | (uint16_t)(ins[11]); instru.scale = (uint8_t)(ins[12]); @@ -1384,6 +1384,11 @@ static void update_ZM_instruction(uint8 *ins) { DAC_outputV(data); } + case 0x15: { + uint8_t data = (uint8_t)(ins[4]); + LPTIAGainCtrl(data); + } + case 0x03: { // ble write: 0x3000FF 03 if (ins[4] == 1) { Elite_led_color(COLOR_RED); //0301