From 0071cd6dc0ddf4a40e59268963628f59afb2202e Mon Sep 17 00:00:00 2001 From: roy01 Date: Mon, 25 May 2026 10:08:31 +0800 Subject: [PATCH] fix: pack flash code --- flash_code_20260515.7z | Bin 5128320 -> 0 bytes flash_code_20260525.7z | Bin 0 -> 5128088 bytes .../flash_code/flash_code_linux.sh | 1 + .../flash_code/flash_code_win.bat | 2 + .../flash_code/flashloader/loader.bin | Bin 0 -> 680 bytes .../2025.10/OpenULINK/ulink_firmware.hex | 347 + .../openocd/linux/2025.10/README.md | 130 + .../linux/2025.10/angie/angie_bitstream.bit | Bin 0 -> 340704 bytes .../linux/2025.10/angie/angie_firmware.bin | Bin 0 -> 10216 bytes .../openocd/linux/2025.10/bin/libftdi1.so.2 | 1 + .../linux/2025.10/bin/libftdi1.so.2.4.0 | Bin 0 -> 73184 bytes .../linux/2025.10/bin/libhidapi-hidraw.so.0 | 1 + .../2025.10/bin/libhidapi-hidraw.so.0.0.0 | Bin 0 -> 22880 bytes .../openocd/linux/2025.10/bin/libiconv.so.2 | 1 + .../linux/2025.10/bin/libiconv.so.2.6.0 | Bin 0 -> 992280 bytes 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literal 0
HcmV?d00001

diff --git a/flash_code_20260525/flash_code/flash_code_linux.sh b/flash_code_20260525/flash_code/flash_code_linux.sh
new file mode 100755
index 0000000..453e197
--- /dev/null
+++ b/flash_code_20260525/flash_code/flash_code_linux.sh
@@ -0,0 +1 @@
+./openocd/linux/2025.10/bin/openocd -s openocd/linux/2025.10/scripts -f openocd/linux/2025.10/scripts/target/pec930.cfg -c "program pec930.hex verify reset exit"
diff --git a/flash_code_20260525/flash_code/flash_code_win.bat b/flash_code_20260525/flash_code/flash_code_win.bat
new file mode 100644
index 0000000..f26cda1
--- /dev/null
+++ b/flash_code_20260525/flash_code/flash_code_win.bat
@@ -0,0 +1,2 @@
+.\openocd\win\2025.10\bin\openocd -s openocd\win\2025.10\scripts -f openocd\win\2025.10\scripts\target\pec930.cfg -c "program pec930.hex verify reset exit"
+pause
diff --git a/flash_code_20260525/flash_code/flashloader/loader.bin b/flash_code_20260525/flash_code/flashloader/loader.bin
new file mode 100644
index 0000000000000000000000000000000000000000..0001e0fc964694c2084c8dba0fc9187e2840e350
GIT binary patch
literal 680
zcmWe>1LFdq6dtgu
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zn;9Ol8@C)~a5%pCc{zj3X&L9u-_sd3KMx1`MI7#ziL5b)H@9zdc$g_0J}ilumAu6

literal 0
HcmV?d00001

diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/OpenULINK/ulink_firmware.hex b/flash_code_20260525/flash_code/openocd/linux/2025.10/OpenULINK/ulink_firmware.hex
new file mode 100644
index 0000000..efaea58
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/OpenULINK/ulink_firmware.hex
@@ -0,0 +1,347 @@
+:040000000200713257
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+:10016D00E0C082C083C007C0D075D000D201AF916E
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diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/README.md b/flash_code_20260525/flash_code/openocd/linux/2025.10/README.md
new file mode 100644
index 0000000..8bfdc5e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/README.md
@@ -0,0 +1,130 @@
+# Nuclei OpenOCD Distribution
+
+For **Nuclei OpenOCD documentation**, please check https://doc.nucleisys.com/nuclei_tools/openocd/intro.html
+
+If the tool version and documentation version not match, please take care.
+
+**Below is the changelog for Nuclei OpenOCD.**
+
+## 2025.10
+
+This release is based on the same code base of **2025.02**, but do some new feature and bugfixes.
+
+* Update ``nuclei cpuinfo`` command implementation using nuclei sdk 0.9.0 cpuinfo same source code to provide same behavior
+* Correct custom flashloader binary file location search rules, where openocd executed, openocd ``scripts`` folder, and absolute path
+* Sync nuclei custom CSRs support
+* Optimize flash probe process, when no flash probed, it will exit with error instead of hang on it
+* Support debug for hypervisor mode
+* Fix debug ``Assertion failed!`` on HBird opensource cpu
+* Fix nuclei riscv cross trigger command implementation ``nuclei cti xxx``
+* Clear ``haltreq`` signal when openocd connect failed
+* Fix segmentation fault issue when debug level set to 3 or 4
+* When debug on FPGA CPU MHz is very slow such as **5MHz**, openocd may work not correctly, it will be fixed by make CPU run faster such as **10MHz**
+
+## 2025.02
+
+* improvement of ci and doc
+* replace ``vslide1down_vx`` to read/write riscv vector register
+* support live watch feature via riscv sba memory access channel
+* organize nuclei commands into ``nuclei_riscv.c``
+* add ``nuclei cti`` command group
+* update ``nuclei etrace`` command group
+* optimize ``nuclei cpuinfo`` command
+
+* add new nuclei customized csrs
+
+    | new csr addr | new csr name |
+    | ------ | ------ |
+    | 0x1a4~0x1af | smpuaddr4~15 |
+    | 0x1c0~0x1ef | smpuaddr16~63 |
+
+* rename nuclei customized csrs
+
+    | old name | new name |
+    | ------ | ------ |
+    | spmpcfg0~3 | smpucfg0~3 |
+    | spmpaddr0~15 | smpuaddr0~15 |
+    | mfp16mode | mmisc_ctl1 |
+    | mecc_ctrl | mecc_ctl |
+    | mstack_ctrl | mstack_ctl |
+
+* changes are based on [riscv/riscv-openocd@f82c5a7](https://github.com/riscv-collab/riscv-openocd/commit/f82c5a7)
+
+
+## 2024.06
+
+* Add and update nuclei custom CSR
+* Fix `nuclei cpuinfo` command implementation
+* Add debug map feature for Nuclei CPU with new `nuclei expose_cpu_core` and `nuclei examine_cpu_core` commands
+* changes are based on [riscv/riscv-openocd](https://github.com/riscv/riscv-openocd/commit/52177592)
+* Fix hbird/hbirdv2 flash programming, and re-route fespi to nuspi flash loader for hbird/hbirdv2 processor
+
+## 2024.02
+
+> **Still in development, not official release.**
+
+* Add Nuclei N100 CSR support
+* Nuclei etrace support multicore trace
+* Fix riscv debug 0.11 call riscv_run_algorithm error such as hbird/hbirdv2 processor
+* Update and fix openocd documentation
+* changes are based on [riscv/riscv-openocd](https://github.com/riscv/riscv-openocd/commit/52177592)
+
+## 2023.10
+
+* Add nuclei command group to contains all nuclei customized commands
+* Add `nuclei cpuinfo` dump support
+* Add more spiflash devices according to customer request
+* Fix gdb flash program error on address size > 32bit on windows
+* Update nuclei custom csr
+* Add `ftdi nscan1_mode` to support 2-wire cjtag for Nuclei CPU, which is replacement for `ftdi oscan1_mode`
+* Add nuclei custom command in openocd documentation
+* **Experimental and may change**: Add nuclei etrace command to support nuclei etrace hardware feature
+* changes are based on [riscv/riscv-openocd](https://github.com/riscv/riscv-openocd/commit/52177592)
+
+## 2022.12
+
+This is release 2022.12 of openocd.
+
+* nor/spi:add w25q512jv
+* add 'init resethalt' command
+* feature:auto search custom flashloader path
+* fix riscv-debug v0.11 call riscv_run_algorithm error.
+
+
+## 2022.08
+
+This is release 2022.08 of openocd.
+
+* spi_nor:add xt25f256b mac25l1633e gd25q80b gd25le32e en25s40a by25q32al fm25q128 gd25B512me.
+* merge upstream https://github.com/riscv/riscv-openocd commit id 52177592f9d3afc6a008f8e1b321cf74e823018f.
+* custom flashloader don't rely on 'src/flash/nor/spi.c', fix memory leaks bug.
+
+
+## 2022.04
+
+This is release 2022.04 of openocd.
+
+* add DSP ucode csr register
+* Adjustment simulation timeout param
+* Fix after write_bank/write_image command read date error bug
+* Add custom flash loader in openocd, please refer wiki for how to use it
+* Custom flash loader: add 'simulation' parameter for simulation test.
+
+
+## 2022.01
+
+This is release 2022.01 of openocd.
+
+* optimize cjtag support for nuclei cjtag
+* spi_nor: add BoHong bh25d80a bh25d40a bh25d20a
+* spi_nor: Add Micron MT25QU512
+* flash:"flash bank" command add simulation param
+* add nuclei all custom csr
+* spi_nor: Add MXIC MX25U51245G
+* transport/ftdi: Update to new standard cJTAG sequence
+* flash: add XinSheng RISC-V MCU CM32M4xxR flash program driver
+* Add nuspi loader support.
+* Add nuspi SPI flash driver support.
+* Enable multi-core debug.
+* Previous fespi loader will be rerouted to nuspi loader.
+* Changes are based on [openocd for riscv 0.11.0](https://github.com/riscv/riscv-openocd/commit/6edf98db7f98c5e24bc51cf98419bdf5bbc530e6)
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/angie/angie_bitstream.bit b/flash_code_20260525/flash_code/openocd/linux/2025.10/angie/angie_bitstream.bit
new file mode 100644
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diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libftdi1.so.2 b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libftdi1.so.2
new file mode 120000
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\ No newline at end of file
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libftdi1.so.2.4.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libftdi1.so.2.4.0
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HcmV?d00001

diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libhidapi-hidraw.so.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libhidapi-hidraw.so.0
new file mode 120000
index 0000000..55a7823
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libhidapi-hidraw.so.0
@@ -0,0 +1 @@
+libhidapi-hidraw.so.0.0.0
\ No newline at end of file
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libhidapi-hidraw.so.0.0.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libhidapi-hidraw.so.0.0.0
new file mode 100644
index 0000000000000000000000000000000000000000..74c6aa473db4f81b800297c0c7d0c5feaba43af6
GIT binary patch
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diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libiconv.so.2 b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libiconv.so.2
new file mode 120000
index 0000000..fe4fc96
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libiconv.so.2
@@ -0,0 +1 @@
+libiconv.so.2.6.0
\ No newline at end of file
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libiconv.so.2.6.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libiconv.so.2.6.0
new file mode 100644
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diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libudev.so b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/libudev.so
new file mode 100644
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diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/openocd b/flash_code_20260525/flash_code/openocd/linux/2025.10/bin/openocd
new file mode 100755
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HcmV?d00001

diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/60-openocd.rules b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/60-openocd.rules
new file mode 100644
index 0000000..29f8d7a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/60-openocd.rules
@@ -0,0 +1,265 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Copy this file to /etc/udev/rules.d/
+# If rules fail to reload automatically, you can refresh udev rules
+# with the command "udevadm control --reload"
+
+ACTION!="add|change", GOTO="openocd_rules_end"
+
+SUBSYSTEM=="gpio", MODE="0660", GROUP="plugdev", TAG+="uaccess"
+
+SUBSYSTEM!="usb|tty|hidraw", GOTO="openocd_rules_end"
+
+# Please keep this list sorted by VID:PID
+
+# opendous and estick
+ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="204f", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT232/FT245 VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6001", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT2232 VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT4232 VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6011", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT232H VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="660", GROUP="plugdev", TAG+="uaccess"
+# Original FT231XQ VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT2233HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6040", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT4233HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6041", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT2232HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6042", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT4232HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6043", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT233HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6044", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT232HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6045", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT4232HA VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6048", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# DISTORTEC JTAG-lock-pick Tiny 2
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8220", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# TUMPA, TUMPA Lite
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8a98", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8a99", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Marvell OpenRD JTAGKey FT2232D B
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="9e90", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# XDS100v2
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="a6d0", MODE="660", GROUP="plugdev", TAG+="uaccess"
+# XDS100v3
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="a6d1", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# OOCDLink
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="baf8", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Kristech KT-Link
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bbe2", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Xverve Signalyzer Tool (DT-USB-ST), Signalyzer LITE (DT-USB-SLITE)
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bca0", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bca1", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# TI/Luminary Stellaris Evaluation Board FTDI (several)
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bcd9", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# TI/Luminary Stellaris In-Circuit Debug Interface FTDI (ICDI) Board
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bcda", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# egnite Turtelizer 2
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bdc8", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Section5 ICEbear
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c140", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c141", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Amontec JTAGkey and JTAGkey-tiny
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="cff8", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# ASIX Presto programmer
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="f1a0", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Nuvoton NuLink
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511b", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511c", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511d", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="5200", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="5201", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# TI ICDI
+ATTRS{idVendor}=="0451", ATTRS{idProduct}=="c32a", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# STMicroelectronics ST-LINK V1
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3744", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# STMicroelectronics ST-LINK/V2
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3748", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# STMicroelectronics ST-LINK/V2.1
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3752", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# STMicroelectronics STLINK-V3
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374d", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374e", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374f", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3753", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3754", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3755", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3757", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Cypress SuperSpeed Explorer Kit
+ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="0007", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Cypress KitProg in KitProg mode
+ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="f139", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Cypress KitProg in CMSIS-DAP mode
+ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="f138", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Infineon DAP miniWiggler v3
+ATTRS{idVendor}=="058b", ATTRS{idProduct}=="0043", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Hitex LPC1768-Stick
+ATTRS{idVendor}=="0640", ATTRS{idProduct}=="0026", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Hilscher NXHX Boards
+ATTRS{idVendor}=="0640", ATTRS{idProduct}=="0028", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Hitex STR9-comStick
+ATTRS{idVendor}=="0640", ATTRS{idProduct}=="002c", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Hitex STM32-PerformanceStick
+ATTRS{idVendor}=="0640", ATTRS{idProduct}=="002d", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Hitex Cortino
+ATTRS{idVendor}=="0640", ATTRS{idProduct}=="0032", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Altera USB Blaster
+ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="660", GROUP="plugdev", TAG+="uaccess"
+# Altera USB Blaster2
+ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6010", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6810", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Ashling Opella-LD
+ATTRS{idVendor}=="0B6B", ATTRS{idProduct}=="0040", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Amontec JTAGkey-HiSpeed
+ATTRS{idVendor}=="0fbb", ATTRS{idProduct}=="1000", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# SEGGER J-Link
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0101", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0102", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0103", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0104", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0105", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0107", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0108", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1010", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1011", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1012", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1013", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1014", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1015", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1016", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1017", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1018", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1020", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1051", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1055", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1061", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Raisonance RLink
+ATTRS{idVendor}=="138e", ATTRS{idProduct}=="9000", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Debug Board for Neo1973
+ATTRS{idVendor}=="1457", ATTRS{idProduct}=="5118", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# OSBDM
+ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0042", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0058", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="005e", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Olimex ARM-USB-OCD
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="0003", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Olimex ARM-USB-OCD-TINY
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="0004", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Olimex ARM-JTAG-EW
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="001e", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Olimex ARM-USB-OCD-TINY-H
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="002a", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Olimex ARM-USB-OCD-H
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="002b", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# ixo-usb-jtag - Emulation of a Altera Bus Blaster I on a Cypress FX2 IC
+ATTRS{idVendor}=="16c0", ATTRS{idProduct}=="06ad", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# USBprog with OpenOCD firmware
+ATTRS{idVendor}=="1781", ATTRS{idProduct}=="0c63", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# TI/Luminary Stellaris In-Circuit Debug Interface (ICDI) Board
+ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00fd", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# TI XDS110 Debug Probe (Launchpads and Standalone)
+ATTRS{idVendor}=="0451", ATTRS{idProduct}=="bef3", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0451", ATTRS{idProduct}=="bef4", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="02a5", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# TI Tiva-based ICDI and XDS110 probes in DFU mode
+ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00ff", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# isodebug v1
+ATTRS{idVendor}=="22b7", ATTRS{idProduct}=="150d", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# PLS USB/JTAG Adapter for SPC5xxx
+ATTRS{idVendor}=="263d", ATTRS{idProduct}=="4001", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Numato Mimas A7 - Artix 7 FPGA Board
+ATTRS{idVendor}=="2a19", ATTRS{idProduct}=="1009", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Ambiq Micro EVK and Debug boards.
+ATTRS{idVendor}=="2aec", ATTRS{idProduct}=="6010", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="2aec", ATTRS{idProduct}=="6011", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="2aec", ATTRS{idProduct}=="1106", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Espressif USB JTAG/serial debug units
+ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1001", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1002", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# ANGIE USB-JTAG Adapter
+ATTRS{idVendor}=="584e", ATTRS{idProduct}=="414f", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="584e", ATTRS{idProduct}=="424e", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4255", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4355", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4a55", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Marvell Sheevaplug
+ATTRS{idVendor}=="9e88", ATTRS{idProduct}=="9e8f", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Keil Software, Inc. ULink
+ATTRS{idVendor}=="c251", ATTRS{idProduct}=="2710", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="c251", ATTRS{idProduct}=="2750", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# CMSIS-DAP compatible adapters
+ATTRS{product}=="*CMSIS-DAP*", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+LABEL="openocd_rules_end"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/README b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/README
new file mode 100644
index 0000000..1135b24
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/README
@@ -0,0 +1,18 @@
+This code is an example of using the openocd debug message system.
+
+Before the message output is seen in the debug window, the functionality
+will need enabling:
+
+From the gdb prompt:
+monitor target_request debugmsgs enable
+monitor trace point 1
+
+From the Telnet prompt:
+target_request debugmsgs enable
+trace point 1
+
+To see how many times the trace point was hit:
+(monitor) trace point 1
+
+Spen
+spen@spen-soft.co.uk
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/dcc_stdio.c b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/dcc_stdio.c
new file mode 100644
index 0000000..9ad633b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/dcc_stdio.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/***************************************************************************
+ *   Copyright (C) 2008 by Dominic Rath                                    *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2008 by Spencer Oliver                                  *
+ *   spen@spen-soft.co.uk                                                  *
+ *   Copyright (C) 2008 by Frederik Kriewtz                                *
+ *   frederik@kriewitz.eu                                                  *
+ ***************************************************************************/
+
+#include "dcc_stdio.h"
+
+#define TARGET_REQ_TRACEMSG					0x00
+#define TARGET_REQ_DEBUGMSG_ASCII			0x01
+#define TARGET_REQ_DEBUGMSG_HEXMSG(size)	(0x01 | ((size & 0xff) << 8))
+#define TARGET_REQ_DEBUGCHAR				0x02
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_6SM__)
+
+/* we use the System Control Block DCRDR reg to simulate a arm7_9 dcc channel
+ * DCRDR[7:0] is used by target for status
+ * DCRDR[15:8] is used by target for write buffer
+ * DCRDR[23:16] is used for by host for status
+ * DCRDR[31:24] is used for by host for write buffer */
+
+#define NVIC_DBG_DATA_R		(*((volatile unsigned short *)0xE000EDF8))
+
+#define	BUSY	1
+
+void dbg_write(unsigned long dcc_data)
+{
+	int len = 4;
+
+	while (len--)
+	{
+		/* wait for data ready */
+		while (NVIC_DBG_DATA_R & BUSY);
+
+		/* write our data and set write flag - tell host there is data*/
+		NVIC_DBG_DATA_R = (unsigned short)(((dcc_data & 0xff) << 8) | BUSY);
+		dcc_data >>= 8;
+	}
+}
+
+#elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5T__)
+
+void dbg_write(unsigned long dcc_data)
+{
+	unsigned long dcc_status;
+
+	do {
+		asm volatile("mrc p14, 0, %0, c0, c0" : "=r" (dcc_status));
+	} while (dcc_status & 0x2);
+
+	asm volatile("mcr p14, 0, %0, c1, c0" : : "r" (dcc_data));
+}
+
+#else
+ #error unsupported target
+#endif
+
+void dbg_trace_point(unsigned long number)
+{
+	dbg_write(TARGET_REQ_TRACEMSG | (number << 8));
+}
+
+void dbg_write_u32(const unsigned long *val, long len)
+{
+	dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(4) | ((len & 0xffff) << 16));
+
+	while (len > 0)
+	{
+		dbg_write(*val);
+
+		val++;
+		len--;
+	}
+}
+
+void dbg_write_u16(const unsigned short *val, long len)
+{
+	unsigned long dcc_data;
+
+	dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(2) | ((len & 0xffff) << 16));
+
+	while (len > 0)
+	{
+		dcc_data = val[0]
+			| ((len > 1) ? val[1] << 16: 0x0000);
+
+		dbg_write(dcc_data);
+
+		val += 2;
+		len -= 2;
+	}
+}
+
+void dbg_write_u8(const unsigned char *val, long len)
+{
+	unsigned long dcc_data;
+
+	dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(1) | ((len & 0xffff) << 16));
+
+	while (len > 0)
+	{
+		dcc_data = val[0]
+			| ((len > 1) ? val[1] << 8 : 0x00)
+			| ((len > 2) ? val[2] << 16 : 0x00)
+			| ((len > 3) ? val[3] << 24 : 0x00);
+
+		dbg_write(dcc_data);
+
+		val += 4;
+		len -= 4;
+	}
+}
+
+void dbg_write_str(const char *msg)
+{
+	long len;
+	unsigned long dcc_data;
+
+	for (len = 0; msg[len] && (len < 65536); len++);
+
+	dbg_write(TARGET_REQ_DEBUGMSG_ASCII | ((len & 0xffff) << 16));
+
+	while (len > 0)
+	{
+		dcc_data = msg[0]
+			| ((len > 1) ? msg[1] << 8 : 0x00)
+			| ((len > 2) ? msg[2] << 16 : 0x00)
+			| ((len > 3) ? msg[3] << 24 : 0x00);
+		dbg_write(dcc_data);
+
+		msg += 4;
+		len -= 4;
+	}
+}
+
+void dbg_write_char(char msg)
+{
+	dbg_write(TARGET_REQ_DEBUGCHAR | ((msg & 0xff) << 16));
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/dcc_stdio.h b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/dcc_stdio.h
new file mode 100644
index 0000000..3447b8c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/dcc_stdio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2008 by Dominic Rath                                    *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2008 by Spencer Oliver                                  *
+ *   spen@spen-soft.co.uk                                                  *
+ ***************************************************************************/
+
+#ifndef DCC_STDIO_H
+#define DCC_STDIO_H
+
+void dbg_trace_point(unsigned long number);
+
+void dbg_write_u32(const unsigned long *val, long len);
+void dbg_write_u16(const unsigned short *val, long len);
+void dbg_write_u8(const unsigned char *val, long len);
+
+void dbg_write_str(const char *msg);
+void dbg_write_char(char msg);
+
+#endif	/* DCC_STDIO_H */
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/example.c b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/example.c
new file mode 100644
index 0000000..7c7d936
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/contrib/libdcc/example.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/***************************************************************************
+ *   Copyright (C) 2008 by Spencer Oliver                                  *
+ *   spen@spen-soft.co.uk                                                  *
+ *   Copyright (C) 2008 by Frederik Kriewtz                                *
+ *   frederik@kriewitz.eu                                                  *
+ ***************************************************************************/
+
+#include "dcc_stdio.h"
+
+/* enable openocd debugmsg at the gdb prompt:
+ * monitor target_request debugmsgs enable
+ *
+ * create a trace point:
+ * monitor trace point 1
+ *
+ * to show how often the trace point was hit:
+ * monitor trace point
+*/
+
+int main(void)
+{
+	dbg_write_str("hello world");
+
+	dbg_write_char('t');
+	dbg_write_char('e');
+	dbg_write_char('s');
+	dbg_write_char('t');
+	dbg_write_char('\n');
+
+	unsigned long test_u32 = 0x01234567;
+	dbg_write_u32(&test_u32, 1);
+
+	static const unsigned short test_u16[] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x0123, 0x4567, 0x89AB, 0xCDEF};
+	dbg_write_u16(test_u16, 8);
+
+	static const unsigned char test_u8[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0XDD, 0xEE, 0xFF};
+	dbg_write_u8(test_u8, 16);
+
+	while(1)
+	{
+		dbg_trace_point(0);
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/CHANGELOG.md b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/CHANGELOG.md
new file mode 100644
index 0000000..249f006
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/CHANGELOG.md
@@ -0,0 +1,232 @@
+## Change & release log
+
+Releases in reverse chronological order.
+
+### 2019-07-20
+
+- v0.10.0-13.1 published on npmjs.com
+
+### 2019-07-17
+
+- v0.10.0-13 released
+
+### 2019-07-08
+
+- update to 263deb380 from 7 Jul 2019
+  
+___
+
+## Historical GNU MCU Eclipse change log
+
+### 2019-04-23
+
+- v0.10.0-12-20190423 released
+
+### 2019-04-09
+
+- prepare - v0.10.0-12
+- update to latest master from Apr 7th, 2019
+- update LIBUSB1_VERSION="1.0.22"
+- update LIBFTDI_VERSION="1.4"
+
+### 2019-01-18
+
+- v0.10.0-11-20190118 released
+- update to latest master from Jan 16, 2019
+- RISC-V specific patches were removed, only upstreamed functionality retained.
+
+### 2018-10-20
+
+- v0.10.0-10-20181020 released
+- rerun, to fix the macOS file dates
+- update the -bit to singular
+
+### 2018-10-16
+
+- v0.10.0-9-20181016 released
+- update to latest master
+- update to latest RISC-V
+- revert some of the RISC-V patches in the common files
+
+### 2018-06-19
+
+- update to latest RISC-V commits, including semihosting
+
+### 2018-06-12
+
+- use separate README-*.md files
+- update to latest commits, which include new semihosting (OpenOCD June 6th, RISC-V June 12th)
+
+### 2018-05-12
+
+- v0.10.0-8-20180512 released
+- use new build scripts based on XBB
+- update to latest commits (OpenOCD April 27th, RISC-V May 8th)
+
+### 2018-01-23
+
+- v0.10.0-7-20180123 released
+- move semihosting code to separate files
+- use them in RISC-V and ARM
+- add 'arm semihosting_resexit enable' to allow exit() to return
+
+### 2018-01-12
+
+- v0.10.0-6-20180112 released
+- update to master from Dec 20
+- update to riscv from Dec 29
+- remove the patch to hide the CSRs, the new version displays only a limited number of them.
+- remove the `remote_bitbang.c` patch, since it compiles ok on mingw-w64
+- the SiFive board scripts were upstreamed to the RISC-V fork
+
+### 2017-11-10
+
+- v0.10.0-5-20171110-dev released
+- update to master from Oct 2
+- update to riscv from Nov 4
+- target.c & riscv/riscv-0[13].c: hide the 4096 CSRs from `monitor reg`
+- update the SiFive board script files
+- revert the risc-v changes in `remote_bitbang.c`, since they break the build on mingw-w64
+
+### 2017-10-04
+
+- v0.10.0-4-20171004-*-dev released
+- update to master from Aug 10
+- update to riscv fom Oct 2
+- gdb_server.c: workaround to gdb errors; disable passing errors back to gdb since this risc-v change breaks other targets.
+
+### 2017-08-25
+
+- v0.10.0-3-20170826-*-dev released
+- merge RISC-V tag v20170818
+- server.c: fix clang warning in getsockname()
+
+### 2017-07-03
+
+- update build script to use Debian 9 Docker containers
+
+### 2017-06-22
+
+- v0.10.0-2-20170622-1535-dev released
+- merge RISC-V tag v20170621 
+
+### 2017-06-15
+
+- move the build specific gnu-mcu-eclipse folder to a separate openocd-build project
+
+### 2017-06-12
+
+- add --enable-riscv and #if BUILD_RISCV
+- add --enable-branding 
+
+### 2017-06-07
+
+- v0.10.0-1-20170607-2132-dev released
+- add sifive-* configuration files to the board folder
+- 60-openocd.rules: simplify access rights
+- merge RISC-V commit '11008ba' into gnu-mcu-eclipse-dev
+
+### 2017-06-06
+
+- rename gnu-mcu-eclipse & content
+
+### 2017-06-04
+
+- merge original branch 'master' from 2017-06-02 into gnuarmeclipse-dev.
+- merge RISC-V commit '51ab5a0' from 2017-05-26 into gnuarmeclipse-dev
+
+### 2017-01-24
+
+- v0.10.0-20170124* released (stable)
+- merge original 0.10.0, override local relative path processing
+
+### 2016-10-28
+
+- v0.10.0-20161028*-dev released
+
+### 2016-10-20
+
+- nsi file: add InstallDir; silent install should honour /D
+
+### 2016-01-10
+
+- v0.10.0-20160110*-dev released
+
+### 2015-10-28
+
+- v0.10.0-20151028*-dev released
+
+### 2015-05-19
+
+- v0.9.0-20150519*-dev released
+- remove @raggedright from openocd.texi
+
+### 2015-05-11
+
+- the three separate build scripts were deprecated, and a single script,
+using Docker, was added to the main gnuarmeclipse-se.git/scripts.
+
+- the greeting shows 32-bits or 64-bits (plural for bits). (wrong!)
+
+### 2015-03-24
+
+- v0.9.0-20150324*-dev released
+- v0.8.0-20150324* released
+
+### 2015-03-22
+
+- the NSIS script was fixed to prevent removing the keys when 
+uninstalling an older version.
+
+### 2015-03-20
+
+- v0.9.0-20150320*-dev released
+- v0.8.0-20150320* released
+
+### 2015-03-18
+
+- the build scripts were extended to generate both the stable and the 
+development version.
+
+- multiple versions of the package can be installed in separate folders, 
+named using the version.
+
+- for Windows, more accurate keys were stored, so remember separate locations 
+for 32/64-bit versions.
+
+### 2015-01-31
+
+- v0.8.0-20150131* released
+
+### 2015-01-30
+
+- gnuarmeclipse
+
+All GNU ARM Eclipse OpenOCD build related files were grouped under this folder.
+
+- README.md
+
+Markdown files were added in all new folders, to improve the look when browsed
+in the SourceForge Git web browser.
+
+### 2015-01-19
+
+- v0.8.0-20150119* released
+
+### 2015-01-12
+
+- src/openocd.c
+
+Add branding 'GNU ARM Eclipse' to the greeting message, to 
+more easily identify this custom version.
+
+- helper/options.c
+
+Update the logic used to locate the 'scripts' folder, by 
+using the argv[0], as on Windows. The logic is a bit more
+complicated, to accomodate 3 cases (no path, relative path
+and absolute path).
+
+
+Liviu Ionescu
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/AUTHORS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/AUTHORS
new file mode 100644
index 0000000..43e5218
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/AUTHORS
@@ -0,0 +1,79 @@
+Main developers:
+
+  Intra2net AG 
+
+Contributors in alphabetical order,
+see Changelog for full details:
+
+  Adam Malinowski 
+  Alain Abbas 
+  Alexander Lehmann 
+  Alex Harford 
+  Anders Larsen 
+  Andrei Errapart 
+  Andrew John Rogers 
+  Arnim Läuger 
+  Aurelien Jarno 
+  Benjamin Vanheuverzwijn 
+  Chris Morgan 
+  Chris Zeh 
+  Clifford Wolf 
+  Daniel Kirkham 
+  David Challis 
+  Davide Michelizza 
+  Denis Sirotkin 
+  Emil 
+  Eric Schott 
+  Eugene Hutorny 
+  Evan Nemerson 
+  Evgeny Sinelnikov 
+  Fahrzin Hemmati 
+  Flynn Marquardt 
+  Forest Crossman 
+  Ian Abbott 
+  Jared Boone 
+  Jarkko Sonninen 
+  Jean-Daniel Merkli 
+  Jochen Sprickerhof 
+  Joe Zbiciak 
+  Jon Beniston 
+  Juergen Beisert 
+  Lorenz Moesenlechner 
+  Marek Vavruša 
+  Marius Kintel 
+  Mark Hämmerling 
+  Matthias Janke 
+  Matthias Kranz 
+  Matthias Richter 
+  Matthijs ten Berge 
+  Max 
+  Maxwell Dreytser 
+  Michel Zou 
+  Mike Frysinger 
+  Nathael Pajani 
+  Nathan Fraser 
+  Oleg Seiljus 
+  Paul Fertser 
+  Peter Holik 
+  Raphael Assenat 
+  Robert Cox 
+  Robin Haberkorn 
+  Rodney Sinclair 
+  Rogier Wolff 
+  Rolf Fiedler 
+  Salvador Eduardo Tropea 
+  Stephan Linz 
+  Steven Turner 
+  Tarek Heiland 
+  Thilo Schulz 
+  Thimo Eichstaedt 
+  Thomas Fischl 
+  Thomas Klose 
+  Tim Ansell 
+  Tom Saunders 
+  Uwe Bonnes 
+  Vladimir Yakovlev 
+  Wilfried Holzke 
+  Xiaofan Chen 
+  Yegor Yefremov 
+  Yi-Shin Li 
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/COPYING-CMAKE-SCRIPTS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/COPYING-CMAKE-SCRIPTS
new file mode 100644
index 0000000..4b41776
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/COPYING-CMAKE-SCRIPTS
@@ -0,0 +1,22 @@
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+3. The name of the author may not be used to endorse or promote products 
+   derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/COPYING.GPL b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/COPYING.GPL
new file mode 100644
index 0000000..d511905
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/COPYING.GPL
@@ -0,0 +1,339 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
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+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Lesser General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
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+that everyone understands that there is no warranty for this free
+software.  If the software is modified by someone else and passed on, we
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+patent must be licensed for everyone's free use or not licensed at all.
+
+  The precise terms and conditions for copying, distribution and
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+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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+Activities other than copying, distribution and modification are not
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+  10. If you wish to incorporate parts of the Program into other free
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+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
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+		     END OF TERMS AND CONDITIONS
+
+	    How to Apply These Terms to Your New Programs
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+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
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+
+    
+    Copyright (C)   
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+    This program is free software; you can redistribute it and/or modify
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+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
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+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
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+
+    Gnomovision version 69, Copyright (C) year name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
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+The hypothetical commands `show w' and `show c' should show the appropriate
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+be called something other than `show w' and `show c'; they could even be
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+
+You should also get your employer (if you work as a programmer) or your
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+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  , 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
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diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/COPYING.LIB b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/COPYING.LIB
new file mode 100644
index 0000000..5bc8fb2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/COPYING.LIB
@@ -0,0 +1,481 @@
+                  GNU LIBRARY GENERAL PUBLIC LICENSE
+                       Version 2, June 1991
+
+ Copyright (C) 1991 Free Software Foundation, Inc.
+ 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the library GPL.  It is
+ numbered 2 because it goes with version 2 of the ordinary GPL.]
+
+                            Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+  This license, the Library General Public License, applies to some
+specially designated Free Software Foundation software, and to any
+other libraries whose authors decide to use it.  You can use it for
+your libraries, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if
+you distribute copies of the library, or if you modify it.
+
+  For example, if you distribute copies of the library, whether gratis
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+  Our method of protecting your rights has two steps: (1) copyright
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+
+  Finally, any free program is threatened constantly by software
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+
+                  GNU LIBRARY GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/LICENSE b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/LICENSE
new file mode 100644
index 0000000..f1831c0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/LICENSE
@@ -0,0 +1,25 @@
+The C library "libftdi1" is distributed under the
+GNU Library General Public License version 2.
+
+A copy of the GNU Library General Public License (LGPL) is included
+in this distribution, in the file COPYING.LIB.
+
+----------------------------------------------------------------------
+
+The C++ wrapper "ftdipp1" is distributed under the GNU General
+Public License version 2 (with a special exception described below).
+
+A copy of the GNU General Public License (GPL) is included
+in this distribution, in the file COPYING.GPL.
+
+As a special exception, if other files instantiate templates or use macros
+or inline functions from this file, or you compile this file and link it
+with other works to produce a work based on this file, this file
+does not by itself cause the resulting work to be covered
+by the GNU General Public License.
+
+However the source code for this file must still be made available
+in accordance with section (3) of the GNU General Public License.
+
+This exception does not invalidate any other reasons why a work based
+on this file might be covered by the GNU General Public License.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/README b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/README
new file mode 100644
index 0000000..072b671
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/README
@@ -0,0 +1,52 @@
+--------------------------------------------------------------------
+libftdi version 1.4
+--------------------------------------------------------------------
+
+libftdi - A library (using libusb) to talk to FTDI's UART/FIFO chips
+including the popular bitbang mode.
+
+The following chips are supported:
+* FT230X
+- FT4232H / FT2232H
+- FT232R  / FT245R
+- FT2232L / FT2232D / FT2232C
+- FT232BM / FT245BM (and the BL/BQ variants)
+- FT8U232AM / FT8U245AM
+
+libftdi requires libusb 1.x.
+
+The AUTHORS file contains a list of all the people
+that made libftdi possible what it is today.
+
+Changes
+-------
+* New ftdi_usb_open_bus_addr() open function
+* Use BM/R series baud rate computation for FT230X
+* ftdi_get_error_string() now returns const char*
+* C++ API: Ability to open devices with empty descriptor strings
+* C++ API: Fix enumerations for buffer purge and modem controls
+* small build fixes and improvements in the python examples
+* ftdi_eeprom / eeprom handling:
+  * New API function: ftdi_eeprom_get_strings()
+  * Fix USE_SERIAL handling for 230X type chips
+  * Make ftdi_read_eeprom_location() endianness independent
+  * Fix flashing of FT245R
+
+You'll find the newest version of libftdi at:
+https://www.intra2net.com/en/developer/libftdi
+
+
+Quick start
+-----------
+mkdir build
+cd build
+
+cmake -DCMAKE_INSTALL_PREFIX="/usr" ../
+make
+make install
+
+More verbose build instructions are in "README.build"
+
+--------------------------------------------------------------------
+www.intra2net.com                             2003-2017 Intra2net AG
+--------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/README.build b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/README.build
new file mode 100644
index 0000000..e130ca0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/README.build
@@ -0,0 +1,96 @@
+Here is a short tutorial on how to build libftdi git under
+Ubuntu 12.10, But it is similar on other Linux distros.
+
+1) Install the build tools
+sudo apt-get install build-essential (yum install make automake gcc gcc-c++ kernel-devel)
+sudo apt-get install git-core (yum install git)
+sudo apt-get install cmake (yum install cmake)
+sudo apt-get install doxygen (for building documentations) (yum install doxygen)
+
+2) Install dependencies
+sudo apt-get install libusb-1.0-devel (yum install libusb-devel)
+(if the system comes with older version like 1.0.8 or
+earlier, it is recommended you build libusbx-1.0.14 or later).
+
+sudo apt-get install libconfuse-dev (for ftdi-eeprom) (yum install libconfuse-devel)
+sudo apt-get install swig python-dev (for python bindings) (yum install swig python-devel)
+sudo apt-get install libboost-all-dev (for C++ binding and unit test) (yum install boost-devel)
+
+3) Clone the git repository
+mkdir libftdi
+cd libftdi
+git clone git://developer.intra2net.com/libftdi
+
+If you are building the release tar ball, just extract the source
+tar ball.
+
+4) Build the git source and install
+cd libftdi
+mkdir build
+cd build
+cmake  -DCMAKE_INSTALL_PREFIX="/usr" ../
+make
+sudo make install
+
+5) carry out some tests
+cd examples
+
+mcuee@Ubuntu1210VM:~/Desktop/build/libftdi/libftdi/build/examples$
+./find_all_pp  -v 0x0403 -p 0x6001
+Found devices ( VID: 0x403, PID: 0x6001 )
+------------------------------------------------
+FTDI (0x8730800): ftdi, usb serial converter, ftDEH51S (Open OK)
+FTDI (0x8730918): FTDI, FT232R USB UART, A8007Ub5 (Open OK)
+
+mcuee@Ubuntu1210VM:~/Desktop/build/libftdi/libftdi/build/examples$ ./eeprom
+2 FTDI devices found: Only Readout on EEPROM done. Use
+VID/PID/desc/serial to select device
+Decoded values of device 1:
+Chip type 1 ftdi_eeprom_size: 128
+0x000: 00 00 03 04 01 60 00 04  a0 16 08 00 10 01 94 0a .....`.. ........
+0x010: 9e 2a c8 12 0a 03 66 00  74 00 64 00 69 00 2a 03 .*....f. t.d.i.*.
+0x020: 75 00 73 00 62 00 20 00  73 00 65 00 72 00 69 00 u.s.b. . s.e.r.i.
+0x030: 61 00 6c 00 20 00 63 00  6f 00 6e 00 76 00 65 00 a.l. .c. o.n.v.e.
+0x040: 72 00 74 00 65 00 72 00  12 03 66 00 74 00 44 00 r.t.e.r. ..f.t.D.
+0x050: 45 00 48 00 35 00 31 00  53 00 02 03 00 00 00 00 E.H.5.1. S.......
+0x060: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00 ........ ........
+0x070: 00 00 00 00 00 00 00 00  00 00 00 00 01 00 16 02 ........ ........
+VID:     0x0403
+PID:     0x6001
+Release: 0x0400
+Bus Powered:  44 mA USB Remote Wake Up
+Manufacturer: ftdi
+Product:      usb serial converter
+Serial:       ftDEH51S
+Checksum      : 0216
+Enable Remote Wake Up
+PNP: 1
+Decoded values of device 2:
+Chip type 3 ftdi_eeprom_size: 128
+0x000: 00 40 03 04 01 60 00 00  a0 2d 08 00 00 00 98 0a .@...`.. .-......
+0x010: a2 20 c2 12 23 10 05 00  0a 03 46 00 54 00 44 00 . ..#... ..F.T.D.
+0x020: 49 00 20 03 46 00 54 00  32 00 33 00 32 00 52 00 I. .F.T. 2.3.2.R.
+0x030: 20 00 55 00 53 00 42 00  20 00 55 00 41 00 52 00  .U.S.B.  .U.A.R.
+0x040: 54 00 12 03 41 00 38 00  30 00 30 00 37 00 55 00 T...A.8. 0.0.7.U.
+0x050: 62 00 35 00 c9 bf 1c 80  00 00 00 00 00 00 00 00 b.5..... ........
+0x060: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00 ........ ........
+0x070: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 0f 23 ........ .......#
+0x080: 2c 04 d3 fb 00 00 c9 bf  1c 80 42 00 00 00 00 00 ,....... ..B.....
+0x090: 00 00 00 00 00 00 00 00  38 41 32 52 4a 33 47 4f ........ 8A2RJ3GO
+VID:     0x0403
+PID:     0x6001
+Release: 0x0000
+Bus Powered:  90 mA USB Remote Wake Up
+Manufacturer: FTDI
+Product:      FT232R USB UART
+Serial:       A8007Ub5
+Checksum      : 230f
+Internal EEPROM
+Enable Remote Wake Up
+PNP: 1
+Channel A has Mode UART VCP
+C0 Function: TXLED
+C1 Function: RXLED
+C2 Function: TXDEN
+C3 Function: PWREN
+C4 Function: SLEEP
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/README.mingw b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/README.mingw
new file mode 100644
index 0000000..771204c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libftdi1-1.4/README.mingw
@@ -0,0 +1,38 @@
+* How to cross compile libftdi-1.x for Windows? *
+   1 - Prepare a pkg-config wrapper according to
+       https://www.flameeyes.eu/autotools-mythbuster/pkgconfig/cross-compiling.html ,
+       additionally export PKG_CONFIG_ALLOW_SYSTEM_CFLAGS and
+       PKG_CONFIG_ALLOW_SYSTEM_LIBS.
+   2 - Write a CMake toolchain file according to
+       http://www.vtk.org/Wiki/CmakeMingw . Change the path to your future sysroot.
+   3 - Get libusb sources (either by cloning the git repo or by downloading a
+       tarball). Unpack, autogen.sh (when building from git), and configure like this:
+       ./configure --build=`./config.guess` --host=i686-w64-mingw32 \
+               --prefix=/usr --with-sysroot=$HOME/i686-w64-mingw32-root/
+   4 - run
+       make install DESTDIR=$HOME/i686-w64-mingw32-root/
+   5 - go to libftdi-1.x source directory and run
+       cmake -DCMAKE_TOOLCHAIN_FILE=~/Toolchain-mingw.cmake \
+             -DCMAKE_INSTALL_PREFIX="/usr" \
+             -DPKG_CONFIG_EXECUTABLE=`which i686-w64-mingw32-pkg-config`
+   6 - run
+       make install DESTDIR=$HOME/i686-w64-mingw32-root/
+
+* How to run libftdi 1.x under Windows *
+
+On 26-Jan-2014, libusbx and libusb project were merged with the release
+of libusb-1.0.18 and now the project is called libusb.
+
+libusb Windows backend will need to rely on a proper driver to run.
+Please refer to the following wiki page for proper driver installation.
+https://github.com/libusb/libusb/wiki/Windows#wiki-How_to_use_libusb_on_Windows
+
+As of 26-Jan-2014, libusb Windows backend supports WinUSB,
+libusb0.sys and libusbk.sys driver. However, libusb's support of
+libusb0.sys and libusbk.sys is considered to be less mature than
+WinUSB. Therefore, WinUSB driver installation using Zadig
+is recommended.
+
+Take note once you replace the original FTDI driver with WinUSB driver,
+you can no longer use the functionality the original FTDI driver provides
+(eg. Virtual Serial Port or D2XX).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/AUTHORS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/AUTHORS
new file mode 100644
index 0000000..8bedd79
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/AUTHORS
@@ -0,0 +1 @@
+Bruno Haible 
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/COPYING b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/COPYING
new file mode 100644
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+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. 
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diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/COPYING.LIB b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/COPYING.LIB
new file mode 100644
index 0000000..778d0bb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/COPYING.LIB
@@ -0,0 +1,482 @@
+		  GNU LIBRARY GENERAL PUBLIC LICENSE
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+That's all there is to it!
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/DEPENDENCIES b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/DEPENDENCIES
new file mode 100644
index 0000000..64b08a9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/DEPENDENCIES
@@ -0,0 +1 @@
+No packages need to be installed before GNU libiconv is installed.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/NEWS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/NEWS
new file mode 100644
index 0000000..cb2a5fb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/NEWS
@@ -0,0 +1,190 @@
+New in 1.15:
+* The UTF-8 converter now rejects surrogates and out-of-range code points.
+* Added ISO-2022-JP-MS converter.
+* Updated the CP1255 converter to map one more character.
+* The functions now support strings longer than 2 GB.
+
+New in 1.14:
+* The 'iconv' program now produces its output as soon as it can. It no longer
+  unnecessarily waits for more input.
+* Updated the GB18030 converter to map 25 characters to code points that have
+  been to Unicode since 2000, rather than to code points in the Private Use
+  Area.
+* Updated the BIG5-HKSCS converter. The old BIG5-HKSCS converter is renamed to
+  BIG5-HKSCS:2004. A new converter BIG5-HKSCS:2008 is added. BIG5-HKSCS is now
+  an alias for BIG5-HKSCS:2008.
+* Fixed a bug in the conversion to wchar_t.
+* Fixed a small bug in the CP1258 converter.
+
+New in 1.13:
+* The library and the iconv program now understand platform dependent aliases,
+  for better compatibility with the platform's own iconv_open function.
+  Examples: "646" on Solaris, "iso88591" on HP-UX, "IBM-1252" on AIX.
+* For stateful encodings, when the input ends with a shift sequence followed
+  by invalid input, the iconv function now increments the input pointer past
+  the shift sequence before returning (size_t)(-1) with errno = EILSEQ. This
+  is also like GNU libc's iconv() behaves.
+* The library exports a new function iconv_open_into() that stores the
+  conversion descriptor in pre-allocated memory, rather than allocating fresh
+  memory for it.
+* Added CP1131 converter.
+
+New in 1.12:
+* The iconv program is now licensed under the GPL version 3, instead of the
+  GPL version 2. The libiconv library continues to be licensed under LGPL.
+* Added RK1048 converter.
+* On AIX, an existing system libiconv no longer causes setlocale() to fail.
+* Upgraded EUC-KR, JOHAB to include the Korean postal code sign.
+
+New in 1.11:
+* The iconv program has new options --unicode-subst, --byte-subst,
+  --widechar-subst that allow to specify substitutions for characters that
+  cannot be converted.
+* The iconv program now understands long options:
+    long option    equivalent to
+    --from-code    -f
+    --to-code      -t
+    --list         -l
+    --silent       -s
+* The CP936 converter is now different from the GBK converter: it has changed
+  to include the Euro sign and private area characters. CP936 is no longer an
+  alias of GBK.
+* Updated GB18030 converter to include all private area characters.
+* Updated CP950 converter to include the Euro sign and private area characters.
+* Updated CP949 converter to include private area characters.
+* Updated the BIG5-HKSCS converter. The old BIG5-HKSCS converter is renamed to
+  BIG5-HKSCS:1999 and updated to Unicode 4. New converters BIG5-HKSCS:2001 and
+  BIG5-HKSCS:2004 are added. BIG5-HKSCS is now an alias for BIG5-HKSCS:2004.
+* Added a few irreversible mappings to the CP932 converter.
+* Tidy up the list of symbols exported from libiconv (assumes gcc >= 4.0).
+
+New in 1.10:
+* Added ISO-8859-11 converter.
+* Updated the ISO-8859-7 converter.
+* Added ATARIST converter, available through --enable-extra-encodings.
+* Added BIG5-2003 converter (experimental), available through
+  --enable-extra-encodings.
+* Updated EUC-TW converter to include the Euro sign.
+* The preloadable library has been renamed from libiconv_plug.so to
+  preloadable_libiconv.so.
+* Portability to mingw.
+
+New in 1.9:
+* Many more transliterations.
+* New configuration option --enable-relocatable.  See the INSTALL.generic file
+  for details.
+
+New in 1.8:
+* The iconv program has new options -l, -c, -s.
+* The iconv program is internationalized.
+* Added C99 converter.
+* Added KOI8-T converter.
+* New configuration option --enable-extra-encodings that enables a bunch of
+  additional encodings; see the README for details.
+* Updated the ISO-8859-16 converter.
+* Upgraded BIG5-HKSCS, EUC-TW, ISO-2022-CN, ISO-2022-CN-EXT converters to
+  Unicode 3.2.
+* Upgraded EUC-KR, CP949, JOHAB converters to include the Euro sign.
+* Changed the ARMSCII-8 converter.
+* Extended the EUC-JP encoder so that YEN SIGN characters don't cause failures
+  in Shift_JIS to EUC-JP conversion.
+* The JAVA converter now handles characters outside the Unicode BMP correctly.
+* Fixed a bug in the CP1255, CP1258, TCVN decoders: The base characters of
+  combining characters could be dropped at the end of the conversion buffer.
+* Fixed a bug in the transliteration that could lead to excessive memory
+  allocations in libintl when transliteration was needed.
+* Portability to BSD/OS and SCO 3.2.5.
+
+New in 1.7:
+* Added UTF-32, UTF-32BE, UTF-32LE converters.
+* Changed CP1255, CP1258 and TCVN converters to handle combining characters.
+* Changed EUC-JP, SHIFT_JIS, CP932, ISO-2022-JP, ISO-2022-JP-2, ISO-2022-JP-1
+  converters to use fullwidth Yen sign instead of halfwidth Yen sign, and
+  fullwidth tilde instead of halfwidth tilde.
+* Upgraded EUC-TW, ISO-2022-CN, ISO-2022-CN-EXT converters to Unicode 3.1.
+* Changed the GB18030 converter to not reject unassigned and private-use
+  Unicode characters.
+* Fixed a bug in the byte order mark treatment of the UCS-4 decoder.
+* The manual pages are now distributed also in HTML format.
+
+New in 1.6:
+* The iconv program's -f and -t options are now optional.
+* Many more transliterations.
+* Added CP862 converter.
+* Changed the GB18030 converter.
+* Portability to DOS with DJGPP.
+
+New in 1.5:
+* Added an iconv(1) program.
+* New locale dependent encodings "char", "wchar_t".
+* Transliteration is now off by default. Use a //TRANSLIT suffix to enable it.
+* The JOHAB encoding is documented again.
+* Changed a few mappings in the CP950 converter.
+
+New in 1.4:
+* Added GB18030, BIG5HKSCS converters.
+* Portability to OS/2 with emx+gcc.
+
+New in 1.3:
+* Added UCS-2BE, UCS-2LE, UCS-4BE, UCS-4LE converters.
+* Fixed the definition of EILSEQ on SunOS4.
+* Fixed a build problem on OSF/1.
+* Support for building as a shared library on Woe32.
+
+New in 1.2:
+* Added UTF-16BE and UTF-16LE converters.
+* Changed the UTF-16 encoder.
+* Fixed the treatment of tab characters in the UTF-7 converter.
+* Fixed an internal error when output buffer was not large enough.
+
+New in 1.1:
+* Added ISO-8859-16 converter.
+* Added CP932 converter, a variant of SHIFT_JIS.
+* Added CP949 converter, a variant of EUC-KR.
+* Improved the ISO-2022-CN-EXT converter: It now covers the ISO-IR-165 range.
+* Updated the ISO-8859-8 conversion table.
+* The JOHAB encoding is deprecated and not documented any more.
+* Fixed two build problems: 1. "make -n check" failed. 2. When libiconv was
+  already installed, "make" failed.
+
+New in 1.0:
+* Added transliteration facilities.
+* Added a test suite.
+* Fixed the iconv(3) manual page and function: the return value was not
+  described correctly.
+* Fixed a bug in the CP1258 decoder: invalid bytes now yield EILSEQ instead of
+  U+FFFD.
+* Fixed a bug in the Georgian-PS encoder: accept U+00E6.
+* Fixed a bug in the EUC-JP encoder: reject 0x8E5C and 0x8E7E.
+* Fixed a bug in the KSC5601 and JOHAB converters: they recognized some Hangul
+  characters at some invalid code positions.
+* Fixed a bug in the EUC-TW decoder; it was severely broken.
+* Fixed a bug in the CP950 converter: it recognized a dubious BIG5 range.
+
+New in 0.3:
+* Reduced the size of the tables needed for the JOHAB converter.
+* Portability to Woe32.
+
+New in 0.2:
+* Added KOI8-RU, CP850, CP866, CP874, CP950, ISO-2022-CN-EXT, GBK and
+  ISO-2022-JP-1 converters.
+* Added MACINTOSH as an alias for MAC-ROMAN.
+* Added ASMO-708 as an alias for ISO-8859-6.
+* Added ELOT_928 as an alias for ISO-8859-7.
+* Improved the EUC-TW converter: Treat CNS 11643 plane 3.
+* Improved the ISO-2022-KR and EUC-KR converters: Hangul characters are
+  decomposed into Jamo when needed.
+* Improved the CP932 converter.
+* Updated the CP1133, MULELAO-1 and ARMSCII-8 mappings.
+* The EUC-JP and SHIFT_JIS converters now cover the user-defined range.
+* Fixed a possible buffer overrun in the JOHAB converter.
+* Fixed a bug in the UTF-7, ISO-2022-*, HZ decoders: a shift sequence a the
+  end of the input no longer gives an error.
+* The HZ encoder now always terminates its output in the ASCII state.
+* Use a perfect hash table for looking up the aliases.
+
+New in 0.1:
+* Portability to Linux/glibc-2.0.x, Linux/libc5, OSF/1, FreeBSD.
+* Fixed a bug in the EUC-JP decoder. Extended the ISO-2022-JP-2 converter.
+* Made TIS-620 mapping consistent with glibc-2.1.
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/README b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/README
new file mode 100644
index 0000000..19f8370
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/README
@@ -0,0 +1,172 @@
+            GNU LIBICONV - character set conversion library
+
+This library provides an iconv() implementation, for use on systems which
+don't have one, or whose implementation cannot convert from/to Unicode.
+
+It provides support for the encodings:
+
+    European languages
+        ASCII, ISO-8859-{1,2,3,4,5,7,9,10,13,14,15,16},
+        KOI8-R, KOI8-U, KOI8-RU,
+        CP{1250,1251,1252,1253,1254,1257}, CP{850,866,1131},
+        Mac{Roman,CentralEurope,Iceland,Croatian,Romania},
+        Mac{Cyrillic,Ukraine,Greek,Turkish},
+        Macintosh
+    Semitic languages
+        ISO-8859-{6,8}, CP{1255,1256}, CP862, Mac{Hebrew,Arabic}
+    Japanese
+        EUC-JP, SHIFT_JIS, CP932, ISO-2022-JP, ISO-2022-JP-2, ISO-2022-JP-1,
+        ISO-2022-JP-MS
+    Chinese
+        EUC-CN, HZ, GBK, CP936, GB18030, EUC-TW, BIG5, CP950, BIG5-HKSCS,
+        BIG5-HKSCS:2004, BIG5-HKSCS:2001, BIG5-HKSCS:1999, ISO-2022-CN,
+        ISO-2022-CN-EXT
+    Korean
+        EUC-KR, CP949, ISO-2022-KR, JOHAB
+    Armenian
+        ARMSCII-8
+    Georgian
+        Georgian-Academy, Georgian-PS
+    Tajik
+        KOI8-T
+    Kazakh
+        PT154, RK1048
+    Thai
+        ISO-8859-11, TIS-620, CP874, MacThai
+    Laotian
+        MuleLao-1, CP1133
+    Vietnamese
+        VISCII, TCVN, CP1258
+    Platform specifics
+        HP-ROMAN8, NEXTSTEP
+    Full Unicode
+        UTF-8
+        UCS-2, UCS-2BE, UCS-2LE
+        UCS-4, UCS-4BE, UCS-4LE
+        UTF-16, UTF-16BE, UTF-16LE
+        UTF-32, UTF-32BE, UTF-32LE
+        UTF-7
+        C99, JAVA
+    Full Unicode, in terms of 'uint16_t' or 'uint32_t'
+        (with machine dependent endianness and alignment)
+        UCS-2-INTERNAL, UCS-4-INTERNAL
+    Locale dependent, in terms of 'char' or 'wchar_t'
+        (with machine dependent endianness and alignment, and with OS and
+        locale dependent semantics)
+        char, wchar_t
+        The empty encoding name "" is equivalent to "char": it denotes the
+        locale dependent character encoding.
+
+When configured with the option --enable-extra-encodings, it also provides
+support for a few extra encodings:
+
+    European languages
+        CP{437,737,775,852,853,855,857,858,860,861,863,865,869,1125}
+    Semitic languages
+        CP864
+    Japanese
+        EUC-JISX0213, Shift_JISX0213, ISO-2022-JP-3
+    Chinese
+        BIG5-2003 (experimental)
+    Turkmen
+        TDS565
+    Platform specifics
+        ATARIST, RISCOS-LATIN1
+
+It can convert from any of these encodings to any other, through Unicode
+conversion.
+
+It has also some limited support for transliteration, i.e. when a character
+cannot be represented in the target character set, it can be approximated
+through one or several similarly looking characters. Transliteration is
+activated when "//TRANSLIT" is appended to the target encoding name.
+
+libiconv is for you if your application needs to support multiple character
+encodings, but that support lacks from your system.
+
+
+Installation
+------------
+
+As usual for GNU packages:
+
+    $ ./configure --prefix=/usr/local
+    $ make
+    $ make install
+
+After installing GNU libiconv for the first time, it is recommended to
+recompile and reinstall GNU gettext, so that it can take advantage of
+libiconv.
+
+On systems other than GNU/Linux, the iconv program will be internationalized
+only if GNU gettext has been built and installed before GNU libiconv. This
+means that the first time GNU libiconv is installed, we have a circular
+dependency between the GNU libiconv and GNU gettext packages, which can be
+resolved by building and installing either
+  - first libiconv, then gettext, then libiconv again,
+or (on systems supporting shared libraries, excluding AIX)
+  - first gettext, then libiconv, then gettext again.
+Recall that before building a package for the second time, you need to erase
+the traces of the first build by running "make distclean".
+
+This library can be built and installed in two variants:
+
+  - The library mode. This works on all systems, and uses a library
+    'libiconv.so' and a header file ''. (Both are installed
+    through "make install".)
+
+    To use it, simply #include  and use the functions.
+
+    To use it in an autoconfiguring package:
+    - If you don't use automake, append m4/iconv.m4 to your aclocal.m4
+      file.
+    - If you do use automake, add m4/iconv.m4 to your m4 macro repository.
+    - Add to the link command line of libraries and executables that use
+      the functions the placeholder @LIBICONV@ (or, if using libtool for
+      the link, @LTLIBICONV@). If you use automake, the right place for
+      these additions are the *_LDADD variables.
+    Note that 'iconv.m4' is also part of the GNU gettext package, which
+    installs it in /usr/local/share/aclocal/iconv.m4.
+
+  - The libc plug/override mode. This works on GNU/Linux, Solaris and OSF/1
+    systems only. It is a way to get good iconv support without having
+    glibc-2.1.
+    It installs a library 'preloadable_libiconv.so'. This library can be used
+    with LD_PRELOAD, to override the iconv* functions present in the C library.
+
+    On GNU/Linux and Solaris:
+        $ export LD_PRELOAD=/usr/local/lib/preloadable_libiconv.so
+
+    On OSF/1:
+        $ export _RLD_LIST=/usr/local/lib/preloadable_libiconv.so:DEFAULT
+
+    A program's source need not be modified, the program need not even be
+    recompiled. Just set the LD_PRELOAD environment variable, that's it!
+
+
+Copyright
+---------
+
+The libiconv and libcharset _libraries_ and their header files are under LGPL,
+see file COPYING.LIB.
+
+The iconv _program_ and the documentation are under GPL, see file COPYING.
+
+
+Download
+--------
+
+    http://ftp.gnu.org/gnu/libiconv/libiconv-1.15.tar.gz
+
+Homepage
+--------
+
+    http://www.gnu.org/software/libiconv/
+
+Bug reports to
+--------------
+
+    
+
+
+Bruno Haible 
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/README.djgpp b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/README.djgpp
new file mode 100644
index 0000000..aa8c420
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/README.djgpp
@@ -0,0 +1,3 @@
+Installation on DJGPP:
+
+See the file djgpp/README.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/README.windows b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/README.windows
new file mode 100644
index 0000000..7b8b508
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/README.windows
@@ -0,0 +1,255 @@
+Installation on Microsoft Windows:
+
+There are three ways to create binaries of this package for Microsoft Windows:
+1) Native binaries, built using the mingw tool chain.
+2) Native binaries, built using the MS Visual C/C++ tool chain.
+3) Binaries for the Cygwin environment.
+
+===============================================================================
+1) Native binaries, built using the mingw tool chain.
+
+   I recommend to use the Cygwin environment as the development environment
+   and mingw only as the target (runtime, deployment) environment.
+   For this, you need to install
+     * Cygwin (from https://cygwin.com/),
+     * some packages available from the Cygwin package installer:
+         make
+     * the mingw cross-compilation tools and runtime package, available from
+       the Cygwin package installer (setup-x86_64.exe):
+       - for creating 32-bit binaries: packages
+           mingw64-i686-gcc-core,
+           mingw64-i686-headers,
+           mingw64-i686-runtime
+       - for creating 64-bit binaries: packages
+           mingw64-x86_64-gcc-core,
+           mingw64-x86_64-headers,
+           mingw64-x86_64-runtime
+
+   Building 32-bit binaries for mingw is achieved through the following
+   preparation, configure, and build commands:
+
+      PATH=/usr/local/mingw32/bin:$PATH
+      export PATH
+      ./configure --host=i686-w64-mingw32 --prefix=/usr/local/mingw32 \
+            CC=i686-w64-mingw32-gcc \
+            CPPFLAGS="-I/usr/local/mingw32/include -Wall" \
+            LDFLAGS="-L/usr/local/mingw32/lib"
+      make
+      make check
+
+   Building 64-bit binaries for mingw is achieved through the following
+   preparation, configure, and build commands:
+
+      PATH=/usr/local/mingw64/bin:$PATH
+      export PATH
+      ./configure --host=x86_64-w64-mingw32 --prefix=/usr/local/mingw64 \
+            CC=x86_64-w64-mingw32-gcc \
+            CPPFLAGS="-I/usr/local/mingw64/include -Wall" \
+            LDFLAGS="-L/usr/local/mingw64/lib"
+      make
+      make check
+
+   Installation:
+
+      make install
+
+===============================================================================
+2) Native binaries, built using the MS Visual C/C++ tool chain.
+
+   Note that binaries created with MSVC have a distribution constraint: They
+   depend on a closed-source library ('msvcr90.dll' for MSVC 9.0,
+   'vcruntime140.dll' for MSVC 14.0, and so on) which is not normally part of
+   a Windows installation.
+   You cannot distribute 'vcruntime*.dll' with the binaries - this would be a
+   violation of the GPL and of the Microsoft EULA.
+   You can distribute the binaries without including 'vcruntime*.dll'. Users
+   who don't have this library on their system will require to pull some files
+   (api-ms-win*.dll) through the Windows Update mechanism, see
+   https://support.microsoft.com/en-us/kb/2999226 .
+
+   This recipe requires MS Visual C/C++ 9.0 or newer.
+   You don't need the Visual Studio IDE, just the C/C++ tool chain.
+   As of 2016, you can install the MS Visual C/C++ 14.0 tool chain from
+   http://landinghub.visualstudio.com/visual-cpp-build-tools (it's the file
+   visualcppbuildtools_full.exe).
+
+   This recipe requires also a Cygwin environment (with 'bash', the common POSIX
+   commands, and 'make') as a build environment. Building with 'nmake' is not
+   supported.
+   For this, you need to install
+     * Cygwin (from https://cygwin.com/),
+     * some packages available from the Cygwin package installer:
+         make
+
+   You also need the scripts 'ar-lib' and 'compile' from
+     http://git.savannah.gnu.org/gitweb/?p=automake.git;a=blob_plain;f=lib/ar-lib;hb=HEAD
+     http://git.savannah.gnu.org/gitweb/?p=automake.git;a=blob_plain;f=lib/compile;hb=HEAD
+   respectively.
+   They may also be included in this package, in directory 'build-aux/'.
+   Save them; the instructions below assume that you stored them in $HOME/msvc/.
+   Make them executable:
+      chmod a+x ar-lib compile
+
+   Start a bash (from Cygwin).
+
+   Make sure that the MSVC tools ("cl" etc.) are found in PATH and the
+   environment variables INCLUDE and LIB are set appropriately.
+   In a typical MSVC 9.0 installation, it can be achieved by running
+     C:\Program Files\Microsoft Visual Studio 9.0\Common7\Tools\vsvars32.bat
+   In a typical MSVC 14.0 installation on Windows 10, it can be achieved
+   - for creating 32-bit binaries: through the following bash commands:
+
+      # Set environment variables for using MSVC 14,
+      # for creating native 32-bit Windows executables.
+
+      # Windows C library headers and libraries.
+      WindowsCrtIncludeDir='C:\Program Files (x86)\Windows Kits\10\Include\10.0.10240.0\ucrt'
+      WindowsCrtLibDir='C:\Program Files (x86)\Windows Kits\10\Lib\10.0.10240.0\ucrt\'
+      INCLUDE="${WindowsCrtIncludeDir};$INCLUDE"
+      LIB="${WindowsCrtLibDir}x86;$LIB"
+
+      # Windows API headers and libraries.
+      WindowsSdkIncludeDir='C:\Program Files (x86)\Windows Kits\8.1\Include\'
+      WindowsSdkLibDir='C:\Program Files (x86)\Windows Kits\8.1\Lib\winv6.3\um\'
+      INCLUDE="${WindowsSdkIncludeDir}um;${WindowsSdkIncludeDir}shared;$INCLUDE"
+      LIB="${WindowsSdkLibDir}x86;$LIB"
+
+      # Visual C++ tools, headers and libraries.
+      VSINSTALLDIR='C:\Program Files (x86)\Microsoft Visual Studio 14.0'
+      VCINSTALLDIR="${VSINSTALLDIR}"'\VC'
+      PATH=`cygpath -u "${VCINSTALLDIR}"`/bin:"$PATH"
+      INCLUDE="${VCINSTALLDIR}"'\include;'"${INCLUDE}"
+      LIB="${VCINSTALLDIR}"'\lib;'"${LIB}"
+
+      export INCLUDE LIB
+
+   - for creating 64-bit binaries: through the following bash commands:
+
+     # Set environment variables for using MSVC 14,
+     # for creating native 64-bit Windows executables.
+
+     # Windows C library headers and libraries.
+     WindowsCrtIncludeDir='C:\Program Files (x86)\Windows Kits\10\Include\10.0.10240.0\ucrt'
+     WindowsCrtLibDir='C:\Program Files (x86)\Windows Kits\10\Lib\10.0.10240.0\ucrt\'
+     INCLUDE="${WindowsCrtIncludeDir};$INCLUDE"
+     LIB="${WindowsCrtLibDir}x64;$LIB"
+
+     # Windows API headers and libraries.
+     WindowsSdkIncludeDir='C:\Program Files (x86)\Windows Kits\8.1\Include\'
+     WindowsSdkLibDir='C:\Program Files (x86)\Windows Kits\8.1\Lib\winv6.3\um\'
+     INCLUDE="${WindowsSdkIncludeDir}um;${WindowsSdkIncludeDir}shared;$INCLUDE"
+     LIB="${WindowsSdkLibDir}x64;$LIB"
+
+     # Visual C++ tools, headers and libraries.
+     VSINSTALLDIR='C:\Program Files (x86)\Microsoft Visual Studio 14.0'
+     VCINSTALLDIR="${VSINSTALLDIR}"'\VC'
+     PATH=`cygpath -u "${VCINSTALLDIR}"`/bin/amd64:"$PATH"
+     INCLUDE="${VCINSTALLDIR}"'\include;'"${INCLUDE}"
+     LIB="${VCINSTALLDIR}"'\lib\amd64;'"${LIB}"
+
+     export INCLUDE LIB
+
+   Building 32-bit binaries with MSVC is achieved through the following
+   preparation, configure, and build commands:
+
+      PATH=/usr/local/msvc32/bin:$PATH
+      export PATH
+
+      win32_target=_WIN32_WINNT_WINXP   # for MSVC 9.0
+      win32_target=_WIN32_WINNT_VISTA   # possibly for MSVC >= 10.0
+      win32_target=_WIN32_WINNT_WIN7    # possibly for MSVC >= 10.0
+      win32_target=_WIN32_WINNT_WIN8    # possibly for MSVC >= 10.0
+
+      ./configure --host=i686-w64-mingw32 --prefix=/usr/local/msvc32 \
+            CC="$HOME/msvc/compile cl -nologo" \
+            CFLAGS="-MD" \
+            CXX="$HOME/msvc/compile cl -nologo" \
+            CXXFLAGS="-MD" \
+            CPPFLAGS="-D_WIN32_WINNT=$win32_target -I/usr/local/msvc32/include" \
+            LDFLAGS="-L/usr/local/msvc32/lib" \
+            LD="link" \
+            NM="dumpbin -symbols" \
+            STRIP=":" \
+            AR="$HOME/msvc/ar-lib lib" \
+            RANLIB=":"
+      make
+      make check
+
+   Building 64-bit binaries with MSVC is achieved through the following
+   preparation, configure, and build commands:
+
+      PATH=/usr/local/msvc64/bin:$PATH
+      export PATH
+
+      win32_target=_WIN32_WINNT_WINXP   # for MSVC 9.0
+      win32_target=_WIN32_WINNT_VISTA   # possibly for MSVC >= 10.0
+      win32_target=_WIN32_WINNT_WIN7    # possibly for MSVC >= 10.0
+      win32_target=_WIN32_WINNT_WIN8    # possibly for MSVC >= 10.0
+
+      ./configure --host=x86_64-w64-mingw32 --prefix=/usr/local/msvc64 \
+            CC="$HOME/msvc/compile cl -nologo" \
+            CFLAGS="-MD" \
+            CXX="$HOME/msvc/compile cl -nologo" \
+            CXXFLAGS="-MD" \
+            CPPFLAGS="-D_WIN32_WINNT=$win32_target -I/usr/local/msvc64/include" \
+            LDFLAGS="-L/usr/local/msvc64/lib" \
+            LD="link" \
+            NM="dumpbin -symbols" \
+            STRIP=":" \
+            AR="$HOME/msvc/ar-lib lib" \
+            RANLIB=":"
+      make
+      make check
+
+   Installation:
+
+      make install
+
+===============================================================================
+3) Binaries for the Cygwin environment.
+
+   The generic instructions in the INSTALL file apply. But here are more
+   specific ones.
+
+   You need to install
+     * Cygwin (from https://cygwin.com/),
+     * some packages available from the Cygwin package installer:
+         make
+     * the Cygwin [cross-]compilation tools package, available from
+       the Cygwin package installer (setup-x86_64.exe):
+       - for creating 32-bit binaries: packages
+           cygwin32-gcc-core,
+           cygwin32
+       - for creating 64-bit binaries: packages
+           gcc-core
+
+   Building 32-bit binaries for Cygwin must be done in a directory *outside*
+   the Cygwin /home and /usr hierarchies. It is achieved through the following
+   preparation, configure, and build commands:
+
+      PATH=/usr/local/cygwin32/bin:/usr/i686-pc-cygwin/sys-root/usr/bin:$PATH
+      export PATH
+      ./configure --host=i686-pc-cygwin --prefix=/usr/local/cygwin32 \
+            CC=i686-pc-cygwin-gcc \
+            CPPFLAGS="-I/usr/local/cygwin32/include -Wall" \
+            LDFLAGS="-L/usr/local/cygwin32/lib"
+      make
+      make check
+
+   Building 64-bit binaries for Cygwin is achieved through the following
+   preparation, configure, and build commands:
+
+      PATH=/usr/local/cygwin64/bin:$PATH
+      export PATH
+      ./configure --host=x86_64-pc-cygwin --prefix=/usr/local/cygwin64 \
+            CC=x86_64-pc-cygwin-gcc \
+            CPPFLAGS="-I/usr/local/cygwin64/include -Wall" \
+            LDFLAGS="-L/usr/local/cygwin64/lib"
+      make
+      make check
+
+   Installation:
+
+      make install
+
+===============================================================================
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/THANKS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/THANKS
new file mode 100644
index 0000000..a6f02ff
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libiconv-1.15/THANKS
@@ -0,0 +1,15 @@
+          Thanks to                               for
+
+Edmund Grimley Evans        bug reports
+
+Taro Muraoka             Woe32 DLL support
+
+Akira Hatakeyama             OS/2 support
+
+Juan Manuel Guerrero  
+                                              DOS/DJGPP support
+
+Hironori Sakamoto    advice on EUC-JP and JISX0213
+
+Ken Lunde                    detailed information about GB18030
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/AUTHORS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/AUTHORS
new file mode 100644
index 0000000..e90ad9b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/AUTHORS
@@ -0,0 +1,119 @@
+Copyright © 2001 Johannes Erdfelt 
+Copyright © 2007-2009 Daniel Drake 
+Copyright © 2010-2012 Peter Stuge 
+Copyright © 2008-2016 Nathan Hjelm 
+Copyright © 2009-2013 Pete Batard 
+Copyright © 2009-2013 Ludovic Rousseau 
+Copyright © 2010-2012 Michael Plante 
+Copyright © 2011-2013 Hans de Goede 
+Copyright © 2012-2013 Martin Pieuchot 
+Copyright © 2012-2013 Toby Gray 
+Copyright © 2013-2018 Chris Dickens 
+
+Other contributors:
+Adrian Bunk
+Akshay Jaggi
+Alan Ott
+Alan Stern
+Alex Vatchenko
+Andrew Fernandes
+Andy Chunyu
+Andy McFadden
+Angus Gratton
+Anil Nair
+Anthony Clay
+Antonio Ospite
+Artem Egorkine
+Aurelien Jarno
+Bastien Nocera
+Bei Zhang
+Benjamin Dobell
+Brent Rector
+Carl Karsten
+Christophe Zeitouny
+Colin Walters
+Dave Camarillo
+David Engraf
+David Moore
+Davidlohr Bueso
+Dmitry Fleytman
+Doug Johnston
+Evan Hunter
+Federico Manzan
+Felipe Balbi
+Florian Albrechtskirchinger
+Francesco Montorsi
+Francisco Facioni
+Gaurav Gupta
+Graeme Gill
+Gustavo Zacarias
+Hans Ulrich Niedermann
+Hector Martin
+Hoi-Ho Chan
+Ilya Konstantinov
+Jakub Klama
+James Hanko
+Jeffrey Nichols
+Johann Richard
+John Sheu
+Jonathon Jongsma
+Joost Muller
+Josh Gao
+Joshua Blake
+Justin Bischoff
+KIMURA Masaru
+Karsten Koenig
+Konrad Rzepecki
+Kuangye Guo
+Lars Kanis
+Lars Wirzenius
+Lei Chen
+Luca Longinotti
+Marcus Meissner
+Markus Heidelberg
+Martin Ettl
+Martin Koegler
+Matthew Stapleton
+Matthias Bolte
+Michel Zou
+Mike Frysinger
+Mikhail Gusarov
+Morgan Leborgne
+Moritz Fischer
+Ларионов Даниил
+Nicholas Corgan
+Omri Iluz
+Orin Eman
+Paul Fertser
+Pekka Nikander
+Rob Walker
+Romain Vimont
+Roman Kalashnikov
+Sameeh Jubran
+Sean McBride
+Sebastian Pipping
+Sergey Serb
+Simon Haggett
+Simon Newton
+Stefan Agner
+Stefan Tauner
+Steinar H. Gunderson
+Thomas Röfer
+Tim Hutt
+Tim Roberts
+Tobias Klauser
+Toby Peterson
+Tormod Volden
+Trygve Laugstøl
+Uri Lublin
+Vasily Khoruzhick
+Vegard Storheil Eriksen
+Venkatesh Shukla
+Vianney le Clément de Saint-Marcq
+Victor Toso
+Vitali Lovich
+William Skellenger
+Xiaofan Chen
+Zoltán Kovács
+Роман Донченко
+parafin
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/COPYING b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/COPYING
new file mode 100644
index 0000000..5ab7695
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/COPYING
@@ -0,0 +1,504 @@
+		  GNU LESSER GENERAL PUBLIC LICENSE
+		       Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+ 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL.  It also counts
+ as the successor of the GNU Library Public License, version 2, hence
+ the version number 2.1.]
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
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+
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+specially designated software packages--typically libraries--of the
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+can use it too, but we suggest you first think carefully about whether
+this license or the ordinary General Public License is the better
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+
+  When we speak of free software, we are referring to freedom of use,
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+
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+
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+  Most GNU software, including some libraries, is covered by the
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+is quite different from the ordinary General Public License.  We use
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+  When a program is linked with a library, whether statically or using
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+
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+That's all there is to it!
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+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/NEWS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/NEWS
new file mode 100644
index 0000000..07695ab
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/NEWS
@@ -0,0 +1,2 @@
+For the latest libusb news, please refer to the ChangeLog file, or visit:
+http://libusb.info
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/README b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/README
new file mode 100644
index 0000000..0e7228a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-1.0.22/README
@@ -0,0 +1,32 @@
+# libusb
+
+[![Build Status](https://travis-ci.org/libusb/libusb.svg?branch=master)](https://travis-ci.org/libusb/libusb)
+[![Build status](https://ci.appveyor.com/api/projects/status/xvrfam94jii4a6lw?svg=true)](https://ci.appveyor.com/project/LudovicRousseau/libusb)
+[![Coverity Scan Build Status](https://scan.coverity.com/projects/2180/badge.svg)](https://scan.coverity.com/projects/libusb-libusb)
+
+libusb is a library for USB device access from Linux, macOS,
+Windows, OpenBSD/NetBSD and Haiku userspace.
+It is written in C (Haiku backend in C++) and licensed under the GNU
+Lesser General Public License version 2.1 or, at your option, any later
+version (see [COPYING](COPYING)).
+
+libusb is abstracted internally in such a way that it can hopefully
+be ported to other operating systems. Please see the [PORTING](PORTING)
+file for more information.
+
+libusb homepage:
+http://libusb.info/
+
+Developers will wish to consult the API documentation:
+http://api.libusb.info
+
+Use the mailing list for questions, comments, etc:
+http://mailing-list.libusb.info
+
+- Hans de Goede 
+- Xiaofan Chen 
+- Ludovic Rousseau 
+- Nathan Hjelm 
+- Chris Dickens 
+
+(Please use the mailing list rather than mailing developers directly)
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/AUTHORS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/AUTHORS
new file mode 100644
index 0000000..d2beff9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/AUTHORS
@@ -0,0 +1,2 @@
+Daniel Drake 
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/COPYING b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/COPYING
new file mode 100644
index 0000000..5ab7695
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/COPYING
@@ -0,0 +1,504 @@
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+license would not permit royalty-free redistribution of the Library by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Library.
+
+If any portion of this section is held invalid or unenforceable under any
+particular circumstance, the balance of the section is intended to apply,
+and the section as a whole is intended to apply in other circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system which is
+implemented by public license practices.  Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+  12. If the distribution and/or use of the Library is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Library under this License may add
+an explicit geographical distribution limitation excluding those countries,
+so that distribution is permitted only in or among countries not thus
+excluded.  In such case, this License incorporates the limitation as if
+written in the body of this License.
+
+  13. The Free Software Foundation may publish revised and/or new
+versions of the Lesser General Public License from time to time.
+Such new versions will be similar in spirit to the present version,
+but may differ in detail to address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Library
+specifies a version number of this License which applies to it and
+"any later version", you have the option of following the terms and
+conditions either of that version or of any later version published by
+the Free Software Foundation.  If the Library does not specify a
+license version number, you may choose any version ever published by
+the Free Software Foundation.
+
+  14. If you wish to incorporate parts of the Library into other free
+programs whose distribution conditions are incompatible with these,
+write to the author to ask for permission.  For software which is
+copyrighted by the Free Software Foundation, write to the Free
+Software Foundation; we sometimes make exceptions for this.  Our
+decision will be guided by the two goals of preserving the free status
+of all derivatives of our free software and of promoting the sharing
+and reuse of software generally.
+
+			    NO WARRANTY
+
+  15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO
+WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
+EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
+OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY
+KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
+LIBRARY IS WITH YOU.  SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME
+THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+  16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
+WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY
+AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU
+FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE
+LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING
+RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A
+FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
+SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGES.
+
+		     END OF TERMS AND CONDITIONS
+
+           How to Apply These Terms to Your New Libraries
+
+  If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
+everyone can redistribute and change.  You can do so by permitting
+redistribution under these terms (or, alternatively, under the terms of the
+ordinary General Public License).
+
+  To apply these terms, attach the following notices to the library.  It is
+safest to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least the
+"copyright" line and a pointer to where the full notice is found.
+
+    
+    Copyright (C)   
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+Also add information on how to contact you by electronic and paper mail.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the library, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the
+  library `Frob' (a library for tweaking knobs) written by James Random Hacker.
+
+  , 1 April 1990
+  Ty Coon, President of Vice
+
+That's all there is to it!
+
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/LICENSE b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/LICENSE
new file mode 100644
index 0000000..f98680a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/LICENSE
@@ -0,0 +1,47 @@
+libusb is covered by the LGPL:
+
+This library is free software; you can redistribute it and/or
+modify it under the terms of the GNU Lesser General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+This library is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Lesser General Public License for more details.
+
+You should have received a copy of the GNU Lesser General Public
+License along with this library; if not, write to the
+Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+----
+
+Alternatively, the files usb.h.in and/or usb.h may be licensed under the
+BSD license:
+
+Copyright (c) 2000-2003 Johannes Erdfelt 
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+3. The name of the author may not be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/NEWS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/NEWS
new file mode 100644
index 0000000..05928ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/NEWS
@@ -0,0 +1,31 @@
+This file lists notable changes in each release. For the full history of all
+changes, see ChangeLog.
+
+2012-04-24: libusb-compat-0.1.4 release
+ * Change usb_*_write() prototypes to use const for read-only parameters
+ * Fix #42 usb_detach_kernel_driver_np() error mapping
+ * Prefer libtoolize over glibtoolize in autogen.sh
+
+2009-07-09: libusb-compat-0.1.3 release
+ * Fix cross-compiling
+ * Improved error code compatibility
+
+2009-06-11: libusb-compat-0.1.2 release
+ * Handle libusb initialization failure
+
+2009-05-28: libusb-compat-0.1.1 release
+ * Further improvements to match libusb-0.1 endpoint addressing behaviour
+
+2008-12-13: libusb-compat-0.1.0 release
+ * Documentation changes only
+
+2008-11-21: libusb-compat-0.1.0-beta3 release
+ * Bug fixes
+
+2008-06-28: libusb-compat-0.1.0-beta2 release
+ * Match libusb-0.1 endpoint addressing behaviour
+ * Update for libusb-0.9.1
+
+2008-05-25: libusb-compat-0.1.0-beta1 release
+ * Initial beta release
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/README b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/README
new file mode 100644
index 0000000..308bbc1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/libusb-compat-0.1.5/README
@@ -0,0 +1,46 @@
+libusb-compat-0.1
+=================
+
+A compatibility layer allowing applications written for libusb-0.1 to work
+with libusb-1.0. libusb-compat-0.1 attempts to look, feel, smell and walk
+like libusb-0.1.
+
+Do not attempt to install libusb-0.1 and libusb-compat-0.1 on the same system.
+
+Known quirks/differences from libusb-0.1:
+ 1. usb_resetep(), a previously deprecated function, is implemented as
+    equivalent to calling usb_clear_halt().
+ 2. libusb-0.1 allowed you to open a device which you did not have permission
+    to do anything useful with (all I/O requests would immediately fail).
+    libusb-compat-0.1 does not allow you to open such devices. You can still
+    read descriptor info without opening a device.
+ 3. usb_device's "num_children" attribute is hardcoded to 0, and "children"
+    is hardcoded to NULL. Do you need this information in your software? Let
+    us know on the mailing list, and we'll add it.
+ 4. Some libusb-0.1 users may have implemented I/O cancellation by running
+    transfers in their own threads and simply killing the thread when they
+    don't want to do the transfer any more. This is bad programming practice
+    for obvious reasons, and this lack of functionality was one of the primary
+    drivers for libusb-1.0 development. With libusb-1.0 or libusb-compat-0.1
+    backed by libusb-1.0, forcefully killing threads in this way is likely
+    to cause all libusb I/O to halt. Instead, port your application to use
+    libusb-1.0's asynchronous transfer API, which supports transfer
+    cancellation.
+ 5. Error codes returned on certain events may not exactly match the error
+    codes returned by libusb-0.1. Patches accepted to bring us closer to the
+    behaviour of libusb-0.1 on Linux.
+ 6. The internal structure of usb_dev_handle is different from libusb-0.1. Of
+    course, since this is a purely internal structure, that shouldn't cause
+    any problems. In reality, some libusb-0.1 users make assumptions about what
+    is inside (bad programming practice) and those assumptions are no longer
+    true, resulting in broken software.
+
+libusb homepage:
+http://libusb.org/
+
+Use the mailing list for questions, comments, etc:
+https://sourceforge.net/mailarchive/forum.php?forum_name=libusb-devel
+
+- Peter Stuge 
+(use the mailing list rather than mailing developers directly)
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/AUTHORS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/AUTHORS
new file mode 100644
index 0000000..7489834
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/AUTHORS
@@ -0,0 +1,2 @@
+Please check the source code files and/or Git history for a list of all authors
+and contributors.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/AUTHORS.ChangeLog b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/AUTHORS.ChangeLog
new file mode 100644
index 0000000..b2b5e6b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/AUTHORS.ChangeLog
@@ -0,0 +1,10 @@
+drath:Dominic Rath 
+mlu:Magnus Lundin 
+mifi:Michael Fischer 
+ntfreak:Spencer Oliver 
+duane:Duane Ellis 
+oharboe:Øyvind Harboe 
+kc8apf:Rick Altherr 
+zwelch:Zachary T Welch 
+vpalatin:Vincent Palatin 
+bodylove:Carsten Schlote 
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/COPYING b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/COPYING
new file mode 100644
index 0000000..0e8db92
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/COPYING
@@ -0,0 +1,16 @@
+OpenOCD is provided under:
+
+	SPDX-License-Identifier: GPL-2.0-or-later
+
+Being under the terms of the GNU General Public License version 2 or
+later, according with:
+
+	LICENSES/preferred/GPL-2.0
+
+In addition, other licenses may also apply. Please see:
+
+	LICENSES/license-rules.txt
+
+for more details.
+
+All contributions to OpenOCD are subject to this COPYING file.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS
new file mode 100644
index 0000000..9db6c5f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS
@@ -0,0 +1,35 @@
+This file includes highlights of the changes made in the OpenOCD
+source archive release.
+
+JTAG Layer:
+
+Boundary Scan:
+
+Target Layer:
+
+Flash Layer:
+
+Board, Target, and Interface Configuration Scripts:
+
+Server Layer:
+
+RTOS:
+
+Documentation:
+
+Build and Release:
+
+
+This release also contains a number of other important functional and
+cosmetic bugfixes. For more details about what has changed since the
+last release, see the git repository history:
+
+http://sourceforge.net/p/openocd/code/ci/v0.x.0/log/?path=
+
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.10.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.10.0
new file mode 100644
index 0000000..e3b1e25
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.10.0
@@ -0,0 +1,155 @@
+This file includes highlights of the changes made in the OpenOCD
+source archive release.
+
+JTAG Layer:
+	* New driver for J-Link adapters based on libjaylink
+          (including support for FPGA configuration, SWO and EMUCOM)
+	* FTDI improvements to work at 30MHz clock
+	* BCM2835 native driver SWD and Raspberry Pi2 support
+	* BCM2835 is set to 4ma drive, slow slew rate
+	* ixo-usb-jtag (emulation of an Altera Bus Blaster I on
+          Cypress FX2 IC) support
+	* JTAG pass-through mode for CMSIS-DAP (including support for
+          FPGA configuration)
+	* OpenJTAG support for Cypress CY7C65215
+	* connect_assert_srst support for SWD
+	* Xilinx Virtex-II Series7 bitstream loading support
+	* Use JEP106 data to decode IDs
+	* Deprecated "ft2232" driver removed (use "ftdi" instead)
+	* GPL-incompatible FTDI D2XX library support dropped (Presto,
+          OpenJTAG and USB-Blaster I are using libftdi only now)
+	* ZY1000 support dropped (unmaintained since long)
+	* oocd_trace support dropped
+
+Boundary Scan:
+
+Target Layer:
+	* ARMv7-A, Cortex-M, Cortex-A/R important fixes and
+          improvements (allowing e.g. simultaneous debugging of A8 and
+          M3 cores, JTAG WAIT support etc.)
+	* ARM Cortex-A,R allow interrupt disable during single-step
+          (maskisr command)
+	* Semihosting support for ARMv7-A
+	* ARM Cortex-M7 support
+	* Intel Quark mcu D2000 support
+	* Freescale LS102x SAP support
+	* ThreadX RTOS support on ARM926E-JS
+	* Cortex-M RTOS stack alignment fixes
+	* FreeRTOS FPU support
+	* uC/OS-III RTOS support
+	* bridging semihosting to GDB's File-I/O support
+	* -defer-examine option added to target create command
+	* verify_image_checksum command added
+
+Flash Layer:
+	* Atmel SAM4S, SAM4N, SAM4C support
+	* Atmel SAMV, SAMS, SAME (Cortex-M7) support
+	* Atmel AT91SAMD handle reset run/halt in DSU, other fixes
+	* Atmel AT91SAML21, SAML22, SAMC20/SAMC21, SAMD09 support
+	* ST STM32F4x support
+	* ST STM32F74x/76x/77x, STM32L4 support
+	* ST STM32L0 categories 1, 2 and 5 support
+	* Kinetis K02, K21, K22, K24, K26, K63, K64, K66 support
+	* Kinetis KE, KVx, K8x families support
+	* Kinetis FlexNVM handling
+	* Kinetis flash protection, security, mass_erase improvements
+	* Infineon XMC4xxx family support
+	* Infineon XMC1000 flash driver
+	* Energy Micro EFM32 Happy Gecko support
+	* Energy Micro EFM32 debug interface lock support
+	* Analog Devices ADuCM360 support
+	* Unified Nuvoton NuMicro flash driver
+	* NIIET K1921VK01T (Cortex-M4) support
+	* Nordic Semiconductor nRF51 improvements
+	* Spansion FM4 flash (including MB9BFx64/x65, S6E2DH) driver
+	* Ambiq Micro Apollo flash driver
+	* PIC32MX new device IDs, 17x/27x flash support
+	* read_bank() and verify_bank() NOR flash internal API to
+          allow reading (and verifying) non-memory-mapped devices
+	* JTAGSPI driver to access SPI NOR flashes via a trivial
+          FPGA proxy
+	* Milandr read/verify for Info memory support
+	* Various discrete SPI NOR flashes support
+	* CFI 16-bit flash reversed endianness support
+
+Board, Target, and Interface Configuration Scripts:
+	* Digilent JTAG-HS2, JTAG-HS3 interfaces configs
+	* FTDI UM232H module as JTAG interface config
+	* 100ask's OpenJTAG interface config
+	* MBFTDI interface config
+	* XDS100v3 interface config
+	* Freescale Vybrid VF6xx target config
+	* EmCraft VF6 SOM and baseboard configs
+	* Freescale SabreSD board config
+	* Freescale VF65GS10 tower board config
+	* Pipistrello Xilinx Spartan6 LX45 FPGA board config
+	* miniSpartan6+ board config
+	* Xilinx Kintex7 Development board config
+	* Parallella-I board config
+	* Digilent Atlys and Analog Discovery board configs
+	* Numato Opsis board config
+	* Xilinx Spartan 6 FPGA "Device DNA" reading support
+	* Altera 10M50 FPGA (MAX10 family) target config
+	* Altera EPM240 CPLD (MAXII family) target config
+	* Marsohod2, Marsohod3 FPGA, Marsohod CPLD boards configs
+	* Novena's integrated FPGA board config
+	* XMOS XS1-XAU8A-10's ARM core config
+	* XMOS xCORE-XA Core Module board config
+	* Exynos5250 target config
+	* Arndale board config
+	* FM4 MB9BFxxx family configs
+	* Spansion SK-FM4-U120-9B560 board config
+	* Diolan LPC4357-DB1 board config
+	* ST STM32F469 discovery board config
+	* ST STM32F7-DISCO, STM327[4|5]6G-EVAL boards configs
+	* ST STM32L4 discovery, NUCLEO L476RG, STM32F429I-DISC1 boards
+          configs
+	* Atheros AR2313, AR2315 targets config
+	* Netgear WP102 board config
+	* La Fonera FON2200 board config
+	* Linksys WAG200G board config
+	* LPC-Link2 board config
+	* NXP LPC4370 target config
+	* Atmel SAMV, SAMS, SAME target configs
+	* Atmel SAM E70 Xplained, SAM V71 Xplained Ultra boards
+          configs
+	* Nordic nRF52 target config
+	* Nordic nRF51-DK, nRF52-DK boards configs
+	* Infineon XMC4700 Relax Kit, XMC4800 Relax EtherCAT Kit,
+          XMC4300 Relax EtherCAT Kit boards configs
+	* Renesas S7G2 target config
+	* Renesas DK-S7G2 board config
+	* Altera EP3C10 FPGA (Cyclone III family) target config
+	* TI MSP432P4xx target config
+	* Cypress PSoC 5LP target config
+	* Analog Devices ADSP-SC58x target config (Cortex-A5 core only)
+
+Server Layer:
+	* tcl_trace command for async target trace output via Tcl RPC
+
+Documentation:
+
+Build and Release:
+	* Various fixes thanks to http://coccinellery.org/
+	* libftdi is now autodetected with pkgconfig
+	* Releases should now support reproducible builds
+	* Conversion to non-recursive make, requires automake >= 1.14
+	* Udev rules modified to add uaccess tag and moved to
+          60-openocd.rules
+	* Support searching for scripts relative to the openocd binary
+          for all major architectures
+
+
+This release also contains a number of other important functional and
+cosmetic bugfixes. For more details about what has changed since the
+last release, see the git repository history:
+
+http://sourceforge.net/p/openocd/code/ci/v0.10.0/log/?path=
+
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.11.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.11.0
new file mode 100644
index 0000000..4542aa2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.11.0
@@ -0,0 +1,238 @@
+This file includes highlights of the changes made in the OpenOCD
+source archive release.
+
+JTAG Layer:
+	* add debug level 4 for verbose I/O debug
+	* bitbang, add read buffer to improve performance
+	* Cadence SystemVerilog Direct Programming Interface (DPI) adapter driver
+	* CMSIS-DAP v2 (USB bulk based) adapter driver
+	* Cypress KitProg adapter driver
+	* FTDI FT232R sync bitbang adapter driver
+	* Linux GPIOD bitbang adapter driver through libgpiod
+	* Mellanox rshim USB or PCIe adapter driver
+	* Nuvoton Nu-Link and Nu-Link2 adapter drivers
+	* NXP IMX GPIO mmap based adapter driver
+	* ST-Link consolidate all versions in single config
+	* ST-Link read properly old USB serial numbers
+	* STLink/V3 support (for ST devices only !)
+	* STM8 SWIM transport
+	* TI XDS110 adapter driver
+	* Xilinx XVC/PCIe adapter driver
+
+Boundary Scan:
+
+Target Layer:
+	* 64 bit address support
+	* ARCv2 target support
+	* ARM Cortex-A hypervisor mode support
+	* ARM Cortex-M fast PC sampling support for profiling
+	* ARM generic CTI support
+	* ARM generic mem-ap target support
+	* ARMv7-A MMU tools
+	* ARMv7m traces add TCP stream server
+	* ARMv8 AARCH64 target support and semihosting support
+	* ARMv8 AARCH64 disassembler support through capstone library
+	* ARMv8-M target support
+	* EnSilica eSi-RISC target support, including instruction tracing
+          eSi-Trace support
+	* MIPS64 target support
+	* Motorola SREC S6 record image file support
+	* RISC-V target support
+	* SEGGER Real Time Transfer (RTT) initial support (for single target,
+	  Cortex-M only)
+	* ST STM8 target support
+	* Various MIPS32 target improvements
+
+Flash Layer:
+	* Atheros (ath79) SPI interface support
+	* Atmel atmega128rfa1 support
+	* Atmel SAM D21, D51, DA1, E51, E53, E54, G55, R30 support
+	* Atmel SAMC2?N* support
+	* Cypress PSoC5LP, PSoC6 support
+	* EnSilica eSi-RISC support
+	* Foshan Synwit Tech SWM050 support
+	* Maxim Integrated MAX32XXX support
+	* Nordic Semiconductor nRF51822, nRF52810, nRF52832 support
+	* NXP Kinetis K27, K28, KE1x, KEAx, KL28, KL8x, KV5x, KWx support
+	* Renesas RPC HF support
+	* SH QSPI support
+	* SiFive Freedom E support
+	* Silicon Labs EFR-family, EZR32HG support
+	* ST BlueNRG support
+	* ST STM32 QUAD/OCTO-SPI interface support for Flash, FRAM and EEPROM
+	* ST STM32F72x, STM32F4x3, STM32H7xx support
+	* ST STM32G0xx, STM32G4xx, STM32L4x, STM32WB, STM32WL support
+	* ST STM32L5x support (non secure mode)
+	* TI CC13xx, CC26xx, CC32xx support
+	* TI MSP432 support
+	* Winner Micro w600 support
+	* Xilinx XCF platform support
+	* Various discrete SPI NOR flashes support
+
+Board, Target, and Interface Configuration Scripts:
+	* 8devices LIMA board config
+	* Achilles Instant-Development Kit Arria 10 board config
+	* Amazon Kindle 2 and DX board config
+	* Analog Devices ADSP-SC58x, ADSP-SC584-EZBRD board config
+	* Andes Technology ADP-XC7KFF676 board config
+	* Andes Technology Corvette-F1 board config
+	* ARM Musca A board config
+	* Arty Spartan 7 FPGA board config
+	* Atmel SAMD10 Xplained mini board config
+	* Atmel SAMD11 Xplained Pro board config
+	* Atmel SAM G55 Xplained Pro board config
+	* AVNET UltraZED EG StarterKit board config
+	* Blue Pill STM32F103C8 board config
+	* DP Busblaster v4.1a board config
+	* DPTechnics DPT-Board-v1 board config
+	* Emcraft imx8 SOM BSB board config
+	* Globalscale ESPRESSObin board config
+	* Kasli board config
+	* Kintex Ultrascale XCKU040 board config
+	* Knovative KC-100 board config
+	* LeMaker HiKey board config
+	* Microchip (Atmel) SAME54 Xplained Pro board config
+	* Microchip (Atmel) SAML11 Xplained Pro board config
+	* Nordic module NRF52 board config
+	* Numato Lab Mimas A7 board config
+	* NXP Freedom FRDM-LS1012A board config
+	* NXP IMX7SABRE board config
+	* NXP IMX8MP-EVK board config
+	* NXP MC-IMX8M-EVK board config
+	* QuickLogic QuickFeather board config
+	* Renesas R-Car E2, H2, M2 board config
+	* Renesas R-Car Salvator-X(S) board config
+	* Renesas RZ/A1H GR-Peach board config
+	* Rigado BMD-300 board config
+	* Sayma AMC board config
+	* Sifive e31arty, e51arty, hifive1 board config
+	* ST B-L475E-IOT01A board config
+	* ST BlueNRG idb007v1, idb008v1, idb011v1 board config
+	* ST STM32F412g discovery board config
+	* ST STM32F413h discovery board config
+	* ST STM32F469i discovery board config
+	* ST STM32F7 Nucleo board config
+	* ST STM32F723e discovery board config
+	* ST STM32F746g discovery board config
+	* ST STM32F769i discovery board config
+	* ST STM32H735g discovery board config
+	* ST STM32H743zi Nucleo board config
+	* ST STM32H745i discovery board config
+	* ST STM32H747i discovery board config
+	* ST STM32H750b discovery board config
+	* ST STM32H7b3i discovery board config
+	* ST STM32H7x_dual_qspi board config
+	* ST STM32H7x3i Eval boards config
+	* ST STM32L073 Nucleo board config
+	* ST STM32L476g discovery board config
+	* ST STM32L496g discovery board config
+	* ST STM32L4p5g discovery board config
+	* ST STM32L4r9i discovery board config
+	* ST STM32L5 Nucleo board config
+	* ST STM32MP15x DK2 board config
+	* ST STM32WB Nucleo board config
+	* ST STM8L152R8 Nucleo board config
+	* Synopsys DesignWare ARC EM board config
+	* Synopsys DesignWare ARC HSDK board config
+	* TI BeagleBone family boards config
+	* TI CC13xx, CC26xx, CC32xx LaunchPad board config
+	* TI MSP432 LaunchPad board config
+	* Tocoding Poplar board config
+	* TP-Link WDR4300 board config
+	* Allwinner V3s target config
+	* Andes Technology NDS V5 target config
+	* Atmel atmega128rfa1 target config
+	* ARM corelink SSE-200 target config
+	* Atheros_ar9344 target config
+	* Cypress PSoC5LP, PSoC6 target config
+	* EnSilica eSi-RISC target config
+	* Foshan Synwit Tech SWM050 target config
+	* GigaDevice GD32VF103 target config
+	* Hisilicon Hi3798 target config
+	* Hisilicon Hi6220 target config
+	* Infineon TLE987x target config
+	* Marvell Armada 3700 target config
+	* Maxim Integrated MAX32XXX target config
+	* Mellanox BlueField target config
+	* Microchip (Atmel) SAME5x, SAML1x target config
+	* NXP IMX6SX, IMX6UL, IMX7, IMX7ULP, IMX8 target config
+	* NXP Kinetis KE1xZ, KE1xF target config
+	* NXP LPC84x, LPC8Nxx, LS1012A, NHS31xx target config
+	* Qualcomm QCA4531 target config
+	* QuickLogic EOS S3 target config
+	* Renesas R-Car E2, H2, M2 target config
+	* Renesas R-Car Gen3 target config
+	* Renesas RZ/A1H target config
+	* Rockchip RK3308 target config
+	* ST BlueNRG target config
+	* ST STM32G0, STM32G4, STM32H7, STM32L0, STM32L5 target config
+	* ST STM32MP15x target config
+	* ST STM32WBx, STM32WLEx target config
+	* ST STM8L152, S003, S103, S105 target config
+	* Synopsys DesignWare ARC EM target config
+	* Synopsys DesignWare ARC HS Development Kit SoC target config
+	* TI CC13xx, CC26xx, CC32xx target config
+	* TI TNETC4401 target config
+	* Xilinx UltraScale+ target config
+	* Altera 5M570Z (MAXV family) CPLD config
+	* Xilinx Ultrascale, XCF CPLD config
+	* Intel (Altera) Arria10 FPGA config
+	* Cadence SystemVerilog Direct Programming Interface (DPI) interface config
+	* Cypress KitProg interface config
+	* Digilent SMT2 NC interface config
+	* DLN-2 example of Linux GPIOD interface config
+	* FTDI C232HM interface config
+	* HIE JTAG Debugger interface config
+	* In-Circuit's ICprog interface config
+	* isodebug isolated JTAG/SWD+UART interface config
+	* Mellanox rshim USB or PCIe interface config
+	* Nuvoton Nu-Link interface config
+	* NXP IMX GPIO mmap based interface config
+	* Steppenprobe open hardware interface config
+	* TI XDS110 interface config
+
+Server Layer:
+	* 64 bit address support
+	* default bind to IPv4 localhost
+	* gdb: allow multiple connections
+	* gdb: architecture element support
+	* gdb: vCont, vRun support
+	* telnet: handle Ctrl+A, Ctrl+E and Ctrl+K
+
+RTOS:
+	* Chromium-EC rtos support
+	* hwthread pseudo rtos support
+	* NuttX rtos support
+	* RIOT rtos support
+
+Documentation:
+	* Improve STM32 flash driver
+	* Various typo fix and improvements
+
+Build and Release:
+	* Add libutil to support jimtcl version 0.80
+	* Clang warning fixes
+	* GitHub workflow for Win32 snapshot binaries
+	* Handle Tcl return values consistently
+	* Mitigation for CVE-2018-5704: Prevent some forms of Cross
+          Protocol Scripting attacks
+	* Support for libftdi 1.5
+	* Travis-CI basic support
+	* Update libjaylink to version 0.2.0
+	* Update jimtcl to version 0.79
+	* Use external (optional) library capstone for ARM and AARCH64 disassembly
+
+
+This release also contains a number of other important functional and
+cosmetic bugfixes. For more details about what has changed since the
+last release, see the git repository history:
+
+http://sourceforge.net/p/openocd/code/ci/v0.11.0/log/?path=
+
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.12.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.12.0
new file mode 100644
index 0000000..208146a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.12.0
@@ -0,0 +1,132 @@
+This file includes highlights of the changes made in the OpenOCD
+source archive release.
+
+JTAG Layer:
+	* add default to adapter speed when unspecified (100 kHz)
+	* AM335X gpio (BeagleBones) adapter driver
+	* BCM2835 support for SWD
+	* Cadence Virtual Debug (vdebug) adapter driver
+	* CMSIS-DAP support for SWO and SWD multidrop
+	* Espressif USB JTAG Programmer adapter driver
+	* Remote bitbang support for Windows host
+	* ST-LINK add TCP server support to adapter driver
+	* SWD multidrop support
+
+Boundary Scan:
+
+Target Layer:
+	* aarch64: support watchpoints
+	* arm: support independent TPIU and SWO for trace
+	* arm adi v5: support Large Physical Address Extension
+	* arm adi v6: support added, for jtag and swd transport
+	* cortex_a: support watchpoints
+	* elf 64bit load support
+	* Espressif: support ESP32, ESP32-S2 and ESP32-S3 cores
+	* semihosting: support user defined operations
+	* Xtensa: support Xtensa LX architecture via JTAG and ADIv5 DAP
+
+Flash Layer:
+	* Atmel/Microchip SAM E51G18A, E51G19A, R35J18B, LAN9255 support
+	* GigaDevice GD32E23x, GD32F1x0/3x0, GD32VF103 support
+	* Nuvoton NPCX series support
+	* onsemi RSL10 support
+	* Raspberry Pi Pico RP2040 support
+	* ST BlueNRG-LPS support
+	* ST STM32 G05x, G06x, G0Bx, G0Cx, U57x, U58x, WB1x, WL5x support
+	* ST STM32 G0, G4, L4, L4+, L5, WB, WL OTP support
+
+Board, Target, and Interface Configuration Scripts:
+	* Ampere Computing eMAG8180, Altra ("Quicksilver") and Altra Max ("Mystique") board config
+	* Cadence KC705 FPGA (Xtensa Development Platform) via JTAG and ADIv5 DAP board config
+	* Digilent Nexys Video board config
+	* Espressif ESP32 ETHERNET-KIT and WROVER-KIT board config
+	* Espressif ESP32 via ESP USB Bridge generic board config
+	* Espressif ESP32-S2 Kaluga 1 board config
+	* Espressif ESP32-S2 with ESP USB Bridge board config
+	* Espressif ESP32-S3 example board config
+	* Kontron SMARC-sAL28 board config
+	* LambdaConcept ECPIX-5 board config
+	* Microchip ATSAMA5D27-SOM1-EK1 board config
+	* Microchip EVB-LAN9255 board config
+	* Microchip SAME51 Curiosity Nano board config
+	* NXP FRDM-K64F, LS1046ARDB and LS1088ARDB board config
+	* NXP RT6XX board config
+	* Olimex H405 board config
+	* Radiona ULX3S board config
+	* Raspberry Pi 3 and Raspberry Pi 4 model B board config
+	* Raspberry Pi Pico-Debug board config
+	* Renesas R-Car V3U Falcon board config
+	* ST BlueNRG-LPS steval-idb012v1 board config
+	* ST NUCLEO-8S208RB board config
+	* ST NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB board config
+	* ST NUCLEO-G431KB, NUCLEO-G431RB, NUCLEO-G474RE board config
+	* ST STM32MP13x-DK board config
+	* TI AM625 EVM, AM642 EVM and AM654 EVM board config
+	* TI J721E EVM, J721S2 EVM and J7200 EVM board config
+	* Ampere Computing eMAG, Altra ("Quicksilver") and Altra Max ("Mystique") target config
+	* Cadence Xtensa generic and Xtensa VDebug target config
+	* Broadcom BCM2711, BCM2835, BCM2836 and BCM2837 target config
+	* Espressif ESP32, ESP32-S2 and ESP32-S3 target config
+	* Microchip ATSAMA5D2 series target config
+	* NanoXplore NG-Ultra SoC target config
+	* NXP IMX8QM target config
+	* NXP LS1028A, LS1046A and LS1088A target config
+	* NXP RT600 (Xtensa HiFi DSP) target config
+	* onsemi RSL10 target config
+	* Raspberry Pi Pico RP2040 target config
+	* Renesas R8A779A0 V3U target config
+	* Renesas RZ/Five target config
+	* Renesas RZ/G2 MPU family target config
+	* Rockchip RK3399 target config
+	* ST BlueNRG-LPS target config
+	* ST STM32MP13x target config
+	* TI AM625, AM654, J721E and J721S2 target config
+	* Ashling Opella-LD interface config
+	* Aspeed AST2600 linuxgpiod based interface config
+	* Blinkinlabs JTAG_Hat interface config
+	* Cadence Virtual Debug (vdebug) interface config
+	* Espressif ESP32-S2 Kaluga 1 board's interface config
+	* Espressif USB Bridge jtag interface config
+	* Infineon DAP miniWiggler V3 interface config
+	* PLS SPC5 interface config
+	* Tigard interface config
+	* Lattice MachXO3 family FPGA config
+
+Server Layer:
+	* GDB: add per-target remote protocol extensions
+	* GDB: more 'Z' packets support
+	* IPDBG JtagHost server functionality
+	* semihosting: I/O redirection to TCP server
+	* telnet: support for command's autocomplete
+
+RTOS:
+	* 'none' rtos support
+	* Zephyr rtos support
+
+Documentation:
+
+Build and Release:
+	* Add json extension to jimtcl build
+	* Drop dependency from libusb0
+	* Drop repository repo.or.cz for submodules
+	* Move gerrit to https://review.openocd.org/
+	* Require autoconf 2.69 or newer
+	* Update jep106 to revision JEP106BF.01
+	* Update jimtcl to version 0.81
+	* Update libjaylink to version 0.3.1
+	* New configure flag '--enable-jimtcl-maintainer' for jimtcl build
+
+
+This release also contains a number of other important functional and
+cosmetic bugfixes. For more details about what has changed since the
+last release, see the git repository history:
+
+http://sourceforge.net/p/openocd/code/ci/v0.12.0/log/?path=
+
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.2.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.2.0
new file mode 100644
index 0000000..7426926
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.2.0
@@ -0,0 +1,80 @@
+The OpenOCD 0.2.0 source archive release includes numerous improvements
+that were made since the initial 0.1.0 source archive release.  Many
+contributors helped make this release a great success, and the community
+of developers and maintainers look forward to any response.
+
+In addition to the list of changes below, countless bug fixing and
+cleaning was performed across the tree.  Various TCL command parameters
+must past stricter value checks, and many more error conditions have
+been handled correctly.  These efforts helped to make the 0.2.0 release
+more stable and robust, though some changes may expose latent bugs in
+your existing configuration scripts.
+
+This release does not maintain backward compatibility in all respects,
+so some target or configuration scripts may need to be updated.  In some
+cases, you may also see warnings; resolve those, because they indicate
+commands that will be removed in the future.
+
+The following areas of OpenOCD functionality changed in this release:
+
+JTAG Layer:
+- Improves modularity: core, TCL, driver commands, and interface have
+  been separated, encapsulated, and documented for developers.  Mostly.
+- Improves JTAG TAP transition tables:
+   * Makes TAP paths variable length, rather than being fixed at 7 steps.
+   * Fixes problems with some targets that did not like longer paths.
+- Improves JTAG driver/minidriver modularity and encapsulation.
+- New drivers:
+   * Adds stub minidriver for developing new embedded JTAG interfaces.
+- Improves drivers:
+   * ft2232+ftd2xx:
+      + Adds initial high-speed device support: --enable-ftd2xx-highspeed
+      + Supports more types of FTDI-based devices.
+   * jlink:
+      + Works with more versions of the firmware (v3 and newer)
+      + Supports dynamically detects device capabilities and limits
+   * vsllink:
+      + Supports very long scan chains
+   * amtjtagaccel:
+      + Fixes broken ID code detection problems.
+
+Target Layer:
+- New devices: AVR, FA526
+- Improved support: ARM ADI, ARM11, MIPS
+- Numerous other bug fixes and improvements
+
+Flash Layer:
+- Improved drivers: mflash
+- New drivers: AT91SAM3, AVR, Davinci NAND
+
+Board, Interface, and Target Configuration Scripts:
+- Many new and improved targets and boards are now available.
+- Better separation of "board" and "target" configuration
+- Moved all TCL files to top-level "tcl" directory in the source tree
+- Installation moved from '$pkglibdir/' to '$pkgdatadir/scripts/'.
+- Site-specific files should be installed under '$pkgdatadir/site/';
+  files that exist this tree will be used in preference to default
+  distribution configurations in '$pkgdatadir/scripts/'.
+
+Documentation:
+- Updated User Guide:     http://openocd.berlios.de/doc/html/index.html
+   * Partially re-written and re-organized.
+   * Standardized presentation for all commands.
+   * Covers many drivers and commands that were previously omitted.
+   * New index for commands and drivers.
+- Added Developer Manual: http://openocd.berlios.de/doc/doxygen/index.html
+   * Now includes architecture, technical primers, style guides, and more.
+   * Available in-tree and on-line.
+
+Build and Release:
+- Increased configuration and compilation warning coverage.
+   * Use --disable-werror to work around build errors caused by warnings.
+- Use libtool to produce helper libraries as a step toward "libopenocd".
+- New processes and scripting to facilitate future source releases.
+
+For more details about what has changed since 0.1.0, see the ChangeLog
+associated with this release.
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.3.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.3.0
new file mode 100644
index 0000000..80e8823
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.3.0
@@ -0,0 +1,82 @@
+This file should include highlights of the changes made in the
+OpenOCD openocd-0.3.0 source archive release.  See the repository
+history for details about what changed, including bugfixes and
+other issues not mentioned here.
+
+JTAG Layer:
+    FT2232H (high speed USB) support doesn't need separate configuration
+    New FT2232H JTAG adapters:  Amontec, Olimex, Signalyzer
+    New reset_config options for SRST gating the JTAG clock (or not)
+    TAP declaration no longer requires ircapture and mask attributes
+    Scan chain setup should be more robust, with better diagnostics
+    New TAP events:
+	"post-reset" for TAP-invariant setup code (TAPs not usable yet)
+	"setup" for use once TAPs are addressable (e.g. with ICEpick)
+    Overridable Tcl "init_reset" and "jtag_init" procedures
+    Simple "autoprobe" mechanism to help simplify server setup
+
+Boundary Scan:
+    SVF bugfixes ... parsing fixes, better STATE switch conformance
+    XSVF bugfixes ... be more correct, handle Xilinx tool output
+
+Target Layer:
+    Warn on use of obsolete numeric target IDs
+    New commands for use with Cortex-M3 processors:
+	"cortex_m3 disassemble" ... Thumb2 disassembly (UAL format)
+	"cortex_m3 vector_catch" ... traps certain hardware faults
+		without tying up breakpoint resources
+    If you're willing to help debug it
+	VERY EARLY Cortex-A8 and ARMv7A support
+	Updated BeagleBoard.org hardware support
+	you may need to explicitly "reset" after connect-to-Beagle
+    New commands for use with XScale processors: "xscale vector_table"
+    ARM
+	bugfixes to single-stepping Thumb code
+	ETM: unavailable registers are not listed
+	ETB, ETM: report actual hardware status
+    ARM9
+	name change:  "arm9 vector_catch" not "arm9tdmi vector_catch"
+    ARM11
+	single stepping support for i.MX31
+	bugfix for missing "arm11" prefix on "arm11 memwrite ..."
+    GDB support
+	gdb_attach command is gone
+
+Flash Layer:
+    The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips
+    New drivers:
+	lpc2900, for NXP LPC2900 chips (ARM968 based)
+	mx3_nand, for imx31
+    New "last" flag for NOR "flash erase_sector" and "flash protect"
+    The "nand erase N" command now erases all of bank N
+    Speed up davinci_nand by about 3x
+
+Board, Target, and Interface Configuration Scripts:
+    Amontec JTAGkey2 support
+    Cleanup and additions for the TI/Luminary Stellaris scripts
+    LPC1768 target (and flash) support
+	Keil MCB1700 eval board
+    Samsung s3c2450
+	Mini2440 board
+    Numeric TAP and Target identifiers now trigger warnings
+    PXA255 partially enumerates
+
+Documentation:
+    Capture more debugging and setup advice
+    Notes on target source code changes that may help debugging
+
+Build and Release:
+    Repository moved from SVN at Berlios to GIT at SourceForge
+    Clean builds on (32-bit) Cygwin
+    Clean builds on 64-bit MinGW
+
+For more details about what has changed since the last release,
+see the git repository history.  With gitweb, you can browse that
+in various levels of detail.
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.4.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.4.0
new file mode 100644
index 0000000..cbd5526
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.4.0
@@ -0,0 +1,98 @@
+This file includes highlights of the changes made in the
+OpenOCD 0.4.0 source archive release.  See the repository
+history for details about what changed, including bugfixes
+and other issues not mentioned here.
+
+JTAG Layer:
+	Support KT-Link JTAG adapter.
+	Support USB-JTAG, Altera USB-Blaster and compatibles.
+
+Boundary Scan:
+
+Target Layer:
+	General
+		- Removed commands which have been obsolete for at least
+		  a year (from both documentation and, sometimes, code).
+		- new "reset-assert" event, for systems without SRST
+	ARM
+		- supports "reset-assert" event (except on Cortex-M3)
+		- renamed "armv4_5" command prefix as "arm"
+		- recognize TrustZone "Secure Monitor" mode
+		- "arm regs" command output changed
+		- register names use "sp" not "r13"
+		- add top-level "mcr" and "mrc" commands, replacing
+		  various core-specific operations
+		- basic semihosting support (ARM7/ARM9 only, for now)
+	ARM11
+		- Should act much more like other ARM cores:
+		   * Preliminary ETM and ETB hookup
+		   * accelerated "flash erase_check"
+		   * accelerated GDB memory checksum
+		   * support "arm regs" command
+		   * can access all core modes and registers
+		   * watchpoint support
+		- Shares some core debug code with Cortex-A8
+	Cortex-A8
+		- Should act much more like other ARM cores:
+		   * support "arm regs" command
+		   * can access all core modes and registers
+		   * watchpoint support
+		- Shares some core debug code with ARM11
+	Cortex-M3
+		- Exposed DWT registers like cycle counter
+		- vector_catch settings not clobbered by resets
+		- no longer interferes with firmware's fault handling
+	ETM, ETB
+		- "trigger_percent" command moved ETM --> ETB
+		- "etm trigger_debug" command added
+	MIPS
+		- use fastdata writes
+	Freescale DSP563xx cores (partial support)
+
+Flash Layer:
+	'flash bank' and 'nand device' take  as first argument.
+	With this, flash/NAND commands allow referencing banks by name:
+		- : reference the bank with its defined name
+		- [.N]: reference the driver's Nth bank
+	New 'nand verify' command to check bank against an image file.
+	The "flash erase_address" command now rejects partial sectors;
+		previously it would silently erase extra data.  If you
+		want to erase the rest of the first and/or last sectors
+		instead of failing, you must pass an explicit "pad" flag.
+	New at91sam9 NAND controller driver.
+	New s3c64xx NAND controller driver.
+
+Board, Target, and Interface Configuration Scripts:
+	ARM9
+		- ETM and ETB hookup for iMX2* targets
+	Add $HOME/.openocd to the search path.
+	Handle Rev C of LM3S811 eval boards.
+		- use "luminary-lm3s811.cfg" for older boards
+		- use "luminary.cfg" for RevC and newer
+
+Core Jim/TCL Scripting:
+	New 'usage' command to provide terse command help.
+	Improved command 'help' command output (sorted and indented).
+	Improved command handling:
+		- Most boolean settings now accept any of the following:
+		  on/off, enable/disable, true/false, yes/no, 1/0
+		- More error checking and reporting.
+
+Documentation:
+	New built-in command development documentation and primer.
+
+Build and Release:
+	Use --enable-doxygen-pdf to build PDF developer documentation.
+	Consider upgrading to libftdi 0.17 if you use that library; it
+		includes bugfixes which improve FT2232H support.
+
+For more details about what has changed since the last release,
+see the git repository history.  With gitweb, you can browse that
+in various levels of detail.
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.5.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.5.0
new file mode 100644
index 0000000..90ea35c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.5.0
@@ -0,0 +1,73 @@
+This file includes highlights of the changes made in the
+OpenOCD 0.5.0 source archive release.  See the repository
+history for details about what changed, including bugfixes
+and other issues not mentioned here.
+
+JTAG Layer:
+	New driver for "Bus Pirate"
+	Rename various commands so they're not JTAG-specific
+	   There are migration procedures for most of these, but you should
+	   convert your scripts to the new names, since those procedures
+	   will not be around forever.
+		jtag jinterface ... is now adapter_name
+	   	jtag_khz	... is now adapter_khz
+		jtag_nsrst_delay ... is now adapter_nsrst_delay
+		jtag_nsrst_assert_width ... is now adapter_nsrst_assert_width
+	Support Voipac VPACLink JTAG Adapter.
+
+Boundary Scan:
+
+Transport framework core ... supporting future work for SWD, SPI, and other
+non-JTAG ways to debug targets or program flash.
+
+Target Layer:
+	ARM:
+		- basic semihosting support for ARMv7M.
+		- renamed "armv7m" command prefix as "arm"
+	MIPS:
+		- "ejtag_srst" variant removed. The same functionality is
+		  obtained by using "reset_config none".
+		- added PIC32MX software reset support, this means srst is not
+		  required to be connected anymore.
+	OTHER:
+		- preliminary AVR32 AP7000 support.
+
+Flash Layer:
+	New "stellaris recover" command, implements the procedure
+		to recover locked devices (restoring non-volatile
+		state to the factory defaults, including erasing
+		the flash and its protection bits, and possibly
+		re-enabling hardware debugging).
+	PIC32MX now uses algorithm for flash programming, this
+		has increased the performance by approx 96%.
+	New 'pic32mx unlock' cmd to remove readout protection.
+	New STM32 Value Line Support.
+	New 'virtual' flash driver, used to associate other addresses
+		with a flash bank. See pic32mx.cfg for usage.
+	New iMX27 NAND flash controller driver.
+
+Board, Target, and Interface Configuration Scripts:
+	Support IAR LPC1768 kickstart board (by Olimex)
+	Support Voipac PXA270/PXA270M module.
+	New $PARPORTADDR tcl variable used to change default
+		parallel port address used.
+	Remove lm3s811.cfg; use "stellaris.cfg" instead
+
+Core Jim/TCL Scripting:
+	New "add_script_search_dir" command, behaviour is the same
+		as the "-s" cmd line option.
+
+Documentation:
+
+Build and Release:
+
+For more details about what has changed since the last release,
+see the git repository history.  With gitweb, you can browse that
+in various levels of detail.
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.6.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.6.0
new file mode 100644
index 0000000..0acd242
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.6.0
@@ -0,0 +1,54 @@
+This file includes highlights of the changes made in the
+OpenOCD  source archive release.  See the
+repository history for details about what changed, including
+bugfixes and other issues not mentioned here.
+
+JTAG Layer:
+	New STLINK V1/V2 JTAG/SWD adapter support.
+	New OSJTAG adapter support.
+	New Tincantools Flyswatter2 support.
+	Improved ULINK driver.
+	Improved RLINK driver.
+	Support for adapters based on FT232H chips.
+	New experimental driver for FTDI based adapters, using libusb-1.0 in asynchronous mode.
+
+Boundary Scan:
+
+Target Layer:
+	New Cortex-M0 support.
+	New Cortex-M4 support.
+	Improved Working area algorithm.
+	New RTOS support. Currently linux, FreeRTOS, ThreadX and eCos.
+	Connecting under reset to Cortex-Mx and MIPS chips.
+
+Flash Layer:
+	New SST39WF1601 support.
+	New EN29LV800BB support.
+	New async algorithm support for selected targets, stm32, stellaris and pic32.
+	New Atmel SAM3S, SAM3N support.
+	New ST STM32L support.
+	New Microchip PIC32MX1xx/2xx support.
+	New Freescale Kinetis K40 support.
+
+Board, Target, and Interface Configuration Scripts:
+	Support Dangerous Prototypes Bus Blaster.
+	Support ST SPEAr Family.
+	Support Gumstix Verdex boards.
+	Support TI Beaglebone.
+
+Documentation:
+	Improved HACKING info for submitting patches.
+	Fixed numerous broken links.
+
+Build and Release:
+
+For more details about what has changed since the last release,
+see the git repository history.  With gitweb, you can browse that
+in various levels of detail.
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.7.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.7.0
new file mode 100644
index 0000000..47a8fa6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.7.0
@@ -0,0 +1,43 @@
+This file includes highlights of the changes made in the
+OpenOCD  source archive release.  See the
+repository history for details about what changed, including
+bugfixes and other issues not mentioned here.
+
+JTAG Layer:
+	New TI ICDI adapter support.
+	Support Latest OSBDM firmware.
+	Improved MIPS EJTAG Support.
+
+Boundary Scan:
+
+Target Layer:
+	New ARMv7R and Cortex-R4 support.
+	Added ChibiOS/RT support.
+
+Flash Layer:
+	New NXP LPC1850 support.
+	New NXP LPC4300 support.
+	New NXP SPIFI support.
+	New Energy Micro EFM32 support.
+	New ST STM32W support.
+	New ST STM32f2 write protection and lock/unlock support.
+	Ability to override STM32 flash bank size.
+
+Board, Target, and Interface Configuration Scripts:
+	Support Freescale i.MX6 series targets.
+
+Documentation:
+	New MIPS debugging info.
+
+Build and Release:
+
+For more details about what has changed since the last release,
+see the git repository history.  With gitweb, you can browse that
+in various levels of detail.
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.8.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.8.0
new file mode 100644
index 0000000..33b3af4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.8.0
@@ -0,0 +1,111 @@
+This file includes highlights of the changes made in the OpenOCD
+source archive release.
+
+JTAG Layer:
+	* New CMSIS-DAP driver
+	* Andes AICE debug adapter support
+	* New OpenJTAG driver
+	* New BCM2835 (RaspberryPi) driver
+	* JTAG VPI client driver (for OpenRISC Reference Platform SoC)
+	* Xilinx BSCAN_* for OpenRISC support
+	* ST-LINKv2-1 support
+	* ST-LINKv2 SWO tracing support (UART emulation)
+	* JLink-OB (onboard) support
+	* Altera USB Blaster driver rewrite, initial Blaster II
+	  support
+	* ULINK driver ported to libusb-1.0, OpenULINK build fixes
+	* Support up to 64 bit IR lengths
+	* SVF playback (FPGA programming) fixes
+	* "ftdi" interface driver got extensive testing and is now
+	  recommended over the old ft2232 implementation
+
+Boundary Scan:
+
+Target Layer:
+	* New target: Andes nds32
+	* New target: OpenRISC OR1K
+	* New target: Intel Quark X10xx
+	* MIPS EJTAG 1.5/2.0 support
+	* MIPS speed improvements
+	* Cortex-M, Cortex-A (MEM-AP, APB-AP) targets working with BE
+	  hosts now
+	* XScale vector_catch support, reset fixes
+	* dsp563xx ad-hoc breakpoint/watchpoint support
+	* RTOS support for embKernel
+	* Target profiling improvements
+	* Memory access functions testbench
+
+Flash Layer:
+	* STM32 family sync with reference manuals, other bugfixes
+	* STM32F401, STM32F07x support
+	* Atmel SAM4L, SAMG5x support
+	* at91sam3sd8{a,b}, at91sam3s8{a,b,c}, at91sam4s,
+	  at91sam3n0{a,b,0a,0b} support, bugfixes
+	* Atmel SAMD support
+	* Milandr 1986ВЕ* support
+	* Kinetis KL, K21 support
+	* Nuvoton NuMicro MINI5{1,2,4} support
+	* Nuvoton NUC910 series support
+	* NXP LPC43xx, LPC2000 fixes
+	* NXP LPC800, LPC810 support
+	* More ATmega parts supported
+	* Fujitsu MB9Ax family support
+	* EFM32 Wonder Gecko family support
+	* Nordic nRF51 support
+
+Board, Target, and Interface Configuration Scripts:
+	* STM32W108xx generic target config
+	* STM32F429 discovery board config
+	* STM32 Nucleo boards configs
+	* DENX M53EVK board config
+	* Altera Cyclone V SoC, SoCkit config
+	* New TI Launchpads board configs
+	* TI am43xx devices, AM437x GP EVM, AM438x ePOS EVM board
+	  configs
+	* Marvell Armada 370 family initial support
+	* TI TMDX570LS31USB (TMS570, Cortex-R4) support scripts
+	* Freescale FRDM-KL25Z, KL46Z board configs
+	* Digilent Zedboard config
+	* Asus RT-N16, Linksys WRT54GL, BT HomeHub board configs
+	* Atmel Xplained initial support
+	* Broadcom bcm28155_ap board config
+	* TUMPA, TUMPA Lite interface configs
+	* Digilent JTAG-SMT2 interface config
+	* New RAM testing functions
+	* Easy-to-use firmware recovery helpers targetting ordinary
+	  users with common equipment
+
+Server Layer:
+	* Auto-generation of GDB target description for ARMv7-M,
+	  ARM4, nds32, OR1K, Quark
+	* GDB File-I/O Remote Protocol extension support
+	* Default GDB flashing events handlers to initialise and reset
+	  the target automatically when "load" is used
+
+Documentation:
+	* Extensive README* changes
+	* The official User's Guide was proofread
+	* Example cross-build script
+	* RTOS documentation improvements
+	* Tcl RPC documentation and examples added
+
+Build and Release:
+	* *BSD, OS X, clang, ARM, windows build fixes
+	* New pkg-config support changes the way libusb (and other
+	  dependencies) are handled. Many adapter drivers are now
+	  selected automatically during the configure stage.
+
+
+This release also contains a number of other important functional and
+cosmetic bugfixes. For more details about what has changed since the
+last release, see the git repository history:
+
+http://sourceforge.net/p/openocd/code/ci/v0.8.0/log/?path=
+
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.9.0 b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.9.0
new file mode 100644
index 0000000..77ae4b0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/NEWS-0.9.0
@@ -0,0 +1,110 @@
+This file includes highlights of the changes made in the OpenOCD
+source archive release.
+
+JTAG Layer:
+	* SWD support with FTDI, Versaloon, J-Link, sysfsgpio
+	* CMSIS-DAP massive speed and stability improvements
+	* Versaloon driver ported to libusb-1.0
+	* STLink can reestablish communication with a target that was
+          disconnected or rebooted
+	* STLink FAULT and WAIT SWD handling improved
+	* New hla_serial command to distinguish between several HLA
+          adapters attached to a single machine
+	* Serial number support for CMSIS-DAP and J-Link adapters
+	* Support for more J-Link adapters
+	* TAP autoprobing improvements
+	* Big speedup for SVF playback with USB Blaster
+
+Boundary Scan:
+
+Target Layer:
+	* Stability improvements for targets that get disconnected or
+          rebooted during a debug session
+	* MIPS speed and reliability improvements
+	* MIPS 1.5/2.0 fixes
+	* ARMv7-R improvements
+	* Cortex-A improvements, A7, A15 MPCores support
+	* FPU support for ARMv7-M (Cortex-M4F)
+	* TPIU/ITM support (including SWO/SWV tracing), can be
+          captured with external tools or STLink
+	* JTAG Serial Port (Advanced Debug System softcore) support
+	* Profiling support for OpenRISC
+	* ChibiOS/RT 3.0 support (with and without FPU)
+	* FreeRTOS current versions support
+	* Freescale MQX RTOS support
+	* GDB target description support for MIPS
+	* The last created target is auto-selected as the current
+
+Flash Layer:
+	* nRF51 async loader to improve flashing performance and stability
+	* Cypress PSoC 41xx/42xx and CCG1 families flash driver
+	* Silabs SiM3 family flash driver
+	* Marvell Wireless Microcontroller SPI flash driver
+	* Kinetis mass erase (part unsecuring) implemented
+	* lpcspifi stability fixes
+	* STM32 family sync with reference manuals, L0 support, bugfixes
+	* LPC2000 driver automatically determines part and flash size
+	* NXP LPC11(x)xx, LPC13xx, LPC15xx, LPC8xx, LPC5410x, LPC407x support
+	* Atmel SAMD, SAMR, SAML21 devices support
+	* Atmel SAM4E16 support
+	* ZeroGecko family support
+	* TI Tiva C Blizzard and Snowflake families support
+	* Nuvoton NuMicro M051 support
+	* EZR32 support in EFM32 driver
+
+Board, Target, and Interface Configuration Scripts:
+	* Normal target configs can work with HLA (STLink, ICDI) adapters
+	* STM32 discovery and Nucleo boards configs
+	* Gumstix AeroCore board config
+	* General Plus GP326XXXA target config
+	* Micrel KS869x target config
+	* ASUS RT-N66U board config
+	* Atmel SAM4E-EK board config
+	* Atmel AT91SAM4L proper reset handling implemented
+	* TI OMAP/AM 3505, 3517 target configs
+	* nRF51822-mKIT board config
+	* RC Module К1879ХБ1Я target config
+	* TI TMDX570LS20SUSB board config
+	* TI TMS570 USB Kit board config
+	* TI CC2538, CC26xx target configs
+	* TI AM437x major config improvements, DDR support
+	* TI AM437X IDK board config
+	* TI SimpleLink Wi-Fi CC3200 LaunchPad configs
+	* Silicon Labs EM357, EM358 target configs
+	* Infineon XMC1000, XMC4000 family targets and boards configs
+	* Atheros AR9331 target config
+	* TP-LINK TL-MR3020 board config
+	* Alphascale asm9260t target and eval kit configs
+	* Olimex SAM7-LA2 (AT91SAM7A2) board config
+	* EFM32 Gecko boards configs
+	* Spansion FM4 target and SK-FM4-176L-S6E2CC board configs
+	* LPC1xxx target configs were restructured
+	* IoT-LAB debug adapter config
+	* DP BusBlaster KT-Link compatible config
+
+Server Layer:
+	* Polling period can be configured
+	* "shutdown" command has an immediate effect
+	* The "program" command doesn't lead to a shutdown by
+          default, use optional "exit" parameter for the old behaviour
+	* Proper OS signal handling was implemented
+	* Async target notifications for the Tcl RPC
+
+Documentation:
+
+Build and Release:
+
+
+This release also contains a number of other important functional and
+cosmetic bugfixes. For more details about what has changed since the
+last release, see the git repository history:
+
+http://sourceforge.net/p/openocd/code/ci/v0.9.0/log/?path=
+
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README
new file mode 100644
index 0000000..950c71f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README
@@ -0,0 +1,336 @@
+# Welcome to OpenOCD!
+
+OpenOCD provides on-chip programming and debugging support with a
+layered architecture of JTAG interface and TAP support including:
+
+- (X)SVF playback to facilitate automated boundary scan and FPGA/CPLD
+  programming;
+- debug target support (e.g. ARM, MIPS): single-stepping,
+  breakpoints/watchpoints, gprof profiling, etc;
+- flash chip drivers (e.g. CFI, NAND, internal flash);
+- embedded TCL interpreter for easy scripting.
+
+Several network interfaces are available for interacting with OpenOCD:
+telnet, TCL, and GDB. The GDB server enables OpenOCD to function as a
+"remote target" for source-level debugging of embedded systems using
+the GNU GDB program (and the others who talk GDB protocol, e.g. IDA
+Pro).
+
+This README file contains an overview of the following topics:
+
+- quickstart instructions,
+- how to find and build more OpenOCD documentation,
+- list of the supported hardware,
+- the installation and build process,
+- packaging tips.
+
+
+# Quickstart for the impatient
+
+If you have a popular board then just start OpenOCD with its config,
+e.g.:
+
+    openocd -f board/stm32f4discovery.cfg
+
+If you are connecting a particular adapter with some specific target,
+you need to source both the jtag interface and the target configs,
+e.g.:
+
+```
+openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \
+        -f target/ti_calypso.cfg
+```
+
+```
+openocd -f interface/stlink.cfg -c "transport select hla_swd" \
+        -f target/stm32l0.cfg
+```
+
+After OpenOCD startup, connect GDB with
+
+    (gdb) target extended-remote localhost:3333
+
+
+# OpenOCD Documentation
+
+In addition to the in-tree documentation, the latest manuals may be
+viewed online at the following URLs:
+
+  OpenOCD User's Guide:
+    http://openocd.org/doc/html/index.html
+
+  OpenOCD Developer's Manual:
+    http://openocd.org/doc/doxygen/html/index.html
+
+These reflect the latest development versions, so the following section
+introduces how to build the complete documentation from the package.
+
+For more information, refer to these documents or contact the developers
+by subscribing to the OpenOCD developer mailing list:
+
+	openocd-devel@lists.sourceforge.net
+
+## Building the OpenOCD Documentation
+
+By default the OpenOCD build process prepares documentation in the
+"Info format" and installs it the standard way, so that `info openocd`
+can access it.
+
+Additionally, the OpenOCD User's Guide can be produced in the
+following different formats:
+
+If `PDFVIEWER` is set, this creates and views the PDF User Guide.
+
+    make pdf && ${PDFVIEWER} doc/openocd.pdf
+
+If `HTMLVIEWER` is set, this creates and views the HTML User Guide.
+
+    make html && ${HTMLVIEWER} doc/openocd.html/index.html
+
+The OpenOCD Developer Manual contains information about the internal
+architecture and other details about the code:
+
+Note: make sure doxygen is installed, type doxygen --version
+
+    make doxygen && ${HTMLVIEWER} doxygen/index.html
+
+
+# Supported hardware
+
+## JTAG adapters
+
+AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835,
+Bus Blaster, Buspirate, Cadence DPI, Cadence vdebug, Chameleon, CMSIS-DAP,
+Cortino, Cypress KitProg, DENX, Digilent JTAG-SMT2, DLC 5, DLP-USB1232H,
+embedded projects, Espressif USB JTAG Programmer,
+eStick, FlashLINK, FlossJTAG, Flyswatter, Flyswatter2,
+FTDI FT232R, Gateworks, Hoegl, ICDI, ICEBear, J-Link, JTAG VPI, JTAGkey,
+JTAGkey2, JTAG-lock-pick, KT-Link, Linux GPIOD, Lisa/L, LPC1768-Stick,
+Mellanox rshim, MiniModule, NGX, Nuvoton Nu-Link, Nu-Link2, NXHX, NXP IMX GPIO,
+OOCDLink, Opendous, OpenJTAG, Openmoko, OpenRD, OSBDM, Presto, Redbee,
+Remote Bitbang, RLink, SheevaPlug devkit, Stellaris evkits,
+ST-LINK (SWO tracing supported), STM32-PerformanceStick, STR9-comStick,
+sysfsgpio, Tigard, TI XDS110, TUMPA, Turtelizer, ULINK, USB-A9260, USB-Blaster,
+USB-JTAG, USBprog, VPACLink, VSLLink, Wiggler, XDS100v2, Xilinx XVC/PCIe,
+Xverve.
+
+## Debug targets
+
+ARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M),
+FA526, Feroceon/Dragonite, XScale.
+ARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64),
+ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, RISC-V, ST STM8,
+Xtensa.
+
+## Flash drivers
+
+ADUC702x, AT91SAM, AT91SAM9 (NAND), ATH79, ATmega128RFA1, Atmel SAM, AVR, CFI,
+DSP5680xx, EFM32, EM357, eSi-RISC, eSi-TSMC, EZR32HG, FM3, FM4, Freedom E SPI,
+GD32, i.MX31, Kinetis, LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPC3180, LPC32xx,
+LPCSPIFI, Marvell QSPI, MAX32, Milandr, MXC, NIIET, nRF51, nRF52 , NuMicro,
+NUC910, Nuvoton NPCX, onsemi RSL10, Orion/Kirkwood, PIC32mx, PSoC4/5LP/6,
+Raspberry RP2040, Renesas RPC HF and SH QSPI,
+S3C24xx, S3C6400, SiM3x, SiFive Freedom E, Stellaris, ST BlueNRG, STM32,
+STM32 QUAD/OCTO-SPI for Flash/FRAM/EEPROM, STMSMI, STR7x, STR9x, SWM050,
+TI CC13xx, TI CC26xx, TI CC32xx, TI MSP432, Winner Micro w600, Xilinx XCF,
+XMC1xxx, XMC4xxx.
+
+
+# Installing OpenOCD
+
+## A Note to OpenOCD Users
+
+If you would rather be working "with" OpenOCD rather than "on" it, your
+operating system or JTAG interface supplier may provide binaries for
+you in a convenient-enough package.
+
+Such packages may be more stable than git mainline, where
+bleeding-edge development takes place. These "Packagers" produce
+binary releases of OpenOCD after the developers produces new "release"
+versions of the source code. Previous versions of OpenOCD cannot be
+used to diagnose problems with the current release, so users are
+encouraged to keep in contact with their distribution package
+maintainers or interface vendors to ensure suitable upgrades appear
+regularly.
+
+Users of these binary versions of OpenOCD must contact their Packager to
+ask for support or newer versions of the binaries; the OpenOCD
+developers do not support packages directly.
+
+## A Note to OpenOCD Packagers
+
+You are a PACKAGER of OpenOCD if you:
+
+- Sell dongles and include pre-built binaries;
+- Supply tools or IDEs (a development solution integrating OpenOCD);
+- Build packages (e.g. RPM or DEB files for a GNU/Linux distribution).
+
+As a PACKAGER, you will experience first reports of most issues.
+When you fix those problems for your users, your solution may help
+prevent hundreds (if not thousands) of other questions from other users.
+
+If something does not work for you, please work to inform the OpenOCD
+developers know how to improve the system or documentation to avoid
+future problems, and follow-up to help us ensure the issue will be fully
+resolved in our future releases.
+
+That said, the OpenOCD developers would also like you to follow a few
+suggestions:
+
+- Send patches, including config files, upstream, participate in the
+  discussions;
+- Enable all the options OpenOCD supports, even those unrelated to your
+  particular hardware;
+- Use "ftdi" interface adapter driver for the FTDI-based devices.
+
+
+# Building OpenOCD
+
+The INSTALL file contains generic instructions for running `configure`
+and compiling the OpenOCD source code. That file is provided by
+default for all GNU autotools packages. If you are not familiar with
+the GNU autotools, then you should read those instructions first.
+
+The remainder of this document tries to provide some instructions for
+those looking for a quick-install.
+
+## OpenOCD Dependencies
+
+GCC or Clang is currently required to build OpenOCD. The developers
+have begun to enforce strict code warnings (-Wall, -Werror, -Wextra,
+and more) and use C99-specific features: inline functions, named
+initializers, mixing declarations with code, and other tricks. While
+it may be possible to use other compilers, they must be somewhat
+modern and could require extending support to conditionally remove
+GCC-specific extensions.
+
+You'll also need:
+
+- make
+- libtool
+- pkg-config >= 0.23 or pkgconf
+
+OpenOCD uses jimtcl library; build from git can retrieve jimtcl as git
+submodule.
+
+Additionally, for building from git:
+
+- autoconf >= 2.69
+- automake >= 1.14
+- texinfo >= 5.0
+
+Optional USB-based adapter drivers need libusb-1.0.
+
+Optional USB-Blaster, ASIX Presto and OpenJTAG interface adapter
+drivers need:
+  - libftdi: http://www.intra2net.com/en/developer/libftdi/index.php
+
+Optional CMSIS-DAP adapter driver needs HIDAPI library.
+
+Optional linuxgpiod adapter driver needs libgpiod library.
+
+Optional J-Link adapter driver needs libjaylink library.
+
+Optional ARM disassembly needs capstone library.
+
+Optional development script checkpatch needs:
+
+- perl
+- python
+- python-ply
+
+## Permissions delegation
+
+Running OpenOCD with root/administrative permissions is strongly
+discouraged for security reasons.
+
+For USB devices on GNU/Linux you should use the contrib/60-openocd.rules
+file. It probably belongs somewhere in /etc/udev/rules.d, but
+consult your operating system documentation to be sure. Do not forget
+to add yourself to the "plugdev" group.
+
+For parallel port adapters on GNU/Linux and FreeBSD please change your
+"ppdev" (parport* or ppi*) device node permissions accordingly.
+
+For parport adapters on Windows you need to run install_giveio.bat
+(it's also possible to use "ioperm" with Cygwin instead) to give
+ordinary users permissions for accessing the "LPT" registers directly.
+
+## Compiling OpenOCD
+
+To build OpenOCD, use the following sequence of commands:
+
+    ./bootstrap
+    ./configure [options]
+    make
+    sudo make install
+
+The `bootstrap` command is only necessary when building from the Git repository. The `configure` step generates the Makefiles required to build
+OpenOCD, usually with one or more options provided to it. The first
+'make' step will build OpenOCD and place the final executable in
+'./src/'. The final (optional) step, `make install`, places all of
+the files in the required location.
+
+To see the list of all the supported options, run `./configure --help`
+
+## Cross-compiling Options
+
+Cross-compiling is supported the standard autotools way, you just need
+to specify the cross-compiling target triplet in the --host option,
+e.g. for cross-building for Windows 32-bit with MinGW on Debian:
+
+    ./configure --host=i686-w64-mingw32 [options]
+
+To make pkg-config work nicely for cross-compiling, you might need an
+additional wrapper script as described at
+
+    https://autotools.io/pkgconfig/cross-compiling.html
+
+This is needed to tell pkg-config where to look for the target
+libraries that OpenOCD depends on. Alternatively, you can specify
+`*_CFLAGS` and `*_LIBS` environment variables directly, see `./configure
+--help` for the details.
+
+For a more or less complete script that does all this for you, see
+
+    contrib/cross-build.sh
+
+## Parallel Port Dongles
+
+If you want to access the parallel port using the PPDEV interface you
+have to specify both `--enable-parport` and `--enable-parport-ppdev`, since
+the later option is an option to the parport driver.
+
+The same is true for the `--enable-parport-giveio` option, you have to
+use both the `--enable-parport` and the `--enable-parport-giveio` option
+if you want to use giveio instead of ioperm parallel port access
+method.
+
+
+# Obtaining OpenOCD From GIT
+
+You can download the current GIT version with a GIT client of your
+choice from the main repository:
+
+    git://git.code.sf.net/p/openocd/code
+
+You may prefer to use a mirror:
+
+    http://repo.or.cz/r/openocd.git
+    git://repo.or.cz/openocd.git
+
+Using the GIT command line client, you might use the following command
+to set up a local copy of the current repository (make sure there is no
+directory called "openocd" in the current directory):
+
+    git clone git://git.code.sf.net/p/openocd/code openocd
+
+Then you can update that at your convenience using `git pull`.
+
+There is also a gitweb interface, which you can use either to browse
+the repository or to download arbitrary snapshots using HTTP:
+
+    http://repo.or.cz/w/openocd.git
+
+Snapshots are compressed tarballs of the source tree, about 1.3 MBytes
+each at this writing.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README.Windows b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README.Windows
new file mode 100644
index 0000000..64bf5c0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README.Windows
@@ -0,0 +1,56 @@
+Building OpenOCD for Windows
+----------------------------
+
+You can build OpenOCD for Windows natively with either MinGW-w64/MSYS
+or Cygwin (plain MinGW might work with --disable-werror but is not
+recommended as it doesn't provide enough C99 compatibility).
+Alternatively, one can cross-compile it using MinGW-w64 on a *nix
+host. See README for the generic instructions.
+
+Also, the MSYS2 project provides both ready-made binaries and an easy
+way to self-compile from their software repository out of the box.
+
+Native MinGW-w64/MSYS compilation
+-----------------------------
+
+As MSYS doesn't come with pkg-config pre-installed, you need to add it
+manually. The easiest way to do that is to download pkg-config-lite
+from:
+
+  http://sourceforge.net/projects/pkgconfiglite/
+
+Then simply unzip the archive to the root directory of your MinGW-w64
+installation.
+
+USB adapters
+------------
+
+For the adapters that use a HID-based protocol, e.g. CMSIS-DAP, you do
+not need to perform any additional configuration.
+
+For all the others you usually need to have WinUSB.sys (or
+libusbK.sys) driver installed. Some vendor software (e.g. for
+ST-LINKv2) does it on its own. For the other cases the easiest way to
+assign WinUSB to a device is to use the latest Zadig installer:
+
+  http://zadig.akeo.ie
+
+When using a composite USB device, it's often necessary to assign
+WinUSB.sys to the composite parent instead of the specific
+interface. To do that one needs to activate an advanced option in the
+Zadig installer.
+
+If you need to use the same adapter with other applications that may
+require another driver, a solution for Windows Vista and above is to
+activate the IgnoreHWSerNum registry setting for the USB device.
+
+That setting forces Windows to associate the driver per port instead of
+per serial number, the same behaviour as when the device does not contain
+a serial number. So different drivers can be installed for the adapter on
+different ports and you just need to plug the adapter into the correct
+port depending on which application to use.
+
+For more information, see:
+
+  https://learn.microsoft.com/en-us/windows-hardware/drivers/usbcon/usb-device-specific-registry-settings
+  http://www.ftdichip.com/Support/Knowledgebase/index.html?ignorehardwareserialnumber.htm
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README.macOS b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README.macOS
new file mode 100644
index 0000000..91d5e92
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README.macOS
@@ -0,0 +1,54 @@
+Building OpenOCD for macOS
+--------------------------
+
+There are a few prerequisites you will need first:
+
+- Xcode (install from the AppStore)
+- Command Line Tools (install from Xcode -> Preferences -> Downloads)
+- Gentoo Prefix (http://www.gentoo.org/proj/en/gentoo-alt/prefix/bootstrap.xml)
+  or
+- Homebrew (http://mxcl.github.io/homebrew/)
+  or
+- MacPorts (http://www.macports.org/install.php)
+
+
+If you're building manually you need Texinfo version 5.0 or later. The
+simplest way to get it is to use Homebrew (brew install texinfo) and
+then ``export PATH=/usr/local/opt/texinfo/bin:$PATH``.
+
+
+With Gentoo Prefix you can build the release version or the latest
+devel version (-9999) the usual way described in the Gentoo
+documentation. Alternatively, install the prerequisites and build
+manually from the sources.
+
+
+With Homebrew you can either run:
+  brew install [--HEAD] openocd (where optional --HEAD asks brew to
+                                 install the current git version)
+    or
+  brew install libtool automake libusb [hidapi] [libftdi]
+    (to install the needed dependencies and then proceed with the
+     manual building procedure)
+
+
+For building with MacPorts you need to run:
+  sudo port install libtool automake autoconf pkgconfig \
+    libusb [libftdi1]
+
+You should also specify LDFLAGS and CPPFLAGS to allow configure to use
+MacPorts' libraries, so run configure like this:
+  LDFLAGS=-L/opt/local/lib CPPFLAGS=-I/opt/local/include ./configure [options]
+
+
+See README for the generic building instructions.
+
+If you're using a USB adapter and have a driver kext matched to it,
+you will need to unload it prior to running OpenOCD. E.g. with Apple
+driver (OS X 10.9 or later) for FTDI run:
+  sudo kextunload -b com.apple.driver.AppleUSBFTDI
+for FTDI vendor driver use:
+  sudo kextunload FTDIUSBSerialDriver.kext
+
+To learn more on the topic please refer to the official libusb FAQ:
+https://github.com/libusb/libusb/wiki/FAQ
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README.md b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README.md
new file mode 100644
index 0000000..f0a4636
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/licenses/openocd-0.11.0/README.md
@@ -0,0 +1,15 @@
+# Notice
+
+If you are looking for how to build Nuclei OpenOCD,
+please follow this [guidance](https://github.com/riscv-mcu/openocd-xpack/blob/xpack_nuclei_next/README-BUILD-Nuclei.md)
+
+About how to use openocd, please check http://openocd.org/documentation/
+
+[![Build Nuclei OpenOCD](https://github.com/riscv-mcu/riscv-openocd/workflows/Build%20Nuclei%20OpenOCD/badge.svg)](https://github.com/riscv-mcu/riscv-openocd/actions)
+
+- `nuclei-master` - the updated content, used during builds and releases
+- `nuclei-develop` - the updated content, used during development
+
+Since we are always merging changes from upstream, forced update to these two branches
+might be happened in future, please take care.
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/README.md b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/README.md
new file mode 100644
index 0000000..320d0d5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/README.md
@@ -0,0 +1,7 @@
+These are small patches required to correct some problems identified in the official packages.
+
+* `libftdi1-1.2-cmake-FindUSB1.patch` - adds `NO_DEFAULT_PATH` to `FIND_PATH()` and `FIND_LIBRARY()`, to make cmake not search libusb in system default locations;
+
+* `libusb-win32-1.2.6.0-mingw-w64.patch` - makes `libusb-win32` build without the Microsoft DDK; it was copied from the [JTAG Tools](https://gitorious.org/jtag-tools/openocd-mingw-build-scripts) project, and repuires `-p1` when applying.
+
+For details on how to create the patches, see the helper [README](../scripts/helper/README.md).
\ No newline at end of file
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/libftdi1-1.2-cmake-FindUSB1.patch b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/libftdi1-1.2-cmake-FindUSB1.patch
new file mode 100644
index 0000000..cccd23d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/libftdi1-1.2-cmake-FindUSB1.patch
@@ -0,0 +1,15 @@
+--- cmake/FindUSB1.cmake	2015-01-29 23:17:41.780000063 +0200
++++ cmake/FindUSB1-patched.cmake	2015-01-29 23:18:26.192000175 +0200
+@@ -24,10 +24,10 @@
+ 
+   FIND_PATH(LIBUSB_INCLUDE_DIR libusb.h
+     PATH_SUFFIXES libusb-1.0
+-    PATHS ${PC_LIBUSB_INCLUDEDIR} ${PC_LIBUSB_INCLUDE_DIRS})
++    PATHS ${PC_LIBUSB_INCLUDEDIR} ${PC_LIBUSB_INCLUDE_DIRS} NO_DEFAULT_PATH)
+ 
+   FIND_LIBRARY(LIBUSB_LIBRARIES NAMES usb-1.0
+-    PATHS ${PC_LIBUSB_LIBDIR} ${PC_LIBUSB_LIBRARY_DIRS})
++    PATHS ${PC_LIBUSB_LIBDIR} ${PC_LIBUSB_LIBRARY_DIRS} NO_DEFAULT_PATH)
+ 
+   include(FindPackageHandleStandardArgs)
+   FIND_PACKAGE_HANDLE_STANDARD_ARGS(LIBUSB DEFAULT_MSG LIBUSB_LIBRARIES LIBUSB_INCLUDE_DIR)
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/libftdi1-1.4-cmake-FindUSB1.patch b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/libftdi1-1.4-cmake-FindUSB1.patch
new file mode 100644
index 0000000..4d24491
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/libftdi1-1.4-cmake-FindUSB1.patch
@@ -0,0 +1,15 @@
+--- cmake/FindUSB1.cmake	2017-08-07 17:52:39.000000000 +0300
++++ cmake/FindUSB1-patched.cmake	2019-06-17 16:37:34.000000000 +0300
+@@ -24,10 +24,10 @@
+ 
+   FIND_PATH(LIBUSB_INCLUDE_DIR libusb.h
+     PATH_SUFFIXES libusb-1.0
+-    PATHS ${PC_LIBUSB_INCLUDEDIR} ${PC_LIBUSB_INCLUDE_DIRS})
++    PATHS ${PC_LIBUSB_INCLUDEDIR} ${PC_LIBUSB_INCLUDE_DIRS} NO_DEFAULT_PATH)
+ 
+   FIND_LIBRARY(LIBUSB_LIBRARIES NAMES usb-1.0
+-    PATHS ${PC_LIBUSB_LIBDIR} ${PC_LIBUSB_LIBRARY_DIRS})
++    PATHS ${PC_LIBUSB_LIBDIR} ${PC_LIBUSB_LIBRARY_DIRS} NO_DEFAULT_PATH)
+ 
+   include(FindPackageHandleStandardArgs)
+   FIND_PACKAGE_HANDLE_STANDARD_ARGS(LIBUSB DEFAULT_MSG LIBUSB_LIBRARIES LIBUSB_INCLUDE_DIR)
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/libusb-win32-1.2.6.0-mingw-w64.patch b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/libusb-win32-1.2.6.0-mingw-w64.patch
new file mode 100644
index 0000000..3a68fdc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/patches/libusb-win32-1.2.6.0-mingw-w64.patch
@@ -0,0 +1,60 @@
+diff -purN src/install.c src/install-patched.c
+--- src/install.c	2011-10-28 14:34:08.000000000 +0200
++++ src/install-patched.c	2013-05-30 11:28:54.000000000 +0200
+@@ -31,14 +31,8 @@
+ #include 
+ #include 
+ 
+-#ifdef __GNUC__
+-#if  defined(_WIN64)
+-#include 
+-#else
+-#include 
+-#endif
+-#else
+ #include 
++#ifndef __GNUC__
+ #define strlwr(p) _strlwr(p)
+ #endif
+ 
+diff -purN src/install_filter_win.c src/install_filter_win-patched.c
+--- src/install_filter_win.c	2010-09-22 22:35:52.000000000 +0200
++++ src/install_filter_win-patched.c	2013-05-30 11:39:19.000000000 +0200
+@@ -21,15 +21,9 @@
+ 
+ #include 
+ 
+-#ifdef __GNUC__
+-	#if  defined(_WIN64)
+-		#include 
+-	#else
+-		#include 
+-	#endif
+-#else
+-	#include 
+-	#define strlwr(p) _strlwr(p)
++#include 
++#ifndef __GNUC__
++#define strlwr(p) _strlwr(p)
+ #endif
+ 
+ #include 
+diff -purN src/registry.c src/registry-patched.c
+--- src/registry.c	2010-09-23 17:40:50.000000000 +0200
++++ src/registry-patched.c	2013-05-30 11:29:22.000000000 +0200
+@@ -24,14 +24,8 @@
+ #include 
+ #include 
+ 
+-#ifdef __GNUC__
+-#if  defined(_WIN64)
+-#include 
+-#else
+-#include 
+-#endif
+-#else
+ #include 
++#ifndef __GNUC__
+ #define strlwr(p) _strlwr(p)
+ #endif
+ 
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/README-0.10.0-13.md b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/README-0.10.0-13.md
new file mode 100644
index 0000000..64252a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/README-0.10.0-13.md
@@ -0,0 +1,49 @@
+# The xPack OpenOCD
+
+This is the **xPack** version of **OpenOCD** (formerly part of the 
+GNU MCU Eclipse project).
+
+For details, see 
+[The xPack OpenOCD](https://xpack.github.io/openocd/) pages.
+
+## Compliance
+
+The xPack OpenOCD generally follows the official 
+[OpenOCD](http://openocd.org) releases.
+
+The current version is based on:
+
+- OpenOCD version 0.10.0, the development commit 
+[263deb380](https://github.com/xpack-dev-tools/openocd/commit/263deb3802a515ba8155b6c59146f0f539de4e43) 
+from 7 July 2019
+
+## Changes
+
+Compared to the master branch, the following changes were applied:
+
+- a configure option was added to configure branding (`--enable-branding`)
+- the src/openocd.c file was edited to display the branding string
+- the contrib/60-openocd.rules file was simplified to avoid protection related issues.
+
+## Build
+
+The scripts used to build this distribution are in:
+
+- `distro-info/scripts`
+
+For the prerequisites and more details on the build procedure, please see the 
+[How to build?](https://github.com/xpack-dev-tools/openocd-xpack/blob/xpack/README-BUILD.md) page. 
+
+## Documentation
+
+The original documentation is available in the `share/doc` folder.
+
+## More info
+
+For more info and support, please see the xPack project pages from:
+
+  http://xpack.github.io/dev-tools/openocd
+
+Thank you for using open source software,
+
+Liviu Ionescu
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/README-0.10.0-15.md b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/README-0.10.0-15.md
new file mode 100644
index 0000000..b44cc1a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/README-0.10.0-15.md
@@ -0,0 +1,5 @@
+# Nuclei OpenOCD Distribution
+
+## Changes
+
+* added FTD2XX driver support.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/README-Changelog.md b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/README-Changelog.md
new file mode 100644
index 0000000..8bfdc5e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/README-Changelog.md
@@ -0,0 +1,130 @@
+# Nuclei OpenOCD Distribution
+
+For **Nuclei OpenOCD documentation**, please check https://doc.nucleisys.com/nuclei_tools/openocd/intro.html
+
+If the tool version and documentation version not match, please take care.
+
+**Below is the changelog for Nuclei OpenOCD.**
+
+## 2025.10
+
+This release is based on the same code base of **2025.02**, but do some new feature and bugfixes.
+
+* Update ``nuclei cpuinfo`` command implementation using nuclei sdk 0.9.0 cpuinfo same source code to provide same behavior
+* Correct custom flashloader binary file location search rules, where openocd executed, openocd ``scripts`` folder, and absolute path
+* Sync nuclei custom CSRs support
+* Optimize flash probe process, when no flash probed, it will exit with error instead of hang on it
+* Support debug for hypervisor mode
+* Fix debug ``Assertion failed!`` on HBird opensource cpu
+* Fix nuclei riscv cross trigger command implementation ``nuclei cti xxx``
+* Clear ``haltreq`` signal when openocd connect failed
+* Fix segmentation fault issue when debug level set to 3 or 4
+* When debug on FPGA CPU MHz is very slow such as **5MHz**, openocd may work not correctly, it will be fixed by make CPU run faster such as **10MHz**
+
+## 2025.02
+
+* improvement of ci and doc
+* replace ``vslide1down_vx`` to read/write riscv vector register
+* support live watch feature via riscv sba memory access channel
+* organize nuclei commands into ``nuclei_riscv.c``
+* add ``nuclei cti`` command group
+* update ``nuclei etrace`` command group
+* optimize ``nuclei cpuinfo`` command
+
+* add new nuclei customized csrs
+
+    | new csr addr | new csr name |
+    | ------ | ------ |
+    | 0x1a4~0x1af | smpuaddr4~15 |
+    | 0x1c0~0x1ef | smpuaddr16~63 |
+
+* rename nuclei customized csrs
+
+    | old name | new name |
+    | ------ | ------ |
+    | spmpcfg0~3 | smpucfg0~3 |
+    | spmpaddr0~15 | smpuaddr0~15 |
+    | mfp16mode | mmisc_ctl1 |
+    | mecc_ctrl | mecc_ctl |
+    | mstack_ctrl | mstack_ctl |
+
+* changes are based on [riscv/riscv-openocd@f82c5a7](https://github.com/riscv-collab/riscv-openocd/commit/f82c5a7)
+
+
+## 2024.06
+
+* Add and update nuclei custom CSR
+* Fix `nuclei cpuinfo` command implementation
+* Add debug map feature for Nuclei CPU with new `nuclei expose_cpu_core` and `nuclei examine_cpu_core` commands
+* changes are based on [riscv/riscv-openocd](https://github.com/riscv/riscv-openocd/commit/52177592)
+* Fix hbird/hbirdv2 flash programming, and re-route fespi to nuspi flash loader for hbird/hbirdv2 processor
+
+## 2024.02
+
+> **Still in development, not official release.**
+
+* Add Nuclei N100 CSR support
+* Nuclei etrace support multicore trace
+* Fix riscv debug 0.11 call riscv_run_algorithm error such as hbird/hbirdv2 processor
+* Update and fix openocd documentation
+* changes are based on [riscv/riscv-openocd](https://github.com/riscv/riscv-openocd/commit/52177592)
+
+## 2023.10
+
+* Add nuclei command group to contains all nuclei customized commands
+* Add `nuclei cpuinfo` dump support
+* Add more spiflash devices according to customer request
+* Fix gdb flash program error on address size > 32bit on windows
+* Update nuclei custom csr
+* Add `ftdi nscan1_mode` to support 2-wire cjtag for Nuclei CPU, which is replacement for `ftdi oscan1_mode`
+* Add nuclei custom command in openocd documentation
+* **Experimental and may change**: Add nuclei etrace command to support nuclei etrace hardware feature
+* changes are based on [riscv/riscv-openocd](https://github.com/riscv/riscv-openocd/commit/52177592)
+
+## 2022.12
+
+This is release 2022.12 of openocd.
+
+* nor/spi:add w25q512jv
+* add 'init resethalt' command
+* feature:auto search custom flashloader path
+* fix riscv-debug v0.11 call riscv_run_algorithm error.
+
+
+## 2022.08
+
+This is release 2022.08 of openocd.
+
+* spi_nor:add xt25f256b mac25l1633e gd25q80b gd25le32e en25s40a by25q32al fm25q128 gd25B512me.
+* merge upstream https://github.com/riscv/riscv-openocd commit id 52177592f9d3afc6a008f8e1b321cf74e823018f.
+* custom flashloader don't rely on 'src/flash/nor/spi.c', fix memory leaks bug.
+
+
+## 2022.04
+
+This is release 2022.04 of openocd.
+
+* add DSP ucode csr register
+* Adjustment simulation timeout param
+* Fix after write_bank/write_image command read date error bug
+* Add custom flash loader in openocd, please refer wiki for how to use it
+* Custom flash loader: add 'simulation' parameter for simulation test.
+
+
+## 2022.01
+
+This is release 2022.01 of openocd.
+
+* optimize cjtag support for nuclei cjtag
+* spi_nor: add BoHong bh25d80a bh25d40a bh25d20a
+* spi_nor: Add Micron MT25QU512
+* flash:"flash bank" command add simulation param
+* add nuclei all custom csr
+* spi_nor: Add MXIC MX25U51245G
+* transport/ftdi: Update to new standard cJTAG sequence
+* flash: add XinSheng RISC-V MCU CM32M4xxR flash program driver
+* Add nuspi loader support.
+* Add nuspi SPI flash driver support.
+* Enable multi-core debug.
+* Previous fespi loader will be rerouted to nuspi loader.
+* Changes are based on [openocd for riscv 0.11.0](https://github.com/riscv/riscv-openocd/commit/6edf98db7f98c5e24bc51cf98419bdf5bbc530e6)
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/VERSION b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/VERSION
new file mode 100644
index 0000000..c698930
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/VERSION
@@ -0,0 +1 @@
+2025.10
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/build-native.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/build-native.sh
new file mode 100644
index 0000000..99aa7dd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/build-native.sh
@@ -0,0 +1,154 @@
+#!/usr/bin/env bash
+# -----------------------------------------------------------------------------
+# This file is part of the xPack distribution.
+#   (https://xpack.github.io)
+# Copyright (c) 2019 Liviu Ionescu.
+#
+# Permission to use, copy, modify, and/or distribute this software 
+# for any purpose is hereby granted, under the terms of the MIT license.
+# -----------------------------------------------------------------------------
+
+# -----------------------------------------------------------------------------
+# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d).
+
+if [[ ! -z ${DEBUG} ]]
+then
+  set ${DEBUG} # Activate the expand mode if DEBUG is anything but empty.
+else
+  DEBUG=""
+fi
+
+set -o errexit # Exit if command failed.
+set -o pipefail # Exit if pipe failed.
+set -o nounset # Exit if variable not set.
+
+# Remove the initial space and instead use '\n'.
+IFS=$'\n\t'
+
+# -----------------------------------------------------------------------------
+# Identify the script location, to reach, for example, the helper scripts.
+
+build_script_path="$0"
+if [[ "${build_script_path}" != /* ]]
+then
+  # Make relative path absolute.
+  build_script_path="$(pwd)/$0"
+fi
+
+script_folder_path="$(dirname "${build_script_path}")"
+script_folder_name="$(basename "${script_folder_path}")"
+
+# =============================================================================
+
+# Script to build a native xPack OpenOCD, which uses the
+# tools and libraries available on the host machine. It is generally
+# intended for development and creating customised versions (as opposed
+# to the build intended for creating distribution packages).
+#
+# Developed on Ubuntu 18 LTS x64 and macOS 10.13. 
+
+# -----------------------------------------------------------------------------
+
+echo
+echo "xPack OpenOCD native build script."
+
+echo
+host_functions_script_path="${script_folder_path}/helper/host-functions-source.sh"
+echo "Host helper functions source script: \"${host_functions_script_path}\"."
+source "${host_functions_script_path}"
+
+host_detect
+
+# -----------------------------------------------------------------------------
+
+help_message="    bash $0 [--win] [--debug] [--develop] [--jobs N] [--help] [clean|cleanlibs|cleanall]"
+host_native_options "${help_message}" $@
+
+# -----------------------------------------------------------------------------
+
+host_common
+
+prepare_xbb_env
+prepare_xbb_extras
+
+# -----------------------------------------------------------------------------
+
+common_libs_functions_script_path="${script_folder_path}/${COMMON_LIBS_FUNCTIONS_SCRIPT_NAME}"
+echo "Common libs functions source script: \"${common_libs_functions_script_path}\"."
+source "${common_libs_functions_script_path}"
+
+common_apps_functions_script_path="${script_folder_path}/${COMMON_APPS_FUNCTIONS_SCRIPT_NAME}"
+echo "Common app functions source script: \"${common_apps_functions_script_path}\"."
+source "${common_apps_functions_script_path}"
+
+# -----------------------------------------------------------------------------
+
+# CHANGES: OpenOCD version
+OPENOCD_PROJECT_NAME=${OPENOCD_PROJECT_NAME:-"openocd"}
+OPENOCD_VERSION=${OPENOCD_VERSION:-"0.11.0"}
+
+OPENOCD_SRC_FOLDER_NAME=${OPENOCD_SRC_FOLDER_NAME:-"${OPENOCD_PROJECT_NAME}.git"}
+OPENOCD_GIT_URL=${OPENOCD_GIT_URL:-"https://github.com/riscv-mcu/riscv-openocd"}
+
+if [ "${IS_DEVELOP}" == "y" ]
+then
+  OPENOCD_GIT_BRANCH=${OPENOCD_GIT_BRANCH:-"nuclei-develop"}
+else
+  OPENOCD_GIT_BRANCH=${OPENOCD_GIT_BRANCH:-"nuclei-master"}
+fi
+
+OPENOCD_GIT_COMMIT=${OPENOCD_GIT_COMMIT:-""}
+
+# Used in the licenses folder.
+OPENOCD_FOLDER_NAME="openocd-${OPENOCD_VERSION}"
+
+# -----------------------------------------------------------------------------
+
+LIBUSB1_VERSION="1.0.22"
+LIBUSB0_VERSION="0.1.5"
+LIBUSB_W32_VERSION="1.2.6.0"
+LIBFTDI_VERSION="1.4"
+LIBICONV_VERSION="1.15"
+HIDAPI_VERSION="0.8.0-rc1"
+
+LIBFTDI_PATCH="libftdi1-${LIBFTDI_VERSION}-cmake-FindUSB1.patch"
+LIBUSB_W32_PATCH="libusb-win32-${LIBUSB_W32_VERSION}-mingw-w64.patch"
+
+# -----------------------------------------------------------------------------
+# Build dependent libraries.
+
+if true
+then
+
+  do_libusb1
+  if [ "${TARGET_PLATFORM}" == "win32" ]
+  then
+    do_libusb_w32
+  else
+    do_libusb0
+  fi
+
+  do_libftdi
+
+  do_libiconv
+
+  do_hidapi
+
+  do_ftd2xx "2.12.28"
+
+fi
+
+# -----------------------------------------------------------------------------
+
+do_openocd
+
+run_openocd
+
+# -----------------------------------------------------------------------------
+
+host_stop_timer
+
+# Completed successfully.
+exit 0
+
+# -----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/build.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/build.sh
new file mode 100644
index 0000000..5ee2d2e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/build.sh
@@ -0,0 +1,189 @@
+#!/usr/bin/env bash
+# -----------------------------------------------------------------------------
+# This file is part of the xPack distribution.
+#   (https://xpack.github.io)
+# Copyright (c) 2019 Liviu Ionescu.
+#
+# Permission to use, copy, modify, and/or distribute this software 
+# for any purpose is hereby granted, under the terms of the MIT license.
+# -----------------------------------------------------------------------------
+
+# -----------------------------------------------------------------------------
+# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d).
+
+if [[ ! -z ${DEBUG} ]]
+then
+  set ${DEBUG} # Activate the expand mode if DEBUG is anything but empty.
+else
+  DEBUG=""
+fi
+
+set -o errexit # Exit if command failed.
+set -o pipefail # Exit if pipe failed.
+set -o nounset # Exit if variable not set.
+
+# Remove the initial space and instead use '\n'.
+IFS=$'\n\t'
+
+# -----------------------------------------------------------------------------
+# Identify the script location, to reach, for example, the helper scripts.
+
+build_script_path="$0"
+if [[ "${build_script_path}" != /* ]]
+then
+  # Make relative path absolute.
+  build_script_path="$(pwd)/$0"
+fi
+
+script_folder_path="$(dirname "${build_script_path}")"
+script_folder_name="$(basename "${script_folder_path}")"
+
+# =============================================================================
+
+# Script to build the xPack OpenOCD distribution packages.
+#
+# Developed on macOS 10.13 High Sierra, but intended to run on
+# macOS 10.10 Yosemite and CentOS 6 XBB. 
+
+# -----------------------------------------------------------------------------
+
+echo
+echo "xPack OpenOCD distribution build script."
+
+host_functions_script_path="${script_folder_path}/helper/host-functions-source.sh"
+source "${host_functions_script_path}"
+
+# -----------------------------------------------------------------------------
+
+# Array where the remaining args will be stored.
+declare -a rest
+
+host_options "    bash $0 [--win32] [--win64] [--linux32] [--linux64] [--osx] [--all] [clean|cleanlibs|cleanall|preload-images] [--env-file file] [--disable-strip] [--without-pdf] [--with-html] [--develop] [--debug] [--jobs N] [--help]" $@
+
+echo
+echo "Host helper functions source script: \"${host_functions_script_path}\"."
+
+host_detect
+
+# docker_linux64_image="ilegeul/centos:6-xbb-v2.1"
+# docker_linux32_image="ilegeul/centos32:6-xbb-v2.1"
+
+host_common
+
+CONTAINER_RUN_AS_ROOT="y"
+
+# -----------------------------------------------------------------------------
+
+if [ ! -z "${DO_BUILD_LINUX64}${DO_BUILD_WIN64}${DO_BUILD_LINUX32}${DO_BUILD_WIN32}" ]
+then
+  host_prepare_docker
+fi
+
+if [ -z "${DO_BUILD_ANY}" ]
+then
+
+  # ----- Build the native distribution. --------------------------------------
+
+  host_build_target "Creating the native distribution..." \
+    --script "${HOST_WORK_FOLDER_PATH}/${CONTAINER_BUILD_SCRIPT_REL_PATH}" \
+    --env-file "${ENV_FILE}" \
+    -- \
+    ${rest[@]-}
+
+else
+
+  # ----- Build the OS X distribution. ----------------------------------------
+
+  if [ "${DO_BUILD_OSX}" == "y" ]
+  then
+    if [ "${HOST_UNAME}" == "Darwin" ]
+    then
+      host_build_target "Creating the OS X distribution..." \
+        --script "${HOST_WORK_FOLDER_PATH}/${CONTAINER_BUILD_SCRIPT_REL_PATH}" \
+        --env-file "${ENV_FILE}" \
+        --target-platform "darwin" \
+        -- \
+        ${rest[@]-}
+    else
+      echo "Building the macOS image is not possible on this platform."
+      exit 1
+    fi
+  fi
+
+  # ----- Build the GNU/Linux 64-bit distribution. ----------------------------
+
+  linux_distribution="centos"
+  
+  if [ "${DO_BUILD_LINUX64}" == "y" ]
+  then
+    host_build_target "Creating the GNU/Linux 64-bit distribution..." \
+      --script "${CONTAINER_WORK_FOLDER_PATH}/${CONTAINER_BUILD_SCRIPT_REL_PATH}" \
+      --env-file "${ENV_FILE}" \
+      --target-platform "linux" \
+      --target-arch "x64" \
+      --target-bits 64 \
+      --docker-image "${docker_linux64_image}" \
+      -- \
+      ${rest[@]-}
+  fi
+
+  # ----- Build the Windows 64-bit distribution. ------------------------------
+
+  if [ "${DO_BUILD_WIN64}" == "y" ]
+  then
+    host_build_target "Creating the Windows 64-bit distribution..." \
+      --script "${CONTAINER_WORK_FOLDER_PATH}/${CONTAINER_BUILD_SCRIPT_REL_PATH}" \
+      --env-file "${ENV_FILE}" \
+      --target-platform "win32" \
+      --target-arch "x64" \
+      --target-bits 64 \
+      --docker-image "${docker_linux64_image}" \
+      -- \
+      ${rest[@]-}
+  fi
+
+  # ----- Build the GNU/Linux 32-bit distribution. ----------------------------
+
+  if [ "${DO_BUILD_LINUX32}" == "y" ]
+  then
+    host_build_target "Creating the GNU/Linux 32-bit distribution..." \
+      --script "${CONTAINER_WORK_FOLDER_PATH}/${CONTAINER_BUILD_SCRIPT_REL_PATH}" \
+      --env-file "${ENV_FILE}" \
+      --target-platform "linux" \
+      --target-arch "x32" \
+      --target-bits 32 \
+      --docker-image "${docker_linux32_image}" \
+      -- \
+      ${rest[@]-}
+  fi
+
+  # ----- Build the Windows 32-bit distribution. ------------------------------
+
+  # Since the actual container is a 32-bit, use the debian32 binaries.
+  if [ "${DO_BUILD_WIN32}" == "y" ]
+  then
+    host_build_target "Creating the Windows 32-bit distribution..." \
+      --script "${CONTAINER_WORK_FOLDER_PATH}/${CONTAINER_BUILD_SCRIPT_REL_PATH}" \
+      --env-file "${ENV_FILE}" \
+      --target-platform "win32" \
+      --target-arch "x32" \
+      --target-bits 32 \
+      --docker-image "${docker_linux32_image}" \
+      -- \
+      ${rest[@]-}
+  fi
+
+fi
+
+host_show_sha
+
+# -----------------------------------------------------------------------------
+
+host_stop_timer
+
+host_notify_completed
+
+# Completed successfully.
+exit 0
+
+# -----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-apps-functions-source.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-apps-functions-source.sh
new file mode 100644
index 0000000..4b476d1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-apps-functions-source.sh
@@ -0,0 +1,404 @@
+# -----------------------------------------------------------------------------
+# This file is part of the xPack distribution.
+#   (https://xpack.github.io)
+# Copyright (c) 2019 Liviu Ionescu.
+#
+# Permission to use, copy, modify, and/or distribute this software
+# for any purpose is hereby granted, under the terms of the MIT license.
+# -----------------------------------------------------------------------------
+
+# Helper script used in the second edition of the xPack build
+# scripts. As the name implies, it should contain only functions and
+# should be included with 'source' by the container build scripts.
+
+# -----------------------------------------------------------------------------
+
+function download_openocd()
+{
+  if [ ! -d "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}" ]
+  then
+    (
+      xbb_activate
+
+      cd "${WORK_FOLDER_PATH}"
+      git_clone "${OPENOCD_GIT_URL}" "${OPENOCD_GIT_BRANCH}" \
+          "${OPENOCD_GIT_COMMIT}" "${OPENOCD_SRC_FOLDER_NAME}"
+      cd "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}"
+      git submodule update --init --recursive --remote
+    )
+  fi
+}
+
+# -----------------------------------------------------------------------------
+
+function do_openocd()
+{
+    download_openocd
+
+    (
+      xbb_activate
+      xbb_activate_installed_dev
+
+      cd "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}"
+      if [ ! -d "autom4te.cache" ]
+      then
+        ./bootstrap
+      fi
+
+      mkdir -p "${APP_BUILD_FOLDER_PATH}"
+      cd "${APP_BUILD_FOLDER_PATH}"
+
+      export JAYLINK_CFLAGS='${XBB_CFLAGS} -fvisibility=hidden'
+
+      if [ "${TARGET_PLATFORM}" == "win32" ]
+      then
+
+        # --enable-minidriver-dummy -> configure error
+        # --enable-zy1000 -> netinet/tcp.h: No such file or directory
+
+        # --enable-openjtag_ftdi -> --enable-openjtag
+        # --enable-presto_libftdi -> --enable-presto
+        # --enable-usb_blaster_libftdi -> --enable-usb_blaster
+
+        export OUTPUT_DIR="${BUILD_FOLDER_PATH}"
+
+        export CFLAGS="${XBB_CXXFLAGS} -Wno-pointer-to-int-cast"
+        export CXXFLAGS="${XBB_CXXFLAGS}"
+        export LDFLAGS="${XBB_LDFLAGS_APP}"
+
+        AMTJTAGACCEL="--enable-amtjtagaccel"
+        # --enable-buspirate -> not supported on mingw
+        BUSPIRATE="--disable-buspirate"
+        GW18012="--enable-gw16012"
+        PARPORT="--enable-parport"
+        PARPORT_GIVEIO="--enable-parport-giveio"
+        # --enable-sysfsgpio -> available only on Linux
+        SYSFSGPIO="--disable-sysfsgpio"
+        FTD2XX="--enable-ftd2xx"
+
+      elif [ "${TARGET_PLATFORM}" == "linux" ]
+      then
+
+        # --enable-minidriver-dummy -> configure error
+
+        # --enable-openjtag_ftdi -> --enable-openjtag
+        # --enable-presto_libftdi -> --enable-presto
+        # --enable-usb_blaster_libftdi -> --enable-usb_blaster
+
+        export CFLAGS="${XBB_CFLAGS} -Wno-format-truncation -Wno-format-overflow"
+        export CXXFLAGS="${XBB_CXXFLAGS}"
+        export LDFLAGS="${XBB_LDFLAGS_APP}"
+        export LIBS="-lpthread -lrt -ludev"
+
+        AMTJTAGACCEL="--enable-amtjtagaccel"
+        BUSPIRATE="--enable-buspirate"
+        GW18012="--enable-gw16012"
+        PARPORT="--enable-parport"
+        PARPORT_GIVEIO="--enable-parport-giveio"
+        SYSFSGPIO="--enable-sysfsgpio"
+        FTD2XX="--disable-ftd2xx"
+
+      elif [ "${TARGET_PLATFORM}" == "darwin" ]
+      then
+
+        # --enable-minidriver-dummy -> configure error
+
+        # --enable-openjtag_ftdi -> --enable-openjtag
+        # --enable-presto_libftdi -> --enable-presto
+        # --enable-usb_blaster_libftdi -> --enable-usb_blaster
+
+        export CFLAGS="${XBB_CFLAGS}"
+        export CXXFLAGS="${XBB_CXXFLAGS}"
+        export LDFLAGS="${XBB_LDFLAGS_APP}"
+        # export LIBS="-lobjc"
+
+        # --enable-amtjtagaccel -> 'sys/io.h' file not found
+        AMTJTAGACCEL="--disable-amtjtagaccel"
+        BUSPIRATE="--enable-buspirate"
+        # --enable-gw16012 -> 'sys/io.h' file not found
+        GW18012="--disable-gw16012"
+        PARPORT="--disable-parport"
+        PARPORT_GIVEIO="--disable-parport-giveio"
+        # --enable-sysfsgpio -> available only on Linux
+        SYSFSGPIO="--disable-sysfsgpio"
+        FTD2XX="--disable-ftd2xx"
+
+      else
+
+        echo "Unsupported target platorm ${TARGET_PLATFORM}."
+        exit 1
+
+      fi
+
+      if [ ! -f "config.status" ]
+      then
+
+        # May be required for repetitive builds, because this is an executable built
+        # in place and using one for a different architecture may not be a good idea.
+        rm -rfv "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}/jimtcl/autosetup/jimsh0"
+
+        (
+          echo
+          echo "Running openocd configure..."
+
+          bash "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}/configure" --help
+
+          bash ${DEBUG} "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}/configure" \
+            --prefix="${APP_PREFIX}"  \
+            \
+            --build=${BUILD} \
+            --host=${HOST} \
+            --target=${TARGET} \
+            \
+            --datarootdir="${INSTALL_FOLDER_PATH}" \
+            --localedir="${APP_PREFIX}/share/locale"  \
+            --mandir="${APP_PREFIX_DOC}/man"  \
+            --pdfdir="${APP_PREFIX_DOC}/pdf"  \
+            --infodir="${APP_PREFIX_DOC}/info" \
+            --docdir="${APP_PREFIX_DOC}"  \
+            \
+            --disable-wextra \
+            --disable-werror \
+            --enable-dependency-tracking \
+            \
+            --enable-branding="${BRANDING}" \
+            \
+            --enable-aice \
+            ${AMTJTAGACCEL} \
+            --enable-armjtagew \
+            --enable-at91rm9200 \
+            --enable-bcm2835gpio \
+            ${BUSPIRATE} \
+            --enable-cmsis-dap \
+            --enable-dummy \
+            --enable-ep93xx \
+            --enable-ftdi \
+            ${GW18012} \
+            --disable-ioutil \
+            --enable-jlink \
+            --enable-internal-libjaylink \
+            --enable-jtag_vpi \
+            --disable-minidriver-dummy \
+            --disable-oocd_trace \
+            --enable-opendous \
+            --enable-openjtag \
+            --enable-osbdm \
+            ${PARPORT} \
+            --disable-parport-ppdev \
+            ${PARPORT_GIVEIO} \
+            --enable-presto \
+            --enable-remote-bitbang \
+            --enable-rlink \
+            --enable-stlink \
+            ${SYSFSGPIO} \
+            --enable-ti-icdi \
+            --enable-ulink \
+            --enable-usb-blaster \
+            --enable-usb_blaster_2 \
+            --enable-usbprog \
+            --enable-vsllink \
+            --disable-zy1000-master \
+            --disable-zy1000 \
+            --enable-jtag_vpi \
+            ${FTD2XX} \
+
+          cp "config.log" "${LOGS_FOLDER_PATH}/config-openocd-log.txt"
+        ) 2>&1 | tee "${LOGS_FOLDER_PATH}/configure-openocd-output.txt"
+
+      fi
+
+      (
+        echo
+        echo "Running openocd make..."
+
+        # Parallel builds fail.
+        make bindir="bin" pkgdatadir="" -j32
+        if [ "${WITH_STRIP}" == "y" ]
+        then
+          make install-strip
+        else
+          make install
+        fi
+
+        if [ "${TARGET_PLATFORM}" == "linux" ]
+        then
+          echo
+          echo "Shared libraries:"
+          echo "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}"
+          readelf -d "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}" | grep 'Shared library:'
+
+          # For just in case, normally must be done by the make file.
+          strip "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}"  || true
+
+          echo
+          echo "Preparing libraries..."
+          patch_linux_elf_origin "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}"
+
+          echo
+          copy_dependencies_recursive "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}" "${APP_PREFIX}/bin"
+        elif [ "${TARGET_PLATFORM}" == "darwin" ]
+        then
+          echo
+          echo "Initial dynamic libraries:"
+          otool -L "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}"
+
+          # For just in case, normally must be done by the make file.
+          strip "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}" || true
+
+          echo
+          echo "Preparing libraries..."
+          copy_dependencies_recursive "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}" "${APP_PREFIX}/bin"
+
+          echo
+          echo "Updated dynamic libraries:"
+          otool -L "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}"
+        elif [ "${TARGET_PLATFORM}" == "win32" ]
+        then
+          echo
+          echo "Dynamic libraries:"
+          echo "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}.exe"
+          ${CROSS_COMPILE_PREFIX}-objdump -x "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}.exe" | grep -i 'DLL Name'
+
+          # For just in case, normally must be done by the make file.
+          ${CROSS_COMPILE_PREFIX}-strip "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}.exe" || true
+
+          rm -f "${APP_PREFIX}/bin/openocdw.exe"
+
+          echo
+          echo "Preparing libraries..."
+          copy_dependencies_recursive "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}.exe" "${APP_PREFIX}/bin"
+        fi
+
+        if [ "${IS_DEVELOP}" != "y" ]
+        then
+          strip_binaries
+          check_application "${APP_EXECUTABLE_NAME}"
+        fi
+
+        (
+          xbb_activate_tex
+
+          if [ "${WITH_PDF}" == "y" ]
+          then
+            make bindir="bin" pkgdatadir="" pdf
+            make install-pdf
+          fi
+
+          if [ "${WITH_HTML}" == "y" ]
+          then
+            make bindir="bin" pkgdatadir="" html
+            make install-html
+          fi
+        )
+
+      ) 2>&1 | tee "${LOGS_FOLDER_PATH}/make-openocd-output.txt"
+    )
+}
+
+function run_openocd()
+{
+  echo
+
+  if [ "${TARGET_PLATFORM}" == "linux" ]
+  then
+    "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}" --version
+  elif [ "${TARGET_PLATFORM}" == "darwin" ]
+  then
+    "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}" --version
+  elif [ "${TARGET_PLATFORM}" == "win32" ]
+  then
+    local wsl_path=$(which wsl.exe)
+    if [ ! -z "${wsl_path}" ]
+    then
+      "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}.exe" --version
+    else
+      (
+        xbb_activate
+        xbb_activate_installed_bin
+
+        local wine_path=$(which wine)
+        if [ ! -z "${wine_path}" ]
+        then
+          wine "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}.exe" --version
+        else
+          echo "Install wine if you want to run the .exe binaries on Linux."
+        fi
+      )
+    fi
+  fi
+}
+
+function strip_binaries()
+{
+  if [ "${WITH_STRIP}" == "y" ]
+  then
+    (
+      xbb_activate
+
+      echo
+      echo "Striping binaries..."
+
+      if [ "${TARGET_PLATFORM}" == "win32" ]
+      then
+        ${CROSS_COMPILE_PREFIX}-strip "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}.exe" || true
+        ${CROSS_COMPILE_PREFIX}-strip "${APP_PREFIX}/bin/"*.dll || true
+      else
+        strip "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}" || true
+        if [ "${TARGET_PLATFORM}" == "linux" ]
+        then
+          : # strip "${APP_PREFIX}/bin/${APP_EXECUTABLE_NAME}" || true
+        fi
+      fi
+    )
+  fi
+}
+
+# -----------------------------------------------------------------------------
+
+function copy_distro_files()
+{
+  (
+    xbb_activate
+
+    rm -rf "${APP_PREFIX}/${DISTRO_INFO_NAME}"
+    mkdir -p "${APP_PREFIX}/${DISTRO_INFO_NAME}"
+
+    echo
+    echo "Copying license files..."
+
+    copy_license \
+      "${SOURCES_FOLDER_PATH}/${LIBUSB1_SRC_FOLDER_NAME}" \
+      "${LIBUSB1_FOLDER_NAME}"
+
+    if [ "${TARGET_PLATFORM}" != "win32" ]
+    then
+      copy_license \
+        "${SOURCES_FOLDER_PATH}/${LIBUSB0_SRC_FOLDER_NAME}" \
+        "${LIBUSB0_FOLDER_NAME}"
+    else
+      copy_license \
+        "${SOURCES_FOLDER_PATH}/${LIBUSB_W32_SRC_FOLDER_NAME}" \
+        "${LIBUSB_W32_FOLDER_NAME}"
+    fi
+
+    copy_license \
+      "${SOURCES_FOLDER_PATH}/${LIBFTDI_SRC_FOLDER_NAME}" \
+      "${LIBFTDI_FOLDER_NAME}"
+    copy_license \
+      "${SOURCES_FOLDER_PATH}/${LIBICONV_SRC_FOLDER_NAME}" \
+      "${LIBICONV_FOLDER_NAME}"
+
+    copy_license \
+      "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}" \
+      "${OPENOCD_FOLDER_NAME}"
+
+    copy_build_files
+
+    echo
+    echo "Copying GME files..."
+
+    cd "${WORK_FOLDER_PATH}/build.git"
+    install -v -c -m 644 "scripts/${README_OUT_FILE_NAME}" \
+      "${APP_PREFIX}/README.md"
+  )
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-functions-source.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-functions-source.sh
new file mode 100644
index 0000000..4f1d934
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-functions-source.sh
@@ -0,0 +1,17 @@
+# -----------------------------------------------------------------------------
+# This file is part of the xPack distribution.
+#   (https://xpack.github.io)
+# Copyright (c) 2019 Liviu Ionescu.
+#
+# Permission to use, copy, modify, and/or distribute this software 
+# for any purpose is hereby granted, under the terms of the MIT license.
+# -----------------------------------------------------------------------------
+
+# Helper script used in the second edition of the xPack build 
+# scripts. As the name implies, it should contain only functions and 
+# should be included with 'source' by the build scripts (both native
+# and container).
+
+# -----------------------------------------------------------------------------
+
+# -----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-libs-functions-source.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-libs-functions-source.sh
new file mode 100644
index 0000000..57c244e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-libs-functions-source.sh
@@ -0,0 +1,685 @@
+# -----------------------------------------------------------------------------
+# This file is part of the xPack distribution.
+#   (https://xpack.github.io)
+# Copyright (c) 2019 Liviu Ionescu.
+#
+# Permission to use, copy, modify, and/or distribute this software
+# for any purpose is hereby granted, under the terms of the MIT license.
+# -----------------------------------------------------------------------------
+
+# Helper script used in the second edition of the xPack build
+# scripts. As the name implies, it should contain only functions and
+# should be included with 'source' by the container build scripts.
+
+# -----------------------------------------------------------------------------
+
+function do_libusb1()
+{
+  # https://sourceforge.net/projects/libusb/files/libusb-1.0/
+  # https://aur.archlinux.org/cgit/aur.git/tree/PKGBUILD?h=mingw-w64-libusb
+
+  # 2015-09-14, 1.0.20
+  # 2018-03-25, 1.0.22
+
+  LIBUSB1_SRC_FOLDER_NAME="libusb-${LIBUSB1_VERSION}"
+  LIBUSB1_FOLDER_NAME="${LIBUSB1_SRC_FOLDER_NAME}"
+  local libusb1_archive="${LIBUSB1_SRC_FOLDER_NAME}.tar.bz2"
+  local libusb1_url="http://sourceforge.net/projects/libusb/files/libusb-1.0/${LIBUSB1_FOLDER_NAME}/${libusb1_archive}"
+
+  local libusb1_stamp_file_path="${INSTALL_FOLDER_PATH}/stamp-libusb1-${LIBUSB1_VERSION}-installed"
+  if [ ! -f "${libusb1_stamp_file_path}" ]
+  then
+
+    cd "${SOURCES_FOLDER_PATH}"
+
+    download_and_extract "${libusb1_url}" "${libusb1_archive}" \
+      "${LIBUSB1_SRC_FOLDER_NAME}"
+
+    (
+      mkdir -p "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB1_FOLDER_NAME}"
+      cd "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB1_FOLDER_NAME}"
+
+      xbb_activate
+      xbb_activate_installed_dev
+
+      if [ "${TARGET_PLATFORM}" == "darwin" ]
+      then
+        # GCC-7 fails to compile Darwin USB.h:
+        # error: too many #pragma options align=reset
+        export CC=clang
+      fi
+
+      export CFLAGS="${XBB_CFLAGS} -Wno-non-literal-null-conversion -Wno-deprecated-declarations  -Wno-format"
+      export CPPFLAGS="${XBB_CPPFLAGS}"
+      export LDFLAGS="${XBB_LDFLAGS_LIB}"
+
+      if [ ! -f "config.status" ]
+      then
+
+        (
+          echo
+          echo "Running libusb1 configure..."
+
+          bash "${SOURCES_FOLDER_PATH}/${LIBUSB1_SRC_FOLDER_NAME}/configure" --help
+
+          # --enable-shared required by libftdi.
+          # --enable-static required by libftdi. (odd...)
+          bash ${DEBUG} "${SOURCES_FOLDER_PATH}/${LIBUSB1_SRC_FOLDER_NAME}/configure" \
+            --prefix="${LIBS_INSTALL_FOLDER_PATH}" \
+            \
+            --build=${BUILD} \
+            --host=${HOST} \
+            --target=${TARGET} \
+            \
+            --enable-shared \
+            --enable-static
+
+          cp "config.log" "${LOGS_FOLDER_PATH}/config-libusb1-log.txt"
+        ) 2>&1 | tee "${LOGS_FOLDER_PATH}/configure-libusb1-output.txt"
+
+      fi
+
+      (
+        echo
+        echo "Running libusb1 make..."
+
+        # Build.
+        # WARNING: Parallel build fails!
+        make
+        if [ "${WITH_STRIP}" == "y" ]
+        then
+          make install-strip
+        else
+          make install
+        fi
+      ) 2>&1 | tee "${LOGS_FOLDER_PATH}/make-libusb1-output.txt"
+    )
+
+    touch "${libusb1_stamp_file_path}"
+
+  else
+    echo "Library libusb1 already installed."
+  fi
+}
+
+# Required by GNU/Linux and macOS.
+function do_libusb0()
+{
+  # https://sourceforge.net/projects/libusb/files/libusb-compat-0.1/
+
+  # 2013-05-21, 0.1.5, latest
+
+  LIBUSB0_SRC_FOLDER_NAME="libusb-compat-${LIBUSB0_VERSION}"
+  LIBUSB0_FOLDER_NAME="${LIBUSB0_SRC_FOLDER_NAME}"
+  local libusb0_archive="${LIBUSB0_SRC_FOLDER_NAME}.tar.bz2"
+  local libusb0_url="http://sourceforge.net/projects/libusb/files/libusb-compat-0.1/${LIBUSB0_FOLDER_NAME}/${libusb0_archive}"
+
+  local libusb0_stamp_file_path="${INSTALL_FOLDER_PATH}/stamp-libusb0-${LIBUSB0_VERSION}-installed"
+  if [ ! -f "${libusb0_stamp_file_path}" ]
+  then
+
+    cd "${SOURCES_FOLDER_PATH}"
+
+    download_and_extract "${libusb0_url}" "${libusb0_archive}" \
+      "${LIBUSB0_SRC_FOLDER_NAME}"
+
+    (
+      mkdir -p "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB0_FOLDER_NAME}"
+      cd "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB0_FOLDER_NAME}"
+
+      xbb_activate
+      xbb_activate_installed_dev
+
+      export CFLAGS="${XBB_CFLAGS}"
+      export CPPFLAGS="${XBB_CPPFLAGS}"
+      export LDFLAGS="${XBB_LDFLAGS_LIB}"
+
+      if [ ! -f "config.status" ]
+      then
+
+        (
+          echo
+          echo "Running libusb0 configure..."
+
+          bash "${SOURCES_FOLDER_PATH}/${LIBUSB0_SRC_FOLDER_NAME}/configure" --help
+
+          bash ${DEBUG} "${SOURCES_FOLDER_PATH}/${LIBUSB0_SRC_FOLDER_NAME}/configure" \
+            --prefix="${LIBS_INSTALL_FOLDER_PATH}" \
+            \
+            --build=${BUILD} \
+            --host=${HOST} \
+            --target=${TARGET} \
+            \
+            --enable-shared \
+            --disable-static
+
+          cp "config.log" "${LOGS_FOLDER_PATH}/config-libusb0-log.txt"
+        ) 2>&1 | tee "${LOGS_FOLDER_PATH}/configure-libusb0-output.txt"
+
+      fi
+
+      (
+        echo
+        echo "Running libusb0 make..."
+
+        # Build.
+        make -j ${JOBS}
+        if [ "${WITH_STRIP}" == "y" ]
+        then
+          make install-strip
+        else
+          make install
+        fi
+      ) 2>&1 | tee "${LOGS_FOLDER_PATH}/make-libusb0-output.txt"
+    )
+
+    touch "${libusb0_stamp_file_path}"
+
+  else
+    echo "Library libusb0 already installed."
+  fi
+}
+
+# Required by Windows.
+function do_libusb_w32()
+{
+  # https://sourceforge.net/projects/libusb-win32/files/libusb-win32-releases/
+  # 2012-01-17, 1.2.6.0
+  # LIBUSB_W32_VERSION="1.2.6.0" # +PATCH!
+
+  LIBUSB_W32_PREFIX="libusb-win32"
+  LIBUSB_W32="${LIBUSB_W32_PREFIX}-${LIBUSB_W32_VERSION}"
+
+  LIBUSB_W32_SRC_FOLDER_NAME="${LIBUSB_W32_PREFIX}-src-${LIBUSB_W32_VERSION}"
+  LIBUSB_W32_FOLDER_NAME="${LIBUSB_W32_SRC_FOLDER_NAME}"
+  local libusb_w32_archive="${LIBUSB_W32_SRC_FOLDER_NAME}.zip"
+  local linusb_w32_url="http://sourceforge.net/projects/libusb-win32/files/libusb-win32-releases/${LIBUSB_W32_VERSION}/${libusb_w32_archive}"
+
+  local libusb_w32_stamp_file_path="${INSTALL_FOLDER_PATH}/stamp-libusb-w32-${LIBUSB_W32_VERSION}-installed"
+  if [ ! -f "${libusb_w32_stamp_file_path}" ]
+  then
+
+    cd "${SOURCES_FOLDER_PATH}"
+
+    download_and_extract "${linusb_w32_url}" "${libusb_w32_archive}" \
+      "${LIBUSB_W32_SRC_FOLDER_NAME}"
+
+    # Mandatory build in the source folder, so make a local copy.
+    rm -rf "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB_W32_FOLDER_NAME}"
+    mkdir -p "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB_W32_FOLDER_NAME}"
+    cp -r "${SOURCES_FOLDER_PATH}/${LIBUSB_W32_SRC_FOLDER_NAME}"/* \
+      "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB_W32_FOLDER_NAME}"
+
+    (
+      echo
+      echo "Running libusb-win32 make..."
+
+      cd "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB_W32_FOLDER_NAME}"
+
+      xbb_activate
+      xbb_activate_installed_dev
+
+      # Patch from:
+      # https://gitorious.org/jtag-tools/openocd-mingw-build-scripts
+
+      # The conversions are needed to avoid errors like:
+      # 'Hunk #1 FAILED at 31 (different line endings).'
+      dos2unix src/install.c
+      dos2unix src/install_filter_win.c
+      dos2unix src/registry.c
+
+      if [ -f "${BUILD_GIT_PATH}/patches/${LIBUSB_W32_PATCH}" ]
+      then
+        patch -p0 < "${BUILD_GIT_PATH}/patches/${LIBUSB_W32_PATCH}"
+      fi
+
+      # Build.
+      (
+          export CFLAGS="${XBB_CFLAGS} -Wno-unknown-pragmas -Wno-unused-variable -Wno-pointer-sign -Wno-unused-but-set-variable"
+          make \
+            host_prefix=${CROSS_COMPILE_PREFIX} \
+            host_prefix_x86=i686-w64-mingw32 \
+            dll
+
+      ) 2>&1 | tee "${LOGS_FOLDER_PATH}/make-libusb-w32-output.txt"
+
+      # Manually install, could not find a make target.
+      mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/bin"
+
+      # Skipping it does not remove the reference from openocd, so for the
+      # moment it is preserved.
+      cp -v "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB_W32_FOLDER_NAME}/libusb0.dll" \
+        "${LIBS_INSTALL_FOLDER_PATH}/bin"
+
+      mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/lib"
+      cp -v "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB_W32_FOLDER_NAME}/libusb.a" \
+        "${LIBS_INSTALL_FOLDER_PATH}/lib"
+
+      mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig"
+      sed -e "s|XXX|${LIBS_INSTALL_FOLDER_PATH}|" \
+        "${BUILD_GIT_PATH}/pkgconfig/${LIBUSB_W32}.pc" \
+        > "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig/libusb.pc"
+
+      mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/include/libusb"
+      cp -v "${LIBS_BUILD_FOLDER_PATH}/${LIBUSB_W32_FOLDER_NAME}/src/lusb0_usb.h" \
+        "${LIBS_INSTALL_FOLDER_PATH}/include/libusb/usb.h"
+    )
+
+    touch "${libusb_w32_stamp_file_path}"
+
+  else
+    echo "Library libusb-w32 already installed."
+  fi
+}
+
+function do_libftdi()
+{
+  # http://www.intra2net.com/en/developer/libftdi/download.php
+  # https://www.intra2net.com/en/developer/libftdi/download/libftdi1-1.4.tar.bz2
+
+  # 1.2 (no date)
+  # LIBFTDI_VERSION="1.2" # +PATCH!
+
+  LIBFTDI_SRC_FOLDER_NAME="libftdi1-${LIBFTDI_VERSION}"
+  LIBFTDI_FOLDER_NAME="${LIBFTDI_SRC_FOLDER_NAME}"
+  local libftdi_archive="${LIBFTDI_SRC_FOLDER_NAME}.tar.bz2"
+
+  libftdi_url="http://www.intra2net.com/en/developer/libftdi/download/${libftdi_archive}"
+
+  local libftdi_stamp_file_path="${INSTALL_FOLDER_PATH}/stamp-libftdi-${LIBFTDI_VERSION}-installed"
+  if [ ! -f "${libftdi_stamp_file_path}" ]
+  then
+
+    cd "${SOURCES_FOLDER_PATH}"
+
+    download_and_extract "${libftdi_url}" "${libftdi_archive}" \
+      "${LIBFTDI_SRC_FOLDER_NAME}" \
+      "${LIBFTDI_PATCH}"
+
+    (
+      mkdir -p "${LIBS_BUILD_FOLDER_PATH}/${LIBFTDI_FOLDER_NAME}"
+      cd "${LIBS_BUILD_FOLDER_PATH}/${LIBFTDI_FOLDER_NAME}"
+
+      xbb_activate
+      xbb_activate_installed_dev
+
+      export CFLAGS="${XBB_CFLAGS}"
+      export CPPFLAGS="${XBB_CPPFLAGS}"
+      export LDFLAGS="${XBB_LDFLAGS_LIB}"
+
+      (
+        echo
+        echo "Running libftdi configure..."
+
+        if [ "${TARGET_PLATFORM}" == "win32" ]
+        then
+
+          # Configure for Windows.
+          cmake \
+          -DPKG_CONFIG_EXECUTABLE="${PKG_CONFIG}" \
+          -DCMAKE_TOOLCHAIN_FILE="${SOURCES_FOLDER_PATH}/${LIBFTDI_SRC_FOLDER_NAME}/cmake/Toolchain-${CROSS_COMPILE_PREFIX}.cmake" \
+          -DCMAKE_INSTALL_PREFIX="${LIBS_INSTALL_FOLDER_PATH}" \
+          -DLIBUSB_INCLUDE_DIR="${LIBS_INSTALL_FOLDER_PATH}/include/libusb-1.0" \
+          -DLIBUSB_LIBRARIES="${LIBS_INSTALL_FOLDER_PATH}/lib/libusb-1.0.a" \
+          -DBUILD_TESTS:BOOL=off \
+          -DFTDIPP:BOOL=off \
+          -DPYTHON_BINDINGS:BOOL=off \
+          -DEXAMPLES:BOOL=off \
+          -DDOCUMENTATION:BOOL=off \
+          -DFTDI_EEPROM:BOOL=off \
+          "${SOURCES_FOLDER_PATH}/${LIBFTDI_SRC_FOLDER_NAME}"
+
+        else
+
+          # Configure for GNU/Linux and macOS.
+          cmake \
+          -DPKG_CONFIG_EXECUTABLE="${PKG_CONFIG}" \
+          -DCMAKE_INSTALL_PREFIX="${LIBS_INSTALL_FOLDER_PATH}" \
+          -DBUILD_TESTS:BOOL=off \
+          -DFTDIPP:BOOL=off \
+          -DPYTHON_BINDINGS:BOOL=off \
+          -DEXAMPLES:BOOL=off \
+          -DDOCUMENTATION:BOOL=off \
+          -DFTDI_EEPROM:BOOL=off \
+          "${SOURCES_FOLDER_PATH}/${LIBFTDI_SRC_FOLDER_NAME}"
+
+        fi
+      ) 2>&1 | tee "${LOGS_FOLDER_PATH}/configure-libftdi-output.txt"
+
+      (
+        echo
+        echo "Running libftdi make..."
+
+        # Build.
+        make -j ${JOBS}
+        make install
+
+      ) 2>&1 | tee "${LOGS_FOLDER_PATH}/make-libftdi-output.txt"
+    )
+
+    touch "${libftdi_stamp_file_path}"
+
+  else
+    echo "Library libftdi already installed."
+  fi
+}
+
+function do_libiconv()
+{
+  # https://www.gnu.org/software/libiconv/
+  # https://ftp.gnu.org/pub/gnu/libiconv/
+  # https://aur.archlinux.org/cgit/aur.git/tree/PKGBUILD?h=libiconv
+
+  # 2011-08-07, "1.14"
+  # 2017-02-02, "1.15", latest
+
+  LIBICONV_SRC_FOLDER_NAME="libiconv-${LIBICONV_VERSION}"
+  LIBICONV_FOLDER_NAME="${LIBICONV_SRC_FOLDER_NAME}"
+  local libiconv_archive="${LIBICONV_SRC_FOLDER_NAME}.tar.gz"
+  local libiconv_url="https://ftp.gnu.org/pub/gnu/libiconv/${libiconv_archive}"
+
+  local libiconv_stamp_file_path="${INSTALL_FOLDER_PATH}/stamp-libiconv-${LIBICONV_VERSION}-installed"
+  if [ ! -f "${libiconv_stamp_file_path}" ]
+  then
+
+    cd "${SOURCES_FOLDER_PATH}"
+
+    download_and_extract "${libiconv_url}" "${libiconv_archive}" \
+      "${LIBICONV_SRC_FOLDER_NAME}"
+
+    (
+      mkdir -p "${LIBS_BUILD_FOLDER_PATH}/${LIBICONV_FOLDER_NAME}"
+      cd "${LIBS_BUILD_FOLDER_PATH}/${LIBICONV_FOLDER_NAME}"
+
+      xbb_activate
+      xbb_activate_installed_dev
+
+      # -fgnu89-inline fixes "undefined reference to `aliases2_lookup'"
+      #  https://savannah.gnu.org/bugs/?47953
+      export CFLAGS="${XBB_CFLAGS} -fgnu89-inline -Wno-tautological-compare -Wno-parentheses-equality -Wno-static-in-inline -Wno-pointer-to-int-cast"
+      export CPPFLAGS="${XBB_CPPFLAGS}"
+      export LDFLAGS="${XBB_LDFLAGS_LIB}"
+
+      if [ ! -f "config.status" ]
+      then
+
+        (
+          echo
+          echo "Running libiconv configure..."
+
+          bash "${SOURCES_FOLDER_PATH}/${LIBICONV_SRC_FOLDER_NAME}/configure" --help
+
+          bash ${DEBUG} "${SOURCES_FOLDER_PATH}/${LIBICONV_SRC_FOLDER_NAME}/configure" \
+            --prefix="${LIBS_INSTALL_FOLDER_PATH}" \
+            \
+            --build=${BUILD} \
+            --host=${HOST} \
+            --target=${TARGET} \
+            \
+            --enable-shared \
+            --disable-static \
+            --disable-nls
+
+          cp "config.log" "${LOGS_FOLDER_PATH}/config-libiconv-log.txt"
+        ) 2>&1 | tee "${LOGS_FOLDER_PATH}/configure-libiconv-output.txt"
+
+      fi
+
+      (
+        echo
+        echo "Running libiconv make..."
+
+        # Build.
+        make -j ${JOBS}
+        if [ "${WITH_STRIP}" == "y" ]
+        then
+          make install-strip
+        else
+          make install
+        fi
+      ) 2>&1 | tee "${LOGS_FOLDER_PATH}/make-libiconv-output.txt"
+    )
+
+    touch "${libiconv_stamp_file_path}"
+
+  else
+    echo "Library libiconv already installed."
+  fi
+}
+
+function do_hidapi()
+{
+  # https://github.com/signal11/hidapi/downloads
+
+  # Oct 26, 2011, "0.7.0"
+
+  # https://github.com/signal11/hidapi/archive/hidapi-0.8.0-rc1.zip
+  # Oct 7, 2013, "0.8.0-rc1", latest
+
+  HIDAPI_SRC_FOLDER_NAME="hidapi-hidapi-${HIDAPI_VERSION}"
+  HIDAPI_FOLDER_NAME="${HIDAPI_SRC_FOLDER_NAME}"
+
+  local hidapi_archive="hidapi-${HIDAPI_VERSION}.zip"
+  local hidapi_url="https://github.com/signal11/hidapi/archive/${hidapi_archive}"
+
+  local hidapi_stamp_file_path="${INSTALL_FOLDER_PATH}/stamp-hidapi-${HIDAPI_VERSION}-installed"
+  if [ ! -f "${hidapi_stamp_file_path}" ]
+  then
+
+    cd "${SOURCES_FOLDER_PATH}"
+
+    download_and_extract "${hidapi_url}" "${hidapi_archive}" \
+      "${HIDAPI_SRC_FOLDER_NAME}"
+
+    # Mandatory build in the source folder, so make a local copy.
+    rm -rf "${LIBS_BUILD_FOLDER_PATH}/${HIDAPI_FOLDER_NAME}"
+    mkdir -p "${LIBS_BUILD_FOLDER_PATH}/${HIDAPI_FOLDER_NAME}"
+    cp -r "${SOURCES_FOLDER_PATH}/${HIDAPI_SRC_FOLDER_NAME}"/* \
+      "${LIBS_BUILD_FOLDER_PATH}/${HIDAPI_FOLDER_NAME}"
+
+    (
+      cd "${LIBS_BUILD_FOLDER_PATH}/${HIDAPI_FOLDER_NAME}"
+
+      xbb_activate
+      xbb_activate_installed_dev
+
+      if [ "${TARGET_PLATFORM}" == "win32" ]
+      then
+
+        HIDAPI_OBJECT="hid.o"
+        HIDAPI_A="libhid.a"
+
+        cd "${LIBS_BUILD_FOLDER_PATH}/${HIDAPI_FOLDER_NAME}/windows"
+
+        export CFLAGS="${XBB_CFLAGS}"
+
+        make -f Makefile.mingw \
+          CC=${CROSS_COMPILE_PREFIX}-gcc \
+          "${HIDAPI_OBJECT}"
+
+        # Make just compiles the file. Create the archive and convert it to library.
+        # No dynamic/shared libs involved.
+        ar -r  libhid.a "${HIDAPI_OBJECT}"
+        ${CROSS_COMPILE_PREFIX}-ranlib libhid.a
+
+        mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/lib"
+        cp -v libhid.a \
+          "${LIBS_INSTALL_FOLDER_PATH}/lib"
+
+        mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig"
+        sed -e "s|XXX|${LIBS_INSTALL_FOLDER_PATH}|" \
+          "${BUILD_GIT_PATH}/pkgconfig/hidapi-${HIDAPI_VERSION}-windows.pc" \
+          > "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig/hidapi.pc"
+
+        mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/include/hidapi"
+        cp -v "${SOURCES_FOLDER_PATH}/${HIDAPI_FOLDER_NAME}/hidapi/hidapi.h" \
+          "${LIBS_INSTALL_FOLDER_PATH}/include/hidapi"
+
+      elif [ "${TARGET_PLATFORM}" == "linux" -o "${TARGET_PLATFORM}" == "darwin" ]
+      then
+
+        if [ "${TARGET_PLATFORM}" == "linux" ]
+        then
+          do_copy_libudev
+
+          export LIBS="-liconv"
+        fi
+
+        echo
+        echo "Running hidapi bootstrap..."
+
+        bash ./bootstrap
+
+        export CFLAGS="${XBB_CFLAGS}"
+        export CPPFLAGS="${XBB_CPPFLAGS}"
+        export LDFLAGS="${XBB_LDFLAGS_LIB}"
+
+        (
+          echo
+          echo "Running hidapi configure..."
+
+          bash "./configure" --help
+
+          bash ${DEBUG} "./configure" \
+            --prefix="${LIBS_INSTALL_FOLDER_PATH}" \
+            \
+            --build=${BUILD} \
+            --host=${HOST} \
+            --target=${TARGET} \
+            \
+            --enable-shared \
+            --disable-static \
+            --disable-testgui
+
+          cp "config.log" "${LOGS_FOLDER_PATH}/config-hidapi-log.txt"
+        ) 2>&1 | tee "${LOGS_FOLDER_PATH}/configure-hidapi-output.txt"
+
+        (
+          echo
+          echo "Running hidapi make..."
+
+          # Build.
+          make -j ${JOBS}
+          if [ "${WITH_STRIP}" == "y" ]
+          then
+            make install-strip
+          else
+            make install
+          fi
+        ) 2>&1 | tee "${LOGS_FOLDER_PATH}/make-hidapi-output.txt"
+
+      fi
+
+      rm -f "${LIBS_INSTALL_FOLDER_PATH}"/lib*/libhidapi-hidraw.la
+    )
+
+    touch "${hidapi_stamp_file_path}"
+
+  else
+    echo "Library hidapi already installed."
+  fi
+}
+
+function do_copy_libudev()
+{
+  cp "/usr/include/libudev.h" "${LIBS_INSTALL_FOLDER_PATH}/include"
+
+  if [ "${TARGET_ARCH}" == "x64" ]
+  then
+    if [ -f "/usr/lib/x86_64-linux-gnu/libudev.so" ]
+    then
+      cp "/usr/lib/x86_64-linux-gnu/libudev.so" "${LIBS_INSTALL_FOLDER_PATH}/lib"
+      cp "/usr/lib/x86_64-linux-gnu/pkgconfig/libudev.pc" "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig"
+    elif [ -f "/lib/x86_64-linux-gnu/libudev.so" ]
+    then
+      # In Debian 9 the location changed to /lib
+      cp "/lib/x86_64-linux-gnu/libudev.so" "${LIBS_INSTALL_FOLDER_PATH}/lib"
+      cp "/usr/lib/x86_64-linux-gnu/pkgconfig/libudev.pc" "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig"
+    elif [ -f "/usr/lib/libudev.so" ]
+    then
+      # In ARCH the location is /usr/lib
+      cp "/usr/lib/libudev.so" "${LIBS_INSTALL_FOLDER_PATH}/lib"
+      cp "/usr/lib/pkgconfig/libudev.pc" "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig"
+    elif [ -f "/usr/lib64/libudev.so" ]
+    then
+      # In CentOS the location is /usr/lib64
+      cp "/usr/lib64/libudev.so" "${LIBS_INSTALL_FOLDER_PATH}/lib"
+      cp "/usr/lib64/pkgconfig/libudev.pc" "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig"
+    else
+      echo "No libudev.so; abort."
+      exit 1
+    fi
+  elif [ "${TARGET_ARCH}" == "x32" ]
+  then
+    if [ -f "/usr/lib/i386-linux-gnu/libudev.so" ]
+    then
+      cp "/usr/lib/i386-linux-gnu/libudev.so" "${LIBS_INSTALL_FOLDER_PATH}/lib"
+      cp "/usr/lib/i386-linux-gnu/pkgconfig/libudev.pc" "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig"
+    elif [ -f "/lib/i386-linux-gnu/libudev.so" ]
+    then
+      # In Debian 9 the location changed to /lib
+      cp "/lib/i386-linux-gnu/libudev.so" "${LIBS_INSTALL_FOLDER_PATH}/lib"
+      cp "/usr/lib/i386-linux-gnu/pkgconfig/libudev.pc" "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig"
+    elif [ -f "/lib/libudev.so.0" ]
+    then
+      # In CentOS the location is /lib
+      cp "/lib/libudev.so.0" "${LIBS_INSTALL_FOLDER_PATH}/lib"
+      cp "/usr/lib/pkgconfig/libudev.pc" "${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig"
+    else
+      echo "No libudev.so; abort."
+      exit 1
+    fi
+  fi
+}
+
+function do_ftd2xx() {
+  FTD2XX_SRC_FOLDER_NAME="ftd2xx"
+  FTD2XX_FOLDER_NAME="${FTD2XX_SRC_FOLDER_NAME}"
+  local ftd2xx_archive="${FTD2XX_SRC_FOLDER_NAME}.zip"
+
+  local FTD2XX_VERSION="$1"
+  local ftd2xx_url="https://www.ftdichip.com/Driver/CDM/CDM%20v${FTD2XX_VERSION}%20WHQL%20Certified.zip"
+
+  local ftd2xx_stamp_file_path="${INSTALL_FOLDER_PATH}/stamp-ftd2xx-${FTD2XX_VERSION}-installed"
+  if [ ! -f "${ftd2xx_stamp_file_path}" ]
+  then
+
+    mkdir -p "${SOURCES_FOLDER_PATH}/${FTD2XX_SRC_FOLDER_NAME}"
+    cd "${SOURCES_FOLDER_PATH}/${FTD2XX_SRC_FOLDER_NAME}"
+
+    # that `echo "A"` is send to unzip to let it overwrite all files
+    echo "A" | download_and_extract "${ftd2xx_url}" "${ftd2xx_archive}" \
+      "${FTD2XX_SRC_FOLDER_NAME}"
+
+    # if using --all on a clean build, linux-* is going to be built eariler than win*.
+    # so we need to create the dirs first
+    mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/../../../win32-x32/install/libs/bin"
+    mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/../../../win32-x64/install/libs/bin"
+
+    # this function is going to be invoked during a linux-* build;
+    # in any case, just put the files in win* directories
+    cp -rv ./i386/*.{dll,lib,sys} "${LIBS_INSTALL_FOLDER_PATH}/../../../win32-x32/install/libs/bin"
+    cp -rv ./amd64/*.{dll,lib,sys} "${LIBS_INSTALL_FOLDER_PATH}/../../../win32-x64/install/libs/bin"
+
+    mv "${LIBS_INSTALL_FOLDER_PATH}/../../../win32-x32/install/libs/bin/ftd2xx.dll" "${LIBS_INSTALL_FOLDER_PATH}/../../../win32-x32/install/libs/bin/FTD2XX.dll"
+    mv "${LIBS_INSTALL_FOLDER_PATH}/../../../win32-x64/install/libs/bin/ftd2xx64.dll" "${LIBS_INSTALL_FOLDER_PATH}/../../../win32-x64/install/libs/bin/FTD2XX.dll"
+
+    # hard code preprocessor
+    # CAVEAT: source code may not be here on the first build; but the first clean build when using `--all`
+    # is a linux build so it doesn't matter if the sources are patched at that time
+    # if you are using --win32 or --win64 in a clean build, this is likely to fail.
+    if [ -d "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}"/src/jtag/drivers ]; then
+      cp -v ./*.h "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}"/src/jtag/drivers/
+      sed -ie "s//\"ftd2xx.h\"/g" "${WORK_FOLDER_PATH}/${OPENOCD_SRC_FOLDER_NAME}"/src/jtag/drivers/mpsse.c
+    fi
+    mkdir -p "${LIBS_INSTALL_FOLDER_PATH}/include"
+    cp -v ./*.h "${LIBS_INSTALL_FOLDER_PATH}/include/"
+
+    touch "${ftd2xx_stamp_file_path}"
+
+    ls "${LIBS_INSTALL_FOLDER_PATH}/include/"
+
+  else
+    echo "Library ftd2xx already installed."
+  fi
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-source-template.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-source-template.sh
new file mode 100644
index 0000000..3f30ced
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-source-template.sh
@@ -0,0 +1,26 @@
+# -----------------------------------------------------------------------------
+# This file is part of the xPack distribution.
+#   (https://xpack.github.io)
+# Copyright (c) 2019 Liviu Ionescu.
+#
+# Permission to use, copy, modify, and/or distribute this software 
+# for any purpose is hereby granted, under the terms of the MIT license.
+# -----------------------------------------------------------------------------
+
+# Helper script used in the second edition of the xPack build 
+# scripts. As the name implies, it should contain only functions and 
+# should be included with 'source' by the build scripts (both native
+# and container).
+
+# -----------------------------------------------------------------------------
+
+# Use this as openocd source code definition template
+# Create your own scripts/common-source.sh
+# -----------------------------------------------------------------------------
+OPENOCD_PROJECT_NAME="openocd"
+OPENOCD_VERSION="0.11.0"
+OPENOCD_GIT_BRANCH="nuclei-develop"
+OPENOCD_GIT_COMMIT=""
+README_OUT_FILE_NAME="README-Changelog.md"
+OPENOCD_GIT_URL="https://github.com/riscv-mcu/riscv-openocd"
+OPENOCD_SRC_FOLDER_NAME="${OPENOCD_PROJECT_NAME}.git"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-versions-source.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-versions-source.sh
new file mode 100644
index 0000000..458e9c0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/common-versions-source.sh
@@ -0,0 +1,162 @@
+# -----------------------------------------------------------------------------
+# This file is part of the xPacks distribution.
+#   (https://xpack.github.io)
+# Copyright (c) 2019 Liviu Ionescu.
+#
+# Permission to use, copy, modify, and/or distribute this software 
+# for any purpose is hereby granted, under the terms of the MIT license.
+# -----------------------------------------------------------------------------
+
+# Helper script used in the second edition of the GNU MCU Eclipse build 
+# scripts. As the name implies, it should contain only functions and 
+# should be included with 'source' by the container build scripts.
+
+# -----------------------------------------------------------------------------
+
+function build_versions()
+{
+  # The \x2C is a comma in hex; without this trick the regular expression
+  # that processes this string in the Makefile, silently fails and the 
+  # bfdver.h file remains empty.
+  BRANDING="${BRANDING}\x2C ${TARGET_MACHINE}"
+
+  OPENOCD_PROJECT_NAME="openocd"
+  OPENOCD_GIT_COMMIT=${OPENOCD_GIT_COMMIT:-""}
+  README_OUT_FILE_NAME="README-${RELEASE_VERSION}.md"
+
+  OPENOCD_SRC_FOLDER_NAME=${OPENOCD_SRC_FOLDER_NAME:-"${OPENOCD_PROJECT_NAME}.git"}
+  OPENOCD_GIT_URL=${OPENOCD_GIT_URL:-"https://github.com/xpack-dev-tools/openocd.git"}
+
+  LIBFTDI_PATCH=""
+  LIBUSB_W32_PATCH=""
+
+  USE_TAR_GZ="y"
+  USE_SINGLE_FOLDER_PATH="y"
+
+  # Keep them in sync with combo archive content.
+  if [[ "${RELEASE_VERSION}" =~ 0\.10\.0-15 ]]
+  then
+    # Nuclei: starting from 0.10.0-15 we do not track upstream (xPack) versions
+    # anymore. 
+    # -------------------------------------------------------------------------
+    
+    OPENOCD_VERSION="0.10.0-15"
+
+    # Used in the licenses folder.
+    OPENOCD_FOLDER_NAME="openocd-${OPENOCD_VERSION}"
+
+    OPENOCD_GIT_BRANCH=${OPENOCD_GIT_BRANCH:-"xpack"}
+    # OPENOCD_GIT_BRANCH=${OPENOCD_GIT_BRANCH:-"xpack-develop"}
+    OPENOCD_GIT_COMMIT=${OPENOCD_GIT_COMMIT:-"e5be992df1a893e2e865419a02a564d5f9ccd9dd"}
+    
+    # -------------------------------------------------------------------------
+
+    do_libusb1 "1.0.22"
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+      do_libusb_w32 "1.2.6.0"
+    else
+      do_libusb0 "0.1.5"
+    fi
+
+    do_libftdi "1.4"
+
+    build_libiconv "1.15"
+
+    do_hidapi "0.8.0-rc1"
+
+    do_ftd2xx "2.12.28"
+
+    # -------------------------------------------------------------------------
+
+    do_openocd
+
+    run_openocd
+
+    # -------------------------------------------------------------------------
+  elif [[ "${RELEASE_VERSION}" =~ 0\.10\.0-14 ]]
+  then
+
+    # -------------------------------------------------------------------------
+    
+    OPENOCD_VERSION="0.10.0-14"
+
+    # Used in the licenses folder.
+    OPENOCD_FOLDER_NAME="openocd-${OPENOCD_VERSION}"
+
+    OPENOCD_GIT_BRANCH=${OPENOCD_GIT_BRANCH:-"xpack"}
+    # OPENOCD_GIT_BRANCH=${OPENOCD_GIT_BRANCH:-"xpack-develop"}
+    OPENOCD_GIT_COMMIT=${OPENOCD_GIT_COMMIT:-"e5be992df1a893e2e865419a02a564d5f9ccd9dd"}
+    
+    # -------------------------------------------------------------------------
+
+    do_libusb1 "1.0.22"
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+      do_libusb_w32 "1.2.6.0"
+    else
+      do_libusb0 "0.1.5"
+    fi
+
+    do_libftdi "1.4"
+
+    build_libiconv "1.15"
+
+    do_hidapi "0.8.0-rc1"
+
+    do_ftd2xx "2.12.28"
+
+    # -------------------------------------------------------------------------
+
+    do_openocd
+
+    run_openocd
+
+    # -------------------------------------------------------------------------
+  elif [[ "${RELEASE_VERSION}" =~ 0\.10\.0-15 ]]
+  then
+
+    # -------------------------------------------------------------------------
+    
+    OPENOCD_VERSION="0.10.0-15"
+
+    # Used in the licenses folder.
+    OPENOCD_FOLDER_NAME="openocd-${OPENOCD_VERSION}"
+
+    OPENOCD_GIT_BRANCH=${OPENOCD_GIT_BRANCH:-"xpack"}
+    OPENOCD_GIT_COMMIT=${OPENOCD_GIT_COMMIT:-"191d1b176cf32280fc649d3c5afcff44d6205daf"}
+    
+    # -------------------------------------------------------------------------
+
+    USE_TAR_GZ=""
+
+    do_libusb1 "1.0.22"
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+      do_libusb_w32 "1.2.6.0"
+    else
+      do_libusb0 "0.1.5"
+    fi
+
+    do_libftdi "1.4"
+
+    build_libiconv "1.15"
+
+    do_hidapi "0.8.0-rc1"
+
+    do_ftd2xx "2.12.28"
+
+    # -------------------------------------------------------------------------
+
+    do_openocd
+
+    run_openocd
+
+    # -------------------------------------------------------------------------
+  else
+    echo "Unsupported version ${RELEASE_VERSION}."
+    exit 1
+  fi
+}
+
+# -----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/container-build.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/container-build.sh
new file mode 100644
index 0000000..c389181
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/container-build.sh
@@ -0,0 +1,266 @@
+#!/usr/bin/env bash
+# -----------------------------------------------------------------------------
+# This file is part of the xPack distribution.
+#   (https://xpack.github.io)
+# Copyright (c) 2019 Liviu Ionescu.
+#
+# Permission to use, copy, modify, and/or distribute this software
+# for any purpose is hereby granted, under the terms of the MIT license.
+# -----------------------------------------------------------------------------
+
+# -----------------------------------------------------------------------------
+# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d).
+
+if [[ ! -z ${DEBUG} ]]
+then
+  set ${DEBUG} # Activate the expand mode if DEBUG is anything but empty.
+else
+  DEBUG=""
+fi
+
+set -o errexit # Exit if command failed.
+set -o pipefail # Exit if pipe failed.
+set -o nounset # Exit if variable not set.
+
+# Remove the initial space and instead use '\n'.
+IFS=$'\n\t'
+
+# -----------------------------------------------------------------------------
+# Identify the script location, to reach, for example, the helper scripts.
+
+build_script_path="$0"
+if [[ "${build_script_path}" != /* ]]
+then
+  # Make relative path absolute.
+  build_script_path="$(pwd)/$0"
+fi
+
+script_folder_path="$(dirname "${build_script_path}")"
+script_folder_name="$(basename "${script_folder_path}")"
+
+# =============================================================================
+
+# Inner script to run inside Docker containers to build the
+# xPack OpenOCD distribution packages.
+
+# For native builds, it runs on the host (macOS build cases,
+# and development builds for GNU/Linux).
+
+# -----------------------------------------------------------------------------
+
+defines_script_path="${script_folder_path}/defs-source.sh"
+echo "Definitions source script: \"${defines_script_path}\"."
+source "${defines_script_path}"
+
+# This file is generated by the host build script.
+host_defines_script_path="${script_folder_path}/host-defs-source.sh"
+echo "Host definitions source script: \"${host_defines_script_path}\"."
+source "${host_defines_script_path}"
+
+common_helper_functions_script_path="${script_folder_path}/helper/common-functions-source.sh"
+echo "Common helper functions source script: \"${common_helper_functions_script_path}\"."
+source "${common_helper_functions_script_path}"
+
+common_functions_script_path="${script_folder_path}/common-functions-source.sh"
+echo "Common functions source script: \"${common_functions_script_path}\"."
+source "${common_functions_script_path}"
+
+# User defined openocd source code, branch, commit, version
+common_source_path="${script_folder_path}/common-source.sh"
+if [ -f ${common_source_path} ] ; then
+  echo "Common source script: \"${common_source_path}\"."
+  source "${common_source_path}"
+fi
+
+container_functions_script_path="${script_folder_path}/helper/container-functions-source.sh"
+echo "Container helper functions source script: \"${container_functions_script_path}\"."
+source "${container_functions_script_path}"
+
+container_libs_functions_script_path="${script_folder_path}/${COMMON_LIBS_FUNCTIONS_SCRIPT_NAME}"
+echo "Container libs functions source script: \"${container_libs_functions_script_path}\"."
+source "${container_libs_functions_script_path}"
+
+container_app_functions_script_path="${script_folder_path}/${COMMON_APPS_FUNCTIONS_SCRIPT_NAME}"
+echo "Container app functions source script: \"${container_app_functions_script_path}\"."
+source "${container_app_functions_script_path}"
+
+# -----------------------------------------------------------------------------
+
+if [ ! -z "#{DEBUG}" ]
+then
+  echo $@
+fi
+
+WITH_STRIP="y"
+WITH_PDF="y"
+WITH_HTML="n"
+IS_DEVELOP=""
+IS_DEBUG=""
+
+JOBS=""
+
+while [ $# -gt 0 ]
+do
+
+  case "$1" in
+
+    --disable-strip)
+      WITH_STRIP="n"
+      shift
+      ;;
+
+    --without-pdf)
+      WITH_PDF="n"
+      shift
+      ;;
+
+    --with-pdf)
+      WITH_PDF="y"
+      shift
+      ;;
+
+    --without-html)
+      WITH_HTML="n"
+      shift
+      ;;
+
+    --with-html)
+      WITH_HTML="y"
+      shift
+      ;;
+
+    --jobs)
+      JOBS=$2
+      shift 2
+      ;;
+
+    --develop)
+      IS_DEVELOP="y"
+      shift
+      ;;
+
+    --debug)
+      IS_DEBUG="y"
+      shift
+      ;;
+
+    *)
+      echo "Unknown action/option $1"
+      exit 1
+      ;;
+
+  esac
+
+done
+
+if [ "${IS_DEBUG}" == "y" ]
+then
+  WITH_STRIP="n"
+fi
+
+# -----------------------------------------------------------------------------
+
+start_timer
+
+detect_container
+
+prepare_xbb_env
+
+prepare_xbb_extras
+
+# -----------------------------------------------------------------------------
+
+# The \x2C is a comma in hex; without this trick the regular expression
+# that processes this string in the Makefile, silently fails and the
+# bfdver.h file remains empty.
+BRANDING="${BRANDING}\x2C ${TARGET_BITS}-bit"
+
+OPENOCD_PROJECT_NAME=${OPENOCD_PROJECT_NAME:-"openocd"}
+OPENOCD_VERSION=${OPENOCD_VERSION:-"0.11.0"}
+OPENOCD_GIT_BRANCH=${OPENOCD_GIT_BRANCH:-"nuclei-develop"}
+OPENOCD_GIT_COMMIT=${OPENOCD_GIT_COMMIT:-""}
+README_OUT_FILE_NAME=${README_OUT_FILE_NAME:-"README-Changelog.md"}
+OPENOCD_GIT_URL=${OPENOCD_GIT_URL:-"https://github.com/riscv-mcu/riscv-openocd"}
+OPENOCD_SRC_FOLDER_NAME=${OPENOCD_SRC_FOLDER_NAME:-"${OPENOCD_PROJECT_NAME}.git"}
+
+LIBFTDI_PATCH=""
+LIBUSB_W32_PATCH=""
+
+# Keep them in sync with combo archive content.
+if true
+then
+
+  # ---------------------------------------------------------------------------
+
+  # ---------------------------------------------------------------------------
+
+  LIBUSB1_VERSION="1.0.22"
+  LIBUSB0_VERSION="0.1.5"
+  LIBUSB_W32_VERSION="1.2.6.0"
+  LIBFTDI_VERSION="1.4"
+  LIBICONV_VERSION="1.15"
+  HIDAPI_VERSION="0.8.0-rc1"
+
+  LIBFTDI_PATCH="libftdi1-${LIBFTDI_VERSION}-cmake-FindUSB1.patch"
+  LIBUSB_W32_PATCH="libusb-win32-${LIBUSB_W32_VERSION}-mingw-w64.patch"
+
+  # ---------------------------------------------------------------------------
+else
+  echo "Unsupported version ${RELEASE_VERSION}."
+  exit 1
+fi
+
+# -----------------------------------------------------------------------------
+
+# Used in the licenses folder.
+OPENOCD_FOLDER_NAME="openocd-${OPENOCD_VERSION}"
+
+# -----------------------------------------------------------------------------
+
+echo
+echo "Here we go..."
+echo
+
+# -----------------------------------------------------------------------------
+# Build dependent libraries.
+
+do_libusb1
+if [ "${TARGET_PLATFORM}" == "win32" ]
+then
+  do_libusb_w32
+else
+  do_libusb0
+fi
+
+do_libftdi
+
+do_libiconv
+
+do_hidapi
+
+do_ftd2xx "2.12.28"
+
+# -----------------------------------------------------------------------------
+
+do_openocd
+
+run_openocd
+
+# -----------------------------------------------------------------------------
+
+check_binaries
+
+copy_distro_files
+
+create_archive
+
+# Change ownership to non-root Linux user.
+fix_ownership
+
+# -----------------------------------------------------------------------------
+
+stop_timer
+
+exit 0
+
+# -----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/defs-source.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/defs-source.sh
new file mode 100644
index 0000000..39e4f48
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/defs-source.sh
@@ -0,0 +1,42 @@
+# -----------------------------------------------------------------------------
+# This file is part of the xPack distribution.
+#   (https://xpack.github.io)
+# Copyright (c) 2019 Liviu Ionescu.
+#
+# Permission to use, copy, modify, and/or distribute this software 
+# for any purpose is hereby granted, under the terms of the MIT license.
+# -----------------------------------------------------------------------------
+
+# Helper script used in the second edition of the build scripts.
+# As the name implies, it should contain only definitions and should
+# be included with 'source' by the host and container scripts.
+
+# Warning: MUST NOT depend on $HOME or other environment variables.
+
+# -----------------------------------------------------------------------------
+
+# Used to display the application name.
+APP_NAME=${APP_NAME:-"OpenOCD"}
+APP_BUILD=${APP_BUILD:-"build"}
+
+# Used as part of file/folder paths.
+APP_UC_NAME=${APP_UC_NAME:-"OpenOCD"}
+APP_LC_NAME=${APP_LC_NAME:-"openocd"}
+
+APP_EXECUTABLE_NAME=${APP_EXECUTABLE_NAME:-"openocd"}
+
+DISTRO_UC_NAME=${DISTRO_UC_NAME:-"Nuclei"}
+DISTRO_LC_NAME=${DISTRO_LC_NAME:-"nuclei"}
+DISTRO_TOP_FOLDER=${DISTRO_TOP_FOLDER:-"Nuclei"}
+
+# Use the new xPack naming convention.
+HAS_NAME_ARCH="y"
+
+BRANDING=${BRANDING:-"${DISTRO_UC_NAME} OpenOCD"}
+
+CONTAINER_SCRIPT_NAME=${CONTAINER_SCRIPT_NAME:-"container-build.sh"}
+
+COMMON_LIBS_FUNCTIONS_SCRIPT_NAME=${COMMON_LIBS_FUNCTIONS_SCRIPT_NAME:-"common-libs-functions-source.sh"}
+COMMON_APPS_FUNCTIONS_SCRIPT_NAME=${COMMON_APPS_FUNCTIONS_SCRIPT_NAME:-"common-apps-functions-source.sh"}
+
+# -----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/git-clone.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/git-clone.sh
new file mode 100644
index 0000000..0f4f1b6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/git-clone.sh
@@ -0,0 +1,3 @@
+#!/usr/bin/env bash
+rm -rf "${HOME}/Downloads/openocd-xpack.git"
+git clone --branch xpack_nuclei_next --recurse-submodules https://github.com/riscv-mcu/openocd-xpack.git "${HOME}/Downloads/openocd-xpack.git"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/LICENSE b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/LICENSE
new file mode 100644
index 0000000..79612f3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/LICENSE
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2017 Liviu Ionescu
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/README.md b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/README.md
new file mode 100644
index 0000000..b042a46
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/README.md
@@ -0,0 +1,54 @@
+# build-helper
+
+Common script used in other build scripts.
+
+- `host-functions-source.sh`: to be included with `source` in the host build script
+- `container-functions-source.sh`: to be included with `source` in the container build script
+
+Deprecated:
+
+- `builder-helper.sh`: used in the first generation of build scripts.
+
+# Patches
+
+The code used to download and extract archives can also be used
+to post-patch the downloaded files. For this a patch file must be
+placed in the `patches` folder, and the name must be passed as the
+third param to `extract()`.
+
+## Memo
+
+The code to apply the patch (`common-functions-source.sh:extract()`) does 
+the following:
+
+```console
+$ cd sources/binutils
+$ patch -p0 < "binutils-2.31.patch"
+```
+
+The patch is applied from the library source folder, so it must be created
+with the library relative path.
+
+For example, to create a binutils patch, use:
+
+```console
+$ cd sources/binutils
+$ cp bfd/ihex.c bfd/ihex-patched.c
+$ vi bfd/ihex-patched.c
+$ diff -u bfd/ihex.c bfd/ihex-patched.c > patches/binutils-2.31.patch
+```
+
+
+There may also be git patches; they are applied with `git apply file.git-patch`.
+
+To create a patch with the uncommitted changes: 
+
+```console
+$ git diff > file.git-patch
+```
+
+Links:
+
+- https://git-scm.com/docs/git-diff
+- https://git-scm.com/docs/git-apply
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/common-functions-source.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/common-functions-source.sh
new file mode 100644
index 0000000..8472c1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/common-functions-source.sh
@@ -0,0 +1,1826 @@
+# -----------------------------------------------------------------------------
+
+# Helper script used in the second edition of the xPack build 
+# scripts. As the name implies, it should contain only functions and 
+# should be included with 'source' by the build scripts (both native
+# and container).
+
+# -----------------------------------------------------------------------------
+
+# Default empty definition, if XBB is available, it should
+# redefine it.
+function xbb_activate()
+{
+  :
+}
+
+# Add the freshly built binaries.
+function xbb_activate_installed_bin()
+{
+  # Add the XBB bin to the PATH.
+  PATH="${LIBS_INSTALL_FOLDER_PATH}/bin:${PATH}"
+
+  # Add the XBB lib to the LD_LIBRARY_PATH.
+  LD_LIBRARY_PATH="${LIBS_INSTALL_FOLDER_PATH}/lib:${LD_LIBRARY_PATH}"
+
+  if [ -d "${LIBS_INSTALL_FOLDER_PATH}/lib64" ]
+  then
+    # On 64-bit systems, add lib64 to the LD_LIBRARY_PATH.
+    LD_LIBRARY_PATH="${LIBS_INSTALL_FOLDER_PATH}/lib64:${LD_LIBRARY_PATH}"
+  fi
+
+  export PATH
+  export LD_LIBRARY_PATH
+}
+
+# Add the freshly built headrs and libraries.
+function xbb_activate_installed_dev()
+{
+  # Add XBB include in front of XBB_CPPFLAGS.
+  XBB_CPPFLAGS="-I${LIBS_INSTALL_FOLDER_PATH}/include ${XBB_CPPFLAGS}"
+
+  # Add XBB lib in front of XBB_LDFLAGS.
+  XBB_LDFLAGS="-L${LIBS_INSTALL_FOLDER_PATH}/lib ${XBB_LDFLAGS}"
+  XBB_LDFLAGS_LIB="-L${LIBS_INSTALL_FOLDER_PATH}/lib ${XBB_LDFLAGS_LIB}"
+  XBB_LDFLAGS_APP="-L${LIBS_INSTALL_FOLDER_PATH}/lib ${XBB_LDFLAGS_APP}"
+  XBB_LDFLAGS_APP_STATIC_GCC="-L${LIBS_INSTALL_FOLDER_PATH}/lib ${XBB_LDFLAGS_APP_STATIC_GCC}"
+
+  # Add XBB lib in front of PKG_CONFIG_PATH.
+  PKG_CONFIG_PATH="${LIBS_INSTALL_FOLDER_PATH}/lib/pkgconfig:${PKG_CONFIG_PATH}"
+
+  LD_LIBRARY_PATH="${LIBS_INSTALL_FOLDER_PATH}/lib:${LD_LIBRARY_PATH}"
+
+  if [ -d "${LIBS_INSTALL_FOLDER_PATH}/lib64" ]
+  then
+    # For 64-bit systems, add XBB lib64 in front of paths.
+    XBB_LDFLAGS="-L${LIBS_INSTALL_FOLDER_PATH}/lib64 ${XBB_LDFLAGS_LIB}"
+    XBB_LDFLAGS_LIB="-L${LIBS_INSTALL_FOLDER_PATH}/lib64 ${XBB_LDFLAGS_LIB}"
+    XBB_LDFLAGS_APP="-L${LIBS_INSTALL_FOLDER_PATH}/lib64 ${XBB_LDFLAGS_APP}"
+    XBB_LDFLAGS_APP_STATIC_GCC="-L${LIBS_INSTALL_FOLDER_PATH}/lib64 ${XBB_LDFLAGS_APP_STATIC_GCC}"
+
+    PKG_CONFIG_PATH="${LIBS_INSTALL_FOLDER_PATH}/lib64/pkgconfig:${PKG_CONFIG_PATH}"
+
+    LD_LIBRARY_PATH="${LIBS_INSTALL_FOLDER_PATH}/lib64:${LD_LIBRARY_PATH}"
+  fi
+
+  export XBB_CPPFLAGS
+
+  export XBB_LDFLAGS
+  export XBB_LDFLAGS_LIB
+  export XBB_LDFLAGS_APP
+  export XBB_LDFLAGS_APP_STATIC_GCC
+
+  export PKG_CONFIG_PATH
+  export LD_LIBRARY_PATH
+}
+
+# -----------------------------------------------------------------------------
+
+function do_config_guess() 
+{
+  if [ -f "${XBB_FOLDER}/share/libtool/build-aux/config.guess" ]
+  then
+    BUILD="$(${XBB_FOLDER}/share/libtool/build-aux/config.guess)"
+  elif [ -f "/usr/share/libtool/build-aux/config.guess" ]
+  then
+    BUILD="$(/usr/share/libtool/build-aux/config.guess)"
+  elif [ -f "/usr/share/misc/config.guess" ]
+  then
+    BUILD="$(/usr/share/misc/config.guess)"
+  else
+    echo "Could not find config.guess."
+    exit 1
+  fi
+}
+
+function prepare_xbb_env() 
+{
+  # Defaults, to ensure the variables are defined.
+  PATH="${PATH:-""}"
+  LD_LIBRARY_PATH="${LD_LIBRARY_PATH:-""}"
+
+  # Without this, on 32-bit the bootstrap perl fails to find libcrypt.
+  # LD_LIBRARY_PATH="/lib:${LD_LIBRARY_PATH}"
+
+  if [ -f "${HOME}/opt/xbb/xbb-source.sh" ]
+  then
+    echo
+    echo "Sourcing ${HOME}/opt/xbb/xbb-source.sh..."
+    source "${HOME}/opt/xbb/xbb-source.sh"
+  elif [ -f "${HOME}/opt/homebrew/xbb/xbb-source.sh" ]
+  then
+    # Deprecated, on macOS it was moved to HOME/opt/xbb
+    echo
+    echo "Sourcing ${HOME}/opt/homebrew/xbb/xbb-source.sh..."
+    source "${HOME}/opt/homebrew/xbb/xbb-source.sh"
+  elif [ -f "/opt/xbb/xbb-source.sh" ]
+  then
+    echo
+    echo "Sourcing /opt/xbb/xbb-source.sh..."
+    source "/opt/xbb/xbb-source.sh"
+  fi
+
+  TARGET_FOLDER_NAME="${TARGET_PLATFORM}-${TARGET_ARCH}"
+
+  # Compute the BUILD/HOST/TARGET for configure.
+  CROSS_COMPILE_PREFIX=""
+  if [ "${TARGET_PLATFORM}" == "win32" ]
+  then
+
+    # For Windows targets, decide which cross toolchain to use.
+    if [ ${TARGET_ARCH} == "x32" ]
+    then
+      CROSS_COMPILE_PREFIX="i686-w64-mingw32"
+    elif [ ${TARGET_ARCH} == "x64" ]
+    then
+      CROSS_COMPILE_PREFIX="x86_64-w64-mingw32"
+    fi
+
+    do_config_guess
+
+    HOST="${CROSS_COMPILE_PREFIX}"
+    TARGET="${HOST}"
+
+  elif [ "${TARGET_PLATFORM}" == "darwin" ]
+  then
+
+    TARGET_BITS="64" # For now, only 64-bit macOS binaries
+
+    do_config_guess
+
+    HOST="${BUILD}"
+    TARGET="${HOST}"
+
+  elif [ "${TARGET_PLATFORM}" == "linux" ]
+  then
+
+    do_config_guess
+
+    HOST="${BUILD}"
+    TARGET="${HOST}"
+
+  else
+    echo "Unsupported target platform ${TARGET_PLATFORM}"
+    exit 1
+  fi
+
+  if [ -f "/.dockerenv" -o -f "/run/.containerenv" ]
+  then
+    WORK_FOLDER_PATH="${CONTAINER_WORK_FOLDER_PATH}"
+    DOWNLOAD_FOLDER_PATH="${CONTAINER_CACHE_FOLDER_PATH}"
+  else
+    WORK_FOLDER_PATH="${HOST_WORK_FOLDER_PATH}"
+    DOWNLOAD_FOLDER_PATH="${HOST_CACHE_FOLDER_PATH}"
+  fi
+
+  # Develop builds use the host folder.
+  BUILD_FOLDER_PATH="${WORK_FOLDER_PATH}/${TARGET_FOLDER_NAME}/build"
+  if [ -f "/.dockerenv" -o -f "/run/.containerenv" ]
+  then 
+    if [ "${IS_DEVELOP}" != "y" ]
+    then
+      # Docker builds use a temporary folder.
+      BUILD_FOLDER_PATH="/tmp/${TARGET_FOLDER_NAME}/build"
+    fi
+  fi
+
+  LIBS_BUILD_FOLDER_PATH="${BUILD_FOLDER_PATH}/libs"
+  mkdir -p "${LIBS_BUILD_FOLDER_PATH}"
+
+  APP_BUILD_FOLDER_PATH="${BUILD_FOLDER_PATH}/${APP_LC_NAME}"
+  # Do it later, only if needed.
+  # mkdir -p "${APP_BUILD_FOLDER_PATH}"
+
+  INSTALL_FOLDER_PATH="${WORK_FOLDER_PATH}/${TARGET_FOLDER_NAME}/install"
+
+  LIBS_INSTALL_FOLDER_PATH="${INSTALL_FOLDER_PATH}/libs"
+  mkdir -p "${LIBS_INSTALL_FOLDER_PATH}"
+
+  APP_INSTALL_FOLDER_PATH="${INSTALL_FOLDER_PATH}/${APP_LC_NAME}"
+  mkdir -p "${APP_INSTALL_FOLDER_PATH}"
+
+  LOGS_FOLDER_NAME=${LOGS_FOLDER_NAME:-"logs"}
+  LOGS_FOLDER_PATH="${WORK_FOLDER_PATH}/${TARGET_FOLDER_NAME}/${LOGS_FOLDER_NAME}"
+  mkdir -p "${LOGS_FOLDER_PATH}"
+
+  DEPLOY_FOLDER_NAME=${DEPLOY_FOLDER_NAME:-"deploy"}
+  DEPLOY_FOLDER_PATH="${WORK_FOLDER_PATH}/${DEPLOY_FOLDER_NAME}"
+  # Do it later, only if needed.
+  # mkdir -p "${DEPLOY_FOLDER_PATH}"
+
+  DISTRO_INFO_NAME=${DISTRO_INFO_NAME:-"distro-info"}
+  
+  BUILD_GIT_PATH="${WORK_FOLDER_PATH}/build.git"
+
+  # ---------------------------------------------------------------------------
+
+  APP_PREFIX="${INSTALL_FOLDER_PATH}/${APP_LC_NAME}"
+  if [ "${TARGET_PLATFORM}" == "win32" ]
+  then
+    APP_PREFIX_DOC="${APP_PREFIX}/doc"
+  else
+    # For POSIX platforms, keep the tradition.
+    APP_PREFIX_DOC="${APP_PREFIX}/share/doc"
+  fi
+
+  # ---------------------------------------------------------------------------
+
+  SOURCES_FOLDER_PATH=${SOURCES_FOLDER_PATH:-"${WORK_FOLDER_PATH}/sources"}
+  mkdir -p "${SOURCES_FOLDER_PATH}"
+
+  # Empty defaults.
+  IS_DEVELOP=${IS_DEVELOP:-""}
+  IS_DEBUG=${IS_DEBUG:-""}
+  WITH_PDF=${WITH_PDF:-""}
+  WITH_HTML=${WITH_HTML:-""}
+
+  # Redefine this to "y" to create files that include the architecture.
+  HAS_NAME_ARCH=${HAS_NAME_ARCH:-""}
+
+  # ---------------------------------------------------------------------------
+
+  export PATH
+  export LD_LIBRARY_PATH
+
+  export SOURCES_FOLDER_PATH
+
+  # libtool fails with the Ubuntu /bin/sh.
+  export SHELL="/bin/bash"
+  export CONFIG_SHELL="/bin/bash"
+}
+
+function prepare_xbb_extras()
+{
+  # ---------------------------------------------------------------------------
+
+  XBB_CPPFLAGS=""
+
+  XBB_CFLAGS="-ffunction-sections -fdata-sections -m${TARGET_BITS} -pipe"
+  XBB_CXXFLAGS="-ffunction-sections -fdata-sections -m${TARGET_BITS} -pipe"
+
+  XBB_LDFLAGS=""
+
+  if [ "${IS_DEBUG}" == "y" ]
+  then
+    XBB_CFLAGS+=" -g -O0"
+    XBB_CXXFLAGS+=" -g -O0"
+    XBB_LDFLAGS+=" -g -O0"
+  else
+    XBB_CFLAGS+=" -O2"
+    XBB_CXXFLAGS+=" -O2"
+    XBB_LDFLAGS+=" -O2"
+  fi
+
+  if [ "${TARGET_PLATFORM}" == "linux" ]
+  then
+    local which_gcc_7="$(xbb_activate; which "g++-7")"
+    if [ ! -z "${which_gcc_7}" ]
+    then
+      CC="gcc-7"
+      CXX="g++-7"
+    else
+      CC="gcc"
+      CXX="g++"
+    fi
+    # Do not add -static here, it fails.
+    # Do not try to link pthread statically, it must match the system glibc.
+    XBB_LDFLAGS_LIB="${XBB_LDFLAGS}"
+    XBB_LDFLAGS_APP="${XBB_LDFLAGS} -Wl,--gc-sections"
+    XBB_LDFLAGS_APP_STATIC_GCC="${XBB_LDFLAGS_APP} -static-libgcc -static-libstdc++"
+  elif [ "${TARGET_PLATFORM}" == "darwin" ]
+  then
+    CC="gcc-7"
+    CXX="g++-7"
+    # Note: macOS linker ignores -static-libstdc++, so 
+    # libstdc++.6.dylib should be handled.
+    XBB_LDFLAGS+=" -Wl,-macosx_version_min,10.10"
+    XBB_LDFLAGS_LIB="${XBB_LDFLAGS}"
+    XBB_LDFLAGS_APP="${XBB_LDFLAGS} -Wl,-dead_strip"
+    XBB_LDFLAGS_APP_STATIC_GCC="${XBB_LDFLAGS_APP}"
+  elif [ "${TARGET_PLATFORM}" == "win32" ]
+  then
+    # CRT_glob is from ARM script
+    # -static avoids libwinpthread-1.dll 
+    # -static-libgcc avoids libgcc_s_sjlj-1.dll 
+    XBB_LDFLAGS_LIB="${XBB_LDFLAGS}"
+    XBB_LDFLAGS_APP="${XBB_LDFLAGS} -Wl,--gc-sections"
+    XBB_LDFLAGS_APP_STATIC_GCC="${XBB_LDFLAGS_APP} -static-libgcc -static-libstdc++"
+  fi
+
+  set +u
+  if [ ! -z "${XBB_FOLDER}" -a -x "${XBB_FOLDER}/bin/pkg-config-verbose" ]
+  then
+    PKG_CONFIG="${XBB_FOLDER}/bin/pkg-config-verbose"
+  fi
+  set -u
+
+  PKG_CONFIG_PATH=${PKG_CONFIG_PATH:-":"}
+
+  # Prevent pkg-config to search the system folders (configured in the
+  # pkg-config at build time).
+  PKG_CONFIG_LIBDIR=${PKG_CONFIG_LIBDIR:-":"}
+
+  set +u
+  echo
+  echo "CC=${CC}"
+  echo "CXX=${CXX}"
+  echo "XBB_CPPFLAGS=${XBB_CPPFLAGS}"
+  echo "XBB_CFLAGS=${XBB_CFLAGS}"
+  echo "XBB_CXXFLAGS=${XBB_CXXFLAGS}"
+
+  echo "XBB_LDFLAGS_LIB=${XBB_LDFLAGS_LIB}"
+  echo "XBB_LDFLAGS_APP=${XBB_LDFLAGS_APP}"
+  echo "XBB_LDFLAGS_APP_STATIC_GCC=${XBB_LDFLAGS_APP_STATIC_GCC}"
+
+  echo "PKG_CONFIG=${PKG_CONFIG}"
+  echo "PKG_CONFIG_PATH=${PKG_CONFIG_PATH}"
+  echo "PKG_CONFIG_LIBDIR=${PKG_CONFIG_LIBDIR}"
+  set -u
+
+  (
+    xbb_activate
+
+    echo
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+      which ${CROSS_COMPILE_PREFIX}-gcc
+      ${CROSS_COMPILE_PREFIX}-gcc --version
+    else
+      which ${CC}
+      ${CC} --version
+    fi
+
+    which make
+    make --version
+  )
+
+  set +u
+  if [ "${TARGET_PLATFORM}" == "win32" -a ! -z "${CC}" -a ! -z  "${CXX}" ]
+  then
+    echo "CC and CXX must not be set for cross builds."
+    exit 1
+  fi
+  set -u
+
+  # ---------------------------------------------------------------------------
+
+  export XBB_CPPFLAGS
+
+  export XBB_CFLAGS
+  export XBB_CXXFLAGS
+
+  export XBB_LDFLAGS
+  export XBB_LDFLAGS_LIB
+  export XBB_LDFLAGS_APP
+  export XBB_LDFLAGS_APP_STATIC_GCC
+
+  export CC
+  export CXX
+
+
+  export PKG_CONFIG
+  export PKG_CONFIG_PATH
+  export PKG_CONFIG_LIBDIR
+
+}
+
+# -----------------------------------------------------------------------------
+
+function do_actions()
+{
+  if [ "${ACTION}" == "clean" ]
+  then
+    echo
+
+    if [ "${IS_NATIVE}" == "y" ]
+    then
+      echo "Removing the ${TARGET_FOLDER_NAME} build and install ${APP_LC_NAME} folders..."
+
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${TARGET_FOLDER_NAME}/build/${APP_LC_NAME}"
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${TARGET_FOLDER_NAME}/install/${APP_LC_NAME}"
+    elif [ ! -z "${DO_BUILD_WIN32}${DO_BUILD_WIN64}${DO_BUILD_LINUX32}${DO_BUILD_LINUX64}${DO_BUILD_OSX}" ]
+    then
+      if [ "${DO_BUILD_WIN32}" == "y" ]
+      then
+        echo "Removing the win32-x32 build and install ${APP_LC_NAME} folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x32/build/${APP_LC_NAME}"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x32/install/${APP_LC_NAME}"
+      fi
+      if [ "${DO_BUILD_WIN64}" == "y" ]
+      then
+        echo "Removing the win32-x64 build and install ${APP_LC_NAME} folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x64/build/${APP_LC_NAME}"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x64/install/${APP_LC_NAME}"
+      fi
+      if [ "${DO_BUILD_LINUX32}" == "y" ]
+      then
+        echo "Removing the linux-x32 build and install ${APP_LC_NAME} folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x32/build/${APP_LC_NAME}"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x32/install/${APP_LC_NAME}"
+      fi
+      if [ "${DO_BUILD_LINUX64}" == "y" ]
+      then
+        echo "Removing the linux-x64 build and install ${APP_LC_NAME} folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x64/build/${APP_LC_NAME}"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x64/install/${APP_LC_NAME}"
+      fi
+      if [ "${DO_BUILD_OSX}" == "y" ]
+      then
+        echo "Removing the darwin-x64 build and install ${APP_LC_NAME} folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/darwin-x64/build/${APP_LC_NAME}"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/darwin-x64/install/${APP_LC_NAME}"
+      fi
+    else
+      echo "Removing the ${HOST_NODE_PLATFORM}-${HOST_NODE_ARCH} build and install ${APP_LC_NAME} folders..."
+
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${HOST_NODE_PLATFORM}-${HOST_NODE_ARCH}/build/${APP_LC_NAME}"
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${HOST_NODE_PLATFORM}-${HOST_NODE_ARCH}/install/${APP_LC_NAME}"
+    fi
+  fi
+
+  if [ "${ACTION}" == "cleanlibs" ]
+  then
+    echo
+
+    if [ "${IS_NATIVE}" == "y" ]
+    then
+      echo "Removing the ${TARGET_FOLDER_NAME} build and install libs folders..."
+
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${TARGET_FOLDER_NAME}/build/libs"
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${TARGET_FOLDER_NAME}/install/libs"
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${TARGET_FOLDER_NAME}/install"/stamp-*-installed
+    elif [ ! -z "${DO_BUILD_WIN32}${DO_BUILD_WIN64}${DO_BUILD_LINUX32}${DO_BUILD_LINUX64}${DO_BUILD_OSX}" ]
+    then
+      if [ "${DO_BUILD_WIN32}" == "y" ]
+      then
+        echo "Removing the win32-x32 build and install libs folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x32/build/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x32/install/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x32/install"/stamp-*-installed
+      fi
+      if [ "${DO_BUILD_WIN64}" == "y" ]
+      then
+        echo "Removing the win32-x64 build and install libs folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x64/build/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x64/install/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x64/install"/stamp-*-installed
+      fi
+      if [ "${DO_BUILD_LINUX32}" == "y" ]
+      then
+        echo "Removing the linux-x32 build and install libs folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x32/build/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x32/install/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x32/install"/stamp-*-installed
+      fi
+      if [ "${DO_BUILD_LINUX64}" == "y" ]
+      then
+        echo "Removing the linux-x64 build and install libs folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x64/build/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x64/install/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x64/install"/stamp-*-installed
+      fi
+      if [ "${DO_BUILD_OSX}" == "y" ]
+      then
+        echo "Removing the darwin-x64 build and install libs folders..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/darwin-x64/build/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/darwin-x64/install/libs"
+        rm -rf "${HOST_WORK_FOLDER_PATH}/darwin-x64/install"/stamp-*-installed
+      fi
+    else
+      echo "Removing the ${HOST_NODE_PLATFORM}-${HOST_NODE_ARCH} build and install libs folders..."
+
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${HOST_NODE_PLATFORM}-${HOST_NODE_ARCH}/build/libs"
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${HOST_NODE_PLATFORM}-${HOST_NODE_ARCH}/install/libs"
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${HOST_NODE_PLATFORM}-${HOST_NODE_ARCH}/install"/stamp-*-installed
+    fi
+  fi
+
+  if [ "${ACTION}" == "cleanall" ]
+  then
+    echo
+    if [ "${IS_NATIVE}" == "y" ]
+    then
+      echo "Removing the ${TARGET_FOLDER_NAME} folder..."
+  
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${TARGET_FOLDER_NAME}"
+    elif [ ! -z "${DO_BUILD_WIN32}${DO_BUILD_WIN64}${DO_BUILD_LINUX32}${DO_BUILD_LINUX64}${DO_BUILD_OSX}" ]
+    then
+      if [ "${DO_BUILD_WIN32}" == "y" ]
+      then
+        echo "Removing the win32-x32 folder..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x32"
+      fi
+      if [ "${DO_BUILD_WIN64}" == "y" ]
+      then
+        echo "Removing the win32-x64 folder..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/win32-x64"
+      fi
+      if [ "${DO_BUILD_LINUX32}" == "y" ]
+      then
+        echo "Removing the linux-x32 folder..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x32"
+      fi
+      if [ "${DO_BUILD_LINUX64}" == "y" ]
+      then
+        echo "Removing the linux-x64 folder..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/linux-x64"
+      fi
+      if [ "${DO_BUILD_OSX}" == "y" ]
+      then
+        echo "Removing the darwin-x64 folder..."
+
+        rm -rf "${HOST_WORK_FOLDER_PATH}/darwin-x64"
+      fi
+    else
+      echo "Removing the ${HOST_NODE_PLATFORM}-${HOST_NODE_ARCH} folder..."
+
+      rm -rf "${HOST_WORK_FOLDER_PATH}/${HOST_NODE_PLATFORM}-${HOST_NODE_ARCH}"
+    fi
+  fi
+
+  if [ "${ACTION}" == "clean" -o "${ACTION}" == "cleanlibs" -o "${ACTION}" == "cleanall" ]
+  then
+    echo
+    echo "Clean completed. Proceed with a regular build."
+
+    exit 0
+  fi
+
+  # Not used for native buils. Otherwise the names of the docker images
+  # must be set.
+  if [ "${ACTION}" == "preload-images" ]
+  then
+    host_start_timer
+
+    host_prepare_docker
+
+    echo
+    echo "Check/Preload Docker images..."
+
+    echo
+    docker run --interactive --tty "${docker_linux64_image}" \
+      lsb_release --description --short
+
+    echo
+    docker run --interactive --tty "${docker_linux32_image}" \
+      lsb_release --description --short
+
+    echo
+    docker images
+
+    host_stop_timer
+
+    exit 0
+  fi
+}
+
+# -----------------------------------------------------------------------------
+
+function run_app()
+{
+  # Does not include the .exe extension.
+  local app_path=$1
+  shift
+
+  echo
+  echo "${app_path} $@"
+  if [ "${TARGET_PLATFORM}" == "linux" ]
+  then
+    "${app_path}" $@
+  elif [ "${TARGET_PLATFORM}" == "darwin" ]
+  then
+    "${app_path}" $@
+  elif [ "${TARGET_PLATFORM}" == "win32" ]
+  then
+    local wsl_path=$(which wsl.exe)
+    if [ ! -z "${wsl_path}" ]
+    then
+      "${app_path}.exe" $@
+    else 
+      (
+        xbb_activate
+        
+        local wine_path=$(which wine)
+        if [ ! -z "${wine_path}" ]
+        then
+          wine "${app_path}.exe" $@
+        else
+          echo "Install wine if you want to run the .exe binaries on Linux."
+        fi
+      )
+    fi
+  fi
+
+}
+
+# -----------------------------------------------------------------------------
+
+function do_patch()
+{
+  if [ ! -z "$1" ]
+  then
+    local patch_file_name="$1"
+    local patch_path="${BUILD_GIT_PATH}/patches/${patch_file_name}"
+    if [ -f "${patch_path}" ]
+    then
+      echo "Patching..."
+      patch -p0 < "${patch_path}"
+    fi
+  fi
+}
+
+function extract()
+{
+  local archive_name="$1"
+  local folder_name="$2"
+  # local patch_file_name="$3"
+  local pwd="$(pwd)"
+
+  if [ ! -d "${folder_name}" ]
+  then
+    (
+      xbb_activate
+
+      echo
+      echo "Extracting \"${archive_name}\"..."
+      if [[ "${archive_name}" == *zip ]]
+      then
+        unzip "${archive_name}" 
+      else
+        if [ ! -z "${DEBUG}" ]
+        then
+          tar -x -v -f "${archive_name}"
+        else
+          tar -x -f "${archive_name}"
+        fi
+      fi
+
+      if [ $# -gt 2 ]
+      then
+        cd "${folder_name}"
+        do_patch "$3"
+      fi
+    )
+  else
+    echo "Folder \"${pwd}/${folder_name}\" already present."
+  fi
+}
+
+
+function download()
+{
+  local url="$1"
+  local archive_name="$2"
+
+  if [ ! -f "${DOWNLOAD_FOLDER_PATH}/${archive_name}" ]
+  then
+    (
+      xbb_activate
+
+      echo
+      echo "Downloading \"${archive_name}\" from \"${url}\"..."
+      rm -f "${DOWNLOAD_FOLDER_PATH}/${archive_name}.download"
+      mkdir -p "${DOWNLOAD_FOLDER_PATH}"
+      curl -k --fail -L -o "${DOWNLOAD_FOLDER_PATH}/${archive_name}.download" "${url}"
+      mv "${DOWNLOAD_FOLDER_PATH}/${archive_name}.download" "${DOWNLOAD_FOLDER_PATH}/${archive_name}"
+    )
+  else
+    echo "File \"${DOWNLOAD_FOLDER_PATH}/${archive_name}\" already downloaded."
+  fi
+}
+
+function download_and_extract()
+{
+  local url="$1"
+  local archive_name="$2"
+  local folder_name="$3"
+
+  download "${url}" "${archive_name}"
+  if [ $# -gt 3 ]
+  then
+    extract "${DOWNLOAD_FOLDER_PATH}/${archive_name}" "${folder_name}" "$4"
+  else
+    extract "${DOWNLOAD_FOLDER_PATH}/${archive_name}" "${folder_name}"
+  fi
+}
+
+function git_clone()
+{
+  local url="$1"
+  local branch="$2"
+  local commit="$3"
+  local folder_name="$4"
+
+  (
+    echo
+    echo "Cloning \"${folder_name}\" from \"${url}\"..."
+    git clone --branch="${branch}" "${url}" "${folder_name}"
+    if [ -n "${commit}" ]
+    then
+      cd "${folder_name}"
+      git checkout -qf "${commit}"
+    fi
+  )
+}
+
+# Copy the build files to the Work area, to make them easily available. 
+function copy_build_git()
+{
+  rm -rf "${HOST_WORK_FOLDER_PATH}/build.git"
+  mkdir -p "${HOST_WORK_FOLDER_PATH}/build.git"
+  cp -r "$(dirname ${script_folder_path})"/* "${HOST_WORK_FOLDER_PATH}/build.git"
+  rm -rf "${HOST_WORK_FOLDER_PATH}/build.git/scripts/helper/.git"
+  rm -rf "${HOST_WORK_FOLDER_PATH}/build.git/scripts/helper/build-helper.sh"
+}
+
+# -----------------------------------------------------------------------------
+
+function check_binary()
+{
+  local file_path="$1"
+
+  if [ ! -x "${file_path}" ]
+  then
+    return 0
+  fi
+
+  if file --mime "${file_path}" | grep -q text
+  then
+    return 0
+  fi
+
+  check_binary_for_libraries "$1"
+}
+
+function check_binary_for_libraries()
+{
+  local file_path="$1"
+  local file_name="$(basename ${file_path})"
+  local folder_path="$(dirname ${file_path})"
+
+  (
+    xbb_activate
+
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+      echo
+      echo "${file_name}"
+      set +e
+      ${CROSS_COMPILE_PREFIX}-objdump -x "${file_path}" | grep -i 'DLL Name'
+
+      local dll_names=$(${CROSS_COMPILE_PREFIX}-objdump -x "${file_path}" \
+        | grep -i 'DLL Name' \
+        | sed -e 's/.*DLL Name: \(.*\)/\1/' \
+      )
+
+      local n
+      for n in ${dll_names}
+      do
+        if [ ! -f "${folder_path}/${n}" ] 
+        then
+          if is_win_sys_dll "${n}"
+          then
+            :
+          elif [ "${n}${HAS_WINPTHREAD}" == "libwinpthread-1.dlly" ]
+          then
+            :
+          elif [[ ${n} == python*.dll ]] && [[ ${file_name} == *-gdb-py.exe ]]
+          then
+            :
+          else
+            echo "Unexpected |${n}|"
+            exit 1
+          fi
+        fi
+      done
+      set -e
+    elif [ "${TARGET_PLATFORM}" == "darwin" ]
+    then
+      echo
+      (
+        set +e
+        cd ${folder_path}
+        otool -L "${file_name}"
+        set -e
+      )
+
+      set +e
+      local unxp
+      if [[ "${file_name}" == *\.dylib ]]
+      then
+        unxp=$(otool -L "${file_path}" | sed '1d' | sed '1d' | grep -v "${file_name}" | egrep -e "(macports|homebrew|opt|install)/")
+      else
+        unxp=$(otool -L "${file_path}" | sed '1d' | grep -v "${file_name}" | egrep -e "(macports|homebrew|opt|install)/")
+      fi
+      set -e
+
+      # echo "|${unxp}|"
+      if [ ! -z "$unxp" ]
+      then
+        echo "Unexpected |${unxp}|"
+        exit 1
+      fi
+    elif [ "${TARGET_PLATFORM}" == "linux" ]
+    then
+      echo
+      echo "${file_name}"
+      set +e
+      readelf -d "${file_path}" | egrep -i 'library|dynamic'
+
+      local so_names=$(readelf -d "${file_path}" \
+        | grep -i 'Shared library' \
+        | sed -e 's/.*Shared library: \[\(.*\)\]/\1/' \
+      )
+
+      local n
+      for n in ${so_names}
+      do
+        if [ ! -f "${folder_path}/${n}" ] 
+        then
+          if is_linux_sys_so "${n}"
+          then
+            :
+          elif [[ ${n} == libpython* ]] && [[ ${file_name} == *-gdb-py ]]
+          then
+            :
+          else
+            echo "Unexpected |${n}|"
+            exit 1
+          fi
+        fi
+      done
+      set -e
+    fi
+  )
+}
+
+function is_win_sys_dll() 
+{
+  local dll_name="$1"
+
+  # DLLs that are expected to be present on any Windows.
+  local sys_dlls=(ADVAPI32.dll \
+    KERNEL32.dll \
+    msvcrt.dll \
+    MSVCR90.dll \
+    SHELL32.dll \
+    USER32.dll \
+    WINMM.dll \
+    WINMM.DLL \
+    WS2_32.dll \
+    ole32.dll \
+    DNSAPI.dll \
+    IPHLPAPI.dll \
+    GDI32.dll \
+    IMM32.dll \
+    IMM32.DLL \
+    OLEAUT32.dll \
+    IPHLPAPI.DLL \
+    VERSION.dll \
+    SETUPAPI.dll \
+    CFGMGR32.dll \
+    PSAPI.DLL \
+    USERENV.dll \
+  )
+
+  local dll
+  for dll in "${sys_dlls[@]}"
+  do
+    if [ "${dll}" == "${dll_name}" ]
+    then
+        return 0 # True
+    fi
+  done
+  return 1 # False
+}
+
+function is_linux_sys_so() 
+{
+  local lib_name="$1"
+
+  # Do not add these two, they are present if the toolchain is installed, 
+  # but this is not guaranteed, so better copy them from the xbb toolchain.
+  # libstdc++.so.6 
+  # libgcc_s.so.1 
+
+  # Shared libraries that are expected to be present on any Linux.
+  # Note the X11 libraries.
+  local sys_libs=(\
+    librt.so.1 \
+    libm.so.6 \
+    libc.so.6 \
+    libutil.so.1 \
+    libpthread.so.0 \
+    libdl.so.2 \
+    ld-linux-x86-64.so.2 \
+    ld-linux.so.2 \
+    libX11.so.6 \
+    libXau.so.6 \
+    libxcb.so.1 \
+  )
+
+  local lib
+  for lib in "${sys_libs[@]}"
+  do
+    if [ "${lib}" == "${lib_name}" ]
+    then
+      return 0 # True
+    fi
+  done
+  return 1 # False
+}
+
+function is_darwin_sys_dylib() 
+{
+  local lib_name="$1"
+
+  if [[ ${lib_name} == /usr/lib* ]]
+  then
+    return 0
+  fi
+  if [[ ${lib_name} == /System/Library* ]]
+  then
+    return 0
+  fi
+
+  return 1
+}
+
+# -----------------------------------------------------------------------------
+
+function has_origin()
+{
+  if [ $# -lt 1 ]
+  then
+    warning "has_origin: Missing file argument"
+    exit 1
+  fi
+
+  local bin="$1"
+  if [ "${TARGET_PLATFORM}" == "linux" ]
+  then
+    local origin=$(readelf -d ${bin} | grep 'Library runpath: \[$ORIGIN\]')
+    if [ ! -z "${origin}" ]
+    then
+      return 0 # true
+    fi
+  fi
+  return 1 # false
+}
+
+# Strip binary files as in "strip binary" form, for both native
+# (linux/mac) and mingw.
+function strip_binary2() 
+{
+    set +e
+    if [ $# -lt 2 ]
+    then
+        warning "strip_binary: Missing arguments"
+        exit 1
+    fi
+
+    local strip="$1"
+    local bin="$2"
+
+    if is_elf "${bin}"
+    then
+      if has_origin "${bin}"
+      then
+        echo "${strip} ${bin} skipped (patched)"
+      else
+        echo "${strip} ${bin}"
+        # ${strip} ${bin} 2>/dev/null || true
+        "${strip}" -S "${bin}" || true
+      fi
+    else
+      echo $(file "${bin}")
+    fi
+
+    set -e
+}
+
+function strip_binary() 
+{
+  if [ $# -lt 1 ]
+  then
+    warning "strip_binary: Missing file argument"
+    exit 1
+  fi
+
+  local bin="$1"
+
+  local strip="strip"
+  if [ "${TARGET_PLATFORM}" == "win32" ]
+  then
+    strip="${CROSS_COMPILE_PREFIX}-strip"
+    if [[ "${bin}" != *.exe ]]
+    then
+      bin="${bin}.exe"
+    fi
+  fi
+
+  if has_origin "${bin}"
+  then
+    # If the file was patched, skip strip, otherwise
+    # we may damage the binary due to a bug in strip.
+    echo "${strip} ${bin} skipped (patched)"
+    return
+  fi
+
+  echo "${strip} ${bin}"
+  "${strip}" -S "${bin}" || true
+}
+
+function is_elf()
+{
+  if [ $# -lt 1 ]
+  then
+    warning "is_elf: Missing arguments"
+    exit 1
+  fi
+  local bin="$1"
+
+  # Symlinks do not match.
+  if [ -L "${bin}" ]
+  then
+    return 1
+  fi
+
+  if [ -f "${bin}" -a -x "${bin}" ]
+  then
+    # Return 0 (true) if found.
+    file ${bin} | egrep -q "( ELF )|( PE )|( PE32 )|( PE32\+ )|( Mach-O )"
+  else
+    return 1
+  fi
+}
+
+# -----------------------------------------------------------------------------
+
+# Deprecated, use copy_dependencies_recursive().
+function copy_win_gcc_dll() 
+{
+  local dll_name="$1"
+
+  # Identify the current cross gcc version, to locate the specific dll folder.
+  local cross_gcc_version=$(${CROSS_COMPILE_PREFIX}-gcc --version | grep 'gcc' | sed -e 's/.*\s\([0-9]*\)[.]\([0-9]*\)[.]\([0-9]*\).*/\1.\2.\3/')
+  local cross_gcc_version_short=$(echo ${cross_gcc_version} | sed -e 's/\([0-9]*\)[.]\([0-9]*\)[.]\([0-9]*\).*/\1.\2/')
+  local SUBLOCATION="-win32"
+
+  # First try Ubuntu specific locations,
+  # then do a long full search.
+
+  if [ -f "${XBB_FOLDER}/${CROSS_COMPILE_PREFIX}/lib/${dll_name}" ]
+  then
+    cp -v "${XBB_FOLDER}/${CROSS_COMPILE_PREFIX}/lib/${dll_name}" \
+      "${APP_PREFIX}/bin"
+  elif [ -f "/usr/lib/gcc/${CROSS_COMPILE_PREFIX}/${cross_gcc_version}/${dll_name}" ]
+  then
+    cp -v "/usr/lib/gcc/${CROSS_COMPILE_PREFIX}/${cross_gcc_version}/${dll_name}" \
+      "${APP_PREFIX}/bin"
+  elif [ -f "/usr/lib/gcc/${CROSS_COMPILE_PREFIX}/${cross_gcc_version_short}/${dll_name}" ]
+  then
+    cp -v "/usr/lib/gcc/${CROSS_COMPILE_PREFIX}/${cross_gcc_version_short}/${dll_name}" \
+      "${APP_PREFIX}/bin"
+  elif [ -f "/usr/lib/gcc/${CROSS_COMPILE_PREFIX}/${cross_gcc_version_short}${SUBLOCATION}/${dll_name}" ]
+  then
+    cp -v "/usr/lib/gcc/${CROSS_COMPILE_PREFIX}/${cross_gcc_version_short}${SUBLOCATION}/${dll_name}" \
+      "${APP_PREFIX}/bin"
+  else
+    echo "Searching /usr for ${dll_name}..."
+    SJLJ_PATH=$(find "${XBB_FOLDER}/${CROSS_COMPILE_PREFIX}" /usr \! -readable -prune -o -name ${dll_name} -print | grep ${CROSS_COMPILE_PREFIX})
+    cp -v ${SJLJ_PATH} "${APP_PREFIX}/bin"
+  fi
+}
+
+# Deprecated, use copy_dependencies_recursive().
+function copy_win_libwinpthread_dll() 
+{
+  if [ -f "${XBB_FOLDER}/${CROSS_COMPILE_PREFIX}/bin/libwinpthread-1.dll" ]
+  then
+    cp "${XBB_FOLDER}/${CROSS_COMPILE_PREFIX}/bin/libwinpthread-1.dll" \
+      "${APP_PREFIX}/bin"
+  else
+    echo "No libwinpthread-1.dll"
+    exit 1
+  fi
+}
+
+# -----------------------------------------------------------------------------
+
+function change_dylib()
+{
+  local dylib_name="$1"
+  local file_path="$2"
+
+  local dylib_path="$(otool -L "${file_path}" | grep "${dylib_name}" | sed -e 's|[[:space:]]*\(.*\)[[:space:]][(].*[)]|\1|')"
+
+  if [ -z "${dylib_path}" ]
+  then
+    echo "Dylib ${dylib_name} not used in binary ${file_path}..."
+    exit 1
+  fi
+
+  # Hack to bring Python library name in line with the other libraries.
+  if [ "${dylib_name}" == "Python" ]
+  then
+    local version="$(otool -L "${file_path}" | grep "${dylib_name}" | sed -e 's|.*current version \([0-9][0-9]*\.[0-9][0-9]*\).*|\1|')"
+    dylib_name="libpython${version}.dylib"
+    rm -rf "$(dirname ${file_path})/Python"
+  fi
+
+  chmod +w "${file_path}"
+  install_name_tool \
+    -change "${dylib_path}" \
+    "@executable_path/${dylib_name}" \
+    "${file_path}"
+
+  if [ ! -f "$(dirname ${file_path})/${dylib_name}" ]
+  then
+    install -v -c -m 644 "${dylib_path}" "$(dirname ${file_path})/${dylib_name}"
+  fi
+}
+
+# Workaround to Docker error on 32-bit image:
+# stat: Value too large for defined data type (requires -D_FILE_OFFSET_BITS=64)
+function patch_linux_elf_origin()
+{
+  local file_path="$1"
+
+  local tmp_path=$(mktemp)
+  rm -rf "${tmp_path}"
+  cp "${file_path}" "${tmp_path}"
+  patchelf --set-rpath '$ORIGIN' "${tmp_path}"
+  cp "${tmp_path}" "${file_path}"
+  rm -rf "${tmp_path}"
+}
+
+# $1 - absolute path to executable
+function prepare_app_libraries()
+{
+  local app_path="$1"
+  shift
+
+  (
+    xbb_activate
+
+    local app_folder_path="$(dirname "${app_path}")"
+
+    if [ "${WITH_STRIP}" == "y" ]
+    then
+      strip_binary "${app_path}"
+    fi
+
+    if [ "${TARGET_PLATFORM}" == "linux" ]
+    then
+      echo
+      echo "Shared libraries:"
+      echo "${app_path}"
+      readelf -d "${app_path}" | grep 'Shared library:'
+
+      echo
+      echo "Preparing libraries..."
+      patch_linux_elf_origin "${app_path}"
+
+      echo
+      copy_dependencies_recursive "${app_path}" "${app_folder_path}"
+    elif [ "${TARGET_PLATFORM}" == "darwin" ]
+    then
+      echo
+      echo "Initial dynamic libraries:"
+      otool -L "${app_path}"
+
+      echo
+      echo "Preparing libraries..."
+      copy_dependencies_recursive "${app_path}" "${app_folder_path}"
+
+      echo
+      echo "Updated dynamic libraries:"
+      otool -L "${app_path}"
+    elif [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+      echo
+      echo "Dynamic libraries:"
+      echo "${app_path}.exe"
+      ${CROSS_COMPILE_PREFIX}-objdump -x "${app_path}.exe" | grep -i 'DLL Name'
+
+      echo
+      echo "Preparing libraries..."
+      copy_dependencies_recursive "${app_path}.exe" "${app_folder_path}"
+    fi
+  )
+}
+
+function prepare_app_folder_libraries()
+{
+  local folder_path="${APP_PREFIX}"
+  if [ $# -ge 1 ]
+  then
+    folder_path="$1"
+  fi
+
+  (
+    xbb_activate
+
+    echo
+    echo "Preparing ${folder_path} libraries..."
+
+    local binaries
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+
+      binaries=$(find "${folder_path}" -name \*.exe)
+      for bin in ${binaries} 
+      do
+        echo "Preparing ${bin} libraries..."
+        copy_dependencies_recursive "${bin}" "$(dirname "${bin}")"
+      done
+
+    elif [ "${TARGET_PLATFORM}" == "darwin" ]
+    then
+
+      binaries=$(find "${folder_path}" -name \* -perm +111 -and ! -type d)
+      for bin in ${binaries} 
+      do
+        if is_elf "${bin}"
+        then
+          echo "Preparing ${bin} libraries..."
+          copy_dependencies_recursive "${bin}" "$(dirname "${bin}")"
+        fi
+      done
+
+    elif [ "${TARGET_PLATFORM}" == "linux" ]
+    then
+
+      binaries=$(find "${folder_path}" -name \* -perm /111 -and ! -type d)
+      for bin in ${binaries} 
+      do
+        if is_elf "${bin}"
+        then
+          echo "Preparing ${bin} libraries..."
+          copy_dependencies_recursive "${bin}" "$(dirname "${bin}")"
+        fi
+      done
+
+    fi
+  )
+}
+
+function copy_dependencies_recursive()
+{
+  if [ $# -ne 2 ]
+  then 
+    echo "copy_dependencies_recursive requires 2 args." 
+    exit 1
+  fi
+  local file_path="$1"
+  local dest_path="$2"
+
+  local file_name="$(basename "${file_path}")"
+  local folder_path="$(dirname "${file_path}")"
+
+  if is_elf "${file_path}"
+  then
+    if [ "${folder_path}" != "${dest_path}" ]
+    then
+      if [ ! -f "${dest_path}/${file_name}" ]
+      then
+        install -v -c -m 644 "${file_path}" "${dest_path}"
+        if [ "${WITH_STRIP}" == "y" ]
+        then
+          strip_binary "${dest_path}/${file_name}"
+        fi
+      fi
+    fi
+    if [ "${TARGET_PLATFORM}" == "linux" ]
+    then
+      patch_linux_elf_origin "${dest_path}/${file_name}"
+    fi
+  else
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+      # On Windows don't bother with links, simply copy the file.
+      local link_path="$(readlink -f "${file_path}")"
+      if [ ! -f "${dest_path}/${file_name}" ]
+      then
+        install -v -c -m 644 "${link_path}" "${dest_path}"
+        if [ "${WITH_STRIP}" == "y" ]
+        then
+          strip_binary "${dest_path}/${file_name}"
+        fi
+      fi
+    else
+      # On POSIX preserve symbolic links, since shared libraries can be
+      # referred with different names.
+      if [ -L "${file_path}" ]
+      then
+        (
+          local which_realpath="$(which "realpath")"
+          if [ ! -z "${which_realpath}" ]
+          then
+            # Resolve only one link level. If there are more, they
+            # are resolved recursively.
+            local link_path="$(readlink "${file_path}")"
+            cd "${folder_path}"
+            # Compute the absolute path of the link.
+            local real_path="$(realpath "${link_path}")"
+            copy_dependencies_recursive "${real_path}" "${dest_path}"
+
+            cd "${dest_path}"
+            if [ \( "$(basename "${link_path}")" != "${file_name}" \) -a \( ! -L "${file_name}" \) ]
+            then
+              rm -rf "${file_name}"
+              ln -sv "$(basename "${link_path}")" "${file_name}" 
+            fi
+          else
+            # Compute the final absolute path of the link, regardless
+            # how many links there are on the way.
+            local link_path="$(readlink -f "${file_path}")"
+            copy_dependencies_recursive "${link_path}" "${dest_path}"
+
+            cd "${dest_path}"
+            if [ \( "$(basename "${link_path}")" != "${file_name}" \) -a \( ! -L "${file_name}" \) ]
+            then
+              rm -rf "${file_name}"
+              ln -sv "$(basename "${link_path}")" "${file_name}" 
+            fi
+          fi
+        )
+        return
+      else
+        if [ ! -f "${dest_path}/${file_name}" ]
+        then
+          install -v -c -m 644 "${file_path}" "${dest_path}"
+          if [ "${WITH_STRIP}" == "y" ]
+          then
+            strip_binary "${dest_path}/${file_name}"
+          fi
+        fi
+        if [ "${TARGET_PLATFORM}" == "linux" ]
+        then
+          patch_linux_elf_origin "${dest_path}/${file_name}"
+        fi
+      fi
+    fi
+  fi
+
+  if [ "${TARGET_PLATFORM}" == "linux" ]
+  then
+    local libs=$(readelf -d "${dest_path}/${file_name}" \
+          | grep -i 'Shared library' \
+          | sed -e 's/.*Shared library: \[\(.*\)\]/\1/' \
+        )
+    local lib
+    for lib in ${libs}
+    do
+      if is_linux_sys_so "${lib}"
+      then
+        : # System library, no need to copy it.
+      else
+        if [ -f "${LIBS_INSTALL_FOLDER_PATH}/lib64/${lib}" ]
+        then
+          copy_dependencies_recursive "${LIBS_INSTALL_FOLDER_PATH}/lib64/${lib}" "${dest_path}"
+        elif [ -f "${LIBS_INSTALL_FOLDER_PATH}/lib/${lib}" ]
+        then
+          copy_dependencies_recursive "${LIBS_INSTALL_FOLDER_PATH}/lib/${lib}" "${dest_path}"
+        else
+          local full_path=$(${CC} -print-file-name=${lib})
+          # -print-file-name outputs back the requested name if not found.
+          if [ "${full_path}" != "${lib}" ]
+          then
+            copy_dependencies_recursive "${full_path}" "${dest_path}"
+          else
+            if [ -f "${XBB_FOLDER}/lib64/${lib}" ]
+            then
+              copy_dependencies_recursive "${XBB_FOLDER}/lib64/${lib}" "${dest_path}"
+            elif [ -f "${XBB_FOLDER}/lib/${lib}" ]
+            then
+              copy_dependencies_recursive "${XBB_FOLDER}/lib/${lib}" "${dest_path}"
+            else
+              echo "${lib} not found"
+              exit 1
+            fi
+          fi
+        fi
+      fi
+    done
+  elif [ "${TARGET_PLATFORM}" == "darwin" ]
+  then
+    echo
+    otool -L "${dest_path}/${file_name}"
+    local libs=$(otool -L "${dest_path}/${file_name}" \
+          | sed '1d' \
+          | sed -e 's|[[:space:]]*\(.*\) (.*)|\1|' \
+        )
+    local exec_prefix="@executable_path/"
+    local loader_path="@loader_path/"
+    local lib
+    for lib in ${libs}
+    do
+      if [ "${lib}" == "${exec_prefix}${file_name}" ]
+      then
+        :
+      elif [ "${lib}" == "${loader_path}${file_name}" ]
+      then
+        :
+      elif [ "$(basename $(readlink -f ${lib}))" == "${file_name}" ]
+      then
+        : # Libraries return a line with their own name.
+      else
+        if is_darwin_sys_dylib "${lib}"
+        then
+          : # System library, no need to copy it.
+        else
+          # The libs can be relative to @executable_path or absolute.
+          if [ "${lib:0:${#exec_prefix}}" == "${exec_prefix}" ]
+          then
+            : 
+          else
+            if [ -f "${lib}" ]
+            then
+              copy_dependencies_recursive "${lib}" "${dest_path}"
+            elif [ -f "${LIBS_INSTALL_FOLDER_PATH}/lib/${lib}" ]
+            then
+              copy_dependencies_recursive "${LIBS_INSTALL_FOLDER_PATH}/lib/${lib}" "${dest_path}"
+            else
+              echo "${lib} not found"
+              exit 1
+            fi
+            # Change library path to '@executable_path' inside the lib or app.
+            change_dylib "$(basename "${lib}")" "${dest_path}/${file_name}"
+          fi
+        fi
+      fi
+    done
+  elif [ "${TARGET_PLATFORM}" == "win32" ]
+  then
+    local libs=$(${CROSS_COMPILE_PREFIX}-objdump -x "${dest_path}/${file_name}" \
+          | grep -i 'DLL Name' \
+          | sed -e 's/.*DLL Name: \(.*\)/\1/' \
+        )
+    local lib
+    for lib in ${libs}
+    do
+      if is_win_sys_dll "${lib}"
+      then
+        : # System DLL, no need to copy it.
+      else
+        if [ -f "${LIBS_INSTALL_FOLDER_PATH}/bin/${lib}" ]
+        then
+          copy_dependencies_recursive "${LIBS_INSTALL_FOLDER_PATH}/bin/${lib}" "${dest_path}"
+        elif [ -f "${XBB_FOLDER}/${CROSS_COMPILE_PREFIX}/bin/${lib}" ]
+        then
+          copy_dependencies_recursive "${XBB_FOLDER}/${CROSS_COMPILE_PREFIX}/bin/${lib}" "${dest_path}"
+        else
+          local full_path=$(${CROSS_COMPILE_PREFIX}-gcc -print-file-name=${lib})
+          # -print-file-name outputs back the requested name if not found.
+          if [ "${full_path}" != "${lib}" ]
+          then
+            copy_dependencies_recursive "${full_path}" "${dest_path}"
+          else
+            echo "${lib} required by ${file_name}, not found"
+            exit 1
+          fi
+        fi
+      fi
+    done
+  fi
+}
+
+function check_binaries()
+{
+  local folder_path="${APP_PREFIX}"
+  if [ $# -ge 1 ]
+  then
+    folder_path="$1"
+  fi
+
+  (
+    xbb_activate
+    
+    echo
+    echo "Checking binaries for unwanted libraries..."
+
+    local binaries
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+
+      binaries=$(find "${folder_path}" -name \*.exe)
+      for bin in ${binaries} 
+      do
+        check_binary "${bin}"
+      done
+
+    elif [ "${TARGET_PLATFORM}" == "darwin" ]
+    then
+
+      binaries=$(find "${folder_path}" -name \* -perm +111 -and ! -type d)
+      for bin in ${binaries} 
+      do
+        if is_elf "${bin}"
+        then
+          check_binary "${bin}"
+        fi
+      done
+
+    elif [ "${TARGET_PLATFORM}" == "linux" ]
+    then
+
+      binaries=$(find "${folder_path}" -name \* -perm /111 -and ! -type d)
+      for bin in ${binaries} 
+      do
+        if is_elf "${bin}"
+        then
+          check_binary "${bin}"
+        fi
+      done
+
+    fi
+  )
+}
+
+# -----------------------------------------------------------------------------
+
+# $1 - absolute path to input folder
+# $2 - name of output folder below INSTALL_FOLDER
+function copy_license() 
+{
+  # Iterate all files in a folder and install some of them in the
+  # destination folder
+  echo
+  echo "$2"
+  (
+    cd "$1"
+    local f
+    for f in *
+    do
+      if [ -f "$f" ]
+      then
+        if [[ "$f" =~ AUTHORS.*|NEWS.*|COPYING.*|README.*|LICENSE.*|FAQ.*|DEPENDENCIES.*|THANKS.* ]]
+        then
+          install -d -m 0755 \
+            "${APP_PREFIX}/${DISTRO_INFO_NAME}/licenses/$2"
+          install -v -c -m 644 "$f" \
+            "${APP_PREFIX}/${DISTRO_INFO_NAME}/licenses/$2"
+        fi
+      fi
+    done
+  )
+  (
+    xbb_activate
+
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+      find "${APP_PREFIX}/${DISTRO_INFO_NAME}/licenses" \
+        -type f \
+        -exec unix2dos '{}' ';'
+    fi
+  )
+}
+
+function copy_build_files()
+{
+  echo
+  echo "Copying build files..."
+
+  (
+    cd "${BUILD_GIT_PATH}"
+
+    mkdir -p patches
+
+    find scripts patches -type d \
+      -exec install -d -m 0755 \
+        "${APP_PREFIX}/${DISTRO_INFO_NAME}"/'{}' ';'
+
+    find scripts patches -type f \
+      -exec install -v -c -m 644 \
+        '{}' "${APP_PREFIX}/${DISTRO_INFO_NAME}"/'{}' ';'
+
+    if [ -f CHANGELOG.txt ]
+    then
+      install -v -c -m 644 \
+          CHANGELOG.txt "${APP_PREFIX}/${DISTRO_INFO_NAME}"
+    fi
+    if [ -f CHANGELOG.md ]
+    then
+      install -v -c -m 644 \
+          CHANGELOG.md "${APP_PREFIX}/${DISTRO_INFO_NAME}"
+    fi
+  )
+}
+
+# -----------------------------------------------------------------------------
+
+# Copy one folder to another
+function copy_dir() 
+{
+  local from_path="$1"
+  local to_path="$2"
+
+  set +u
+  # rm -rf "${to_path}"
+  mkdir -p "${to_path}"
+
+  (
+    cd "${from_path}"
+    if [ "${TARGET_PLATFORM}" == "darwin" ]
+    then
+      find . -xdev -print0 | cpio -oa0 | (cd "${to_path}" && cpio -im)
+    else
+      find . -xdev -print0 | cpio -oa0V | (cd "${to_path}" && cpio -imuV)
+    fi
+  )
+
+  set -u
+}
+
+# -----------------------------------------------------------------------------
+
+function create_archive()
+{
+  (
+    xbb_activate
+
+    local distribution_file_version="${RELEASE_VERSION}"
+
+    local target_folder_name=${TARGET_FOLDER_NAME}
+
+    if [ "${HAS_NAME_ARCH}" != "y" ]
+    then
+      # Pre xPack distributions use the old file name convention.
+      distribution_file_version="${RELEASE_VERSION}-${DISTRIBUTION_FILE_DATE}"
+
+      if [ "${TARGET_PLATFORM}" == "win32" ]
+      then
+        target_folder_name="win${TARGET_BITS}"
+      elif [ "${TARGET_PLATFORM}" == "darwin" ]
+      then
+        target_folder_name="macos"
+      elif [ "${TARGET_PLATFORM}" == "linux" ]
+      then
+        target_folder_name="${CONTAINER_DISTRO_LC_NAME}${TARGET_BITS}"
+      fi
+    fi
+
+    local distribution_file="${DEPLOY_FOLDER_PATH}/${DISTRO_LC_NAME}-${APP_LC_NAME}-${distribution_file_version}-${target_folder_name}"
+
+    cd "${APP_PREFIX}"
+    find . -name '.DS_Store' -exec rm '{}' ';'
+
+    echo
+    echo "Creating distribution..."
+
+    mkdir -p "${DEPLOY_FOLDER_PATH}"
+
+    # The folder is temprarily moved into a a more elaborate hierarchy like
+    # xPacks//.
+    # After the archive is created, the folders are moved back.
+    # The atempt to transform the tar path failes, since symlinks were
+    # also transformed, which is bad.
+    if [ "${TARGET_PLATFORM}" == "win32" ]
+    then
+
+      local distribution_file="${distribution_file}.zip"
+      local archive_version_path="${INSTALL_FOLDER_PATH}/archive/${DISTRO_UC_NAME}/${APP_UC_NAME}/${distribution_file_version}"
+
+      echo
+      echo "ZIP file: \"${distribution_file}\"."
+
+      rm -rf "${INSTALL_FOLDER_PATH}/archive"
+      mkdir -p "${archive_version_path}"
+      mv "${APP_PREFIX}"/* "${archive_version_path}"
+
+      cd "${INSTALL_FOLDER_PATH}/archive"
+      zip -r9 -q "${distribution_file}" *
+
+      # Put folders back.
+      mv "${archive_version_path}"/* "${APP_PREFIX}"
+
+    else
+
+      # Unfortunately on node.js, xz & bz2 require native modules, which
+      # proved unsafe, some xz versions failed to compile on node.js v9.x,
+      # so use the good old .tgz.
+      local distribution_file="${distribution_file}.tgz"
+      local archive_version_path="${INSTALL_FOLDER_PATH}/archive/${DISTRO_TOP_FOLDER}/${APP_LC_NAME}/${distribution_file_version}"
+
+      echo "Compressed tarball: \"${distribution_file}\"."
+
+      rm -rf "${INSTALL_FOLDER_PATH}/archive"
+      mkdir -p "${archive_version_path}"
+      mv -v "${APP_PREFIX}"/* "${archive_version_path}"
+
+      # Without --hard-dereference the hard links may be turned into
+      # broken soft links on macOS.
+      cd "${INSTALL_FOLDER_PATH}"/archive
+      # -J uses xz for compression; best compression ratio.
+      # -j uses bz2 for compression; good compression ratio.
+      # -z uses gzip for compression; fair compression ratio.
+      tar -c -z -f "${distribution_file}" \
+        --owner=0 \
+        --group=0 \
+        --format=posix \
+        --hard-dereference \
+        *
+
+      # Put folders back.
+      mv -v "${archive_version_path}"/* "${APP_PREFIX}"
+
+    fi
+
+    cd "${DEPLOY_FOLDER_PATH}"
+    compute_sha shasum -a 256 "$(basename ${distribution_file})"
+  )
+}
+
+# -----------------------------------------------------------------------------
+
+# $1 = application name
+function check_application()
+{
+  local app_name=$1
+
+  if [ "${TARGET_PLATFORM}" == "linux" ]
+  then
+
+    echo
+    echo "Checking binaries for unwanted shared libraries..."
+
+    check_binary "${APP_PREFIX}/bin/${app_name}"
+
+    local libs=$(find "${APP_PREFIX}/bin" -name \*.so.\* -type f)
+    local lib
+    for lib in ${libs} 
+    do
+      check_binary_for_libraries "${lib}"
+    done
+
+  elif [ "${TARGET_PLATFORM}" == "darwin" ]
+  then
+
+    echo
+    echo "Checking binaries for unwanted dynamic libraries..."
+
+    check_binary "${APP_PREFIX}/bin/${app_name}"
+
+    local libs=$(find "${APP_PREFIX}/bin" -name \*.dylib -type f)
+    local lib
+    for lib in ${libs} 
+    do
+      check_binary_for_libraries "${lib}"
+    done
+
+  elif [ "${TARGET_PLATFORM}" == "win32" ]
+  then
+
+    echo
+    echo "Checking binaries for unwanted DLLs..."
+
+    check_binary "${APP_PREFIX}/bin/${app_name}.exe"
+
+    local libs=$(find "${APP_PREFIX}/bin" -name \*.dll -type f)
+    local lib
+    for lib in ${libs} 
+    do
+      check_binary_for_libraries "${lib}"
+    done
+
+  else
+
+    echo "Unsupported TARGET_PLATFORM ${TARGET_PLATFORM}"
+    exit 1
+
+  fi
+
+  echo
+}
+
+# -----------------------------------------------------------------------------
+
+function compute_sha() 
+{
+  # $1 shasum program
+  # $2.. options
+  # ${!#} file
+
+  file=${!#}
+  sha_file="${file}.sha"
+  "$@" >"${sha_file}"
+  echo "SHA: $(cat ${sha_file})"
+}
+
+# -----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/container-functions-source.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/container-functions-source.sh
new file mode 100644
index 0000000..fa014cd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/container-functions-source.sh
@@ -0,0 +1,160 @@
+# -----------------------------------------------------------------------------
+
+# Helper script used in the second edition of the xPack build 
+# scripts. As the name implies, it should contain only functions and 
+# should be included with 'source' by the container build scripts.
+
+# -----------------------------------------------------------------------------
+
+function start_timer() 
+{
+  CONTAINER_BEGIN_SECOND=$(date +%s)
+  echo
+  echo "Container script \"$0\" started at $(date)."
+}
+
+function stop_timer() 
+{
+  local end_second=$(date +%s)
+  echo
+  echo "Container script \"$0\" completed at $(date)."
+  local delta_seconds=$((end_second-CONTAINER_BEGIN_SECOND))
+  if [ ${delta_seconds} -lt 100 ]
+  then
+    echo "Duration: ${delta_seconds} seconds."
+  else
+    local delta_minutes=$(((delta_seconds+30)/60))
+    echo "Duration: ${delta_minutes} minutes."
+  fi
+}
+
+# -----------------------------------------------------------------------------
+
+function detect_container() 
+{
+  echo
+  uname -a
+
+  CONTAINER_DISTRO_NAME=""
+  CONTAINER_UNAME="$(uname)"
+  CONTAINER_NODE_PLATFORM=""
+  CONTAINER_NODE_ARCH=""
+
+  if [ "${CONTAINER_UNAME}" == "Darwin" ]
+  then
+
+    CONTAINER_BITS="64"
+    CONTAINER_MACHINE="x86_64"
+
+    CONTAINER_NODE_PLATFORM="darwin"
+    CONTAINER_NODE_ARCH="x64"
+
+    CONTAINER_DISTRO_NAME=Darwin
+    CONTAINER_DISTRO_LC_NAME=darwin
+
+  elif [ "${CONTAINER_UNAME}" == "Linux" ]
+  then
+    # ----- Determine distribution name and word size -----
+
+    set +e
+    CONTAINER_DISTRO_NAME=$(lsb_release -si)
+    set -e
+
+    CONTAINER_NODE_PLATFORM="linux"
+    CONTAINER_NODE_ARCH="x64"
+
+    if [ -z "${CONTAINER_DISTRO_NAME}" ]
+    then
+      echo "Please install the lsb core package and rerun."
+      CONTAINER_DISTRO_NAME="Linux"
+    fi
+
+    CONTAINER_MACHINE="$(uname -m)"
+    if [ "${CONTAINER_MACHINE}" == "x86_64" ]
+    then
+      CONTAINER_BITS="64"
+      CONTAINER_NODE_ARCH="x64"
+    elif [ "${CONTAINER_MACHINE}" == "i686" ]
+    then
+      CONTAINER_BITS="32"
+      CONTAINER_NODE_ARCH="x32"
+    else
+      echo "Unknown uname -m ${CONTAINER_MACHINE}"
+      exit 1
+    fi
+
+    CONTAINER_DISTRO_LC_NAME=$(echo ${CONTAINER_DISTRO_NAME} | tr "[:upper:]" "[:lower:]")
+
+  else
+    echo "Unknown uname ${CONTAINER_UNAME}"
+    exit 1
+  fi
+
+  echo
+  echo "Container script running on ${CONTAINER_DISTRO_NAME} ${CONTAINER_BITS}-bit."
+  echo "User $(whoami), in '${HOME}'"
+
+  HAS_WINPTHREAD=${HAS_WINPTHREAD:-""}
+  CONTAINER_ROOT_UMASK=${CONTAINER_ROOT_UMASK:-"000"}
+
+  if [ -f "/.dockerenv" -a "$(whoami)" == "root" ]
+  then
+    umask ${CONTAINER_ROOT_UMASK}
+  fi
+}
+
+
+# -----------------------------------------------------------------------------
+
+function fix_ownership()
+{
+  if [ -f "/.dockerenv" -a "${CONTAINER_RUN_AS_ROOT}" == "y" ]
+  then
+    (
+      xbb_activate
+      
+      # Set the owner of the folder and files created by the docker CentOS 
+      # container to match the user running the build script on the host. 
+      # When running on linux host, these folders and their content remain  
+      # owned by root if this is not done. However, on macOS  
+      # the owner used by Docker is the same as the macOS user, so an 
+      # ownership change is not realy necessary. 
+      echo
+      echo "Changing ownership to non-root GNU/Linux user..."
+
+      if [ -d "${BUILD_FOLDER_PATH}" ]
+      then
+        chown -R ${USER_ID}:${GROUP_ID} "${BUILD_FOLDER_PATH}"
+      fi
+      if [ -d "${INSTALL_FOLDER_PATH}" ]
+      then
+        chown -R ${USER_ID}:${GROUP_ID} "${INSTALL_FOLDER_PATH}"
+      fi
+      chown -R ${USER_ID}:${GROUP_ID} "${DEPLOY_FOLDER_PATH}"
+    )
+  fi
+}
+
+# -----------------------------------------------------------------------------
+
+# Hack to make pdftex ignore errors.
+# Used for newlib manuals, which issue some errors, but the
+# pdf file is generated anyway.
+function hack_pdfetex()
+{
+  local bin=$(which pdfetex)
+  local hacked_pdfetex="hack/pdfetex"
+
+  mkdir -p "$(dirname "${hacked_pdfetex}")"
+  rm -rf "${hacked_pdfetex}"
+  echo '#!/usr/bin/env bash' >"${hacked_pdfetex}"
+  echo 'set -x' >>"${hacked_pdfetex}"
+  echo 'set +e' >>"${hacked_pdfetex}"
+  echo "${bin}" '$@' >>"${hacked_pdfetex}"
+  echo 'set -e' >>"${hacked_pdfetex}"
+  echo 'true' >>"${hacked_pdfetex}"
+  chmod +x "${hacked_pdfetex}"
+
+  export PATH="$(pwd)/$(dirname "${hacked_pdfetex}"):${PATH}"
+}
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/host-functions-source.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/host-functions-source.sh
new file mode 100644
index 0000000..7aa20c3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/host-functions-source.sh
@@ -0,0 +1,949 @@
+# -----------------------------------------------------------------------------
+
+# Helper script used in the second edition of the xPack build 
+# scripts. As the name implies, it should contain only functions and 
+# should be included with 'source' by the host build scripts.
+
+# -----------------------------------------------------------------------------
+
+function host_get_current_date() 
+{
+  # Use the UTC date as version in the name of the distribution file.
+  DISTRIBUTION_FILE_DATE=${DISTRIBUTION_FILE_DATE:-$(date -u +%Y%m%d-%H%M)}
+
+  # Leave a track of the start date, in case of resume needed.
+  mkdir -p "${HOST_WORK_FOLDER_PATH}"
+  touch "${HOST_WORK_FOLDER_PATH}/${DISTRIBUTION_FILE_DATE}"
+  echo
+  echo "DISTRIBUTION_FILE_DATE=\"${DISTRIBUTION_FILE_DATE}\""
+}
+
+function host_start_timer() 
+{
+  HOST_BEGIN_SECOND=$(date +%s)
+  echo
+  echo "Script \"$0\" started at $(date)."
+}
+
+function host_stop_timer() 
+{
+  local host_end_second=$(date +%s)
+  echo
+  echo "Script \"$0\" completed at $(date)."
+  local delta_seconds=$((host_end_second-HOST_BEGIN_SECOND))
+  if [ ${delta_seconds} -lt 100 ]
+  then
+    echo "Duration: ${delta_seconds} seconds."
+  else
+    local delta_minutes=$(((delta_seconds+30)/60))
+    echo "Duration: ${delta_minutes} minutes."
+  fi
+}
+
+function host_notify_completed()
+{
+  if [ "${HOST_UNAME}" == "Darwin" ]
+  then
+    say "Wake up, the build completed successfully"
+  fi
+}
+
+# -----------------------------------------------------------------------------
+
+# Detect the machine the build runs on.
+function host_detect() 
+{
+  echo
+  uname -a
+
+  HOST_UNAME="$(uname)"
+  HOST_MACHINE="$(uname -m)"
+
+  HOST_DISTRO_NAME="?" # Linux distribution name (Ubuntu|CentOS|...)
+  HOST_DISTRO_LC_NAME="?" # Same, in lower case.
+
+  HOST_NODE_ARCH="?" # Node.js process.arch (x32|x64|arm|arm64)
+  HOST_NODE_PLATFORM="?" # Node.js process.platform (darwin|linux|win32)
+
+  if [ "${HOST_UNAME}" == "Darwin" ]
+  then
+    # uname -p -> i386
+    # uname -m -> x86_64
+
+    HOST_BITS="64"
+
+    HOST_DISTRO_NAME=Darwin
+    HOST_DISTRO_LC_NAME=darwin
+
+    HOST_NODE_ARCH="x64" # For now.
+    HOST_NODE_PLATFORM="darwin"
+
+  elif [ "${HOST_UNAME}" == "Linux" ]
+  then
+    # ----- Determine distribution name and word size -----
+
+    # uname -p -> x86_64|i686 (unknown in recent versions, use -m)
+    # uname -m -> x86_64|i686
+
+    if [ "${HOST_MACHINE}" == "x86_64" ]
+    then
+      HOST_BITS="64"
+      HOST_NODE_ARCH="x64"
+    elif [ "${HOST_MACHINE}" == "i686" ]
+    then
+      HOST_BITS="32"
+      HOST_NODE_ARCH="x32"
+    else
+      echo "Unknown uname -m ${HOST_MACHINE}"
+      exit 1
+    fi
+
+    HOST_NODE_PLATFORM="linux"
+
+    local lsb_path=$(which lsb_release)
+    if [ -z "${lsb_path}" ]
+    then
+      echo "Please install the lsb core package and rerun."
+      exit 1
+    fi
+
+    HOST_DISTRO_NAME=$(lsb_release -si)
+    HOST_DISTRO_LC_NAME=$(echo ${HOST_DISTRO_NAME} | tr "[:upper:]" "[:lower:]")
+
+  else
+    echo "Unsupported uname ${HOST_UNAME}"
+    exit 1
+  fi
+
+  echo
+  echo "Running on ${HOST_DISTRO_NAME} ${HOST_BITS}-bit."
+
+  USER_ID=$(id -u)
+  USER_NAME="$(id -u -n)"
+  GROUP_ID=$(id -g)
+  GROUP_NAME="$(id -g -n)"
+
+  TARGET_ARCH="${HOST_NODE_ARCH}"
+  TARGET_PLATFORM="${HOST_NODE_PLATFORM}"
+
+  IS_NATIVE=""
+  # Redefine it to "y" to run as root inside the container.
+  CONTAINER_RUN_AS_ROOT=${CONTAINER_RUN_AS_ROOT:-""}
+  HAS_WINPTHREAD=${HAS_WINPTHREAD:-""}
+}
+
+# -----------------------------------------------------------------------------
+
+function host_prepare_cache()
+{
+  # The folder that caches all downloads is in Work, for easy access.
+  HOST_CACHE_FOLDER_PATH=${HOST_CACHE_FOLDER_PATH:-"${HOME}/Work/cache"}
+  CONTAINER_CACHE_FOLDER_PATH="/Host${HOST_CACHE_FOLDER_PATH}"
+
+  mkdir -p "${HOST_CACHE_FOLDER_PATH}"
+}
+
+function host_options()
+{
+  local help_message="$1"
+  shift
+
+  ACTION=""
+
+  DO_BUILD_WIN32=""
+  DO_BUILD_WIN64=""
+  DO_BUILD_LINUX32=""
+  DO_BUILD_LINUX64=""
+  DO_BUILD_OSX=""
+  ENV_FILE=""
+
+  argc=$#
+  declare -a argv
+  argv=( $@ )
+  if [ ! -z "${DEBUG}" ]
+  then
+    echo ${argv[@]-}
+  fi
+  i=0
+
+  # Must be declared by the caller.
+  # declare -a rest
+
+
+  # Identify some of the options. The rest are collected and passed
+  # to the container script.
+  while [ $i -lt $argc ]
+  do
+
+    arg="${argv[$i]}"
+    case "${arg}" in
+
+      clean|cleanlibs|cleanall|preload-images)
+        ACTION="${arg}"
+        ;;
+
+      --win32|--windows32)
+        DO_BUILD_WIN32="y"
+        ;;
+
+      --win64|--windows64)
+        DO_BUILD_WIN64="y"
+        ;;
+
+      --linux32)
+        DO_BUILD_LINUX32="y"
+        ;;
+
+      --linux64)
+        DO_BUILD_LINUX64="y"
+        ;;
+
+      --osx)
+        DO_BUILD_OSX="y"
+        ;;
+
+      --all)
+        DO_BUILD_WIN32="y"
+        DO_BUILD_WIN64="y"
+        DO_BUILD_LINUX32="y"
+        DO_BUILD_LINUX64="y"
+        if [ "$(uname)" == "Darwin" ] 
+        then
+          DO_BUILD_OSX="y"
+        fi
+        ;;
+
+      --env-file)
+        ((++i))
+        ENV_FILE="${argv[$i]}"
+        if [ ! -f "${ENV_FILE}" ];
+        then
+          echo "The specified environment file \"${ENV_FILE}\" does not exist, exiting..."
+          exit 1
+        fi
+        ;;
+
+      # Deprecated.
+      --date)
+        ((++i))
+        DISTRIBUTION_FILE_DATE="${argv[$i]}"
+        ;;
+
+      --help)
+        echo "Usage:"
+        # Some of the options are processed by the container script.
+        echo "${help_message}"
+        echo
+        exit 1
+        ;;
+
+      *)
+        # Collect all other in an array. Append to the end.
+        # Will be later processed by the container script.
+        set +u
+        rest[${#rest[*]}]="$arg"
+        set -u
+        ;;
+
+    esac
+    ((++i))
+
+  done
+
+  DO_BUILD_ANY="${DO_BUILD_OSX}${DO_BUILD_LINUX64}${DO_BUILD_WIN64}${DO_BUILD_LINUX32}${DO_BUILD_WIN32}"
+
+  # The ${rest[@]} options will be passed to the inner script.
+  if [ ! -z "${DEBUG}" ]
+  then
+    echo ${rest[@]-}
+  fi
+}
+
+function host_options_windows()
+{
+  local help_message="$1"
+  shift
+
+  ACTION=""
+
+  DO_BUILD_WIN32=""
+  DO_BUILD_WIN64=""
+
+  # Kept, since they are used in various common functions.
+  DO_BUILD_LINUX32=""
+  DO_BUILD_LINUX64=""
+  DO_BUILD_OSX=""
+
+  ENV_FILE=""
+
+  argc=$#
+  declare -a argv
+  argv=( $@ )
+  if [ ! -z "${DEBUG}" ]
+  then
+    echo ${argv[@]-}
+  fi
+  i=0
+
+  # Must be declared by the caller.
+  # declare -a rest
+
+
+  # Identify some of the options. The rest are collected and passed
+  # to the container script.
+  while [ $i -lt $argc ]
+  do
+
+    arg="${argv[$i]}"
+    case "${arg}" in
+
+      clean|cleanlibs|cleanall|preload-images)
+        ACTION="${arg}"
+        ;;
+
+      --win32|--windows32)
+        DO_BUILD_WIN32="y"
+        ;;
+
+      --win64|--windows64)
+        DO_BUILD_WIN64="y"
+        ;;
+
+      --all)
+        DO_BUILD_WIN32="y"
+        DO_BUILD_WIN64="y"
+        ;;
+
+      --env-file)
+        ((++i))
+        ENV_FILE="${argv[$i]}"
+        if [ ! -f "${ENV_FILE}" ];
+        then
+          echo "The specified environment file \"${ENV_FILE}\" does not exist, exiting..."
+          exit 1
+        fi
+        ;;
+
+      # Deprecated.
+      --date)
+        ((++i))
+        DISTRIBUTION_FILE_DATE="${argv[$i]}"
+        ;;
+
+      --help)
+        echo "Usage:"
+        # Some of the options are processed by the container script.
+        echo "${help_message}"
+        echo
+        exit 1
+        ;;
+
+      *)
+        # Collect all other in an array. Append to the end.
+        # Will be later processed by the container script.
+        set +u
+        rest[${#rest[*]}]="$arg"
+        set -u
+        ;;
+
+    esac
+    ((++i))
+
+  done
+
+  DO_BUILD_ANY="${DO_BUILD_WIN64}${DO_BUILD_WIN32}"
+
+  # The ${rest[@]} options will be passed to the inner script.
+  if [ ! -z "${DEBUG}" ]
+  then
+    echo ${rest[@]-}
+  fi
+}
+
+function host_native_options()
+{
+  local help_message="$1"
+  shift
+
+  ACTION=""
+
+  DO_BUILD_WIN=""
+  IS_DEBUG=""
+  IS_DEVELOP=""
+  WITH_STRIP=""
+  IS_NATIVE="y"
+
+  JOBS=""
+
+  while [ $# -gt 0 ]
+  do
+    case "$1" in
+
+      clean|cleanlibs|cleanall)
+        ACTION="$1"
+        ;;
+
+      --win|--windows)
+        DO_BUILD_WIN="y"
+        ;;
+
+      --debug)
+        IS_DEBUG="y"
+        ;;
+
+      --develop)
+        IS_DEVELOP="y"
+        ;;
+
+      --jobs)
+        shift
+        JOBS=$1
+        ;;
+
+    --help)
+        echo "Build a local/native ${DISTRO_UC_NAME} ${APP_UC_NAME}."
+        echo "Usage:"
+        # Some of the options are processed by the container script.
+        echo "${help_message}"
+        echo
+        exit 0
+        ;;
+
+      *)
+        echo "Unknown action/option $1"
+        exit 1
+        ;;
+
+    esac
+    shift
+
+  done
+
+  if [ "${DO_BUILD_WIN}" == "y" ]
+  then
+    if [ "${HOST_NODE_PLATFORM}" == "linux" ]
+    then
+      TARGET_PLATFORM="win32"
+    else
+      echo "Windows cross builds are available only on GNU/Linux."
+      exit 1
+    fi
+  fi
+}
+
+function host_common()
+{
+  if [ -f "${script_folder_path}/VERSION" ]
+  then
+    # When running from the distribution folder.
+    RELEASE_VERSION=${RELEASE_VERSION:-"$(cat "${script_folder_path}"/VERSION)"}
+  fi
+  APP_BUILD=${APP_BUILD:-"build"}
+
+  echo
+  echo "Preparing release ${RELEASE_VERSION}..."
+
+  echo
+  defines_script_path="${script_folder_path}/defs-source.sh"
+  echo "Definitions source script: \"${defines_script_path}\"."
+  source "${defines_script_path}"
+
+  # -----------------------------------------------------------------------------
+
+  common_helper_functions_script_path="${script_folder_path}/helper/common-functions-source.sh"
+  echo "Common helper functions source script: \"${common_helper_functions_script_path}\"."
+  source "${common_helper_functions_script_path}"
+
+  # May override some of the helper/common definitions.
+  common_functions_script_path="${script_folder_path}/common-functions-source.sh"
+  if [ -f "${common_functions_script_path}" ]
+  then
+    echo "Common functions source script: \"${common_functions_script_path}\"."
+    source "${common_functions_script_path}"
+  fi
+
+  # ---------------------------------------------------------------------------
+
+  # The Work folder is in HOME.
+  if [ "${IS_NATIVE}" != "y" ]
+  then
+    HOST_WORK_FOLDER_PATH=${HOST_WORK_FOLDER_PATH:-"${HOME}/Work/${APP_LC_NAME}-${APP_BUILD}"}
+  else
+    HOST_WORK_FOLDER_PATH=${HOST_WORK_FOLDER_PATH:-"${HOME}/Work/${APP_LC_NAME}-dev"}
+  fi
+  CONTAINER_WORK_FOLDER_PATH="/Host${HOST_WORK_FOLDER_PATH}"
+
+  SOURCES_FOLDER_PATH="${SOURCES_FOLDER_PATH:-"${HOST_WORK_FOLDER_PATH}/sources"}"
+
+  # The names of the two Docker images used for the build.
+  # docker run --interactive --tty ilegeul/centos:6-xbb-v2.1
+  docker_linux64_image=${docker_linux64_image:-"ilegeul/centos:6-xbb-v2.2"}
+  docker_linux32_image=${docker_linux32_image:-"ilegeul/centos32:6-xbb-v2.2"}
+
+  do_actions
+
+  host_prepare_cache
+
+  CONTAINER_BUILD_SCRIPT_REL_PATH="build.git/scripts/${CONTAINER_SCRIPT_NAME}"
+  echo "Container build script: \"${HOST_WORK_FOLDER_PATH}/${CONTAINER_BUILD_SCRIPT_REL_PATH}\"."
+
+  # ---------------------------------------------------------------------------
+
+  mkdir -p "${HOST_WORK_FOLDER_PATH}"
+  mkdir -p "${SOURCES_FOLDER_PATH}"
+
+  # ---------------------------------------------------------------------------
+
+  # Set the DISTRIBUTION_FILE_DATE.
+  host_get_current_date
+
+  # ---------------------------------------------------------------------------
+
+  host_start_timer
+
+  host_prepare_prerequisites
+
+  # ---------------------------------------------------------------------------
+
+  copy_build_git
+}
+
+function host_prepare_prerequisites() 
+{
+  if [ "${HOST_UNAME}" == "Darwin" ]
+  then
+    local xbb_folder
+
+    
+    local must_install=""
+
+    if [ -d "${HOME}/opt/xbb" ]
+    then
+      xbb_folder="${HOME}/opt/xbb"
+    elif [ -d "${HOME}/opt/homebrew/xbb" ]
+    then
+      xbb_folder="${HOME}/opt/homebrew/xbb"
+    else
+      must_install="y"
+    fi
+
+
+    if [ ! -z "${xbb_folder}" ]
+    then
+
+      echo
+      echo "Checking XBB in '${xbb_folder}'..."
+      if [ ! -f "${xbb_folder}/xbb-source.sh" ]
+      then
+        must_install="y"
+      fi
+      
+    fi
+
+    if [ -n "${must_install}" ]
+    then
+
+      echo
+      echo "Please install the macOS XBB and rerun."
+      echo "https://github.com/xpack/xpack-build-box/tree/master/macos"
+      
+      exit 1
+
+    fi
+
+    if true
+    then
+
+      local tl_folder="$HOME/opt/texlive"
+
+      must_install=""
+      # Check local TeX Live.
+      if [ ! -d "${tl_folder}" ]
+      then
+        must_install="y"
+      else
+
+        PATH="${tl_folder}/bin/x86_64-darwin:${PATH}"
+        export PATH
+
+        echo
+        echo "Checking TeX Live in '${tl_folder}'..."
+        set +e
+        tex --version | grep 'TeX 3'
+        if [ $? != 0 ]
+        then
+          must_install="y"
+        fi
+        set -e
+
+      fi
+
+      if [ -n "${must_install}" ]
+      then
+
+        echo
+        echo "Please install TeX Live and rerun."
+        echo "Alternatively restart the build script using '--without-pdf'."
+        echo "https://github.com/xpack/xpack-build-box/blob/master/macos/README.md#install-tex"
+
+        exit 1
+
+      fi
+
+    fi # -z "${no_pdf}"
+  fi # "${HOST_UNAME}" == "Darwin"
+
+  host_prepare_cache
+
+  # The host script will pass to the container script
+  # various environment variables.
+  HOST_DEFINES_SCRIPT_PATH="${HOST_WORK_FOLDER_PATH}/build.git/scripts/host-defs-source.sh"
+
+  DEPLOY_FOLDER_NAME=${DEPLOY_FOLDER_NAME:-"deploy"}
+}
+
+# -----------------------------------------------------------------------------
+
+function host_prepare_docker() 
+{
+  echo
+  echo "Checking Docker..."
+
+  set +e
+  docker --version
+  if [ $? != 0 ]
+  then
+    echo "Please start docker daemon and rerun."
+    echo "If not installed, see https://docs.docker.com/installation/."
+    exit 1
+  fi
+  set -e
+}
+
+# -----------------------------------------------------------------------------
+
+function host_build_target() 
+{
+  message="$1"
+  shift
+
+  echo
+  echo "================================================================================"
+  echo "=== ${message}"
+
+  echo
+  echo $@
+
+  local container_script_path=""
+  local target_platform="${HOST_NODE_PLATFORM}"
+  local target_arch="${HOST_NODE_ARCH}"
+  local target_bits="${HOST_BITS}"
+  # If the docker image is not set, it is a native build.
+  local docker_image=""
+  local build_binaries_path=""
+  local env_file=""
+
+  while [ $# -gt 0 ]
+  do
+
+    case "$1" in
+      --script)
+        container_script_path="$2"
+        shift 2
+        ;;
+
+      --target-platform)
+        target_platform="$2"
+        shift 2
+        ;;
+
+      --target-arch)
+        target_arch="$2"
+        shift 2
+        ;;
+
+      --target-bits)
+        target_bits="$2"
+        shift 2
+        ;;
+
+      --docker-image)
+        docker_image="$2"
+        shift 2
+        ;;
+
+      --env-file)
+        env_file="$2"
+        shift 2
+        ;;
+
+      --)
+        shift
+        break
+        ;;
+
+      *)
+        echo "Unknown option $1, exit."
+        exit 1
+
+    esac
+
+  done
+
+  # The remaining $@ options will be passed to the inner script.
+  if [ -n "${DEBUG}" ]
+  then
+    echo $@
+  fi
+
+  # ---------------------------------------------------------------------------
+
+  mkdir -p "$(dirname "${HOST_DEFINES_SCRIPT_PATH}")"
+  echo "${RELEASE_VERSION}" >"$(dirname "${HOST_DEFINES_SCRIPT_PATH}")"/VERSION
+
+  rm -rf "${HOST_DEFINES_SCRIPT_PATH}"
+  touch "${HOST_DEFINES_SCRIPT_PATH}"
+
+  echo "RELEASE_VERSION=\"${RELEASE_VERSION}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+
+  echo "DISTRIBUTION_FILE_DATE=\"${DISTRIBUTION_FILE_DATE}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+
+  echo "TARGET_PLATFORM=\"${target_platform}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+  echo "TARGET_ARCH=\"${target_arch}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+  echo "TARGET_BITS=\"${target_bits}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+
+  echo "HOST_UNAME=\"${HOST_UNAME}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+
+  echo "USER_ID=\"${USER_ID}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+  echo "USER_NAME=\"${USER_NAME}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+  echo "GROUP_ID=\"${GROUP_ID}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+  echo "GROUP_NAME=\"${GROUP_NAME}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+
+  echo "CONTAINER_RUN_AS_ROOT=\"${CONTAINER_RUN_AS_ROOT}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+
+  echo "HOST_WORK_FOLDER_PATH=\"${HOST_WORK_FOLDER_PATH}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+  echo "CONTAINER_WORK_FOLDER_PATH=\"${CONTAINER_WORK_FOLDER_PATH}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+
+  echo "HOST_CACHE_FOLDER_PATH=\"${HOST_CACHE_FOLDER_PATH}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+  echo "CONTAINER_CACHE_FOLDER_PATH=\"${CONTAINER_CACHE_FOLDER_PATH}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+
+  echo "DEPLOY_FOLDER_NAME=\"${DEPLOY_FOLDER_NAME}\"" >>"${HOST_DEFINES_SCRIPT_PATH}"
+
+  if [ -z "${docker_image}" ]
+  then
+
+    host_run_native_script \
+      --script "${container_script_path}" \
+      --env-file "${env_file}" \
+      -- \
+      $@
+
+  else
+
+    host_run_docker_script \
+      --script "${container_script_path}" \
+      --docker-image "${docker_image}" \
+      --docker-container-name "${APP_LC_NAME}-${target_platform}-${target_arch}-build" \
+      --env-file "${env_file}" \
+      --host-uname "${HOST_UNAME}" \
+      -- \
+      $@    
+
+  fi
+
+  if [ -n "${DEBUG}" ]
+  then
+    echo "host_build_target ${rest[@]-} completed."
+  fi
+}
+
+# -----------------------------------------------------------------------------
+
+function host_run_native_script() 
+{
+  local local_script=""
+  local env_file=""
+
+  while [ $# -gt 0 ]
+  do
+
+    case "$1" in
+
+      --script)
+        local_script="$2"
+        shift 2
+        ;;
+
+      --env-file)
+        env_file="$2"
+        shift 2
+        ;;
+
+      --)
+        shift
+        break
+        ;;
+
+      *)
+        echo "Unknown option $1, exit."
+        exit 1
+
+    esac
+
+  done
+
+  # The remaining $@ options will be passed to the inner script.
+
+  echo
+  echo "Running script \"$(basename "${local_script}")\" natively..."
+
+  # Run the inner script in a local sub-shell, possibly with the 
+  # custom environment.
+  (
+    if [ -n "${env_file}" -a -f "${env_file}" ]
+    then
+      source "${env_file}"
+    fi
+    /bin/bash ${DEBUG} "${local_script}" $@
+  )
+}
+
+# -----------------------------------------------------------------------------
+
+function host_run_docker_script() 
+{
+  local docker_script=""
+  local docker_image=""
+  local docker_container_name=""
+  local host_uname=""
+  local env_file=""
+  local opt_env_file=
+
+  while [ $# -gt 0 ]
+  do
+
+    case "$1" in
+
+      --script)
+        docker_script="$2"
+        shift 2
+        ;;
+
+      --docker-image)
+        docker_image="$2"
+        shift 2
+        ;;
+
+      --docker-container-name)
+        docker_container_name="$2"
+        shift 2
+        ;;
+
+      --host-uname)
+        host_uname="$2"
+        shift 2
+        ;;
+
+      --env-file)
+        env_file="$2"
+        shift 2
+        ;;
+
+      --)
+        shift
+        break
+        ;;
+
+      *)
+        echo "Unknown option $1, exit."
+        exit 1
+
+    esac
+
+  done
+
+  set +e
+  # Remove a possible previously crashed container.
+  docker rm --force "${docker_container_name}" > /dev/null 2> /dev/null
+  set -e
+
+  echo
+  echo "Running script \"$(basename "${docker_script}")\" inside docker image \"${docker_image}\"..."
+
+
+  local env_file_option=""
+  # Run the inner script in a fresh Docker container.
+  if [ -n "${env_file}" -a -f "${env_file}" ]
+  then
+    env_file_option="--env-file=\"${env_file}\""
+  fi
+
+  if [ "${CONTAINER_RUN_AS_ROOT}" == "y" ]
+  then
+
+    docker run \
+      --name="${docker_container_name}" \
+      --tty \
+      --hostname "docker" \
+      --workdir="/root" \
+      --volume="${HOST_WORK_FOLDER_PATH}/:${CONTAINER_WORK_FOLDER_PATH}" \
+      --volume="${HOST_CACHE_FOLDER_PATH}/:${CONTAINER_CACHE_FOLDER_PATH}" \
+      ${env_file_option} \
+      "${docker_image}" \
+      /bin/bash ${DEBUG} "${docker_script}" $@
+
+  else
+
+    # This is a bit tricky, since it needs to do multiple actions in
+    # one go: add a new user and run the script with that user credentials,
+    # including passing the extra args (in the middle of the string).
+    #
+    # From the [bash manual](https://www.gnu.org/software/bash/manual/bash.html):
+    # ($*) Expands to the positional parameters, starting from one. 
+    # When the expansion is not within double quotes, each positional 
+    # parameter expands to a separate word. In contexts where it is 
+    # performed, those words are subject to further word splitting and 
+    # pathname expansion. When the expansion occurs within double quotes, 
+    # it expands to a single word with the value of each parameter separated 
+    # by the first character of the IFS special variable. That is, "$*" 
+    # is equivalent to "$1c$2c…", where c is the first character of the 
+    # value of the IFS variable. If IFS is unset, the parameters are 
+    # separated by spaces. If IFS is null, the parameters are joined 
+    # without intervening separators.
+    local ifs="${IFS}"
+    IFS=" "
+    local cmd_string="groupadd -g ${GROUP_ID} ${GROUP_NAME} && useradd -u ${USER_ID} -g ${GROUP_ID} ${USER_NAME} && su -c \"DEBUG=${DEBUG} bash ${docker_script} $*\" ${USER_NAME}"
+    IFS="${ifs}"
+ 
+    docker run \
+      --name="${docker_container_name}" \
+      --tty \
+      --hostname "docker" \
+      --workdir="/root" \
+      --volume="${HOST_WORK_FOLDER_PATH}/:${CONTAINER_WORK_FOLDER_PATH}" \
+      --volume="${HOST_CACHE_FOLDER_PATH}/:${CONTAINER_CACHE_FOLDER_PATH}" \
+      ${env_file_option} \
+      "${docker_image}" \
+      /bin/bash ${DEBUG} -c "${cmd_string}"
+
+  fi
+
+  # Remove the container.
+  echo "Docker container \"$(docker rm --force "${docker_container_name}")\" removed."
+}
+
+# -----------------------------------------------------------------------------
+
+function host_show_sha() {
+
+  if [ -d "${HOST_WORK_FOLDER_PATH}/${DEPLOY_FOLDER_NAME}" ]
+  then
+    echo
+    echo "SHA signatures..."
+    set +e
+    cat "${HOST_WORK_FOLDER_PATH}/${DEPLOY_FOLDER_NAME}"/*.sha
+    set -e
+  fi
+}
+
+# -----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/templates.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/templates.sh
new file mode 100644
index 0000000..2ae3deb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/helper/templates.sh
@@ -0,0 +1,77 @@
+# Templates to be used with copy/paste in the bash source files.
+
+# Build xxx library.
+
+function do_xxx() 
+{
+  # XXX_VERSION="1.1"
+
+  XXX_SRC_FOLDER_NAME="xxx-${XXX_VERSION}"
+  XXX_FOLDER_NAME="${XXX_SRC_FOLDER_NAME}"
+  local xxx_archive="${XXX_SRC_FOLDER_NAME}.tar.gz"
+  local xxx_url="http://.../${xxx_archive}"
+
+  local xxx_stamp_file_path="${INSTALL_FOLDER_PATH}/stamp-xxx-installed"
+  if [ ! -f "${xxx_stamp_file_path}" ]
+  then
+
+    cd "${WORK_FOLDER_PATH}"
+
+    download_and_extract "${xxx_url}" "${xxx_archive}" \
+      "${XXX_SRC_FOLDER_NAME}"
+
+    (
+      mkdir -p "${BUILD_FOLDER_PATH}/${XXX_FOLDER_NAME}"
+      cd "${BUILD_FOLDER_PATH}/${XXX_FOLDER_NAME}"
+
+      xbb_activate
+
+      export CFLAGS="${XBB_CFLAGS}"
+      export CPPFLAGS="${XBB_CPPFLAGS}"
+      export LDFLAGS="${XBB_LDFLAGS}"
+      
+      if [ ! -f "config.status" ]
+      then 
+
+        echo
+        echo "Running xxx configure..."
+
+        (
+          bash "${WORK_FOLDER_PATH}/${XXX_SRC_FOLDER_NAME}/configure" --help
+
+          bash "${WORK_FOLDER_PATH}/${XXX_SRC_FOLDER_NAME}/configure" \
+            --prefix="${INSTALL_FOLDER_PATH}" \
+            \
+            --build=${BUILD} \
+            --host=${HOST} \
+            --target=${TARGET} \
+            \
+            --disable-shared \
+            --enable-static
+
+        ) 2>&1 | tee "${INSTALL_FOLDER_PATH}/configure-xxx-output.txt"
+        cp "config.log" "${INSTALL_FOLDER_PATH}"/config-xxx-log.txt
+
+      fi
+
+      echo
+      echo "Running xxx make..."
+
+      (
+        # Build.
+        make -j ${JOBS}
+        if [ "${WITH_STRIP}" == "y" ]
+        then
+          make install-strip
+        else
+          make install
+        fi
+      ) 2>&1 | tee "${INSTALL_FOLDER_PATH}/make-xxx-output.txt"
+    )
+
+    touch "${xxx_stamp_file_path}"
+
+  else
+    echo "Library xxx already installed."
+  fi
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/host-defs-source.sh b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/host-defs-source.sh
new file mode 100644
index 0000000..b7a7898
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/distro-info/scripts/host-defs-source.sh
@@ -0,0 +1,16 @@
+RELEASE_VERSION="2025.10"
+DISTRIBUTION_FILE_DATE="20251102-1159"
+TARGET_PLATFORM="linux"
+TARGET_ARCH="x64"
+TARGET_BITS="64"
+HOST_UNAME="Linux"
+USER_ID="410000001"
+USER_NAME="xl_ci"
+GROUP_ID="410000001"
+GROUP_NAME="xl_ci"
+CONTAINER_RUN_AS_ROOT="y"
+HOST_WORK_FOLDER_PATH="/home/xl_ci/Work/openocd-build"
+CONTAINER_WORK_FOLDER_PATH="/Host/home/xl_ci/Work/openocd-build"
+HOST_CACHE_FOLDER_PATH="/home/xl_ci/Work/cache"
+CONTAINER_CACHE_FOLDER_PATH="/Host/home/xl_ci/Work/cache"
+DEPLOY_FOLDER_NAME="deploy"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/bitsbytes.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/bitsbytes.tcl
new file mode 100644
index 0000000..03d758e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/bitsbytes.tcl
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#----------------------------------------
+# Purpose - Create some $BIT variables
+#           Create $K and $M variables
+#          and some bit field extraction variables.
+# Create helper variables ...
+#    BIT0.. BIT31
+
+for { set x 0  } { $x < 32 } { set x [expr {$x + 1}]} {
+    set vn [format "BIT%d" $x]
+    global $vn
+    set $vn   [expr {1 << $x}]
+}
+
+# Create K bytes values
+#    __1K ... to __2048K
+for { set x 1  } { $x < 2048 } { set x [expr {$x * 2}]} {
+    set vn [format "__%dK" $x]
+    global $vn
+    set $vn   [expr {1024 * $x}]
+}
+
+# Create M bytes values
+#    __1M ... to __2048K
+for { set x 1  } { $x < 2048 } { set x [expr {$x * 2}]} {
+    set vn [format "__%dM" $x]
+    global $vn
+    set $vn [expr {1024 * 1024 * $x}]
+}
+
+proc create_mask { MSB LSB } {
+    return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}]
+}
+
+# Cut Bits $MSB to $LSB out of this value.
+# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16]
+# Result:  0x02340000
+
+proc extract_bitfield { VALUE MSB LSB } {
+    return [expr {[create_mask $MSB $LSB] & $VALUE}]
+}
+
+
+# Cut bits $MSB to $LSB out of this value
+# and shift (normalize) them down to bit 0.
+#
+# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16]
+# Result:  0x00000234
+#
+proc normalize_bitfield { VALUE MSB LSB } {
+    return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}]
+}
+
+proc show_normalize_bitfield { VALUE MSB LSB } {
+    set m [create_mask $MSB $LSB]
+    set mr [expr {$VALUE & $m}]
+    set sr [expr {$mr >> $LSB}]
+    echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
+   return $sr
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/8devices-lima.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/8devices-lima.cfg
new file mode 100644
index 0000000..a094cae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/8devices-lima.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Product page:
+# https://www.8devices.com/products/lima
+#
+# Location of JTAG pins:
+# J2 GPIO0	JTAG TCK
+# J2 GPIO1	JTAG TDI
+# J2 GPIO2	JTAG TDO
+# J2 GPIO3	JTAG TMS
+# J2 RST	directly connected to RESET_L of the SoC and can be used as
+#               JTAG SRST. Note: this pin will also reset the debug engine.
+# J1 +3,3V	Can be use as JTAG Vref
+# J1 or J2 GND	Can be used for JTAG GND
+#
+# This board is powered from mini USB connecter which is also used
+# as USB to UART converted based on FTDI FT230XQ chip
+
+source [find target/qualcomm_qca4531.cfg]
+
+proc board_init { } {
+	qca4531_ddr2_550_550_init
+}
+
+$_TARGETNAME configure -event reset-init {
+	board_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/actux3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/actux3.cfg
new file mode 100644
index 0000000..7c2ce06
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/actux3.cfg
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# board config file for AcTux3/XBA IXP42x board
+# Date:   2010-12-16
+# Author: Michael Schwingen 
+
+reset_config trst_and_srst separate
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+source [find target/ixp42x.cfg]
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init { init_actux3 }
+
+proc init_actux3 { } {
+    ##########################################################################
+    # setup expansion bus CS
+    ##########################################################################
+    mww 0xc4000000  0xbd113842  ;#CS0  : Flash, write enabled @0x50000000
+    mww 0xc4000004  0x94d10013  ;#CS1
+    mww 0xc4000008  0x95960003  ;#CS2
+    mww 0xc400000c  0x00000000  ;#CS3
+    mww 0xc4000010  0x80900003  ;#CS4
+    mww 0xc4000014  0x9d520003  ;#CS5
+    mww 0xc4000018  0x81860001  ;#CS6
+    mww 0xc400001c  0x80900003  ;#CS7
+
+    ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3
+
+    #mww 0xc4000020  0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000
+
+    ixp42x_set_bigendian
+
+    flash probe 0
+}
+
+proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } {
+    echo "writing bootloader: $FILE"
+    flash write_image erase $FILE 0x50000000 bin
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
+
+init
+reset init
+
+# setup to debug u-boot in flash
+proc uboot_debug {} {
+    gdb breakpoint_override hard
+    xscale vector_catch 0xFF
+
+    xscale vector_table low  1 0xe59ff018
+    xscale vector_table low  2 0xe59ff018
+    xscale vector_table low  3 0xe59ff018
+    xscale vector_table low  4 0xe59ff018
+    xscale vector_table low  5 0xe59ff018
+    xscale vector_table low  6 0xe59ff018
+    xscale vector_table low  7 0xe59ff018
+
+    xscale vector_table high 1 0xe59ff018
+    xscale vector_table high 2 0xe59ff018
+    xscale vector_table high 3 0xe59ff018
+    xscale vector_table high 4 0xe59ff018
+    xscale vector_table high 5 0xe59ff018
+    xscale vector_table high 6 0xe59ff018
+    xscale vector_table high 7 0xe59ff018
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/adapteva_parallella1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/adapteva_parallella1.cfg
new file mode 100644
index 0000000..d6336a8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/adapteva_parallella1.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Adapteva Parallella-I board (via Porcupine-1 adapter board)
+#
+
+reset_config srst_only
+
+source [find target/zynq_7000.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/adsp-sc584-ezbrd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/adsp-sc584-ezbrd.cfg
new file mode 100644
index 0000000..366a24a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/adsp-sc584-ezbrd.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Analog Devices ADSP-SC584-EZBRD evaluation board
+#
+# Evaluation boards by Analog Devices (and designs derived from them) use a
+# non-standard 10-pin 0.05" ARM Cortex Debug Connector.  In this bastardized
+# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST.
+#
+# As a result, a standards-compliant debug pod will force /TRST active,
+# putting the processor's debug interface into reset and preventing usage.
+#
+# A connector adapter must be employed on these boards to isolate or remap
+# /TRST so that it is only asserted when intended.
+
+# Analog expects users to use their proprietary ICE-1000 / ICE-2000 with all
+# ADSP-SC58x designs, but this is an ARM target (and subject to the
+# qualifications above) many ARM debug pods should be compatible.
+
+#source [find interface/cmsis-dap.cfg]
+source [find interface/jlink.cfg]
+
+# Analog's silicon supports SWD and JTAG, but their proprietary ICE is limited
+# to JTAG.  (This is presumably why their connector pinout was modified.)
+# SWD is chosen here, as it is more efficient and doesn't require /TRST.
+
+transport select swd
+
+# chosen speed is 'safe' choice, but your adapter may be capable of more
+adapter speed 400
+
+source [find target/adsp-sc58x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/advantech_imx8qm_dmsse20.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/advantech_imx8qm_dmsse20.cfg
new file mode 100644
index 0000000..a867b2d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/advantech_imx8qm_dmsse20.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for Advantech IMX8QM DMSSE20
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+# board has an i.MX8QM with 4 Cortex-A53 cores and 2 Cortex-A72
+set CHIPNAME imx8qm
+set CHIPCORES 6
+
+# source SoC configuration
+source [find tcl/target/imx8qm.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/alphascale_asm9260_ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/alphascale_asm9260_ek.cfg
new file mode 100644
index 0000000..33a8354
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/alphascale_asm9260_ek.cfg
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/alphascale_asm9260t.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event reset-init {
+	echo "Configure clock"
+	# Enable SRAM clk
+	mww 0x80040024 0x4
+	# Enable IRQ clk
+	mww 0x80040034 0x100
+	# Enable DMA0,1 clk
+	mww 0x80040024 0x600
+	# Make sysre syspll is enabled
+	mww 0x80040238 0x750
+	#CPU = PLLCLK/2
+	mww 0x8004017C 0x2
+	#SYSAHBCLK = CPUCLK/2
+	mww 0x80040180 0x2
+	# Set PLL freq to 480MHz
+	mww 0x80040100 480
+	# normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
+	sleep 100
+
+	# select PLL as main source
+	mww 0x80040120 0x1
+	# disable and enable main clk to update changes?
+	mww 0x80040124 0x0
+	mww 0x80040124 0x1
+
+	echo "Configure memory"
+	#enable EMI CLK
+	mww 0x80040024 0x40
+
+	# configure memory controller for internal SRAM
+	mww 0x80700000 0x1188
+	# change default emi clk delay
+	mww 0x8004034C 0xA0503
+	# make sure chip_select_register2_low has correct value (why?)
+	mww 0x8070001c 0x20000000
+	# set type to sdram and size to 32MB
+	mww 0x8070005c 0xa
+	# configure internal SDRAM timing
+	mww 0x80700004 0x024996d9
+	# configure Static Memory timing
+	mww 0x80700094 0x00542b4f
+
+	echo "Configure uart4"
+	# enable pinctrl clk
+	mww 0x80040024 0x2000000
+	# mux GPIO3_0 and GPIO3_1 to UART4
+	mww 0x80044060 0x2
+	mww 0x80044064 0x2
+	# configure UART4CLKDIV
+	mww 0x800401a8 0x1
+	# enable uart4 clk
+	mww 0x80040024 0x8000
+	# clear softrst and clkgate on uart4
+	mww 0x80010008 0xC0000000
+	# set bandrate 115200 12M
+	mww 0x80010030 0x00062070
+	# enable Rx&Tx
+	mww 0x80010024 0x301
+	# clear hw control
+	mww 0x80010028 0xc000
+}
+
+$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
+$_TARGETNAME arm7_9 fast_memory_access enable
+$_TARGETNAME arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/altera_sockit.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/altera_sockit.cfg
new file mode 100644
index 0000000..bbd87d6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/altera_sockit.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Cyclone V SocKit board
+# http://www.altera.com/b/arrow-sockit.html
+#
+# Software support page:
+# http://www.rocketboards.org/
+
+# openocd does not currently support the on-board USB Blaster II.
+# Install the JTAG header and use a USB Blaster instead.
+adapter driver usb_blaster
+
+source [find target/altera_fpgasoc.cfg]
+
+# If the USB Blaster II were supported, these settings would be needed
+#usb_blaster vid_pid 0x09fb 0x6810
+#usb_blaster device_desc "USB-Blaster II"
+
+adapter speed 100
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/am3517evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/am3517evm.cfg
new file mode 100644
index 0000000..0b19be6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/am3517evm.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# DANGER!!!! early work in progress for this PCB/target.
+#
+# The most basic operations work well enough that it is
+# useful to have this in the repository for cooperation
+# alpha testing purposes.
+#
+# TI AM3517
+#
+# http://focus.ti.com/docs/prod/folders/print/am3517.html
+# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
+# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
+
+set CHIPTYPE "am35x"
+source [find target/amdm37x.cfg]
+
+# The TI-14 JTAG connector does not have srst.  CPU reset is handled in
+# hardware.
+reset_config trst_only
+
+# "amdm37x_dbginit am35x.cpu" needs to be run after init.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ampere_emag8180.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ampere_emag8180.cfg
new file mode 100644
index 0000000..736be12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ampere_emag8180.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# OpenOCD Board Configuration for eMAG Development Platform
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+#
+
+#
+# Configure JTAG speed
+#
+
+adapter speed 2000
+
+#
+# Configure Resets
+#
+
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+source [find target/ampere_emag.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ampere_qs_mq_1s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ampere_qs_mq_1s.cfg
new file mode 100644
index 0000000..bc649ed
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ampere_qs_mq_1s.cfg
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
+# Ampere Altra Max ("Mystique") processors
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+
+# Argument Description
+#
+# JTAGFREQ
+# Set the JTAG clock frequency
+# Syntax: -c "set JTAGFREQ {freq_in_khz}"
+#
+# SYSNAME
+# Set the system name
+# If not specified, defaults to "qs"
+# Syntax: -c "set SYSNAME {qs}"
+#
+# Life-Cycle State (LCS)
+# If not specified, defaults to "Secure LCS"
+# LCS=0, "Secure LCS"
+# LCS=1, "Chip Manufacturing LCS"
+# Syntax: -c "set LCS {0}"
+# Syntax: -c "set LCS {1}"
+#
+# CORELIST_S0
+# Specify available physical cores by number
+# Example syntax to connect to physical cores 16 and 17 for S0
+# Syntax: -c "set CORELIST_S0 {16 17}"
+#
+# COREMASK_S0_LO
+# Specify available physical cores 0-63 by mask
+# Example syntax to connect to physical cores 16 and 17 for S0
+# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
+#
+# COREMASK_S0_HI
+# Specify available physical cores 64 and above by mask
+# Example syntax to connect to physical cores 94 and 95 for S0
+# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
+#
+# PHYS_IDX
+# Enable OpenOCD ARMv8 core target physical indexing
+# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
+# Syntax: -c "set PHYS_IDX {}"
+
+#
+# Configure JTAG speed
+#
+
+if { [info exists JTAGFREQ] } {
+	adapter speed $JTAGFREQ
+} else {
+	adapter speed 100
+}
+
+#
+# Set the system name
+#
+
+if { [info exists SYSNAME] } {
+	set _SYSNAME $SYSNAME
+} else {
+	set _SYSNAME qs
+}
+
+#
+# Configure Resets
+#
+
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] } {
+	set CHIPNAME ${_SYSNAME}0
+	if { [info exists CORELIST_S0] } {
+		set CORELIST $CORELIST_S0
+	} else {
+		if { [info exists COREMASK_S0_LO] } {
+			set COREMASK_LO $COREMASK_S0_LO
+		} else {
+			set COREMASK_LO 0x0
+		}
+
+		if { [info exists COREMASK_S0_HI] } {
+			set COREMASK_HI $COREMASK_S0_HI
+		} else {
+			set COREMASK_HI 0x0
+		}
+	}
+} else {
+	set CHIPNAME ${_SYSNAME}0
+	set COREMASK_LO 0x1
+	set COREMASK_HI 0x0
+}
+
+source [find target/ampere_qs_mq.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ampere_qs_mq_2s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ampere_qs_mq_2s.cfg
new file mode 100644
index 0000000..76d82d2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ampere_qs_mq_2s.cfg
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
+# Ampere Altra Max ("Mystique") processors
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+
+# Argument Description
+#
+# JTAGFREQ
+# Set the JTAG clock frequency
+# Syntax: -c "set JTAGFREQ {freq_in_khz}"
+#
+# SYSNAME
+# Set the system name
+# If not specified, defaults to "qs"
+# Syntax: -c "set SYSNAME {qs}"
+#
+# Life-Cycle State (LCS)
+# If not specified, defaults to "Secure LCS"
+# LCS=0, "Secure LCS"
+# LCS=1, "Chip Manufacturing LCS"
+# Syntax: -c "set LCS {0}"
+# Syntax: -c "set LCS {1}"
+#
+# CORELIST_S0, CORELIST_S1
+# Specify available physical cores by number
+# Example syntax to connect to physical cores 16 and 17 for S0 and S1
+# Syntax: -c "set CORELIST_S0 {16 17}"
+# Syntax: -c "set CORELIST_S1 {16 17}"
+#
+# COREMASK_S0_LO, COREMASK_S1_LO
+# Specify available physical cores 0-63 by mask
+# Example syntax to connect to physical cores 16 and 17 for S0 and S1
+# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
+# Syntax: -c "set COREMASK_S1_LO {0x0000000000030000}"
+#
+# COREMASK_S0_HI, COREMASK_S1_HI
+# Specify available physical cores 64 and above by mask
+# Example syntax to connect to physical cores 94 and 95 for S0 and S1
+# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
+# Syntax: -c "set COREMASK_S1_HI {0x00000000C0000000}"
+#
+# SPLITSMP
+# Group all ARMv8 cores per socket into individual SMP sessions
+# If not specified, group ARMv8 cores from both sockets into one SMP session
+# Syntax: -c "set SPLITSMP {}"
+#
+# PHYS_IDX
+# Enable OpenOCD ARMv8 core target physical indexing
+# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
+# Syntax: -c "set PHYS_IDX {}"
+
+#
+# Configure JTAG speed
+#
+
+if { [info exists JTAGFREQ] } {
+	adapter speed $JTAGFREQ
+} else {
+	adapter speed 100
+}
+
+#
+# Set the system name
+#
+
+if { [info exists SYSNAME] } {
+	set _SYSNAME $SYSNAME
+} else {
+	set _SYSNAME qs
+}
+
+#
+# Configure Board level SMP configuration if necessary
+#
+
+if { ![info exists SPLITSMP] } {
+	# Group dual chip into a single SMP configuration
+	set SMP_STR "target smp"
+	set CORE_INDEX_OFFSET 0
+	set DUAL_SOCKET_SMP_ENABLED ""
+}
+
+#
+# Configure Resets
+#
+
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \
+     [info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } {
+	set CHIPNAME ${_SYSNAME}1
+	if { [info exists CORELIST_S1] } {
+		set CORELIST $CORELIST_S1
+	} else {
+		if { [info exists COREMASK_S1_LO] } {
+			set COREMASK_LO $COREMASK_S1_LO
+		} else {
+			set COREMASK_LO 0x0
+		}
+
+		if { [info exists COREMASK_S1_HI] } {
+			set COREMASK_HI $COREMASK_S1_HI
+		} else {
+			set COREMASK_HI 0x0
+		}
+	}
+	source [find target/ampere_qs_mq.cfg]
+
+	if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
+		if { [info exists MQ_ENABLE] } {
+			set CORE_INDEX_OFFSET 128
+		} else {
+			set CORE_INDEX_OFFSET 80
+		}
+	}
+
+	set CHIPNAME ${_SYSNAME}0
+	if { [info exists CORELIST_S0] } {
+		set CORELIST $CORELIST_S0
+	} else {
+		if { [info exists COREMASK_S0_LO] } {
+			set COREMASK_LO $COREMASK_S0_LO
+		} else {
+			set COREMASK_LO 0x0
+		}
+
+		if { [info exists COREMASK_S0_HI] } {
+			set COREMASK_HI $COREMASK_S0_HI
+		} else {
+			set COREMASK_HI 0x0
+		}
+	}
+	source [find target/ampere_qs_mq.cfg]
+} else {
+	set CHIPNAME ${_SYSNAME}1
+	set COREMASK_LO 0x0
+	set COREMASK_HI 0x0
+	source [find target/ampere_qs_mq.cfg]
+
+	if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
+		if { [info exists MQ_ENABLE] } {
+			set CORE_INDEX_OFFSET 128
+		} else {
+			set CORE_INDEX_OFFSET 80
+		}
+	}
+
+	set CHIPNAME ${_SYSNAME}0
+	set COREMASK_LO 0x1
+	set COREMASK_HI 0x0
+	source [find target/ampere_qs_mq.cfg]
+}
+
+if { [info exists DUAL_SOCKET_SMP_ENABLED] } {
+	# For dual socket SMP configuration, evaluate the string
+	eval $SMP_STR
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/arm_evaluator7t.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/arm_evaluator7t.cfg
new file mode 100644
index 0000000..0fb8778
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/arm_evaluator7t.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This board is from ARM and has an samsung s3c45101x01 chip
+
+source [find target/samsung_s3c4510.cfg]
+
+#
+# FIXME:
+#  Add (A) sdram configuration
+#  Add (B) flash cfi programming configuration
+#
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/arm_musca_a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/arm_musca_a.cfg
new file mode 100644
index 0000000..b4880d1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/arm_musca_a.cfg
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration script for ARM Musca-A development board
+#
+# For now we do not support Musca A flash programming using OpenOCD. However, a
+# work area is configured for flash programming speed up.
+#
+# GDB considers all memory as RAM unless target supplies a memory map.
+# OpenOCD will only send memory map if flash banks are configured. Otherwise,
+# configure GDB after connection by issuing following commands:
+# (gdb) mem 0x10200000 0x109FFFFF ro
+# (gdb) mem 0x00200000 0x009FFFFF ro
+# (gdb) set mem inaccessible-by-default off
+
+# ARM Musca A board supports both JTAG and SWD transports.
+source [find target/swj-dp.tcl]
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+global _CHIPNAME
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME MUSCA_A
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x6ba00477
+}
+
+# Enable CPU1 debugging as a separate GDB target
+set _ENABLE_CPU1 1
+
+# Musca A1 has 32KB SRAM banks. Override default work-area-size to 8KB per CPU
+set WORKAREASIZE_CPU0 0x2000
+set WORKAREASIZE_CPU1 0x2000
+
+# Set SRAM bank 1 to be used for work area. Override here if needed.
+set WORKAREAADDR_CPU0 0x30008000
+set WORKAREAADDR_CPU1 0x3000A000
+
+source [find target/arm_corelink_sse200.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/arty_s7.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/arty_s7.cfg
new file mode 100644
index 0000000..eaa15ab
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/arty_s7.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Arty S7: Spartan7 25/50 FPGA Board for Makers and Hobbyists
+#
+# https://www.xilinx.com/products/boards-and-kits/1-pnziih.html
+# https://store.digilentinc.com/arty-s7-spartan-7-fpga-board-for-makers-and-hobbyists/
+
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# Xilinx Spartan7-25/50 FPGA (XC7S{25,50}-CSGA324)
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+
+adapter speed 25000
+
+# Usage:
+#
+# Load Bitstream into FPGA:
+#    openocd -f board/arty_s7.cfg -c "init;\
+#    pld load 0 bitstream.bit;\
+#    shutdown"
+#
+# Write Bitstream to Flash:
+#    openocd -f board/arty_s7.cfg -c "init;\
+#    jtagspi_init 0 bscan_spi_xc7s??.bit;\
+#    jtagspi_program bitstream.bin 0;\
+#    xc7_program xc7.tap;\
+#    shutdown"
+#
+# jtagspi flash proxies can be found at:
+# https://github.com/quartiq/bscan_spi_bitstreams
+#
+# For the Spartan 50 variant, use
+#  - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s50.bit
+# For the Spartan 25 variant, use
+#  - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s25.bit
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/asus-rt-n16.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/asus-rt-n16.cfg
new file mode 100644
index 0000000..a02bab8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/asus-rt-n16.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# http://wikidevi.com/wiki/ASUS_RT-N16
+#
+
+set partition_list {
+    CFE		{ Bootloader			0xbc000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0xbc040000 0x01fa0000 }
+    nvram	{ "Config space"		0xbdfe0000 0x00020000 }
+}
+
+source [find target/bcm4718.cfg]
+
+# External 32MB NOR Flash (Macronix MX29GL256EHTI2I-90Q)
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 1 1 $_TARGETNAME x16_as_x8
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/asus-rt-n66u.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/asus-rt-n66u.cfg
new file mode 100644
index 0000000..dda0f33
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/asus-rt-n66u.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# http://wikidevi.com/wiki/Asus_RT-N66U
+#
+
+echo "ATTENTION: you need to solder a 4.7-10k pullup resistor to pin 21 of flash IC"
+echo "to enable JTAG, see http://wl500g.info/album.php?albumid=28&attachmentid=8991 ,"
+echo "there is an unpopulated footprint near U8.\n"
+
+set partition_list {
+    CFE		{ Bootloader			0xbc000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0xbc040000 0x01fa0000 }
+    nvram	{ "Config space"		0xbdfe0000 0x00020000 }
+}
+
+source [find target/bcm4706.cfg]
+
+# External 32MB NOR Flash (Spansion S29GL256P10TF101
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91cap7a-stk-sdram.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91cap7a-stk-sdram.cfg
new file mode 100644
index 0000000..6da917a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91cap7a-stk-sdram.cfg
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
+#
+# use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME cap7
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x40700f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start {
+	# start off real slow when we're running off internal RC oscillator
+	adapter speed 32
+}
+
+proc peek32 {address} {
+	return [read_memory $address 32 1]
+}
+
+# Wait for an expression to be true with a timeout
+proc wait_state {expression} {
+	for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {
+		if {[uplevel 1 $expression] == 0} {
+			return
+		}
+	}
+	return -code 1 "Timed out"
+}
+
+# Use a global variable here to be able to tinker interactively with
+# post reset jtag frequency.
+global post_reset_khz
+# Danger!!!! Even 16MHz kinda works with this target, but
+# it needs to be as low as 2000kHz to be stable.
+set post_reset_khz 2000
+
+$_TARGETNAME configure -event reset-init {
+	echo "Configuring master clock"
+	# disable watchdog
+	mww 0xfffffd44 0xff008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# Enable main oscillator
+	mww 0xFFFFFc20  0x00000f01
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
+
+	# Set PLLA to 96MHz
+	mww 0xFFFFFc28 0x20072801
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
+
+	# Select prescaler
+	mww 0xFFFFFC30 0x00000004
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
+
+	# Select master clock to 48MHz
+	mww 0xFFFFFC30 0x00000006
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
+
+	echo "Master clock ok."
+
+	# Now that we're up and running, crank up speed!
+	global post_reset_khz ;	adapter speed $post_reset_khz
+
+	echo "Configuring the SDRAM controller..."
+
+	# Configure EBI Chip select for SDRAM
+	mww 0xFFFFEF30 0x00000102
+
+	# Enable clock on EBI PIOs
+	mww 0xFFFFFC10 0x00000004
+
+	# Configure PIO for SDRAM
+	mww 0xFFFFF470 0xFFFF0000
+	mww 0xFFFFF474 0x00000000
+	mww 0xFFFFF404 0xFFFF0000
+
+	# Configure SDRAMC CR
+	mww 0xFFFFEA08 0xA63392F9
+
+	# NOP command
+	mww 0xFFFFEA00 0x1
+	mww 0x20000000 0
+
+	# Precharge All Banks command
+	mww 0xFFFFEA00 0x2
+	mww 0x20000000 0
+
+	# Set 1st CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000010 0x00000001
+
+	# Set 2nd CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000020 0x00000002
+
+	# Set 3rd CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000030 0x00000003
+
+	# Set 4th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000040 0x00000004
+
+	# Set 5th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000050 0x00000005
+
+	# Set 6th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000060 0x00000006
+
+	# Set 7th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000070 0x00000007
+
+	# Set 8th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000080 0x00000008
+
+	# Set LMR operation
+	mww 0xFFFFEA00 0x00000003
+
+	# Perform LMR burst=1, lat=2
+	mww 0x20000020 0xCAFEDEDE
+
+	# Set Refresh Timer
+	mww 0xFFFFEA04 0x00000203
+
+	# Set Normal mode
+	mww 0xFFFFEA00 0x00000000
+	mww 0x20000000 0x00000000
+
+	#remap internal memory at address 0x0
+	mww 0xffffef00 0x3
+
+	echo "SDRAM configuration ok."
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+#set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91eb40a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91eb40a.cfg
new file mode 100644
index 0000000..60c6c6e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91eb40a.cfg
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#Script for AT91EB40a
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME at91eb40a
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+#flash driver
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x01000000 0x200000 2 2 $_TARGETNAME
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+$_TARGETNAME configure -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+	echo "Running reset init script for AT91EB40A"
+	# Reset script for AT91EB40a
+	reg cpsr 0x000000D3
+	mww 0xFFE00020 0x1
+	mww 0xFFE00024 0x00000000
+	mww 0xFFE00000 0x01002539
+	mww 0xFFFFF124 0xFFFFFFFF
+	mww 0xffff0010 0x100
+	mww 0xffff0034 0x100
+}
+
+# This target is pretty snappy...
+adapter speed 16000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91rm9200-dk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91rm9200-dk.cfg
new file mode 100644
index 0000000..3751103
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91rm9200-dk.cfg
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is for the "at91rm9200-DK" (not the EK) eval board.
+#
+# The two are probably very simular.... I have DK...
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
+
+#flash bank       
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME
+
+
+proc at91rm9200_dk_init { } {
+    # Try to run at 1khz... Yea, that slow!
+    # Chip is really running @ 32khz
+    adapter speed 8
+
+    mww 0xfffffc64 0xffffffff
+    ##  disable all clocks but system clock
+    mww 0xfffffc04 0xfffffffe
+    ##  disable all clocks to pioa and piob
+    mww 0xfffffc14 0xffffffc3
+    ##  master clock = slow cpu = slow
+    ##  (means the CPU is running at 32khz!)
+    mww 0xfffffc30 0
+    ##  main osc enable
+    mww 0xfffffc20 0x0000ff01
+    ##  program pllA
+    mww 0xfffffc28 0x20263e04
+    ##  program pllB
+    mww 0xfffffc2c 0x10483e0e
+    ##  let pll settle... sleep 100msec
+    sleep 100
+    ##  switch to fast clock
+    mww 0xfffffc30 0x202
+    ## Sleep some - (go read)
+    sleep 100
+
+    #========================================
+    # CPU now runs at 180mhz
+    # SYS runs at 60mhz.
+    adapter speed 40000
+    #========================================
+
+
+    ##  set memc for all memories
+    mww 0xffffff60 0x02
+    ##  program smc controller
+    mww 0xffffff70 0x3284
+    ##  init sdram
+    mww 0xffffff98 0x7fffffd0
+    ##  all banks precharge
+    mww 0xffffff80 0x02
+    ##  touch sdram chip to make it work
+    mww 0x20000000 0
+    ##  sdram controller mode register
+    mww 0xffffff90 0x04
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    ##  sdram controller mode register
+    ##  Refresh, etc....
+    mww 0xffffff90 0x03
+    mww 0x20000080 0
+    mww 0xffffff94 0x1f4
+    mww 0x20000080 0
+    mww 0xffffff90 0x10
+    mww 0x20000000 0
+    mww 0xffffff00 0x01
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91rm9200-ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91rm9200-ek.cfg
new file mode 100644
index 0000000..e38914e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91rm9200-ek.cfg
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD 
+#
+# under GPLv2 Only
+#
+# This is for the "at91rm9200-ek" eval board.
+#
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
+
+## flash bank       
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+
+# The chip may run @ 32khz, so set a really low JTAG speed
+adapter speed 8
+
+proc at91rm9200_ek_init { } {
+	# Try to run at 1khz... Yea, that slow!
+	# Chip is really running @ 32khz
+	adapter speed 8
+
+	mww 0xfffffc64 0xffffffff
+	## disable all clocks but system clock
+	mww 0xfffffc04 0xfffffffe
+	## disable all clocks to pioa and piob
+	mww 0xfffffc14 0xffffffc3
+	## master clock = slow cpu = slow
+	## (means the CPU is running at 32khz!)
+	mww 0xfffffc30 0
+	## main osc enable
+	mww 0xfffffc20 0x0000ff01
+	## MC_PUP
+	mww 0xFFFFFF50 0x00000000
+	## MC_PUER: Memory controller protection unit disable
+	mww 0xFFFFFF54 0x00000000
+	## EBI_CFGR
+	mww 0xFFFFFF64 0x00000000
+	## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
+	mww 0xFFFFFF70 0x00003284
+
+	## Init Clocks
+	## CKGR_PLLAR
+	mww 0xFFFFFC28 0x2000BF05
+	## PLLAR: 179,712000 MHz for PCK
+	mww 0xFFFFFC28 0x20263E04
+	sleep 100
+	## PMC_MCKR
+	mww 0xFFFFFC30 0x00000100
+	sleep 100
+	## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
+	mww 0xFFFFFC30 0x00000202
+	sleep 100
+
+	#========================================
+	# CPU now runs at 180mhz
+	# SYS runs at 60mhz.
+	adapter speed 40000
+	#========================================
+
+	## Init SDRAM
+	## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
+	mww 0xFFFFF870 0xFFFF0000
+	## PIOC_BSR:
+	mww 0xFFFFF874 0x00000000
+	## PIOC_PDR:
+	mww 0xFFFFF804 0xFFFF0000
+	## EBI_CSA : CS1=SDRAM
+	mww 0xFFFFFF60 0x00000002
+	## EBI_CFGR:
+	mww 0xFFFFFF64 0x00000000
+	## SDRC_CR :
+	mww 0xFFFFFF98 0x2188c155
+	## SDRC_MR : Precharge All
+	mww 0xFFFFFF90 0x00000002
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Refresh
+	mww 0xFFFFFF90 0x00000004
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Load Mode Register
+	mww 0xFFFFFF90 0x00000003
+	## access SDRAM
+	mww 0x20000080 0x00000000
+	## SDRC_TR : Write refresh rate
+	mww 0xFFFFFF94 0x000002E0
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Normal Mode
+	mww 0xFFFFFF90 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91sam9261-ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91sam9261-ek.cfg
new file mode 100644
index 0000000..c2d97b0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91sam9261-ek.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Atmel AT91SAM9261-EK eval board
+################################################################################
+
+source [find mem_helper.tcl]
+source [find target/at91sam9261.cfg]
+uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9261.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+scan_chain
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }
+$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
+
+proc at91sam9261ek_reset_init { } {
+
+	;# for ppla at 199 Mhz
+	set config(master_pll_div)	15
+	set config(master_pll_mul)	162
+
+	;# for ppla at 239 Mhz
+	;# set master_pll_div	1
+	;# set master_pll_mul	13
+
+	set val	$::AT91_WDT_WDV							;# Counter Value
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]		;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]			;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
+
+	set config(wdt_mr_val) $val
+
+	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
+	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBICSA
+	set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
+
+	;# SDRAMC_CR - Configuration register
+	set val $::AT91_SDRAMC_NC_9
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (2 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (3 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (8 << 28)}]		;# Exit Self Refresh to Active Delay
+
+	set config(sdram_cr_val) $val
+
+	set config(sdram_tr_val) 0x13c
+
+	set config(sdram_base) $::AT91_CHIPSELECT_1
+	at91sam9_reset_init $config
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91sam9263-ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91sam9263-ek.cfg
new file mode 100644
index 0000000..328a792
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91sam9263-ek.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Atmel AT91SAM9263-EK eval board
+################################################################################
+
+source [find mem_helper.tcl]
+source [find target/at91sam9263.cfg]
+uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9263.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+scan_chain
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }
+$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
+
+proc at91sam9263ek_reset_init { } {
+
+	set config(master_pll_div)	14
+	set config(master_pll_mul)	171
+
+	set val	$::AT91_WDT_WDV							;# Counter Value
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]		;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]			;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
+
+	set config(wdt_mr_val) $val
+
+	set config(sdram_piod) 1
+	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
+	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBI0CSA
+
+	set val	$::AT91_MATRIX_EBI0_DBPUC
+	set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}]
+	set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}]
+	set config(matrix_ebicsa_val) $val
+
+	;# SDRAMC_CR - Configuration register
+	set val $::AT91_SDRAMC_NC_9
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (1 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (2 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (1 << 28)}]		;# Exit Self Refresh to Active Delay
+
+	set config(sdram_cr_val) $val
+
+	set config(sdram_tr_val) 0x13c
+
+	set config(sdram_base) $::AT91_CHIPSELECT_1
+	at91sam9_reset_init $config
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91sam9g20-ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91sam9g20-ek.cfg
new file mode 100644
index 0000000..22a38a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/at91sam9g20-ek.cfg
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#################################################################################################
+#												#
+# Author: Gary Carlson (gcarlson@carlson-minot.com)						#
+# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8.	#
+#												#
+#################################################################################################
+
+source [find target/at91sam9g20.cfg]
+
+set _FLASHTYPE nandflash_cs3
+
+# Set reset type.  Note that the AT91SAM9G20-EK board has the trst signal disconnected.  Therefore
+# the reset needs to be configured for "srst_only".  If for some reason, a zero-ohm jumper is
+# added to the board to connect the trst signal, then this parameter may need to be changed.
+
+reset_config srst_only
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
+# AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
+# some powerful features, we want to have a special function that handles "reset init".  To do this we declare
+# an event handler where these special activities can take place.
+
+scan_chain
+$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
+$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
+
+# NandFlash configuration and definition
+
+nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800
+at91sam9 cle 0 22
+at91sam9 ale 0 21
+at91sam9 rdy_busy 0 0xfffff800 13
+at91sam9 ce 0 0xfffff800 14
+
+proc read_register {register} {
+	return [read_memory $register 32 1]
+}
+
+proc at91sam9g20_reset_start { } {
+
+	# Make sure that the jtag is running slow, since there are a number of different ways the board
+	# can be configured coming into this state that can cause communication problems with the jtag
+	# adapter.  Also since this call can be made following a "reset init" where fast memory accesses
+	# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
+	# jtag speed without causing GDB keep alive problem.
+
+	arm7_9 fast_memory_access disable
+	adapter speed 2                 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+	halt                            ;# Make sure processor is halted, or error will result in following steps.
+	wait_halt 10000
+	mww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.
+}
+
+proc at91sam9g20_reset_init { } {
+
+	# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
+	# a number of steps that must be carefully performed.  The process outline below follows the
+	# recommended procedure outlined in the AT91SAM9G20 technical manual.
+	#
+	# Several key and very important things to keep in mind:
+	# The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This
+	# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
+	# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+	mww 0xfffffd44 0x00008000	;# WDT_MR : disable watchdog.
+
+	# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
+	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
+
+	mww 0xfffffc20 0x00004001
+	while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
+
+	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
+	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+	mww 0xfffffc28 0x202a3f01
+	while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
+
+	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00000101
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Now change PMC_MCKR register to select PLLA.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00001302
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Processor and master clocks are now operating and stable at maximum frequency possible:
+	#	-> MCLK = 132.096 MHz
+	#	-> PCLK = 396.288 MHz
+
+	# Switch over to adaptive clocking.
+
+	adapter speed 0
+
+	# Enable faster DCC downloads and memory accesses.
+
+	arm7_9 dcc_downloads enable
+	arm7_9 fast_memory_access enable
+
+	# To be able to use external SDRAM, several peripheral configuration registers must
+	# be modified.  The first change is made to PIO_ASR to select peripheral functions
+	# for D15 through D31.  The second change is made to the PIO_PDR register to disable
+	# this for D15 through D31.
+
+	mww 0xfffff870 0xffff0000
+	mww 0xfffff804 0xffff0000
+
+	# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+	# using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
+	# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+	mww 0xffffef1c 0x000100a
+
+	# The AT91SAM9G20-EK evaluation board has built-in NandFlash.  The exact physical timing characteristics
+	# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+	# a number of registers.  The first step involves setting up the general I/O pins on the processor
+	# to be able to interface and support the external memory.
+
+	mww 0xfffffc10 0x00000010	;# PMC_PCER : enable PIOC clock
+	mww 0xfffff800 0x00006000	;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+	mww 0xfffff810 0x00004000	;# PIOC_OER : enable output on 14
+	mww 0xfffff814 0x00002000	;# PIOC_ODR : disable output on 13
+    	mww 0xfffff830 0x00004000	;# PIOC_SODR : set 14 to disable NAND
+
+	# The exact physical timing characteristics for the memory type used on the current board
+	# (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
+	# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
+	# is a little tedious to do here.  If you have questions about how to do this, Atmel has
+	# a decent application note #6255B that covers this process.
+
+	mww 0xffffec30 0x00020002	;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
+	mww 0xffffec34 0x04040404	;# SMC_PULSE3 : 4 clock cycle pulse for all signals
+	mww 0xffffec38 0x00070006	;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
+	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+
+	mww 0xffffe800 0x00000001	;# ECC_CR : reset the ECC parity registers
+	mww 0xffffe804 0x00000002	;# ECC_MR : page size is 2112 words (word is 8 bits)
+
+	# Identify NandFlash bank 0.
+
+	nand probe nandflash_cs3
+
+	# The AT91SAM9G20-EK evaluation board has built-in serial data flash also.
+
+	# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
+	# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference
+	# for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
+	# into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock
+	# of 132.096 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:
+	#
+	#	CAS latency = 3 cycles
+	#	TXSR = 10 cycles
+	#	TRAS = 6 cycles
+	#	TRCD = 3 cycles
+	#	TRP = 3 cycles
+	#	TRC = 9 cycles
+	#	TWR = 2 cycles
+	#	9 column, 13 row, 4 banks
+	#	refresh equal to or less then 7.8 us for commercial/industrial rated devices
+	#
+	#	Thus SDRAM_CR = 0xa6339279
+
+	mww 0xffffea08 0xa6339279
+
+	# Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
+	# the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x00000001
+	mww 0x20000000 0
+
+	# Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
+	# value into the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x00000002
+	mww 0x20000000 0
+
+	# Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing
+	# zero values eight times into the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+
+	# Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
+	# the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x3
+	mww 0x20000000 0
+
+	# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting
+	# memory location for the SDRAM.
+
+	mww 0xffffea00 0x0
+	mww 0x20000000 0
+
+	# Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
+
+	mww 0xffffea04 0x0000039c
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_at91sam7s-ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_at91sam7s-ek.cfg
new file mode 100644
index 0000000..9cf85df
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_at91sam7s-ek.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Atmel AT91SAM7S-EK
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
+
+set CHIPNAME at91sam7s256
+
+source [find target/at91sam7sx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_at91sam9260-ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_at91sam9260-ek.cfg
new file mode 100644
index 0000000..56fce3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_at91sam9260-ek.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Atmel AT91SAM9260-EK eval board
+#
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9260.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
+        sleep 10                          ;# wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	mww 0xfffff870 0xffff0000         ;# PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         ;# PIO_PDR  : Disable PIO function for D15..D31
+
+        mww 0xffffef1c 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_at91sam9rl-ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_at91sam9rl-ek.cfg
new file mode 100644
index 0000000..cc3d974
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_at91sam9rl-ek.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+#
+# Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
+#
+# Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9rl.cfg]
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc28 0x2031bf03         ;# CKGR_PLLR: Set PLL Register for 200 MHz
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLL is selected (100 MHz)
+        sleep 10                          ;# wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	mww 0xfffff670 0xffff0000         ;# PIO_ASR  : Select peripheral function for D16..D31 (PIOB)
+        mww 0xfffff604 0xffff0000         ;# PIO_PDR  : Disable PIO function for D16..D31 (PIOB)
+
+        mww 0xffffef20 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3n_ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3n_ek.cfg
new file mode 100644
index 0000000..af2fd95
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3n_ek.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration for Atmel's SAM3N-EK
+#
+
+reset_config srst_only
+
+set CHIPNAME at91sam3n4c
+
+adapter speed 32
+
+source [find target/at91sam3nXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3s_ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3s_ek.cfg
new file mode 100644
index 0000000..136e31d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3s_ek.cfg
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam3sXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3u_ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3u_ek.cfg
new file mode 100644
index 0000000..c308003
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3u_ek.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam3u4e.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3x_ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3x_ek.cfg
new file mode 100644
index 0000000..c321cfb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam3x_ek.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam3ax_8x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4e_ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4e_ek.cfg
new file mode 100644
index 0000000..61191a9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4e_ek.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an SAM4E-EK board with a single SAM4E16 chip.
+# http://www.atmel.com/tools/sam4e-ek.aspx
+
+# chip name
+set CHIPNAME SAM4E16E
+
+source [find target/at91sam4sXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4l8_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4l8_xplained_pro.cfg
new file mode 100644
index 0000000..d0c4516
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4l8_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAM4L8 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAM4L8-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAM4LC8CA
+
+source [find target/at91sam4lXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4s_ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4s_ek.cfg
new file mode 100644
index 0000000..7e4bb83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4s_ek.cfg
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam4sXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4s_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4s_xplained_pro.cfg
new file mode 100644
index 0000000..92191c7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_sam4s_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAM4S Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAM4S-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAM4SD32C
+
+source [find target/at91sam4sd32x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samc20_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samc20_xplained_pro.cfg
new file mode 100644
index 0000000..3ac89a5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samc20_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMC20 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samc20j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samc21_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samc21_xplained_pro.cfg
new file mode 100644
index 0000000..5ad6ccf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samc21_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMC21 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMC21-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samc21j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd10_xplained_mini.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd10_xplained_mini.cfg
new file mode 100644
index 0000000..f9f1d24
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd10_xplained_mini.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMD10 Xplained mini evaluation kit.
+# http://www.atmel.com/tools/atsamd10-xmini.aspx
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd10d14
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd11_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd11_xplained_pro.cfg
new file mode 100644
index 0000000..724c921
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd11_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMD11 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd11d14
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd20_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd20_xplained_pro.cfg
new file mode 100644
index 0000000..1492958
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd20_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMD20 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMD20-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd20j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd21_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd21_xplained_pro.cfg
new file mode 100644
index 0000000..f55b6b9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samd21_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMD21 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd21j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_same70_xplained.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_same70_xplained.cfg
new file mode 100644
index 0000000..f20e2a3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_same70_xplained.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAME70 Xplained evaluation kit.
+# http://www.atmel.com/tools/ATSAME70-XPLD.aspx
+#
+# Connect using the EDBG chip on the dev kit over USB
+source [find interface/cmsis-dap.cfg]
+
+set CHIPNAME atsame70q21
+
+source [find target/atsamv.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samg53_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samg53_xplained_pro.cfg
new file mode 100644
index 0000000..060750c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samg53_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMG53 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMG53-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAMG53N19
+
+source [find target/at91samg5x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samg55_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samg55_xplained_pro.cfg
new file mode 100644
index 0000000..147dc73
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samg55_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMG55 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMG55-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAMG55J19
+
+source [find target/at91samg5x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_saml21_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_saml21_xplained_pro.cfg
new file mode 100644
index 0000000..8e62eb2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_saml21_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAML21 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91saml21j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samr21_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samr21_xplained_pro.cfg
new file mode 100644
index 0000000..cd6d28e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samr21_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMR21 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samr21g18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samv71_xplained_ultra.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samv71_xplained_ultra.cfg
new file mode 100644
index 0000000..9368f61
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/atmel_samv71_xplained_ultra.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMV71 Xplained Ultra evaluation kit.
+# http://www.atmel.com/tools/ATSAMV71-XULT.aspx
+#
+# To connect using the EDBG chip on the dev kit over USB, you will
+# first need to source [find interface/cmsis-dap.cfg]
+# however, since this board also has a SWD+ETM connector, we don't
+# automatically source that file here.
+
+set CHIPNAME samv71
+
+source [find target/atsamv.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/avnet_ultrazed-eg.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/avnet_ultrazed-eg.cfg
new file mode 100644
index 0000000..6701fd1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/avnet_ultrazed-eg.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# AVNET UltraZED EG StarterKit
+# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2
+#
+source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
+# jtag transport only
+transport select jtag
+# reset lines are not wired
+reset_config none
+
+# slow default clock
+adapter speed 1000
+
+set CHIPNAME uscale
+
+source [find target/xilinx_zynqmp.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/balloon3-cpu.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/balloon3-cpu.cfg
new file mode 100644
index 0000000..3ee840b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/balloon3-cpu.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
+# The board has separate JTAG ports for cpu and CPLD/FPGA devices
+# Chaining is done on IO interfaces if desired.
+
+source [find target/pxa270.cfg]
+
+# The board supports separate reset lines
+# Override this in the interface config for parallel dongles
+reset_config trst_and_srst separate
+
+# flash bank       
+# 29LV650 64Mbit Flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bcm28155_ap.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bcm28155_ap.cfg
new file mode 100644
index 0000000..99da948
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bcm28155_ap.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BCM28155_AP
+
+adapter speed 20000
+
+set CHIPNAME bcm28155
+source [find target/bcm281xx.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bemicro_cycloneiii.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bemicro_cycloneiii.cfg
new file mode 100644
index 0000000..3c92b50
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bemicro_cycloneiii.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BeMicro Cyclone III
+
+
+adapter driver ftdi
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+ftdi vid_pid 0x0403 0xa4a0
+reset_config none
+transport select jtag
+
+adapter speed 10000
+
+source [find fpga/altera-cycloneiii.cfg]
+
+#quartus_cpf --option=bitstream_compression=off -c output_files\cycloneiii_blinker.sof cycloneiii_blinker.rbf
+
+#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load cycloneiii.pld cycloneiii_blinker.rbf"
+# "ipdbg create-hub cycloneiii.ipdbghub -tap cycloneiii.tap -ir 0x00e"
+# "cycloneiii.ipdbghub ipdbg start -tool 0 -port 5555"
+
+
+set JTAGSPI_CHAIN_ID cycloneiii.pld
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bluefield.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bluefield.cfg
new file mode 100644
index 0000000..e96a74e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bluefield.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration for BlueField SoC.
+#
+
+source [find interface/rshim.cfg]
+source [find target/bluefield.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bt-homehubv1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bt-homehubv1.cfg
new file mode 100644
index 0000000..bbb6fa4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/bt-homehubv1.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# BT HomeHub v1
+#
+
+set partition_list {
+    CFE       { Bootloader              0xbe400000 0x00020000 }
+    firmware  { "Kernel+rootfs"         0xbe420000 0x007d0000 }
+    fisdir    { "FIS Directory"         0xbebf0000 0x0000f000 }
+    nvram     { "Config space"          0xbebff000 0x00001000 }
+}
+
+source [find target/bcm6348.cfg]
+
+set _FLASHNAME $_CHIPNAME.norflash
+flash bank $_FLASHNAME cfi 0xbe400000 0x00800000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/calao-usb-a9260.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/calao-usb-a9260.cfg
new file mode 100644
index 0000000..52fede0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/calao-usb-a9260.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# CALAO Systems USB-A9260 (C01 and C02)
+
+adapter driver ftdi
+ftdi device_desc "USB-A9260"
+ftdi vid_pid 0x0403 0x6001 0x0403 0x6010
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+
+transport select jtag
+
+source [find target/at91sam9260.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/calao-usb-a9g20-c01.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/calao-usb-a9g20-c01.cfg
new file mode 100644
index 0000000..d201786
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/calao-usb-a9g20-c01.cfg
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# CALAO Systems USB-A9G20-C01
+# Authors: Gregory Hermant, Jean-Christophe PLAGNIOL-VILLARD, Wolfram Sang
+
+adapter driver ftdi
+ftdi device_desc "USB-A9G20"
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+
+transport select jtag
+
+source [find target/at91sam9g20.cfg]
+source [find mem_helper.tcl]
+
+proc at91sam9g20_reset_start { } {
+
+        # Make sure that the jtag is running slow, since there are a number of different ways the board
+        # can be configured coming into this state that can cause communication problems with the jtag
+        # adapter.  Also since this call can be made following a "reset init" where fast memory accesses
+        # are enabled, Need to temporarily shut this down so that the RSTC_MR register can be written at slower
+        # jtag speed without causing GDB keep alive problem.
+
+        arm7_9 fast_memory_access disable
+        adapter speed 2                   ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+        halt 0                            ;# Make sure processor is halted, or error will result in following steps.
+        wait_halt 10000
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+proc at91sam9g20_reset_init { } {
+
+        # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
+        # a number of steps that must be carefully performed.  The process outline below follows the
+        # recommended procedure outlined in the AT91SAM9G20 technical manual.
+        #
+        # Several key and very important things to keep in mind:
+        # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This
+        # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
+        # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+        mww 0xfffffd44 0x00008000      ;# WDT_MR : disable watchdog.
+
+        # Set oscillator bypass bit (12.00 MHz external oscillator) in CKGR_MOR register.
+
+        mww 0xfffffc20 0x00000002
+
+        # Set PLLA Register for 798.000 MHz (divider: bypass, multiplier: 132).
+        # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+        mww 0xfffffc28 0x20843F02
+        while { [expr { [mrw 0xfffffc68] & 0x02 } ] != 2 } { sleep 1 }
+
+        # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+        # Wait for MCKRDY signal from PMC_SR to assert.
+
+        mww 0xfffffc30 0x00001300
+        while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
+
+        # Now change PMC_MCKR register to select PLLA.
+        # Wait for MCKRDY signal from PMC_SR to assert.
+
+        mww 0xfffffc30 0x00001302
+        while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
+
+        # Processor and master clocks are now operating and stable at maximum frequency possible:
+        #       -> MCLK = 133.000 MHz
+        #       -> PCLK = 400.000 MHz
+
+        # Switch to fast JTAG speed
+
+        adapter speed 9500
+
+        # Enable faster DCC downloads.
+
+        arm7_9 dcc_downloads enable
+        arm7_9 fast_memory_access enable
+
+        # To be able to use external SDRAM, several peripheral configuration registers must
+        # be modified.  The first change is made to PIO_ASR to select peripheral functions
+        # for D15 through D31.  The second change is made to the PIO_PDR register to disable
+        # this for D15 through D31.
+
+        mww 0xfffff870 0xffff0000
+        mww 0xfffff804 0xffff0000
+
+        # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+        # using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
+        # the board to the 1.8V VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+        mww 0xffffef1c 0x000000a
+
+        # The USB-A9G20 Embedded computer has built-in NandFlash.  The exact physical timing characteristics
+        # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+        # four registers in order:  SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
+
+        mww 0xffffec30 0x00020002
+        mww 0xffffec34 0x04040404
+        mww 0xffffec38 0x00070007
+        mww 0xffffec3c 0x00030003
+
+        # Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
+        # are based on 2 x Micron LPSDRAM MT48H16M16LFBF-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference
+        # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
+        # into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock
+        # of 133.000 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:
+        #
+        #       CAS latency = 3 cycles
+        #       TXSR = 10 cycles
+        #       TRAS = 6 cycles
+        #       TRCD = 3 cycles
+        #       TRP = 3 cycles
+        #       TRC = 9 cycles
+        #       TWR = 2 cycles
+        #       9 column, 13 row, 4 banks
+        #       refresh equal to or less then 7.8 us for commercial/industrial rated devices
+        #
+        #       Thus SDRAM_CR = 0xa6339279
+
+        mww 0xffffea08 0xa6339279
+
+        # Memory Device Type: SDRAM (low-power would be 0x1)
+        mww 0xffffea24 0x00000000
+
+        # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
+        # the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x00000001
+        mww 0x20000000 0
+
+        # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
+        # value into the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x00000002
+        mww 0x20000000 0
+
+        # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing
+        # zero values eight times into the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x4
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+
+        # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
+        # the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x3
+        mww 0x20000000 0
+
+        # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting
+        # memory location for the SDRAM.
+
+        mww 0xffffea00 0x0
+        mww 0x20000000 0
+
+        # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
+
+        mww 0xffffea04 0x0000039c
+}
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
+$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/certuspro_evaluation.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/certuspro_evaluation.cfg
new file mode 100644
index 0000000..ba2f17c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/certuspro_evaluation.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# https://www.latticesemi.com/products/developmentboardsandkits/certuspro-nx-versa-board
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+reset_config none
+transport select jtag
+adapter speed 10000
+
+source [find fpga/lattice_certuspro.cfg]
+
+#openocd -f board/certuspro_evaluation.cfg -c "init" -c "pld load certuspro.pld shared_folder/certuspro_blinker_impl_1.bit"
+
+set JTAGSPI_CHAIN_ID certuspro.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init certuspro.pld "" -1
+#jtagspi_program shared_folder/certuspro_blinker_impl1.bit 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/colibri.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/colibri.cfg
new file mode 100644
index 0000000..b44985d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/colibri.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Toradex Colibri PXA270
+source [find target/pxa270.cfg]
+reset_config trst_and_srst srst_push_pull
+adapter srst pulse_width 40
+
+# CS0 -- one bank of CFI flash, 32 MBytes
+# the bank is 32-bits wide, two 16-bit chips in parallel
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/crossbow_tech_imote2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/crossbow_tech_imote2.cfg
new file mode 100644
index 0000000..07ce8c7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/crossbow_tech_imote2.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Crossbow Technology iMote2
+
+set  CHIPNAME imote2
+source [find target/pxa270.cfg]
+
+# longer-than-normal reset delay
+adapter srst delay 800
+
+reset_config trst_and_srst separate
+
+# works for P30 flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/csb337.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/csb337.cfg
new file mode 100644
index 0000000..f75abbe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/csb337.cfg
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Cogent CSB337
+#   http://cogcomp.com/csb_csb337.htm
+
+source [find target/at91rm9200.cfg]
+
+# boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+
+# ETM9 trace port connector present on this board, 16 data pins.
+if { [info exists ETM_DRIVER] } {
+	etm config $_TARGETNAME 16 normal half $ETM_DRIVER
+	# OpenOCD may someday support a real trace port driver...
+	# system config file would need to configure it.
+} else {
+	etm config $_TARGETNAME 16 normal half dummy
+	etm_dummy config $_TARGETNAME
+}
+
+proc csb337_clk_init { } {
+	# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
+	adapter speed 8
+
+	# CKGR_MOR:  start main oscillator (3.6864 MHz)
+	mww 0xfffffc20 0xff01
+	sleep 10
+
+	# CKGR_PLLAR:  start PLL A for CPU and peripherals (184.32 MHz)
+	mww 0xfffffc28 0x20313e01
+	# CKGR_PLLBR:  start PLL B for USB timing (96 MHz, with div2)
+	mww 0xfffffc2c 0x12703e18
+	# let PLLs lock
+	sleep 10
+
+	# PMC_MCKR:  switch to CPU clock = PLLA, master clock = CPU/4
+	mww 0xfffffc30 0x0302
+	sleep 20
+
+	# CPU is in Normal Mode ... allows faster JTAG clock speed
+	adapter speed 40000
+}
+
+proc csb337_nor_init { } {
+	# SMC_CSR0:  adjust timings (10 wait states)
+	mww 0xffffff70 0x1100318a
+
+	flash probe 0
+}
+
+proc csb337_sdram_init { } {
+	# enable PIOC clock
+	mww 0xfffffc10 0x0010
+	# PC31..PC16 are D31..D16, with internal pullups like D15..D0
+	mww 0xfffff870 0xffff0000
+	mww 0xfffff874 0x0
+	mww 0xfffff804 0xffff0000
+
+	# SDRC_CR: set timings
+	mww 0xffffff98 0x2188b0d5
+
+	# SDRC_MR: issue all banks precharge to SDRAM
+	mww 0xffffff90 2
+	mww 0x20000000 0
+
+	# SDRC_MR: 8 autorefresh cycles
+	mww 0xffffff90 4
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+
+	# SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
+	mww 0xffffff90 3
+	mww 0x20000080 0
+
+	# SDRC_TR: set refresh rate
+	mww 0xffffff94 0x200
+	mww 0x20000000 0
+
+	# SDRC_MR: normal mode, 32 bit bus
+	mww 0xffffff90 0
+	mww 0x20000000 0
+}
+
+# The rm9200 chip has just been reset.  Bring it up far enough
+# that we can write flash or run code from SDRAM.
+proc csb337_reset_init { } {
+	csb337_clk_init
+
+	# EBI_CSA:  CS0 = NOR, CS1 = SDRAM
+	mww 0xffffff60 0x02
+
+	csb337_nor_init
+	csb337_sdram_init
+
+	# Update CP15 control register ... we don't seem to be able to
+	# read/modify/write its value through a TCL variable, so just
+	# write it.  Fields are zero unless listed here ... and note
+	# that OpenOCD numbers this register "2", not "1" (!).
+	#
+	#  - Core to use Async Clocking mode (so it uses 184 MHz most
+	#    of the time instead of limiting to the master clock rate):
+	#	iA(31) = 1, nF(30) = 1
+	#  - Icache on (it's disabled now, slowing i-fetches)
+	#	I(12) = 1
+	#  - Reserved/ones
+	#	6:3 = 1
+	arm920t cp15 2 0xc0001078
+}
+
+$_TARGETNAME configure -event reset-init {csb337_reset_init}
+
+arm7_9 fast_memory_access enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/csb732.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/csb732.cfg
new file mode 100644
index 0000000..6df1750
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/csb732.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Cogent CSB732 board has a single i.MX35 chip
+source [find target/imx35.cfg]
+
+# Determined by trial and error
+reset_config trst_and_srst combined
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { csb732_init }
+
+# Bare-bones initialization of core clocks and SDRAM
+proc csb732_init { } {
+
+	# Disable fast writing only for init
+	memwrite burst disable
+
+	# All delay loops are omitted.
+	# We assume the interpreter latency is enough.
+
+	# Allow access to all coprocessors
+	arm mcr 15 0 15 1 0 0x2001
+
+	# Disable MMU, caches, write buffer
+	arm mcr 15 0 1 0 0 0x78
+
+	# Grant manager access to all domains
+	arm mcr 15 0 3 0 0 0xFFFFFFFF
+
+	# Set ARM clock to 532 MHz, AHB to 133 MHz
+	mww 0x53F80004 0x1000
+
+	# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
+	mww 0x53F8001C 0xB2C01
+
+	set ESDMISC 0xB8001010
+	set ESDCFG0 0xB8001004
+	set ESDCTL0 0xB8001000
+
+	# Enable DDR
+	mww $ESDMISC 0x4
+
+	# Timing
+	mww $ESDCFG0 0x007fff3f
+
+	# CS0
+	mww $ESDCTL0 0x92120080
+
+	# Precharge all dummy write
+	mww 0x80000400 0
+
+	# Enable CS) auto-refresh
+	mww $ESDCTL0 0xA2120080
+
+	# Refresh twice (dummy writes)
+	mww 0x80000000 0
+	mww 0x80000000 0
+
+	# Enable CS0 load mode register
+	mww $ESDCTL0 0xB2120080
+
+	# Dummy writes
+	mwb 0x80000033 0x01
+	mwb 0x81000000 0x01
+
+	mww $ESDCTL0 0x82226080
+	mww 0x80000000 0
+
+	# Re-enable fast writing
+	memwrite burst enable
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/da850evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/da850evm.cfg
new file mode 100644
index 0000000..12de3a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/da850evm.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#DA850 EVM board
+# http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939
+# http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
+
+source [find target/omapl138.cfg]
+
+reset_config trst_and_srst separate
+
+#currently any pinmux/timing must be setup by UBL before openocd can do debug
+#TODO: implement pinmux/timing on reset like in board/dm365evm.cfg
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digi_connectcore_wi-9c.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digi_connectcore_wi-9c.cfg
new file mode 100644
index 0000000..0ff4742
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digi_connectcore_wi-9c.cfg
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target: DIGI ConnectCore Wi-9C
+######################################
+
+reset_config trst_and_srst
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME ns9360
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+  # This config file was defaulting to big endian..
+   set  _ENDIAN big
+}
+
+
+# What's a good fallback frequency for this board if RCLK is
+# not available??
+jtag_rclk 1000
+
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926031
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+adapter srst delay 200
+jtag_ntrst_delay 0
+
+
+######################
+# Target configuration
+######################
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x90600104 0x33313333
+	mww 0xA0700000 0x00000001  ;# Enable the memory controller.
+	mww 0xA0700024 0x00000006  ;# Set the refresh counter 6
+	mww 0xA0700028 0x00000001  ;#
+	mww 0xA0700030 0x00000001  ;# Set the precharge period
+	mww 0xA0700034 0x00000004  ;# Active to precharge command period is 16 clock cycles
+	mww 0xA070003C 0x00000001  ;# tAPR
+	mww 0xA0700040 0x00000005  ;# tDAL
+	mww 0xA0700044 0x00000001  ;# tWR
+	mww 0xA0700048 0x00000006  ;# tRC 32 clock cycles
+	mww 0xA070004C 0x00000006  ;# tRFC 32 clock cycles
+	mww 0xA0700054 0x00000001  ;# tRRD
+	mww 0xA0700058 0x00000001  ;# tMRD
+	mww 0xA0700100 0x00004280  ;# Dynamic Config 0 (cs4)
+	mww 0xA0700120 0x00004280  ;# Dynamic Config 1 (cs5)
+	mww 0xA0700140 0x00004280  ;# Dynamic Config 2 (cs6)
+	mww 0xA0700160 0x00004280  ;# Dynamic Config 3 (cs7)
+	#
+	mww 0xA0700104 0x00000203  ;# CAS latency is 2 at 100 MHz
+	mww 0xA0700124 0x00000203  ;# CAS latency is 2 at 100 MHz
+	mww 0xA0700144 0x00000203  ;# CAS latency is 2 at 100 MHz
+	mww 0xA0700164 0x00000203  ;# CAS latency is 2 at 100 MHz
+	#
+	mww 0xA0700020 0x00000103  ;# issue SDRAM PALL command
+	#
+	mww 0xA0700024 0x00000001  ;# Set the refresh counter to be as small as possible
+	#
+	# Add some dummy writes to give the SDRAM time to settle, it needs two
+	# AHB clock cycles, here we poke in the debugger flag, this lets
+	# the software know that we are in the debugger
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	#
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	#
+	mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30
+	mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command
+	#
+	# Next we perform a read of RAM.
+	# mw = move word.
+	mdw 0x00022000
+	# mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
+	#
+	mww 0xA0700020 0x00000003   ;# issue SDRAM NORMAL command
+	mww 0xA0700100 0x00084280   ;# Enable buffer access
+	mww 0xA0700120 0x00084280   ;# Enable buffer access
+	mww 0xA0700140 0x00084280   ;# Enable buffer access
+	mww 0xA0700160 0x00084280   ;# Enable buffer access
+
+	#Set byte lane state (static mem 1)"
+	mww 0xA0700220 0x00000082
+	#Flash Start
+	mww 0xA09001F8 0x50000000
+	#Flash Mask Reg
+	mww 0xA09001FC 0xFF000001
+	mww 0xA0700028 0x00000001
+
+	#  RAMAddr = 0x00020000
+	#  RAMSize = 0x00004000
+
+	# Set the processor mode
+	reg cpsr 0xd3
+}
+
+$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
+
+#####################
+# Flash configuration
+#####################
+
+#M29DW323DB - not working
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_analog_discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_analog_discovery.cfg
new file mode 100644
index 0000000..1bc239b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_analog_discovery.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent Analog Discovery
+#
+# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,842,1018&Prod=ANALOG-DISCOVERY
+#
+# Config is based on data from
+# https://github.com/bvanheu/urjtag-ad/commit/8bd883ee01d134f94b79cbbd00df42cd03bafd71
+#
+
+adapter driver ftdi
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6014
+
+ftdi layout_init 0x8008 0x800b
+
+adapter speed 25000
+
+source [find cpld/xilinx-xc6s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_anvyl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_anvyl.cfg
new file mode 100644
index 0000000..e820028
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_anvyl.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Digilent Anvyl with Xilinx Spartan-6 FPGA
+# https://digilent.com/reference/programmable-logic/anvyl/start
+# Almost the same setup as the Digilent Nexys Video board or the Digilent HS1
+# adapter.
+adapter driver ftdi
+adapter speed 30000
+
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6010
+
+# channel 0 is the JTAG channel
+# channel 1 is a user serial channel to pins on the FPGA
+ftdi channel 0
+
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0088 0x008b
+reset_config none
+
+# Enable sampling on falling edge for high JTAG speeds.
+ftdi tdo_sample_edge falling
+
+transport select jtag
+
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_atlys.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_atlys.cfg
new file mode 100644
index 0000000..568253b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_atlys.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://digilentinc.com/atlys/
+#
+# The Digilent Atlys normally requires proprietary tools to program and will
+# enumerate as:
+#   ID 1443:0007 Digilent Development board JTAG
+#
+# However, the ixo-usb-jtag project provides an alternative open firmware for
+# the on board programmer. When using this firmware the board will then
+# enumerate as:
+#   ID 16c0:06ad Van Ooijen Technische Informatica
+# (With SerialNumber == hw_nexys)
+#
+# See the interface/usb-jtag.cfg for more information.
+
+source [find interface/usb-jtag.cfg]
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_cmod_s7.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_cmod_s7.cfg
new file mode 100644
index 0000000..4fa45a1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_cmod_s7.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# digilent CMOD S7
+# https://digilent.com/reference/programmable-logic/cmod-s7/reference-manual
+
+
+adapter driver ftdi
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+ftdi vid_pid 0x0403 0x6010
+reset_config none
+transport select jtag
+
+adapter speed 10000
+
+source [find cpld/xilinx-xc7.cfg]
+
+# "ipdbg create-hub xc7.ipdbghub -tap xc7.tap -ir 0x02"
+# "xc7.ipdbghub ipdbg start -tool 0 -port 5555"
+#openocd -f board/digilent_cmod_s7.cfg -c "init" -c "pld load xc7.pld shared_folder/cmod_s7_fast.bit"
+
+set JTAGSPI_CHAIN_ID xc7.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init xc7.pld "shared_folder/bscan_spi_xc7s25.bit" 0xab
+#jtagspi_program shared_folder/cmod_s7_fast.bit 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_nexys2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_nexys2.cfg
new file mode 100644
index 0000000..c1c5b2a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_nexys2.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# https://digilent.com/reference/programmable-logic/nexys-2/start
+#
+# The Digilent Nexy2 normally requires proprietary tools to program and will
+# enumerate as:
+#   ID 1443:0005 1443 ONBOARD USB
+#
+# However, the ixo-usb-jtag project provides an alternative open firmware for
+# the on board programmer. When using this firmware the board will then
+# enumerate as:
+#   ID 16c0:06ad ixo.de USB-JTAG-IF (With SerialNumber == hw_nexys)
+#
+# See the interface/usb-jtag.cfg for more information.
+
+source [find interface/usb-jtag.cfg]
+source [find cpld/xilinx-xcf-s.cfg]
+source [find fpga/xilinx-xc3s.cfg]
+
+# Usage:
+#
+# Load Bitstream into FPGA:
+#    openocd -f board/digilent_nexys2.cfg -c "init;\
+#    pld load 0 bitstream.bit;\
+#    shutdown"
+
+# Read Unique Device Identifier (DNA):
+#    openocd -f board/digilent_nexys2.cfg -c "init;\
+#    xilinx_print_dna [xc3s_get_dna xc3s.tap];\
+#    shutdown"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_nexys_video.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_nexys_video.cfg
new file mode 100644
index 0000000..b60ec91
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_nexys_video.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Digilent Nexys Video with Xilinx Artix-7 FPGA
+# https://reference.digilentinc.com/programmable-logic/nexys-video/start
+
+adapter driver ftdi
+adapter speed 30000
+
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6010
+
+# channel 0 is dedicated for Digilent's DPTI Interface
+# channel 1 is used for JTAG
+ftdi channel 1
+
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0088 0x008b
+reset_config none
+
+# Enable sampling on falling edge for high JTAG speeds.
+ftdi tdo_sample_edge falling
+
+transport select jtag
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_zedboard.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_zedboard.cfg
new file mode 100644
index 0000000..010e8c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/digilent_zedboard.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent Zedboard Rev.C, Rev.D with Xilinx Zynq chip
+#
+# http://zedboard.com/product/zedboard
+#
+
+source [find interface/ftdi/digilent_jtag_smt2.cfg]
+
+reset_config srst_only srst_push_pull
+
+source [find target/zynq_7000.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/diolan_lpc4350-db1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/diolan_lpc4350-db1.cfg
new file mode 100644
index 0000000..c55621d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/diolan_lpc4350-db1.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Diolan LPC-4350-DB1 development board
+#
+
+set CHIPNAME lpc4350
+
+source [find target/lpc4350.cfg]
+
+flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/diolan_lpc4357-db1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/diolan_lpc4357-db1.cfg
new file mode 100644
index 0000000..155328a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/diolan_lpc4357-db1.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Diolan LPC-4357-DB1 development board
+#
+
+set CHIPNAME lpc4357
+
+source [find target/lpc4357.cfg]
+
+flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dk-tm4c129.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dk-tm4c129.cfg
new file mode 100644
index 0000000..27bd432
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dk-tm4c129.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti_dk-tm4c129.cfg"
+
+source [find board/ti_dk-tm4c129.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dm355evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dm355evm.cfg
new file mode 100644
index 0000000..0dbffa8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dm355evm.cfg
@@ -0,0 +1,203 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# DM355 EVM board
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
+#   http://c6000.spectrumdigital.com/evmdm355/
+
+source [find target/ti_dm355.cfg]
+
+reset_config trst_and_srst separate
+
+# NOTE:  disable or replace this call to dm355evm_init if you're
+# debugging new UBL code from SRAM.
+$_TARGETNAME configure -event reset-init { dm355evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm355evm_init {} {
+	global dm355
+
+	echo "Initialize DM355 EVM board"
+
+	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
+	jtag_rclk 1500
+
+	########################
+	# PLL1		= 432 MHz (/8, x144)
+	# ...SYSCLK1	= 216 MHz (/2)  ... ARM, MJCP
+	# ...SYSCLK2	= 108 MHz (/4)  ... Peripherals
+	# ...SYSCLK3	= 27  MHz (/16) ... VPBE, DAC
+	# ...SYSCLK4	= 108 MHz (/4)  ... VPSS
+	#	pll1.{prediv,div1,div2} are fixed
+	#	pll1.postdiv set in MISC (for *this* speed grade)
+
+	set addr [dict get $dm355 pllc1]
+	set pll_divs [dict create]
+	dict set pll_divs div3 16
+	dict set pll_divs div4 4
+	pll_v02_setup $addr 144 $pll_divs
+
+	# ARM is now running at 216 MHz, so JTAG can go faster
+	jtag_rclk 20000
+
+	########################
+	# PLL2		= 342 MHz (/8, x114)
+	# ....SYSCLK1	= 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock
+	#	pll2.{postdiv,div1} are fixed
+
+	set addr [dict get $dm355 pllc2]
+	set pll_divs [dict create]
+	dict set pll_divs div1 1
+	dict set pll_divs prediv 8
+	pll_v02_setup $addr 114 $pll_divs
+
+	########################
+	# PINMUX
+
+	# All Video Inputs
+	davinci_pinmux $dm355 0 0x00007f55
+	# All Video Outputs
+	davinci_pinmux $dm355 1 0x00145555
+	# EMIFA (NOTE: more could be set up for use as GPIOs)
+	davinci_pinmux $dm355 2 0x00000c08
+	# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+	davinci_pinmux $dm355 3 0x1bff55ff
+	# MMC/SD0 instead of MS; SPI0
+	davinci_pinmux $dm355 4 0x00000000
+
+	########################
+	# PSC setup (minimal)
+
+	# DDR EMIF/13, AEMIF/14, UART0/19
+	psc_enable 13
+	psc_enable 14
+	psc_enable 19
+	psc_go
+
+	########################
+	# DDR2 EMIF
+
+	# VTPIOCR impedance calibration
+	set addr [dict get $dm355 sysbase]
+	set addr [expr {$addr + 0x70}]
+
+	# clear CLR, LOCK, PWRDN; wait a clock; set CLR
+	mmw $addr 0 0x20c0
+	mmw $addr 0x2000 0
+
+	# wait for READY
+        while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
+
+	# set IO_READY; then LOCK and PWRSAVE; then PWRDN
+	mmw $addr 0x4000 0
+	mmw $addr 0x0180 0
+	mmw $addr 0x0040 0
+
+	# NOTE:  this DDR2 initialization sequence borrows from
+	# both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
+
+	# reset (then re-enable) DDR controller
+	psc_reset 13
+	psc_go
+	psc_enable 13
+	psc_go
+
+	# now set it up for Micron MT47H64M16HR-37E @ 171 MHz
+
+	set addr [dict get $dm355 ddr_emif]
+
+	# DDRPHYCR1
+	mww [expr {$addr + 0xe4}] 0x50006404
+
+	# PBBPR -- burst priority
+	mww [expr {$addr + 0x20}] 0xfe
+
+	# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
+	mmw [expr {$addr + 0x08}] 0x00800000 0
+	mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
+
+	# SDTIMR0, SDTIMR1
+	mww [expr {$addr + 0x10}] 0x2a923249
+	mww [expr {$addr + 0x14}] 0x4c17c763
+
+	# SDCR -- relock SDTIM*
+	mmw [expr {$addr + 0x08}] 0 0x00008000
+
+	# SDRCR -- refresh rate (171 MHz * 7.8usec)
+	mww [expr {$addr + 0x0c}] 1336
+
+	########################
+	# ASYNC EMIF
+
+	set addr [dict get $dm355 a_emif]
+
+	# slow/pessimistic timings
+	set nand_timings 0x40400204
+	# fast (25% faster page reads)
+	#set nand_timings 0x0400008c
+
+	# AWCCR
+	mww [expr {$addr + 0x04}] 0xff
+	# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
+	mww [expr {$addr + 0x10}] $nand_timings
+	# CS1 == dm9000 Ethernet
+	mww [expr {$addr + 0x14}] 0x00a00505
+	# NANDFCR -- only CS0 has NAND
+	mww [expr {$addr + 0x60}] 0x01
+
+	# default: both chipselects to the NAND socket are used
+	nand probe 0
+	nand probe 1
+
+	########################
+	# UART0
+
+	set addr [dict get $dm355 uart0]
+
+	# PWREMU_MGNT -- rx + tx in reset
+	mww [expr {$addr + 0x30}] 0
+
+	# DLL, DLH -- 115200 baud
+	mwb [expr {$addr + 0x20}] 0x0d
+	mwb [expr {$addr + 0x24}] 0x00
+
+	# FCR - clear and disable FIFOs
+	mwb [expr {$addr + 0x08}] 0x07
+	mwb [expr {$addr + 0x08}] 0x00
+
+	# IER - disable IRQs
+	mwb [expr {$addr + 0x04}] 0x00
+
+	# LCR - 8-N-1
+	mwb [expr {$addr + 0x0c}] 0x03
+
+	# MCR - no flow control or loopback
+	mwb [expr {$addr + 0x10}] 0x00
+
+	# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
+	mww [expr {$addr + 0x30}] 0xe001
+
+
+	########################
+
+	# turn on icache - set I bit in cp15 register c1
+	arm mcr 15 0 0 1 0 0x00051078
+}
+
+# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
+#
+# NOTE:  "hwecc4" here presumes that if you're using the standard 2GB NAND
+# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
+# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
+# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
+set _FLASHNAME $_CHIPNAME.boot
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
+
+# FIXME
+#  - support writing UBL with its header (new layout only with new ROMs)
+#  - support writing ABL/U-Boot with its header (new layout)
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dm365evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dm365evm.cfg
new file mode 100644
index 0000000..15db24c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dm365evm.cfg
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# DM365 EVM board -- Beta
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
+#   http://support.spectrumdigital.com/boards/evmdm365
+
+source [find target/ti_dm365.cfg]
+
+# NOTE:  in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
+# connector, so it doesn't affect generation of the reset signal.
+# Accordingly, resets require something else.  ICEpick could do it;
+# but its docs aren't generally available.
+#
+# At this writing, newer boards aren't available ... so assume no SRST.
+# Also ICEpick docs aren't available ... so we must use watchdog reset,
+# and hope the CPU isn't wedged or in a WFI loop (either of which can
+# block access to CPU and thus watchdog registers).
+
+reset_config trst_only
+$_TARGETNAME configure -event reset-assert "davinci_wdog_reset"
+
+# SW5.1 routes CS0: NAND vs OneNAND.
+# SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)
+# for boot-from-flash, those must agree with SW4.3:1 settings.
+
+if { [info exists CS0MODE] } {
+	# NAND or OneNAND
+	set CS0 $CS0MODE
+} else {
+	set CS0 ""
+	echo "WARNING:  CS0 configuration not known"
+	proc cs0_setup {a_emif} {}
+	proc flashprobe {} {}
+}
+
+set a_emif [dict get $dm365 a_emif]
+
+# As shipped:  boot from NAND.
+if { $CS0 == "NAND" } {
+	echo "CS0 NAND"
+
+	# NAND socket has two chipselects.  Default MT29F16G08FAA chip
+	# has 1GByte on each one.
+	# NOTE:  "hwecc4" here presumes that you're not updating anything
+	# that needs infix layout (e.g. UBL, old U-Boot, etc)
+	nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif
+	nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif
+
+	proc cs0_setup {a_emif} {
+		global dm365
+
+		# 8 bit EMIF
+		davinci_pinmux $dm365 2 0x00000016
+
+		# slow/pessimistic timings
+		set nand_timings 0x40400204
+		# fast (25% faster page reads)
+		#set nand_timings 0x0400008c
+
+		# CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
+		mww [expr {$a_emif + 0x10}] $nand_timings
+
+		# NANDFCR -- CS0 has NAND
+		mww [expr {$a_emif + 0x60}] 0x01
+	}
+	proc flashprobe {} {
+		nand probe 0
+		nand probe 1
+	}
+
+} elseif { $CS0 == "OneNAND" } {
+	echo "CS0 OneNAND"
+
+	# No support for this OneNAND in OpenOCD (yet) or Linux ...
+	# REVISIT OneNAND timings not verified to work!
+	echo "WARNING -- OneNAND not yet tested!"
+
+	proc cs0_setup {a_emif} {
+		global dm365
+
+		# 16 bit EMIF
+		davinci_pinmux $dm365 2 0x00000055
+
+		# CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
+		mww [expr {$a_emif + 0x10}] 0x00000001
+
+		# ONENANDCTRL -- CS0 has OneNAND, enable sync reads
+		mww [expr {$a_emif + 0x5c}] 0x0441
+	}
+	proc flashprobe {} { }
+}
+
+# NOTE:  disable or replace this call to dm365evm_init if you're
+# debugging new UBL/NANDboot code from SRAM.
+$_TARGETNAME configure -event reset-init { dm365evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm365evm_init {} {
+	global dm365
+
+	echo "Initialize DM365 EVM board"
+
+	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
+	adapter speed 1500
+
+	# FIXME -- PLL init
+
+	########################
+	# PINMUX setup
+
+	davinci_pinmux $dm365 0 0x00fd0000
+	davinci_pinmux $dm365 1 0x00145555
+	# mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand
+	davinci_pinmux $dm365 3 0x375affff
+	davinci_pinmux $dm365 4 0x55556555
+
+	########################
+	# PSC setup (minimal)
+
+	# DDR EMIF/13, AEMIF/14, UART0/19
+	psc_enable 13
+	psc_enable 14
+	psc_enable 19
+	psc_go
+
+	# FIXME setup DDR2 (needs PLL)
+
+	########################
+	# ASYNC EMIF
+
+	set a_emif [dict get $dm365 a_emif]
+
+	# AWCCR
+	mww [expr {$a_emif + 0x04}] 0xff
+	# CS0 == NAND or OneNAND
+	cs0_setup $a_emif
+	# CS1 == CPLD
+	mww [expr {$a_emif + 0x14}] 0x00a00505
+
+	# FIXME setup UART0
+
+	flashprobe
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dm6446evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dm6446evm.cfg
new file mode 100644
index 0000000..1236b86
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dm6446evm.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# DM6446 EVM board
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html
+#   http://c6000.spectrumdigital.com/davincievm/
+# EVM is just the board; buy that at Spectrum.
+# The "kit" from TI also has: video camera, LCD video monitor, more.
+
+source [find target/ti_dm6446.cfg]
+
+# J4 controls what CS2 hooks up to, usually NOR or NAND flash.
+# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings.
+# S3.3 controls AEMIF bus width.
+
+if { [info exists J4_OPTION] } {
+	# NOR, NAND, SRAM, ...
+	set CS2_MODE $J4_OPTION
+} else {
+	set CS2_MODE ""
+}
+
+# ARM boot:
+#  S3.1 = 0, S3.2 = 0	==> ROM/UBL boot via NAND (J4 == NAND)
+#  S3.1 = 1, S3.2 = 0	==> AEMIF boot (J4 == NOR or SRAM)
+#  S3.1 = 0, S3.2 = 1	==> ROM/UBL boot via HPI
+#  S3.1 = 1, S3.2 = 1	==> ROM/UBL boot via UART (J4 == don't care)
+# AEMIF bus width:
+#  S3.3 = 0		==> 8 bit bus width
+#  S3.3 = 1		==> 16 bit bus width
+# DSP boot:
+#  S3.4 = 0		==> controlled by ARM
+
+if { $CS2_MODE == "NOR" } {
+	# 16 Mbytes address space; 16 bit bus width
+	# (older boards used 32MB parts, with upper 16 MB unusable)
+	set _FLASHNAME $_CHIPNAME.flash
+	flash bank $_FLASHNAME cfi 0x02000000 0x01000000 2 2 $_TARGETNAME
+	proc flashprobe {} { flash probe 0 }
+} elseif { $CS2_MODE == "NAND" } {
+	# 64 Mbyte small page; 8 bit bus width
+	nand device davinci $_TARGETNAME 0x02000000 hwecc1 0x01e00000
+	proc flashprobe {} { nand probe 0 }
+} elseif { $CS2_MODE == "SRAM" } {
+	# 4 Mbyte address space; 16 bit bus width
+	# loaded via JTAG or HPI
+	proc flashprobe {} {}
+} else {
+	# maybe it's HPI boot?  can't tell...
+	echo "WARNING:  CS2/flash configuration not recognized"
+	proc flashprobe {} {}
+}
+
+# NOTE:  disable or replace this call to dm6446evm_init if you're
+# debugging new UBL code from SRAM (for NAND boot).
+$_TARGETNAME configure -event reset-init { dm6446evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm6446evm_init {} {
+
+	echo "Initialize DM6446 EVM board"
+
+	# FIXME initialize everything:
+	#  - PLL1
+	#  - PLL2
+	#  - PINMUX
+	#  - PSC
+	#  - DDR
+	#  - AEMIF
+	#  - UART0
+	#  - icache
+
+	flashprobe
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dp_busblaster_v3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dp_busblaster_v3.cfg
new file mode 100644
index 0000000..5599617
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dp_busblaster_v3.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Dangerous Prototypes - Bus Blaster
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+# To reprogram the on-board CPLD do:
+# openocd -f board/dp_busblaster_v3.cfg -c "adapter speed 1000; init; svf ; shutdown"
+#
+
+source [find interface/ftdi/dp_busblaster.cfg]
+ftdi channel 1
+
+jtag newtap xc2c32a tap -expected-id 0x06e1c093 -irlen 8
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dp_busblaster_v4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dp_busblaster_v4.cfg
new file mode 100644
index 0000000..2c2f0e9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dp_busblaster_v4.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Dangerous Prototypes - Bus Blaster
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+# The Bus Blaster has a configurable buffer between the FTDI FT2232H
+# and the JTAG header which allows it to emulate various debugger
+# types. This config works with KT-Link compatible implementation from
+# https://raw.githubusercontent.com/dergraaf/busblaster_v4/master/ktlink/ktlink.svf
+#
+# To reprogram the on-board CPLD do:
+# openocd -f board/dp_busblaster_v4.cfg -c "adapter speed 1000; init; svf ; shutdown"
+#
+
+source [find interface/ftdi/dp_busblaster.cfg]
+ftdi channel 1
+
+jtag newtap xc2c64a tap -expected-id 0x06e5c093 -irlen 8
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dptechnics_dpt-board-v1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dptechnics_dpt-board-v1.cfg
new file mode 100644
index 0000000..3ab2c68
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/dptechnics_dpt-board-v1.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Product page:
+# https://www.dptechnics.com/en/products/dpt-board-v1.html
+#
+# JTAG is a 5 pin array located close to main module in following order:
+# 1. JTAG TCK
+# 2. JTAG TDO
+# 3. JTAG TDI
+# 4. JTAG TMS
+# 5. GND	The GND is located near letter G of word JTAG on board.
+#
+# Two RST pins are connected to:
+# 1. GND
+# 2. GPIO11	this pin is located near letter R of word RST.
+#
+# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
+# with 10K resistor connected to V3.3 pin.
+#
+# This board is powered from micro USB connector. No real reset pin or button, for
+# example RESET_L is available.
+
+source [find target/atheros_ar9331.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	ar9331_25mhz_pll_init
+	sleep 1
+	ar9331_ddr2_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ecp5_evaluation.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ecp5_evaluation.cfg
new file mode 100644
index 0000000..71769f6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ecp5_evaluation.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Lattice ECP5 evaluation Kit
+# https://www.latticesemi.com/view_document?document_id=52479
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+reset_config none
+transport select jtag
+adapter speed 6000
+
+source [find fpga/lattice_ecp5.cfg]
+
+#openocd -f board/ecp5_evaluation.cfg -c "init" -c "pld load ecp5.pld shared_folder/ecp5_blinker_impl1.bit"
+#ipdbg create-hub ecp5.ipdbghub -tap ecp5.tap -ir 0x32
+#ecp5.ipdbghub ipdbg start -tool 0 -port 5555
+
+set JTAGSPI_CHAIN_ID ecp5.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init ecp5.pld "" -1
+#jtagspi_program shared_folder/ecp5_blinker_impl1_slow.bit 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/efikamx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/efikamx.cfg
new file mode 100644
index 0000000..9083543
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/efikamx.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Genesi USA EfikaMX
+#  http://www.genesi-usa.com/products/efika
+
+# Fall back to 6MHz if RTCK is not supported
+jtag_rclk 6000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 6000 }
+
+source [find target/imx51.cfg]
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/efm32.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/efm32.cfg
new file mode 100644
index 0000000..0ffab04
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/efm32.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for EFM32 boards with on-board SEGGER J-Link
+#
+# Tested with Tiny, Giant and Zero Gecko Starter Kit.
+#
+
+source [find interface/jlink.cfg]
+transport select swd
+adapter speed 1000
+
+set CHIPNAME efm32
+source [find target/efm32.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/eir.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/eir.cfg
new file mode 100644
index 0000000..d634249
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/eir.cfg
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Elector Internet Radio board
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+source [find target/at91sam7se512.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	# WDT_MR, disable watchdog
+	mww 0xFFFFFD44 0x00008000
+
+	# RSTC_MR, enable user reset
+	mww 0xfffffd08 0xa5000001
+
+	# CKGR_MOR
+	mww 0xFFFFFC20 0x00000601
+	sleep 10
+
+	# CKGR_PLLR
+	mww 0xFFFFFC2C 0x00481c0e
+	sleep 10
+
+	# PMC_MCKR
+	mww 0xFFFFFC30 0x00000007
+	sleep 10
+
+	# PMC_IER
+	mww 0xFFFFFF60 0x00480100
+
+	#
+	# Enable SDRAM interface.
+	#
+
+	# Enable SDRAM control at PIO A.
+	mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
+	mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
+
+	# Enable address bus (A0, A2-A11, A13-A17) at PIO B
+	mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
+	mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
+
+	# Enable 16 bit data bus at PIO C
+	mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
+	mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
+
+	# Enable SDRAM chip select
+	mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
+
+	# Set SDRAM characteristics in configuration register.
+	# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
+	mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
+	sleep 10
+
+	# Issue 16 bit SDRAM command: NOP
+	mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 16 bit SDRAM command: Precharge all
+	mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 8 auto-refresh cycles
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 16 bit SDRAM command: Set mode register
+	mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
+	mww 0x20000014 0xcafedede
+
+	# Set refresh rate count ???
+	mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
+
+	# Issue 16 bit SDRAM command: Normal mode
+	mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000180
+
+	#
+	# Enable external reset key.
+	#
+	mww 0xfffffd08 0xa5000001
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s1968.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s1968.cfg
new file mode 100644
index 0000000..c794a17
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s1968.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S1968 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s1968
+#
+
+# NOTE:  to use J-Link instead of the on-board interface,
+# you may also need to reduce adapter speed to be about 1200.
+# source [find interface/jlink.cfg]
+
+# include the FT2232 interface config for on-board JTAG interface
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# include the target config
+set WORKAREASIZE 0x2000
+set CHIPNAME lm3s1968
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s3748.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s3748.cfg
new file mode 100644
index 0000000..705cb64
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s3748.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris lm3s3748 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s3748
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# 20k working area
+set WORKAREASIZE 0x4000
+set CHIPNAME lm3s3748
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s6965.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s6965.cfg
new file mode 100644
index 0000000..ee4e15f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s6965.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S6965 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s6965
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# 20k working area
+set WORKAREASIZE 0x5000
+set CHIPNAME lm3s6965
+# include the target config
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s811-revb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s811-revb.cfg
new file mode 100644
index 0000000..f968eec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s811-revb.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S811 Evaluation Kits (rev B and earlier)
+#
+# http://www.ti.com/tool/ek-lm3s811
+#
+
+# NOTE: newer 811-EK boards (rev C and above) shouldn't use this.
+# use board/ek-lm3s811.cfg
+source [find interface/ftdi/luminary-lm3s811.cfg]
+
+# include the target config
+set WORKAREASIZE 0x2000
+set CHIPNAME lm3s811
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s811.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s811.cfg
new file mode 100644
index 0000000..0cf36c2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s811.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S811 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s811
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+# NOTE:  older '811-EK boards (before rev C) shouldn't use this.
+source [find interface/ftdi/luminary.cfg]
+
+# include the target config
+set WORKAREASIZE 0x2000
+set CHIPNAME lm3s811
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s8962.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s8962.cfg
new file mode 100644
index 0000000..71a1b10
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s8962.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S8962 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s8962
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# 64k working area
+set WORKAREASIZE 0x10000
+set CHIPNAME lm3s8962
+# include the target config
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s9b9x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s9b9x.cfg
new file mode 100644
index 0000000..289a2cc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s9b9x.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S9B9x Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s9b90
+# http://www.ti.com/tool/ek-lm3s9b92
+#
+
+# NOTE:  using the bundled FT2232 JTAG/SWD/SWO interface is optional!
+# so is using in JTAG mode, as done here.
+source [find interface/ftdi/luminary-icdi.cfg]
+
+set WORKAREASIZE 0x4000
+set CHIPNAME lm3s9b9x
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s9d92.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s9d92.cfg
new file mode 100644
index 0000000..08bbbdb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm3s9d92.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S9D92 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s9d92
+#
+
+# NOTE:  using the bundled FT2232 JTAG/SWD/SWO interface is optional!
+# so is using in JTAG mode, as done here.
+source [find interface/ftdi/luminary-icdi.cfg]
+
+# 64k working area
+set WORKAREASIZE 0x10000
+set CHIPNAME lm3s9d92
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm4f120xl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm4f120xl.cfg
new file mode 100644
index 0000000..db8b201
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm4f120xl.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Stellaris Launchpad ek-lm4f120xl Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm4f120xl
+#
+
+#
+# NOTE: using the bundled ICDI interface is optional!
+# This interface is not ftdi based as previous boards were
+#
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME lm4f120h5qr
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm4f232.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm4f232.cfg
new file mode 100644
index 0000000..89b2c3c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-lm4f232.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Stellaris LM4F232 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm4f232
+#
+
+#
+# NOTE: using the bundled ICDI interface is optional!
+# This interface is not ftdi based as previous boards were
+#
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME lm4f23x
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-tm4c123gxl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-tm4c123gxl.cfg
new file mode 100644
index 0000000..d569e58
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-tm4c123gxl.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti_ek-tm4c123gxl.cfg"
+
+source [find board/ti_ek-tm4c123gxl.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-tm4c1294xl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-tm4c1294xl.cfg
new file mode 100644
index 0000000..5c11674
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ek-tm4c1294xl.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti_ek-tm4c1294xl.cfg"
+
+source [find board/ti_ek-tm4c1294xl.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/embedded-artists_lpc2478-32.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/embedded-artists_lpc2478-32.cfg
new file mode 100644
index 0000000..ef61060
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/embedded-artists_lpc2478-32.cfg
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Embedded Artists eval board for LPC2478
+# http://www.embeddedartists.com/
+
+# Target device: LPC2478
+set CCLK 72000
+source [find target/lpc2478.cfg]
+
+# Helper
+#
+proc read_register {register} {
+    return [read_memory $register 32 1]
+}
+
+proc init_board {} {
+    # Delays on reset lines
+    adapter srst delay 500
+    jtag_ntrst_delay 1
+
+    # Adaptive JTAG clocking through RTCK.
+    #
+    jtag_rclk 20
+
+    global _TARGETNAME
+    global _CHIPNAME
+
+    # A working area will help speeding the flash programming
+    $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0
+
+    # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
+    flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
+
+    # Event handlers
+    #
+    $_TARGETNAME configure -event reset-start {
+        # Back to the slow JTAG clock
+        jtag_rclk 20
+    }
+
+    $_TARGETNAME configure -event reset-init {
+        arm core_state arm
+        arm7_9 dcc_downloads enable     ;# Speed up downloads by using DCC transfer
+        arm7_9 fast_memory_access enable
+
+        # Peripheral clocks
+        mww 0xE01FC0C4 0x04280FFE       ;# PCONP: (reset value)
+
+        # Map the user flash to the vector table area (0x00...0x3F)
+        mww 0xE01FC040 0x00000001       ;# MEMMAP: User flash
+
+        # Memory accelerator module
+        mww 0xE01FC004 0x00000003       ;# MAMTIM: 3 clock cycles
+        mww 0xE01FC000 0x00000002       ;# MAMCR: fully enabled
+
+        # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
+        mww 0xE002C014 0x55010115       ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
+                                         # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
+                                         # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
+        mww 0xE002C018 0x55555555       ;# PINSEL6: P3.0...P3.15=D0...D15
+        mww 0xE002C01C 0x55555555       ;# PINSEL7: P3.16...P3.31=D16...D31
+        mww 0xE002C020 0x55555555       ;# PINSEL8: P4.0...P4.15=A0...A15
+        mww 0xE002C024 0x50051555       ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
+                                         # P4.25=WE, P4.30=CS0, P4.31=CS1
+        mww 0xFFE08000 0x00000001       ;# EMCControl: Enable EMC
+
+        # Start PLL, then use faster JTAG clock
+        enable_pll
+        jtag_rclk 3000
+
+        # 16-bit flash @ CS0 (SST39VF3201-70)
+        mww 0xFFE08200 0x00080081       ;# EMCStaticConfig0: 16 bit, PB=1, buffers on
+        mww 0xFFE08204 0x00000000       ;# EMCStaticWaitWen0
+        mww 0xFFE08208 0x00000000       ;# EMCStaticWaitOen0
+        mww 0xFFE0820C 0x00000005       ;# EMCStaticWaitRd0
+        mww 0xFFE08210 0x00000005       ;# EMCStaticWaitPage0
+        mww 0xFFE08214 0x00000003       ;# EMCStaticWaitWr0
+        mww 0xFFE08218 0x00000001       ;# EMCStaticWaitTurn0
+
+        # 8-bit NAND @ CS1
+        # TODO
+
+        # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
+        mww 0xFFE08028 0x00000001       ;# EMCDynamicReadConfig
+        mww 0xFFE08030 0x00000001       ;# EMCDynamicRP
+        mww 0xFFE08034 0x00000003       ;# EMCDynamicRAS
+        mww 0xFFE08038 0x00000005       ;# EMCDynamicSREX
+        mww 0xFFE0803C 0x00000001       ;# EMCDynamicAPR
+        mww 0xFFE08040 0x00000005       ;# EMCDynamicDAL
+        mww 0xFFE08044 0x00000001       ;# EMCDynamicWR
+        mww 0xFFE08048 0x00000005       ;# EMCDynamicRC
+        mww 0xFFE0804C 0x00000005       ;# EMCDynamicRFC
+        mww 0xFFE08050 0x00000005       ;# EMCDynamicXSR
+        mww 0xFFE08054 0x00000001       ;# EMCDynamicRRD
+        mww 0xFFE08058 0x00000001       ;# EMCDynamicMRD
+        #
+        mww 0xFFE08104 0x00000202       ;# EMCDynamicRasCas0
+        mww 0xFFE08100 0x00005488       ;# EMCDynamicConfig0
+        sleep 100
+        mww 0xFFE08020 0x00000183       ;# EMCDynamicControl: Clock on continuously, NOP
+        sleep 10
+        mww 0xFFE08020 0x00000103       ;# EMCDynamicControl: PRECHARGE-ALL
+        mww 0xFFE08024 0x00000046       ;# EMCDynamicRefresh
+        sleep 100
+        mww 0xFFE08020 0x00000083       ;# EMCDynamicControl: MODE
+        mdw 0xA0011000 1                ;# Set SDRAM mode register
+        mww 0xFFE08020 0x00000000       ;# EMCDynamicControl: NORMAL
+        mww 0xFFE08100 0x00085488       ;# EMCDynamicConfig0: Enable buffers
+    }
+
+    $_TARGETNAME configure -event gdb-attach {
+        # Without this gdb-attach will first time as probe will fail
+        reset init
+    }
+}
+
+# Enable the PLL.
+# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
+# Note: The PLL output runs at a frequency N times the desired CPU clock.
+#       It in unavoidable that the CPU clock drops down to (4 MHz/N) during
+#       the initialization!
+#       Here: N=4
+#       Note that if the PLL is already active at the time this script is
+#       called, the effective value of N is the value of CCLKCFG at that time!
+#
+proc enable_pll {} {
+    # Disconnect PLL in case it is already connected
+    if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} {
+        # Disconnect it, but leave it enabled
+        # (This MUST be done in two steps)
+        mww 0xE01FC080 0x00000001       ;# PLLCON: disconnect PLL
+        mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+        mww 0xE01FC08C 0x00000055       ;# PLLFEED
+    }
+    # Disable PLL (as it might already be enabled at this time!)
+    mww 0xE01FC080 0x00000000       ;# PLLCON: disable PLL
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+
+    # Setup PLL to generate 288 MHz from internal RC oscillator
+    mww 0xE01FC10C 0x00000000       ;# CLKSRCSEL: IRC
+    mww 0xE01FC084 0x00000023       ;# PLLCFG: N=1, M=36
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+    mww 0xE01FC080 0x00000001       ;# PLLCON: enable PLL
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+    sleep 100
+    mww 0xE01FC104 0x00000003       ;# CCLKCFG: divide by 4 (72 MHz)
+    mww 0xE01FC080 0x00000003       ;# PLLCON: connect PLL
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/emcraft_imx8m-som-bsb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/emcraft_imx8m-som-bsb.cfg
new file mode 100644
index 0000000..7b9f7b1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/emcraft_imx8m-som-bsb.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for Emcraft IMX8M-SOM-BSB
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# SRST and TRST are wired up
+reset_config trst_and_srst
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+# board has an i.MX8MQ with 4 Cortex-A53 cores
+set CHIPNAME imx8mq
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/emcraft_twr-vf6-som-bsb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/emcraft_twr-vf6-som-bsb.cfg
new file mode 100644
index 0000000..57efa8f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/emcraft_twr-vf6-som-bsb.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# EmCraft Systems TWR-VF6-SOM-BSB
+#
+# http://www.emcraft.com/products/259#twr-kit
+#
+
+source [find board/emcraft_vf6-som.cfg]
+
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/emcraft_vf6-som.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/emcraft_vf6-som.cfg
new file mode 100644
index 0000000..0a6f0f8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/emcraft_vf6-som.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# EmCraft Systems Vybrid VF6 SOM
+#
+# http://www.emcraft.com/products/259#som
+#
+
+set CHIPNAME vf610
+source [find target/vybrid_vf6xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-bridge.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-bridge.cfg
new file mode 100644
index 0000000..17146e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-bridge.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32 connected via ESP USB Bridge board
+#
+# For example, OpenOCD can be started for ESP32 debugging on
+#
+#   openocd -f board/esp32-bridge.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_bridge.cfg]
+# ESP32 chip id defined in the idf esp_chip_model_t
+espusbjtag chip_id 1
+# Source the ESP32 configuration file
+source [find target/esp32.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-ethernet-kit-3.3v.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-ethernet-kit-3.3v.cfg
new file mode 100644
index 0000000..3bfe84b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-ethernet-kit-3.3v.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-ETHERNET-KIT board.
+#
+# For example, OpenOCD can be started for ESP32 debugging on
+#
+#   openocd -f board/esp32-ethernet-kit-3.3v.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+set ESP32_FLASH_VOLTAGE 3.3
+# Source the ESP32 configuration file
+source [find target/esp32.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-wrover-kit-1.8v.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-wrover-kit-1.8v.cfg
new file mode 100644
index 0000000..9aa3954
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-wrover-kit-1.8v.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-WROVER-KIT board.
+#
+# For example, OpenOCD can be started for ESP32 debugging on
+#
+#   openocd -f board/esp32-wrover-kit-1.8v.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+set ESP32_FLASH_VOLTAGE 1.8
+# Source the ESP32 configuration file
+source [find target/esp32.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-wrover-kit-3.3v.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-wrover-kit-3.3v.cfg
new file mode 100644
index 0000000..ce62436
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32-wrover-kit-3.3v.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-WROVER-KIT board.
+#
+# For example, OpenOCD can be started for ESP32 debugging on
+#
+#   openocd -f board/esp32-wrover-kit-3.3v.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+set ESP32_FLASH_VOLTAGE 3.3
+# Source the ESP32 configuration file
+source [find target/esp32.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c2-ftdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c2-ftdi.cfg
new file mode 100644
index 0000000..bc2b82f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c2-ftdi.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C2 connected via ESP-Prog.
+#
+# For example, OpenOCD can be started for ESP32-C2 debugging on
+#
+#   openocd -f board/esp32c2-ftdi.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+# Source the ESP32-C2 configuration file
+source [find target/esp32c2.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c3-builtin.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c3-builtin.cfg
new file mode 100644
index 0000000..9e19b1b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c3-builtin.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C3 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-C3 debugging on
+#
+#   openocd -f board/esp32c3-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-C3 configuration file
+source [find target/esp32c3.cfg]
+
+adapter speed 40000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c3-ftdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c3-ftdi.cfg
new file mode 100644
index 0000000..5595374
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c3-ftdi.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C3 connected via ESP-Prog.
+#
+# For example, OpenOCD can be started for ESP32-C3 debugging on
+#
+#   openocd -f board/esp32c3-ftdi.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+# Source the ESP32-C3 configuration file
+source [find target/esp32c3.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c6-builtin.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c6-builtin.cfg
new file mode 100644
index 0000000..abc96b2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32c6-builtin.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C6 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-C6 debugging on
+#
+#   openocd -f board/esp32c6-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-C6 configuration file
+source [find target/esp32c6.cfg]
+
+adapter speed 40000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32h2-builtin.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32h2-builtin.cfg
new file mode 100644
index 0000000..1ce5961
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32h2-builtin.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C3 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-C3 debugging on
+#
+#   openocd -f board/esp32c3-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-C3 configuration file
+source [find target/esp32h2.cfg]
+
+adapter speed 40000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s2-bridge.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s2-bridge.cfg
new file mode 100644
index 0000000..b87be8b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s2-bridge.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S2 connected via ESP USB Bridge board
+#
+# For example, OpenOCD can be started for ESP32-S2 debugging on
+#
+#   openocd -f board/esp32s2-bridge.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_bridge.cfg]
+# ESP32S2 chip id defined in the idf esp_chip_model_t
+espusbjtag chip_id 2
+# Source the ESP32-S2 configuration file
+source [find target/esp32s2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s2-kaluga-1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s2-kaluga-1.cfg
new file mode 100644
index 0000000..783ea21
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s2-kaluga-1.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S2 Kaluga board.
+#
+# For example, OpenOCD can be started for ESP32-S2 debugging on
+#
+#   openocd -f board/esp32s2-kaluga-1.cfg
+#
+
+source [find interface/ftdi/esp32s2_kaluga_v1.cfg]
+source [find target/esp32s2.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+# On ESP32-S2, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s3-bridge.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s3-bridge.cfg
new file mode 100644
index 0000000..a42e257
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s3-bridge.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S3 connected via ESP USB Bridge board
+#
+# For example, OpenOCD can be started for ESP32-S3 debugging on
+#
+#   openocd -f board/esp32s3-bridge.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_bridge.cfg]
+# ESP32S3 chip id defined in the idf esp_chip_model_t
+espusbjtag chip_id 9
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s3-builtin.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s3-builtin.cfg
new file mode 100644
index 0000000..353099c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s3-builtin.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S3 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-S3 debugging on
+#
+#   openocd -f board/esp32s3-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
+
+adapter speed 40000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s3-ftdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s3-ftdi.cfg
new file mode 100644
index 0000000..6070664
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/esp32s3-ftdi.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S3 connected via ESP-Prog.
+#
+# For example, OpenOCD can be started for ESP32-S3 debugging on
+#
+#   openocd -f board/esp32s3-ftdi.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ethernut3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ethernut3.cfg
new file mode 100644
index 0000000..384db1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ethernut3.cfg
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Ethernut 3 board configuration file
+#
+# http://www.ethernut.de/en/hardware/enut3/
+
+
+# AT91R40008-66AU ARM7TDMI Microcontroller
+# 256kB internal RAM
+source [find target/at91r40008.cfg]
+
+
+# AT49BV322A-70TU NOR Flash
+# 2M x 16 mode at address 0x10000000
+# Common flash interface supported
+#
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
+
+
+# Micrel MIC2775-29YM5 Supervisor
+# Reset output will remain active for 280ms (maximum)
+#
+adapter srst delay 300
+jtag_ntrst_delay 300
+
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+adapter speed 16000
+
+
+# Target events
+#
+$_TARGETNAME configure -event reset-init { board_init }
+
+# Initialize board hardware
+#
+proc board_init { } {
+	board_remap
+	flash probe 0
+}
+
+# Memory remap
+#
+proc board_remap {{VERBOSE 0}} {
+	# CS0: NOR flash
+	#      16MB @ 0x10000000
+	#      16-bit data bus
+	#      4 wait states
+	#
+	mww 0xffe00000 0x1000212d
+
+	# CS1: Ethernet controller
+	#      1MB @ 0x20000000
+	#      16-bit data bus
+	#      2 wait states
+	#      Byte select access
+	#
+	mww 0xffe00004 0x20003025
+
+	# CS2: CPLD registers
+	#      1MB @ 0x21000000
+	#      8-bit data bus
+	#      2 wait states
+	#
+	mww 0xffe00008 0x21002026
+
+	# CS3: Expansion bus
+	#      1MB @ 0x22000000
+	#      8-bit data bus
+	#      8 wait states
+	#
+	mww 0xffe00010 0x22002e3e
+
+	# Remap command
+	#
+	mww 0xffe00020 0x00000001
+
+	if {$VERBOSE != 0} {
+		echo "0x00000000 RAM"
+		echo "0x10000000 Flash"
+		echo "0x20000000 Ethernet"
+		echo "0x21000000 CPLD"
+		echo "0x22000000 Expansion"
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/evb-lan9255.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/evb-lan9255.cfg
new file mode 100644
index 0000000..3fd6f60
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/evb-lan9255.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip LAN9255 evaluation board
+# https://www.microchip.com/en-us/development-tool/EV25Y25A
+#
+
+set CHIPNAME same53
+
+source [find target/atsame5x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/frdm-kl25z.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/frdm-kl25z.cfg
new file mode 100644
index 0000000..68dc48d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/frdm-kl25z.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an Freescale Freedom eval board with a single MKL25Z128VLK4 chip.
+# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL25Z
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# increase working area to 16KB
+set WORKAREASIZE 0x4000
+
+# chip name
+set CHIPNAME MKL25Z128VLK4
+
+reset_config srst_only
+
+source [find target/kl25.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/frdm-kl46z.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/frdm-kl46z.cfg
new file mode 100644
index 0000000..3fb7205
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/frdm-kl46z.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an Freescale Freedom eval board with a single MKL46Z256VLL4 chip.
+# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL46Z
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# increase working area to 16KB
+set WORKAREASIZE 0x4000
+
+# chip name
+set CHIPNAME MKL46Z256VLL4
+
+reset_config srst_only
+
+source [find target/kl46.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/fsl_imx6q_sabresd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/fsl_imx6q_sabresd.cfg
new file mode 100644
index 0000000..faeeafb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/fsl_imx6q_sabresd.cfg
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration file for the Freescale IMX6Q Sabre SD EVM
+#
+# This board does not have an embedded JTAG adapter, you must source
+# a suitable adapter configuration before sourcing this file.
+
+# Sabre SD has a standard ARM-20 JTAG connector with
+# nTRST and nSRST available.
+reset_config trst_and_srst
+
+# the only possible transport is JTAG
+transport select jtag
+
+# iMX6Q POR gates JTAG and the chip is completely incommunicado
+# over JTAG for at least 10ms after nSRST is deasserted
+adapter srst delay 11
+
+# Source generic iMX6Q target configuration
+set CHIPNAME imx6q
+source [find target/imx6.cfg]
+
+# function to apply initial configuration after a reset. It
+# provides a basic pad configuration and also DDR memory and clocks
+# sufficient to load and execute a boot loader (e.g. barebox) from
+# DDR memory. This list is extracted from the barebox flash image
+# header.
+proc apply_dcd { } {
+	mww 0x020e05a8 0x00000030
+	mww 0x020e05b0 0x00000030
+	mww 0x020e0524 0x00000030
+	mww 0x020e051c 0x00000030
+	mww 0x020e0518 0x00000030
+	mww 0x020e050c 0x00000030
+	mww 0x020e05b8 0x00000030
+	mww 0x020e05c0 0x00000030
+	mww 0x020e05ac 0x00020030
+	mww 0x020e05b4 0x00020030
+	mww 0x020e0528 0x00020030
+	mww 0x020e0520 0x00020030
+	mww 0x020e0514 0x00020030
+	mww 0x020e0510 0x00020030
+	mww 0x020e05bc 0x00020030
+	mww 0x020e05c4 0x00020030
+	mww 0x020e056c 0x00020030
+	mww 0x020e0578 0x00020030
+	mww 0x020e0588 0x00020030
+	mww 0x020e0594 0x00020030
+	mww 0x020e057c 0x00020030
+	mww 0x020e0590 0x00003000
+	mww 0x020e0598 0x00003000
+	mww 0x020e058c 0x00000000
+	mww 0x020e059c 0x00003030
+	mww 0x020e05a0 0x00003030
+	mww 0x020e0784 0x00000030
+	mww 0x020e0788 0x00000030
+	mww 0x020e0794 0x00000030
+	mww 0x020e079c 0x00000030
+	mww 0x020e07a0 0x00000030
+	mww 0x020e07a4 0x00000030
+	mww 0x020e07a8 0x00000030
+	mww 0x020e0748 0x00000030
+	mww 0x020e074c 0x00000030
+	mww 0x020e0750 0x00020000
+	mww 0x020e0758 0x00000000
+	mww 0x020e0774 0x00020000
+	mww 0x020e078c 0x00000030
+	mww 0x020e0798 0x000c0000
+	mww 0x021b081c 0x33333333
+	mww 0x021b0820 0x33333333
+	mww 0x021b0824 0x33333333
+	mww 0x021b0828 0x33333333
+	mww 0x021b481c 0x33333333
+	mww 0x021b4820 0x33333333
+	mww 0x021b4824 0x33333333
+	mww 0x021b4828 0x33333333
+	mww 0x021b0018 0x00081740
+	mww 0x021b001c 0x00008000
+	mww 0x021b000c 0x555a7975
+	mww 0x021b0010 0xff538e64
+	mww 0x021b0014 0x01ff00db
+	mww 0x021b002c 0x000026d2
+	mww 0x021b0030 0x005b0e21
+	mww 0x021b0008 0x09444040
+	mww 0x021b0004 0x00025576
+	mww 0x021b0040 0x00000027
+	mww 0x021b0000 0x831a0000
+	mww 0x021b001c 0x04088032
+	mww 0x021b001c 0x0408803a
+	mww 0x021b001c 0x00008033
+	mww 0x021b001c 0x0000803b
+	mww 0x021b001c 0x00428031
+	mww 0x021b001c 0x00428039
+	mww 0x021b001c 0x09408030
+	mww 0x021b001c 0x09408038
+	mww 0x021b001c 0x04008040
+	mww 0x021b001c 0x04008048
+	mww 0x021b0800 0xa1380003
+	mww 0x021b4800 0xa1380003
+	mww 0x021b0020 0x00005800
+	mww 0x021b0818 0x00022227
+	mww 0x021b4818 0x00022227
+	mww 0x021b083c 0x434b0350
+	mww 0x021b0840 0x034c0359
+	mww 0x021b483c 0x434b0350
+	mww 0x021b4840 0x03650348
+	mww 0x021b0848 0x4436383b
+	mww 0x021b4848 0x39393341
+	mww 0x021b0850 0x35373933
+	mww 0x021b4850 0x48254A36
+	mww 0x021b080c 0x001f001f
+	mww 0x021b0810 0x001f001f
+	mww 0x021b480c 0x00440044
+	mww 0x021b4810 0x00440044
+	mww 0x021b08b8 0x00000800
+	mww 0x021b48b8 0x00000800
+	mww 0x021b001c 0x00000000
+	mww 0x021b0404 0x00011006
+	mww 0x020c4068 0x00c03f3f
+	mww 0x020c406c 0x0030fc03
+	mww 0x020c4070 0x0fffc000
+	mww 0x020c4074 0x3ff00000
+	mww 0x020c4078 0x00fff300
+	mww 0x020c407c 0x0f0000c3
+	mww 0x020c4080 0x000003ff
+	mww 0x020e0010 0xf00000cf
+	mww 0x020e0018 0x007f007f
+	mww 0x020e001c 0x007f007f
+}
+
+# disable watchdog
+proc disable_wdog { } {
+	mwh 0x020bc000 0x30
+}
+
+# This function applies the initial configuration after a "reset init"
+# command
+proc imx6q_sabresd_init { } {
+	disable_wdog
+	apply_dcd
+}
+
+# prevent cortex-a code from asserting SRST again
+$_TARGETNAME.0 configure -event reset-assert { }
+# hook the init function into the reset-init event
+$_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init }
+# set a slow default JTAG clock, can be overridden later
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gatemate_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gatemate_eval.cfg
new file mode 100644
index 0000000..c4d3f3d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gatemate_eval.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# GateMateTM FPGA Evaluation Board
+# https://www.colognechip.com/programmable-logic/gatemate-evaluation-board/
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0014 0x011b
+reset_config none
+transport select jtag
+adapter speed 6000
+
+source [find fpga/gatemate.cfg]
+
+set JTAGSPI_CHAIN_ID gatemate.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init gatemate.pld "" -1
+#jtagspi_program workspace/blink/blink_slow.cfg.bit 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/glyn_tonga2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/glyn_tonga2.cfg
new file mode 100644
index 0000000..d847bec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/glyn_tonga2.cfg
@@ -0,0 +1,201 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9)
+#
+# http://toshiba-mikrocontroller.de/sites/TMPA900CPUBOARDStarter.htm
+#
+# Hardware on the S0-DIMM module:
+#   - Toshiba TMPA900CMXBG (ARM9, ARM926EJ-S, max. 200MHz)
+#   - DDR SDRAM: Hynix H5MS5162DFR-J3M (64Mbyte, x16, 1.8V, 166/83MHz at CL3/2)
+#   - NAND flash: Samsung K9F2G08U0B-PIB0 (256M x 8 Bit, 3.3V)
+#   - Ethernet: SMSC LAN9221I-ABZJ (10/100Mbit, Non-PCI, 16 bit interface)
+#
+
+source [find target/tmpa900.cfg]
+
+########################
+# Target configuration #
+########################
+
+# Initial JTAG speed should not exceed 1/6 of the initial CPU clock
+# frequency (24MHz). Be conservative and use 1/8 of the frequency.
+# (24MHz / 8 = 3MHz)
+adapter speed 3000
+
+$_TARGETNAME configure -event reset-start {
+	# Upon reset, set the JTAG frequency to 3MHz again, see above.
+	echo "Setting JTAG speed to 3MHz until clocks are initialized."
+	adapter speed 3000
+
+	# Halt the CPU.
+	halt
+
+	# Disable faster memory access for now.
+	arm7_9 fast_memory_access disable
+}
+
+$_TARGETNAME configure -event reset-init {
+	# Setup clocks, and initialize SRAM and DDR SDRAM.
+	tonga2_init
+
+	# At this point the CPU is running at 192MHz, increase JTAG speed.
+	# Tests showed that 15MHz works OK, higher speeds can cause problems,
+	# though. Not sure if this is a CPU issue or JTAG adapter issue.
+	echo "Increasing JTAG speed to 15MHz."
+	adapter speed 15000
+
+	# Enable faster memory access.
+	arm7_9 fast_memory_access enable
+}
+
+proc tonga2_init { } {
+	######################
+	# PLL initialization #
+	######################
+
+	# Clock overview (see datasheet chapter 3.5.2, page 57):
+	#   - fs: Low-frequency oscillator
+	#   - fOSCH: High-frequency oscillator (24MHz on this board)
+	#   - fPLL = fOSCH * multiplier (where multiplier can be 6 or 8)
+	#   - fFCLK = fPLL / gear (where gear can be 1/2/4/8)
+	#   - fHCLK is always fFCLK/2. fPCLK is also fFCLK/2.
+	#
+	# We select multiplier = 8 and gear = 1, so
+	#   fFCLK = fOSCH * 8 / 1 = 192MHz.
+
+	# SYSCR3 (System Control Register 3): Disable and configure PLL.
+	#   - PLL operation control: off
+	#   - PLL constant value setting 1: always 0, as per datasheet
+	#   - PLL constant value setting 2: x8 (multiplier = 8)
+	mww 0xf005000c 0x00000007
+
+	# SYSCR4 (System Control Register 4): Configure PLL.
+	#   - PLL constant value setting 3: 140MHz or more
+	#   - PLL constant value setting 4: always 1, as per datasheet
+	#   - PLL constant value setting 5: 140MHz or more
+	mww 0xf0050010 0x00000065
+
+	# SYSCR3 (System Control Register 3): Enable PLL.
+	#   - PLL operation control: on
+	#   - All other bits remain set as above.
+	mww 0xf005000c 0x00000087
+
+	# Wait for PLL to stabilize.
+	sleep 10
+
+	# SYSCR2 (System Control Register 2): Switch from fOSCH to fPLL.
+	#   - Selection of the PLL output clock: fPLL
+	mww 0xf0050008 0x00000002
+
+	# SYSCR1 (System Control Register 1):
+	#   - Clock gear programming: fc/1 (i.e., gear = 1, don't divide).
+	mww 0xf0050004 0x00000000
+
+	# CLKCR5 (Clock Control Register 5): Set bits 3 and 6. The datasheet
+	# says the bits are reserved, but also recommends "Write as one".
+	mww 0xf0050054 0x00000048
+
+
+	##############################################################
+	# Dynamic Memory Controller (DMC) / DDR SDRAM initialization #
+	##############################################################
+
+	# PMC (Power Management Controller):
+	# PMCDRV (External Port "Driverbility" control register):
+	# Bits DRV_MEM0/DRV_MEM1 (memory relation port drive power):
+	mww 0xf0020260 0x00000003	;# Select 1.8V +/- 0.1V
+
+	# Setup DDR SDRAM timing parameters for our specific chip.
+	mww 0xf4310014 0x00000004	;# cas_latency = 2
+	mww 0xf4310018 0x00000001	;# t_dqss = 1
+	mww 0xf431001c 0x00000002	;# t_mrd = 2
+	mww 0xf4310020 0x0000000a	;# t_ras = 10
+	mww 0xf4310024 0x0000000a	;# t_rc = 10
+	mww 0xf4310028 0x00000013	;# t_rcd = 3, schedule_rcd = 2
+	mww 0xf431002c 0x0000010a	;# t_rfc = 10, schedule_rfc = 8
+	mww 0xf4310030 0x00000013	;# t_rp = 3, schedule_rp = 2
+	mww 0xf4310034 0x00000002	;# t_rrd = 2
+	mww 0xf4310038 0x00000002	;# t_wr = 2
+	mww 0xf431003c 0x00000001	;# t_wtr = 1
+	mww 0xf4310040 0x0000000a	;# t_xp = 10
+	mww 0xf4310044 0x0000000c	;# t_xsr = 12
+	mww 0xf4310048 0x00000014	;# t_esr = 20
+
+	# dmc_memory_cfg_5 (DMC Memory Configuration register):
+	# Set memory configuration:
+	# column_bits = 10, row_bits = 13, ap-bit = 10, power_down_prd = 0,
+	# auto_power_down = disable, stop_mem_clock = disable, memory_burst = 4
+	mww 0xf431000c 0x00010012
+
+	# dmc_user_config_5 (DMC user_config register):
+	# Data bus width of DDR SDRAM: 16 bit
+	mww 0xf4310304 0x00000058
+
+	# dmc_refresh_prd_5 (DMC Refresh Period register):
+	# Auto refresh: every 2656 (0xa60) DMCSCLK periods.
+	mww 0xf4310010 0x00000a60
+
+	# dmc_chip_0_cfg_5 (DMC chip_0_cfg registers):
+	#   - SDRAM address structure: bank, row, column
+	#   - address_match = 01000000 (start address [31:24])
+	#   - address_mask  = 11111100 (start address [31:24] mask value)
+	mww 0xf4310200 0x000140fc
+
+	# Initialize the DDR SDRAM chip.
+	# dmc_direct_cmd_5 (DMC Direct Command register).
+	# See datasheet chapter 3.10.5.1, page 268.
+	mww 0xf4310008 0x000c0000	;# RAM init: NOP
+	mww 0xf4310008 0x00000000	;# RAM init: Precharge all
+	mww 0xf4310008 0x00040000	;# RAM init: Autorefresh
+	mww 0xf4310008 0x00040000	;# RAM init: Autorefresh
+	mww 0xf4310008 0x00080032	;# RAM init: addr_13_to_0 = 0x32
+	mww 0xf4310008 0x000c0000	;# RAM init: NOP
+	mww 0xf4310008 0x000a0000	;# RAM init: bank_addr = bank 2
+
+	# dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg registers):
+	# Set min./max. QoS values.
+	#   - 0x5: Enable QoS, max. QoS = 1
+	#   - 0xb: Enable QoS, min. QoS = 2
+	mww 0xf4310100 0x00000005	;# AHB0: CPU Data
+	mww 0xf4310104 0x00000005	;# AHB1: CPU Inst
+	mww 0xf4310108 0x0000000b	;# AHB2: LCDC
+	mww 0xf431010c 0x00000005	;# AHB3: LCDDA, USB
+	mww 0xf4310110 0x00000005	;# AHB4: DMA1
+	mww 0xf4310114 0x00000005	;# AHB5: DMA2
+
+	# dmc_memc_cmd_5 (DMC Memory Controller Command register):
+	# Change DMC state to ready.
+	mww 0xf4310004 0x00000000	;# memc_cmd = "Go"
+
+	# EBI: SMC Timeout register
+	mww 0xf00a0050 0x00000001	;# smc_timeout = 1
+
+
+	########################################################
+	# Static Memory Controller (SMC) / SRAM initialization #
+	########################################################
+
+	# smc_set_cycles_5 (SMC Set Cycles register):
+	# tRC = 10, tWC = 10, tCEOE = 7, tWP = 5, tPC=2, tTR=2
+	mww 0xf4311014 0x0004afaa
+
+	# smc_set_opmode_5 (SMC Set Opmode register):
+	# Memory data bus width = 16 bits, async read mode, read burst
+	# length = 1 beat, async write mode, write burst length = 1 beat,
+	# byte enable (SMCBE0-1) timing = SMCCSn timing, memory burst boundary
+	# split setting = burst can cross any address boundary
+	mww 0xf4311018 0x00000001
+
+	# smc_direct_cmd_5 (SMC Direct Command register):
+	# cmd_type = UpdateRegs, chip_select = CS1
+	mww 0xf4311010 0x00c00000
+
+	echo "Clocks, SRAM, and DDR SDRAM are now initialized."
+}
+
+#######################
+# Flash configuration #
+#######################
+
+# TODO: Implement NAND support.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gowin_runber.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gowin_runber.cfg
new file mode 100644
index 0000000..6cb0736
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gowin_runber.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Gowin RUNBER FPGA Development Board
+# https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+reset_config none
+transport select jtag
+adapter speed 6000
+
+source [find fpga/gowin_gw1n.cfg]
+
+
+#openocd -f board/gowin_runber.cfg  -c "init" -c "pld load 0 impl/pnr/gw1n_blinker.fs"
+#ipdbg create-hub gw1n.ipdbghub -tap gw1n.tap -ir 0x42
+#gw1n.ipdbghubipdbg start  -tool 0 -port 5555
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gti/espressobin.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gti/espressobin.cfg
new file mode 100644
index 0000000..d1492df
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gti/espressobin.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# config for ESPRESSObin from
+# Globalscale Technologies Inc.
+
+# srst is isolated through missing resistor
+reset_config trst_only
+
+source [find target/marvell/88f3720.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gumstix-aerocore.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gumstix-aerocore.cfg
new file mode 100644
index 0000000..ddadc88
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/gumstix-aerocore.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# JTAG for the STM32F4x chip used on the Gumstix AeroCore is available on
+# the first interface of a Quad FTDI chip.  nTRST is bit 4.
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6011
+
+ftdi layout_init 0x0000 0x001b
+ftdi layout_signal nTRST -data 0x0010
+
+source [find target/stm32f4x.cfg]
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hammer.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hammer.cfg
new file mode 100644
index 0000000..79d58ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hammer.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
+# http://www.tincantools.com
+
+source [find target/samsung_s3c2410.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	# Reset Script for the TinCanTools S3C2410 Based Hammer Module
+	# http://www.tincantools.com
+	#
+	# Setup primary clocks and initialize the SDRAM
+	mww 0x53000000 0x00000000
+	mww 0x4a000008 0xffffffff
+	mww 0x4a00000c 0x000007ff
+	mww 0x4c000000 0x00ffffff
+	mww 0x4c000014 0x00000003
+	mww 0x4c000004 0x000a1031
+	mww 0x48000000 0x11111122
+	mww 0x48000004 0x00000700
+	mww 0x48000008 0x00000700
+	mww 0x4800000c 0x00000700
+	mww 0x48000010 0x00000700
+	mww 0x48000014 0x00000700
+	mww 0x48000018 0x00000700
+	mww 0x4800001c 0x00018005
+	mww 0x48000020 0x00018005
+	mww 0x48000024 0x009c0459
+	mww 0x48000028 0x000000b2
+	mww 0x4800002c 0x00000030
+	mww 0x48000030 0x00000030
+	flash probe 0
+}
+
+
+#flash configuration
+#flash bank        [driver_options ...]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x1000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxdb500sys.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxdb500sys.cfg
new file mode 100644
index 0000000..68e1cda
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxdb500sys.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for paired K4S561632C (64MB) "
+  mww 0x00100140 0
+  mww 0x00100144 0x03C13261
+  mww 0x00100140 0x030D0121
+
+  puts "Configuring SRAM nCS0 for 150ns paired Par. Flash (x32)"
+  mww 0x00100100 0x0201000E
+
+  flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+flash bank parflash cfi 0xC0000000 0x02000000 4 4 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxeb500hmi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxeb500hmi.cfg
new file mode 100644
index 0000000..a814365
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxeb500hmi.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads disable
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for MT48LC8M32 (32MB) "
+  mww 0x00100140 0
+  mww 0x00100144 0x03C23251
+  mww 0x00100140 0x030D0111
+
+  puts "Configuring SRAM nCS0 for 150ns Par. Flash (x16)"
+  mww 0x00100100 0x0101000E
+
+  flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxhx10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxhx10.cfg
new file mode 100644
index 0000000..e116a6c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxhx10.cfg
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx10.cfg]
+
+# Usually it is not needed to set srst_pulls_trst
+# but sometimes it does not work without it. If you encounter
+# problems try to line below
+# reset_config trst_and_srst srst_pulls_trst
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
+
+# Par. Flash can only be accessed if DIP switch on the board is set in proper
+# position and init_sdrambus was called. Don't call these functions if the DIP
+# switch is in invalid position, as some outputs may collide. This is why this
+# function is not called automatically
+proc flash_init { } {
+  puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+  mww 0x101C0100 0x01010008
+
+  flash probe 0
+}
+
+proc mread32 {addr} {
+  return [read_memory $addr 32 1]
+}
+
+proc init_clocks { } {
+  puts "Enabling all clocks "
+  set accesskey [mread32 0x101c0070]
+  mww  0x101c0070 $accesskey
+
+  mww  0x101c0028 0x00007511
+}
+
+proc init_sdrambus { } {
+  puts "Initializing external SDRAM Bus 16 Bit "
+  set accesskey [mread32 0x101c0070]
+  mww  0x101c0070 $accesskey
+  mww  0x101c0C40 0x00000050
+
+  puts "Configuring SDRAM controller for K4S561632E (32MB) "
+  mww 0x101C0140 0
+  sleep 100
+  #mww 0x101C0144 0x00a13262
+  mww 0x101C0144 0x00a13251
+  mww 0x101C0148 0x00000033
+  mww 0x101C0140 0x030d0121
+}
+
+$_TARGETNAME configure -event reset-init {
+  halt
+  wait_halt 1000
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  init_clocks
+#  init_sdrambus
+
+  puts ""
+  puts "-------------------------------------------------"
+  puts "Call 'init_clocks' to enable all clocks"
+  puts "Call 'init_sdrambus' to enable external SDRAM bus"
+  puts "-------------------------------------------------"
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxhx50.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxhx50.cfg
new file mode 100644
index 0000000..8aef6ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxhx50.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx50.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
+  mww 0x1C000140 0
+  mww 0x1C000144 0x00A12151
+  mww 0x1C000140 0x030D0001
+
+  puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+  mww 0x1C000100 0x01010008
+
+  flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxhx500.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxhx500.cfg
new file mode 100644
index 0000000..9ddf657
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxhx500.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  sleep 100
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
+  mww 0x00100140 0
+  mww 0x00100144 0x03C23251
+  mww 0x00100140 0x030D0001
+
+  puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+  mww 0x00100100 0x01010008
+
+  flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxsb100.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxsb100.cfg
new file mode 100644
index 0000000..b59ea17
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hilscher_nxsb100.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
+  mww 0x00100140 0
+  mww 0x00100144 0x03C23251
+  mww 0x00100140 0x030D0001
+
+}
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_lpc1768stick.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_lpc1768stick.cfg
new file mode 100644
index 0000000..52cf370
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_lpc1768stick.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hitex LPC1768 Stick
+#
+# http://www.hitex.com/?id=1602
+#
+
+reset_config trst_and_srst
+
+source [find interface/ftdi/hitex_lpc1768stick.cfg]
+
+source [find target/lpc17xx.cfg]
+
+
+# startup @ 500kHz
+adapter speed 500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_lpc2929.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_lpc2929.cfg
new file mode 100644
index 0000000..35007c0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_lpc2929.cfg
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hitex eval board for LPC2929/LPC2939
+# http://www.hitex.com/
+
+# Delays on reset lines
+adapter srst delay 50
+jtag_ntrst_delay 1
+
+# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
+# Adaptive clocking through RTCK is not supported.
+adapter speed 2000
+
+# Target device: LPC29xx with ETB
+# The following variables are used by the LPC2900 script:
+#   HAS_ETB             Must be set to 1. The CPU on this board has ETB.
+#   FLASH_CLOCK         CPU frequency at the time of flash programming (in kHz)
+set HAS_ETB             1
+set FLASH_CLOCK         112000
+source [find target/lpc2900.cfg]
+
+# A working area will help speeding the flash programming
+#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0
+$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0
+
+# Event handlers
+$_TARGETNAME configure -event reset-start {
+  # Back to the slow JTAG clock
+  adapter speed 2000
+}
+
+# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
+set _FLASHNAME $_CHIPNAME.extflash
+flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
+
+
+$_TARGETNAME configure -event reset-init {
+  # Flash
+  mww 0x20200010 0x00000007     ;# FBWST: 7 wait states, not cached
+
+  # Use PLL
+  mww 0xFFFF8020 0x00000001     ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
+  mww 0xFFFF8070 0x01000000     ;# SYS_CLK_CONF: Crystal
+  mww 0xFFFF8028 0x00000005     ;# PLL: (power down)
+  mww 0xFFFF8028 0x01060004     ;# PLL: M=7, 2P=2 (power up)
+                                 # --> f=112 MHz, fcco=224 MHz
+  sleep 100
+  mww 0xFFFF8070 0x02000000     ;# SYS_CLK_CONF: PLL
+
+  # Increase JTAG speed
+  adapter speed 6000
+
+  # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
+  mww 0xE0001138 0x0000001F     ;# P1.14 = D0
+  mww 0xE000113C 0x0000001F     ;# P1.15 = D1
+  mww 0xE0001140 0x0000001F     ;# P1.16 = D2
+  mww 0xE0001144 0x0000001F     ;# P1.17 = D3
+  mww 0xE0001148 0x0000001F     ;# P1.18 = D4
+  mww 0xE000114C 0x0000001F     ;# P1.19 = D5
+  mww 0xE0001150 0x0000001F     ;# P1.20 = D6
+  mww 0xE0001154 0x0000001F     ;# P1.21 = D7
+  mww 0xE0001200 0x0000001F     ;# P2.0  = D8
+  mww 0xE0001204 0x0000001F     ;# P2.1  = D9
+  mww 0xE0001208 0x0000001F     ;# P2.2  = D10
+  mww 0xE000120C 0x0000001F     ;# P2.3  = D11
+  mww 0xE0001210 0x0000001F     ;# P2.4  = D12
+  mww 0xE0001214 0x0000001F     ;# P2.5  = D13
+  mww 0xE0001218 0x0000001F     ;# P2.6  = D14
+  mww 0xE000121C 0x0000001F     ;# P2.7  = D15
+  mww 0xE0001104 0x00000007     ;# P1.1  = A1
+  mww 0xE0001108 0x00000007     ;# P1.2  = A2
+  mww 0xE000110C 0x00000007     ;# P1.3  = A3
+  mww 0xE0001110 0x00000007     ;# P1.4  = A4
+  mww 0xE0001114 0x00000007     ;# P1.5  = A5
+  mww 0xE0001118 0x00000007     ;# P1.6  = A6
+  mww 0xE000111C 0x00000007     ;# P1.7  = A7
+  mww 0xE0001028 0x00000007     ;# P0.10 = A8
+  mww 0xE000102C 0x00000007     ;# P0.11 = A9
+  mww 0xE0001030 0x00000007     ;# P0.12 = A10
+  mww 0xE0001034 0x00000007     ;# P0.13 = A11
+  mww 0xE0001038 0x00000007     ;# P0.14 = A12
+  mww 0xE000103C 0x00000007     ;# P0.15 = A13
+  mww 0xE0001048 0x00000007     ;# P0.18 = A14
+  mww 0xE000104C 0x00000007     ;# P0.19 = A15
+  mww 0xE0001050 0x00000007     ;# P0.20 = A16
+  mww 0xE0001054 0x00000007     ;# P0.21 = A17
+  mww 0xE0001058 0x00000007     ;# P0.22 = A18
+  mww 0xE000105C 0x00000007     ;# P0.23 = A19
+  mww 0xE0001238 0x00000007     ;# P2.14 = BLS0
+  mww 0xE000123C 0x00000007     ;# P2.15 = BLS1
+  mww 0xE0001300 0x00000007     ;# P3.0  = CS6
+  mww 0xE0001304 0x00000007     ;# P3.1  = CS7
+  mww 0xE0001130 0x00000007     ;# P1.12 = OE_N
+  mww 0xE0001134 0x00000007     ;# P1.13 = WE_N
+  mww 0x600000BC 0x00000041     ;# Bank6 16-bit mode, RBLE=1
+  mww 0x600000B4 0x00000000     ;# Bank6 WSTOEN=0
+  mww 0x600000AC 0x00000005     ;# Bank6 WST1=5
+  mww 0x600000B8 0x00000001     ;# Bank6 WSTWEN=1
+  mww 0x600000B0 0x00000006     ;# Bank6 WST2=6
+  mww 0x600000A8 0x00000002     ;# Bank6 IDCY=2
+  mww 0x600000D8 0x00000041     ;# Bank7 16-bit mode, RBLE=1
+  mww 0x600000D0 0x00000000     ;# Bank7 WSTOEN=0
+  mww 0x600000C8 0x0000000A     ;# Bank7 WST1=10
+  mww 0x600000D4 0x00000001     ;# Bank7 WSTWEN=1
+  mww 0x600000CC 0x0000000C     ;# Bank7 WST2=8
+  mww 0x600000C4 0x00000002     ;# Bank7 IDCY=2
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_stm32-performancestick.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_stm32-performancestick.cfg
new file mode 100644
index 0000000..bab5964
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_stm32-performancestick.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hitex stm32 performance stick
+
+reset_config trst_and_srst
+
+source [find interface/ftdi/stm32-stick.cfg]
+
+set  CHIPNAME stm32_hitex
+source [find target/stm32f1x.cfg]
+
+# configure str750 connected to jtag chain
+# FIXME -- source [find target/str750.cfg] after cleaning that up
+jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041
+
+# for some reason this board like to startup @ 500kHz
+adapter speed 500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_str9-comstick.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_str9-comstick.cfg
new file mode 100644
index 0000000..a508046
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/hitex_str9-comstick.cfg
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hitex STR9-comStick
+# http://www.hitex.com/index.php?id=383
+# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
+
+source [find interface/ftdi/hitex_str9-comstick.cfg]
+
+# set jtag speed
+adapter speed 3000
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#
+# FIXME use the standard str912 target config; that script might need
+# updating to "-ignore-version" for the boundary scan TAP
+#
+#	source [find target/str912.cfg]
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists FLASHTAPID] } {
+   set _FLASHTAPID $FLASHTAPID
+} else {
+   set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+   # Found on STR9-comStick, revision STR912CS-A1
+   set _BSTAPID1 0x1457f041
+   # Found on STR9-comStick, revision STR912CS-A2
+   set _BSTAPID2 0x2457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	#jtag_rclk 3000
+
+	# -- Enable 96K RAM
+	# PFQBC enabled / DTCM & AHB wait-states disabled
+	mww 0x5C002034 0x0191
+
+	str9x flash_config 0 4 2 0 0x80000
+	flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+
+#flash bank     
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/iar_lpc1768.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/iar_lpc1768.cfg
new file mode 100644
index 0000000..d8d669e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/iar_lpc1768.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Board from IAR KickStart Kit for LPC1768
+# See www.iar.com and also
+# http://www.olimex.com/dev/lpc-1766stk.html
+#
+
+source [find target/lpc17xx.cfg]
+
+# The chip has just been reset.
+#
+$_TARGETNAME configure -event reset-init {
+	# FIXME update the core clock to run at 100 MHz;
+	# and update JTAG clocking similarly; then
+	# make CCLK match,
+
+	flash probe 0
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/iar_str912_sk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/iar_str912_sk.cfg
new file mode 100644
index 0000000..d94c0ce
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/iar_str912_sk.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IAR str912-sk evaluation kick start board has an str912
+
+source [find target/str912.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/icnova_imx53_sodimm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/icnova_imx53_sodimm.cfg
new file mode 100644
index 0000000..c4e8bde
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/icnova_imx53_sodimm.cfg
@@ -0,0 +1,450 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#################################################################################################
+# Author: Benjamin Tietz                                         ;#
+# based on work from: Wjatscheslaw Stoljarski (Slawa)    ;#
+# Kiwigrid GmbH                                                                                ;#
+# Generated for In-Circuit i.MX53 SO-Dimm                                                      ;#
+#################################################################################################
+
+# The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip
+source [find target/imx53.cfg]
+# Helper for common memory read/modify/write procedures
+source [find mem_helper.tcl]
+
+echo "i.MX53 SO-Dimm board lodaded."
+
+# Set reset type
+#reset_config srst_only
+
+adapter speed 3000
+
+# Slow speed to be sure it will work
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+
+$_TARGETNAME configure -event "reset-assert" {
+	echo "Resetting ...."
+	#cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-init { sodimm_init }
+
+global AIPS1_BASE_ADDR
+set AIPS1_BASE_ADDR     0x53F00000
+global AIPS2_BASE_ADDR
+set AIPS2_BASE_ADDR     0x63F00000
+
+proc sodimm_init { } {
+	echo "Reset-init..."
+	; # halt the CPU
+	halt
+
+	echo "HW version [format %x [mrw 0x48]]"
+
+	dap apsel 1
+	DCD
+
+	; # ARM errata ID #468414
+	set tR [arm mrc 15 0 1 0 1]
+	arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]	; # enable L1NEON bit
+
+	init_l2cc
+	init_aips
+	init_clock
+
+	dap apsel 0
+
+	; # Force ARM state
+	; #reg cpsr 0x000001D3
+	arm core_state arm
+
+	jtag_rclk 3000
+#	adapter speed 3000
+}
+
+
+# L2CC Cache setup/invalidation/disable
+proc init_l2cc { } {
+	; #/* explicitly disable L2 cache */
+	; #mrc 15, 0, r0, c1, c0, 1
+	set tR [arm mrc 15 0 1 0 1]
+	; #bic r0, r0, #0x2
+	; #mcr 15, 0, r0, c1, c0, 1
+	arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
+
+	; #/* reconfigure L2 cache aux control reg */
+	; #mov r0, #0xC0                   /* tag RAM */
+	; #add r0, r0, #0x4                /* data RAM */
+	; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+	; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+	; #orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	; #mcr 15, 1, r0, c9, c0, 2
+	arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
+}
+
+
+# AIPS setup - Only setup MPROTx registers.
+# The PACR default values are good.
+proc init_aips { } {
+	; # Set all MPROTx to be non-bufferable, trusted for R/W,
+	; # not forced to user-mode.
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set VAL			0x77777777
+
+#	dap apsel 1
+	mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
+#	dap apsel 0
+}
+
+
+proc init_clock { } {
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set CCM_BASE_ADDR	[expr {$AIPS1_BASE_ADDR + 0x000D4000}]
+	set CLKCTL_CCSR         0x0C
+	set CLKCTL_CBCDR	0x14
+	set CLKCTL_CBCMR        0x18
+	set PLL1_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00080000}]
+	set PLL2_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00084000}]
+	set PLL3_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00088000}]
+	set PLL4_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x0008C000}]
+	set CLKCTL_CSCMR1	0x1C
+	set CLKCTL_CDHIPR	0x48
+	set PLATFORM_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x000A0000}]
+	set CLKCTL_CSCDR1	0x24
+	set CLKCTL_CCDR		0x04
+
+	; # Switch ARM to step clock
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
+
+	return
+	echo "not returned"
+	setup_pll $PLL1_BASE_ADDR 800
+	setup_pll $PLL3_BASE_ADDR 400
+
+	; # Switch peripheral to PLL3
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL2_BASE_ADDR 400
+
+	; # Switch peripheral to PLL2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
+
+	; # change uart clk parent to pll2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
+
+	; # make sure change is effective
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL3_BASE_ADDR 216
+
+	setup_pll $PLL4_BASE_ADDR 455
+
+	; # Set the platform clock dividers
+	mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
+
+	mww [expr {$CCM_BASE_ADDR + 0x10}] 0
+
+	; # Switch ARM back to PLL 1.
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
+
+	; # make uart div=6
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
+
+	; # Restore the default values in the Gate registers
+	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
+
+	; # for cko - for ARM div by 8
+	mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
+}
+
+
+proc setup_pll { PLL_ADDR CLK } {
+	set PLL_DP_CTL		0x00
+	set PLL_DP_CONFIG   	0x04
+	set PLL_DP_OP		0x08
+	set PLL_DP_HFS_OP	0x1C
+	set PLL_DP_MFD		0x0C
+	set PLL_DP_HFS_MFD	0x20
+	set PLL_DP_MFN		0x10
+	set PLL_DP_HFS_MFN	0x24
+
+	if {$CLK == 1000} {
+		set DP_OP	[expr {(10 << 4) + ((1 - 1) << 0)}]
+		set DP_MFD	[expr {12 - 1}]
+		set DP_MFN	5
+	} elseif {$CLK == 850} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	41
+	} elseif {$CLK == 800} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 700} {
+		set DP_OP	[expr {(7 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	7
+	} elseif {$CLK == 600} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 665} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {96 - 1}]
+		set DP_MFN	89
+	} elseif {$CLK == 532} {
+		set DP_OP	[expr {(5 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	13
+	} elseif {$CLK == 455} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	71
+	} elseif {$CLK == 400} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 216} {
+		set DP_OP	[expr {(6 << 4) + ((3 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	3
+	} else {
+		error "Error (setup_dll): clock not found!"
+	}
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
+
+	mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
+}
+
+
+proc CPU_2_BE_32 { L } {
+	return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
+}
+
+
+# Device Configuration Data
+proc DCD { } {
+#	dap apsel 1
+#*========================================================================================== ======
+# Initialization script for 32 bit DDR3 (CS0+CS1)
+#*========================================================================================== ======
+# Remux D24/D25 to perform Flash-access
+	mww 0x53fa818C 0x00000000 ; #EIM_RW
+	mww 0x53fa8180 0x00000000 ; #EIM_CS0
+	mww 0x53fa8188 0x00000000 ; #EIM_OE
+	mww 0x53fa817C 0x00000000 ; #A16
+	mww 0x53fa8178 0x00000000 ; #A17
+	mww 0x53fa8174 0x00000000 ; #A18
+	mww 0x53fa8170 0x00000000 ; #A19
+	mww 0x53fa816C 0x00000000 ; #A20
+	mww 0x53fa8168 0x00000000 ; #A21
+	mww 0x53fa819C 0x00000000 ; #DA0
+	mww 0x53fa81A0 0x00000000 ; #DA1
+	mww 0x53fa81A4 0x00000000 ; #DA2
+	mww 0x53fa81A8 0x00000000 ; #DA3
+	mww 0x53fa81AC 0x00000000 ; #DA4
+	mww 0x53fa81B0 0x00000000 ; #DA5
+	mww 0x53fa81B4 0x00000000 ; #DA6
+	mww 0x53fa81B8 0x00000000 ; #DA7
+	mww 0x53fa81BC 0x00000000 ; #DA8
+	mww 0x53fa81C0 0x00000000 ; #DA9
+	mww 0x53fa81C4 0x00000000 ; #DA10
+	mww 0x53fa81C8 0x00000000 ; #DA11
+	mww 0x53fa81CC 0x00000000 ; #DA12
+	mww 0x53fa81D0 0x00000000 ; #DA13
+	mww 0x53fa81D4 0x00000000 ; #DA14
+	mww 0x53fa81D8 0x00000000 ; #DA15
+	mww 0x53fa8118 0x00000000 ; #D16
+	mww 0x53fa811C 0x00000000 ; #D17
+	mww 0x53fa8120 0x00000000 ; #D18
+	mww 0x53fa8124 0x00000000 ; #D19
+	mww 0x53fa8128 0x00000000 ; #D20
+	mww 0x53fa812C 0x00000000 ; #D21
+	mww 0x53fa8130 0x00000000 ; #D22
+	mww 0x53fa8134 0x00000000 ; #D23
+	mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24
+	mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25
+	mww 0x53fa8144 0x00000000 ; #D26
+	mww 0x53fa8148 0x00000000 ; #D27
+	mww 0x53fa814C 0x00000000 ; #D28
+	mww 0x53fa8150 0x00000000 ; #D29
+	mww 0x53fa8154 0x00000000 ; #D30
+	mww 0x53fa8158 0x00000000 ; #D31
+
+# DDR3 IOMUX configuration
+#* Global pad control options */
+	mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+	mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
+	mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+	mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+	mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
+	mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency
+	mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+	mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency
+	mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
+	mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+	mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+	mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+	mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
+	mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+	mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS
+	mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+	mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+#	mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
+	mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
+	mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS
+	mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS
+	mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS
+	mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX
+	mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS
+	mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS
+#	mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode
+#	mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode
+#	mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+#	mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
+
+#* Data bus byte lane pad drive strength control options */
+#	mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS
+#	mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+#	mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
+#	mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS
+#	mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+#	mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
+#	mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS
+#	mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+#	mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
+#	mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS
+#	mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+#	mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
+
+#* SDCLK pad drive strength control options */
+#	mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
+#	mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
+
+#* Control and addr bus pad drive strength control options */
+#	mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+#	mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+#	mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
+#	mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE
+
+#	mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+#	mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+
+# Initialize DDR3 memory - Micron MT41J128M16-187Er
+#** Keep for now, same setting as CPU3 board **#
+	mww 0x63fd901c 0x00008000
+#	mww 0x63fd904c 0x01680172 ; #write leveling reg 0
+#	mww 0x63fd9050 0x0021017f ; #write leveling reg 1
+	mww 0x63fd9088 0x32383535 ; #read delay lines
+	mww 0x63fd9090 0x40383538 ; #write delay lines
+#	mww 0x63fd90F8 0x00000800 ; #Measure unit
+	mww 0x63fd907c 0x0136014d ; #DQS gating 0
+	mww 0x63fd9080 0x01510141 ; #DQS gating 1
+#* CPU3 Board settingr
+# Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
+#	mww 0x63fd9018 0x00091740 ; #Misc register:
+#* Quick Silver board setting
+# Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
+	mww 0x63fd9018 0x00011740 ; #Misc register
+
+# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
+#	mww 0x63fd9000 0xc3190000 ; #Main control register
+# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
+	mww 0x63fd9000 0x83190000 ; #Main control register
+# tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
+	mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0
+# tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
+	mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1
+# tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
+	mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2
+	mww 0x63fd902c 0x000026d2 ; #command delay (default)
+	mww 0x63fd9030 0x009f0e21 ; #out of reset delays
+# Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
+	mww 0x63fd9008 0x12273030 ; #ODT timings
+# tCKE=3; tCKSRX=5; tCKSRE=5
+	mww 0x63fd9004 0x0002002d
+#Power down control
+#**********************************
+#DDR device configuration:
+#**********************************
+#**********************************
+# CS0:
+#**********************************
+	mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)
+# Full array self refresh
+# Rtt_WR disabled (no ODT at IO CMOS operation)
+# Manual self refresh
+# CWS=5
+	mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.
+	mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)
+# out impedance = RZQ/7
+# Rtt_nom disabled (no ODT at IO CMOS operation)
+# Aditive latency off
+# write leveling disabled
+# tdqs (differential?) disabled
+
+	mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0
+	mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)
+#**********************************
+# CS1:
+#**********************************
+#	mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.
+#	mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.
+#	mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7
+#	mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.
+#	mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)
+#**********************************
+
+
+	mww 0x63fd9020 0x00001800 ; # Refresh control register
+	mww 0x63fd9040 0x04b80003 ; # ZQ HW control
+	mww 0x63fd9058 0x00022227 ; # ODT control register
+
+	mww 0x63fd901c 0x00000000
+
+# CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)
+#	mww 0x53FA8314 = 0
+#	mww 0x53FA8320 0x4
+#	mww 0x53FD4060 0x01e900f0
+
+#	dap apsel 0
+}
+
+# IRAM
+$_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1
+
+flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME
+
+# vim:filetype=tcl
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/icnova_sam9g45_sodimm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/icnova_sam9g45_sodimm.cfg
new file mode 100644
index 0000000..7efa8c2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/icnova_sam9g45_sodimm.cfg
@@ -0,0 +1,276 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#################################################################################################
+#												                                                #
+# Author: Lars Poeschel (larsi@wh2.tu-dresden.de)												#
+# Generated for In-Circuit ICnova SAM9G45 SODIMM												#
+# http://www.ic-board.de/product_info.php?info=p214_ICnova-SAM9G45-SODIMM.html|ICnova			#
+#																								#
+#################################################################################################
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+source [find target/at91sam9g45.cfg]
+
+# Set reset type.
+# reset_config trst_and_srst
+
+# adapter srst delay 200
+# jtag_ntrst_delay 200
+
+
+# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
+# AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
+# some powerful features, we want to have a special function that handles "reset init".  To do this we declare
+# an event handler where these special activities can take place.
+
+scan_chain
+$_TARGETNAME configure -event reset-init {at91sam9g45_init}
+
+# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
+# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+$_TARGETNAME configure -event reset-start {at91sam9g45_start}
+
+
+# NandFlash configuration and definition
+# Future TBD
+# Flash configuration
+# flash bank cfi     
+set _FLASHNAME $_CHIPNAME.flash
+# set _NANDNAME $_CHIPNAME.nand
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+# nand device $_NANDNAME at91sam9 $_TARGETNAME 0x40000000 0xFFFFE800
+
+
+proc read_register {register} {
+	return [read_memory $register 32 1]
+}
+
+proc at91sam9g45_start { } {
+
+	# Make sure that the the jtag is running slow, since there are a number of different ways the board
+	# can be configured coming into this state that can cause communication problems with the jtag
+	# adapter.  Also since this call can be made following a "reset init" where fast memory accesses
+	# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
+	# jtag speed without causing GDB keep alive problem.
+
+	arm7_9 fast_memory_access disable
+    # Slow-speed oscillator enabled at reset, so run jtag speed slow.
+	adapter speed 4
+    # Make sure processor is halted, or error will result in following steps.
+	halt
+	wait_halt 10000
+    # RSTC_MR : enable user reset.
+	mww 0xfffffd08 0xa5000501
+}
+
+
+proc at91sam9g45_init { } {
+
+	# At reset AT91SAM9G45 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
+	# a number of steps that must be carefully performed.  The process outline below follows the
+	# recommended procedure outlined in the AT91SAM9G45 technical manual.
+	#
+	# Several key and very important things to keep in mind:
+	# The SDRAM parts used currently on the board are -75 grade parts.  This
+	# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
+	# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+	# Make sure processor is halted, or error will result in following steps.
+	halt
+	# RSTC_MR : enable user reset.
+	mww 0xfffffd08 0xa5000501
+	# WDT_MR : disable watchdog.
+	mww 0xfffffd44 0x00008000
+
+	# Enable the main 15.000 MHz oscillator in CKGR_MOR register.
+	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
+
+	mww 0xfffffc20 0x00004001
+	while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
+
+	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
+	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+	#mww 0xfffffc28 0x202a3f01
+	mww 0xfffffc28 0x20c73f03
+	while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
+
+	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	#mww 0xfffffc30 0x00000101
+	mww 0xfffffc30 0x00001301
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Now change PMC_MCKR register to select PLLA.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00001302
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Processor and master clocks are now operating and stable at maximum frequency possible:
+	#	-> MCLK = 132.096 MHz
+	#	-> PCLK = 396.288 MHz
+
+	# Switch over to adaptive clocking.
+
+	adapter speed 6000
+
+	# Enable faster DCC downloads.
+
+	arm7_9 dcc_downloads enable
+
+	# To be able to use external SDRAM, several peripheral configuration registers must
+	# be modified.  The first change is made to PIO_ASR to select peripheral functions
+	# for D15 through D31.  The second change is made to the PIO_PDR register to disable
+	# this for D15 through D31.
+
+#	mww 0xfffff870 0xffff0000
+#	mww 0xfffff804 0xffff0000
+
+	# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+	# using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
+	# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+	# mww 0xffffef1c 0x000100a
+
+	# The ICnova SAM9G45 SODIMM has built-in NandFlash.  The exact physical timing characteristics
+	# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+	# four registers in order:  SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
+
+	# mww 0xffffec30 0x00020002
+	# mww 0xffffec34 0x04040404
+	# mww 0xffffec38 0x00070007
+	# mww 0xffffec3c 0x00030003
+
+	# Identify NandFlash bank 0.  Disabled at the moment because a memory driver is not yet complete.
+
+#	nand probe 0
+
+    # SMC_SETUP0 : Setup SMC for NOR Flash
+	mww 0xffffe800 0x0012000a
+    # SMC_PULSE0
+	mww 0xffffe804 0x3b38343b
+    # SMC_CYCLE0
+	mww 0xffffe808 0x003f003f
+    # SMC_MODE0
+	mww 0xffffe80c 0x00001000
+    # Identify flash bank 0
+	flash probe 0
+
+	# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
+	# are based on 2 x Samsung K4T51083QG memory.
+
+	# 0. Enable DDR2 Clock
+	mww 0xfffffc00 0x4
+	# 1. Program memory device type
+	# 1.1 configure the DDR controller
+	mww 0xffffe620 0x16
+	# 1.2 program the DDR controller
+	mww 0xffffe608 0x3d
+
+	# 2. program memory device features
+	# 2.1 assume timings for 7.5ns min clock period
+	mww 0xffffe60c 0x21128226
+	# 2.2 pSDDRC->HDDRSDRC2_T1PR
+	mww 0xffffe610 0x02c8100e
+	# 2.3 pSDDRC->HDDRSDRC2_T2PR
+	mww 0xffffe614 0x01000702
+	# 3. NOP
+	mww 0xffffe600 0x1
+	mww 0x70000000 0x1
+	# 3.1 delay 200us
+	sleep 1
+	# jim tcl alternative: after ms
+	# after 0.2
+
+	# 4. NOP
+	mww 0xffffe600 0x1
+	mww 0x70000000 0x1
+	# 4.1 delay 400ns
+
+	# 5. set all bank precharge
+	mww 0xffffe600 0x2
+	mww 0x70000000 0x1
+	# 5.1 delay 400ns
+
+	# 6. set EMR operation (EMRS2)
+	mww 0xffffe600 0x5
+	mww 0x74000000 0x1
+	# 6.1 delay 2 cycles
+
+	# 7. set EMR operation (EMRS3)
+	mww 0xffffe600 0x5
+	mww 0x76000000 0x1
+	# 7.1 delay 2 cycles
+
+	# 8. set EMR operation (EMRS1)
+	mww 0xffffe600 0x5
+	mww 0x72000000 0x1
+	# 8.1 delay 200 cycles (400Mhz -> 5 * 10^-7s)
+	sleep 1
+
+	# 9. Enable DLL Reset (set DLL bit)
+	set CR  [expr {[read_register 0xffffe608] | 0x80}]
+	mww 0xffffe608 $CR
+
+	# 10. mode register cycle to reset the DLL
+	mww 0xffffe600 0x5
+	mww 0x70000000 0x1
+	# 10.1 delay 2 cycles
+
+	# 11. set all bank precharge
+	mww 0xffffe600 0x2
+	mww 0x70000000 0x1
+	# 11.1 delay 400 ns
+
+	# 12. two auto-refresh (CBR) cycles are provided.
+	mww 0xffffe600 0x4
+	mww 0x70000000 0x1
+	# 12.1 delay 10 cycles
+	# 12.2 2nd cycle (schreiben des Mode Register sparen wir uns)
+	mww 0x70000000 0x1
+	# 12.3 delay 10 cycles
+
+	# 13. disable DLL reset (clear DLL bit)
+	set CR  [expr {[read_register 0xffffe608] & 0xffffff7f}]
+	mww 0xffffe608 $CR
+
+	# 14. mode register set cycle
+	mww 0xffffe600 0x3
+	mww 0x70000000 0x1
+
+	# 15. program OCD field (set OCD bits)
+	set CR  [expr {[read_register 0xffffe608] | 0x7000}]
+	mww 0xffffe608 $CR
+
+	# 16. (EMRS1)
+	mww 0xffffe600 0x5
+	mww 0x72000000 0x1
+	# 16.1 delay 2 cycles
+
+	# 17. disable OCD field (clear OCD bits)
+	set CR  [expr {[read_register 0xffffe608] & 0xffff8fff}]
+	mww 0xffffe608 $CR
+
+	# 18. (EMRS1)
+	mww 0xffffe600 0x5
+	mww 0x76000000 0x1
+	# 18.1 delay 2 cycles
+
+	# 19. normal mode command
+	mww 0xffffe600 0x0
+	mww 0x70000000 0x1
+
+	# 20. perform write to any address
+	#mww 0x70000000 0x1
+
+	# 21. write refresh rate into the count field of the refresh rate register
+	mww 0xffffe604 0x24b
+	# 21.1 delay (500 * 6 cycles)
+
+	arm7_9 fast_memory_access enable
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx27ads.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx27ads.cfg
new file mode 100644
index 0000000..79d3c51
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx27ads.cfg
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IMX27 ADS eval board has a single IMX27 chip
+# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
+source [find target/imx27.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { imx27ads_init }
+
+# The IMX27 ADS board has a NOR flash on CS0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
+
+proc imx27ads_init { } {
+	# This setup puts RAM at 0xA0000000
+
+	# reset the board correctly
+	reset run
+	reset halt
+
+	mww 0x10000000 0x20040304
+	mww 0x10020000 0x00000000
+	mww 0x10000004 0xDFFBFCFB
+	mww 0x10020004 0xFFFFFFFF
+
+	sleep 100
+
+	# ========================================
+	#  Configure DDR on CSD0 -- initial reset
+	# ========================================
+	mww 0xD8001010 0x00000008
+
+	# ========================================
+	#  Configure PSRAM on CS5
+	# ========================================
+	mww 0xd8002050 0x0000dcf6
+	mww 0xd8002054 0x444a4541
+	mww 0xd8002058 0x44443302
+
+	#  ========================================
+	#         Configure16 bit NorFlash on CS0
+	#  ========================================
+	mww 0xd8002000 0x0000CC03
+	mww 0xd8002004 0xa0330D01
+	mww 0xd8002008 0x00220800
+
+	# ========================================
+	#  Configure CPLD on CS4
+	# ========================================
+	mww 0xd8002040 0x0000DCF6
+	mww 0xd8002044 0x444A4541
+	mww 0xd8002048 0x44443302
+
+	# ========================================
+	#  Configure DDR on CSD0 -- wait 5000 cycle
+	# ========================================
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
+
+	mww 0xD8001010 0x00000004
+
+	mww 0xD8001004 0x00795729
+
+	mww 0xD8001000 0x92200000
+	mww 0xA0000F00 0x0
+
+	mww 0xD8001000 0xA2200000
+	mww 0xA0000F00 0x0
+	mww 0xA0000F00 0x0
+
+	mww 0xD8001000 0xB2200000
+	mwb 0xA0000033 0xFF
+	mwb 0xA1000000 0xAA
+
+	mww 0xD8001000 0x82228085
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx27lnst.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx27lnst.cfg
new file mode 100644
index 0000000..24f6ed8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx27lnst.cfg
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Linuxstamp-mx27 is board has a single IMX27 chip
+# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
+source [find target/imx27.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { imx27lnst_init }
+
+proc imx27lnst_init { } {
+	# This setup puts RAM at 0xA0000000
+
+	# reset the board correctly
+	adapter speed 500
+	reset run
+	reset halt
+
+	mww 0x10000000 0x20040304
+	mww 0x10020000 0x00000000
+	mww 0x10000004 0xDFFBFCFB
+	mww 0x10020004 0xFFFFFFFF
+
+	sleep 100
+
+	# ========================================
+	#  Configure DDR on CSD0 -- initial reset
+	# ========================================
+	mww 0xD8001010 0x00000008
+
+	sleep 100
+
+	# ========================================
+	#  Configure DDR on CSD0 -- wait 5000 cycle
+	# ========================================
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
+
+	mww 0xD8001010 0x00000004
+
+	mww 0xD8001004 0x00795729
+
+	#mww 0xD8001000 0x92200000
+	mww 0xD8001000 0x91120000
+	mww 0xA0000F00 0x0
+
+	#mww 0xD8001000 0xA2200000
+	mww 0xD8001000 0xA1120000
+	mww 0xA0000F00 0x0
+	mww 0xA0000F00 0x0
+
+	#mww 0xD8001000 0xB2200000
+	mww 0xD8001000 0xB1120000
+	mwb 0xA0000033 0xFF
+	mwb 0xA1000000 0xAA
+
+	#mww 0xD8001000 0x82228085
+	mww 0xD8001000 0x81128080
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx28evk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx28evk.cfg
new file mode 100644
index 0000000..cc13c51
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx28evk.cfg
@@ -0,0 +1,170 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IMX28EVK eval board has a IMX28 chip
+# Tested on SCH-26241 Rev D board with Olimex ARM-USB-OCD
+# Date:	201-02-01
+# Authors: James Robinson & Fabio Estevam
+
+source [find target/imx28.cfg]
+$_TARGETNAME configure -event gdb-attach { imx28evk_init }
+$_TARGETNAME configure -event reset-init { imx28evk_init }
+
+proc imx28evk_init { } {
+
+	halt
+
+	#****************************
+	# VDDD setting
+	#****************************
+	# set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e
+	mww 0x80044010 0x0003F503
+	mww 0x80044040 0x0002041E
+
+	#****************************
+	# CLOCK set up
+	#****************************
+	# Power up PLL0 HW_CLKCTRL_PLL0CTRL0
+	mww 0x80040000 0x00020000
+	# Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0
+	# EMI - first set DIV_EMI to div-by-2 before programming frac divider
+	mww 0x800400F0 0x80000002
+
+
+	# CPU: CPUFRAC=19 480*18/29=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz
+	mww 0x800401B0 0x92921613
+	# Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR
+	mww 0x800401D8 0x00040080
+	# HCLK = 227MHz,HW_CLKCTRL_HBUS DIV =0x2
+	mww 0x80040060 0x00000002
+
+	#****************************
+	# POWER up DCDD_VDDA (DDR2)
+	#****************************
+	# Now set the voltage level to 1.8V HW_POWER_VDDACTRL bits TRC=0xC
+	mww 0x80044050 0x0000270C
+
+	#****************************
+	# DDR2 DCDD_VDDA
+	#****************************
+	# First set up pin muxing and drive strength
+	# Ungate module clock and bring out of reset HW_PINCTRL_CTRL_CLR
+	mww 0x80018008 0xC0000000
+
+	#****************************
+	# EMI PAD setting
+	#****************************
+	# Set up drive strength for EMI pins
+	mww 0x80019B80 0x00030000
+	#IOMUXC_SW_PAD_CTL_GRP_CTLDS
+
+	# Set up pin muxing for EMI, HW_PINCTRL_MUXSEL10, 11, 12, 13
+	mww 0x800181A8 0xFFFFFFFF
+	mww 0x800181B8 0xFFFFFFFF
+	mww 0x800181C8 0xFFFFFFFF
+	mww 0x800181D8 0xFFFFFFFF
+
+	#** Ungate EMI clock in CCM
+	mww 0x800400F0 0x00000002
+
+	#============================================================================
+	# DDR Controller Registers
+	#============================================================================
+	# Manufacturer:    Elpida
+	# Device Part Number:    EDE1116AEBG
+	# Clock Freq.:     200MHz
+	# Density:         1Gb
+	# Chip Selects:    1
+	# Number of Banks: 8
+	# Row address:     13
+	# Column address:  10
+	#============================================================================
+	mww 0x800E0000 0x00000000
+	mww 0x800E0040 0x00000000
+	mww 0x800E0054 0x00000000
+	mww 0x800E0058 0x00000000
+	mww 0x800E005C 0x00000000
+	mww 0x800E0060 0x00000000
+	mww 0x800E0064 0x00000000
+	mww 0x800E0068 0x00010101
+	mww 0x800E006C 0x01010101
+	mww 0x800E0070 0x000f0f01
+	mww 0x800E0074 0x0102020A
+	mww 0x800E007C 0x00010101
+	mww 0x800E0080 0x00000100
+	mww 0x800E0084 0x00000100
+	mww 0x800E0088 0x00000000
+	mww 0x800E008C 0x00000002
+	mww 0x800E0090 0x01010000
+	mww 0x800E0094 0x07080403
+	mww 0x800E0098 0x06005003
+	mww 0x800E009C 0x0A0000C8
+	mww 0x800E00A0 0x02009C40
+	mww 0x800E00A4 0x0002030C
+	mww 0x800E00A8 0x0036B009
+	mww 0x800E00AC 0x031A0612
+	mww 0x800E00B0 0x02030202
+	mww 0x800E00B4 0x00C8001C
+	mww 0x800E00C0 0x00011900
+	mww 0x800E00C4 0xffff0303
+	mww 0x800E00C8 0x00012100
+	mww 0x800E00CC 0xffff0303
+	mww 0x800E00D0 0x00012100
+	mww 0x800E00D4 0xffff0303
+	mww 0x800E00D8 0x00012100
+	mww 0x800E00DC 0xffff0303
+	mww 0x800E00E0 0x00000003
+	mww 0x800E00E8 0x00000000
+	mww 0x800E0108 0x00000612
+	mww 0x800E010C 0x01000f02
+	mww 0x800E0114 0x00000200
+	mww 0x800E0118 0x00020007
+	mww 0x800E011C 0xf4004a27
+	mww 0x800E0120 0xf4004a27
+	mww 0x800E012C 0x07400300
+	mww 0x800E0130 0x07400300
+	mww 0x800E013C 0x00000005
+	mww 0x800E0140 0x00000000
+	mww 0x800E0144 0x00000000
+	mww 0x800E0148 0x01000000
+	mww 0x800E014C 0x01020408
+	mww 0x800E0150 0x08040201
+	mww 0x800E0154 0x000f1133
+	mww 0x800E015C 0x00001f04
+	mww 0x800E0160 0x00001f04
+	mww 0x800E016C 0x00001f04
+	mww 0x800E0170 0x00001f04
+	mww 0x800E0288 0x00010000
+	mww 0x800E028C 0x00030404
+	mww 0x800E0290 0x00000003
+	mww 0x800E02AC 0x01010000
+	mww 0x800E02B0 0x01000000
+	mww 0x800E02B4 0x03030000
+	mww 0x800E02B8 0x00010303
+	mww 0x800E02BC 0x01020202
+	mww 0x800E02C0 0x00000000
+	mww 0x800E02C4 0x02030303
+	mww 0x800E02C8 0x21002103
+	mww 0x800E02CC 0x00061200
+	mww 0x800E02D0 0x06120612
+	mww 0x800E02D4 0x04420442
+	# Mode register 0 for CS1 and CS0, ok to program CS1 even if not used
+	mww 0x800E02D8 0x00000000
+	# Mode register 0 for CS2 and CS3, not supported in this processor
+	mww 0x800E02DC 0x00040004
+	# Mode register 1 for CS1 and CS0, ok to program CS1 even if not used
+	mww 0x800E02E0 0x00000000
+	# Mode register 1 for CS2 and CS3, not supported in this processor
+	mww 0x800E02E4 0x00000000
+	# Mode register 2 for CS1 and CS0, ok to program CS1 even if not used
+	mww 0x800E02E8 0x00000000
+	# Mode register 2 for CS2 and CS3, not supported in this processor
+	mww 0x800E02EC 0x00000000
+	# Mode register 3 for CS1 and CS0, ok to program CS1 even if not used
+	mww 0x800E02F0 0x00000000
+	# Mode register 3 for CS2 and CS3, not supported in this processor
+	mww 0x800E02F4 0xffffffff
+
+	#**  start controller **#
+	mww 0x800E0040 0x00000001
+	# bit[0]: start
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx31pdk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx31pdk.cfg
new file mode 100644
index 0000000..65fa520
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx31pdk.cfg
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IMX31PDK eval board has a single IMX31 chip
+source [find target/imx31.cfg]
+source [find target/imx.cfg]
+$_TARGETNAME configure -event reset-init { imx31pdk_init }
+
+proc self_test {} {
+	echo "Running 100 iterations of test."
+	dump_image /ram/test 0x80000000 0x40000
+	for {set i 0} {$i < 100} {set i [expr {$i+1}]} {
+		echo "Iteration $i"
+		reset init
+		mww 0x80000000 0x12345678 0x10000
+		load_image /ram/test 0x80000000 bin
+		verify_image /ram/test 0x80000000 bin
+	}
+}
+
+
+# Slow fallback frequency
+# measure_clk indicates ca. 3-4MHz.
+jtag_rclk 1000
+
+proc imx31pdk_init { } {
+
+	imx3x_reset
+
+	# This setup puts RAM at 0x80000000
+
+	mww 0x53FC0000 0x040
+	mww 0x53F80000 0x074B0B7D
+
+	# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
+	#mww 0x53F80004 0xFF871D50
+	#mww 0x53F80010 0x00271C1B
+
+	# Start 16 bit NorFlash Initialization on CS0
+	mww 0xb8002000 0x0000CC03
+	mww 0xb8002004 0xa0330D01
+	mww 0xb8002008 0x00220800
+
+	# Configure CPLD on CS4
+	mww 0xb8002040 0x0000DCF6
+	mww 0xb8002044 0x444A4541
+	mww 0xb8002048 0x44443302
+
+	# SDCLK
+	mww 0x43FAC26C 0
+
+	# CAS
+	mww 0x43FAC270 0
+
+	# RAS
+	mww 0x43FAC274 0
+
+	# CS2 (CSD0)
+	mww 0x43FAC27C 0x1000
+
+	# DQM3
+	mww 0x43FAC284 0
+
+	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
+	mww 0x43FAC288 0
+	mww 0x43FAC28C 0
+	mww 0x43FAC290 0
+	mww 0x43FAC294 0
+	mww 0x43FAC298 0
+	mww 0x43FAC29C 0
+	mww 0x43FAC2A0 0
+	mww 0x43FAC2A4 0
+	mww 0x43FAC2A8 0
+	mww 0x43FAC2AC 0
+	mww 0x43FAC2B0 0
+	mww 0x43FAC2B4 0
+	mww 0x43FAC2B8 0
+	mww 0x43FAC2BC 0
+	mww 0x43FAC2C0 0
+	mww 0x43FAC2C4 0
+	mww 0x43FAC2C8 0
+	mww 0x43FAC2CC 0
+	mww 0x43FAC2D0 0
+	mww 0x43FAC2D4 0
+	mww 0x43FAC2D8 0
+	mww 0x43FAC2DC 0
+
+	# Initialization script for 32 bit DDR on MX31 ADS
+	mww 0xB8001010 0x00000004
+	mww 0xB8001004 0x006ac73a
+	mww 0xB8001000 0x92100000
+	mww 0x80000f00 0x12344321
+	mww 0xB8001000 0xa2100000
+	mww 0x80000000 0x12344321
+	mww 0x80000000 0x12344321
+	mww 0xB8001000 0xb2100000
+	mwb 0x80000033 0xda
+	mwb 0x81000000 0xff
+	mww 0xB8001000 0x82226080
+	mww 0x80000000 0xDEADBEEF
+	mww 0xB8001010 0x0000000c
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx35pdk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx35pdk.cfg
new file mode 100644
index 0000000..41206c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx35pdk.cfg
@@ -0,0 +1,254 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IMX35PDK eval board has a single IMX35 chip
+source [find target/imx35.cfg]
+source [find target/imx.cfg]
+$_TARGETNAME configure -event reset-init { imx35pdk_init }
+
+# Stick to *really* low clock rate or reset will fail
+# without RTCK / RCLK
+jtag_rclk 10
+
+proc imx35pdk_init { } {
+
+	imx3x_reset
+
+	mww 0x43f00040 0x00000000
+	mww 0x43f00044 0x00000000
+	mww 0x43f00048 0x00000000
+	mww 0x43f0004C 0x00000000
+	mww 0x43f00050 0x00000000
+	mww 0x43f00000 0x77777777
+	mww 0x43f00004 0x77777777
+	mww 0x53f00040 0x00000000
+	mww 0x53f00044 0x00000000
+	mww 0x53f00048 0x00000000
+	mww 0x53f0004C 0x00000000
+	mww 0x53f00050 0x00000000
+	mww 0x53f00000 0x77777777
+	mww 0x53f00004 0x77777777
+
+	# clock setup
+	mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
+	mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
+
+	#=================================================
+	# WEIM config
+	#=================================================
+	# CS0U
+	mww 0xB8002000 0x0000CC03
+	# CS0L
+	mww 0xB8002004 0xA0330D01
+	# CS0A
+	mww 0xB8002008 0x00220800
+	# CS5U
+	mww 0xB8002050 0x0000dcf6
+	# CS5L
+	mww 0xB8002054 0x444a4541
+	# CS5A
+	mww 0xB8002058 0x44443302
+
+	# IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
+	mww 0x43FAC368 0x00000006
+	mww 0x43FAC36C 0x00000006
+	mww 0x43FAC370 0x00000006
+	mww 0x43FAC374 0x00000006
+	mww 0x43FAC378 0x00000006
+	mww 0x43FAC37C 0x00000006
+	mww 0x43FAC380 0x00000006
+	mww 0x43FAC384 0x00000006
+	mww 0x43FAC388 0x00000006
+	mww 0x43FAC38C 0x00000006
+	mww 0x43FAC390 0x00000006
+	mww 0x43FAC394 0x00000006
+	mww 0x43FAC398 0x00000006
+	mww 0x43FAC39C 0x00000006
+	mww 0x43FAC3A0 0x00000006
+	mww 0x43FAC3A4 0x00000006
+	mww 0x43FAC3A8 0x00000006
+	mww 0x43FAC3AC 0x00000006
+	mww 0x43FAC3B0 0x00000006
+	mww 0x43FAC3B4 0x00000006
+	mww 0x43FAC3B8 0x00000006
+	mww 0x43FAC3BC 0x00000006
+	mww 0x43FAC3C0 0x00000006
+	mww 0x43FAC3C4 0x00000006
+	mww 0x43FAC3C8 0x00000006
+	mww 0x43FAC3CC 0x00000006
+	mww 0x43FAC3D0 0x00000006
+	mww 0x43FAC3D4 0x00000006
+	mww 0x43FAC3D8 0x00000006
+
+	# DDR data bus SD 0 through 31
+	mww 0x43FAC3DC 0x00000082
+	mww 0x43FAC3E0 0x00000082
+	mww 0x43FAC3E4 0x00000082
+	mww 0x43FAC3E8 0x00000082
+	mww 0x43FAC3EC 0x00000082
+	mww 0x43FAC3F0 0x00000082
+	mww 0x43FAC3F4 0x00000082
+	mww 0x43FAC3F8 0x00000082
+	mww 0x43FAC3FC 0x00000082
+	mww 0x43FAC400 0x00000082
+	mww 0x43FAC404 0x00000082
+	mww 0x43FAC408 0x00000082
+	mww 0x43FAC40C 0x00000082
+	mww 0x43FAC410 0x00000082
+	mww 0x43FAC414 0x00000082
+	mww 0x43FAC418 0x00000082
+	mww 0x43FAC41c 0x00000082
+	mww 0x43FAC420 0x00000082
+	mww 0x43FAC424 0x00000082
+	mww 0x43FAC428 0x00000082
+	mww 0x43FAC42c 0x00000082
+	mww 0x43FAC430 0x00000082
+	mww 0x43FAC434 0x00000082
+	mww 0x43FAC438 0x00000082
+	mww 0x43FAC43c 0x00000082
+	mww 0x43FAC440 0x00000082
+	mww 0x43FAC444 0x00000082
+	mww 0x43FAC448 0x00000082
+	mww 0x43FAC44c 0x00000082
+	mww 0x43FAC450 0x00000082
+	mww 0x43FAC454 0x00000082
+	mww 0x43FAC458 0x00000082
+
+	# DQM setup
+	mww 0x43FAC45c 0x00000082
+	mww 0x43FAC460 0x00000082
+	mww 0x43FAC464 0x00000082
+	mww 0x43FAC468 0x00000082
+
+	mww 0x43FAC46c 0x00000006
+	mww 0x43FAC470 0x00000006
+	mww 0x43FAC474 0x00000006
+	mww 0x43FAC478 0x00000006
+	mww 0x43FAC47c 0x00000006
+	mww 0x43FAC480 0x00000006	;# CSD0
+	mww 0x43FAC484 0x00000006	;# CSD1
+	mww 0x43FAC488 0x00000006
+	mww 0x43FAC48c 0x00000006
+	mww 0x43FAC490 0x00000006
+	mww 0x43FAC494 0x00000006
+	mww 0x43FAC498 0x00000006
+	mww 0x43FAC49c 0x00000006
+	mww 0x43FAC4A0 0x00000006
+	mww 0x43FAC4A4 0x00000006	;# RAS
+	mww 0x43FAC4A8 0x00000006	;# CAS
+	mww 0x43FAC4Ac 0x00000006	;# SDWE
+	mww 0x43FAC4B0 0x00000006 	;# SDCKE0
+	mww 0x43FAC4B4 0x00000006  ;# SDCKE1
+	mww 0x43FAC4B8 0x00000002  ;# SDCLK
+
+	# SDQS0 through SDQS3
+	mww 0x43FAC4Bc 0x00000082
+	mww 0x43FAC4C0 0x00000082
+	mww 0x43FAC4C4 0x00000082
+	mww 0x43FAC4C8 0x00000082
+
+
+	# *==================================================
+	#  Initialization script for 32 bit DDR2 on RINGO 3DS
+	# *==================================================
+
+	#--------------------------------------------
+	# Init CCM
+	#--------------------------------------------
+	mww 0x53F80028 0x7D000028
+
+	#--------------------------------------------
+	# Init IOMUX for JTAG
+	#--------------------------------------------
+	mww 0x43FAC5EC 0x000000C3
+	mww 0x43FAC5F0 0x000000C3
+	mww 0x43FAC5F4 0x000000F3
+	mww 0x43FAC5F8 0x000000F3
+	mww 0x43FAC5FC 0x000000F3
+	mww 0x43FAC600 0x000000F3
+	mww 0x43FAC604 0x000000F3
+
+
+	# ESD_MISC : enable DDR2
+	mww 0xB8001010 0x00000304
+
+	#--------------------------------------------
+	# Init 32-bit DDR2 memory on CSD0
+	# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
+	#--------------------------------------------
+
+	# ESD_ESDCFG0 : set timing parameters
+	mww 0xB8001004 0x007ffC2f
+
+	# ESD_ESDCTL0 : select Prechare-All mode
+	mww 0xB8001000 0x92220000
+	# DDR2 : Prechare-All
+	mww 0x80000400 0x12345678
+
+	# ESD_ESDCTL0 : select Load-Mode-Register mode
+	mww 0xB8001000 0xB2220000
+	# DDR2 : Load reg EMR2
+	mwb 0x84000000 0xda
+	# DDR2 : Load reg EMR3
+	mwb 0x86000000 0xda
+	# DDR2 : Load reg EMR1 -- enable DLL
+	mwb 0x82000400 0xda
+	# DDR2 : Load reg MR -- reset DLL
+	mwb 0x80000333 0xda
+
+	# ESD_ESDCTL0 : select Prechare-All mode
+	mww 0xB8001000 0x92220000
+	# DDR2 : Prechare-All
+	mwb 0x80000400 0x12345678
+
+	# ESD_ESDCTL0 : select Manual-Refresh mode
+	mww 0xB8001000 0xA2220000
+	# DDR2 : Manual-Refresh 2 times
+	mww 0x80000000 0x87654321
+	mww 0x80000000 0x87654321
+
+	# ESD_ESDCTL0 : select Load-Mode-Register mode
+	mww 0xB8001000 0xB2220000
+	# DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
+	mwb 0x80000233 0xda
+	# DDR2 : Load reg EMR1 -- OCD default
+	mwb 0x82000780 0xda
+	# DDR2 : Load reg EMR1 -- OCD exit
+	mwb 0x82000400 0xda	;# ODT disabled
+
+	# ESD_ESDCTL0 : select normal-operation mode
+	# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
+	# disable PWT & PRCT
+	# disable Auto-Refresh
+	mww 0xB8001000 0x82220080
+
+	## ESD_ESDCTL0 : enable Auto-Refresh
+	mww 0xB8001000 0x82228080
+	## ESD_ESDCTL1 : enable Auto-Refresh
+	mww 0xB8001008 0x00002000
+
+
+	#***********************************************
+	# Adjust the ESDCDLY5 register
+	#***********************************************
+	# Vary DQS_ABS_OFFSET5 for writes
+	mww 0xB8001020 0x00F48000	;# this is the default value
+	mww 0xB8001024 0x00F48000	;# this is the default value
+	mww 0xB8001028 0x00F48000	;# this is the default value
+	mww 0xB800102c 0x00F48000	;# this is the default value
+
+
+	#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
+	mww 0xB8001010 0x00000384
+	# wait a while
+	sleep 1000
+	# now clear the force measurement bit
+	mww 0xB8001010 0x00000304
+
+	# dummy write to DDR memory to set DQS low
+	mww 0x80000000 0x00000000
+
+	mww 0x30000100 0x0
+	mww 0x30000104 0x31024
+
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx53-m53evk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx53-m53evk.cfg
new file mode 100644
index 0000000..6f9210a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx53-m53evk.cfg
@@ -0,0 +1,320 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#######################################
+# DENX M53EVK                         #
+# http://www.denx-cs.de/?q=M53EVK     #
+# Author: Marek Vasut  #
+# Based on imx53loco.cfg              #
+#######################################
+
+# The DENX M53EVK has on-board JTAG adapter
+source [find interface/ftdi/m53evk.cfg]
+# The DENX M53EVK board has a single i.MX53 chip
+source [find target/imx53.cfg]
+# Helper for common memory read/modify/write procedures
+source [find mem_helper.tcl]
+
+echo "iMX53 M53EVK board lodaded."
+
+# Set reset type
+reset_config trst_and_srst separate trst_open_drain srst_open_drain
+
+# Run at 6 MHz
+adapter speed 6000
+
+$_TARGETNAME configure -event "reset-assert" {
+	echo "Resetting ...."
+	#cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-init { m53evk_init }
+
+global AIPS1_BASE_ADDR
+set AIPS1_BASE_ADDR     0x53F00000
+global AIPS2_BASE_ADDR
+set AIPS2_BASE_ADDR     0x63F00000
+
+proc m53evk_init { } {
+	echo "Reset-init..."
+	; # halt the CPU
+	halt
+
+	echo "HW version [format %x [mrw 0x48]]"
+
+	dap apsel 1
+	DCD
+
+	; # ARM errata ID #468414
+	set tR [arm mrc 15 0 1 0 1]
+	arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]	; # enable L1NEON bit
+
+	init_l2cc
+	init_aips
+	init_clock
+
+	dap apsel 0
+
+	; # Force ARM state
+	; #reg cpsr 0x000001D3
+	arm core_state arm
+}
+
+
+# L2CC Cache setup/invalidation/disable
+proc init_l2cc { } {
+	; #/* explicitly disable L2 cache */
+	; #mrc 15, 0, r0, c1, c0, 1
+	set tR [arm mrc 15 0 1 0 1]
+	; #bic r0, r0, #0x2
+	; #mcr 15, 0, r0, c1, c0, 1
+	arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
+
+	; #/* reconfigure L2 cache aux control reg */
+	; #mov r0, #0xC0                   /* tag RAM */
+	; #add r0, r0, #0x4                /* data RAM */
+	; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+	; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+	; #orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	; #mcr 15, 1, r0, c9, c0, 2
+	arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
+}
+
+
+# AIPS setup - Only setup MPROTx registers.
+# The PACR default values are good.
+proc init_aips { } {
+	; # Set all MPROTx to be non-bufferable, trusted for R/W,
+	; # not forced to user-mode.
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set VAL			0x77777777
+
+#	dap apsel 1
+	mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
+#	dap apsel 0
+}
+
+
+proc init_clock { } {
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set CCM_BASE_ADDR	[expr {$AIPS1_BASE_ADDR + 0x000D4000}]
+	set CLKCTL_CCSR         0x0C
+	set CLKCTL_CBCDR	0x14
+	set CLKCTL_CBCMR        0x18
+	set PLL1_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00080000}]
+	set PLL2_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00084000}]
+	set PLL3_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00088000}]
+	set PLL4_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x0008C000}]
+	set CLKCTL_CSCMR1	0x1C
+	set CLKCTL_CDHIPR	0x48
+	set PLATFORM_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x000A0000}]
+	set CLKCTL_CSCDR1	0x24
+	set CLKCTL_CCDR		0x04
+
+	; # Switch ARM to step clock
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
+
+	return
+	echo "not returned"
+	setup_pll $PLL1_BASE_ADDR 800
+	setup_pll $PLL3_BASE_ADDR 400
+
+	; # Switch peripheral to PLL3
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL2_BASE_ADDR 400
+
+	; # Switch peripheral to PLL2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
+
+	; # change uart clk parent to pll2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
+
+	; # make sure change is effective
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL3_BASE_ADDR 216
+
+	setup_pll $PLL4_BASE_ADDR 455
+
+	; # Set the platform clock dividers
+	mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
+
+	mww [expr {$CCM_BASE_ADDR + 0x10}] 0
+
+	; # Switch ARM back to PLL 1.
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
+
+	; # make uart div=6
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
+
+	; # Restore the default values in the Gate registers
+	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
+
+	; # for cko - for ARM div by 8
+	mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
+}
+
+
+proc setup_pll { PLL_ADDR CLK } {
+	set PLL_DP_CTL		0x00
+	set PLL_DP_CONFIG   	0x04
+	set PLL_DP_OP		0x08
+	set PLL_DP_HFS_OP	0x1C
+	set PLL_DP_MFD		0x0C
+	set PLL_DP_HFS_MFD	0x20
+	set PLL_DP_MFN		0x10
+	set PLL_DP_HFS_MFN	0x24
+
+	if {$CLK == 1000} {
+		set DP_OP	[expr {(10 << 4) + ((1 - 1) << 0)}]
+		set DP_MFD	[expr {12 - 1}]
+		set DP_MFN	5
+	} elseif {$CLK == 850} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	41
+	} elseif {$CLK == 800} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 700} {
+		set DP_OP	[expr {(7 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	7
+	} elseif {$CLK == 600} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 665} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {96 - 1}]
+		set DP_MFN	89
+	} elseif {$CLK == 532} {
+		set DP_OP	[expr {(5 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	13
+	} elseif {$CLK == 455} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	71
+	} elseif {$CLK == 400} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 216} {
+		set DP_OP	[expr {(6 << 4) + ((3 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	3
+	} else {
+		error "Error (setup_dll): clock not found!"
+	}
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
+
+	mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
+}
+
+
+proc CPU_2_BE_32 { L } {
+	return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
+}
+
+
+# Device Configuration Data
+proc DCD { } {
+#	dap apsel 1
+	mww 0x53fa86f4 0x00000000	 ;# GRP_DDRMODE_CTL
+	mww 0x53fa8714 0x00000000	 ;# GRP_DDRMODE
+	mww 0x53fa86fc 0x00000000	 ;# GRP_DDRPKE
+	mww 0x53fa8724 0x04000000	 ;# GRP_DDR_TYPE
+
+	mww 0x53fa872c 0x00300000	 ;# GRP_B3DS
+	mww 0x53fa8554 0x00300000	 ;# DRAM_DQM3
+	mww 0x53fa8558 0x00300040	 ;# DRAM_SDQS3
+
+	mww 0x53fa8728 0x00300000	 ;# GRP_B2DS
+	mww 0x53fa8560 0x00300000	 ;# DRAM_DQM2
+	mww 0x53fa8568 0x00300040	 ;# DRAM_SDQS2
+
+	mww 0x53fa871c 0x00300000	 ;# GRP_B1DS
+	mww 0x53fa8594 0x00300000	 ;# DRAM_DQM1
+	mww 0x53fa8590 0x00300040	 ;# DRAM_SDQS1
+
+	mww 0x53fa8718 0x00300000	 ;# GRP_B0DS
+	mww 0x53fa8584 0x00300000	 ;# DRAM_DQM0
+	mww 0x53fa857c 0x00300040	 ;# DRAM_SDQS0
+
+	mww 0x53fa8578 0x00300000	 ;# DRAM_SDCLK_0
+	mww 0x53fa8570 0x00300000	 ;# DRAM_SDCLK_1
+
+	mww 0x53fa8574 0x00300000	 ;# DRAM_CAS
+	mww 0x53fa8588 0x00300000	 ;# DRAM_RAS
+	mww 0x53fa86f0 0x00300000	 ;# GRP_ADDDS
+	mww 0x53fa8720 0x00300000	 ;# GRP_CTLDS
+
+	mww 0x53fa8564 0x00300040	 ;# DRAM_SDODT1
+	mww 0x53fa8580 0x00300040	 ;# DRAM_SDODT0
+
+	# Initialize DDR2 memory
+	mww 0x63fd9088 0x32383535
+	mww 0x63fd9090 0x40383538
+	mww 0x63fd907c 0x0136014d
+	mww 0x63fd9080 0x01510141
+
+	mww 0x63fd9018 0x00011740
+	mww 0x63fd9000 0xc3190000
+	mww 0x63fd900c 0x555952e3
+	mww 0x63fd9010 0xb68e8b63
+	mww 0x63fd9014 0x01ff00db
+	mww 0x63fd902c 0x000026d2
+	mww 0x63fd9030 0x009f0e21
+	mww 0x63fd9008 0x12273030
+	mww 0x63fd9004 0x0002002d
+	mww 0x63fd901c 0x00008032
+	mww 0x63fd901c 0x00008033
+	mww 0x63fd901c 0x00028031
+	mww 0x63fd901c 0x092080b0
+	mww 0x63fd901c 0x04008040
+	mww 0x63fd901c 0x0000803a
+	mww 0x63fd901c 0x0000803b
+	mww 0x63fd901c 0x00028039
+	mww 0x63fd901c 0x09208138
+	mww 0x63fd901c 0x04008048
+	mww 0x63fd9020 0x00001800
+	mww 0x63fd9040 0x04b80003
+	mww 0x63fd9058 0x00022227
+	mww 0x63fd901c 0x00000000
+#	dap apsel 0
+}
+
+# vim:filetype=tcl
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx53loco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx53loco.cfg
new file mode 100644
index 0000000..fcc2f4d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx53loco.cfg
@@ -0,0 +1,317 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+##################################################################################
+# Author: Wjatscheslaw Stoljarski (Slawa)  #
+# Kiwigrid GmbH                                                                  #
+##################################################################################
+
+# The IMX53LOCO (QSB) board has a single IMX53 chip
+source [find target/imx53.cfg]
+# Helper for common memory read/modify/write procedures
+source [find mem_helper.tcl]
+
+echo "iMX53 Loco board lodaded."
+
+# Set reset type
+#reset_config srst_only
+
+adapter speed 3000
+
+# Slow speed to be sure it will work
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+
+#adapter srst delay 200
+#jtag_ntrst_delay 200
+
+$_TARGETNAME configure -event "reset-assert" {
+	echo "Resetting ...."
+	#cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-init { loco_init }
+
+global AIPS1_BASE_ADDR
+set AIPS1_BASE_ADDR     0x53F00000
+global AIPS2_BASE_ADDR
+set AIPS2_BASE_ADDR     0x63F00000
+
+proc loco_init { } {
+	echo "Reset-init..."
+	; # halt the CPU
+	halt
+
+	echo "HW version [format %x [mrw 0x48]]"
+
+	dap apsel 1
+	DCD
+
+	; # ARM errata ID #468414
+	set tR [arm mrc 15 0 1 0 1]
+	arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]	; # enable L1NEON bit
+
+	init_l2cc
+	init_aips
+	init_clock
+
+	dap apsel 0
+
+	; # Force ARM state
+	; #reg cpsr 0x000001D3
+	arm core_state arm
+
+	jtag_rclk 3000
+#	adapter speed 3000
+}
+
+
+# L2CC Cache setup/invalidation/disable
+proc init_l2cc { } {
+	; #/* explicitly disable L2 cache */
+	; #mrc 15, 0, r0, c1, c0, 1
+	set tR [arm mrc 15 0 1 0 1]
+	; #bic r0, r0, #0x2
+	; #mcr 15, 0, r0, c1, c0, 1
+	arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
+
+	; #/* reconfigure L2 cache aux control reg */
+	; #mov r0, #0xC0                   /* tag RAM */
+	; #add r0, r0, #0x4                /* data RAM */
+	; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+	; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+	; #orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	; #mcr 15, 1, r0, c9, c0, 2
+	arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
+}
+
+
+# AIPS setup - Only setup MPROTx registers.
+# The PACR default values are good.
+proc init_aips { } {
+	; # Set all MPROTx to be non-bufferable, trusted for R/W,
+	; # not forced to user-mode.
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set VAL			0x77777777
+
+#	dap apsel 1
+	mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
+#	dap apsel 0
+}
+
+
+proc init_clock { } {
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set CCM_BASE_ADDR	[expr {$AIPS1_BASE_ADDR + 0x000D4000}]
+	set CLKCTL_CCSR         0x0C
+	set CLKCTL_CBCDR	0x14
+	set CLKCTL_CBCMR        0x18
+	set PLL1_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00080000}]
+	set PLL2_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00084000}]
+	set PLL3_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00088000}]
+	set PLL4_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x0008C000}]
+	set CLKCTL_CSCMR1	0x1C
+	set CLKCTL_CDHIPR	0x48
+	set PLATFORM_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x000A0000}]
+	set CLKCTL_CSCDR1	0x24
+	set CLKCTL_CCDR		0x04
+
+	; # Switch ARM to step clock
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
+
+	return
+	echo "not returned"
+	setup_pll $PLL1_BASE_ADDR 800
+	setup_pll $PLL3_BASE_ADDR 400
+
+	; # Switch peripheral to PLL3
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL2_BASE_ADDR 400
+
+	; # Switch peripheral to PLL2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
+
+	; # change uart clk parent to pll2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
+
+	; # make sure change is effective
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL3_BASE_ADDR 216
+
+	setup_pll $PLL4_BASE_ADDR 455
+
+	; # Set the platform clock dividers
+	mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
+
+	mww [expr {$CCM_BASE_ADDR + 0x10}] 0
+
+	; # Switch ARM back to PLL 1.
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
+
+	; # make uart div=6
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
+
+	; # Restore the default values in the Gate registers
+	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
+
+	; # for cko - for ARM div by 8
+	mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
+}
+
+
+proc setup_pll { PLL_ADDR CLK } {
+	set PLL_DP_CTL		0x00
+	set PLL_DP_CONFIG   	0x04
+	set PLL_DP_OP		0x08
+	set PLL_DP_HFS_OP	0x1C
+	set PLL_DP_MFD		0x0C
+	set PLL_DP_HFS_MFD	0x20
+	set PLL_DP_MFN		0x10
+	set PLL_DP_HFS_MFN	0x24
+
+	if {$CLK == 1000} {
+		set DP_OP	[expr {(10 << 4) + ((1 - 1) << 0)}]
+		set DP_MFD	[expr {12 - 1}]
+		set DP_MFN	5
+	} elseif {$CLK == 850} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	41
+	} elseif {$CLK == 800} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 700} {
+		set DP_OP	[expr {(7 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	7
+	} elseif {$CLK == 600} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 665} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {96 - 1}]
+		set DP_MFN	89
+	} elseif {$CLK == 532} {
+		set DP_OP	[expr {(5 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	13
+	} elseif {$CLK == 455} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	71
+	} elseif {$CLK == 400} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 216} {
+		set DP_OP	[expr {(6 << 4) + ((3 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	3
+	} else {
+		error "Error (setup_dll): clock not found!"
+	}
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
+
+	mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
+}
+
+
+proc CPU_2_BE_32 { L } {
+	return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
+}
+
+
+# Device Configuration Data
+proc DCD { } {
+#	dap apsel 1
+	mww 0x53FA8554 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+	mww 0x53FA8558 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
+	mww 0x53FA8560 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+	mww 0x53FA8564 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT
+	mww 0x53FA8568 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
+	mww 0x53FA8570 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
+	mww 0x53FA8574 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+	mww 0x53FA8578 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
+	mww 0x53FA857c 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
+	mww 0x53FA8580 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+	mww 0x53FA8584 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+	mww 0x53FA8588 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+	mww 0x53FA8590 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
+	mww 0x53FA8594 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+	mww 0x53FA86f0 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_ADDDS
+	mww 0x53FA86f4 0x00000000	;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+	mww 0x53FA86fc 0x00000000	;# IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+	mww 0x53FA8714 0x00000000	;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode
+	mww 0x53FA8718 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_B0DS
+	mww 0x53FA871c 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_B1DS
+	mww 0x53FA8720 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_CTLDS
+	mww 0x53FA8724 0x04000000	;# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0=
+	mww 0x53FA8728 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_B2DS
+	mww 0x53FA872c 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_B3DS
+
+	# Initialize DDR2 memory
+	mww 0x63FD9088 0x35343535	;# ESDCTL_RDDLCTL
+	mww 0x63FD9090 0x4d444c44	;# ESDCTL_WRDLCTL
+	mww 0x63FD907c 0x01370138	;# ESDCTL_DGCTRL0
+	mww 0x63FD9080 0x013b013c	;# ESDCTL_DGCTRL1
+	mww 0x63FD9018 0x00011740	;# ESDCTL_ESDMISC
+	mww 0x63FD9000 0xc3190000	;# ESDCTL_ESDCTL
+	mww 0x63FD900c 0x9f5152e3	;# ESDCTL_ESDCFG0
+	mww 0x63FD9010 0xb68e8a63	;# ESDCTL_ESDCFG1
+	mww 0x63FD9014 0x01ff00db	;# ESDCTL_ESDCFG2
+	mww 0x63FD902c 0x000026d2	;# ESDCTL_ESDRWD
+	mww 0x63FD9030 0x009f0e21	;# ESDCTL_ESDOR
+	mww 0x63FD9008 0x12273030	;# ESDCTL_ESDOTC
+	mww 0x63FD9004 0x0002002d	;# ESDCTL_ESDPDC
+	mww 0x63FD901c 0x00008032	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x00008033	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x00028031	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x052080b0	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x04008040	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x0000803a	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x0000803b	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x00028039	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x05208138	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x04008048	;# ESDCTL_ESDSCR
+	mww 0x63FD9020 0x00005800	;# ESDCTL_ESDREF
+	mww 0x63FD9040 0x04b80003	;# ESDCTL_ZQHWCTRL
+	mww 0x63FD9058 0x00022227	;# ESDCTL_ODTCTRL
+	mww 0x63FD901C 0x00000000	;# ESDCTL_ESDSCR
+#	dap apsel 0
+}
+
+# vim:filetype=tcl
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx8mp-evk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx8mp-evk.cfg
new file mode 100644
index 0000000..898f3b7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/imx8mp-evk.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for NXP MC-IMX8MP-EVK
+#
+# Board includes FTDI-based JTAG adapter: interface/ftdi/imx8mp-evk.cfg
+#
+
+transport select jtag
+adapter speed 1000
+reset_config srst_only
+adapter srst delay 100
+
+set CHIPNAME imx8mp
+set CHIPCORES 4
+
+source [find target/imx8m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/insignal_arndale.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/insignal_arndale.cfg
new file mode 100644
index 0000000..c7c28b3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/insignal_arndale.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# InSignal Arndale board
+#
+
+source [find target/exynos5250.cfg]
+
+# Experimentally determined highest working speed
+adapter speed 200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kasli.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kasli.cfg
new file mode 100644
index 0000000..d85e1ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kasli.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter driver ftdi
+ftdi device_desc "Quad RS232-HS"
+ftdi vid_pid 0x0403 0x6011
+ftdi channel 0
+ftdi layout_init 0x0008 0x000b
+# adapter usb location 1:8
+
+reset_config none
+transport select jtag
+adapter speed 25000
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+source [find fpga/xilinx-xadc.cfg]
+source [find fpga/xilinx-dna.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kc100.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kc100.cfg
new file mode 100644
index 0000000..2fd6965
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kc100.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Knovative KC-100 cable modem
+
+# TNETC4401PYP, 208-QFP U3
+source [find target/tnetc4401.cfg]
+
+# 14-pin EJTAG on JP1. Standard pinout, 1-3-5-7-9-11 = nTRST-TDI-TDO-TMS-TCK-nSRST. Use 2 for GND.
+# Was initially disabled in hardware; had to add a solder bridge reenabling R124, R125 on back.
+reset_config trst_and_srst separate
+
+# 16Mb Intel CFI flash. Note this CPU has an internal ROM at 0x1FC0000 (phys) for cold boot.
+# All that really does is some minimal checks before jumping to external flash at 0x00000000 phys.
+# That is remapped to 0xB0000000 uncached, 0x90000000 cached.
+flash bank intel cfi 0xB0000000 0x200000 2 2 $_TARGETNAME
+
+# Perform this after a clean reboot, halt, and reset init (which should also leave it halted).
+proc kc100_dump_flash {} {
+	echo "Probing 48 TSOP Intel CFI flash chip (2MB)..."
+	flash probe intel
+	echo "Dumping 2MB flash chip to flashdump.bin.
+	flash read_bank 0 flashdump.bin 0 0x200000
+}
+
+#TODO figure out memory init sequence to be able to dump from cached segment instead
+
+# There is also a serial console on JP2, 3-5-6 = TX-RX-GND. 9600/8/N/1.
+
+# Possibly of note, this modem's ancient ethernet port does not support Auto-MDIX.
+
+# This modem in many ways appears to be essentially a clone of the SB5120. See usbjtag.com.
+# The firmware/OS is also susceptible to many of the same procedures in "Hacking the Cable Modem"
+# by DerEngel (Ryan Harris), available from No Starch Press.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kc705.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kc705.cfg
new file mode 100644
index 0000000..fad9fff
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kc705.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html
+
+source [find interface/ftdi/digilent-hs1.cfg]
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+source [find fpga/xilinx-xadc.cfg]
+source [find fpga/xilinx-dna.cfg]
+adapter speed 25000
+
+# example command to write bitstream, soft-cpu bios and runtime:
+# openocd -f board/kc705.cfg -c "init;\
+# jtagspi_init 0 bscan_spi_xc7k325t.bit;\
+# jtagspi_program bitstream-kc705.bin 0;\
+# jtagspi_program bios.bin 0xaf0000;\
+# jtagspi_program runtime.fbi 0xb00000;\
+# xc7_program xc7.tap;\
+# exit"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kcu105.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kcu105.cfg
new file mode 100644
index 0000000..1510a06
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kcu105.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx ultrascale
+# http://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
+
+source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
+
+set CHIP XCKU040
+source [find cpld/xilinx-xcu.cfg]
+
+source [find cpld/jtagspi.cfg]
+
+adapter speed 25000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/keil_mcb1700.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/keil_mcb1700.cfg
new file mode 100644
index 0000000..6efbd63
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/keil_mcb1700.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Keil MCB1700 eval board
+#
+# http://www.keil.com/mcb1700/picture.asp
+#
+
+source [find target/lpc17xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/keil_mcb2140.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/keil_mcb2140.cfg
new file mode 100644
index 0000000..bb1d10b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/keil_mcb2140.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Keil MCB2140 eval board
+#
+# http://www.keil.com/mcb2140/picture.asp
+#
+
+source [find target/lpc2148.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kindle2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kindle2.cfg
new file mode 100644
index 0000000..8c032cb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kindle2.cfg
@@ -0,0 +1,183 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Board configuration file for Amazon Kindle Model No. D00701 and D00801
+# AKA Kindle 2nd generation and Kindle DX
+# using a Freescale MCIMX31LDVKN5D i.MX31 processor
+#
+# Pins at J9 40-Pin FFC-A:
+#  1 - GND
+# 16 - TRSTB
+# 17 - TDI
+# 18 - TMS
+# 19 - TCK
+# 20 - RTCK
+# 21 - TDO
+# 22 - DE
+# 25 - BOOT_MODE4
+# 27 - BOOT_MODE2
+
+source [find target/imx31.cfg]
+source [find target/imx.cfg]
+
+$_TARGETNAME configure -event reset-init { kindle2_init }
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
+
+# 8MiB NOR Flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xa0000000 0x800000 2 2 $_TARGETNAME
+
+# 16kiB internal SRAM
+$_TARGETNAME configure -work-area-phys 0x1fffc000 \
+	-work-area-size 0x4000 -work-area-backup 0
+
+# FIXME: currently SRST is not wired to the system
+reset_config trst_only
+jtag_ntrst_assert_width 10
+jtag_ntrst_delay 30
+
+# this is broken but enabled by default
+arm11 memwrite burst disable
+
+adapter speed 1000
+ftdi tdo_sample_edge falling
+
+proc kindle2_init {} {
+	imx3x_reset
+	kindle2_clock_setup
+	disable_mmu_and_cache
+	kindle2_misc_init
+	kindle2_sdram_init
+	arm core_state arm
+}
+
+proc kindle2_clock_setup {} {
+	# CCMR: clock from FPM/CKIL
+	mww 0x53f80000  0x074b0b7b
+	# IPU_CONF
+	mww 0x53fc0000  0x040
+	# 398MHz
+	mww 0x53f80004 0xff871650
+	mww 0x53f80010 0x00331c23
+}
+
+proc kindle2_misc_init { } {
+	# AIPS1
+	mww 0x43f00040 0x0
+	mww 0x43f00044 0x0
+	mww 0x43f00048 0x0
+	mww 0x43f0004c 0x0
+	mww 0x43f00050 0x0
+	mww 0x43f00000 0x77777777
+	mww 0x43f00004 0x77777777
+
+	# AIPS2
+	mww 0x53f00040 0x0
+	mww 0x53f00044 0x0
+	mww 0x53f00048 0x0
+	mww 0x53f0004c 0x0
+	mww 0x53f00050 0x0
+	mww 0x53f00000 0x77777777
+	mww 0x53f00004 0x77777777
+
+	# Start 16 bit NorFlash Initialization on CS0
+	mww 0xb8002000 0x0000cc03
+	mww 0xb8002004 0xa0330d01
+	mww 0xb8002008 0x00220800
+}
+
+proc disable_mmu_and_cache {} {
+	# Mode Supervisor, disable FIQ, IRQ and imprecise data aborts
+	reg cpsr 0x1d3
+
+	# flush entire BTAC
+	arm mcr 15 0 7 5 6 0
+	# invalidate instruction and data cache
+	# MCR CP15, 0, R1, C7, C7, 0
+	arm mcr 15 0 7 7 0
+
+	# clean and invalidate cache
+	arm mcr 15 0 7 15 0
+
+	# disable MMU and caches
+	arm mcr 15 0 1 0 0 0
+
+	arm mcr 15 0 15 2 4 0
+
+	# invalidate TLBs
+	arm mcr 15 0 8 7 0 0
+
+	# Drain the write buffer
+	arm mcr 15 0 7 10 4 0
+
+	# start from AIPS 2GB region
+	arm mcr 15 0 15 2 4 0x40000015
+}
+
+proc kindle2_sdram_init {} {
+	#--------------------------------------------
+	# Samsung K4X1G323PC-8GC3 32Mx32 Mobile DDR SDRAM
+	#--------------------------------------------
+	# SDCLK
+	mww 0x43fac26c 0
+
+	# CAS
+	mww 0x43fac270 0
+
+	# RAS
+	mww 0x43fac274 0
+
+	# CS2 (CSD0)
+	mww 0x43fac27c 0x1000
+
+	# DQM3
+	mww 0x43fac284 0
+
+	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2dc)
+	mww 0x43fac288 0
+	mww 0x43fac28c 0
+	mww 0x43fac290 0
+	mww 0x43fac294 0
+	mww 0x43fac298 0
+	mww 0x43fac29c 0
+	mww 0x43fac2a0 0
+	mww 0x43fac2a4 0
+	mww 0x43fac2a8 0
+	mww 0x43fac2ac 0
+	mww 0x43fac2b0 0
+	mww 0x43fac2b4 0
+	mww 0x43fac2b8 0
+	mww 0x43fac2bc 0
+	mww 0x43fac2c0 0
+	mww 0x43fac2c4 0
+	mww 0x43fac2c8 0
+	mww 0x43fac2cc 0
+	mww 0x43fac2d0 0
+	mww 0x43fac2d4 0
+	mww 0x43fac2d8 0
+	mww 0x43fac2dc 0
+
+	# ?
+	mww 0xb8002000 0x00006602
+	mww 0xb8002004 0x00000501
+	mww 0xb8002008 0x00000000
+
+	# LPDDR1 Initialization script
+	mww 0xb8001010 0x00000002
+	mww 0xb8001010 0x00000004
+	# ESDCFG0: set timing parameters
+	mww 0xb8001004 0x007fff7f
+	# ESDCTL0: select Prechare-All mode
+	mww 0xb8001000 0x92100000
+	mww 0x80000f00 0x12344321
+	# ESDCTL0: Auto Refresh
+	mww 0xb8001000 0xa2100000
+	mww 0x80000000 0x12344321
+	mww 0x80000000 0x12344321
+	# ESDCTL0: Load Mode Register
+	mww 0xb8001000 0xb2100000
+	mwb 0x80000033 0xda
+	mwb 0x81000000 0xff
+	# ESDCTL0: enable Auto-Refresh
+	mww 0xb8001000 0x82226080
+	mww 0x80000000 0xdeadbeef
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kontron_sl28.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kontron_sl28.cfg
new file mode 100644
index 0000000..9816f38
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kontron_sl28.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Kontron SMARC-sAL28
+
+transport select jtag
+reset_config srst_only srst_nogate
+
+jtag newtap unknown0 tap -irlen 12
+
+set _CPUS 2
+source [find target/ls1028a.cfg]
+
+source [find tcl/cpld/altera-epm240.cfg]
+
+adapter speed 2000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kwikstik.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kwikstik.cfg
new file mode 100644
index 0000000..ade0c91
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/kwikstik.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale KwikStik development board
+#
+
+#
+# JLINK interface is onboard
+#
+source [find interface/jlink.cfg]
+
+source [find target/k40.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/la_fonera-fon2200.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/la_fonera-fon2200.cfg
new file mode 100644
index 0000000..b0b2966
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/la_fonera-fon2200.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/atheros_ar2315.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lambdaconcept_ecpix-5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lambdaconcept_ecpix-5.cfg
new file mode 100644
index 0000000..19b9c1c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lambdaconcept_ecpix-5.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# LambdaConcept ECPIX-5
+# http://docs.lambdaconcept.com/ecpix-5/
+# Currently there are following board variants:
+# ECPIX-5 45F - LFE5UM5G-45F
+# ECPIX-5 85F - LFE5UM5G-85F
+#
+# This boards have two JTAG interfaces:
+# - CN4, micro USB port connected to FT2232HQ chip:
+#        ADBUS0 TCK
+#        ADBUS1 TDI
+#        ADBUS2 TDO
+#        ADBUS3 TMS
+#        BDBUS0 UART_TXD
+#        BDBUS1 UART_RXD
+#   This interface should be used with following config:
+#        interface/ftdi/lambdaconcept_ecpix-5.cfg
+# - CN3, 6 pin connector
+# See schematics for more details:
+# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF
+#
+# No reset lines are implemented. So it is not possible to remote reset the FPGA
+# by using any of this interfaces
+
+source [find interface/ftdi/lambdaconcept_ecpix-5.cfg]
+source [find fpga/lattice_ecp5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lemaker_hikey.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lemaker_hikey.cfg
new file mode 100644
index 0000000..fc04435
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lemaker_hikey.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# board configuration for LeMaker Hikey
+#
+
+# board does not feature anything but JTAG
+transport select jtag
+
+# SRST-only reset configuration
+reset_config srst_only srst_push_pull
+
+source [find target/hi6220.cfg]
+
+# make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# examine remaining cores
+	foreach _core $args {
+		${_TARGETNAME}$_core arp_examine
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/linksys-wag200g.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/linksys-wag200g.cfg
new file mode 100644
index 0000000..26900a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/linksys-wag200g.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Linksys WAG200G Router
+#
+# The stock firmware Flash layout is organized as follow:
+#
+#   Start       End         Device
+#   0x90000000  0x90020000  /dev/mtdblock/2
+#   0x90020000  0x900d0000  /dev/mtdblock/1
+#   0x900d0000  0x903a0000  /dev/mtdblock/0
+#   0x903a0000  0x903e0000  /dev/mtdblock/5
+#   0x903e0000  0x903f0000  /dev/mtdblock/3
+#   0x903f0000  0x90400000  /dev/mtdblock/4
+
+set partition_list {
+    adam2	{ "Adam2 bootloader"		0x90000000 0x00020000 }
+    kernel	{ "Kernel"			0x90020000 0x000b0000 }
+    rootfs	{ "Root FS"			0x900d0000 0x002d0000 }
+    lang	{ "Minix language part"		0x903a0000 0x00040000 }
+    config	{ "Firmware config"		0x903e0000 0x00010000 }
+    adam2env	{ "Adam2 environment"		0x903f0000 0x00010000 }
+}
+
+source [find target/ti-ar7.cfg]
+
+# External 4MB MXIC 29LV320MBTC Flash (Manufacturer/Device: 0x00c2 0x227e)
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/linksys-wrt54gl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/linksys-wrt54gl.cfg
new file mode 100644
index 0000000..58dfec3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/linksys-wrt54gl.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Linksys WRT54GL v1.1
+#
+
+source [find target/bcm5352e.cfg]
+
+set partition_list {
+    CFE		{ Bootloader			0x1c000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0x1c040000 0x003b0000 }
+    nvram	{ "Config space"		0x1c3f0000 0x00010000 }
+}
+
+# External 4MB NOR Flash (Intel TE28F320C3BD90 or similar)
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x1c000000 0x00400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/linksys_nslu2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/linksys_nslu2.cfg
new file mode 100644
index 0000000..536f97e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/linksys_nslu2.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for the LinkSys (CISCO) NSLU2 board
+# It is an Intel XSCALE IXP420 CPU.
+
+source [find target/ixp42x.cfg]
+# The _TARGETNAME is set by the above.
+
+$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lisa-l.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lisa-l.cfg
new file mode 100644
index 0000000..1607fb8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lisa-l.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# the Lost Illusions Serendipitous Autopilot
+# http://paparazzi.enac.fr/wiki/Lisa
+
+# Work-area size (RAM size) = 20kB for STM32F103RB device
+set WORKAREASIZE 0x5000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/logicpd_imx27.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/logicpd_imx27.cfg
new file mode 100644
index 0000000..8365d4f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/logicpd_imx27.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The LogicPD Eval IMX27 eval board has a single IMX27 chip
+source [find target/imx27.cfg]
+
+# The Logic PD board has a NOR flash on CS0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
+
+#
+# FIX ME, Add support to
+#
+# (A) hard reset the board.
+# (B) Initialize the SDRAM on the board
+#
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lpc1850_spifi_generic.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lpc1850_spifi_generic.cfg
new file mode 100644
index 0000000..167b624
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lpc1850_spifi_generic.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Generic LPC1850 board w/ SPIFI flash.
+# This config file is intended as an example of how to
+# use the lpcspifi flash driver, but it should be functional
+# for most LPC1850 boards utilizing SPIFI flash.
+
+set CHIPNAME lpc1850
+
+source [find target/lpc1850.cfg]
+
+#A large working area greatly reduces flash write times
+set _WORKAREASIZE 0x4000
+
+$_CHIPNAME.m3 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
+
+#Configure the flash bank; 0x14000000 is the base address for
+#lpc43xx/lpc18xx family micros.
+flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m3
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lpc4350_spifi_generic.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lpc4350_spifi_generic.cfg
new file mode 100644
index 0000000..8a017ec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lpc4350_spifi_generic.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Generic LPC4350 board w/ SPIFI flash.
+# This config file is intended as an example of how to
+# use the lpcspifi flash driver, but it should be functional
+# for most LPC4350 boards utilizing SPIFI flash.
+
+set CHIPNAME lpc4350
+
+source [find target/lpc4350.cfg]
+
+#Configure the flash bank; 0x14000000 is the base address for
+#lpc43xx/lpc18xx family micros.
+flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lubbock.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lubbock.cfg
new file mode 100644
index 0000000..e4de385
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/lubbock.cfg
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel "Lubbock" Development Board with PXA255 (dbpxa255)
+#  Obsolete; this was Intel's original PXA255 development system
+#  Board also had CPU cards for SA1100, PXA210, PXA250, and more.
+
+source [find target/pxa255.cfg]
+
+adapter srst delay 250
+jtag_ntrst_delay 250
+
+# NOTE: until after pinmux and such are set up, only CS0 is
+# available ... not 2nd bank of CFI, or FPGA, SRAM, ENET, etc.
+
+# CS0, CS1 -- two banks of CFI flash, 32 MBytes each
+# each bank is 32-bits wide, two 16-bit chips in parallel
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
+
+# CS2 low -- FPGA registers
+# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
+$_TARGETNAME configure -work-area-phys 0x0a0f0000
+
+$_TARGETNAME configure -event reset-assert-pre \
+	"$_TARGETNAME configure -work-area-size 0"
+
+# Make the hex led display a number, assuming CS2 is set up
+# and all digits have been enabled through the FPGA.
+proc hexled {u32} {
+	mww 0x08000010 $u32
+}
+
+# CS3 -- Ethernet
+# CS4 -- SA1111
+# CS5 -- PCMCIA
+
+# NOTE:  system console normally uses the FF UART connector
+
+proc lubbock_init {target} {
+
+	echo "Initialize PXA255 Lubbock board"
+
+	# (1) pinmux
+
+	# GPSR0..GPSR2
+	mww 0x40e00018 0x00008000
+	mww 0x40e0001c 0x00FC0382
+	mww 0x40e00020 0x0001FFFF
+	# GPDR0..GPDR2
+	mww 0x40e0000c 0x0060A800
+	mww 0x40e00010 0x00FF0382
+	mww 0x40e00014 0x0001C000
+	# GAFR0_[LU]..GAFR2_[LU]
+	mww 0x40e00054 0x98400000
+	mww 0x40e00058 0x00002950
+	mww 0x40e0005c 0x000A9558
+	mww 0x40e00060 0x0005AAAA
+	mww 0x40e00064 0xA0000000
+	mww 0x40e00068 0x00000002
+
+	# write PSSR, enable GPIOs
+	mww 0x40f00000 0x00000020
+
+	# write LED ctrl register ... ones disable
+	# high byte, 8 hex leds; low byte, 8 discretes
+	mwh 0x08000040 0xf0ff
+
+	hexled 0x0000
+
+	# (2) Address space setup
+
+	# MSC0/MSC1/MSC2
+	mww 0x48000008 0x23f223f2
+	mww 0x4800000c 0x3ff1a441
+	mww 0x48000010 0x7ff97ff1
+	# pcmcia/cf
+	mww 0x48000014 0x00000000
+	mww 0x48000028 0x00010504
+	mww 0x4800002c 0x00010504
+	mww 0x48000030 0x00010504
+	mww 0x48000034 0x00010504
+	mww 0x48000038 0x00004715
+	mww 0x4800003c 0x00004715
+
+	hexled 0x1111
+
+	# (3) SDRAM setup
+	# REVISIT this looks dubious ... no refresh cycles
+	mww 0x48000004 0x03CA4018
+	mww 0x48000004 0x004B4018
+	mww 0x48000004 0x000B4018
+	mww 0x48000004 0x000BC018
+	mww 0x48000000 0x00001AC8
+	mww 0x48000000 0x00001AC9
+
+	mww 0x48000040 0x00000000
+
+	# FIXME -- setup:
+	#  CLOCKS (and faster JTAG)
+	#  enable icache
+
+	# FIXME SRAM isn't working
+	# $target configure -work-area-size 0x10000
+
+	hexled 0x2222
+
+	flash probe 0
+	flash probe 1
+
+	hexled 0xcafe
+}
+$_TARGETNAME configure -event reset-init "lubbock_init $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/marsohod.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/marsohod.cfg
new file mode 100644
index 0000000..2be8391
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/marsohod.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marsohod CPLD Development and Education board
+#
+# http://marsohod.org/howtostart/plata
+#
+
+# Recommended MBFTDI programmer
+source [find interface/ftdi/mbftdi.cfg]
+adapter speed 2000
+transport select jtag
+
+# Altera MAXII EPM240T100C CPLD
+source [find cpld/altera-epm240.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/marsohod2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/marsohod2.cfg
new file mode 100644
index 0000000..9575100
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/marsohod2.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marsohod2 FPGA Development and Education board
+#
+# http://www.marsohod.org/prodmarsohod2
+#
+
+# Built-in MBFTDI programmer
+source [find interface/ftdi/mbftdi.cfg]
+adapter speed 2000
+transport select jtag
+
+# Cyclone III EP3C10E144 FPGA
+source [find fpga/altera-ep3c10.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/marsohod3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/marsohod3.cfg
new file mode 100644
index 0000000..b4f2d30
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/marsohod3.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marsohod3 FPGA Development and Education board
+#
+# http://www.marsohod.org/plata-marsokhod3
+#
+
+# Built-in MBFTDI programmer
+source [find interface/ftdi/mbftdi.cfg]
+adapter speed 2000
+transport select jtag
+
+# MAX10 10M50SAE144C8GES FPGA
+source [find fpga/altera-10m50.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mbed-lpc11u24.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mbed-lpc11u24.cfg
new file mode 100644
index 0000000..9f5be88
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mbed-lpc11u24.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an mbed eval board with a single NXP LPC11U24 chip.
+# http://mbed.org/handbook/mbed-NXP-LPC11U24
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# NXP LPC11U24 Cortex-M0 with 32kB Flash and 8kB SRAM
+set WORKAREASIZE 0x2000
+
+source [find target/lpc11xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mbed-lpc1768.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mbed-lpc1768.cfg
new file mode 100644
index 0000000..62b0911
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mbed-lpc1768.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an mbed eval board with a single NXP LPC1768 chip.
+# http://mbed.org/handbook/mbed-NXP-LPC1768
+#
+
+source [find interface/cmsis-dap.cfg]
+
+source [find target/lpc17xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mcb1700.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mcb1700.cfg
new file mode 100644
index 0000000..8ab6e88
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mcb1700.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Keil MCB1700 PCB with 1768
+#
+# Reset init script sets it to 100MHz
+set CCLK 100000
+
+source [find target/lpc17xx.cfg]
+
+global MCB1700_CCLK
+set MCB1700_CCLK $CCLK
+
+$_TARGETNAME configure -event reset-start {
+	# Start *real slow* as we do not know the
+    # state the boot rom left the clock in
+	adapter speed 10
+}
+
+# Set up 100MHz clock to CPU
+$_TARGETNAME configure -event reset-init {
+    # PLL0CON: Disable PLL
+	mww 0x400FC080 0x00000000
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+    # CCLK=PLL/4 (=100 MHz)
+	mww 0x400FC104 0x00000003
+    # CLKSRCSEL: Clock source = internal RC oscillator
+	mww 0x400FC10C 0x00000000
+
+    # PLL0CFG: M=50,N=1 -> PLL=400 MHz
+	mww 0x400FC084 0x00000031
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+	# PLL0CON: Enable PLL
+	mww 0x400FC080 0x00000001
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+	sleep 50
+
+    # PLL0CON: Connect PLL
+	mww 0x400FC080 0x00000003
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+	# Dividing CPU clock by 8 should be pretty conservative
+	#
+	#
+	global MCB1700_CCLK
+	adapter speed [expr {$MCB1700_CCLK / 8}]
+
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+	# Bit Symbol Value Description Reset
+	# value
+	# 0 MAP Memory map control. 0
+	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+	# 1 User mode. The on-chip Flash memory is mapped to address 0.
+	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+	#
+	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+
+	mww 0x400FC040 0x01
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_explorer16.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_explorer16.cfg
new file mode 100644
index 0000000..6b528d6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_explorer16.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Microchip Explorer 16 with PIC32MX360F512L PIM module.
+# http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en024858
+
+# TAPID for PIC32MX360F512L
+set CPUTAPID 0x30938053
+
+# use 32k working area
+set WORKAREASIZE 32768
+
+source [find target/pic32mx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_sama5d27_som1_kit1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_sama5d27_som1_kit1.cfg
new file mode 100644
index 0000000..8e92040
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_sama5d27_som1_kit1.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip SAMA5D27-SOM1-EK1
+# https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMA5D27-SOM1-EK1
+# This board provide two jtag interfaces:
+# J11 - 10 pin interface
+# J10 - USB interface connected to the J-Link-OB.
+#       This functionality is implemented with an ATSAM3U4C microcontroller and
+#       provides JTAG functions and a bridge USB/Serial debug port (CDC).
+#
+# Jumper J7 disables the J-Link-OB-ATSAM3U4C JTAG functionality.
+# - Jumper J7 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional.
+# - Jumper J7 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG
+#   controller can be used through the 10-pin JTAG port J11.
+
+source [find interface/jlink.cfg]
+reset_config srst_only
+
+source [find target/at91sama5d2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_same51_curiosity_nano.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_same51_curiosity_nano.cfg
new file mode 100644
index 0000000..32e2885
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_same51_curiosity_nano.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip SAME51 Curiosity Nano evaluation kit.
+#
+# https://www.microchip.com/en-us/development-tool/EV76S68A
+#
+
+source [find interface/cmsis-dap.cfg]
+
+set CHIPNAME same51
+
+source [find target/atsame5x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_same54_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_same54_xplained_pro.cfg
new file mode 100644
index 0000000..3588165
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_same54_xplained_pro.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Microchip (former Atmel) SAM E54 Xplained Pro evaluation kit.
+# http://www.microchip.com/developmenttools/productdetails.aspx?partno=atsame54-xpro
+#
+
+source [find interface/cmsis-dap.cfg]
+
+set CHIPNAME same54
+
+source [find target/atsame5x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_saml11_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_saml11_xplained_pro.cfg
new file mode 100644
index 0000000..c2fcd65
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/microchip_saml11_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Microchip (formerly Atmel) SAM L11 Xplained Pro Evaluation Kit.
+# https://www.microchip.com/DevelopmentTools/ProductDetails/dm320205
+#
+
+source [find interface/cmsis-dap.cfg]
+adapter speed 1000
+
+set CHIPNAME saml11
+source [find target/atsaml1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mini2440.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mini2440.cfg
new file mode 100644
index 0000000..5642cb1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mini2440.cfg
@@ -0,0 +1,321 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#-------------------------------------------------------------------------
+# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
+# NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
+# 64 MB NAND (Samsung K9D1208V0M)
+# B Findlay  08/09
+#
+#   ----------- Important notes to help you on your way ----------
+# README:
+#     NOR/NAND Boot Switch - I have not read the vivi source, but from
+#     what I could tell from reading the registers it appears that vivi
+#     loads itself into DRAM and then flips NFCONT (0x4E000004) bits
+#     Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
+#     FLASH at the bottom 64MB of memory. This essentially takes the
+#     NOR Flash out of the circuit so you can't trash it.
+#
+#     I adapted the samsung_s3c2440.cfg file which is why I did not
+#     include "source [find target/samsung_s3c2440.cfg]".  I believe
+#     the -work-area-phys 0x200000 is incorrect, but also had to pad
+#     some additional resets.  I didn't modify it as if it is working
+#     for someone, the work-area-phys is not used by most.
+#
+#     JTAG ADAPTER SPECIFIC
+#     IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
+#     FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
+#     This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
+#     necessary to FORCE setting the clock. Normally this should be configured
+#     in the openocd.cfg file, but was placed here as it can be a tough
+#     problem to figure out.  THIS MAY NOT FIX YOUR PROBLEM.. I modified
+#     the openOCD driver jlink.c and posted it here. It may eventually end
+#     up changed in openOCD, but its a hack in the driver and really should
+#     be in the jtag layer (core.c me thinks), but haven't done it yet. My
+#     hack for jlink.c may be found here.
+#
+#     http://forum.sparkfun.com/viewtopic.php?t=16763&sid=946e65abdd3bab39cc7d90dee33ff135
+#
+#     Note: Also if you have a USB JTAG, you will need the USB library installed
+#     on your system "libusb-dev" or the make of openocd will fail. I *think*
+#     it's apt-get install libusb-dev.  When I made my config I only included
+#     --enable-jlink and --enable-usbdevs
+#
+#     I HAVE NOT Tested this thoroughly, so there could still be problems.
+#     But it should get you way ahead of the game from where I started.
+#     If you find problems (and fixes) please post them to
+#     openocd-development@lists.berlios.de and join the developers and
+#     check in fixes to this and anything else you find.  I do not
+#     provide support, but if you ask really nice and I see anything
+#     obvious I will tell you.. mostly just dig, fix, and submit to openocd.
+#
+#     best!   brfindla@yahoo.com   Nashua, NH USA
+#
+#     Recommended resources:
+#       - first two are the best Mini2440 resources anywhere
+#       - maintained by buserror... thanks guy!
+#
+#       http://bliterness.blogspot.com/
+#       http://code.google.com/p/mini2440/
+#
+#       others....
+#
+#       http://forum.sparkfun.com/viewforum.php?f=18
+#       http://labs.kernelconcepts.de/Publications/Micro24401/
+#       http://www.friendlyarm.net/home
+#       http://www.amontec.com/jtag_pinout.shtml
+#
+#-------------------------------------------------------------------------
+#
+#
+# Your openocd.cfg file should contain:
+# source [find interface/.cfg]
+# source [find board/mini2440.cfg]
+#
+#
+#
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+#-------------------------------------------------------------------------
+# Target configuration for the Samsung 2440 system on chip
+# Tested on a S3C2440 Evaluation board by keesj
+# Processor : ARM920Tid(wb) rev 0 (v4l)
+# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
+#  (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+#-------------------------------------------------------------------------
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME s3c2440
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+  # this defaults to a bigendian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0032409d
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x40000000  -work-area-size 0x4000 -work-area-backup 1
+
+#reset configuration
+adapter srst delay 100
+jtag_ntrst_delay 100
+reset_config trst_and_srst
+
+#-------------------------------------------------------------------------
+# JTAG ADAPTER SPECIFIC
+# IMPORTANT! See README at top of this file.
+#-------------------------------------------------------------------------
+
+    adapter speed 12000
+
+#-------------------------------------------------------------------------
+# GDB Setup
+#-------------------------------------------------------------------------
+
+    gdb breakpoint_override hard
+
+#------------------------------------------------
+# ARM SPECIFIC
+#------------------------------------------------
+
+    targets
+  #  arm7_9 dcc_downloads enable
+  #  arm7_9 fast_memory_access enable
+
+
+    nand device s3c2440 0
+
+    adapter srst delay 100
+    jtag_ntrst_delay 100
+    reset_config trst_and_srst
+    init
+
+    echo " "
+    echo "-------------------------------------------"
+    echo "--- login with - telnet localhost 4444  ---"
+    echo "--- then type help_2440                 ---"
+    echo "-------------------------------------------"
+    echo " "
+
+
+
+#------------------------------------------------
+# Processor Initialialization
+# Note: Processor writes can only occur when
+# the state is in SYSTEM. When you call init_2440
+# one of the first lines will tell you what state
+# you are in. If a linux image is booting
+# when you run this, it will not work
+# a vivi boot loader will run with this just
+# fine. The reg values were obtained by a combination
+# of figuring them out fromt the manual, and looking
+# at post vivi values with the debugger. Don't
+# place too much faith in them, but seem to work.
+#------------------------------------------------
+
+proc init_2440 { } {
+
+    halt
+    s3c2440.cpu curstate
+
+    #-----------------------------------------------
+    # Set Processor Clocks - mini2440 xtal=12mHz
+    # we set main clock for 405mHZ
+    # we set the USB Clock for 48mHz
+    # OM2 OM3 pulled to ground so main clock and
+    # usb clock are off 12mHz xtal
+    #-----------------------------------------------
+
+    mww phys 0x4C000014 0x00000005 ;#  Clock Divider control Reg
+    mww phys 0x4C000000 0xFFFFFFFF ;#  LOCKTIME count register
+    mww phys 0x4C000008 0x00038022 ;#  UPPLCON  USB clock config Reg
+    mww phys 0x4C000004 0x0007F021 ;#  MPPLCON  Proc clock config Reg
+
+    #-----------------------------------------------
+    # Configure Memory controller
+    # BWSCON configures all banks, NAND, NOR, DRAM
+    # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
+    #-----------------------------------------------
+
+    mww phys 0x48000000 0x22111112 ;#  BWSCON - Bank and Bus Width
+    mww phys 0x48000010 0x00001112 ;#  BANKCON4 - ?
+    mww phys 0x4800001c 0x00018009 ;#  BANKCON6 - DRAM
+    mww phys 0x48000020 0x00018009 ;#  BANKCON7 - DRAM
+    mww phys 0x48000024 0x008E04EB ;#  REFRESH  - DRAM
+    mww phys 0x48000028 0x000000B2 ;#  BANKSIZE - DRAM
+    mww phys 0x4800002C 0x00000030 ;#  MRSRB6 - DRAM
+    mww phys 0x48000030 0x00000030 ;#  MRSRB7 - DRAM
+
+    #-----------------------------------------------
+    # Now port configuration for enables for memory
+    # and other stuff.
+    #-----------------------------------------------
+
+    mww phys 0x56000000	0x007FFFFF ;#  GPACON
+
+    mww phys 0x56000010	0x00295559 ;#  GPBCON
+    mww phys 0x56000018	0x000003FF ;#  GPBUP (PULLUP ENABLE)
+    mww phys 0x56000014	0x000007C2 ;#  GPBDAT
+
+    mww phys 0x56000020	0xAAAAA6AA ;#  GPCCON
+    mww phys 0x56000028	0x0000FFFF ;#  GPCUP
+    mww phys 0x56000024	0x00000020 ;#  GPCDAT
+
+    mww phys 0x56000030	0xAAAAAAAA ;#  GPDCON
+    mww phys 0x56000038	0x0000FFFF ;#  GPDUP
+
+    mww phys 0x56000040	0xAAAAAAAA ;#  GPECON
+    mww phys 0x56000048	0x0000FFFF ;#  GPEUP
+
+    mww phys 0x56000050	0x00001555 ;#  GPFCON
+    mww phys 0x56000058	0x0000007F ;#  GPFUP
+    mww phys 0x56000054	0x00000000 ;#  GPFDAT
+
+    mww phys 0x56000060	0x00150114 ;#  GPGCON
+    mww phys 0x56000068	0x0000007F ;#  GPGUP
+
+    mww phys 0x56000070	0x0015AAAA ;#  GPHCON
+    mww phys 0x56000078	0x000003FF ;#  GPGUP
+
+}
+
+
+
+proc flash_config { } {
+
+    #-----------------------------------------
+    # Finish Flash Configuration
+    #-----------------------------------------
+
+    halt
+
+    #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
+    nand probe 0
+    nand list
+}
+
+proc flash_uboot { } {
+
+	# flash the u-Boot binary and reboot into it
+	init_2440
+	flash_config
+	nand erase 0 0x0 0x40000
+	nand write 0 /tftpboot/u-boot-nand512.bin 0 oob_softecc_kw
+	resume
+}
+
+
+proc load_uboot { } {
+        echo " "
+        echo " "
+        echo "----------------------------------------------------------"
+        echo "---- Load U-Boot into RAM and execute it.              ---"
+        echo "---- NOTE: loads, partially runs, and hangs            ---"
+        echo "---- U-Boot is fine, this image runs from vivi.        ---"
+        echo "---- I burned u-boot into NAND so I didn't finish      ---"
+        echo "---- debugging it. I am leaving this here as it is     ---"
+        echo "---- part of the way there if you want to fix it.      ---"
+        echo "----                                                   ---"
+        echo "---- mini2440 U-boot here:                             ---"
+        echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git  ---"
+        echo "---- Also this:                                        ---"
+        echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
+        echo "----------------------------------------------------------"
+
+	init_2440
+	echo "Loading /tftpboot/u-boot-nand512.bin"
+	load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
+	echo "Verifying image...."
+	verify_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
+	echo "jumping to u-boot"
+        #bp 0x33f80068 4 hw
+        reg 0 0
+        reg 1 0
+        reg 2 0
+        reg 3 0
+        reg 4 0x33f80000
+      	resume 0x33f80000
+}
+
+       # this may help a little bit debugging the load_uboot
+proc s {} {
+        step
+        reg
+        arm disassemble 0x33F80068 0x10
+}
+
+proc help_2440 {} {
+    echo " "
+    echo " "
+    echo "-----------------------------------------------------------"
+    echo "---- The following mini2440 funcs are supported        ----"
+    echo "----   init_2440 - initialize clocks, DRAM, IO         ----"
+    echo "----   flash_config - configures nand flash            ----"
+    echo "----   load_uboot - loads uboot into ram               ----"
+    echo "----   flash_uboot - flashes uboot to nand (untested)  ----"
+    echo "----   help_2440 - this help display                   ----"
+    echo "-----------------------------------------------------------"
+    echo " "
+    echo " "
+}
+
+
+#----------------------------------------------------------------------------
+#----------------------------------- END ------------------------------------
+#----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mini6410.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mini6410.cfg
new file mode 100644
index 0000000..276e718
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/mini6410.cfg
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a tiny6410
+# Processor       : ARM1176
+# Info : JTAG tap: s3c6410.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2)
+# Info : JTAG tap: s3c6410.cpu tap/device found: 0x07b76f0f (mfg: 0x787, part: 0x7b76, ver: 0x0)
+
+source [find target/samsung_s3c6410.cfg]
+
+proc init_6410 {} {
+	halt
+	reg cpsr 0x1D3
+	arm mcr 15 0 15 2 4 0x70000013
+
+	#-----------------------------------------------
+	# Clock and Timer Setting
+	#-----------------------------------------------
+	mww 0x7e004000 0		;# WATCHDOG 	- Disable
+	mww 0x7E00F120 0x0003		;# MEM_SYS_CFG	- CS0:8 bit, Mem1:32bit, CS2=NAND
+	#mww 0x7E00F120 0x1000		;# MEM_SYS_CFG	- CS0:16bit, Mem1:32bit, CS2=SROMC
+	#mww 0x7E00F120 0x1002		;# MEM_SYS_CFG	- CS0:16bit, Mem1:32bit, CS2=OND
+	mww 0x7E00F900 0x805e		;# OTHERS	- Change SYNCMUX[6] to “1”
+	sleep 1000
+	mww 0x7E00F900 0x80de		;# OTHERS	- Assert SYNCREQ&VICSYNCEN to “1”(rb1004modify)
+	sleep 1000			;#		- Others[11:8] to 0xF
+	mww 0x7E00F000 0xffff		;# APLL_LOCK	- APLL LockTime
+	mww 0x7E00F004 0xffff		;# MPLL_LOCK	- MPLL LockTime
+	mww 0x7E00F020 0x1047310	;# CLK_DIV0 	- ARMCLK:HCLK:PCLK = 1:4:16
+	mww 0x7E00F00c 0x81900302	;# APLL_CON 	- A:400, P:3, S:2 => 400MHz
+	mww 0x7E00F010 0x81900303	;# MPLL_CON 	- M:400, P:3, S:3 => 200MHz
+	mww 0x7E00F01c 0x3		;# CLK_SRC 	- APLL,MPLL Clock Select
+
+	#-----------------------------------------------
+	# DRAM initialization
+	#-----------------------------------------------
+	mww 0x7e001004 0x4		;# P1MEMCCMD	- Enter the config state
+	mww 0x7e001010 0x30C		;# P1REFRESH	- Refresh Period register (7800ns), 100MHz
+#	mww 0x7e001010 0x40e		;# P1REFRESH	- Refresh Period register (7800ns), 133MHz
+	mww 0x7e001014 0x6		;# P1CASLAT	- CAS Latency = 3
+	mww 0x7e001018 0x1		;# P1T_DQSS
+	mww 0x7e00101c 0x2		;# P1T_MRD
+	mww 0x7e001020 0x7		;# P1T_RAS	- 45 ns
+	mww 0x7e001024 0xA		;# P1T_RC	- 67.5 ns
+	mww 0x7e001028 0xC		;# P1T_RCD	- 22.5 ns
+	mww 0x7e00102C 0x10B		;# P1T_RFC	- 80 ns
+	mww 0x7e001030 0xC		;# P1T_RP	- 22.5 ns
+	mww 0x7e001034 0x3		;# P1T_RRD	- 15 ns
+	mww 0x7e001038 0x3		;# P1T_WR	- 15 ns
+	mww 0x7e00103C 0x2		;# P1T_WTR
+	mww 0x7e001040 0x2		;# P1T_XP
+	mww 0x7e001044 0x11		;# P1T_XSR	- 120 ns
+	mww 0x7e001048 0x11		;# P1T_ESR
+
+	#-----------------------------------------------
+	# Memory Configuration Registers
+	#-----------------------------------------------
+	mww 0x7e00100C 0x00010012 	;# P1MEMCFG	- 1 CKE, 1Chip, 4burst, Alw, AP[10],ROW/Column bit
+	mww 0x7e00104C 0x0B41 		;# P1MEMCFG2	- Read delay 1 Cycle, mDDR, 32bit, Sync.
+	mww 0x7e001200 0x150F0 		;# CHIP_N_CFG	- 0x150F0 for 256M, 0x150F8 for 128M
+
+	#-----------------------------------------------
+	# Memory Direct Commands
+	#-----------------------------------------------
+	mww 0x7e001008 0xc0000		;# Chip0 Direct Command :NOP5
+	mww 0x7e001008 0x0		;# Chip0 Direct Command :PreCharge al
+	mww 0x7e001008 0x40000		;# Chip0 Direct Command :AutoRefresh
+	mww 0x7e001008 0x40000		;# Chip0 Direct Command :AutoRefresh
+	mww 0x7e001008 0xA0000		;# EMRS, DS:Full, PASR:Full
+	mww 0x7e001008 0x80032		;# MRS, CAS3, BL4
+	mww 0x7e001004 0x0		;# Enable DMC1
+}
+
+proc install_6410_uboot {} {
+	# write U-boot magic number
+	mww 0x50000000 0x24564236
+	mww 0x50000004 0x20764316
+	load_image u-boot_nand-ram256.bin 0x50008000 bin
+	load_image u-boot_nand-ram256.bin 0x57E00000 bin
+
+	#Kick in
+	reg pc 0x57E00000
+	resume
+}
+
+proc init_6410_flash {} {
+	halt
+	nand probe 0
+	nand list
+}
+
+
+adapter speed 1000
+adapter srst delay 100
+jtag_ntrst_delay 100
+reset_config trst_and_srst
+
+gdb breakpoint_override hard
+
+targets
+nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
+
+init
+echo " "
+echo " "
+echo "-------------------------------------------------------------------"
+echo "---- The following mini6410/tiny6410 functions are available:  ----"
+echo "----   init_6410 - initialize clock, timer, DRAM               ----"
+echo "----   init_6410_flash - initializes NAND flash support        ----"
+echo "----   install_6410_uboot - copies u-boot image into RAM and   ----"
+echo "----                        runs it                            ----"
+echo "-------------------------------------------------------------------"
+echo " "
+echo " "
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/minispartan6.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/minispartan6.cfg
new file mode 100644
index 0000000..011cc54
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/minispartan6.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# https://www.scarabhardware.com/minispartan6/
+
+source [find interface/ftdi/minispartan6.cfg]
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
+
+# example command to read the device dna of the FPGA on the board;
+# openocd -f board/minispartan6.cfg -c "init;xc6s_print_dna xc6s.tap;shutdown"
+
+# example command to write bitstream
+# openocd -f board/minispartan6.cfg -c "init;\
+# jtagspi_init 0 bscan_spi_xc6slx??.bit;\
+# jtagspi_program bitstream.bin 0;\
+# xc6s_program xc6s.tap;\
+# shutdown"
+#
+# jtagspi flash procies can be found in the contrib/loaders/flash/fpga/
+# directory, with prebuilt versions available at
+# https://github.com/jordens/bscan_spi_bitstreams
+#
+# For the SLX25 variant, use
+#  - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx25.bit
+# For the SLX9 variant, use
+#  - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx9.bit
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nds32_corvettef1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nds32_corvettef1.cfg
new file mode 100644
index 0000000..7300ce0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nds32_corvettef1.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ADP-Corvette-F1 R1.0
+# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r1/
+# ADP-Corvette-F1 R2.0
+# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r2/
+
+adapter speed     10000
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+reset_config srst_only
+
+source [find target/nds32v5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nds32_xc7.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nds32_xc7.cfg
new file mode 100644
index 0000000..82c00ac
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nds32_xc7.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ADP-XC7K160/410
+# http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/
+
+source [find target/nds32v5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/netgear-dg834v3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/netgear-dg834v3.cfg
new file mode 100644
index 0000000..a993888
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/netgear-dg834v3.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Netgear DG834v3 Router
+# Internal 4Kb RAM (@0x80000000)
+# Flash is located at 0x90000000 (CS0) and RAM is located at 0x94000000 (CS1)
+#
+
+set partition_list {
+    loader	{ "Bootloader (ADAM2)"		0x90000000 0x00020000 }
+    firmware	{ "Kernel+rootfs"		0x90020000 0x003d0000 }
+    config	{ "Bootloader config space"	0x903f0000 0x00010000 }
+}
+
+source [find target/ti-ar7.cfg]
+
+# External 16MB SDRAM - disabled as we use internal sram
+#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000
+
+# External 4MB NOR Flash
+set _FLASHNAME $_CHIPNAME.norflash
+flash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/netgear-wg102.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/netgear-wg102.cfg
new file mode 100644
index 0000000..0a7dad5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/netgear-wg102.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/atheros_ar2313.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event reset-init {
+	mips32 cp0 12 0 0x10400000
+
+	# configure sdram controller
+	mww 0xb8300004 0x0e03
+	sleep 100
+	mww 0xb8300004 0x0e01
+	mww 0xb8300008 0x10
+	sleep 500
+	mww 0xb8300004 0x0e02
+
+	mww 0xb8300000 0x6c0088
+	mww 0xb8300008 0x57e
+	mww 0xb8300004 0x0e00
+	mww 0xb8300004 0xb00
+
+	# configure flash
+	#                 0x00000001 - 0x01 << FLASHCTL_IDCY_S
+	#                 0x000000e0 - 0x07 << FLASHCTL_WST1_S
+	# FLASHCTL_RBLE   0x00000400 - Read byte lane enable
+	#                 0x00003800 - 0x07 << FLASHCTL_WST2_S
+	# FLASHCTL_AC_8M  0x00060000 - Size of flash
+	# FLASHCTL_E      0x00080000 - Flash bank enable (added)
+	# FLASHCTL_WP     0x04000000 - write protect. If used, CFI mode won't work!!
+	# FLASHCTL_MWx16  0x10000000 - 16bit mode. Do not use it!!
+	# FLASHCTL_MWx8   0x00000000 - 8bit mode.
+	mww 0xb8400000 0x000d3ce1
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbe000000 0x00400000 1 1 $_TARGETNAME x16_as_x8
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf51822_mkit.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf51822_mkit.cfg
new file mode 100644
index 0000000..266d710
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf51822_mkit.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic Semiconductor PCA10024 board (aka nRF51822-mKIT)
+#
+
+source [find interface/cmsis-dap.cfg]
+source [find target/nrf51.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf51_dk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf51_dk.cfg
new file mode 100644
index 0000000..7ddae2d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf51_dk.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic Semiconductor NRF51 Development Kit (nRF6824)
+#
+
+source [find interface/jlink.cfg]
+
+transport select swd
+
+source [find target/nrf51.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf52_dk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf52_dk.cfg
new file mode 100644
index 0000000..7366bf9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf52_dk.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic Semiconductor NRF52 Development Kit (nRF52832)
+#
+
+source [find interface/jlink.cfg]
+
+transport select swd
+
+source [find target/nrf52.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf52_ftx232.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf52_ftx232.cfg
new file mode 100644
index 0000000..c3c69a8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nordic_nrf52_ftx232.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# nordic module NRF52 (nRF52832/52840) attached to an adafruit ft232h module
+# or any FT232H/FT2232H/FT4232H based board/module
+#
+
+source [find interface/ftdi/ft232h-module-swd.cfg]
+#source [find interface/ftdi/minimodule-swd.cfg]
+
+transport select swd
+
+source [find target/nrf52.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/novena-internal-fpga.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/novena-internal-fpga.cfg
new file mode 100644
index 0000000..c36938c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/novena-internal-fpga.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Novena open hardware and F/OSS-friendly computing platform
+#
+# Design documentation:
+# http://www.kosagi.com/w/index.php?title=Novena_PVT_Design_Source
+#
+# +-------------+--------------+------+-------+---------+
+# | Pad name    | Schematic    | GPIO | sysfs | JTAG    |
+# +-------------+--------------+------+-------+---------+
+# | DISP0_DAT13 | FPGA_RESET_N | 5-07 |  135  | RESET_N |
+# | DISP0_DAT14 | FPGA_TCK     | 5-08 |  136  | TCK     |
+# | DISP0_DAT15 | FPGA_TDI     | 5-09 |  137  | TDI     |
+# | DISP0_DAT16 | FPGA_TDO     | 5-10 |  138  | TDO     |
+# | DISP0_DAT17 | FPGA_TMS     | 5-11 |  139  | TMS     |
+# +-------------+--------------+------+-------+---------+
+
+adapter driver sysfsgpio
+
+transport select jtag
+
+# TCK TMS TDI TDO
+sysfsgpio jtag_nums 136 139 137 138
+
+source [find cpld/xilinx-xc6s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/npcx_evb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/npcx_evb.cfg
new file mode 100644
index 0000000..4f28bc9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/npcx_evb.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Nuvoton NPCX Evaluation Board
+
+source [find interface/jlink.cfg]
+transport select swd
+
+source [find target/npcx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nuclei-evalsoc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nuclei-evalsoc.cfg
new file mode 100644
index 0000000..2f941c0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nuclei-evalsoc.cfg
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed 1000
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+# change to on to enable cJTAG 2-wire OSCAN1 protocol
+# ocan1_mode -> nscan1_mode in 2023.10 Nuclei OpenOCD release
+# ftdi oscan1_mode off
+ftdi nscan1_mode off
+
+## bindto 0.0.0.0 can be used to cover all available interfaces.
+## Uncomment bindto line to enable remote machine debug
+# bindto 0.0.0.0
+
+# specify adapter serial to select a ftdi chip if you have multiple jtag devices
+# adapter serial "FT6S9RD6"
+
+transport select jtag
+
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
+
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME nuspi 0x20000000 0 0 0 $_TARGETNAME
+
+init
+
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+}
+halt
+
+# We must turn on this because otherwise the IDE version debug cannot download the program into flash
+
+flash protect 0 0 last off
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/numato_mimas_a7.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/numato_mimas_a7.cfg
new file mode 100644
index 0000000..82d6a56
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/numato_mimas_a7.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Numato Mimas A7 - Artix 7 FPGA Board
+#
+# https://numato.com/product/mimas-a7-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet
+#
+# Note: Connect external DC power supply if programming a heavy design onto FPGA.
+#       Programming while powering via USB may lead to programming failure.
+#       Therefore, prefer external power supply.
+
+adapter driver ftdi
+ftdi device_desc "Mimas Artix 7 FPGA Module"
+ftdi vid_pid 0x2a19 0x1009
+
+# channel 0 is for custom purpose by users (like uart, fifo etc)
+# channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers)
+ftdi channel 1
+ftdi tdo_sample_edge falling
+
+
+# FTDI Pin Layout
+#
+# +--------+-------+-------+-------+-------+-------+-------+-------+
+# | DBUS7  | DBUS6 | DBUS5 | DBUS4 | DBUS3 | DBUS2 | DBUS1 | DBUS0 |
+# +--------+-------+-------+-------+-------+-------+-------+-------+
+# | PROG_B | OE_N  |  NC   |  NC   |  TMS  |  TDO  |  TDI  |  TCK  |
+# +--------+-------+-------+-------+-------+-------+-------+-------+
+#
+# OE_N is JTAG buffer output enable signal (active-low)
+# PROG_B is not used, so left as input to FTDI.
+#
+ftdi layout_init 0x0008 0x004b
+reset_config none
+adapter speed 30000
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/numato_opsis.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/numato_opsis.cfg
new file mode 100644
index 0000000..ea07ff3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/numato_opsis.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://opsis.hdmi2usb.tv
+#
+# The Numato Opsis is an FPGA based, open video platform.
+#
+# The board is supported via ixo-usb-jtag project. See the
+# interface/usb-jtag.cfg for more information.
+
+source [find interface/usb-jtag.cfg]
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp/frdm-kv11z-jlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp/frdm-kv11z-jlink.cfg
new file mode 100644
index 0000000..725a37b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp/frdm-kv11z-jlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration file for NXP FRDM-KV11Z development boards.
+#
+# This configuration file is only for FRDM-KV11Z development boards with the
+# SEGGER J-Link OpenSDA firmware, see:
+# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/
+
+source [find interface/jlink.cfg]
+
+# Set working area size to 16 KiB.
+set WORKAREASIZE 0x4000
+
+# Set the chip name.
+set CHIPNAME kv11z
+
+transport select swd
+
+source [find target/kx.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp/frdm-kv31f-jlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp/frdm-kv31f-jlink.cfg
new file mode 100644
index 0000000..e55a01c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp/frdm-kv31f-jlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration file for NXP FRDM-KV31F development boards.
+#
+# This configuration file is only for FRDM-KV31F development boards with the
+# SEGGER J-Link OpenSDA firmware, see:
+# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/
+
+source [find interface/jlink.cfg]
+
+# Set working area size to 32 KiB.
+set WORKAREASIZE 0x8000
+
+# Set the chip name.
+set CHIPNAME kv31f
+
+transport select swd
+
+source [find target/kx.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_frdm-k64f.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_frdm-k64f.cfg
new file mode 100644
index 0000000..1581c95
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_frdm-k64f.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an NXP Freedom eval board with a single MK64FN1M0VLL12 chip.
+# https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# Set working area to 16 KiB
+set WORKAREASIZE 0x4000
+
+set CHIPNAME k64f
+reset_config srst_only
+
+source [find target/kx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_frdm-ls1012a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_frdm-ls1012a.cfg
new file mode 100644
index 0000000..17a50c9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_frdm-ls1012a.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP FRDM-LS1012A (Freedom)
+#
+
+#
+# NXP Kinetis K20
+#
+source [find interface/cmsis-dap.cfg]
+transport select jtag
+
+# Also offers a 10-pin 0.05" CoreSight JTAG connector.
+
+source [find target/ls1012a.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_imx7sabre.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_imx7sabre.cfg
new file mode 100644
index 0000000..9b0c743
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_imx7sabre.cfg
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP IMX7SABRE board
+# use on-board JTAG header
+transport select jtag
+
+# set a safe speed, can be overridden
+adapter speed 1000
+
+# reset configuration has TRST and SRST support
+reset_config trst_and_srst srst_push_pull
+# need at least 100ms delay after SRST release for JTAG
+adapter srst delay 100
+
+# source the target file
+source [find target/imx7.cfg]
+# import mrw proc
+source [find mem_helper.tcl]
+
+# function to disable the on-chip watchdog
+proc imx7_disable_wdog { } {
+        # echo "disable watchdog power-down counter"
+        mwh phys 0x30280008 0x00
+}
+
+proc imx7_uart_dbgconf { } {
+	# disable response to debug_req signal for uart1
+	mww phys 0x308600b4 0x0a60
+}
+
+proc check_bits_set_32 { addr mask } {
+    while { [expr {[mrw $addr] & $mask} == 0] } { }
+}
+
+proc apply_dcd { } {
+    # echo "apply dcd"
+
+    mww phys 0x30340004 0x4F400005
+    # Clear then set bit30 to ensure exit from DDR retention
+    mww phys 0x30360388 0x40000000
+    mww phys 0x30360384 0x40000000
+
+    mww phys 0x30391000 0x00000002
+    mww phys 0x307a0000 0x01040001
+    mww phys 0x307a01a0 0x80400003
+    mww phys 0x307a01a4 0x00100020
+    mww phys 0x307a01a8 0x80100004
+    mww phys 0x307a0064 0x00400046
+    mww phys 0x307a0490 0x00000001
+    mww phys 0x307a00d0 0x00020083
+    mww phys 0x307a00d4 0x00690000
+    mww phys 0x307a00dc 0x09300004
+    mww phys 0x307a00e0 0x04080000
+    mww phys 0x307a00e4 0x00100004
+    mww phys 0x307a00f4 0x0000033f
+    mww phys 0x307a0100 0x09081109
+    mww phys 0x307a0104 0x0007020d
+    mww phys 0x307a0108 0x03040407
+    mww phys 0x307a010c 0x00002006
+    mww phys 0x307a0110 0x04020205
+    mww phys 0x307a0114 0x03030202
+    mww phys 0x307a0120 0x00000803
+    mww phys 0x307a0180 0x00800020
+    mww phys 0x307a0184 0x02000100
+    mww phys 0x307a0190 0x02098204
+    mww phys 0x307a0194 0x00030303
+    mww phys 0x307a0200 0x00000016
+    mww phys 0x307a0204 0x00171717
+    mww phys 0x307a0214 0x04040404
+    mww phys 0x307a0218 0x0f040404
+    mww phys 0x307a0240 0x06000604
+    mww phys 0x307a0244 0x00000001
+    mww phys 0x30391000 0x00000000
+    mww phys 0x30790000 0x17420f40
+    mww phys 0x30790004 0x10210100
+    mww phys 0x30790010 0x00060807
+    mww phys 0x307900b0 0x1010007e
+    mww phys 0x3079009c 0x00000d6e
+    mww phys 0x30790020 0x08080808
+    mww phys 0x30790030 0x08080808
+    mww phys 0x30790050 0x01000010
+    mww phys 0x30790050 0x00000010
+
+    mww phys 0x307900c0 0x0e407304
+    mww phys 0x307900c0 0x0e447304
+    mww phys 0x307900c0 0x0e447306
+
+    check_bits_set_32 0x307900c4 0x1
+
+    mww phys 0x307900c0 0x0e447304
+    mww phys 0x307900c0 0x0e407304
+
+
+    mww phys 0x30384130 0x00000000
+    mww phys 0x30340020 0x00000178
+    mww phys 0x30384130 0x00000002
+    mww phys 0x30790018 0x0000000f
+
+    check_bits_set_32 0x307a0004 0x1
+}
+
+# disable internal reset-assert handling to
+# allow reset-init to work
+$_TARGETNAME.0 configure -event reset-assert ""
+$_TARGETNAME.1 configure -event reset-assert ""
+$_TARGETNAME_2 configure -event reset-assert ""
+
+$_TARGETNAME.0 configure -event reset-init {
+    global _CHIPNAME
+    imx7_disable_wdog
+    imx7_uart_dbgconf
+    apply_dcd
+    $_CHIPNAME.dap memaccess 0
+}
+
+target smp $_TARGETNAME.0 $_TARGETNAME.1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_imx8mp-evk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_imx8mp-evk.cfg
new file mode 100644
index 0000000..4e101d4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_imx8mp-evk.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for NXP IMX8M Plus EVK
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+
+# board has an i.MX8MP with 4 Cortex-A55 cores
+set CHIPNAME imx8mp
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8mp.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_lpc-link2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_lpc-link2.cfg
new file mode 100644
index 0000000..52f13fa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_lpc-link2.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP LPC-Link2
+#
+# http://www.nxp.com/board/OM13054.html
+# https://www.lpcware.com/lpclink2
+# http://embeddedartists.com/products/lpcxpresso/lpclink2.php
+#
+
+source [find target/lpc4370.cfg]
+
+# W25Q80BVSSIG w/ 1 MB flash
+flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_mcimx8m-evk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_mcimx8m-evk.cfg
new file mode 100644
index 0000000..bcd0f67
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_mcimx8m-evk.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for NXP MC-IMX8M-EVK
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+# board has an i.MX8MQ with 4 Cortex-A53 cores
+set CHIPNAME imx8mq
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_rdb-ls1046a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_rdb-ls1046a.cfg
new file mode 100644
index 0000000..fde1829
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_rdb-ls1046a.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1046ARDB (Reference Design Board)
+# This is for the "console" USB port on the front panel
+# You must ensure that SW4-7 is in the "off" position
+
+# NXP K20
+# The firmware implements the old CMSIS-DAP v1 USB HID interface
+# You must pass --enable-cmsis-dap to ./configure to enable it
+source [find interface/cmsis-dap.cfg]
+
+transport select jtag
+reset_config srst_only
+
+source [find target/ls1046a.cfg]
+
+# The adapter can't handle 10MHz
+adapter speed 5000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_rdb-ls1088a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_rdb-ls1088a.cfg
new file mode 100644
index 0000000..40483f2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/nxp_rdb-ls1088a.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1088ARDB (Reference Design Board)
+# This is for the "main" JTAG connector J55
+
+transport select jtag
+reset_config srst_only
+
+# To access the CPLD, populate J48 and add `-c 'set CWTAP 1'` to your command
+# line. At the time of this writing, programming is unsupported.
+if { [info exists CWTAP] } {
+	source [find cpld/altera-epm240.cfg]
+} else {
+	source [find target/ls1088a.cfg]
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_LPC2378STK.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_LPC2378STK.cfg
new file mode 100644
index 0000000..23588ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_LPC2378STK.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#####################################################
+# Olimex LPC2378STK eval board
+#
+# http://olimex.com/dev/lpc-2378stk.html
+#
+# Author: Sten, debian@sansys-electronic.com
+#####################################################
+#
+
+source [find target/lpc2378.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_lpc_h2148.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_lpc_h2148.cfg
new file mode 100644
index 0000000..96ae405
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_lpc_h2148.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex LPC-H2148 eval board
+#
+# http://www.olimex.com/dev/lpc-h2148.html
+#
+
+source [find target/lpc2148.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_sam7_ex256.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_sam7_ex256.cfg
new file mode 100644
index 0000000..9924f27
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_sam7_ex256.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
+
+source [find target/at91sam7x256.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_sam7_la2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_sam7_la2.cfg
new file mode 100644
index 0000000..d91432b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_sam7_la2.cfg
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam7a2.cfg]
+
+# delays needed to get stable reads of cpu state
+jtag_ntrst_delay 10
+adapter srst delay 200
+
+# board uses pullup and connects only srst
+reset_config srst_open_drain
+
+# srst is connected to NRESET of CPU and fully resets everything...
+reset_config srst_only srst_pulls_trst
+
+adapter speed 1
+$_TARGETNAME configure -event reset-start {
+	adapter speed 1
+}
+
+$_TARGETNAME configure -event reset-init {
+	# init script from http://www.mikrocontroller.net/topic/107462
+	# AT91SAM7A2
+	# AMC (advanced memory controller)
+
+	echo "setting up AMC"
+	# AMC_CS0 - FLASH 1MB (0x40000000-0x400FFFFF) + DM9000E (0x40100000)
+	mww 0xFFE00000 0x40003EBD
+
+	# AMC_CS1 - RAM low 2MB (0x40400000-0x405FFFFF)
+	mww 0xFFE00004 0x404030A9
+
+	# AMC_CS2 - RAM high 2MB (0x40800000-0x405FFFFF)
+	#mww 0xFFE00008 0x404030A9
+	# changed to  0x40_8_
+	mww 0xFFE00008 0x408030A9
+
+	# AMC_MCR
+	mww 0xFFE00024 0x00000004
+
+	# AMC_RCR force remap
+	mww 0xFFE00020 0x00000001
+
+	echo "set up AMC"
+	sleep 100
+
+	# the following base addresses from the original script did not correspond to those from datasheet
+	# changed bases from 0xFF000000 to 0xFFF00000
+
+	# disable watchdog, to prevent unwanted resets
+	mww 0xFFFA0068 0x00000000
+	echo "disabled watchdog"
+
+	sleep 50
+
+	# disable PLL
+	mww 0xFFFEC004 0x18070004
+
+	# PLL = 10 ==> Coreclock = 6Mhz*10/2 = 30 Mhz
+	mww 0xFFFEC010 0x762D800A
+
+	# enable PLL
+	mww 0xFFFEC000 0x23050004
+	echo "set up pll"
+
+	sleep 100
+	adapter speed 5000
+}
+
+$_TARGETNAME arm7_9 dcc_downloads enable
+$_TARGETNAME arm7_9 fast_memory_access enable
+
+# remap:  ram at 0, flash at 0x40000000, like reset-init above does
+$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1
+flash bank onboard.flash cfi 0x40000000 0x00100000 2 2 at91sam7a2.cpu
+
+# boot: ram at 0x300000, flash at 0x0, useful if board is in funny configuration
+#$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
+#flash bank onboard1.flash cfi 0x00000000 0x00100000 2 2 at91sam7a2.cpu
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_sam9_l9260.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_sam9_l9260.cfg
new file mode 100644
index 0000000..7491a0e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_sam9_l9260.cfg
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Olimex SAM9-L9260 Development Board
+#
+# http://www.olimex.com/dev/sam9-L9260.html
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+#                     PMC configured for external 18.432 MHz crystal
+#
+# 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
+# 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
+# Dataflash : 1 x Atmel AT45DB161D, 16Mbit
+#
+################################################################################
+
+source [find target/at91sam9260.cfg]
+
+# NTRST_E jumper is enabled by default, so we don't need to override the reset
+# config.
+#reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+	# At reset, CPU runs at 32.768 kHz.  JTAG frequency must be 6 times slower if
+	# RCLK is not supported.
+	jtag_rclk 5
+	halt
+
+	# RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may
+	# be enabled... use physical address.
+	mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
+
+	##
+	# Clock configuration for 99.328 MHz main clock.
+	##
+    echo "Setting up clock"
+	mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup
+	sleep 20                  ;# wait 20 ms (need 15.6 ms for startup)
+	mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz)
+	sleep 10                  ;# wait 10 ms
+	mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
+	sleep 20                  ;# wait 20 ms (need 1.9 ms for startup)
+	mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
+	sleep 10                  ;# wait 10 ms
+	mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
+
+	# Increase JTAG speed to 6 MHz if RCLK is not supported.
+	jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
+
+	##
+	# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
+	##
+    echo "Configuring SDRAM"
+	mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
+	mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
+
+	mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
+
+	mww 0xffffea00 0x1        ;# SDRAMC_MR : issue NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2        ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4        ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3        ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0        ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+
+	mww 0xffffea04 0x2b6      ;# SDRAMC_TR : set refresh timer count to 7 us
+
+    ##
+    # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
+    ##
+    echo "Configuring NAND flash"
+    mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
+    mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+    mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
+    mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
+    mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
+    mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
+
+    mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
+
+    mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
+    mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
+    mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
+    mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+                               #             3 TDF cycles, no optimization
+
+    mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
+    mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
+
+    nand probe at91sam9260.flash
+
+    ##
+    # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
+    ##
+    echo "Setting up dataflash"
+    mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
+                               #            2(SPI0_SPCK), and 11(SPI0_NPCS1)
+    mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
+    mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
+    mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
+
+    mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
+    mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
+    mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
+
+    mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
+                               #             250ns delay before SPCK, 250ns b/n tx
+
+    mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
+    mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
+}
+
+nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800
+at91sam9 cle 0 22
+at91sam9 ale 0 21
+at91sam9 rdy_busy 0 0xfffff800 13
+at91sam9 ce 0 0xfffff800 14
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_h103.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_h103.cfg
new file mode 100644
index 0000000..92ca7ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_h103.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Olimex STM32-H103 eval board
+# http://olimex.com/dev/stm32-h103.html
+
+# Work-area size (RAM size) = 20kB for STM32F103RB device
+set WORKAREASIZE 0x5000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_h107.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_h107.cfg
new file mode 100644
index 0000000..c199cdc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_h107.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex STM32-H107
+#
+# http://olimex.com/dev/stm32-h107.html
+#
+
+# Work-area size (RAM size) = 64kB for STM32F107VC device
+set WORKAREASIZE 0x10000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_h405.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_h405.cfg
new file mode 100644
index 0000000..f2f1d7f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_h405.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Olimex STM32-H405 eval board
+# https://www.olimex.com/Products/ARM/ST/STM32-H405/
+
+# Work-area size (RAM size) = 128kB for STM32F405RG device
+set WORKAREASIZE 0x20000
+
+source [find target/stm32f4x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_p107.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_p107.cfg
new file mode 100644
index 0000000..9511030
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/olimex_stm32_p107.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex STM32-P107
+#
+# http://olimex.com/dev/stm32-p107.html
+#
+
+# Work-area size (RAM size) = 64kB for STM32F107VC device
+set WORKAREASIZE 0x10000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/omap2420_h4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/omap2420_h4.cfg
new file mode 100644
index 0000000..ec16965
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/omap2420_h4.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OMAP2420 SDP board ("H4")
+
+source [find target/omap2420.cfg]
+
+# NOTE: this assumes you're *NOT* using a TI-14 connector.
+reset_config trst_and_srst separate
+
+# Board configs can vary a *LOT* ... parts, jumpers, etc.
+# This GP board boots from cs0 using NOR (2x32M), and also
+# has 64M NAND on cs6.
+flash bank h4.u10 cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
+flash bank h4.u11 cfi 0x06000000 0x02000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/openrd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/openrd.cfg
new file mode 100644
index 0000000..f6c8317
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/openrd.cfg
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell OpenRD
+
+source [find interface/ftdi/openrd.cfg]
+source [find target/feroceon.cfg]
+
+adapter speed 2000
+
+$_TARGETNAME configure \
+	-work-area-phys 0x10000000 \
+	-work-area-size 65536 \
+	-work-area-backup 0
+
+arm7_9 dcc_downloads enable
+
+# this assumes the hardware default peripherals location before u-Boot moves it
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME orion 0 0xd8000000
+
+proc openrd_init { } {
+
+	# We need to assert DBGRQ while holding nSRST down.
+	# However DBGACK will be set only when nSRST is released.
+	# Furthermore, the JTAG interface doesn't respond at all when
+	# the CPU is in the WFI (wait for interrupts) state, so it is
+	# possible that initial tap examination failed.  So let's
+	# re-examine the target again here when nSRST is asserted which
+	# should then succeed.
+	adapter assert srst
+	feroceon.cpu arp_examine
+	halt 0
+	adapter deassert srst
+	wait_halt
+
+	arm mcr 15 0 0 1 0 0x00052078
+
+	mww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register
+	mww 0xD0001404 0x37543000 ;#  Dunit Control Low Register
+	mww 0xD0001408 0x22125451 ;#  DDR SDRAM Timing (Low) Register
+	mww 0xD000140C 0x00000A33 ;#  DDR SDRAM Timing (High) Register
+	mww 0xD0001410 0x000000CC ;#  DDR SDRAM Address Control Register
+	mww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register
+	mww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register
+	mww 0xD000141C 0x00000C52 ;#  DDR SDRAM Mode Register
+	mww 0xD0001420 0x00000004 ;#  DDR SDRAM Extended Mode Register
+	mww 0xD0001424 0x0000F17F ;#  Dunit Control High Register
+	mww 0xD0001428 0x00085520 ;#  Dunit Control High Register
+	mww 0xD000147c 0x00008552 ;#  Dunit Control High Register
+	mww 0xD0001504 0x0FFFFFF1 ;#  CS0n Size Register
+	mww 0xD0001508 0x10000000 ;#  CS1n Base Register
+	mww 0xD000150C 0x0FFFFFF5 ;#  CS1n Size Register
+	mww 0xD0001514 0x00000000 ;#  CS2n Size Register
+	mww 0xD000151C 0x00000000 ;#  CS3n Size Register
+	mww 0xD0001494 0x00120012 ;#  DDR2 SDRAM ODT Control (Low) Register
+	mww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister
+	mww 0xD000149C 0x0000E40F ;#  DDR2 Dunit ODT Control Register
+	mww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register
+	mww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+
+	mww 0xD0010000 0x01111111 ;#  MPP  0 to 7
+	mww 0xD0010004 0x11113322 ;#  MPP  8 to 15
+	mww 0xD0010008 0x00001111 ;#  MPP 16 to 23
+
+	mww 0xD0010418 0x003E07CF ;#  NAND Read Parameters REgister
+	mww 0xD001041C 0x000F0F0F ;#  NAND Write Parameters Register
+	mww 0xD0010470 0x01C7D943 ;#  NAND Flash Control Register
+
+}
+
+proc openrd_reflash_uboot { } {
+
+	# reflash the u-Boot binary and reboot into it
+	openrd_init
+	nand probe 0
+	nand erase 0 0x0 0xa0000
+	nand write 0 uboot.bin 0 oob_softecc_kw
+	resume
+
+}
+
+proc openrd_load_uboot { } {
+
+	# load u-Boot into RAM and execute it
+	openrd_init
+	load_image uboot.elf
+	verify_image uboot.elf
+	resume 0x00600000
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/or1k_generic.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/or1k_generic.cfg
new file mode 100644
index 0000000..b6cf3a0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/or1k_generic.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# If you want to use the VJTAG TAP or the XILINX BSCAN,
+# you must set your FPGA TAP ID here
+
+set FPGATAPID 0x020b30dd
+
+# Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN)
+if { [info exists TAP_TYPE] == 0} {
+   set TAP_TYPE VJTAG
+}
+
+# Set your chip name
+set CHIPNAME or1200
+
+source [find target/or1k.cfg]
+
+# Set the servers polling period to 1ms (needed to JSP Server)
+poll_period 1
+
+# Set the adapter speed
+adapter speed 3000
+
+# Enable the target description feature
+gdb target_description enable
+
+# Add a new register in the cpu register list. This register will be
+# included in the generated target descriptor file.
+# format is addreg [name] [address] [feature] [reg_group]
+addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
+
+# Override default init_reset
+proc init_reset {mode} {
+	soft_reset_halt
+	resume
+}
+
+# Target initialization
+init
+echo "Halting processor"
+halt
+
+foreach name [target names] {
+	set y [$name cget -endian]
+	set z [$name cget -type]
+	puts [format "Chip is %s, Endian: %s, type: %s" \
+	      $name $y $z]
+}
+
+set c_blue  "\033\[01;34m"
+set c_reset "\033\[0m"
+
+puts [format "%sTarget ready...%s" $c_blue $c_reset]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/osk5912.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/osk5912.cfg
new file mode 100644
index 0000000..0759a27
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/osk5912.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://omap.spectrumdigital.com/osk5912/
+
+source [find target/omap5912.cfg]
+
+# NOTE: this assumes you're using the ARM 20-pin ("Multi-ICE")
+# JTAG connector, and accordingly have J1 connecting pins 1 & 2.
+# The TI-14 pin needs "trst_only", and J1 connecting 2 & 3.
+reset_config trst_and_srst separate
+
+# NOTE:  boards with XOMAP parts wire nSRST to nPWRON_RESET.
+# That resets everything -- including JTAG and EmbeddedICE.
+# So they must use "reset_config srst_pulls_trst".
+
+# NOTE:  an expansion board could add a trace connector ... if
+# it does, change this appropriately.  And reset_config too,
+# assuming JTAG_DIS reroutes JTAG to that connector.
+etm config $_TARGETNAME 8 demultiplexed full dummy
+etm_dummy config $_TARGETNAME
+
+# standard boards populate two 16 MB chips, but manufacturing
+# options or an expansion board could change this config.
+flash bank osk.u1 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
+flash bank osk.u2 cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
+
+proc osk5912_init {} {
+	omap5912_reset
+
+	# detect flash
+	flash probe 0
+	flash probe 1
+}
+$_TARGETNAME configure -event reset-init { osk5912_init }
+
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/phone_se_j100i.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/phone_se_j100i.cfg
new file mode 100644
index 0000000..70387ee
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/phone_se_j100i.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Sony Ericsson J100I Phone
+#
+# more information can be found on
+# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
+#
+source [find target/ti_calypso.cfg]
+
+# external flash
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/phytec_lpc3250.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/phytec_lpc3250.cfg
new file mode 100644
index 0000000..036b16f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/phytec_lpc3250.cfg
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/lpc3250.cfg]
+
+adapter srst delay 200
+jtag_ntrst_delay 1
+adapter speed 200
+reset_config trst_and_srst separate
+
+arm7_9 dcc_downloads enable
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+
+$_TARGETNAME configure -event reset-start {
+             arm7_9 fast_memory_access disable
+             adapter speed 200
+}
+
+$_TARGETNAME configure -event reset-end {
+             adapter speed 6000
+             arm7_9 fast_memory_access enable
+}
+
+$_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
+
+# Bare-bones initialization of core clocks and SDRAM
+proc phytec_lpc3250_init { } {
+        # Set clock dividers
+        #   ARMCLK = 266.5 MHz
+        #   HCLK   = 133.25 MHz
+        #   PERIPHCLK = 13.325 MHz
+        mww 0x400040BC 0
+        mww 0x40004050 0x140
+        mww 0x40004040 0x4D
+        mww 0x40004058 0x16250
+
+        # Init PLLs
+        mww 0x40004044 0x006
+        sleep 1 busy
+        mww 0x40004044 0x106
+        sleep 1 busy
+        mww 0x40004044 0x006
+        sleep 1 busy
+        mww 0x40004048 0x2
+
+        # Init SDRAM with 133 MHz timings
+        mww 0x40028134 0x00FFFFFF
+        mww 0x4002802C 0x00000008
+
+        mww 0x31080000 1
+        mww 0x31080008 0
+        mww 0x40004068 0x1C000
+        mww 0x31080028 0x11
+
+        mww 0x31080400 0
+        mww 0x31080440 0
+        mww 0x31080460 0
+        mww 0x31080480 0
+
+        # Delays
+        mww 0x31080030 1
+        mww 0x31080034 6
+        mww 0x31080038 10
+        mww 0x31080044 1
+        mww 0x31080048 9
+        mww 0x3108004C 12
+        mww 0x31080050 10
+        mww 0x31080054 1
+        mww 0x31080058 1
+        mww 0x3108005C 0
+
+        mww 0x31080100 0x5680
+        mww 0x31080104 0x302
+
+        # Init sequence
+        mww 0x31080020 0x193
+        sleep 1 busy
+        mww 0x31080024 1
+        mww 0x31080020 0x113
+        sleep 1 busy
+        mww 0x31080020 0x013
+        sleep 1 busy
+        mww 0x31080024 65
+        mww 0x31080020 0x093
+        mdw 0x80020000
+        mww 0x31080020 0x013
+
+        # SYS_CTRL remapping
+        mww 0x40004014 1
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pic-p32mx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pic-p32mx.cfg
new file mode 100644
index 0000000..0703220
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pic-p32mx.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Olimex PIC-P32MX has a PIC32MX
+
+set CPUTAPID 0x40916053
+source [find target/pic32mx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pico-debug.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pico-debug.cfg
new file mode 100644
index 0000000..ba59f86
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pico-debug.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# pico-debug is a virtual CMSIS-DAP debug adapter
+# it runs on the very same RP2040 target being debugged without additional hardware
+# https://github.com/majbthrd/pico-debug
+
+source [find interface/cmsis-dap.cfg]
+adapter speed 4000
+
+set CHIPNAME rp2040
+source [find target/rp2040-core0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pipistrello.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pipistrello.cfg
new file mode 100644
index 0000000..17584a0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pipistrello.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://pipistrello.saanlima.com/
+
+source [find interface/ftdi/pipistrello.cfg]
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
+
+# example command to write bitstream, soft-cpu bios and runtime:
+# openocd -f board/pipistrello.cfg -c "init;\
+# jtagspi_init 0 bscan_spi_xc6slx45.bit;\
+# jtagspi_program bitstream-pistrello.bin 0;\
+# jtagspi_program bios.bin 0x170000;\
+# jtagspi_program runtime.fbi 0x180000;\
+# xc6s_program xc6s.tap;\
+# exit"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/propox_mmnet1001.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/propox_mmnet1001.cfg
new file mode 100644
index 0000000..0e12604
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/propox_mmnet1001.cfg
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+## Chip:
+set CHIPNAME at91sam9260
+set CPUTAPID 0x0792603f
+set ENDIAN little
+source [find target/at91sam9260.cfg]
+
+$_TARGETNAME configure -event reset-init {at91sam_init}
+
+
+proc at91sam_init { } {
+
+	# at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
+	jtag_rclk 4
+
+	# Enable user reset and disable watchdog
+	mww 0xfffffd08 0xa5000501         ;# RSTC_MR : enable user reset
+	mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	# Oscillator setup
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator (18.432 MHz)
+	sleep 20                          ;# wait 20 ms
+	mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+	sleep 10                          ;# wait 10 ms
+
+	# now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz
+	jtag_rclk 2000
+
+	mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
+	sleep 20                          ;# wait 20 ms
+	mww 0xfffffc2c 0x207c3f0c         ;# CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)
+	sleep 10                          ;# wait 10 ms
+	mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler
+	sleep 10                          ;# wait 10 ms
+	mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected
+	sleep 10                          ;# wait 10 ms
+
+	# now we are running at 198.656 MHz kHz => full speed jtag
+	jtag_rclk 30000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	# Configure PIO Controller for SDRAM data-lines D16-D31
+	# PC16-PC31 = Peripheral A: D16-D32
+	mww 0xfffff844 0xffff0000	;# Interrupt Disable
+	mww 0xfffff854 0xffff0000	;# Multi-Drive Disable
+	mww 0xfffff860 0xffff0000	;# Pull-Up Disable
+	mww 0xfffff870 0xffff0000	;# PIO_ASR : Select peripheral A function for D15..D31
+	mww 0xfffff804 0xffff0000	;# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)
+	mww 0xfffffc10 0x00000010	;# Enable PIO-C Clock in PMC (PID=4)
+
+	# SD-Ram setup
+	mww 0xffffef1c 0x2			;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+	mww 0xffffea08 0x85227259	;# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))
+	mww 0xffffea00 0x1			;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2			;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (1st)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (3th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (4th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (5th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (6th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (7th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (8th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x3			;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0			;# SDRAMC_MR : Normal Mode
+	mww 0x20000000 0
+	mww 0xFFFFEA04 0x30d		;# SDRAM Refresh Time Register
+								 #  datasheet: 8k refresh cycles / 64 ms
+								 #  MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pxa255_sst.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pxa255_sst.cfg
new file mode 100644
index 0000000..8d00dfe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/pxa255_sst.cfg
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# A PXA255 test board with SST 39LF400A flash
+#
+# At reset the memory map is as follows. Note that
+# the memory map changes later on as the application
+# starts...
+#
+# RAM at 0x4000000
+# Flash at 0x00000000
+#
+source [find target/pxa255.cfg]
+
+# Target name is set by above
+$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
+
+# flash bank       [options]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
+
+proc pxa255_sst_init {} {
+	xscale cp15   15      0x00002001  ;#Enable CP0 and CP13 access
+	#
+	# setup GPIO
+	#
+	mww    0x40E00018  0x00008000  ;#CPSR0
+	sleep   20
+	mww    0x40E0001C  0x00000002  ;#GPSR1
+	sleep   20
+	mww    0x40E00020  0x00000008  ;#GPSR2
+	sleep   20
+	mww    0x40E0000C  0x00008000  ;#GPDR0
+	sleep   20
+	mww    0x40E00054  0x80000000  ;#GAFR0_L
+	sleep   20
+	mww    0x40E00058  0x00188010  ;#GAFR0_H
+	sleep   20
+	mww    0x40E0005C  0x60908018  ;#GAFR1_L
+	sleep   20
+	mww    0x40E0000C  0x0280E000  ;#GPDR0
+	sleep   20
+	mww    0x40E00010  0x821C88B2  ;#GPDR1
+	sleep   20
+	mww    0x40E00014  0x000F03DB  ;#GPDR2
+	sleep   20
+	mww    0x40E00000  0x000F03DB  ;#GPLR0
+	sleep   20
+
+
+	mww    0x40F00004  0x00000020  ;#PSSR
+	sleep   20
+
+	#
+	# setup memory controller
+	#
+	mww    0x48000008  0x01111998  ;#MSC0
+	sleep   20
+	mww    0x48000010  0x00047ff0  ;#MSC2
+	sleep   20
+	mww    0x48000014  0x00000000  ;#MECR
+	sleep   20
+	mww    0x48000028  0x00010504  ;#MCMEM0
+	sleep   20
+	mww    0x4800002C  0x00010504  ;#MCMEM1
+	sleep   20
+	mww    0x48000030  0x00010504  ;#MCATT0
+	sleep   20
+	mww    0x48000034  0x00010504  ;#MCATT1
+	sleep   20
+	mww    0x48000038  0x00004715  ;#MCIO0
+	sleep   20
+	mww    0x4800003C  0x00004715  ;#MCIO1
+	sleep   20
+	#
+	mww    0x48000004  0x03CA4018  ;#MDREF
+	sleep   20
+	mww    0x48000004  0x004B4018  ;#MDREF
+	sleep   20
+	mww    0x48000004  0x000B4018  ;#MDREF
+	sleep   20
+	mww    0x48000004  0x000BC018  ;#MDREF
+	sleep   20
+	mww    0x48000000  0x00001AC8  ;#MDCNFG
+	sleep   20
+
+	sleep   20
+
+	mww    0x48000000  0x00001AC9  ;#MDCNFG
+	sleep   20
+	mww    0x48000040  0x00000000  ;#MDMRS
+	sleep   20
+}
+
+$_TARGETNAME configure -event reset-init {pxa255_sst_init}
+
+reset_config trst_and_srst
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+#xscale debug_handler 0  0xFFFF0800      ;# debug handler base address
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/quark_d2000_refboard.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/quark_d2000_refboard.cfg
new file mode 100644
index 0000000..3af5735
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/quark_d2000_refboard.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Quark microcontroller D2000 Reference Board (web search for doc num 333582)
+
+# the board has an onboard FTDI FT232H chip
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6014
+ftdi channel 0
+
+ftdi layout_init 0x0000 0x030b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0100
+
+source [find target/quark_d20xx.cfg]
+
+adapter speed 1000
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/quark_x10xx_board.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/quark_x10xx_board.cfg
new file mode 100644
index 0000000..aa6adaf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/quark_x10xx_board.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# There are many Quark boards that can host the quark_x10xx SoC
+# Galileo is an example board
+
+source [find target/quark_x10xx.cfg]
+
+#default frequency but this can be adjusted at runtime
+adapter speed 4000
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/quicklogic_quickfeather.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/quicklogic_quickfeather.cfg
new file mode 100644
index 0000000..b522eff
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/quicklogic_quickfeather.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# QuickLogic EOS S3 QuickFeather
+# https://www.quicklogic.com/products/eos-s3/quickfeather-development-kit/
+
+source [find target/eos_s3.cfg]
+
+reset_config srst_only
+
+transport select swd
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/radiona_ulx3s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/radiona_ulx3s.cfg
new file mode 100644
index 0000000..eb9b027
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/radiona_ulx3s.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Radiona ULX3S
+# https://radiona.org/ulx3s/
+# Currently there are following board variants:
+# CS-ULX3S-01 - LFE5U 12F
+# CS-ULX3S-02 - LFE5U 45F
+# CS-ULX3S-03 - LFE5U 85F
+#
+# two JTAG interfaces:
+# - US1, micro USB port connected to FT231XQ
+#   This interface should be used with following config:
+#        interface/ft232r/radiona_ulx3s.cfg
+# - J4, 6 pin connector
+#
+# Both of this interfaces share the JTAG lines (TDI, TMS, TCK, TDO) between
+# Lattice ECP5 FPGA chip and ESP32 WiFi controller.
+# Note: TRST_N of the ESP32 is pulled up by default and can be pulled down over
+# J3 interface.
+# See schematics for more information:
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v314.pdf
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v315.pdf
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf
+
+source [find interface/ft232r/radiona_ulx3s.cfg]
+source [find fpga/lattice_ecp5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/redbee.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/redbee.cfg
new file mode 100644
index 0000000..714dfdc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/redbee.cfg
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/mc13224v.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg
new file mode 100644
index 0000000..2d98cc5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Achilles Instant-Development Kit Arria 10 SoC SoM
+# https://www.reflexces.com/products-solutions/achilles-instant-development-kit-arria-10-soc-som
+#
+
+if { [info exists USE_EXTERNAL_DEBUGGER] } {
+	echo "Using external debugger"
+} else {
+	source [find interface/altera-usb-blaster2.cfg]
+	usb_blaster device_desc "Arria10 IDK"
+}
+
+source [find fpga/altera-10m50.cfg]
+source [find target/altera_fpgasoc_arria10.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_dk-s7g2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_dk-s7g2.cfg
new file mode 100644
index 0000000..e310112
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_dk-s7g2.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Renesas Synergy DK-S7G2
+#
+
+source [find interface/jlink.cfg]
+transport select swd
+
+# XXX 19-pin SWD+TRACE connector also available
+
+# Synergy R7FS7G27H2A01CBD
+source [find target/renesas_s7g2.cfg]
+
+# 32 MB QSPI flash (Micron N25Q256A13EF840E)
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_falcon.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_falcon.cfg
new file mode 100644
index 0000000..c796f85
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_falcon.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Renesas R-Car V3U Falcon Board Config
+
+# The Falcon board comes with either an V3U SOC.
+
+echo "\nFalcon:"
+if { ![info exists SOC] } {
+	set SOC V3U
+}
+source [find target/renesas_rcar_gen3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_gr_peach.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_gr_peach.cfg
new file mode 100644
index 0000000..b3823ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_gr_peach.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ/A1H GR-Peach board
+
+reset_config srst_only
+
+source [find target/renesas_r7s72100.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_porter.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_porter.cfg
new file mode 100644
index 0000000..134e9ba
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_porter.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car M2 Evaluation Board
+
+set SOC M2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_salvator-xs.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_salvator-xs.cfg
new file mode 100644
index 0000000..1323c13
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_salvator-xs.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car Gen3 Salvator-X(S) Board Config
+
+# The Salvator-X(S) boards come with either an H3, M3W, or M3N SOC.
+
+echo "\nSalvator-X(S):"
+if { ![info exists SOC] } {
+	set SOC H3
+}
+source [find target/renesas_rcar_gen3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_silk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_silk.cfg
new file mode 100644
index 0000000..dd61e1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_silk.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car E2 Evaluation Board
+
+set SOC E2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_stout.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_stout.cfg
new file mode 100644
index 0000000..69a524b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/renesas_stout.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car H2 Evaluation Board
+
+set SOC H2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rigado_bmd300_ek.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rigado_bmd300_ek.cfg
new file mode 100644
index 0000000..601041d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rigado_bmd300_ek.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Rigado BMD-300 Evaluation Kit
+#
+# https://www.rigado.com/products/modules/bmd-300/
+#
+
+source [find interface/jlink.cfg]
+transport select swd
+adapter speed 1000
+
+source [find target/nrf52.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rpi3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rpi3.cfg
new file mode 100644
index 0000000..fd93a9d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rpi3.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the Raspberry Pi 3 board with BCM2837 chip
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837/README.md
+#
+# Enable JTAG GPIO on Raspberry Pi boards
+# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md
+
+source [find target/bcm2837.cfg]
+transport select jtag
+
+# Raspberry Pi boards only expose Test Reset (TRST) pin, no System Reset (SRST)
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rpi4b.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rpi4b.cfg
new file mode 100644
index 0000000..5b046af
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rpi4b.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the Raspberry Pi 4 model B board with BCM2711 chip
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md
+#
+# Enable JTAG GPIO on Raspberry Pi boards
+# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md
+
+source [find target/bcm2711.cfg]
+transport select jtag
+
+# Raspberry Pi boards only expose Test Reset (TRST) pin, no System Reset (SRST)
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rsc-w910.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rsc-w910.cfg
new file mode 100644
index 0000000..b07f940
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/rsc-w910.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Avalue RSC-W8910 sbc
+# http://www.avalue.com.tw/products/RSC-W910.cfm
+# 2MB NOR Flash
+# 64MB SDRAM
+# 128MB NAND Flash
+
+# Based on Nuvoton nuc910
+source [find target/nuc910.cfg]
+
+#
+# reset only behaves correctly if we use srst_pulls_trst
+#
+reset_config trst_and_srst srst_pulls_trst
+
+adapter speed 1000
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME
+
+set _NANDNAME $_CHIPNAME.nand
+nand device $_NANDNAME nuc910 $_TARGETNAME
+
+#
+# Target events
+#
+
+$_TARGETNAME configure -event reset-start {adapter speed 1000}
+
+$_TARGETNAME configure -event reset-init {
+	# switch on PLL for 200MHz operation
+	# running from 15MHz input clock
+
+	mww 0xB0000200 0x00000030 ;# CLKEN
+	mww 0xB0000204 0x00000f3c ;# CLKSEL
+	mww 0xB0000208 0x05007000 ;# CLKDIV
+	mww 0xB000020C 0x00004f24 ;# PLLCON0
+	mww 0xB0000210 0x00002b63 ;# PLLCON1
+	mww 0xB000000C 0x08817fa6 ;# MFSEL
+	sleep 10
+
+	# we are now running @ 200MHz
+	# enable all openocd speed tweaks
+
+	arm7_9 dcc_downloads enable
+	arm7_9 fast_memory_access enable
+	adapter speed 15000
+
+	# map nor flash to 0x20000000
+	# map sdram to 0x00000000
+
+	mww 0xb0001000 0x000530c1 ;# EBICON
+	mww 0xb0001004 0x40030084 ;# ROMCON
+	mww 0xb0001008 0x000010ee ;# SDCONF0
+	mww 0xb000100C 0x00000000 ;# SDCONF1
+	mww 0xb0001010 0x0000015b ;# SDTIME0
+	mww 0xb0001014 0x0000015b ;# SDTIME1
+	mww 0xb0001018 0x00000000 ;# EXT0CON
+	mww 0xb000101C 0x00000000 ;# EXT1CON
+	mww 0xb0001020 0x00000000 ;# EXT2CON
+	mww 0xb0001024 0x00000000 ;# EXT3CON
+	mww 0xb000102c 0x00ff0048 ;# CKSKEW
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sayma_amc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sayma_amc.cfg
new file mode 100644
index 0000000..b714609
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sayma_amc.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Sayma AMC is an FPGA board for the µTCA AMC format
+# The board is open hardware (CERN OHL) and the gateware and software
+# running on it are open source (ARTIQ, LGPLv3+).
+#
+# https://github.com/m-labs/sinara/wiki/Sayma
+#
+# It contains a Xilinx Kintex Ultrascale 040 FPGA (xcku040).
+# There is a SCANSTA112SM JTAG router on the board which is configured to
+# automatically add devices to the JTAG svcan chain when they are added.
+# Sayma AMC is usually combined with Sayma RTM (rear transition module)
+# which features an Artix 7 FPGA.
+
+adapter driver ftdi
+ftdi device_desc "Quad RS232-HS"
+ftdi vid_pid 0x0403 0x6011
+ftdi channel 0
+# Use this to distinguish multiple boards by topology
+#adapter usb location 5:1
+# sampling on falling edge generally seems to work and accelerates things but
+# is not fully tested
+#ftdi tdo_sample_edge falling
+# EN_USB_JTAG on ADBUS7: out, high
+# USB_nTRST on ADBUS4: out, high, but R46 is DNP
+ftdi layout_init 0x0098 0x008b
+#ftdi layout_signal EN_USB -data 0x0080
+#ftdi layout_signal nTRST -data 0x0010
+reset_config none
+
+adapter speed 5000
+
+transport select jtag
+
+# Add the RTM Artix to the chain. Note that this changes the PLD numbering.
+# Unfortunately openocd TAPs can't be disabled after they have been added and
+# before `init`.
+#source [find cpld/xilinx-xc7.cfg]
+
+set CHIP XCKU040
+source [find cpld/xilinx-xcu.cfg]
+
+set XILINX_USER1 0x02
+set XILINX_USER2 0x03
+set JTAGSPI_IR $XILINX_USER1
+source [find cpld/jtagspi.cfg]
+flash bank xcu.spi1 jtagspi 0 0 0 0 xcu.proxy $XILINX_USER2
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sheevaplug.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sheevaplug.cfg
new file mode 100644
index 0000000..734fab6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sheevaplug.cfg
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell SheevaPlug
+
+source [find interface/ftdi/sheevaplug.cfg]
+source [find target/feroceon.cfg]
+
+adapter speed 2000
+
+$_TARGETNAME configure \
+	-work-area-phys 0x10000000 \
+	-work-area-size 65536 \
+	-work-area-backup 0
+
+arm7_9 dcc_downloads enable
+
+# this assumes the hardware default peripherals location before u-Boot moves it
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME orion 0 0xd8000000
+
+proc sheevaplug_init { } {
+
+	# We need to assert DBGRQ while holding nSRST down.
+	# However DBGACK will be set only when nSRST is released.
+	# Furthermore, the JTAG interface doesn't respond at all when
+	# the CPU is in the WFI (wait for interrupts) state, so it is
+	# possible that initial tap examination failed.  So let's
+	# re-examine the target again here when nSRST is asserted which
+	# should then succeed.
+	adapter assert srst
+	feroceon.cpu arp_examine
+	halt 0
+	adapter deassert srst
+	wait_halt
+
+	arm mcr 15 0 0 1 0 0x00052078
+
+	mww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register
+	mww 0xD0001404 0x39543000 ;#  Dunit Control Low Register
+	mww 0xD0001408 0x22125451 ;#  DDR SDRAM Timing (Low) Register
+	mww 0xD000140C 0x00000833 ;#  DDR SDRAM Timing (High) Register
+	mww 0xD0001410 0x000000CC ;#  DDR SDRAM Address Control Register
+	mww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register
+	mww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register
+	mww 0xD000141C 0x00000C52 ;#  DDR SDRAM Mode Register
+	mww 0xD0001420 0x00000042 ;#  DDR SDRAM Extended Mode Register
+	mww 0xD0001424 0x0000F17F ;#  Dunit Control High Register
+	mww 0xD0001428 0x00085520 ;#  Dunit Control High Register
+	mww 0xD000147c 0x00008552 ;#  Dunit Control High Register
+	mww 0xD0001504 0x0FFFFFF1 ;#  CS0n Size Register
+	mww 0xD0001508 0x10000000 ;#  CS1n Base Register
+	mww 0xD000150C 0x0FFFFFF5 ;#  CS1n Size Register
+	mww 0xD0001514 0x00000000 ;#  CS2n Size Register
+	mww 0xD000151C 0x00000000 ;#  CS3n Size Register
+	mww 0xD0001494 0x003C0000 ;#  DDR2 SDRAM ODT Control (Low) Register
+	mww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister
+	mww 0xD000149C 0x0000F80F ;#  DDR2 Dunit ODT Control Register
+	mww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register
+	mww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+
+	mww 0xD0010000 0x01111111 ;#  MPP  0 to 7
+	mww 0xD0010004 0x11113322 ;#  MPP  8 to 15
+	mww 0xD0010008 0x00001111 ;#  MPP 16 to 23
+
+	mww 0xD0010418 0x003E07CF ;#  NAND Read Parameters REgister
+	mww 0xD001041C 0x000F0F0F ;#  NAND Write Parameters Register
+	mww 0xD0010470 0x01C7D943 ;#  NAND Flash Control Register
+
+}
+
+proc sheevaplug_reflash_uboot { } {
+
+	# reflash the u-Boot binary and reboot into it
+	sheevaplug_init
+	nand probe 0
+	nand erase 0 0x0 0xa0000
+	nand write 0 uboot.bin 0 oob_softecc_kw
+	resume
+
+}
+
+proc sheevaplug_reflash_uboot_env { } {
+
+	# reflash the u-Boot environment variables area
+	sheevaplug_init
+	nand probe 0
+	nand erase 0 0xa0000 0x40000
+	nand write 0 uboot-env.bin 0xa0000 oob_softecc_kw
+	resume
+
+}
+
+proc sheevaplug_load_uboot { } {
+
+	# load u-Boot into RAM and execute it
+	sheevaplug_init
+	load_image uboot.elf
+	verify_image uboot.elf
+	resume 0x00600000
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e31arty-cjtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e31arty-cjtag.cfg
new file mode 100644
index 0000000..58ba23a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e31arty-cjtag.cfg
@@ -0,0 +1,23 @@
+#
+# Be sure you include the speed and interface before this file
+# Example:
+# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty-cjtag.cfg"
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
+
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+  oscan1_ftdi_set_signal nSRST 0
+  oscan1_ftdi_set_signal nSRST z
+}
+halt
+flash protect 0 64 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e31arty-onboard-ftdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e31arty-onboard-ftdi.cfg
new file mode 100644
index 0000000..3d40cfa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e31arty-onboard-ftdi.cfg
@@ -0,0 +1,25 @@
+#
+# Be sure you include the speed and interface before this file
+# Example:
+# -c "adapter_khz 5000" -f "interface/ftdi/arty-onboard-ftdi.cfg" -f "board/sifive-e31arty-onboard-ftdi.cfg"
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 6; # -expected-id 0x0362d093
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+riscv use_bscan_tunnel 5
+
+# Uncomment if hardware has flash
+# flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+}
+halt
+# Uncomment if hardware has flash
+# flash protect 0 64 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e31arty.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e31arty.cfg
new file mode 100644
index 0000000..b3e980f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e31arty.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Be sure you include the speed and interface before this file
+# Example:
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg"
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+  ftdi set_signal nSRST 0
+  ftdi set_signal nSRST z
+}
+halt
+flash protect 0 64 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e51arty.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e51arty.cfg
new file mode 100644
index 0000000..3133c39
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-e51arty.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Be sure you include the speed and interface before this file
+# Example:
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg"
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+  ftdi set_signal nSRST 0
+  ftdi set_signal nSRST z
+}
+halt
+flash protect 0 64 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-hifive1-revb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-hifive1-revb.cfg
new file mode 100644
index 0000000..7fcab0c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-hifive1-revb.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed 4000
+
+adapter driver jlink
+transport select jtag
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 0
+
+riscv set_enable_virt2phys off
+riscv set_enable_virtual off
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME.0
+
+init
+
+jlink jtag 3
+
+halt
+flash protect 0 1 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-hifive1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-hifive1.cfg
new file mode 100644
index 0000000..f69dc4f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/sifive-hifive1.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed     10000
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
+
+#Reset Stretcher logic on FE310 is ~1 second long
+#This doesn't apply if you use
+# ftdi set_signal, but still good to document
+#adapter srst delay 1500
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset -- This type of reset is not implemented yet
+if {[ info exists pulse_srst]} {
+  ftdi set_signal nSRST 0
+  ftdi set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}
+halt
+flash protect 0 64 last off
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/smdk6410.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/smdk6410.cfg
new file mode 100644
index 0000000..be61ae9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/smdk6410.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a SMDK6410
+# Processor       : ARM1176
+# Info:   JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+
+source [find target/samsung_s3c6410.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk.cfg
new file mode 100644
index 0000000..56eed93
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.x
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# 5MHz seems to work good with all cores that might happen in 2.x
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk_v1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk_v1.cfg
new file mode 100644
index 0000000..94aab14
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk_v1.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+adapter speed 10000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk_v2.1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk_v2.1.cfg
new file mode 100644
index 0000000..96391df
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk_v2.1.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
+# 20MHz. 7.5 MHz seems to work fine.
+adapter speed 7500
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk_v2.2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk_v2.2.cfg
new file mode 100644
index 0000000..c1f6a72
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_em_sk_v2.2.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2016,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.2
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_hsdk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_hsdk.cfg
new file mode 100644
index 0000000..24022e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_hsdk.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2019, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC HSDK Software Development Platform (HS38 cores)
+#
+
+source [find interface/ftdi/snps_sdp.cfg]
+adapter speed 10000
+
+# ARCs supports only JTAG.
+transport select jtag
+
+# Configure SoC
+source [find target/snps_hsdk.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_hsdk_4xd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_hsdk_4xd.cfg
new file mode 100644
index 0000000..5901533
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/snps_hsdk_4xd.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Copyright (C) 2023 Synopsys, Inc.
+# Artemiy Volkov 
+
+# Adapted from tcl/board/snps_hsdk.cfg.
+
+#
+# Synopsys DesignWare ARC HSDK Software Development Platform (HS47D cores)
+#
+
+source [find interface/ftdi/snps_sdp.cfg]
+adapter speed 10000
+
+# ARCs supports only JTAG.
+transport select jtag
+
+# Configure SoC
+source [find target/snps_hsdk_4xd.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg
new file mode 100644
index 0000000..c22ace8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion SK-FM4-176L-S6E2CC
+#
+
+#
+# FM3 MB9AF312K
+#
+source [find interface/cmsis-dap.cfg]
+
+# There's also an unpopulated 10-pin 0.05" pinout.
+
+#
+# FM4 S6E2CCAJ0A w/ 192 KB SRAM0
+#
+set CHIPNAME s6e2cc
+set CHIPSERIES S6E2CCAJ0A
+set WORKAREASIZE 0x30000
+source [find target/fm4_s6e2cc.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spansion_sk-fm4-u120-9b560.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spansion_sk-fm4-u120-9b560.cfg
new file mode 100644
index 0000000..15477a2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spansion_sk-fm4-u120-9b560.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion SK-FM4-U120-9B560
+#
+
+#
+# FM3 MB9AF312K
+#
+# source [find interface/cmsis-dap.cfg]
+
+#
+# FM4 MB9BF568R w/ 64 KB SRAM0
+#
+set CHIPNAME mb9bf568
+set CHIPSERIES MB9BF568R
+set WORKAREASIZE 0x10000
+source [find target/fm4_mb9bf.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear300evb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear300evb.cfg
new file mode 100644
index 0000000..f2cf596
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear300evb.cfg
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr300 Evaluation board
+# EVALSPEAr300 Rev. 1.0
+# http://www.st.com/spear
+#
+# Date:      2010-11-27
+# Author:    Antonio Borneo 
+
+# The standard board has JTAG SRST not connected.
+# This script targets such boards using quirky code to bypass the issue.
+
+
+source [find mem_helper.tcl]
+source [find target/spear3xx.cfg]
+source [find chip/st/spear/spear3xx_ddr.tcl]
+source [find chip/st/spear/spear3xx.tcl]
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+
+# Serial NOR on SMI CS0. 8Mbyte.
+set _FLASHNAME1 $_CHIPNAME.snor
+flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
+
+if { [info exists BOARD_HAS_SRST] } {
+	# Modified board has SRST on JTAG connector
+	reset_config trst_and_srst separate srst_gates_jtag \
+		trst_push_pull srst_open_drain
+} else {
+	# Standard board has no SRST on JTAG connector
+	reset_config trst_only separate srst_gates_jtag trst_push_pull
+	source [find chip/st/spear/quirk_no_srst.tcl]
+}
+
+$_TARGETNAME configure -event reset-init { spear300evb_init }
+
+proc spear300evb_init {} {
+	reg pc 0xffff0020;	# loop forever
+
+	sp3xx_clock_default
+	sp3xx_common_init
+	sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
+	sp300_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear300evb_mod.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear300evb_mod.cfg
new file mode 100644
index 0000000..4b1d578
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear300evb_mod.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr300 Evaluation board
+# EVALSPEAr300 Rev. 1.0, modified to enable SRST on JTAG connector
+# http://www.st.com/spear
+#
+# List of board modifications to enable SRST, as reported in
+# ST Application Note (FIXME: add reference).
+# - Modifications on the top layer:
+#    1. replace reset chip U4 with a STM6315SDW13F;
+# - Modifications on the bottom layer:
+#    2. add 0 ohm resistor R10. It is located close to JTAG connector.
+#    3. add a 10K ohm pull-up resistor on the reset wire named as
+#       POWERGOOD in the schematic.
+#
+# The easier way to do modification 3, is to use a resistor in package
+# 0603 and solder it between R10 and R54:
+# - one pad soldered with the pad of R54 connected to 3.3V (this
+#   is the pad of R54 far from JTAG connector J4)
+# - the other pad soldered with the nearest pad of R10.
+#
+# Date:      2011-11-18
+# Author:    Antonio Borneo 
+
+
+# Modified boards has SRST on JTAG connector
+set BOARD_HAS_SRST 1
+source [find board/spear300evb.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear310evb20.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear310evb20.cfg
new file mode 100644
index 0000000..c37bd1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear310evb20.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr310 Evaluation board
+# EVALSPEAr310 Rev. 2.0
+# http://www.st.com/spear
+#
+# Date:      2010-08-17
+# Author:    Antonio Borneo 
+
+# The standard board has JTAG SRST not connected.
+# This script targets such boards using quirky code to bypass the issue.
+#
+# Check ST Application Note AN3321 on how to fix SRST on
+# the board, then use the script board/spear310evb20_mod.cfg
+
+
+source [find mem_helper.tcl]
+source [find target/spear3xx.cfg]
+source [find chip/st/spear/spear3xx_ddr.tcl]
+source [find chip/st/spear/spear3xx.tcl]
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+# CFI parallel NOR on EMI CS0. 2x 16bit 8M devices = 16Mbyte.
+set _FLASHNAME0 $_CHIPNAME.pnor
+flash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME
+
+# Serial NOR on SMI CS0. 8Mbyte.
+set _FLASHNAME1 $_CHIPNAME.snor
+flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
+
+if { [info exists BOARD_HAS_SRST] } {
+	# Modified board has SRST on JTAG connector
+	reset_config trst_and_srst separate srst_gates_jtag \
+		trst_push_pull srst_open_drain
+} else {
+	# Standard board has no SRST on JTAG connector
+	reset_config trst_only separate srst_gates_jtag trst_push_pull
+	source [find chip/st/spear/quirk_no_srst.tcl]
+}
+
+$_TARGETNAME configure -event reset-init { spear310evb20_init }
+
+proc spear310evb20_init {} {
+	reg pc 0xffff0020	;# loop forever
+
+	sp3xx_clock_default
+	sp3xx_common_init
+	sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
+	sp310_init
+	sp310_emi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear310evb20_mod.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear310evb20_mod.cfg
new file mode 100644
index 0000000..2c56254
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear310evb20_mod.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr310 Evaluation board
+# EVALSPEAr310 Rev. 2.0, modified to enable SRST on JTAG connector
+# http://www.st.com/spear
+#
+# List of board modifications to enable SRST, as reported in
+# ST Application Note AN3321.
+# - Modifications on the top layer:
+#    1. remove R137 and C57, located near the SMII PHY U18;
+#    2. remove R172 and C75, located near the SMII PHY U19;
+#    3. remove R207 and C90, located near the SMII PHY U20;
+#    4. remove C236, located near the SMII PHY U21;
+#    5. remove U12, located near the JTAG connector;
+#    6. solder together pins 7, 8 and 9 of U12;
+#    7. solder together pins 11, 12, 13, 14, 15, 16, 17 and 18 of U12.
+# - Modifications on the bottom layer:
+#    8. replace reset chip U11 with a STM6315SDW13F;
+#    9. add 0 ohm resistor R329. It is located close to JTAG connector.
+#
+# Date:      2009-10-31
+# Author:    Antonio Borneo 
+
+
+# Modified boards has SRST on JTAG connector
+set BOARD_HAS_SRST 1
+source [find board/spear310evb20.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear320cpu.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear320cpu.cfg
new file mode 100644
index 0000000..df713ea
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear320cpu.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr320 CPU board
+# EVAL_SPEAr320CPU Rev. 2.0
+# http://www.st.com/spear
+#
+# Date:      2011-11-18
+# Author:    Antonio Borneo 
+
+# The standard board has JTAG SRST not connected.
+# This script targets such boards using quirky code to bypass the issue.
+
+
+source [find mem_helper.tcl]
+source [find target/spear3xx.cfg]
+source [find chip/st/spear/spear3xx_ddr.tcl]
+source [find chip/st/spear/spear3xx.tcl]
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+
+# Serial NOR on SMI CS0. 8Mbyte.
+set _FLASHNAME1 $_CHIPNAME.snor
+flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
+
+if { [info exists BOARD_HAS_SRST] } {
+	# Modified board has SRST on JTAG connector
+	reset_config trst_and_srst separate srst_gates_jtag \
+		trst_push_pull srst_open_drain
+} else {
+	# Standard board has no SRST on JTAG connector
+	reset_config trst_only separate srst_gates_jtag trst_push_pull
+	source [find chip/st/spear/quirk_no_srst.tcl]
+}
+
+$_TARGETNAME configure -event reset-init { spear320cpu_init }
+
+if { [info exists DDR_CHIPS] } {
+        set _DDR_CHIPS $DDR_CHIPS
+} else {
+        set _DDR_CHIPS 1
+}
+
+proc spear320cpu_init {} {
+	global _DDR_CHIPS
+	reg pc 0xffff0020;	# loop forever
+
+	sp3xx_clock_default
+	sp3xx_common_init
+	sp3xx_ddr_init "mt47h64m16_3_333_cl5_async" $_DDR_CHIPS
+	sp320_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear320cpu_mod.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear320cpu_mod.cfg
new file mode 100644
index 0000000..d12607d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/spear320cpu_mod.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr320 Evaluation board
+# EVAL_SPEAr320CPU Rev. 2.0, modified to enable SRST on JTAG connector
+# http://www.st.com/spear
+#
+# List of board modifications to enable SRST, as reported in
+# ST Application Note (FIXME: add reference).
+# - Modifications on the bottom layer:
+#    1. replace reset chip U7 with a STM6315SDW13F;
+#    2. add 0 ohm resistor R45. It is located close to JTAG connector.
+#    3. add a 10K ohm pull-up resistor on the reset wire named as
+#       POWERGOOD in the schematic.
+#
+# The easier way to do modification 3, is to use a resistor in package
+# 0603 or 0402 and solder it between R15 and R45:
+# - one pad soldered with the pad of R15 connected to 3.3V (this
+#   is the pad of R15 closer to R45)
+# - the other pad soldered with the nearest pad of R45.
+#
+# Date:      2011-11-18
+# Author:    Antonio Borneo 
+
+
+# Modified boards has SRST on JTAG connector
+set BOARD_HAS_SRST 1
+source [find board/spear320cpu.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_b-l475e-iot01a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_b-l475e-iot01a.cfg
new file mode 100644
index 0000000..3f3db12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_b-l475e-iot01a.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an B-L475E-IOT01A Discovery kit for IoT node with a single STM32L475VGT6 chip.
+# http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
+
+	# PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+
+	# Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+	mmw 0x48001000 0xAAA00000 0x55500000	;# MODER
+	mmw 0x48001008 0xFFF00000 0x00000000	;# OSPEEDR
+	mmw 0x48001024 0xAAAAAA00 0x55555500	;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00160100				;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_8l152r8.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_8l152r8.cfg
new file mode 100644
index 0000000..681b5a2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_8l152r8.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a ST NUCLEO 8L152R8 board with a single STM8L152R8T6 chip.
+# http://www.st.com/en/evaluation-tools/nucleo-8l152r8.html
+
+source [find interface/stlink.cfg]
+
+transport select swim
+
+source [find target/stm8l15xx8.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_8s208rb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_8s208rb.cfg
new file mode 100644
index 0000000..0f6bde2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_8s208rb.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a ST NUCLEO 8S208RB board with a single STM8S208RBT6 chip.
+# https://www.st.com/en/evaluation-tools/nucleo-8s208rb.html
+
+source [find interface/stlink.cfg]
+
+transport select swim
+
+# 128 KiB flash and 2 KiB EEPROM
+set FLASHEND 0x27fff
+set EEPROMEND 0x47ff
+
+source [find target/stm8s.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f0.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f0.cfg
new file mode 100644
index 0000000..00c131f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f0.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for all ST NUCLEO with any STM32F0. Known boards at the moment:
+# STM32F030R8
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997
+# NUCLEO-F072RB
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997
+# STM32F091RC
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260944
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f0x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f103rb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f103rb.cfg
new file mode 100644
index 0000000..892bdda
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f103rb.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO F103RB board with a single STM32F103RBT6 chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259875
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f1x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f3.cfg
new file mode 100644
index 0000000..38f49e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f3.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO F334R8 board with a single STM32F334R8T6 chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260004
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f3x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f4.cfg
new file mode 100644
index 0000000..7617a17
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f4.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for all ST NUCLEO with any STM32F4. Known boards at the moment:
+# STM32F401RET6
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260000
+# STM32F411RET6
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260320
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f7.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f7.cfg
new file mode 100644
index 0000000..41f8b21
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_f7.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32F7 Nucleo development board
+# Known boards: NUCLEO-F746ZG and NUCLEO-F767ZI
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_g0.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_g0.cfg
new file mode 100644
index 0000000..f22a7e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_g0.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for all ST NUCLEO with any STM32G0. Known boards at the moment:
+# NUCLEO-G031K8
+# https://www.st.com/en/evaluation-tools/nucleo-g031k8.html
+# NUCLEO-G070RB
+# https://www.st.com/en/evaluation-tools/nucleo-g070rb.html
+# NUCLEO-G071RB
+# https://www.st.com/en/evaluation-tools/nucleo-g071rb.html
+# NUCLEO-G0B1RE
+# https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32g0x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_g4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_g4.cfg
new file mode 100644
index 0000000..309f7a4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_g4.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for all ST NUCLEO with any STM32G4. Known boards at the moment:
+# NUCLEO-G431KB
+# https://www.st.com/en/evaluation-tools/nucleo-g431kb.html
+# NUCLEO-G431RB
+# https://www.st.com/en/evaluation-tools/nucleo-g431rb.html
+# NUCLEO-G474RE
+# https://www.st.com/en/evaluation-tools/nucleo-g474re.html
+# NUCLEO-G491RE
+# https://www.st.com/en/evaluation-tools/nucleo-g491re.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32g4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_h743zi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_h743zi.cfg
new file mode 100644
index 0000000..be2d42f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_h743zi.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip.
+# http://www.st.com/en/evaluation-tools/nucleo-h743zi.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_h745zi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_h745zi.cfg
new file mode 100644
index 0000000..84865f4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_h745zi.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip.
+
+source [find interface/stlink.cfg]
+transport select dapdirect_swd
+
+# STM32H745xx devices are dual core (Cortex-M7 and Cortex-M4)
+set DUAL_CORE 1
+
+# enable CTI for cross halting both cores
+set USE_CTI 1
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l073rz.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l073rz.cfg
new file mode 100644
index 0000000..317c86e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l073rz.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO-L073RZ board with single STM32L073RZ chip.
+# http://www.st.com/en/evaluation-tools/nucleo-l073rz.html
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x2000
+
+source [find target/stm32l0_dual_bank.cfg]
+
+# There is only system reset line and JTAG/SWD command can be issued when SRST
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l1.cfg
new file mode 100644
index 0000000..d7474d0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l1.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO L152RE board with a single STM32L152RET6 chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32l1x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l4.cfg
new file mode 100644
index 0000000..b0a75af
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l4.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Should work with all STM32L4 Nucleo Dev Boards.
+# http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32l4x.cfg]
+
+# use hardware reset
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l5.cfg
new file mode 100644
index 0000000..626914a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_l5.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for STM32L5 Nucleo Dev Boards.
+# http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32l5x.cfg]
+
+# use hardware reset
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_wb55.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_wb55.cfg
new file mode 100644
index 0000000..ab7307c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/st_nucleo_wb55.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration for STM32WB55 Nucleo board (STM32WB55RGV6)
+#
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32wbx.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb007v1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb007v1.cfg
new file mode 100644
index 0000000..69d4585
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb007v1.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an evaluation board with a single BlueNRG-1 chip.
+# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb008v1.html
+set CHIPNAME bluenrg-1
+source [find target/bluenrg-x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb008v1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb008v1.cfg
new file mode 100644
index 0000000..057c0dd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb008v1.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an evaluation board with a single BlueNRG-2 chip.
+# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb007v1.html
+set CHIPNAME bluenrg-2
+source [find target/bluenrg-x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb011v1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb011v1.cfg
new file mode 100644
index 0000000..1163508
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb011v1.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an evaluation board with a single BlueNRG-LP chip.
+set CHIPNAME bluenrg-lp
+source [find target/bluenrg-x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb012v1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb012v1.cfg
new file mode 100644
index 0000000..288cbb2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval-idb012v1.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an evaluation board with a single BlueNRG-LPS chip.
+set CHIPNAME bluenrg-lps
+source [find interface/cmsis-dap.cfg]
+source [find target/bluenrg-x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval_pcc010.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval_pcc010.cfg
new file mode 100644
index 0000000..6e006ba
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/steval_pcc010.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram
+# coming with the STEVAL-PCC010 board
+# http://www.st.com/internet/evalboard/product/251530.jsp
+# or any other board with only a STM32F2x in the JTAG chain
+
+# increase working area to 32KB for faster flash programming
+set WORKAREASIZE 0x8000
+
+source [find target/stm32f2x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm320518_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm320518_eval.cfg
new file mode 100644
index 0000000..04486fc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm320518_eval.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6
+# (64KB) chip.
+# http://www.st.com/internet/evalboard/product/252994.jsp
+#
+
+# increase working area to 8KB
+set WORKAREASIZE 0x2000
+
+# chip name
+set CHIPNAME STM32F051R8T6
+
+source [find target/stm32f0x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm320518_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm320518_eval_stlink.cfg
new file mode 100644
index 0000000..997bb4a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm320518_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6
+# (64KB) chip.
+# http://www.st.com/internet/evalboard/product/252994.jsp
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 8KB
+set WORKAREASIZE 0x2000
+
+# chip name
+set CHIPNAME STM32F051R8T6
+
+source [find target/stm32f0x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32100b_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32100b_eval.cfg
new file mode 100644
index 0000000..ebb5681
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32100b_eval.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32 eval board with a single STM32F100VBT6 chip.
+# http://www.st.com/internet/evalboard/product/247099.jsp
+
+# The chip has only 8KB sram
+set WORKAREASIZE 0x2000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3210b_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3210b_eval.cfg
new file mode 100644
index 0000000..072f542
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3210b_eval.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32 eval board with a single STM32F10x (128KB) chip.
+# http://www.st.com/internet/evalboard/product/176090.jsp
+
+# increase working area to 32KB for faster flash programming
+set WORKAREASIZE 0x8000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3210c_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3210c_eval.cfg
new file mode 100644
index 0000000..ec56f63
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3210c_eval.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32 eval board with a single STM32F107VCT chip.
+# http://www.st.com/internet/evalboard/product/217965.jsp
+
+# increase working area to 32KB for faster flash programming
+set WORKAREASIZE 0x8000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3210e_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3210e_eval.cfg
new file mode 100644
index 0000000..f08e04b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3210e_eval.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32 eval board with a single STM32F103ZET6 chip.
+# http://www.st.com/internet/evalboard/product/204176.jsp
+
+# increase working area to 32KB for faster flash programming
+set WORKAREASIZE 0x8000
+
+source [find target/stm32f1x.cfg]
+
+#
+# configure FSMC Bank 1 (NOR/PSRAM Bank 2) NOR flash
+# M29W128GL70ZA6E
+#
+
+set _FLASHNAME $_CHIPNAME.norflash
+flash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME
+
+proc stm32_enable_fsmc {} {
+
+	echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)"
+
+	# enable gpio (defg) clocks for fsmc
+	# RCC_APB2ENR
+	mww 0x40021018 0x000001E0
+
+	# enable fsmc clock
+	# RCC_AHBENR
+	mww 0x40021014 0x00000114
+
+	# configure gpio to alternate function
+	# GPIOD_CRL
+	mww 0x40011400 0x44BB44BB
+	# GPIOD_CRH
+	mww 0x40011404 0xBBBBBBBB
+
+	# GPIOE_CRL
+	mww 0x40011800 0xBBBBB444
+	# GPIOE_CRH
+	mww 0x40011804 0xBBBBBBBB
+
+	# GPIOF_CRL
+	mww 0x40011C00 0x44BBBBBB
+	# GPIOF_CRH
+	mww 0x40011C04 0xBBBB4444
+
+	# GPIOG_CRL
+	mww 0x40012000 0x44BBBBBB
+	# GPIOG_CRH
+	mww 0x40012004 0x444444B4
+
+	# setup fsmc timings
+	# FSMC_BCR1
+	mww 0xA0000008 0x00001058
+
+	# FSMC_BTR1
+	mww 0xA000000C 0x10000502
+
+	# FSMC_BCR1 - enable fsmc
+	mww 0xA0000008 0x00001059
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32_enable_fsmc
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3220g_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3220g_eval.cfg
new file mode 100644
index 0000000..9782a07
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3220g_eval.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6
+# (128KB) chip.
+# http://www.st.com/internet/evalboard/product/250374.jsp
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F207IGH6
+
+source [find target/stm32f2x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3220g_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3220g_eval_stlink.cfg
new file mode 100644
index 0000000..4233d04
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3220g_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6
+# (128KB) chip.
+# http://www.st.com/internet/evalboard/product/250374.jsp
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F207IGH6
+
+source [find target/stm32f2x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3241g_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3241g_eval.cfg
new file mode 100644
index 0000000..7df373f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3241g_eval.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6
+# (1024KB) chip.
+# http://www.st.com/internet/evalboard/product/252216.jsp
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F417IGH6
+
+source [find target/stm32f4x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3241g_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3241g_eval_stlink.cfg
new file mode 100644
index 0000000..3bccd28
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm3241g_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6
+# (1024KB) chip.
+# http://www.st.com/internet/evalboard/product/252216.jsp
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F417IGH6
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32429i_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32429i_eval.cfg
new file mode 100644
index 0000000..3304ef6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32429i_eval.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6
+# (2048KB) chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F429NIH6
+
+source [find target/stm32f4x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32429i_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32429i_eval_stlink.cfg
new file mode 100644
index 0000000..7d04aa7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32429i_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6
+# (2048KB) chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F429NIH6
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32439i_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32439i_eval.cfg
new file mode 100644
index 0000000..c29d4de
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32439i_eval.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6
+# (2048KB) chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F439NIH6
+
+source [find target/stm32f4x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32439i_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32439i_eval_stlink.cfg
new file mode 100644
index 0000000..b9ea084
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32439i_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6
+# (2048KB) chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F439NIH6
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm327x6g_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm327x6g_eval.cfg
new file mode 100644
index 0000000..03fe949
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm327x6g_eval.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM327[4|5]6G-EVAL: This is for the STM32F7 eval boards.
+# STM32746G-EVAL
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261639
+# STM32756G-EVAL
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261640
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f0discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f0discovery.cfg
new file mode 100644
index 0000000..398ecc1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f0discovery.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F0 discovery board with a single STM32F051R8T6 chip.
+# http://www.st.com/internet/evalboard/product/253215.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x2000
+source [find target/stm32f0x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f103c8_blue_pill.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f103c8_blue_pill.cfg
new file mode 100644
index 0000000..0b84f72
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f103c8_blue_pill.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32F103C8 "Blue Pill"
+
+# NOTE:
+# There is a fair bit of confusion about whether the "Blue Pill" has 128kB or 64kB flash size.
+# The most likely cause is that there exist a -C8 and a -CB variant of the STM32F103, where
+# the C8 has 64kB, the CB has 128kB as per specification. "Blue Pill" boards are manufactured
+# by a lot of different vendors, some may actually use the CB variant but from a cursory look
+# it very hard to tell them apart ("C8" and "CB" look very similar). Nevertheless, people have
+# tried using the full 128kB of flash on the C8 and found it to be working. Hence this board file
+# overrides the internal size detection. Be aware though that you may be using you particular
+# board outside of its specification. If in doubt, comment the following line.
+set FLASH_SIZE 0x20000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f334discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f334discovery.cfg
new file mode 100644
index 0000000..3ff2968
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f334discovery.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F334 discovery board with a single STM32F334C8T6 chip.
+# As it is one of the few boards with stlink V.2-1, we source the corresponding
+# nucleo file.
+# http://www.st.com/web/en/catalog/tools/FM116/SC959/SS1532/LN1848/PF260318
+
+source [find board/st_nucleo_f3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f3discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f3discovery.cfg
new file mode 100644
index 0000000..73c349a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f3discovery.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F3 discovery board with a single STM32F303VCT6 chip.
+# http://www.st.com/internet/evalboard/product/254044.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f3x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f412g-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f412g-disco.cfg
new file mode 100644
index 0000000..30a9537
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f412g-disco.cfg
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F412G discovery board with a single STM32F412ZGT6 chip.
+# http://www.st.com/en/evaluation-tools/32f412gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000000FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PG06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
+
+	# PB02:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V, PG06:AF10:V
+
+	# Port B: PB02:AF09:V
+	mmw 0x40020400 0x00000020 0x00000010	;# MODER
+	mmw 0x40020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x00000900 0x00000600	;# AFRL
+
+	# Port F: PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x40021400 0x000AA000 0x00055000	;# MODER
+	mmw 0x40021408 0x000FF000 0x00000000	;# OSPEEDR
+	mmw 0x40021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x40021424 0x000000AA 0x00000055	;# AFRH
+
+	# Port G: PG06:AF10:V
+	mmw 0x40021800 0x00002000 0x00001000	;# MODER
+	mmw 0x40021808 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x40021820 0x0A000000 0x05000000	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000003				;# 3 WS for 96 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24001808				;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
+	mww 0x40023808 0x00001000				;# APB1: /2, APB2: /1
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f413h-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f413h-disco.cfg
new file mode 100644
index 0000000..c82d0d4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f413h-disco.cfg
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F413H discovery board with a single STM32F413ZHT6 chip.
+# http://www.st.com/en/evaluation-tools/32f413hdiscovery.html
+
+#
+# Untested!!!
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000000FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PB02: CLK, PD13: BK1_IO3, PE02: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
+
+	# PB02:AF09:V, PD13:AF09:V, PE02:AF09:V, PF09:AF10:V, PF08:AF10:V, PG06:AF10:V
+
+	# Port B: PB02:AF09:V
+	mmw 0x40020400 0x00000020 0x00000010	;# MODER
+	mmw 0x40020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x00000900 0x00000600	;# AFRL
+
+	# Port D: PD13:AF09:V
+	mmw 0x40020C00 0x08000000 0x04000000	;# MODER
+	mmw 0x40020C08 0x0C000000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00900000 0x00600000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	# Port F: PF09:AF10:V, PF08:AF10:V
+	mmw 0x40021400 0x000A0000 0x00050000	;# MODER
+	mmw 0x40021408 0x000F0000 0x00000000	;# OSPEEDR
+	mmw 0x40021424 0x000000AA 0x00000055	;# AFRH
+
+	# Port G: PG06:AF10:V
+	mmw 0x40021800 0x00002000 0x00001000	;# MODER
+	mmw 0x40021808 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x40021820 0x0A000000 0x05000000	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000003				;# 3 WS for 96 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24001808				;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
+	mww 0x40023808 0x00001000				;# APB1: /2, APB2: /1
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f429disc1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f429disc1.cfg
new file mode 100644
index 0000000..0a8e7ef
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f429disc1.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is an STM32F429 discovery board with a single STM32F429ZI chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
+#
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f429discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f429discovery.cfg
new file mode 100644
index 0000000..865602a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f429discovery.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is an STM32F429 discovery board with a single STM32F429ZI chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
+#
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f469discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f469discovery.cfg
new file mode 100644
index 0000000..c9acbbb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f469discovery.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is an STM32F469 discovery board with a single STM32F469NI chip.
+# http://www.st.com/web/catalog/tools/FM116/CL1620/SC959/SS1532/LN1848/PF262395
+#
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f469i-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f469i-disco.cfg
new file mode 100644
index 0000000..63c42c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f469i-disco.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F469I discovery board with a single STM32F469NIH6 chip.
+# http://www.st.com/en/evaluation-tools/32f469idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PF10: CLK, PB06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
+
+	# PB06:AF10:V, PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
+
+	# Port B: PB06:AF10:V
+	mmw 0x40020400 0x00002000 0x00001000	;# MODER
+	mmw 0x40020408 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000000 0x05000000	;# AFRL
+
+	# Port F: PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x40021400 0x002AA000 0x00155000	;# MODER
+	mmw 0x40021408 0x003FF000 0x00000000	;# OSPEEDR
+	mmw 0x40021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x40021424 0x000009AA 0x00000655	;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000005				;# 5 WS for 160 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24002808				;# 160 MHz: HSI, PLLM=8, PLLN=160, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f4discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f4discovery.cfg
new file mode 100644
index 0000000..d96e2db
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f4discovery.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F4 discovery board with a single STM32F407VGT6 chip.
+# http://www.st.com/internet/evalboard/product/252419.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 64KB
+set WORKAREASIZE 0x10000
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f723e-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f723e-disco.cfg
new file mode 100644
index 0000000..0207956
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f723e-disco.cfg
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F723E discovery board with a single STM32F723IEK6 chip.
+# http://www.st.com/en/evaluation-tools/32f723ediscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
+
+	# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
+
+	# Port B: PB06:AF10:V, PB02:AF09:V
+	mmw 0x40020400 0x00002020 0x00001010	;# MODER
+	mmw 0x40020408 0x00003030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000900 0x05000600	;# AFRL
+
+	# Port C: PC10:AF09:V, PC09:AF09:V
+	mmw 0x40020800 0x00280000 0x00140000	;# MODER
+	mmw 0x40020808 0x003C0000 0x00000000	;# OSPEEDR
+	mmw 0x40020824 0x00000990 0x00000660	;# AFRH
+
+	# Port D: PD13:AF09:V
+	mmw 0x40020C00 0x08000000 0x04000000	;# MODER
+	mmw 0x40020C08 0x0C000000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00900000 0x00600000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00190100				;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 4-byte addresses
+	mww 0xA0001014 0x0D003513				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000006				;# 6 WS for 192 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24003008				;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f746g-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f746g-disco.cfg
new file mode 100644
index 0000000..75ff4ec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f746g-disco.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F746G discovery board with a single STM32F746NGH6 chip.
+# http://www.st.com/en/evaluation-tools/32f746gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PD12: BK1_IO1, PD11: BK1_IO0
+
+	# PB06:AF10:V, PB02:AF09:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PE02:AF09:V
+
+	# Port B: PB06:AF10:V, PB02:AF09:V
+	mmw 0x40020400 0x00002020 0x00001010	;# MODER
+	mmw 0x40020408 0x00003030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000900 0x05000600	;# AFRL
+
+	# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V
+	mmw 0x40020C00 0x0A800000 0x05400000	;# MODER
+	mmw 0x40020C08 0x0FC00000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00999000 0x00666000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000006				;# 6 WS for 192 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24003008				;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f769i-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f769i-disco.cfg
new file mode 100644
index 0000000..cd6383a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f769i-disco.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F769I discovery board with a single STM32F769NIH6 chip.
+# http://www.st.com/en/evaluation-tools/32f769idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
+
+	# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
+
+	# Port B: PB06:AF10:V, PB02:AF09:V
+	mmw 0x40020400 0x00002020 0x00001010	;# MODER
+	mmw 0x40020408 0x00003030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000900 0x05000600	;# AFRL
+
+	# Port C: PC10:AF09:V, PC09:AF09:V
+	mmw 0x40020800 0x00280000 0x00140000	;# MODER
+	mmw 0x40020808 0x003C0000 0x00000000	;# OSPEEDR
+	mmw 0x40020824 0x00000990 0x00000660	;# AFRH
+
+	# Port D: PD13:AF09:V
+	mmw 0x40020C00 0x08000000 0x04000000	;# MODER
+	mmw 0x40020C08 0x0C000000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00900000 0x00600000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00190100				;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# exit qpi mode
+	mww 0xA0001014 0x000033f5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+
+	# 1-line memory-mapped read mode with 4-byte addresses
+	mww 0xA0001014 0x0D003513				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+
+	# 4-line qpi mode
+	mww 0xA0001014 0x00003135				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=EQIO
+
+	# 4-line memory-mapped read mode with 4-byte addresses
+	mww 0xA0001014 0x0F283FEC				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0xA, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=4READ4B
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000006				;# 6 WS for 192 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24003008				;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f7discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f7discovery.cfg
new file mode 100644
index 0000000..6fd6c64
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32f7discovery.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F7 discovery board with a single STM32F756NGH6 chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641
+
+# This is for using the onboard STLINK/V2-1
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h735g-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h735g-disco.cfg
new file mode 100644
index 0000000..327a364
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h735g-disco.cfg
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h735g-dk with a single STM32H735IGK6 chip.
+# https://www.st.com/en/evaluation-tools/stm32h735g-dk.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h735igk6
+
+# enable stmqspi
+if {![info exists OCTOSPI1]} {
+	set OCTOSPI1 1
+	set OCTOSPI2 0
+}
+
+source [find target/stm32h7x.cfg]
+
+reset_config srst_only
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x58024540 0x000006FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
+	sleep 1									;# Wait for clock startup
+
+	mww 0x5200B404 0x03010111				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
+	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2
+
+	# PG06: OCSPI1_NCS, PF10: OCSPI1_CLK, PB02: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PD05: OCSPI1_IO5,
+	# PD04: OCSPI1_IO4, PD13: OCSPI1_IO3, PE02: OCSPI1_IO2, PD12: OCSPI1_IO1, PD11: OCSPI1_IO0
+
+	# PB02:AF10:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V
+	# PD04:AF10:V, PE02:AF09:V, PF10:AF09:V, PG09:AF09:V, PG06:AF10:V
+	# Port B: PB02:AF10:V
+	mmw 0x58020400 0x00000020 0x00000010	;# MODER
+	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x5802040C 0x00000000 0x00000030	;# PUPDR
+	mmw 0x58020420 0x00000A00 0x00000500	;# AFRL
+	# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
+	mmw 0x58020C00 0x0A808A00 0x05404500	;# MODER
+	mmw 0x58020C08 0x0FC0CF00 0x00000000	;# OSPEEDR
+	mmw 0x58020C0C 0x00000000 0x0FC0CF00	;# PUPDR
+	mmw 0x58020C20 0xA0AA0000 0x50550000	;# AFRL
+	mmw 0x58020C24 0x00999000 0x00666000	;# AFRH
+	# Port E: PE02:AF09:V
+	mmw 0x58021000 0x00000020 0x00000010	;# MODER
+	mmw 0x58021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x5802100C 0x00000000 0x00000030	;# PUPDR
+	mmw 0x58021020 0x00000900 0x00000600	;# AFRL
+	# Port F: PF10:AF09:V
+	mmw 0x58021400 0x00200000 0x00100000	;# MODER
+	mmw 0x58021408 0x00300000 0x00000000	;# OSPEEDR
+	mmw 0x5802140C 0x00000000 0x00300000	;# PUPDR
+	mmw 0x58021424 0x00000900 0x00000600	;# AFRH
+	# Port G: PG09:AF09:V, PG06:AF10:V
+	mmw 0x58021800 0x00082000 0x00041000	;# MODER
+	mmw 0x58021808 0x000C3000 0x00000000	;# OSPEEDR
+	mmw 0x5802180C 0x00000000 0x000C3000	;# PUPDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x00000090 0x00000060	;# AFRH
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0x52005130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0x52005008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0x5200500C 0x00000005				;# OCTOSPI_DCR2: PRESCALER=5
+
+	mww 0x52005108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0x52005100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0x52005110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0x52005108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0x52005100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0x52005110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global OCTOSPI1
+	global OCTOSPI2
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $OCTOSPI1 } {
+		octospi_init 1
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h745i-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h745i-disco.cfg
new file mode 100644
index 0000000..9da1dae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h745i-disco.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h745i-disco with a single STM32H745XIH6 chip.
+# www.st.com/en/product/stm32h745i-disco.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h745xih6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+	set QUADSPI 1
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
+
+source [find board/stm32h7x_dual_qspi.cfg]
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global QUADSPI
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $QUADSPI } {
+		qspi_init 1
+	}
+}
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h747i-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h747i-disco.cfg
new file mode 100644
index 0000000..7f8eda8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h747i-disco.cfg
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h747i-disco with a single STM32H747XIH6 chip.
+# www.st.com/en/product/stm32h747i-disco.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h747xih6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+	set QUADSPI 1
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
+
+# QUADSPI initialization
+# qpi: 4-line mode
+proc qspi_init { qpi } {
+	global a
+	mmw 0x580244E0 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x580244D4 0x00004000 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PB02: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
+	# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
+
+	# PB02:AF09:V, PD11:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
+	# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
+
+	# Port B: PB02:AF09:V
+	mmw 0x58020400 0x00000020 0x00000010	;# MODER
+	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x58020420 0x00000900 0x00000600	;# AFRL
+	# Port D: PD11:AF09:V
+	mmw 0x58020C00 0x00800000 0x00400000	;# MODER
+	mmw 0x58020C08 0x00C00000 0x00000000	;# OSPEEDR
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x58021400 0x0008A000 0x00045000	;# MODER
+	mmw 0x58021408 0x000CF000 0x00000000	;# OSPEEDR
+	mmw 0x58021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x58021424 0x000000A0 0x00000050	;# AFRH
+	# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
+	mmw 0x58021800 0x20082000 0x10041000	;# MODER
+	mmw 0x58021808 0x200C2000 0x10001000	;# OSPEEDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x09000090 0x06000060	;# AFRH
+	# Port H: PH03:AF09:V, PH02:AF09:V
+	mmw 0x58021C00 0x000000A0 0x00000050	;# MODER
+	mmw 0x58021C08 0x000000F0 0x00000000	;# OSPEEDR
+	mmw 0x58021C20 0x00009900 0x00006600	;# AFRL
+
+	# correct FSIZE is 0x1A, however, this causes trouble when
+	# reading the last bytes at end of bank in *memory mapped* mode
+
+	# for dual flash mode 2 * mt25ql512
+	mww 0x52005000 0x05500058				;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
+	mww 0x52005004 0x001A0200				;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
+
+	mww 0x52005030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
+	mmw 0x52005000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# Exit QPI mode
+	mmw 0x52005000 0x00000002 0				;# QUADSPI_CR: ABORT=1
+	mww 0x52005014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
+	sleep 1
+
+	if { $qpi == 1 } {
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Configure dummy clocks via volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000181			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
+		mwh 0x52005020 0xABAB				;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
+		sleep 1
+
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Enable QPI mode via enhanced volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000161			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
+		mwh 0x52005020 0x3F3F				;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
+		sleep 1
+
+		# Enter QPI mode
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000135			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
+		sleep 1
+
+		# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0F283FEC			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
+	} else {
+		# memory-mapped read mode with 4-byte addresses
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0D003513			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+	}
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global QUADSPI
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $QUADSPI } {
+		qspi_init 1
+	}
+}
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h750b-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h750b-disco.cfg
new file mode 100644
index 0000000..8b254f2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h750b-disco.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h750b-dk with a single STM32H750XBH6 chip.
+# www.st.com/en/product/stm32h750b-dk.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h750xbh6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+	set QUADSPI 1
+}
+
+source [find target/stm32h7x.cfg]
+
+reset_config srst_only
+
+source [find board/stm32h7x_dual_qspi.cfg]
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global QUADSPI
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $QUADSPI } {
+		qspi_init 1
+	}
+}
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h7b3i-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h7b3i-disco.cfg
new file mode 100644
index 0000000..df0d0a6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h7b3i-disco.cfg
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h7b3i-dk with a single STM32H7B3LIH6Q chip.
+# https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h7b3lih6q
+
+# enable stmqspi
+if {![info exists OCTOSPI1]} {
+	set OCTOSPI1 1
+	set OCTOSPI2 0
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x58024540 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
+	sleep 1									;# Wait for clock startup
+
+	mww 0x5200B404 0x03010111				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
+	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2
+
+	# PG06: OCSPI1_NCS, PB02: OCSPI1_CLK, PC05: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PH03: OCSPI1_IO5,
+	# PC01: OCSPI1_IO4, PF06: OCSPI1_IO3, PF07: OCSPI1_IO2, PF09: OCSPI1_IO1, PD11: OCSPI1_IO0
+
+	# PB02:AF09:V, PC05:AF10:V, PC01:AF10:V, PD11:AF09:V, PD07:AF10:V, PF09:AF10:V
+	# PF07:AF10:V, PF06:AF10:V, PG09:AF09:V, PG06:AF10:V, PH03:AF09:V
+	# Port B: PB02:AF09:V
+	mmw 0x58020400 0x00000020 0x00000010	;# MODER
+	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x5802040C 0x00000000 0x00000030	;# PUPDR
+	mmw 0x58020420 0x00000900 0x00000600	;# AFRL
+	# Port C: PC05:AF10:V, PC01:AF10:V
+	mmw 0x58020800 0x00000808 0x00000404	;# MODER
+	mmw 0x58020808 0x00000C0C 0x00000000	;# OSPEEDR
+	mmw 0x5802080C 0x00000000 0x00000C0C	;# PUPDR
+	mmw 0x58020820 0x00A000A0 0x00500050	;# AFRL
+	# Port D: PD11:AF09:V, PD07:AF10:V
+	mmw 0x58020C00 0x00808000 0x00404000	;# MODER
+	mmw 0x58020C08 0x00C0C000 0x00000000	;# OSPEEDR
+	mmw 0x58020C0C 0x00000000 0x00C0C000	;# PUPDR
+	mmw 0x58020C20 0xA0000000 0x50000000	;# AFRL
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF09:AF10:V, PF07:AF10:V, PF06:AF10:V
+	mmw 0x58021400 0x0008A000 0x00045000	;# MODER
+	mmw 0x58021408 0x000CF000 0x00000000	;# OSPEEDR
+	mmw 0x5802140C 0x00000000 0x000CF000	;# PUPDR
+	mmw 0x58021420 0xAA000000 0x55000000	;# AFRL
+	mmw 0x58021424 0x000000A0 0x00000050	;# AFRH
+	# Port G: PG09:AF09:V, PG06:AF10:V
+	mmw 0x58021800 0x00082000 0x00041000	;# MODER
+	mmw 0x58021808 0x000C3000 0x00000000	;# OSPEEDR
+	mmw 0x5802180C 0x00000000 0x000C3000	;# PUPDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x00000090 0x00000060	;# AFRH
+	# Port H: PH03:AF09:V
+	mmw 0x58021C00 0x00000080 0x00000040	;# MODER
+	mmw 0x58021C08 0x000000C0 0x00000000	;# OSPEEDR
+	mmw 0x58021C0C 0x00000000 0x000000C0	;# PUPDR
+	mmw 0x58021C20 0x00009000 0x00006000	;# AFRL
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0x52005130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0x52005008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0x5200500C 0x00000005				;# OCTOSPI_DCR2: PRESCALER=5
+
+	mww 0x52005108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0x52005100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0x52005110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0x52005108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0x52005100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0x52005110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global OCTOSPI1
+	global OCTOSPI2
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $OCTOSPI1 } {
+		octospi_init 1
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h7x3i_eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h7x3i_eval.cfg
new file mode 100644
index 0000000..508f10d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h7x3i_eval.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32H7[4|5]3I-EVAL: this is for the H7 eval boards.
+# This is an ST EVAL-H743XI board with single STM32H743XI chip.
+# http://www.st.com/en/evaluation-tools/stm32h743i-eval.html
+# This is an ST EVAL-H753XI board with single STM32H753XI chip.
+# http://www.st.com/en/evaluation-tools/stm32h753i-eval.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h7x_dual_qspi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h7x_dual_qspi.cfg
new file mode 100644
index 0000000..0349fad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32h7x_dual_qspi.cfg
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# stm32h754i-disco and stm32h750b-dk dual quad qspi.
+
+# QUADSPI initialization
+# qpi: 4-line mode
+proc qspi_init { qpi } {
+	global a
+	mmw 0x580244E0 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x580244D4 0x00004000 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PF10: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
+	# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
+
+	# PD11:AF09:V, PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
+	# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
+
+	# Port D: PD11:AF09:V
+	mmw 0x58020C00 0x00800000 0x00400000	;# MODER
+	mmw 0x58020C08 0x00C00000 0x00000000	;# OSPEEDR
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x58021400 0x0028A000 0x00145000	;# MODER
+	mmw 0x58021408 0x003CF000 0x00000000	;# OSPEEDR
+	mmw 0x58021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x58021424 0x000009A0 0x00000650	;# AFRH
+	# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
+	mmw 0x58021800 0x20082000 0x10041000	;# MODER
+	mmw 0x58021808 0x200C2000 0x10001000	;# OSPEEDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x09000090 0x06000060	;# AFRH
+	# Port H: PH03:AF09:V, PH02:AF09:V
+	mmw 0x58021C00 0x000000A0 0x00000050	;# MODER
+	mmw 0x58021C08 0x000000F0 0x00000000	;# OSPEEDR
+	mmw 0x58021C20 0x00009900 0x00006600	;# AFRL
+
+	# correct FSIZE is 0x1A, however, this causes trouble when
+	# reading the last bytes at end of bank in *memory mapped* mode
+
+	# for dual flash mode 2 * mt25ql512
+	mww 0x52005000 0x05500058				;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
+	mww 0x52005004 0x001A0200				;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
+
+	mww 0x52005030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
+	mmw 0x52005000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# Exit QPI mode
+	mmw 0x52005000 0x00000002 0				;# QUADSPI_CR: ABORT=1
+	mww 0x52005014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
+	sleep 1
+
+	if { $qpi == 1 } {
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Configure dummy clocks via volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000181			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
+		mwh 0x52005020 0xABAB				;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
+		sleep 1
+
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Enable QPI mode via enhanced volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000161			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
+		mwh 0x52005020 0x3F3F				;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
+		sleep 1
+
+		# Enter QPI mode
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000135			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
+		sleep 1
+
+		# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0F283FEC			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
+	} else {
+		# memory-mapped read mode with 4-byte addresses
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0D003513			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l0discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l0discovery.cfg
new file mode 100644
index 0000000..59aed34
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l0discovery.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32L053 discovery board with a single STM32L053 chip.
+# http://www.st.com/web/en/catalog/tools/PF260319
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x2000
+source [find target/stm32l0.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l476g-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l476g-disco.cfg
new file mode 100644
index 0000000..fe33ffe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l476g-disco.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32L476G discovery board with a single STM32L476VGT6 chip.
+# http://www.st.com/en/evaluation-tools/32l476gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
+
+	# PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+
+	# Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+	mmw 0x48001000 0xAAA00000 0x55500000    ;# MODER
+	mmw 0x48001008 0xFFF00000 0x00000000    ;# OSPEEDR
+	mmw 0x48001024 0xAAAAAA00 0x55555500    ;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l496g-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l496g-disco.cfg
new file mode 100644
index 0000000..823fa6e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l496g-disco.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32L496G discovery board with a single STM32L496AGI6 chip.
+# http://www.st.com/en/evaluation-tools/32l496gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB11: BK1_NCS, PA03: CLK, PA06: BK1_IO3, PA07: BK1_IO2, PB00: BK1_IO1, PB01: BK1_IO0
+
+	# PA07:AF10:V, PA06:AF10:V, PA03:AF10:V, PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
+
+	# Port A: PA07:AF10:V, PA06:AF10:V, PA03:AF10:V
+	mmw 0x48000000 0x0000A080 0x00005040    ;# MODER
+	mmw 0x48000008 0x0000F0C0 0x00000000    ;# OSPEEDR
+	mmw 0x48000020 0xAA00A000 0x55005000    ;# AFRL
+
+	# Port B: PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
+	mmw 0x48000400 0x0080000A 0x00400005    ;# MODER
+	mmw 0x48000408 0x00C0000F 0x00000000    ;# OSPEEDR
+	mmw 0x48000420 0x000000AA 0x00000055    ;# AFRL
+	mmw 0x48000424 0x0000A000 0x00005000    ;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00160100				;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l4discovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l4discovery.cfg
new file mode 100644
index 0000000..64a456b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l4discovery.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Explicitly for the STM32L476 discovery board:
+# http://www.st.com/web/en/catalog/tools/PF261635
+# but perfectly functional for any other STM32L4 board connected via
+# an stlink-v2-1 interface.
+# This is for STM32L4 boards that are connected via stlink-v2-1.
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32l4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l4p5g-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l4p5g-disco.cfg
new file mode 100644
index 0000000..33bb9a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l4p5g-disco.cfg
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a STM32L4P5G discovery board with a single STM32L4R9AGI6 chip.
+# http://www.st.com/en/evaluation-tools/stm32l4p5g-dk.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set OCTOSPI1 1
+set OCTOSPI2 0
+
+source [find target/stm32l4x.cfg]
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x4002104C 0x001001FF 0				;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000300 0				;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
+	mmw 0x40021058 0x10000000 0				;# RCC_APB1ENR1 |= PWREN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	mmw 0x40007004 0x00000200 0				;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
+
+	mww 0x50061C04 0x07050333				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI2
+	mww 0x50061C08 0x03010111				;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
+
+	# PE11: P1_NCS, PE10: P1_CLK, PG06: P1_DQS, PD07: P1_IO7, PC03: P1_IO6, PD05: P1_IO5
+	# PD04: P1_IO4, PA06: P1_IO3, PA07: P1_IO2, PE13: P1_IO1, PE11: P1_IO0
+
+	# PA07:AF10:V, PA06:AF10:V, PC03:AF10:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
+	# PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V, PG06:AF03:V
+
+	# Port A: PA07:AF10:V, PA06:AF10:V
+	mmw 0x48000000 0x0000A000 0x00005000	;# MODER
+	mmw 0x48000008 0x0000F000 0x00000000	;# OSPEEDR
+	mmw 0x4800000C 0x00000000 0x0000F000	;# PUPDR
+	mmw 0x48000020 0xAA000000 0x55000000	;# AFRL
+	# Port C: PC03:AF10:V
+	mmw 0x48000800 0x00000080 0x00000040	;# MODER
+	mmw 0x48000808 0x000000C0 0x00000000	;# OSPEEDR
+	mmw 0x4800080C 0x00000000 0x000000C0	;# PUPDR
+	mmw 0x48000820 0x0000A000 0x00005000	;# AFRL
+	# Port D: PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
+	mmw 0x48000C00 0x00008A00 0x00004500	;# MODER
+	mmw 0x48000C08 0x0000CF00 0x00000000	;# OSPEEDR
+	mmw 0x48000C0C 0x00000000 0x0000CF00	;# PUPDR
+	mmw 0x48000C20 0xA0AA0000 0x50550000	;# AFRL
+	# Port E: PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+	mmw 0x48001000 0x0AA00000 0x05500000	;# MODER
+	mmw 0x48001008 0x0FF00000 0x00000000	;# OSPEEDR
+	mmw 0x4800100C 0x00000000 0x0FF00000	;# PUPDR
+	mmw 0x48001024 0x00AAAA00 0x00555500	;# AFRH
+	# Port G: PG06:AF03:V
+	mmw 0x48001800 0x00002000 0x00001000	;# MODER
+	mmw 0x48001808 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x4800180C 0x00000000 0x00003000	;# PUPDR
+	mmw 0x48001820 0x03000000 0x0C000000	;# AFRL
+
+	# PG12: P2_NCS, PF04: P2_CLK, PF12: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PG01: P2_IO5
+	# PG00: P2_IO4, PF03: P2_IO3, PF02: P2_IO2, PF01: P2_IO1, PF00: P2_IO0
+
+	# PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
+	# PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
+
+	# Port F: PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
+	mmw 0x48001400 0x020002AA 0x01000155	;# MODER
+	mmw 0x48001408 0x030003FF 0x00000000	;# OSPEEDR
+	mmw 0x4800140C 0x00000000 0x030003FF	;# PUPDR
+	mmw 0x48001420 0x00055555 0x000AAAAA	;# AFRL
+	mmw 0x48001424 0x00050000 0x000A0000	;# AFRH
+	# Port G: PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
+	mmw 0x48001800 0x0228000A 0x01140005	;# MODER
+	mmw 0x48001808 0x033C000F 0x00000000	;# OSPEEDR
+	mmw 0x4800180C 0x00000000 0x033C000F	;# PUPDR
+	mmw 0x48001820 0x00000055 0x000000AA	;# AFRL
+	mmw 0x48001824 0x00050550 0x000A0AA0	;# AFRH
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0xA0001130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0xA0001008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0xA000100C 0x00000001				;# OCTOSPI_DCR2: PRESCALER=1
+
+	mww 0xA0001108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0xA0001100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0xA0001110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0xA0001108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0xA0001100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0xA0001110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000003 0x0000000C	;# 3 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 24000
+
+	octospi_init 1
+}
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l4r9i-disco.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l4r9i-disco.cfg
new file mode 100644
index 0000000..cbb8666
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32l4r9i-disco.cfg
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a STM32L4R9I discovery board with a single STM32L4R9AII6 chip.
+# http://www.st.com/en/evaluation-tools/32l4r9idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set OCTOSPI1 1
+set OCTOSPI2 0
+
+source [find target/stm32l4x.cfg]
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x4002104C 0x001001FF 0				;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000300 0				;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
+	mmw 0x40021058 0x10000000 0				;# RCC_APB1ENR1 |= PWREN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	mmw 0x40007004 0x00000200 0				;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
+
+	mww 0x50061C04 0x00000000				;# OCTOSPIM_P1CR: disable Port 1
+	mww 0x50061C08 0x03010111				;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
+
+	# PG12: P2_NCS, PI06: P2_CLK, PG15: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PH10: P2_IO5,
+	# PH09: P2_IO4, PH08: P2_IO3, PI09: P2_IO2, PI10: P2_IO1, PI11: P2_IO0
+
+	# PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PH10:AF05:V, PH09:AF05:V
+	# PH08:AF05:V, PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
+
+	# Port G: PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V
+	mmw 0x48001800 0x82280000 0x41140000	;# MODER
+	mmw 0x48001808 0xC33C0000 0x00000000	;# OSPEEDR
+	mmw 0x48001824 0x50050550 0xA00A0AA0	;# AFRH
+
+	# Port H: PH10:AF05:V, PH09:AF05:V, PH08:AF05:V
+	mmw 0x48001C00 0x002A0000 0x00150000	;# MODER
+	mmw 0x48001C08 0x003F0000 0x00000000	;# OSPEEDR
+	mmw 0x48001C24 0x00000555 0x00000AAA	;# AFRH
+
+	# Port I: PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
+	mmw 0x48002000 0x00A82000 0x00541000	;# MODER
+	mmw 0x48002008 0x00FC3000 0x00000000	;# OSPEEDR
+	mmw 0x48002020 0x05000000 0x0A000000	;# AFRL
+	mmw 0x48002024 0x00005550 0x0000AAA0	;# AFRH
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0xA0001130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0xA0001008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0xA000100C 0x00000001				;# OCTOSPI_DCR2: PRESCALER=1
+
+	mww 0xA0001108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0xA0001100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0xA0001110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0xA0001108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0xA0001100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0xA0001110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000003 0x0000000C	;# 3 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	octospi_init 1
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32ldiscovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32ldiscovery.cfg
new file mode 100644
index 0000000..e39b522
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32ldiscovery.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32L discovery board with a single STM32L152RBT6 chip.
+# http://www.st.com/internet/evalboard/product/250990.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x4000
+source [find target/stm32l1.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32mp13x_dk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32mp13x_dk.cfg
new file mode 100644
index 0000000..08377ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32mp13x_dk.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# board MB1635x
+# http://www.st.com/en/evaluation-tools/stm32mp135f-dk.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32mp13x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32mp15x_dk2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32mp15x_dk2.cfg
new file mode 100644
index 0000000..0e71e05
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32mp15x_dk2.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# board MB1272B
+# http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html
+# http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32mp15x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32vldiscovery.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32vldiscovery.cfg
new file mode 100644
index 0000000..57852bf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/stm32vldiscovery.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32VL discovery board with a single STM32F100RB chip.
+# http://www.st.com/internet/evalboard/product/250863.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x2000
+source [find target/stm32f1x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/str910-eval.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/str910-eval.cfg
new file mode 100644
index 0000000..b6e9837
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/str910-eval.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# str910-eval eval board
+#
+# Need reset scripts
+reset_config trst_and_srst
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists FLASHTAPID] } {
+   set _FLASHTAPID $FLASHTAPID
+} else {
+   set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+   set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs    -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	#jtag_rclk 3000
+
+	# -- Enable 96K RAM
+	# PFQBC enabled / DTCM & AHB wait-states disabled
+	mww 0x5C002034 0x0191
+
+	str9x flash_config 0 4 2 0 0x80000
+	flash protect 0 0 7 off
+}
+
+#flash bank str9x   0 0  
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/telo.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/telo.cfg
new file mode 100644
index 0000000..721c019
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/telo.cfg
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/c100.cfg]
+# basic register definition for C100
+source [find target/c100regs.tcl]
+# board-config info
+source [find target/c100config.tcl]
+# C100 helper functions
+source [find target/c100helper.tcl]
+
+
+# Telo board & C100 support trst and srst
+# make the reset asserted to
+# allow RC circuit to discharge for: [ms]
+adapter srst pulse_width 100
+jtag_ntrst_assert_width 100
+# don't talk to JTAG after reset for: [ms]
+adapter srst delay 100
+jtag_ntrst_delay 100
+reset_config trst_and_srst separate
+
+
+
+
+# issue telnet: reset init
+# issue gdb: monitor reset init
+$_TARGETNAME configure -event reset-init {
+	adapter speed 100
+	# this will setup Telo board
+	setupTelo
+	#turn up the JTAG speed
+	adapter speed 3000
+	echo "JTAG speek now 3MHz"
+	echo "type helpC100 to get help on C100"
+}
+
+$_TARGETNAME configure -event reset-deassert-post {
+	# Force target into ARM state.
+#	soft_reset_halt ;# not implemented on ARM11
+	echo "Detected SRSRT asserted on C100.CPU"
+
+}
+
+$_TARGETNAME configure -event reset-assert-post {
+  echo "Assering reset"
+  #sleep 10
+}
+
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
+
+
+# boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
+# it's really 16MB but the upper 8mb is controller via gpio
+# openocd does not support 'complex reads/writes' to NOR
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
+
+# writing data to memory does not work without this
+arm11 memwrite burst disable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am243_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am243_launchpad.cfg
new file mode 100644
index 0000000..aa75dda
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am243_launchpad.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM243 Launchpad
+# https://www.ti.com/tool/LP-AM243
+#
+
+# AM243 Launchpad has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am243
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am263_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am263_launchpad.cfg
new file mode 100644
index 0000000..a07a21b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am263_launchpad.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM263 Launchpad
+# https://www.ti.com/tool/LP-AM263
+#
+
+# AM263 Launchpad has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am263
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am273_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am273_launchpad.cfg
new file mode 100644
index 0000000..c17170b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am273_launchpad.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM273 Launchpad
+# https://www.ti.com/tool/LP-AM273
+#
+
+# AM273 Launchpad has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am273
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am335xevm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am335xevm.cfg
new file mode 100644
index 0000000..af058ec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am335xevm.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI AM335x Evaluation Module
+#
+# For more information please see http://www.ti.com/tool/tmdxevm3358
+#
+jtag_rclk 6000
+
+source [find target/am335x.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am437x_idk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am437x_idk.cfg
new file mode 100644
index 0000000..b427762
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am437x_idk.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Texas Instruments AM437x Industrial Development Kit
+
+# The JTAG interface is built directly on the board.
+source [find interface/ftdi/xds100v2.cfg]
+
+transport select jtag
+adapter speed 30000
+
+source [find target/am437x.cfg]
+$_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 }
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am43xx_evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am43xx_evm.cfg
new file mode 100644
index 0000000..005421f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am43xx_evm.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Works on both AM437x GP EVM and AM438x ePOS EVM
+transport select jtag
+adapter speed 16000
+
+source [find target/am437x.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am625_swd_native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am625_swd_native.cfg
new file mode 100644
index 0000000..dc4b205
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am625_swd_native.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments am625
+# Link: https://www.ti.com/product/AM625
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every AM625 platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside AM625 and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC am625
+}
+
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am625evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am625evm.cfg
new file mode 100644
index 0000000..4906fd0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am625evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2021-2022 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments am625 EVM/SK
+# Link: https://www.ti.com/lit/zip/sprr448
+#
+
+# AM625 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am625
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62a7_swd_native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62a7_swd_native.cfg
new file mode 100644
index 0000000..99fc0b0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62a7_swd_native.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM62A7
+# Link: https://www.ti.com/product/AM62A7
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every AM62A7 platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside AM62A7 and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC am62a7
+}
+
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62a7evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62a7evm.cfg
new file mode 100644
index 0000000..e407909
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62a7evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments am62a7 EVM/SK
+# Link: https://www.ti.com/tool/SK-AM62A-LP
+#
+
+# AM62a7 EVM/SK has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am62a7
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62p_swd_native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62p_swd_native.cfg
new file mode 100644
index 0000000..fa549f3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62p_swd_native.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments am62p
+# Link: https://www.ti.com/product/AM62P
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every AM62P platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside AM62P and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC am62p
+}
+
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62pevm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62pevm.cfg
new file mode 100644
index 0000000..2322b3d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am62pevm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments SK-AM62P: https://www.ti.com/lit/zip/sprr487
+#
+
+# AM62P SK/EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am62p
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am642evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am642evm.cfg
new file mode 100644
index 0000000..e97fdcf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am642evm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM642 EVM
+#
+
+# AM642 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am642
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am654evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am654evm.cfg
new file mode 100644
index 0000000..a661f60
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_am654evm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM654 EVM/IDK Base Board
+#
+
+# AM654 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+if { ![info exists SOC] } {
+	set SOC am654
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beagleboard.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beagleboard.cfg
new file mode 100644
index 0000000..6767bd6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beagleboard.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OMAP3 BeagleBoard
+#  http://beagleboard.org
+
+# Fall back to 6MHz if RTCK is not supported
+jtag_rclk 6000
+
+source [find target/omap3530.cfg]
+
+# TI-14 JTAG connector
+reset_config trst_only
+
+# Later run:  omap3_dbginit
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beagleboard_xm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beagleboard_xm.cfg
new file mode 100644
index 0000000..fd176a0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beagleboard_xm.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BeagleBoard xM (DM37x)
+#  http://beagleboard.org
+
+set CHIPTYPE "dm37x"
+source [find target/amdm37x.cfg]
+
+# The TI-14 JTAG connector does not have srst.  CPU reset is handled in
+# hardware.
+reset_config trst_only
+
+# "amdm37x_dbginit dm37x.cpu" needs to be run after init.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beaglebone-base.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beaglebone-base.cfg
new file mode 100644
index 0000000..566f0a4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beaglebone-base.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# AM335x Beaglebone family base configuration
+#  http://beagleboard.org/bone
+
+source [find target/am335x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beaglebone.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beaglebone.cfg
new file mode 100644
index 0000000..d96e45f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beaglebone.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# AM335x Beaglebone
+#  http://beagleboard.org/bone
+
+# The JTAG interface is built directly on the board.
+source [find interface/ftdi/xds100v2.cfg]
+
+adapter speed 16000
+
+reset_config trst_and_srst
+
+source [find board/ti_beaglebone-base.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beaglebone_black.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beaglebone_black.cfg
new file mode 100644
index 0000000..d72bf09
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_beaglebone_black.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# AM335x Beaglebone Black
+#  http://beagleboard.org/bone
+
+adapter speed 1000
+
+reset_config trst_and_srst
+
+source [find board/ti_beaglebone-base.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_blaze.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_blaze.cfg
new file mode 100644
index 0000000..e28b05b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_blaze.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+jtag_rclk 6000
+
+source [find target/omap4430.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc13x0_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc13x0_launchpad.cfg
new file mode 100644
index 0000000..f6dfbcd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc13x0_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC13x0 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+transport select jtag
+adapter speed 5500
+source [find target/ti_cc13x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc13x2_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc13x2_launchpad.cfg
new file mode 100644
index 0000000..900842a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc13x2_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC13x2 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc13x2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc26x0_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc26x0_launchpad.cfg
new file mode 100644
index 0000000..431383d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc26x0_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC26x0 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc26x2_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc26x2_launchpad.cfg
new file mode 100644
index 0000000..133f57e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc26x2_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC26x2 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc26x2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc26x2x7_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc26x2x7_launchpad.cfg
new file mode 100644
index 0000000..9e6e72e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc26x2x7_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC1352P7 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc26x2x7.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc3200_launchxl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc3200_launchxl.cfg
new file mode 100644
index 0000000..5f39b8a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc3200_launchxl.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI SimpleLink Wi-Fi CC3200 LaunchPad
+#
+# http://www.ti.com/tool/cc3200-launchxl
+#
+
+source [find interface/ftdi/ti-icdi.cfg]
+
+if { [info exists TRANSPORT] } {
+   transport select $TRANSPORT
+} else {
+   transport select jtag
+}
+
+adapter speed 2500
+
+set WORKAREASIZE 0x40000
+source [find target/ti_cc32xx.cfg]
+
+reset_config srst_only
+adapter srst delay 1100
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc3220sf_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc3220sf_launchpad.cfg
new file mode 100644
index 0000000..fe34554
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc3220sf_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 8500
+transport select swd
+source [find target/ti_cc3220sf.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc32xx_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc32xx_launchpad.cfg
new file mode 100644
index 0000000..343da48
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_cc32xx_launchpad.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC32xx-LaunchXL LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 8500
+transport select swd
+source [find target/ti_cc32xx.cfg]
+
+reset_config srst_only
+adapter srst delay 1100
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_dk-tm4c129.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_dk-tm4c129.cfg
new file mode 100644
index 0000000..d8210e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_dk-tm4c129.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Tiva C DK-TM4C129X Connected Development Kit
+#
+# http://www.ti.com/tool/dk-tm4c129x
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c129xnczad
+
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_ek-tm4c123gxl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_ek-tm4c123gxl.cfg
new file mode 100644
index 0000000..91390fa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_ek-tm4c123gxl.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit
+#
+# http://www.ti.com/tool/ek-tm4c123gxl
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c123gh6pm
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_ek-tm4c1294xl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_ek-tm4c1294xl.cfg
new file mode 100644
index 0000000..63612c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_ek-tm4c1294xl.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Tiva C Series ek-tm4c1294xl Launchpad Evaluation Kit
+#
+# http://www.ti.com/tool/ek-tm4c1294xl
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c1294ncpdt
+
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j7200evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j7200evm.cfg
new file mode 100644
index 0000000..cc70056
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j7200evm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J7200 EVM
+#
+
+# J7200 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j7200
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j721e_swd_native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j721e_swd_native.cfg
new file mode 100644
index 0000000..3041c3c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j721e_swd_native.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments TDA4VM/J721E
+# Link: https://www.ti.com/product/TDA4VM
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every TDA4VM platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside TDA4VM and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+        set SOC j721e
+}
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j721evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j721evm.cfg
new file mode 100644
index 0000000..d0c4b74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j721evm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J721E EVM
+#
+
+# J721E EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j721e
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j721s2evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j721s2evm.cfg
new file mode 100644
index 0000000..72418b5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j721s2evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J721s2 EVM
+# Link(SoM): https://www.ti.com/lit/zip/sprr439
+#
+
+# J721s2 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j721s2
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j722s_swd_native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j722s_swd_native.cfg
new file mode 100644
index 0000000..bbe0d50
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j722s_swd_native.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J722S/AM67/TDA4VEN
+# Link: https://www.ti.com/product/AM67
+# Link: https://www.ti.com/product/TDA4VEN-Q1
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every J722S platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside J722S and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC j722s
+}
+
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j722sevm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j722sevm.cfg
new file mode 100644
index 0000000..6a5c2d9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j722sevm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Texas Instruments EVM-J722S: https://www.ti.com/lit/zip/sprr495
+#
+
+# J722S EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j722s
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j784s4evm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j784s4evm.cfg
new file mode 100644
index 0000000..d23dc8c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_j784s4evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J784S4 EVM: https://www.ti.com/tool/J784S4XEVM
+# Texas Instruments SK-AM69: https://www.ti.com/tool/SK-AM69
+#
+
+# J784S4/AM69 SK/EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j784s4
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_msp432_launchpad.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_msp432_launchpad.cfg
new file mode 100644
index 0000000..4832b83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_msp432_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI MSP432 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 10000
+transport select swd
+source [find target/ti_msp432.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_pandaboard.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_pandaboard.cfg
new file mode 100644
index 0000000..45092e0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_pandaboard.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+jtag_rclk 6000
+
+source [find target/omap4430.cfg]
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_pandaboard_es.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_pandaboard_es.cfg
new file mode 100644
index 0000000..f837358
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_pandaboard_es.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+jtag_rclk 6000
+
+source [find target/omap4460.cfg]
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_tmdx570ls20susb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_tmdx570ls20susb.cfg
new file mode 100644
index 0000000..9c5ef74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_tmdx570ls20susb.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TMS570 Microcontroller USB Kit
+# http://www.ti.com/tool/TMDX570LS20SUSB
+
+# Board uses a FT2232H to emulate an XDS100v2 JTAG debugger
+# TODO: board also supports an SCI UART on the 2232's B Bus
+source [find interface/ftdi/xds100v2.cfg]
+
+# Processor is TMS570LS20216
+source [find target/ti_tms570ls20xxx.cfg]
+
+reset_config trst_only
+
+# xds100v2 config says add this to the end
+init
+ftdi set_signal PWR_RST 1
+jtag arp_init
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_tmdx570ls31usb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_tmdx570ls31usb.cfg
new file mode 100644
index 0000000..324f003
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/ti_tmdx570ls31usb.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed 1500
+
+source [find interface/ftdi/xds100v2.cfg]
+source [find target/ti_tms570.cfg]
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tocoding_poplar.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tocoding_poplar.cfg
new file mode 100644
index 0000000..5f9dba4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tocoding_poplar.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# board configuration for Tocoding Poplar
+#
+
+# board does not feature anything but JTAG
+transport select jtag
+
+adapter speed 10000
+
+# SRST-only reset configuration
+reset_config srst_only srst_push_pull
+
+source [find target/hi3798.cfg]
+
+# make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# examine remaining cores
+	foreach _core $args {
+		${_TARGETNAME}$_core arp_examine
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/topas910.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/topas910.cfg
new file mode 100644
index 0000000..f45f6e7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/topas910.cfg
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Toshiba TOPAS910 -- TMPA910 Starterkit
+#
+######################################
+
+# We add to the minimal configuration.
+source [find target/tmpa910.cfg]
+
+######################
+# Target configuration
+######################
+
+#$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { topas910_init }
+
+proc topas910_init { } {
+# Init PLL
+# my settings
+	mww 0xf005000c 0x00000007
+	mww 0xf0050010 0x00000065
+	mww 0xf005000c 0x000000a7
+	sleep 10
+	mdw 0xf0050008
+	mww 0xf0050008 0x00000002
+	mww 0xf0050004 0x00000000
+# NEW: set CLKCR5
+	mww 0xf0050054 0x00000040
+#
+	sleep 10
+# Init SDRAM
+#  _PMCDRV          = 0x00000071;
+#  //
+#  // Initialize SDRAM timing parameter
+#  //
+#  _DMC_CAS_LATENCY = 0x00000006;
+#  _DMC_T_DQSS      = 0x00000000;
+#  _DMC_T_MRD       = 0x00000002;
+#  _DMC_T_RAS       = 0x00000007;
+#
+#  _DMC_T_RC        = 0x0000000A;
+#  _DMC_T_RCD       = 0x00000013;
+#
+#  _DMC_T_RFC       = 0x0000010A;
+#
+#  _DMC_T_RP        = 0x00000013;
+#  _DMC_T_RRD       = 0x00000002;
+#  _DMC_T_WR        = 0x00000002;
+#  _DMC_T_WTR       = 0x00000001;
+#  _DMC_T_XP        = 0x0000000A;
+#  _DMC_T_XSR       = 0x0000000B;
+#  _DMC_T_ESR       = 0x00000014;
+#
+#  //
+#  // Configure SDRAM type parameter
+#  _DMC_MEMORY_CFG  = 0x00008011;
+#  _DMC_USER_CONFIG = 0x00000011;
+#  // 32 bit memory interface
+#
+#
+#  _DMC_REFRESH_PRD = 0x00000A60;
+#  _DMC_CHIP_0_CFG  = 0x000140FC;
+#
+#  _DMC_DIRECT_CMD  = 0x000C0000;
+#  _DMC_DIRECT_CMD  = 0x00000000;
+#
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00080031;
+#  //
+#  // Finally start SDRAM
+#  //
+#  _DMC_MEMC_CMD    = MEMC_CMD_GO;
+#  */
+
+	mww 0xf0020260 0x00000071
+	mww 0xf4300014 0x00000006
+	mww 0xf4300018 0x00000000
+	mww 0xf430001C 0x00000002
+	mww 0xf4300020 0x00000007
+	mww 0xf4300024 0x0000000A
+	mww 0xf4300028 0x00000013
+	mww 0xf430002C 0x0000010A
+	mww 0xf4300030 0x00000013
+	mww 0xf4300034 0x00000002
+	mww 0xf4300038 0x00000002
+	mww 0xf430003C 0x00000001
+	mww 0xf4300040 0x0000000A
+	mww 0xf4300044 0x0000000B
+	mww 0xf4300048 0x00000014
+	mww 0xf430000C 0x00008011
+	mww 0xf4300304 0x00000011
+	mww 0xf4300010 0x00000A60
+	mww 0xf4300200 0x000140FC
+	mww 0xf4300008 0x000C0000
+	mww 0xf4300008 0x00000000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00080031
+	mww 0xf4300004 0x00000000
+
+	sleep 10
+#	adapter speed NNNN
+
+# remap off in case of IROM boot
+	mww 0xf0000004 0x00000001
+
+}
+
+# comment the following out if usinf J-Link, it soes not support DCC
+arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/topasa900.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/topasa900.cfg
new file mode 100644
index 0000000..d6ddc44
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/topasa900.cfg
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Thanks to Pieter Conradie for this script!
+# Target:    Toshiba TOPAS900 -- TMPA900 Starterkit
+######################################
+
+# We add to the minimal configuration.
+source [find target/tmpa900.cfg]
+
+######################
+# Target configuration
+######################
+
+#$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { topasa900_init }
+
+proc topasa900_init { } {
+# Init PLL
+# my settings
+	mww 0xf005000c 0x00000007
+	mww 0xf0050010 0x00000065
+	mww 0xf005000c 0x000000a7
+	sleep 10
+	mdw 0xf0050008
+	mww 0xf0050008 0x00000002
+	mww 0xf0050004 0x00000000
+# NEW: set CLKCR5
+	mww 0xf0050054 0x00000040
+#
+# bplan settings
+#	mww 0xf0050004 0x00000000
+#	mww 0xf005000c 0x000000a7
+#	sleep 10
+#	mdw 0xf0050008
+#	mww 0xf0050008 0x00000002
+#	mww 0xf0050010 0x00000065
+#	mww 0xf0050054 0x00000040
+	sleep 10
+# Init SDRAM
+#  _PMCDRV          = 0x00000071;
+#  //
+#  // Initialize SDRAM timing parameter
+#  //
+#  _DMC_CAS_LATENCY = 0x00000006;
+#  _DMC_T_DQSS      = 0x00000000;
+#  _DMC_T_MRD       = 0x00000002;
+#  _DMC_T_RAS       = 0x00000007;
+#
+#  _DMC_T_RC        = 0x0000000A;
+#  _DMC_T_RCD       = 0x00000013;
+#
+#  _DMC_T_RFC       = 0x0000010A;
+#
+#  _DMC_T_RP        = 0x00000013;
+#  _DMC_T_RRD       = 0x00000002;
+#  _DMC_T_WR        = 0x00000002;
+#  _DMC_T_WTR       = 0x00000001;
+#  _DMC_T_XP        = 0x0000000A;
+#  _DMC_T_XSR       = 0x0000000B;
+#  _DMC_T_ESR       = 0x00000014;
+#
+#  //
+#  // Configure SDRAM type parameter
+#  _DMC_MEMORY_CFG  = 0x00008011;
+#  _DMC_USER_CONFIG = 0x00000011;   // 32 bit memory interface
+#
+#
+#  _DMC_REFRESH_PRD = 0x00000A60;
+#  _DMC_CHIP_0_CFG  = 0x000140FC;
+#
+#  _DMC_DIRECT_CMD  = 0x000C0000;
+#  _DMC_DIRECT_CMD  = 0x00000000;
+#
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00080031;
+#  //
+#  // Finally start SDRAM
+#  //
+#  _DMC_MEMC_CMD    = MEMC_CMD_GO;
+#  */
+
+	mww 0xf0020260 0x00000071
+	mww 0xf4300014 0x00000006
+	mww 0xf4300018 0x00000000
+	mww 0xf430001C 0x00000002
+	mww 0xf4300020 0x00000007
+	mww 0xf4300024 0x0000000A
+	mww 0xf4300028 0x00000013
+	mww 0xf430002C 0x0000010A
+	mww 0xf4300030 0x00000013
+	mww 0xf4300034 0x00000002
+	mww 0xf4300038 0x00000002
+	mww 0xf430003C 0x00000001
+	mww 0xf4300040 0x0000000A
+	mww 0xf4300044 0x0000000B
+	mww 0xf4300048 0x00000014
+	mww 0xf430000C 0x00008011
+	mww 0xf4300304 0x00000011
+	mww 0xf4300010 0x00000A60
+	mww 0xf4300200 0x000140FC
+	mww 0xf4300008 0x000C0000
+	mww 0xf4300008 0x00000000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00080031
+	mww 0xf4300004 0x00000000
+
+	sleep 10
+#	adapter speed NNNN
+
+# remap off in case of IROM boot
+	mww 0xf0000004 0x00000001
+
+}
+
+# comment the following out if usinf J-Link, it soes not support DCC
+arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tp-link_tl-mr3020.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tp-link_tl-mr3020.cfg
new file mode 100644
index 0000000..1d1d627
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tp-link_tl-mr3020.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/atheros_ar9331.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	ar9331_25mhz_pll_init
+	sleep 1
+	ar9331_ddr1_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tp-link_wdr4300.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tp-link_wdr4300.cfg
new file mode 100644
index 0000000..9947366
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tp-link_wdr4300.cfg
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/atheros_ar9344.cfg]
+
+reset_config trst_only separate
+
+proc ar9344_40mhz_pll_init {} {
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0x13210f00
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x03000000
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0x13210f00
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000000
+	# QCA_PLL_SRIF_BB_DPLL_BASE_REG
+	mww 0xb8116188 0x03000000
+
+	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
+	mww 0xb8050008 0x0130001C
+	mww 0xb8050008 0x0130001C
+	mww 0xb8050008 0x0130001C
+
+	# QCA_PLL_CPU_PLL_CFG_REG
+	mww 0xb8050000 0x40021380
+	# QCA_PLL_DDR_PLL_CFG_REG
+	mww 0xb8050004 0x40815800
+	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
+	mww 0xb8050008 0x0130801C
+
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0x10810F00
+	mww 0xb81161C0 0x41C00000
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0xD0810F00
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x03000000
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0xD0800F00
+
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x03000000
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x43000000
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x030003E8
+
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0x10810F00
+	mww 0xb8116240 0x41680000
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0xD0810F00
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000000
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0xD0800F00
+
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000000
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x43000000
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000718
+
+	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
+	mww 0xb8050008 0x01308018
+	mww 0xb8050008 0x01308010
+	mww 0xb8050008 0x01308000
+
+	# QCA_PLL_DDR_PLL_DITHER_REG
+	mww 0xb8050044 0x78180200
+	# QCA_PLL_CPU_PLL_DITHER_REG
+	mww 0xb8050048 0x41C00000
+
+}
+
+proc ar9344_ddr_init {} {
+	# QCA_DDR_CTRL_CFG_REG
+	mww 0xb8000108 0x40
+	# QCA_DDR_RD_DATA_THIS_CYCLE_REG
+	mww 0xb8000018 0xFF
+	# QCA_DDR_BURST_REG
+	mww 0xb80000C4 0x74444444
+	# QCA_DDR_BURST2_REG
+	mww 0xb80000C8 0x0222
+	# QCA_AHB_MASTER_TOUT_MAX_REG
+	mww 0xb80000CC 0xFFFFF
+
+	# QCA_DDR_CFG_REG
+	mww 0xb8000000 0xC7D48CD0
+	# QCA_DDR_CFG2_REG
+	mww 0xb8000004 0x9DD0E6A8
+
+	# QCA_DDR_DDR2_CFG_REG
+	mww 0xb80000B8 0x0E59
+	# QCA_DDR_CFG2_REG
+	mww 0xb8000004 0x9DD0E6A8
+
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x08
+	mww 0xb8000010 0x08
+	mww 0xb8000010 0x10
+	mww 0xb8000010 0x20
+	# QCA_DDR_EMR_REG
+	mww 0xb800000C 0x02
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x02
+
+	# QCA_DDR_MR_REG
+	mww 0xb8000008 0x0133
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x1
+	mww 0xb8000010 0x8
+	mww 0xb8000010 0x8
+	mww 0xb8000010 0x4
+	mww 0xb8000010 0x4
+
+	# QCA_DDR_MR_REG
+	mww 0xb8000008 0x33
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x1
+
+	# QCA_DDR_EMR_REG
+	mww 0xb800000C 0x0382
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x2
+	# QCA_DDR_EMR_REG
+	mww 0xb800000C 0x0402
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x2
+
+	# QCA_DDR_REFRESH_REG
+	mww 0xb8000014 0x4270
+
+	# QCA_DDR_TAP_CTRL_0_REG
+	mww 0xb800001C 0x0e
+	# QCA_DDR_TAP_CTRL_1_REG
+	mww 0xb8000020 0x0e
+	# QCA_DDR_TAP_CTRL_2_REG
+	mww 0xb8000024 0x0e
+	# QCA_DDR_TAP_CTRL_3_REG
+	mww 0xb8000028 0x0e
+}
+
+$_TARGETNAME configure -event reset-init {
+
+	# mww 0xb806001c 0x1000000
+	ar9344_40mhz_pll_init
+	sleep 100
+
+	# flash remap
+	# SPI_CONTROL_ADDR
+	mww 0xbF000004 0x43
+
+	ar9344_ddr_init
+	sleep 100
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/trion_t20_bga256.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/trion_t20_bga256.cfg
new file mode 100644
index 0000000..ca44f0b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/trion_t20_bga256.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Trion® T20 BGA256 Development Kit
+# https://www.efinixinc.com/docs/trion20-devkit-ug-v1.5.pdf
+#
+# works after power cycle or pushing sw1.
+# it is because we cannot control CDONE which is connected to ftdi channel 0
+# note from an006: For JTAG programming, T4, T8, T13, and T20 FPGAs use the
+# CRESET_N and SS_N pins in addition to the standard JTAG pins.
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 1
+ftdi layout_init 0x0008 0x008b
+reset_config none
+transport select jtag
+adapter speed 6000
+
+source [find fpga/efinix_trion.cfg]
+
+#openocd -f board/trion_t20_bga256.cfg -c "init" -c "pld load trion.pld outflow/trion_blinker.bit"
+#ipdbg create-hub trion.ipdbghub -tap trion.tap -ir 0x8
+#trion.ipdbghub ipdbg start -tool 0 -port 5555
+
+set JTAGSPI_CHAIN_ID trion.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init trion.pld "trion_jtagspi/outflow/trion_jtagspi.bit" 0xAB
+#jtagspi_program trion_blinker/outflow/trion_blinker.bin 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-k60f120m.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-k60f120m.cfg
new file mode 100644
index 0000000..5914cf0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-k60f120m.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale TWRK60F120M development board
+#
+
+source [find target/k60.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	puts "-event reset-init occurred"
+}
+
+#
+# Definitions for the additional 'program flash' banks
+# (instructions and/or data)
+#
+flash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME
+flash bank pflash.2 kinetis 0x00080000 0x40000 0 4 $_TARGETNAME
+flash bank pflash.3 kinetis 0x000c0000 0x40000 0 4 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-k60n512.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-k60n512.cfg
new file mode 100644
index 0000000..b7743a5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-k60n512.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale TWRK60N512 development board
+#
+
+source [find target/k60.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	puts "-event reset-init occurred"
+}
+
+#
+# Definitions for the additional 'program flash' bank
+# (instructions and/or data)
+#
+flash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-vf65gs10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-vf65gs10.cfg
new file mode 100644
index 0000000..bfc7288
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-vf65gs10.cfg
@@ -0,0 +1,203 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration file for the Freescale VF65GS10 tower board
+#
+# Board has a 20 pin Cortex+ETM debug connector with only nSRST available
+reset_config srst_only
+
+# This configuration file only deals with the hardware JTAG.
+# There is has also an embedded Kinetis K20 with OpenSDA
+# where a CMSIS-DAP application can be installed.
+
+# Source generic VF6xx target configuration
+source [find target/vybrid_vf6xx.cfg]
+
+# basic DDR memory init, setting up pad configuration
+# for DDR first then configuring the DDRMC for the
+# board
+proc ddr_init { } {
+	# iomux ddr
+	mww phys 0x40048220 0x00000180
+	mww phys 0x40048224 0x00000180
+	mww phys 0x40048228 0x00000180
+	mww phys 0x4004822c 0x00000180
+	mww phys 0x40048230 0x00000180
+	mww phys 0x40048234 0x00000180
+	mww phys 0x40048238 0x00000180
+	mww phys 0x4004823c 0x00000180
+	mww phys 0x40048240 0x00000180
+	mww phys 0x40048244 0x00000180
+	mww phys 0x40048248 0x00000180
+	mww phys 0x4004824c 0x00000180
+	mww phys 0x40048250 0x00000180
+	mww phys 0x40048254 0x00000180
+	mww phys 0x40048258 0x00000180
+	mww phys 0x4004825c 0x00000180
+	mww phys 0x40048260 0x00000180
+	mww phys 0x40048264 0x00000180
+	mww phys 0x40048268 0x00000180
+	mww phys 0x4004826c 0x00000180
+	mww phys 0x40048270 0x00000180
+	mww phys 0x40048274 0x00000180
+	mww phys 0x40048278 0x00000180
+	mww phys 0x4004827c 0x00010180
+	mww phys 0x40048280 0x00010180
+	mww phys 0x40048284 0x00010180
+	mww phys 0x40048288 0x00010180
+	mww phys 0x4004828c 0x00010180
+	mww phys 0x40048290 0x00010180
+	mww phys 0x40048294 0x00010180
+	mww phys 0x40048298 0x00010180
+	mww phys 0x4004829c 0x00010180
+	mww phys 0x400482a0 0x00010180
+	mww phys 0x400482a4 0x00010180
+	mww phys 0x400482a8 0x00010180
+	mww phys 0x400482ac 0x00010180
+	mww phys 0x400482b0 0x00010180
+	mww phys 0x400482b4 0x00010180
+	mww phys 0x400482b8 0x00010180
+	mww phys 0x400482bc 0x00010180
+	mww phys 0x400482c0 0x00010180
+	mww phys 0x400482c4 0x00010180
+	mww phys 0x400482c8 0x00010180
+	mww phys 0x400482cc 0x00000180
+	mww phys 0x400482d0 0x00000180
+	mww phys 0x400482d4 0x00000180
+	mww phys 0x400482d8 0x00000180
+	mww phys 0x4004821c 0x000001a0
+	# ddr_ctrl_init
+	mww phys 0x400ae000 0x00000600
+	mww phys 0x400ae008 0x00000020
+	mww phys 0x400ae028 0x00013880
+	mww phys 0x400ae02c 0x00030d40
+	mww phys 0x400ae030 0x0000050c
+	mww phys 0x400ae034 0x15040400
+	mww phys 0x400ae038 0x1406040f
+	mww phys 0x400ae040 0x04040000
+	mww phys 0x400ae044 0x006db00c
+	mww phys 0x400ae048 0x00000403
+	mww phys 0x400ae050 0x01000000
+	mww phys 0x400ae054 0x00060001
+	mww phys 0x400ae058 0x000c0000
+	mww phys 0x400ae05c 0x03000200
+	mww phys 0x400ae060 0x00000006
+	mww phys 0x400ae064 0x00010000
+	mww phys 0x400ae068 0x0c30002c
+	mww phys 0x400ae070 0x00000000
+	mww phys 0x400ae074 0x00000003
+	mww phys 0x400ae078 0x0000000a
+	mww phys 0x400ae07c 0x003001d4
+	mww phys 0x400ae084 0x00010000
+	mww phys 0x400ae088 0x00050500
+	mww phys 0x400ae098 0x00000000
+	mww phys 0x400ae09c 0x04001002
+	mww phys 0x400ae0a4 0x00000001
+	mww phys 0x400ae0c0 0x00460420
+	mww phys 0x400ae108 0x01000200
+	mww phys 0x400ae10c 0x00000040
+	mww phys 0x400ae114 0x00000200
+	mww phys 0x400ae118 0x00000040
+	mww phys 0x400ae120 0x00000000
+	mww phys 0x400ae124 0x0a010300
+	mww phys 0x400ae128 0x01014040
+	mww phys 0x400ae12c 0x01010101
+	mww phys 0x400ae130 0x03030100
+	mww phys 0x400ae134 0x01000101
+	mww phys 0x400ae138 0x0700000c
+	mww phys 0x400ae13c 0x00000000
+	mww phys 0x400ae148 0x10000000
+	mww phys 0x400ae15c 0x01000000
+	mww phys 0x400ae160 0x00040000
+	mww phys 0x400ae164 0x00000002
+	mww phys 0x400ae16c 0x00020000
+	mww phys 0x400ae180 0x00002819
+	mww phys 0x400ae184 0x01000000
+	mww phys 0x400ae188 0x00000000
+	mww phys 0x400ae18c 0x00000000
+	mww phys 0x400ae198 0x00000000
+	mww phys 0x400ae1a4 0x00000c00
+	mww phys 0x400ae1a8 0x00000000
+	mww phys 0x400ae1b8 0x0000000c
+	mww phys 0x400ae1c8 0x00000000
+	mww phys 0x400ae1cc 0x00000000
+	mww phys 0x400ae1d4 0x00000000
+	mww phys 0x400ae1d8 0x01010000
+	mww phys 0x400ae1e0 0x02020000
+	mww phys 0x400ae1e4 0x00000202
+	mww phys 0x400ae1e8 0x01010064
+	mww phys 0x400ae1ec 0x00010101
+	mww phys 0x400ae1f0 0x00000064
+	mww phys 0x400ae1f8 0x00000800
+	mww phys 0x400ae210 0x00000506
+	mww phys 0x400ae224 0x00020000
+	mww phys 0x400ae228 0x01000000
+	mww phys 0x400ae22c 0x04070303
+	mww phys 0x400ae230 0x00000040
+	mww phys 0x400ae23c 0x06000080
+	mww phys 0x400ae240 0x04070303
+	mww phys 0x400ae244 0x00000040
+	mww phys 0x400ae248 0x00000040
+	mww phys 0x400ae24c 0x000f0000
+	mww phys 0x400ae250 0x000f0000
+	mww phys 0x400ae25c 0x00000101
+	mww phys 0x400ae268 0x682c4000
+	mww phys 0x400ae26c 0x00000012
+	mww phys 0x400ae278 0x00000006
+	mww phys 0x400ae284 0x00010202
+	mww phys 0x400ae400 0x00002613
+	mww phys 0x400ae440 0x00002613
+	mww phys 0x400ae404 0x00002615
+	mww phys 0x400ae444 0x00002615
+	mww phys 0x400ae408 0x00210000
+	mww phys 0x400ae448 0x00210000
+	mww phys 0x400ae488 0x00210000
+	mww phys 0x400ae40c 0x0001012a
+	mww phys 0x400ae44c 0x0001012a
+	mww phys 0x400ae48c 0x0001012a
+	mww phys 0x400ae410 0x00002400
+	mww phys 0x400ae450 0x00002400
+	mww phys 0x400ae490 0x00002400
+	mww phys 0x400ae4c4 0x00000000
+	mww phys 0x400ae4c8 0x00001100
+	mww phys 0x400ae4d0 0x00010101
+	mww phys 0x400ae000 0x00000601
+}
+
+# clock control init, setting up basic
+# clocks
+proc clock_init { } {
+	# captured from u-boot
+	mww phys 0x4006b040 0xffffffff
+	mww phys 0x4006b044 0xffffffff
+	mww phys 0x4006b048 0xffffffff
+	mww phys 0x4006b04c 0xffffffff
+	mww phys 0x4006b050 0xffffffff
+	mww phys 0x4006b058 0xffffffff
+	mww phys 0x4006b05c 0xffffffff
+	mww phys 0x4006b060 0xffffffff
+	mww phys 0x4006b064 0xffffffff
+	mww phys 0x4006b068 0xffffffff
+	mww phys 0x40050030 0x00002001
+	mww phys 0x40050270 0x80002001
+	mww phys 0x4006b000 0x00011005
+	mww phys 0x4006b008 0x0001ff24
+	mww phys 0x4006b00c 0x00000810
+	mww phys 0x4006b010 0x00cc0000
+	mww phys 0x4006b014 0x01000000
+	mww phys 0x4006b018 0x20000000
+	mww phys 0x4006b01c 0x0000001f
+	mww phys 0x4006b020 0x00000000
+}
+
+# This function applies the initial configuration after a "reset init"
+# command
+proc board_init { } {
+	clock_init
+	ddr_init
+}
+
+# hook the init function into the reset-init event
+${_TARGETNAME}0 configure -event reset-init { board_init }
+# set a slow default JTAG clock, can be overridden later
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-vf65gs10_cmsisdap.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-vf65gs10_cmsisdap.cfg
new file mode 100644
index 0000000..86930c5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/twr-vf65gs10_cmsisdap.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration file for the Freescale VF65GS10 tower board
+#
+# CMSIS-DAP via USB-OTG connector
+#
+source [find interface/cmsis-dap.cfg]
+
+# only SWD is supported by the CMSIS-DAP on this board
+transport select swd
+
+# Source generic part of twr-vf65gs10 configuration
+source [find board/twr-vf65gs10.cfg]
+
+# override reset configuration
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tx25_stk5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tx25_stk5.cfg
new file mode 100644
index 0000000..5bf8fd0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tx25_stk5.cfg
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# -------------------------------------------------------------------------
+# KaRo TX25 CPU Module on a StarterkitV base board
+# http://www.karo-electronics.com/tx25.html
+# -------------------------------------------------------------------------
+
+
+source [find target/imx25.cfg]
+
+	#-------------------------------------------------------------------------
+	# Declare Nand
+	#-------------------------------------------------------------------------
+
+	nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
+
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { tx25_init }
+
+
+proc tx25_init { } {
+
+	#-------------------------------------------------------------------------
+	# AIPS setup - Only setup MPROTx registers. The PACR default values are good.
+	# Set all MPROTx to be non-bufferable, trusted for R/W,
+	# not forced to user-mode.
+	#-------------------------------------------------------------------------
+
+	mww 0x43f00000 0x77777777
+	mww 0x43f00004 0x77777777
+	mww 0x53f00000 0x77777777
+	mww 0x53f00004 0x77777777
+
+	sleep 100
+
+	#-------------------------------------------------------------------------
+	# MAX (Multi-Layer AHB Crossbar Switch) setup
+	# MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
+	#-------------------------------------------------------------------------
+
+	mww 0x43f04000 0x00043210
+	mww 0x43f04100 0x00043210
+	mww 0x43f04200 0x00043210
+	mww 0x43f04300 0x00043210
+	mww 0x43f04400 0x00043210
+
+	# SGPCR - always park on last master
+	mww 0x43f04010 0x10
+	mww 0x43f04110 0x10
+	mww 0x43f04210 0x10
+	mww 0x43f04310 0x10
+	mww 0x43f04410 0x10
+
+	# MGPCR - restore default values
+	mww 0x43f04800 0x0
+	mww 0x43f04900 0x0
+	mww 0x43f04a00 0x0
+	mww 0x43f04b00 0x0
+	mww 0x43f04c00 0x0
+
+	# Configure M3IF registers
+	# M3IF Control Register (M3IFCTL) for MX25
+	# MRRP[0] = LCDC           on priority list (1 << 0)  = 0x00000001
+	# MRRP[1] = MAX1       not on priority list (0 << 1)  = 0x00000000
+	# MRRP[2] = MAX0       not on priority list (0 << 2)  = 0x00000000
+	# MRRP[3] = USB HOST   not on priority list (0 << 3)  = 0x00000000
+	# MRRP[4] = SDMA       not on priority list (0 << 4)  = 0x00000000
+	# MRRP[5] = SD/ATA/FEC not on priority list (0 << 5)  = 0x00000000
+	# MRRP[6] = SCMFBC     not on priority list (0 << 6)  = 0x00000000
+	# MRRP[7] = CSI        not on priority list (0 << 7)  = 0x00000000
+	#                                                       ----------
+	#                                                       0x00000001
+	mww 0xb8003000 0x00000001
+
+	#-------------------------------------------------------------------------
+	# configure ARM CLK
+	#-------------------------------------------------------------------------
+
+	# Set the Clock CTL (HRM p. 355)
+	mww 0x53F80008 0x20034000
+
+	# Setup Clock Gating CTL 0-2 (HRM p. 357)
+	mww 0x53F8000C 0x1fffffff
+	mww 0x53F80010 0xffffffff
+	mww 0x53F80014 0x000fdfff
+
+	#-------------------------------------------------------------------------
+	# SDRAM initialization
+	#-------------------------------------------------------------------------
+
+	# set to 3.3v SDRAM
+	mww 0x43FAC454 0x00000800
+
+	# reset (set up ESDMISC)
+	mww 0xB8001010 0x00000002
+
+	# Setup for SDRAM Bank 0
+	#-------------------------------------------------------------------------
+
+	# Write ESDCFG0
+	mww 0xB8001004 0x00095728
+
+	# CTL SMode = Precharge command
+	mww 0xB8001000 0x92116480
+	mww 0x80000400 0x00000000
+
+	# CTL SMode = Auto Refresh command
+	mww 0xB8001000 0xA2116480
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+
+	# CTL SMode = Load Mode Register command
+	mww 0xB8001000 0xB2116480
+	mwb 0x80000033 0x00
+
+	# CTL SMode = normal
+	mww 0xB8001000 0x82116480
+
+	# Setup for SDRAM Bank 1
+	#-------------------------------------------------------------------------
+
+	# Write ESDCFG1
+	mww 0xB800100C 0x00095728
+
+	# CTL SMode = Precharge command
+	mww 0xB8001008 0x92116480
+	mww 0x90000400 0x00000000
+
+	# CTL SMode = Auto Refresh command
+	mww 0xB8001008 0xA2116480
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+
+	# CTL SMode = Load Mode Register command
+	mww 0xB8001008 0xB2116480
+	mwb 0x90000033 0x00
+
+	# CTL SMode = normal
+	mww 0xB8001008 0x82116480
+
+	# GPIO configuration
+	#-------------------------------------------------------------------------
+
+	mww 0x43FAC02C 0x00000015
+	mww 0x53FD0000 0x01000000
+	mww 0x53FD0004 0x00000080
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tx27_stk5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tx27_stk5.cfg
new file mode 100644
index 0000000..061f1f9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/tx27_stk5.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# KaRo TX27 CPU Module on a StarterkitV base board
+#
+# http://www.karo-electronics.com/tx27.html
+#
+source [find target/imx27.cfg]
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { tx27_init }
+
+proc tx27_init { } {
+	# This setup puts RAM at 0xA0000000
+	# init_aipi (AIPI1.PSR0, AIPI2.PSR0, AIPI1.PSR1 and AIPI2.PSR1)
+	mww 0x10000000 0x20040304
+	mww 0x10020000 0x00000000
+	mww 0x10000004 0xDFFBFCFB
+	mww 0x10020004 0xFFFFFFFF
+
+	sleep 100
+
+	#init_max ( PORT0.MPR, #PORT0.AMPR, #PORT1.MPR, #PORT1.AMPR, #PORT2.MPR, #PORT2.AMPR)
+	mww 0x1003F000 0x00302145
+	mww 0x1003F004 0x00302145
+	mww 0x1003F100 0x00302145
+	mww 0x1003F104 0x00302145
+	mww 0x1003F200 0x00302145
+	mww 0x1003F204 0x00302145
+
+	#init_drive_strength (#DSCR3, #DSCR5, #DSCR6, #DSCR7, #DSCR8 )
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
+
+	#init_sdram_speed
+	#mww 0xD8001010 0x00000004
+	mww 0xD8001010 0x00000024
+
+	mww 0xD8001004 0x00395729
+
+	mww 0xD8001000 0x92120000
+	mww 0xA0000400 0x0
+
+	mww 0xD8001000 0xA2120000
+	mww 0xA0000000 0x0
+	mww 0xA0000000 0x0
+
+	mww 0xD8001000 0xB2120000
+	mdb 0xA0000000
+	mdb 0xA0000033
+
+	mww 0xD8001000 0x82126485
+
+	# =============================================
+	# Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz)
+	# =============================================
+	mww 0xD8002000 0x23524E80
+	mww 0xD8002004 0x10000D03
+	mww 0xD8002008 0x00720900
+
+	nand probe 0
+}
+
+nand device tx27.nand mxc $_TARGETNAME mx27 hwecc biswap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/unknown_at91sam9260.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/unknown_at91sam9260.cfg
new file mode 100644
index 0000000..cab18b6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/unknown_at91sam9260.cfg
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Thanks to Pieter Conradie for this script!
+#
+# Unknown vendor board contains:
+#
+# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
+#                     OSCSEL configured for internal RC oscillator (22 to 42 kHz)
+#
+# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
+# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
+##################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 22 to 42 kHz.
+        # JTAG Frequency must be 6 times slower.
+        jtag_rclk 3
+        halt
+	# RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc28 0x205dbf09         ;# CKGR_PLLAR: Set PLLA Register for 192.512MHz
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
+        sleep 10                          ;# wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	mww 0xffffec00 0x01020102         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+	mww 0xffffec04 0x09070806         ;# SMC_PULSE0
+	mww 0xffffec08 0x000d000b         ;# SMC_CYCLE0
+	mww 0xffffec0c 0x00001003         ;# SMC_MODE0
+
+	flash probe 0                     ;# Identify flash bank 0
+
+	mww 0xfffff870 0xffff0000         ;# PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         ;# PIO_PDR  : Disable PIO function for D15..D31
+        mww 0xfffff860 0xffff0000         ;# PIO_PUDR : Disable D15..D31 pull-ups
+
+        mww 0xffffef1c 0x00010102         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM
+                                           #            VDDIOMSEL set for +3V3 memory
+                                           #            Disable D0..D15 pull-ups
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2a2              ;# SDRAMC_TR : Set refresh timer count to 7us
+}
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/uptech_2410.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/uptech_2410.cfg
new file mode 100644
index 0000000..ba269f5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/uptech_2410.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target Configuration for the Uptech 2410 board.
+# This configuration should also work on smdk2410, but I haven't tested it yet.
+# Author: xionglingfeng@Gmail.com
+
+source [find target/samsung_s3c2410.cfg]
+
+$_TARGETNAME configure -event reset-init { uptech2410_init }
+$_TARGETNAME configure -event gdb-attach { reset init }
+
+proc init_pll_sdram { } {
+	#echo "---------- Initializing PLL and SDRAM ---------"
+	#watchdog timer disable
+	mww phys 0x53000000 0x00000000
+
+	#disable all interrupts
+	mww phys 0x4a000008 0xffffffff
+
+	#disable all sub-interrupts
+	mww phys 0x4a00001c 0x000007ff
+
+	#clear all source pending bits
+	mww phys 0x4a000000 0xffffffff
+
+	#clear all sub-source pending bits
+	mww phys 0x4a000018 0x000007ff
+
+	#clear interrupt pending bit
+	mww phys 0x4a000010 0xffffffff
+
+	#PLL locktime counter
+	mww phys 0x4c000000 0x00ffffff
+
+	#Fin=12MHz Fout=202.8MHz
+	#mww phys 0x4c000004 0x000a1031
+
+	#FCLK:HCLK:PCLK = 1:2:4
+	mww phys 0x4c000014 0x00000003
+
+
+	mww phys 0x48000000 0x11111110
+	mww phys 0x48000004 0x00007FFC
+	mww phys 0x48000008 0x00007FFC
+	mww phys 0x4800000c 0x00000700
+	mww phys 0x48000010 0x00000700
+	mww phys 0x48000014 0x00002E50
+	mww phys 0x48000018 0x00002E50
+	mww phys 0x4800001c 0x00018005
+	mww phys 0x48000020 0x00018005
+	mww phys 0x48000024 0x008c04e9
+	mww phys 0x48000028 0x000000b2
+	mww phys 0x4800002c 0x00000030
+	mww phys 0x48000030 0x00000030
+}
+
+proc uptech2410_init { } {
+	init_pll_sdram
+	#echo "---------- Probing Nand flash ----------"
+	nand probe 0
+	#echo "---------- Enable some functions ----------"
+}
+
+set _NANDNAME $_CHIPNAME.nand
+nand device $_NANDNAME s3c2410 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a53x2_dap.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a53x2_dap.cfg
new file mode 100644
index 0000000..bcf8b44
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a53x2_dap.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CORES 2
+set CHIPNAME a53
+set ACCESSPORT 0
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x80810000 0x80910000}
+set CTIBASE {0x80820000 0x80920000}
+
+# vdebug select transport
+transport select dapdirect_swd
+
+# JTAG reset config, frequency and reset delay
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_swdp_bfm 10ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
+
+swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+source [find target/vd_aarch64.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a53x2_jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a53x2_jtag.cfg
new file mode 100644
index 0000000..0c3eebd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a53x2_jtag.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CORES 2
+set CHIPNAME a53
+set ACCESSPORT 0
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x80810000 0x80910000}
+set CTIBASE {0x80820000 0x80920000}
+set CPUTAPID 0x5ba00477
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
+
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
+jtag arp_init-reset
+
+source [find target/vd_aarch64.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a75x4_dap.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a75x4_dap.cfg
new file mode 100644
index 0000000..5c2a2ef
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a75x4_dap.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CORES 4
+set CHIPNAME a75
+set ACCESSPORT 0x00040000
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
+set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
+
+# vdebug select transport
+transport select dapdirect_swd
+
+# JTAG reset config, frequency and reset delay
+adapter speed 200000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_dap6_bfm 2250ps
+
+# DMA Memories to access backdoor (up to 20)
+#vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
+
+swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+source [find target/vd_aarch64.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a75x4_jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a75x4_jtag.cfg
new file mode 100644
index 0000000..c94a719
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_a75x4_jtag.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CORES 4
+set CHIPNAME a75
+set ACCESSPORT 0x00040000
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
+set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
+set CPUTAPID 0x4ba06477
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 1500000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 333ps
+
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
+jtag arp_init-reset
+
+source [find target/vd_aarch64.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_m4_dap.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_m4_dap.cfg
new file mode 100644
index 0000000..5d3605a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_m4_dap.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex m4 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME m4
+set MEMSTART 0x00000000
+set MEMSIZE 0x10000
+
+# vdebug select transport
+transport select dapdirect_swd
+adapter speed 25000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_swdp_bfm 20ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
+
+swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+source [find target/vd_cortex_m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_m4_jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_m4_jtag.cfg
new file mode 100644
index 0000000..3b32e17
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_m4_jtag.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex m4 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME m4
+set MEMSTART 0x00000000
+set MEMSIZE 0x10000
+set CPUTAPID 0x4ba00477
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 25000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 20ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
+
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
+jtag arp_init-reset
+
+source [find target/vd_cortex_m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_m7_jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_m7_jtag.cfg
new file mode 100644
index 0000000..9a89584
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_m7_jtag.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex m7 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME m7
+set MEMSTART 0x00000000
+set MEMSIZE 0x100000
+set CPUTAPID 0x0ba02477
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $MEMSTART $MEMSIZE
+
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
+jtag arp_init-reset
+
+source [find target/vd_cortex_m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_pulpissimo_jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_pulpissimo_jtag.cfg
new file mode 100644
index 0000000..a3f5a84
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_pulpissimo_jtag.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV Ibex core with Pulpissimo through JTAG
+
+source [find interface/vdebug.cfg]
+
+set _CHIPNAME ibex
+set _HARTID 0x20
+set _CPUTAPID 0x249511c3
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 12500
+adapter srst delay 10
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 40ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[0\].sram_i.mem_array 0x1c000000 0x8000
+vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[1\].sram_i.mem_array 0x1c008000 0x8000
+vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2\[0\].sram_i.mem_array 0x1c010000 0x80000
+
+# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $_CPUTAPID
+
+jtag arp_init-reset
+
+source [find target/vd_riscv.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_swerv_jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_swerv_jtag.cfg
new file mode 100644
index 0000000..c5d33f2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_swerv_jtag.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV swerv core with Swerv through JTAG
+
+source [find interface/vdebug.cfg]
+
+set _CHIPNAME rv32
+set _HARTID 0x00
+set _CPUTAPID 0x1000008b
+set _MEMSTART 0x00000000
+set _MEMSIZE 0x10000
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.i_ahb_ic.mem $_MEMSTART $_MEMSIZE
+
+# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
+
+jtag arp_init-reset
+
+source [find target/vd_riscv.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_xt8_jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_xt8_jtag.cfg
new file mode 100644
index 0000000..867b9e7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/vd_xt8_jtag.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Xtensa xt8 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME xt8
+set CPUTAPID 0x120034e5
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor, the values come from generated xtensa-core-xt8.cfg
+#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray 0x40000000 0x100000
+#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray 0x3ff00000 0x40000
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
+source  [find target/xtensa-core-xt8.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/verdex.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/verdex.cfg
new file mode 100644
index 0000000..8511120
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/verdex.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Gumstix Verdex XM4 and XL6P (PXA270)
+
+set CHIPNAME verdex
+source [find target/pxa270.cfg]
+
+# The board supports separate reset lines
+# Override this in the interface config for parallel dongles
+reset_config trst_and_srst separate
+
+# XM4 = 400MHz, XL6P = 600MHz...let's run at 0.1*400MHz=40MHz
+adapter speed 40000
+
+# flash bank     
+# XL6P has 32 MB flash
+flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x02000000 2 2 $_TARGETNAME
+# XM4 has 16 MB flash
+#flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/voipac.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/voipac.cfg
new file mode 100644
index 0000000..74e651a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/voipac.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Voipac PXA270/PXA270M module.
+
+set CHIPNAME voipac
+source [find target/pxa270.cfg]
+
+# The board supports separate reset lines
+# Override this in the interface config for parallel dongles
+reset_config trst_and_srst separate
+
+# flash bank     
+flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
+flash bank $_CHIPNAME.flash1 cfi 0x02000000 0x2000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/voltcraft_dso-3062c.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/voltcraft_dso-3062c.cfg
new file mode 100644
index 0000000..fd56a81
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/voltcraft_dso-3062c.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Voltcraft DSO-3062C digital oscilloscope (uses a Samsung S3C2440)
+#
+# http://www.eevblog.com/forum/general-chat/hantek-tekway-dso-hack-get-200mhz-bw-for-free/
+# http://www.mikrocontroller.net/topic/249628
+# http://elinux.org/Das_Oszi
+# http://randomprojects.org/wiki/Voltcraft_DSO-3062C
+#
+
+# Enable this if your JTAG adapter supports multiple transports (JTAG or SWD).
+# Otherwise comment it out, as it will cause an OpenOCD error.
+### transport select jtag
+
+source [find target/samsung_s3c2440.cfg]
+
+adapter speed 16000
+
+# Samsung K9F1208U0C NAND flash chip (64MiB, 3.3V, 8-bit)
+nand device $_CHIPNAME.nand s3c2440 $_TARGETNAME
+
+# arm7_9 fast_memory_access enable
+# arm7_9 dcc_downloads enable
+
+init
+reset
+halt
+scan_chain
+targets
+nand probe 0
+nand list
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/x300t.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/x300t.cfg
new file mode 100644
index 0000000..c57c9d9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/x300t.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for the T-Home X300T / X301T IPTV box,
+# which are based on IPTV reference designs from Kiss/Cisco KMM-3***
+#
+# It has Sigma Designs SMP8634 chip.
+source [find target/smp8634.cfg]
+
+$_TARGETNAME configure -event reset-init { x300t_init }
+
+# 1MB CFI capable flash
+# flash bank       
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xac000000 0x100000 2 2 $_TARGETNAME
+
+proc x300t_init { } {
+	# Setup SDRAM config and flash mapping
+	# initialize ram
+	mww 0xa003fffc 3
+	mww 0xa003fffc 2
+	mww 0xa0030000 0xE34111BA
+	mww 0xa003fffc 0xa4444
+	mww 0xa003fffc 0
+
+	# remap boot vector in CPU local RAM
+	mww 0xa006f000 0x60000
+
+	# map flash to CPU address space REG_BASE_cpu_block+CPU_remap4
+	mww 0x0006f010 0x48000000
+
+	# map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS)
+	mww 0x00061ff0 0x48000000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc-2go.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc-2go.cfg
new file mode 100644
index 0000000..dd78a12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc-2go.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC 2Go
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+set CHIPNAME xmc1100
+set WORKAREASIZE 0x4000
+source [find target/xmc1xxx.cfg]
+
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc1100-boot-kit.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc1100-boot-kit.cfg
new file mode 100644
index 0000000..12ee3e2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc1100-boot-kit.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC1100 Boot Kit
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+set CHIPNAME xmc1100
+set WORKAREASIZE 0x4000
+source [find target/xmc1xxx.cfg]
+
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4200-application-kit-actuator.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4200-application-kit-actuator.cfg
new file mode 100644
index 0000000..79befaa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4200-application-kit-actuator.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4200 Application Kit - Actuator
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+set CHIPNAME xmc4200
+source [find target/xmc4xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4300-relax.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4300-relax.cfg
new file mode 100644
index 0000000..b748793
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4300-relax.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4300 Relax EtherCAT Kit
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+set CHIPNAME xmc4300
+source [find target/xmc4xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4500-application-kit-general.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4500-application-kit-general.cfg
new file mode 100644
index 0000000..dbb5325
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4500-application-kit-general.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4500 Application Kit - General Purpose
+#
+
+set CHIPNAME xmc4500
+source [find target/xmc4xxx.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4500-application-kit-sdram.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4500-application-kit-sdram.cfg
new file mode 100644
index 0000000..580dfd8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4500-application-kit-sdram.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4500 Application Kit - SDRAM
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+
+set CHIPNAME xmc4500
+source [find target/xmc4xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4500-relax.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4500-relax.cfg
new file mode 100644
index 0000000..1239f04
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4500-relax.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4500 Relax Kit / Relax Lite Kit
+#
+
+#
+# Segger J-Link Lite XMC4500 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+# There's also an unpopulated 10-pin 0.05" pinout.
+
+set CHIPNAME xmc4500
+source [find target/xmc4xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4700-relax.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4700-relax.cfg
new file mode 100644
index 0000000..ac8ce26
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4700-relax.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4700 Relax Lite Kit / Relax Kit for 5V Shields / Relax Kit
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+# There's also an unpopulated 10-pin 0.05" pinout.
+
+set CHIPNAME xmc4700
+source [find target/xmc4xxx.cfg]
+
+# Relax Kit only: N25Q032A qSPI flash
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4800-relax.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4800-relax.cfg
new file mode 100644
index 0000000..d63159f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmc4800-relax.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4800 Relax EtherCAT Kit
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+# There's also an unpopulated 10-pin 0.05" pinout.
+
+set CHIPNAME xmc4800
+source [find target/xmc4xxx.cfg]
+
+# N25Q032A qSPI flash
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmos_xk-xac-xa8_arm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmos_xk-xac-xa8_arm.cfg
new file mode 100644
index 0000000..2e83977
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xmos_xk-xac-xa8_arm.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# xCORE-XA Core Module
+#
+# https://www.xmos.com/support/boards?product=17940
+#
+
+#
+# J-Link OB STM32F103
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+#
+# XS1-XAU8A-10
+#
+source [find target/xmos_xs1-xau8a-10_arm.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-kc705-ext-dap.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-kc705-ext-dap.cfg
new file mode 100644
index 0000000..ac92c70
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-kc705-ext-dap.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with various external adapters that support DAP, e.g. JLink
+#
+
+adapter speed 5000
+
+# KC705 supports DAP/JTAG
+transport select jtag
+set XTENSA_DAP enable
+set XTENSA_DAP_BASE 0x10000
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-kc705-ext.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-kc705-ext.cfg
new file mode 100644
index 0000000..6be0681
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-kc705-ext.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with various external adapters, e.g. Flyswatter2 or JLink
+#
+
+adapter speed 10000
+
+# KC705 supports JTAG only
+transport select jtag
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-kc705-onboard.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-kc705-onboard.cfg
new file mode 100644
index 0000000..f0a616c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-kc705-onboard.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with on-board (FTDI) adapter or various external adapters
+#
+
+source [find interface/ftdi/xt_kc705_ml605.cfg]
+adapter speed 10000
+
+# KC705 supports JTAG only
+transport select jtag
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-palladium-vdebug-dual.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-palladium-vdebug-dual.cfg
new file mode 100644
index 0000000..447bc1f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-palladium-vdebug-dual.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+source [find interface/vdebug.cfg]
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# Future improvement: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.VJTAG 10ns
+
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Configure dual-core TAP chain
+set XTENSA_NUM_CORES 2
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-palladium-vdebug.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-palladium-vdebug.cfg
new file mode 100644
index 0000000..f14d92d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-palladium-vdebug.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+source [find interface/vdebug.cfg]
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# Future improvement: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.VJTAG 10ns
+
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-rt685-ext.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-rt685-ext.cfg
new file mode 100644
index 0000000..03edb8d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/board/xtensa-rt685-ext.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP RT6XX Developemnt Platform with Xtensa HiFi DSP
+# Can be used with various external adapters that support DAP, e.g. JLink
+#
+
+adapter speed 10000
+
+# RT6XX supports SWD only
+transport select swd
+set XTENSA_DAP enable
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+source [find target/xtensa-core-nxp_rt600.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/aic.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/aic.tcl
new file mode 100644
index 0000000..6657b60
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/aic.tcl
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AIC_SMR      	[expr {$AT91C_BASE_AIC + 0x00000000} ]
+global AIC_SMR
+set AIC_SVR      	[expr {$AT91C_BASE_AIC + 0x00000080} ]
+global AIC_SVR
+set AIC_IVR      	[expr {$AT91C_BASE_AIC + 0x00000100} ]
+global AIC_IVR
+set AIC_FVR      	[expr {$AT91C_BASE_AIC + 0x00000104} ]
+global AIC_FVR
+set AIC_ISR      	[expr {$AT91C_BASE_AIC + 0x00000108} ]
+global AIC_ISR
+set AIC_IPR      	[expr {$AT91C_BASE_AIC + 0x0000010C} ]
+global AIC_IPR
+set AIC_IMR      	[expr {$AT91C_BASE_AIC + 0x00000110} ]
+global AIC_IMR
+set AIC_CISR     	[expr {$AT91C_BASE_AIC + 0x00000114} ]
+global AIC_CISR
+set AIC_IECR     	[expr {$AT91C_BASE_AIC + 0x00000120} ]
+global AIC_IECR
+set AIC_IDCR     	[expr {$AT91C_BASE_AIC + 0x00000124} ]
+global AIC_IDCR
+set AIC_ICCR     	[expr {$AT91C_BASE_AIC + 0x00000128} ]
+global AIC_ICCR
+set AIC_ISCR     	[expr {$AT91C_BASE_AIC + 0x0000012C} ]
+global AIC_ISCR
+set AIC_EOICR    	[expr {$AT91C_BASE_AIC + 0x00000130} ]
+global AIC_EOICR
+set AIC_SPU      	[expr {$AT91C_BASE_AIC + 0x00000134} ]
+global AIC_SPU
+set AIC_DCR      	[expr {$AT91C_BASE_AIC + 0x00000138} ]
+global AIC_DCR
+set AIC_FFER     	[expr {$AT91C_BASE_AIC + 0x00000140} ]
+global AIC_FFER
+set AIC_FFDR     	[expr {$AT91C_BASE_AIC + 0x00000144} ]
+global AIC_FFDR
+set AIC_FFSR     	[expr {$AT91C_BASE_AIC + 0x00000148} ]
+global AIC_FFSR
+
+
+proc aic_enable_disable_list { VAL ENAME DNAME } {
+    global AT91C_ID
+
+    show_mmr32_bits AT91C_ID $VAL
+
+}
+
+proc show_AIC_IPR_helper { NAME ADDR VAL } {
+    aic_enable_disable_list  $VAL "IRQ PENDING" "irq not-pending"
+}
+
+proc show_AIC_IMR_helper { NAME ADDR VAL } {
+    aic_enable_disable_list  $VAL "IRQ ENABLED" "irq disabled"
+}
+
+
+proc show_AIC { } {
+    global AIC_SMR
+    if [catch { set aaa [read_memory $AIC_SMR 32 [expr {32 * 4}]] } msg ] {
+	error [format "%s (%s)" $msg AIC_SMR]
+    }
+    echo "AIC_SMR: Mode & Type"
+    global AT91C_ID
+    for { set x 0 } { $x < 32 } {  } {
+	echo -n "   "
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo  [format "%2d: %5s 0x%08x"  $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+    }
+    global AIC_SVR
+    if [catch { set aaa [read_memory $AIC_SVR 32 [expr {32 * 4}]] } msg ] {
+	error [format "%s (%s)" $msg AIC_SVR]
+    }
+    echo "AIC_SVR: Vectors"
+    for { set x 0 } { $x < 32 } {  } {
+	echo -n "   "
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+    }
+
+    foreach REG {
+	AIC_IVR   AIC_FVR  AIC_ISR
+	AIC_IPR  AIC_IMR  AIC_CISR  AIC_IECR AIC_IDCR
+	AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU  AIC_DCR
+	AIC_FFER AIC_FFDR AIC_FFSR } {
+	if [catch { show_mmr32_reg $REG } msg ] {
+	    error $msg
+	    break
+	}
+    }
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_pio.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_pio.cfg
new file mode 100644
index 0000000..10a1d48
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_pio.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set PIO_PER	0x00	;# Enable Register
+set PIO_PDR	0x04	;# Disable Register
+set PIO_PSR	0x08	;# Status Register
+set PIO_OER	0x10	;# Output Enable Register
+set PIO_ODR	0x14	;# Output Disable Register
+set PIO_OSR	0x18	;# Output Status Register
+set PIO_IFER	0x20	;# Glitch Input Filter Enable
+set PIO_IFDR	0x24	;# Glitch Input Filter Disable
+set PIO_IFSR	0x28	;# Glitch Input Filter Status
+set PIO_SODR	0x30	;# Set Output Data Register
+set PIO_CODR	0x34	;# Clear Output Data Register
+set PIO_ODSR	0x38	;# Output Data Status Register
+set PIO_PDSR	0x3c	;# Pin Data Status Register
+set PIO_IER	0x40	;# Interrupt Enable Register
+set PIO_IDR	0x44	;# Interrupt Disable Register
+set PIO_IMR	0x48	;# Interrupt Mask Register
+set PIO_ISR	0x4c	;# Interrupt Status Register
+set PIO_MDER	0x50	;# Multi-driver Enable Register
+set PIO_MDDR	0x54	;# Multi-driver Disable Register
+set PIO_MDSR	0x58	;# Multi-driver Status Register
+set PIO_PUDR	0x60	;# Pull-up Disable Register
+set PIO_PUER	0x64	;# Pull-up Enable Register
+set PIO_PUSR	0x68	;# Pull-up Status Register
+set PIO_ASR	0x70	;# Peripheral A Select Register
+set PIO_BSR	0x74	;# Peripheral B Select Register
+set PIO_ABSR	0x78	;# AB Status Register
+set PIO_OWER	0xa0	;# Output Write Enable Register
+set PIO_OWDR	0xa4	;# Output Write Disable Register
+set PIO_OWSR	0xa8	;# Output Write Status Register
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_pmc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_pmc.cfg
new file mode 100644
index 0000000..a75cecd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_pmc.cfg
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set	AT91_PMC_SCER		[expr {$AT91_PMC + 0x00}]	;# System Clock Enable Register
+set	AT91_PMC_SCDR		[expr {$AT91_PMC + 0x04}]	;# System Clock Disable Register
+
+set	AT91_PMC_SCSR		[expr {$AT91_PMC + 0x08}]	;# System Clock Status Register
+set		AT91_PMC_PCK		[expr {1 <<  0}]		;# Processor Clock
+set		AT91RM9200_PMC_UDP	[expr {1 <<  1}]		;# USB Devcice Port Clock [AT91RM9200 only]
+set		AT91RM9200_PMC_MCKUDP	[expr {1 <<  2}]		;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
+set		AT91CAP9_PMC_DDR	[expr {1 <<  2}]		;# DDR Clock [CAP9 revC & some SAM9 only]
+set		AT91RM9200_PMC_UHP	[expr {1 <<  4}]		;# USB Host Port Clock [AT91RM9200 only]
+set		AT91SAM926x_PMC_UHP	[expr {1 <<  6}]		;# USB Host Port Clock [AT91SAM926x only]
+set		AT91CAP9_PMC_UHP	[expr {1 <<  6}]		;# USB Host Port Clock [AT91CAP9 only]
+set		AT91SAM926x_PMC_UDP	[expr {1 <<  7}]		;# USB Devcice Port Clock [AT91SAM926x only]
+set		AT91_PMC_PCK0		[expr {1 <<  8}]		;# Programmable Clock 0
+set		AT91_PMC_PCK1		[expr {1 <<  9}]		;# Programmable Clock 1
+set		AT91_PMC_PCK2		[expr {1 << 10}]		;# Programmable Clock 2
+set		AT91_PMC_PCK3		[expr {1 << 11}]		;# Programmable Clock 3
+set		AT91_PMC_HCK0		[expr {1 << 16}]		;# AHB Clock (USB host) [AT91SAM9261 only]
+set		AT91_PMC_HCK1		[expr {1 << 17}]		;# AHB Clock (LCD) [AT91SAM9261 only]
+
+set	AT91_PMC_PCER		[expr {$AT91_PMC + 0x10}]	;# Peripheral Clock Enable Register
+set	AT91_PMC_PCDR		[expr {$AT91_PMC + 0x14}]	;# Peripheral Clock Disable Register
+set	AT91_PMC_PCSR		[expr {$AT91_PMC + 0x18}]	;# Peripheral Clock Status Register
+
+set	AT91_CKGR_UCKR		[expr {$AT91_PMC + 0x1C}]	;# UTMI Clock Register [some SAM9, CAP9]
+set		AT91_PMC_UPLLEN		[expr {1   << 16}]		;# UTMI PLL Enable
+set		AT91_PMC_UPLLCOUNT	[expr {0xf << 20}]		;# UTMI PLL Start-up Time
+set		AT91_PMC_BIASEN		[expr {1   << 24}]		;# UTMI BIAS Enable
+set		AT91_PMC_BIASCOUNT	[expr {0xf << 28}]		;# UTMI BIAS Start-up Time
+
+set	AT91_CKGR_MOR		[expr {$AT91_PMC + 0x20}]	;# Main Oscillator Register [not on SAM9RL]
+set		AT91_PMC_MOSCEN		[expr {1    << 0}]		;# Main Oscillator Enable
+set		AT91_PMC_OSCBYPASS	[expr {1    << 1}]		;# Oscillator Bypass [SAM9x, CAP9]
+set		AT91_PMC_OSCOUNT	[expr {0xff << 8}]		;# Main Oscillator Start-up Time
+
+set	AT91_CKGR_MCFR		[expr {$AT91_PMC + 0x24}]	;# Main Clock Frequency Register
+set		AT91_PMC_MAINF		[expr {0xffff <<  0}]		;# Main Clock Frequency
+set		AT91_PMC_MAINRDY	[expr {1	<< 16}]		;# Main Clock Ready
+
+set	AT91_CKGR_PLLAR		[expr {$AT91_PMC + 0x28}]	;# PLL A Register
+set	AT91_CKGR_PLLBR		[expr {$AT91_PMC + 0x2c}]	;# PLL B Register
+set		AT91_PMC_DIV		[expr {0xff  <<  0}]		;# Divider
+set		AT91_PMC_PLLCOUNT	[expr {0x3f  <<  8}]		;# PLL Counter
+set		AT91_PMC_OUT		[expr {3     << 14}]		;# PLL Clock Frequency Range
+set		AT91_PMC_MUL		[expr {0x7ff << 16}]		;# PLL Multiplier
+set		AT91_PMC_USBDIV		[expr {3     << 28}]		;# USB Divisor (PLLB only)
+set			AT91_PMC_USBDIV_1		[expr {0 << 28}]
+set			AT91_PMC_USBDIV_2		[expr {1 << 28}]
+set			AT91_PMC_USBDIV_4		[expr {2 << 28}]
+set		AT91_PMC_USB96M		[expr {1     << 28}]		;# Divider by 2 Enable (PLLB only)
+set		AT91_PMC_PLLA_WR_ERRATA	[expr {1     << 29}]		;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
+
+set	AT91_PMC_MCKR		[expr {$AT91_PMC + 0x30}]	;# Master Clock Register
+set		AT91_PMC_CSS		[expr {3 <<  0}]		;# Master Clock Selection
+set			AT91_PMC_CSS_SLOW		[expr {0 << 0}]
+set			AT91_PMC_CSS_MAIN		[expr {1 << 0}]
+set			AT91_PMC_CSS_PLLA		[expr {2 << 0}]
+set			AT91_PMC_CSS_PLLB		[expr {3 << 0}]
+set			AT91_PMC_CSS_UPLL		[expr {3 << 0}]	;# [some SAM9 only]
+set		AT91_PMC_PRES		[expr {7 <<  2}]		;# Master Clock Prescaler
+set			AT91_PMC_PRES_1			[expr {0 << 2}]
+set			AT91_PMC_PRES_2			[expr {1 << 2}]
+set			AT91_PMC_PRES_4			[expr {2 << 2}]
+set			AT91_PMC_PRES_8			[expr {3 << 2}]
+set			AT91_PMC_PRES_16		[expr {4 << 2}]
+set			AT91_PMC_PRES_32		[expr {5 << 2}]
+set			AT91_PMC_PRES_64		[expr {6 << 2}]
+set		AT91_PMC_MDIV		[expr {3 <<  8}]		;# Master Clock Division
+set			AT91RM9200_PMC_MDIV_1		[expr {0 << 8}]	;# [AT91RM9200 only]
+set			AT91RM9200_PMC_MDIV_2		[expr {1 << 8}]
+set			AT91RM9200_PMC_MDIV_3		[expr {2 << 8}]
+set			AT91RM9200_PMC_MDIV_4		[expr {3 << 8}]
+set			AT91SAM9_PMC_MDIV_1		[expr {0 << 8}]	;# [SAM9,CAP9 only]
+set			AT91SAM9_PMC_MDIV_2		[expr {1 << 8}]
+set			AT91SAM9_PMC_MDIV_4		[expr {2 << 8}]
+set			AT91SAM9_PMC_MDIV_6		[expr {3 << 8}]	;# [some SAM9 only]
+set			AT91SAM9_PMC_MDIV_3		[expr {3 << 8}]	;# [some SAM9 only]
+set		AT91_PMC_PDIV		[expr {1 << 12}]		;# Processor Clock Division [some SAM9 only]
+set			AT91_PMC_PDIV_1			[expr {0 << 12}]
+set			AT91_PMC_PDIV_2			[expr {1 << 12}]
+set		AT91_PMC_PLLADIV2	[expr {1 << 12}]		;# PLLA divisor by 2 [some SAM9 only]
+set			AT91_PMC_PLLADIV2_OFF		[expr {0 << 12}]
+set			AT91_PMC_PLLADIV2_ON		[expr {1 << 12}]
+
+set	AT91_PMC_USB		[expr {$AT91_PMC + 0x38}]	;# USB Clock Register [some SAM9 only]
+set		AT91_PMC_USBS		[expr {0x1 <<  0}]		;# USB OHCI Input clock selection
+set			AT91_PMC_USBS_PLLA		[expr {0 << 0}]
+set			AT91_PMC_USBS_UPLL		[expr {1 << 0}]
+set		AT91_PMC_OHCIUSBDIV	[expr {0xF <<  8}]		;# Divider for USB OHCI Clock
+
+;# set	AT91_PMC_PCKR(n)	[expr {$AT91_PMC + 0x40 + ((n) * 4)}]	;# Programmable Clock 0-N Registers
+set		AT91_PMC_CSSMCK		[expr {0x1 <<  8}]		;# CSS or Master Clock Selection
+set			AT91_PMC_CSSMCK_CSS		[expr {0 << 8}]
+set			AT91_PMC_CSSMCK_MCK		[expr {1 << 8}]
+
+set	AT91_PMC_IER		[expr {$AT91_PMC + 0x60}]	;# Interrupt Enable Register
+set	AT91_PMC_IDR		[expr {$AT91_PMC + 0x64}]	;# Interrupt Disable Register
+set	AT91_PMC_SR		[expr {$AT91_PMC + 0x68}]	;# Status Register
+set		AT91_PMC_MOSCS		[expr {1 <<  0}]		;# MOSCS Flag
+set		AT91_PMC_LOCKA		[expr {1 <<  1}]		;# PLLA Lock
+set		AT91_PMC_LOCKB		[expr {1 <<  2}]		;# PLLB Lock
+set		AT91_PMC_MCKRDY		[expr {1 <<  3}]		;# Master Clock
+set		AT91_PMC_LOCKU		[expr {1 <<  6}]		;# UPLL Lock [some SAM9, AT91CAP9 only]
+set		AT91_PMC_OSCSEL		[expr {1 <<  7}]		;# Slow Clock Oscillator [AT91CAP9 revC only]
+set		AT91_PMC_PCK0RDY	[expr {1 <<  8}]		;# Programmable Clock 0
+set		AT91_PMC_PCK1RDY	[expr {1 <<  9}]		;# Programmable Clock 1
+set		AT91_PMC_PCK2RDY	[expr {1 << 10}]		;# Programmable Clock 2
+set		AT91_PMC_PCK3RDY	[expr {1 << 11}]		;# Programmable Clock 3
+set	AT91_PMC_IMR		[expr {$AT91_PMC + 0x6c}]	;# Interrupt Mask Register
+
+set AT91_PMC_PROT		[expr {$AT91_PMC + 0xe4}]	;# Protect Register [AT91CAP9 revC only]
+set		AT91_PMC_PROTKEY	0x504d4301	;# Activation Code
+
+set AT91_PMC_VER		[expr {$AT91_PMC + 0xfc}]	;# PMC Module Version [AT91CAP9 only]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_rstc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_rstc.cfg
new file mode 100644
index 0000000..fd17438
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_rstc.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AT91_RSTC_CR		[expr {$AT91_RSTC + 0x00}]	;# Reset Controller Control Register
+set		AT91_RSTC_PROCRST	[expr {1 << 0}]		;# Processor Reset
+set		AT91_RSTC_PERRST	[expr {1 << 2}]		;# Peripheral Reset
+set		AT91_RSTC_EXTRST	[expr {1 << 3}]		;# External Reset
+set		AT91_RSTC_KEY		[expr {0xa5 << 24}]		;# KEY Password
+
+set AT91_RSTC_SR		[expr {$AT91_RSTC + 0x04}]	;# Reset Controller Status Register
+set		AT91_RSTC_URSTS		[expr {1 << 0}]		;# User Reset Status
+set		AT91_RSTC_RSTTYP	[expr {7 << 8}]		;# Reset Type
+set			AT91_RSTC_RSTTYP_GENERAL	[expr {0 << 8}]
+set			AT91_RSTC_RSTTYP_WAKEUP		[expr {1 << 8}]
+set			AT91_RSTC_RSTTYP_WATCHDOG	[expr {2 << 8}]
+set			AT91_RSTC_RSTTYP_SOFTWARE	[expr {3 << 8}]
+set			AT91_RSTC_RSTTYP_USER	[expr {4 << 8}]
+set		AT91_RSTC_NRSTL		[expr {1 << 16}]		;# NRST Pin Level
+set		AT91_RSTC_SRCMP		[expr {1 << 17}]		;# Software Reset Command in Progress
+
+set AT91_RSTC_MR		[expr {$AT91_RSTC + 0x08}]	;# Reset Controller Mode Register
+set		AT91_RSTC_URSTEN	[expr {1 << 0}]		;# User Reset Enable
+set		AT91_RSTC_URSTIEN	[expr {1 << 4}]		;# User Reset Interrupt Enable
+set		AT91_RSTC_ERSTL		[expr {0xf << 8}]		;# External Reset Length
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_wdt.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_wdt.cfg
new file mode 100644
index 0000000..8bba62e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91_wdt.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AT91_WDT_CR		[expr {$AT91_WDT + 0x00}]	;# Watchdog Control Register
+set		AT91_WDT_WDRSTT		[expr {1    << 0}]	;# Restart
+set		AT91_WDT_KEY		[expr {0xa5 << 24}]	;# KEY Password
+
+set AT91_WDT_MR		[expr {$AT91_WDT + 0x04}]	;# Watchdog Mode Register
+set		AT91_WDT_WDV		[expr {0xfff << 0}]	;# Counter Value
+set		AT91_WDT_WDFIEN		[expr {1     << 12}]	;# Fault Interrupt Enable
+set		AT91_WDT_WDRSTEN	[expr {1     << 13}]	;# Reset Processor
+set		AT91_WDT_WDRPROC	[expr {1     << 14}]	;# Timer Restart
+set		AT91_WDT_WDDIS		[expr {1     << 15}]	;# Watchdog Disable
+set		AT91_WDT_WDD		[expr {0xfff << 16}]	;# Delta Value
+set		AT91_WDT_WDDBGHLT	[expr {1     << 28}]	;# Debug Halt
+set		AT91_WDT_WDIDLEHLT	[expr {1     << 29}]	;# Idle Halt
+
+set AT91_WDT_SR		[expr {$AT91_WDT + 0x08}]	;# Watchdog Status Register
+set		AT91_WDT_WDUNF		[expr {1 << 0}]		;# Watchdog Underflow
+set		AT91_WDT_WDERR		[expr {1 << 1}]		;# Watchdog Error
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam7x128.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam7x128.tcl
new file mode 100644
index 0000000..8f46827
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam7x128.tcl
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find bitsbytes.tcl]
+source [find cpu/arm/arm7tdmi.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+set CHIP_MAKER  atmel
+set CHIP_FAMILY at91sam7
+set CHIP_NAME   at91sam7x128
+# how many flash regions.
+set N_FLASH                1
+set FLASH(0,CHIPSELECT)    -1
+set FLASH(0,BASE)          0x00100000
+set FLASH(0,LEN)           $__128K
+set FLASH(0,HUMAN)         "internal flash"
+set FLASH(0,TYPE)          "flash"
+set FLASH(0,RWX)           $RWX_R_X
+set FLASH(0,ACCESS_WIDTH)  $ACCESS_WIDTH_ANY
+# how many ram regions.
+set N_RAM                  1
+set RAM(0,CHIPSELECT)      -1
+set RAM(0,BASE)            0x00200000
+set RAM(0,LEN)             $__32K
+set RAM(0,HUMAN)           "internal ram"
+set RAM(0,TYPE)            "ram"
+set RAM(0,RWX)             $RWX_RWX
+set RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# I AM LAZY... I create 1 region for all MMRs.
+set N_MMREGS    1
+set MMREGS(0,CHIPSELECT)      -1
+set MMREGS(0,BASE)            0xfff00000
+set MMREGS(0,LEN)             0x000fffff
+set MMREGS(0,HUMAN)           "mm-regs"
+set MMREGS(0,TYPE)            "mmr"
+set MMREGS(0,RWX)             $RWX_RW
+set MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# no external memory
+set N_XMEM 0
+
+
+
+
+set AT91C_BASE_SYS       0xFFFFF000
+set AT91C_BASE_AIC       0xFFFFF000
+set AT91C_BASE_PDC_DBGU  0xFFFFF300
+set AT91C_BASE_DBGU      0xFFFFF200
+set AT91C_BASE_PIOA      0xFFFFF400
+set AT91C_BASE_PIOB      0xFFFFF600
+set AT91C_BASE_CKGR      0xFFFFFC20
+set AT91C_BASE_PMC       0xFFFFFC00
+set AT91C_BASE_RSTC      0xFFFFFD00
+set AT91C_BASE_RTTC      0xFFFFFD20
+set AT91C_BASE_PITC      0xFFFFFD30
+set AT91C_BASE_WDTC      0xFFFFFD40
+set AT91C_BASE_VREG      0xFFFFFD60
+set AT91C_BASE_MC        0xFFFFFF00
+set AT91C_BASE_PDC_SPI1  0xFFFE4100
+set AT91C_BASE_SPI1      0xFFFE4000
+set AT91C_BASE_PDC_SPI0  0xFFFE0100
+set AT91C_BASE_SPI0      0xFFFE0000
+set AT91C_BASE_PDC_US1   0xFFFC4100
+set AT91C_BASE_US1       0xFFFC4000
+set AT91C_BASE_PDC_US0   0xFFFC0100
+set AT91C_BASE_US0       0xFFFC0000
+set AT91C_BASE_PDC_SSC   0xFFFD4100
+set AT91C_BASE_SSC       0xFFFD4000
+set AT91C_BASE_TWI       0xFFFB8000
+set AT91C_BASE_PWMC_CH3  0xFFFCC260
+set AT91C_BASE_PWMC_CH2  0xFFFCC240
+set AT91C_BASE_PWMC_CH1  0xFFFCC220
+set AT91C_BASE_PWMC_CH0  0xFFFCC200
+set AT91C_BASE_PWMC      0xFFFCC000
+set AT91C_BASE_UDP       0xFFFB0000
+set AT91C_BASE_TC0       0xFFFA0000
+set AT91C_BASE_TC1       0xFFFA0040
+set AT91C_BASE_TC2       0xFFFA0080
+set AT91C_BASE_TCB       0xFFFA0000
+set AT91C_BASE_CAN_MB0   0xFFFD0200
+set AT91C_BASE_CAN_MB1   0xFFFD0220
+set AT91C_BASE_CAN_MB2   0xFFFD0240
+set AT91C_BASE_CAN_MB3   0xFFFD0260
+set AT91C_BASE_CAN_MB4   0xFFFD0280
+set AT91C_BASE_CAN_MB5   0xFFFD02A0
+set AT91C_BASE_CAN_MB6   0xFFFD02C0
+set AT91C_BASE_CAN_MB7   0xFFFD02E0
+set AT91C_BASE_CAN       0xFFFD0000
+set AT91C_BASE_EMAC      0xFFFDC000
+set AT91C_BASE_PDC_ADC   0xFFFD8100
+set AT91C_BASE_ADC       0xFFFD8000
+
+set AT91C_ID(0) FIQ
+set AT91C_ID(1) SYS
+set AT91C_ID(2) PIOA
+set AT91C_ID(3) PIOB
+set AT91C_ID(4) SPI0
+set AT91C_ID(5) SPI1
+set AT91C_ID(6) US0
+set AT91C_ID(7) US1
+set AT91C_ID(8) SSC
+set AT91C_ID(9) TWI
+set AT91C_ID(10) PWMC
+set AT91C_ID(11) UDP
+set AT91C_ID(12) TC0
+set AT91C_ID(13) TC1
+set AT91C_ID(14) TC2
+set AT91C_ID(15) CAN
+set AT91C_ID(16) EMAC
+set AT91C_ID(17) ADC
+set AT91C_ID(18) ""
+set AT91C_ID(19) ""
+set AT91C_ID(20) ""
+set AT91C_ID(21) ""
+set AT91C_ID(22) ""
+set AT91C_ID(23) ""
+set AT91C_ID(24) ""
+set AT91C_ID(25) ""
+set AT91C_ID(26) ""
+set AT91C_ID(27) ""
+set AT91C_ID(28) ""
+set AT91C_ID(29) ""
+set AT91C_ID(30) IRQ0
+set AT91C_ID(31) IRQ1
+
+source [find chip/atmel/at91/aic.tcl]
+source [find chip/atmel/at91/usarts.tcl]
+source [find chip/atmel/at91/pmc.tcl]
+source [find chip/atmel/at91/rtt.tcl]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam7x256.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam7x256.tcl
new file mode 100644
index 0000000..49d5244
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam7x256.tcl
@@ -0,0 +1,128 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find bitsbytes.tcl]
+source [find cpu/arm/arm7tdmi.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+set CHIP_MAKER  atmel
+set CHIP_FAMILY at91sam7
+set CHIP_NAME   at91sam7x256
+# how many flash regions.
+set N_FLASH                1
+set FLASH(0,CHIPSELECT)    -1
+set FLASH(0,BASE)          0x00100000
+set FLASH(0,LEN)           $__256K
+set FLASH(0,HUMAN)         "internal flash"
+set FLASH(0,TYPE)          "flash"
+set FLASH(0,RWX)           $RWX_R_X
+set FLASH(0,ACCESS_WIDTH)  $ACCESS_WIDTH_ANY
+# how many ram regions.
+set N_RAM                  1
+set RAM(0,CHIPSELECT)      -1
+set RAM(0,BASE)            0x00200000
+set RAM(0,LEN)             $__64K
+set RAM(0,HUMAN)           "internal ram"
+set RAM(0,TYPE)            "ram"
+set RAM(0,RWX)             $RWX_RWX
+set RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# I AM LAZY... I create 1 region for all MMRs.
+set N_MMREGS    1
+set MMREGS(0,CHIPSELECT)      -1
+set MMREGS(0,BASE)            0xfff00000
+set MMREGS(0,LEN)             0x000fffff
+set MMREGS(0,HUMAN)           "mm-regs"
+set MMREGS(0,TYPE)            "mmr"
+set MMREGS(0,RWX)             $RWX_RW
+set MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# no external memory
+set N_XMEM 0
+
+set  AT91C_BASE_SYS              0xFFFFF000
+set  AT91C_BASE_AIC              0xFFFFF000
+set  AT91C_BASE_PDC_DBGU         0xFFFFF300
+set  AT91C_BASE_DBGU             0xFFFFF200
+set  AT91C_BASE_PIOA             0xFFFFF400
+set  AT91C_BASE_PIOB             0xFFFFF600
+set  AT91C_BASE_CKGR             0xFFFFFC20
+set  AT91C_BASE_PMC              0xFFFFFC00
+set  AT91C_BASE_RSTC             0xFFFFFD00
+set  AT91C_BASE_RTTC             0xFFFFFD20
+set  AT91C_BASE_PITC             0xFFFFFD30
+set  AT91C_BASE_WDTC             0xFFFFFD40
+set  AT91C_BASE_VREG             0xFFFFFD60
+set  AT91C_BASE_MC          0xFFFFFF00
+set  AT91C_BASE_PDC_SPI1      0xFFFE4100
+set  AT91C_BASE_SPI1          0xFFFE4000
+set  AT91C_BASE_PDC_SPI0      0xFFFE0100
+set  AT91C_BASE_SPI0          0xFFFE0000
+set  AT91C_BASE_PDC_US1       0xFFFC4100
+set  AT91C_BASE_US1           0xFFFC4000
+set  AT91C_BASE_PDC_US0       0xFFFC0100
+set  AT91C_BASE_US0           0xFFFC0000
+set  AT91C_BASE_PDC_SSC       0xFFFD4100
+set  AT91C_BASE_SSC           0xFFFD4000
+set  AT91C_BASE_TWI           0xFFFB8000
+set  AT91C_BASE_PWMC_CH3      0xFFFCC260
+set  AT91C_BASE_PWMC_CH2      0xFFFCC240
+set  AT91C_BASE_PWMC_CH1      0xFFFCC220
+set  AT91C_BASE_PWMC_CH0      0xFFFCC200
+set  AT91C_BASE_PWMC          0xFFFCC000
+set  AT91C_BASE_UDP           0xFFFB0000
+set  AT91C_BASE_TC0         0xFFFA0000
+set  AT91C_BASE_TC1         0xFFFA0040
+set  AT91C_BASE_TC2         0xFFFA0080
+set  AT91C_BASE_TCB             0xFFFA0000
+set  AT91C_BASE_CAN_MB0         0xFFFD0200
+set  AT91C_BASE_CAN_MB1         0xFFFD0220
+set  AT91C_BASE_CAN_MB2         0xFFFD0240
+set  AT91C_BASE_CAN_MB3         0xFFFD0260
+set  AT91C_BASE_CAN_MB4         0xFFFD0280
+set  AT91C_BASE_CAN_MB5         0xFFFD02A0
+set  AT91C_BASE_CAN_MB6         0xFFFD02C0
+set  AT91C_BASE_CAN_MB7         0xFFFD02E0
+set  AT91C_BASE_CAN             0xFFFD0000
+set  AT91C_BASE_EMAC            0xFFFDC000
+set  AT91C_BASE_PDC_ADC         0xFFFD8100
+set  AT91C_BASE_ADC             0xFFFD8000
+
+set AT91C_ID(0)   "FIQ"
+set AT91C_ID(1)   "SYS"
+set AT91C_ID(2)   "PIOA"
+set AT91C_ID(3)   "PIOB"
+set AT91C_ID(4)   "SPI0"
+set AT91C_ID(5)   "SPI1"
+set AT91C_ID(6)   "US0"
+set AT91C_ID(7)   "US1"
+set AT91C_ID(8)   "SSC"
+set AT91C_ID(9)   "TWI"
+set AT91C_ID(10)   "PWMC"
+set AT91C_ID(11)   "UDP"
+set AT91C_ID(12)   "TC0"
+set AT91C_ID(13)   "TC1"
+set AT91C_ID(14)   "TC2"
+set AT91C_ID(15)   "CAN"
+set AT91C_ID(16)   "EMAC"
+set AT91C_ID(17)   "ADC"
+set AT91C_ID(18)   ""
+set AT91C_ID(19)   ""
+set AT91C_ID(20)   ""
+set AT91C_ID(21)   ""
+set AT91C_ID(22)   ""
+set AT91C_ID(23)   ""
+set AT91C_ID(24)   ""
+set AT91C_ID(25)   ""
+set AT91C_ID(26)   ""
+set AT91C_ID(27)   ""
+set AT91C_ID(28)   ""
+set AT91C_ID(29)   ""
+set AT91C_ID(30)   "IRQ0"
+set AT91C_ID(31)   "IRQ1"
+
+
+source [find chip/atmel/at91/aic.tcl]
+source [find chip/atmel/at91/usarts.tcl]
+source [find chip/atmel/at91/pmc.tcl]
+source [find chip/atmel/at91/rtt.tcl]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9261.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9261.cfg
new file mode 100644
index 0000000..51e7101
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9261.cfg
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Peripheral identifiers/interrupts.
+#
+set AT91_ID_FIQ		0	;# Advanced Interrupt Controller (FIQ)
+set AT91_ID_SYS		1	;# System Peripherals
+set AT91SAM9261_ID_PIOA	2	;# Parallel IO Controller A
+set AT91SAM9261_ID_PIOB	3	;# Parallel IO Controller B
+set AT91SAM9261_ID_PIOC	4	;# Parallel IO Controller C
+set AT91SAM9261_ID_US0	6	;# USART 0
+set AT91SAM9261_ID_US1	7	;# USART 1
+set AT91SAM9261_ID_US2	8	;# USART 2
+set AT91SAM9261_ID_MCI	9	;# Multimedia Card Interface
+set AT91SAM9261_ID_UDP	10	;# USB Device Port
+set AT91SAM9261_ID_TWI	11	;# Two-Wire Interface
+set AT91SAM9261_ID_SPI0	12	;# Serial Peripheral Interface 0
+set AT91SAM9261_ID_SPI1	13	;# Serial Peripheral Interface 1
+set AT91SAM9261_ID_SSC0	14	;# Serial Synchronous Controller 0
+set AT91SAM9261_ID_SSC1	15	;# Serial Synchronous Controller 1
+set AT91SAM9261_ID_SSC2	16	;# Serial Synchronous Controller 2
+set AT91SAM9261_ID_TC0	17	;# Timer Counter 0
+set AT91SAM9261_ID_TC1	18	;# Timer Counter 1
+set AT91SAM9261_ID_TC2	19	;# Timer Counter 2
+set AT91SAM9261_ID_UHP	20	;# USB Host port
+set AT91SAM9261_ID_LCDC	21	;# LDC Controller
+set AT91SAM9261_ID_IRQ0	29	;# Advanced Interrupt Controller (IRQ0)
+set AT91SAM9261_ID_IRQ1	30	;# Advanced Interrupt Controller (IRQ1)
+set AT91SAM9261_ID_IRQ2	31	;# Advanced Interrupt Controller (IRQ2)
+
+
+#
+# User Peripheral physical base addresses.
+#
+set AT91SAM9261_BASE_TCB0		0xfffa0000
+set AT91SAM9261_BASE_TC0		0xfffa0000
+set AT91SAM9261_BASE_TC1		0xfffa0040
+set AT91SAM9261_BASE_TC2		0xfffa0080
+set AT91SAM9261_BASE_UDP		0xfffa4000
+set AT91SAM9261_BASE_MCI		0xfffa8000
+set AT91SAM9261_BASE_TWI		0xfffac000
+set AT91SAM9261_BASE_US0		0xfffb0000
+set AT91SAM9261_BASE_US1		0xfffb4000
+set AT91SAM9261_BASE_US2		0xfffb8000
+set AT91SAM9261_BASE_SSC0		0xfffbc000
+set AT91SAM9261_BASE_SSC1		0xfffc0000
+set AT91SAM9261_BASE_SSC2		0xfffc4000
+set AT91SAM9261_BASE_SPI0		0xfffc8000
+set AT91SAM9261_BASE_SPI1		0xfffcc000
+set AT91_BASE_SYS			0xffffea00
+
+
+#
+# System Peripherals (offset from AT91_BASE_SYS)
+#
+set AT91_SDRAMC	0xffffea00
+set AT91_SMC	0xffffec00
+set AT91_MATRIX	0xffffee00
+set AT91_AIC	0xfffff000
+set AT91_DBGU	0xfffff200
+set AT91_PIOA	0xfffff400
+set AT91_PIOB	0xfffff600
+set AT91_PIOC	0xfffff800
+set AT91_PMC	0xfffffc00
+set AT91_RSTC	0xfffffd00
+set AT91_SHDWC	0xfffffd10
+set AT91_RTT	0xfffffd20
+set AT91_PIT	0xfffffd30
+set AT91_WDT	0xfffffd40
+set AT91_GPBR	0xfffffd50
+
+set AT91_USART0	$AT91SAM9261_BASE_US0
+set AT91_USART1	$AT91SAM9261_BASE_US1
+set AT91_USART2	$AT91SAM9261_BASE_US2
+
+
+#
+# Internal Memory.
+#
+set AT91SAM9261_SRAM_BASE	0x00300000	;# Internal SRAM base address
+set AT91SAM9261_SRAM_SIZE	0x00028000	;# Internal SRAM size (160Kb)
+
+set AT91SAM9261_ROM_BASE	0x00400000	;# Internal ROM base address
+set AT91SAM9261_ROM_SIZE	0x00008000	;# Internal ROM size (32Kb)
+
+set AT91SAM9261_UHP_BASE	0x00500000	;# USB Host controller
+set AT91SAM9261_LCDC_BASE	0x00600000	;# LDC controller
+
+#
+# Cpu Name
+#
+set AT91_CPU_NAME	"AT91SAM9261"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9261_matrix.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9261_matrix.cfg
new file mode 100644
index 0000000..c3656bd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9261_matrix.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AT91_MATRIX_MCFG	[expr {$AT91_MATRIX + 0x00}]	;# Master Configuration Register #
+set		AT91_MATRIX_RCB0	[expr {1 << 0}]		;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
+set		AT91_MATRIX_RCB1	[expr {1 << 1}]		;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
+
+set AT91_MATRIX_SCFG0	[expr {$AT91_MATRIX + 0x04}]	;# Slave Configuration Register 0
+set AT91_MATRIX_SCFG1	[expr {$AT91_MATRIX + 0x08}]	;# Slave Configuration Register 1
+set AT91_MATRIX_SCFG2	[expr {$AT91_MATRIX + 0x0C}]	;# Slave Configuration Register 2
+set AT91_MATRIX_SCFG3	[expr {$AT91_MATRIX + 0x10}]	;# Slave Configuration Register 3
+set AT91_MATRIX_SCFG4	[expr {$AT91_MATRIX + 0x14}]	;# Slave Configuration Register 4
+set		AT91_MATRIX_SLOT_CYCLE		[expr {0xff << 0}]	;# Maximum Number of Allowed Cycles for a Burst
+set		AT91_MATRIX_DEFMSTR_TYPE	[expr {3    << 16}]	;# Default Master Type
+set			AT91_MATRIX_DEFMSTR_TYPE_NONE	[expr {0 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_LAST	[expr {1 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_FIXED	[expr {2 << 16}]
+set		AT91_MATRIX_FIXED_DEFMSTR	[expr {7    << 18}]	;# Fixed Index of Default Master
+
+set AT91_MATRIX_TCR		[expr {$AT91_MATRIX + 0x24}]	;# TCM Configuration Register
+set		AT91_MATRIX_ITCM_SIZE		[expr {0xf << 0}]	;# Size of ITCM enabled memory block
+set			AT91_MATRIX_ITCM_0		[expr {0 << 0}]
+set			AT91_MATRIX_ITCM_16		[expr {5 << 0}]
+set			AT91_MATRIX_ITCM_32		[expr {6 << 0}]
+set			AT91_MATRIX_ITCM_64		[expr {7 << 0}]
+set		AT91_MATRIX_DTCM_SIZE		[expr {0xf << 4}]	;# Size of DTCM enabled memory block
+set			AT91_MATRIX_DTCM_0		[expr {0 << 4}]
+set			AT91_MATRIX_DTCM_16		[expr {5 << 4}]
+set			AT91_MATRIX_DTCM_32		[expr {6 << 4}]
+set			AT91_MATRIX_DTCM_64		[expr {7 << 4}]
+
+set AT91_MATRIX_EBICSA	[expr {$AT91_MATRIX + 0x30}]	;# EBI Chip Select Assignment Register
+set		AT91_MATRIX_CS1A		[expr {1 << 1}]	;# Chip Select 1 Assignment
+set			AT91_MATRIX_CS1A_SMC		[expr {0 << 1}]
+set			AT91_MATRIX_CS1A_SDRAMC		[expr {1 << 1}]
+set		AT91_MATRIX_CS3A		[expr {1 << 3}]	;# Chip Select 3 Assignment
+set			AT91_MATRIX_CS3A_SMC		[expr {0 << 3}]
+set			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	[expr {1 << 3}]
+set		AT91_MATRIX_CS4A		[expr {1 << 4}]	;# Chip Select 4 Assignment
+set			AT91_MATRIX_CS4A_SMC		[expr {0 << 4}]
+set			AT91_MATRIX_CS4A_SMC_CF1	[expr {1 << 4}]
+set		AT91_MATRIX_CS5A		[expr {1 << 5}]	;# Chip Select 5 Assignment
+set			AT91_MATRIX_CS5A_SMC		[expr {0 << 5}]
+set			AT91_MATRIX_CS5A_SMC_CF2	[expr {1 << 5}]
+set		AT91_MATRIX_DBPUC		[expr {1 << 8}]	;# Data Bus Pull-up Configuration
+
+set AT91_MATRIX_USBPUCR	[expr {$AT91_MATRIX + 0x34}]	;# USB Pad Pull-Up Control Register
+set		AT91_MATRIX_USBPUCR_PUON	[expr {1 << 30}]	;# USB Device PAD Pull-up Enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9263.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9263.cfg
new file mode 100644
index 0000000..600c548
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9263.cfg
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Peripheral identifiers/interrupts.
+#
+set AT91_ID_FIQ		0	;# Advanced Interrupt Controller (FIQ)
+set AT91_ID_SYS		1	;# System Peripherals
+set AT91SAM9263_ID_PIOA	2	;# Parallel IO Controller A
+set AT91SAM9263_ID_PIOB	3	;# Parallel IO Controller B
+set AT91SAM9263_ID_PIOCDE	4	;# Parallel IO Controller C, D and E
+set AT91SAM9263_ID_US0	7	;# USART 0
+set AT91SAM9263_ID_US1	8	;# USART 1
+set AT91SAM9263_ID_US2	9	;# USART 2
+set AT91SAM9263_ID_MCI0	10	;# Multimedia Card Interface 0
+set AT91SAM9263_ID_MCI1	11	;# Multimedia Card Interface 1
+set AT91SAM9263_ID_CAN	12	;# CAN
+set AT91SAM9263_ID_TWI	13	;# Two-Wire Interface
+set AT91SAM9263_ID_SPI0	14	;# Serial Peripheral Interface 0
+set AT91SAM9263_ID_SPI1	15	;# Serial Peripheral Interface 1
+set AT91SAM9263_ID_SSC0	16	;# Serial Synchronous Controller 0
+set AT91SAM9263_ID_SSC1	17	;# Serial Synchronous Controller 1
+set AT91SAM9263_ID_AC97C	18	;# AC97 Controller
+set AT91SAM9263_ID_TCB	19	;# Timer Counter 0, 1 and 2
+set AT91SAM9263_ID_PWMC	20	;# Pulse Width Modulation Controller
+set AT91SAM9263_ID_EMAC	21	;# Ethernet
+set AT91SAM9263_ID_2DGE	23	;# 2D Graphic Engine
+set AT91SAM9263_ID_UDP	24	;# USB Device Port
+set AT91SAM9263_ID_ISI	25	;# Image Sensor Interface
+set AT91SAM9263_ID_LCDC	26	;# LCD Controller
+set AT91SAM9263_ID_DMA	27	;# DMA Controller
+set AT91SAM9263_ID_UHP	29	;# USB Host port
+set AT91SAM9263_ID_IRQ0	30	;# Advanced Interrupt Controller (IRQ0)
+set AT91SAM9263_ID_IRQ1	31	;# Advanced Interrupt Controller (IRQ1)
+
+
+#
+# User Peripheral physical base addresses.
+#
+set AT91SAM9263_BASE_UDP		0xfff78000
+set AT91SAM9263_BASE_TCB0		0xfff7c000
+set AT91SAM9263_BASE_TC0		0xfff7c000
+set AT91SAM9263_BASE_TC1		0xfff7c040
+set AT91SAM9263_BASE_TC2		0xfff7c080
+set AT91SAM9263_BASE_MCI0		0xfff80000
+set AT91SAM9263_BASE_MCI1		0xfff84000
+set AT91SAM9263_BASE_TWI		0xfff88000
+set AT91SAM9263_BASE_US0		0xfff8c000
+set AT91SAM9263_BASE_US1		0xfff90000
+set AT91SAM9263_BASE_US2		0xfff94000
+set AT91SAM9263_BASE_SSC0		0xfff98000
+set AT91SAM9263_BASE_SSC1		0xfff9c000
+set AT91SAM9263_BASE_AC97C		0xfffa0000
+set AT91SAM9263_BASE_SPI0		0xfffa4000
+set AT91SAM9263_BASE_SPI1		0xfffa8000
+set AT91SAM9263_BASE_CAN		0xfffac000
+set AT91SAM9263_BASE_PWMC		0xfffb8000
+set AT91SAM9263_BASE_EMAC		0xfffbc000
+set AT91SAM9263_BASE_ISI		0xfffc4000
+set AT91SAM9263_BASE_2DGE		0xfffc8000
+set AT91_BASE_SYS			0xffffe000
+
+#
+# System Peripherals (offset from AT91_BASE_SYS)
+#
+set AT91_ECC0		0xffffe000
+set AT91_SDRAMC0	0xffffe200
+set AT91_SMC0		0xffffe400
+set AT91_ECC1		0xffffe600
+set AT91_SDRAMC1	0xffffe800
+set AT91_SMC1		0xffffea00
+set AT91_MATRIX		0xffffec00
+set AT91_CCFG		0xffffed10
+set AT91_DBGU		0xffffee00
+set AT91_AIC		0xfffff000
+set AT91_PIOA		0xfffff200
+set AT91_PIOB		0xfffff400
+set AT91_PIOC		0xfffff600
+set AT91_PIOD		0xfffff800
+set AT91_PIOE		0xfffffa00
+set AT91_PMC		0xfffffc00
+set AT91_RSTC		0xfffffd00
+set AT91_SHDWC		0xfffffd10
+set AT91_RTT0		0xfffffd20
+set AT91_PIT		0xfffffd30
+set AT91_WDT		0xfffffd40
+set AT91_RTT1		0xfffffd50
+set AT91_GPBR		0xfffffd60
+
+set AT91_USART0	$AT91SAM9263_BASE_US0
+set AT91_USART1	$AT91SAM9263_BASE_US1
+set AT91_USART2	$AT91SAM9263_BASE_US2
+
+set AT91_SMC	$AT91_SMC0
+set AT91_SDRAMC	$AT91_SDRAMC0
+
+#
+# Internal Memory.
+#
+set AT91SAM9263_SRAM0_BASE	0x00300000	;# Internal SRAM 0 base address
+set AT91SAM9263_SRAM0_SIZE	0x00014000	;# Internal SRAM 0 size (80Kb)
+
+set AT91SAM9263_ROM_BASE	0x00400000	;# Internal ROM base address
+set AT91SAM9263_ROM_SIZE	0x00020000	;# Internal ROM size (128Kb)
+
+set AT91SAM9263_SRAM1_BASE	0x00500000	;# Internal SRAM 1 base address
+set AT91SAM9263_SRAM1_SIZE	0x00004000	;# Internal SRAM 1 size (16Kb)
+
+set AT91SAM9263_LCDC_BASE	0x00700000	;# LCD Controller
+set AT91SAM9263_DMAC_BASE	0x00800000	;# DMA Controller
+set AT91SAM9263_UHP_BASE	0x00a00000	;# USB Host controller
+
+#
+# Cpu Name
+#
+set AT91_CPU_NAME	"AT91SAM9263"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9263_matrix.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9263_matrix.cfg
new file mode 100644
index 0000000..20a3107
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9263_matrix.cfg
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AT91_MATRIX_MCFG0	[expr {$AT91_MATRIX + 0x00}]	;# Master Configuration Register 0
+set AT91_MATRIX_MCFG1	[expr {$AT91_MATRIX + 0x04}]	;# Master Configuration Register 1
+set AT91_MATRIX_MCFG2	[expr {$AT91_MATRIX + 0x08}]	;# Master Configuration Register 2
+set AT91_MATRIX_MCFG3	[expr {$AT91_MATRIX + 0x0C}]	;# Master Configuration Register 3
+set AT91_MATRIX_MCFG4	[expr {$AT91_MATRIX + 0x10}]	;# Master Configuration Register 4
+set AT91_MATRIX_MCFG5	[expr {$AT91_MATRIX + 0x14}]	;# Master Configuration Register 5
+set AT91_MATRIX_MCFG6	[expr {$AT91_MATRIX + 0x18}]	;# Master Configuration Register 6
+set AT91_MATRIX_MCFG7	[expr {$AT91_MATRIX + 0x1C}]	;# Master Configuration Register 7
+set AT91_MATRIX_MCFG8	[expr {$AT91_MATRIX + 0x20}]	;# Master Configuration Register 8
+set		AT91_MATRIX_ULBT	[expr {7 << 0}]	;# Undefined Length Burst Type
+set			AT91_MATRIX_ULBT_INFINITE	[expr {0 << 0}]
+set			AT91_MATRIX_ULBT_SINGLE		[expr {1 << 0}]
+set			AT91_MATRIX_ULBT_FOUR		[expr {2 << 0}]
+set			AT91_MATRIX_ULBT_EIGHT		[expr {3 << 0}]
+set			AT91_MATRIX_ULBT_SIXTEEN	[expr {4 << 0}]
+
+set AT91_MATRIX_SCFG0	[expr {$AT91_MATRIX + 0x40}]	;# Slave Configuration Register 0
+set AT91_MATRIX_SCFG1	[expr {$AT91_MATRIX + 0x44}]	;# Slave Configuration Register 1
+set AT91_MATRIX_SCFG2	[expr {$AT91_MATRIX + 0x48}]	;# Slave Configuration Register 2
+set AT91_MATRIX_SCFG3	[expr {$AT91_MATRIX + 0x4C}]	;# Slave Configuration Register 3
+set AT91_MATRIX_SCFG4	[expr {$AT91_MATRIX + 0x50}]	;# Slave Configuration Register 4
+set AT91_MATRIX_SCFG5	[expr {$AT91_MATRIX + 0x54}]	;# Slave Configuration Register 5
+set AT91_MATRIX_SCFG6	[expr {$AT91_MATRIX + 0x58}]	;# Slave Configuration Register 6
+set AT91_MATRIX_SCFG7	[expr {$AT91_MATRIX + 0x5C}]	;# Slave Configuration Register 7
+set		AT91_MATRIX_SLOT_CYCLE		[expr {0xff << 0}]	;# Maximum Number of Allowed Cycles for a Burst
+set		AT91_MATRIX_DEFMSTR_TYPE	[expr {3    << 16}]	;# Default Master Type
+set			AT91_MATRIX_DEFMSTR_TYPE_NONE	[expr {0 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_LAST	[expr {1 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_FIXED	[expr {2 << 16}]
+set		AT91_MATRIX_FIXED_DEFMSTR	[expr {0xf  << 18}]	;# Fixed Index of Default Master
+set		AT91_MATRIX_ARBT		[expr {3    << 24}]	;# Arbitration Type
+set			AT91_MATRIX_ARBT_ROUND_ROBIN	[expr {0 << 24}]
+set			AT91_MATRIX_ARBT_FIXED_PRIORITY	[expr {1 << 24}]
+
+set AT91_MATRIX_PRAS0	[expr {$AT91_MATRIX + 0x80}]	;# Priority Register A for Slave 0
+set AT91_MATRIX_PRBS0	[expr {$AT91_MATRIX + 0x84}]	;# Priority Register B for Slave 0
+set AT91_MATRIX_PRAS1	[expr {$AT91_MATRIX + 0x88}]	;# Priority Register A for Slave 1
+set AT91_MATRIX_PRBS1	[expr {$AT91_MATRIX + 0x8C}]	;# Priority Register B for Slave 1
+set AT91_MATRIX_PRAS2	[expr {$AT91_MATRIX + 0x90}]	;# Priority Register A for Slave 2
+set AT91_MATRIX_PRBS2	[expr {$AT91_MATRIX + 0x94}]	;# Priority Register B for Slave 2
+set AT91_MATRIX_PRAS3	[expr {$AT91_MATRIX + 0x98}]	;# Priority Register A for Slave 3
+set AT91_MATRIX_PRBS3	[expr {$AT91_MATRIX + 0x9C}]	;# Priority Register B for Slave 3
+set AT91_MATRIX_PRAS4	[expr {$AT91_MATRIX + 0xA0}]	;# Priority Register A for Slave 4
+set AT91_MATRIX_PRBS4	[expr {$AT91_MATRIX + 0xA4}]	;# Priority Register B for Slave 4
+set AT91_MATRIX_PRAS5	[expr {$AT91_MATRIX + 0xA8}]	;# Priority Register A for Slave 5
+set AT91_MATRIX_PRBS5	[expr {$AT91_MATRIX + 0xAC}]	;# Priority Register B for Slave 5
+set AT91_MATRIX_PRAS6	[expr {$AT91_MATRIX + 0xB0}]	;# Priority Register A for Slave 6
+set AT91_MATRIX_PRBS6	[expr {$AT91_MATRIX + 0xB4}]	;# Priority Register B for Slave 6
+set AT91_MATRIX_PRAS7	[expr {$AT91_MATRIX + 0xB8}]	;# Priority Register A for Slave 7
+set AT91_MATRIX_PRBS7	[expr {$AT91_MATRIX + 0xBC}]	;# Priority Register B for Slave 7
+set		AT91_MATRIX_M0PR		[expr {3 << 0}]		;# Master 0 Priority
+set		AT91_MATRIX_M1PR		[expr {3 << 4}]		;# Master 1 Priority
+set		AT91_MATRIX_M2PR		[expr {3 << 8}]		;# Master 2 Priority
+set		AT91_MATRIX_M3PR		[expr {3 << 12}]	;# Master 3 Priority
+set		AT91_MATRIX_M4PR		[expr {3 << 16}]	;# Master 4 Priority
+set		AT91_MATRIX_M5PR		[expr {3 << 20}]	;# Master 5 Priority
+set		AT91_MATRIX_M6PR		[expr {3 << 24}]	;# Master 6 Priority
+set		AT91_MATRIX_M7PR		[expr {3 << 28}]	;# Master 7 Priority
+set		AT91_MATRIX_M8PR		[expr {3 << 0}]		;# Master 8 Priority (in Register B)
+
+set AT91_MATRIX_MRCR	[expr {$AT91_MATRIX + 0x100}]	;# Master Remap Control Register
+set		AT91_MATRIX_RCB0		[expr {1 << 0}]	;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
+set		AT91_MATRIX_RCB1		[expr {1 << 1}]	;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
+set		AT91_MATRIX_RCB2		[expr {1 << 2}]
+set		AT91_MATRIX_RCB3		[expr {1 << 3}]
+set		AT91_MATRIX_RCB4		[expr {1 << 4}]
+set		AT91_MATRIX_RCB5		[expr {1 << 5}]
+set		AT91_MATRIX_RCB6		[expr {1 << 6}]
+set		AT91_MATRIX_RCB7		[expr {1 << 7}]
+set		AT91_MATRIX_RCB8		[expr {1 << 8}]
+
+set AT91_MATRIX_TCMR	[expr {$AT91_MATRIX + 0x114}]	;# TCM Configuration Register
+set		AT91_MATRIX_ITCM_SIZE		[expr {0xf << 0}]	;# Size of ITCM enabled memory block
+set			AT91_MATRIX_ITCM_0		[expr {0 << 0}]
+set			AT91_MATRIX_ITCM_16		[expr {5 << 0}]
+set			AT91_MATRIX_ITCM_32		[expr {6 << 0}]
+set		AT91_MATRIX_DTCM_SIZE		[expr {0xf << 4}]	;# Size of DTCM enabled memory block
+set			AT91_MATRIX_DTCM_0		[expr {0 << 4}]
+set			AT91_MATRIX_DTCM_16		[expr {5 << 4}]
+set			AT91_MATRIX_DTCM_32		[expr {6 << 4}]
+
+set AT91_MATRIX_EBI0CSA	[expr {$AT91_MATRIX + 0x120}]	;# EBI0 Chip Select Assignment Register
+set		AT91_MATRIX_EBI0_CS1A		[expr {1 << 1}]	;# Chip Select 1 Assignment
+set			AT91_MATRIX_EBI0_CS1A_SMC		[expr {0 << 1}]
+set			AT91_MATRIX_EBI0_CS1A_SDRAMC		[expr {1 << 1}]
+set		AT91_MATRIX_EBI0_CS3A		[expr {1 << 3}]	;# Chip Select 3 Assignmen
+set			AT91_MATRIX_EBI0_CS3A_SMC		[expr {0 << 3}]
+set			AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA	[expr {1 << 3}]
+set		AT91_MATRIX_EBI0_CS4A		[expr {1 << 4}]	;# Chip Select 4 Assignment
+set			AT91_MATRIX_EBI0_CS4A_SMC		[expr {0 << 4}]
+set			AT91_MATRIX_EBI0_CS4A_SMC_CF1		[expr {1 << 4}]
+set		AT91_MATRIX_EBI0_CS5A		[expr {1 << 5}]	;# Chip Select 5 Assignment
+set			AT91_MATRIX_EBI0_CS5A_SMC		[expr {0 << 5}]
+set			AT91_MATRIX_EBI0_CS5A_SMC_CF2		[expr {1 << 5}]
+set		AT91_MATRIX_EBI0_DBPUC		[expr {1 << 8}]	;# Data Bus Pull-up Configuration
+set		AT91_MATRIX_EBI0_VDDIOMSEL	[expr {1 << 16}]	;# Memory voltage selection
+set			AT91_MATRIX_EBI0_VDDIOMSEL_1_8V		[expr {0 << 16}]
+set			AT91_MATRIX_EBI0_VDDIOMSEL_3_3V		[expr {1 << 16}]
+
+set AT91_MATRIX_EBI1CSA	[expr {$AT91_MATRIX + 0x124}]	;# EBI1 Chip Select Assignment Register
+set		AT91_MATRIX_EBI1_CS1A		[expr {1 << 1}]	;# Chip Select 1 Assignment
+set			AT91_MATRIX_EBI1_CS1A_SMC		[expr {0 << 1}]
+set			AT91_MATRIX_EBI1_CS1A_SDRAMC		[expr {1 << 1}]
+set		AT91_MATRIX_EBI1_CS2A		[expr {1 << 3}]	;# Chip Select 3 Assignment
+set			AT91_MATRIX_EBI1_CS2A_SMC		[expr {0 << 3}]
+set			AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA	[expr {1 << 3}]
+set		AT91_MATRIX_EBI1_DBPUC		[expr {1 << 8}]	;# Data Bus Pull-up Configuration
+set		AT91_MATRIX_EBI1_VDDIOMSEL	[expr {1 << 16}]	;# Memory voltage selection
+set			AT91_MATRIX_EBI1_VDDIOMSEL_1_8V		[expr {0 << 16}]
+set			AT91_MATRIX_EBI1_VDDIOMSEL_3_3V		[expr {1 << 16}]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9_init.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9_init.cfg
new file mode 100644
index 0000000..a64d6ea
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9_init.cfg
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]]
+
+proc at91sam9_reset_start { } {
+
+	arm7_9 fast_memory_access disable
+
+	jtag_rclk 8
+	halt
+	wait_halt 10000
+	set rstc_mr_val $::AT91_RSTC_KEY
+	set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
+	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
+	mww $::AT91_RSTC_MR $rstc_mr_val	;# RSTC_MR : enable user reset.
+}
+
+proc at91sam9_reset_init { config } {
+
+	mww $::AT91_WDT_MR $config(wdt_mr_val)	;# disable watchdog
+
+	set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
+
+	mww $::AT91_CKGR_MOR $ckgr_mor	;# CKGR_MOR - enable main osc.
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 }
+
+	set pllar_val	$::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog
+	set pllar_val	[expr {$pllar_val | $::AT91_PMC_OUT}]
+	set pllar_val	[expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
+	set pllar_val	[expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}]
+	set pllar_val	[expr {$pllar_val | $config(master_pll_div)}]
+
+	mww $::AT91_CKGR_PLLAR $pllar_val	 ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 }
+
+	;# PCK/2 = MCK Master Clock from PLLA
+	set mckr_val	$::AT91_PMC_CSS_PLLA
+	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PRES_1}]
+	set mckr_val	[expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
+	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PDIV_1}]
+
+	mww $::AT91_PMC_MCKR $mckr_val	;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 }
+
+	## switch JTAG clock to highspeed clock
+	jtag_rclk 0
+
+	arm7_9 dcc_downloads enable	;# Enable faster DCC downloads
+	arm7_9 fast_memory_access enable
+
+	set rstc_mr_val $::AT91_RSTC_KEY
+	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
+	mww $::AT91_RSTC_MR $rstc_mr_val	;# user reset enable
+
+	if { [info exists config(sdram_piod)] } {
+		set pdr_addr	[expr {$::AT91_PIOD + $::PIO_PDR}]
+		set pudr_addr	[expr {$::AT91_PIOD + $::PIO_PUDR}]
+		set asr_addr	[expr {$::AT91_PIOD + $::PIO_ASR}]
+		mww $pdr_addr 0xffff0000				;# define PDC[31:16] as DATA[31:16]
+		mww $pudr_addr 0xffff0000				;# no pull-up for D[31:16]
+		mww $asr_addr 0xffff0000
+	} else {
+		set pdr_addr	[expr {$::AT91_PIOC + $::PIO_PDR}]
+		set pudr_addr	[expr {$::AT91_PIOC + $::PIO_PUDR}]
+		mww $pdr_addr 0xffff0000				;# define PDC[31:16] as DATA[31:16]
+		mww $pudr_addr 0xffff0000				;# no pull-up for D[31:16]
+	}
+
+	mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_NORMAL	;# SDRAMC_MR Mode register
+	mww $::AT91_SDRAMC_TR	$config(sdram_tr_val)		;# SDRAMC_TR - Refresh Timer register
+	mww $::AT91_SDRAMC_CR	$config(sdram_cr_val)		;# SDRAMC_CR - Configuration register
+	mww $::AT91_SDRAMC_MDR	$::AT91_SDRAMC_MD_SDRAM		;# Memory Device Register -> SDRAM
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_PRECHARGE	;# SDRAMC_MR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_REFRESH	;# SDRC_MR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_LMR		;# SDRC_MR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_NORMAL	;# SDRC_MR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $::AT91_SDRAMC_TR	1200				;# SDRAM_TR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+
+	mww $::AT91_MATRIX 0xf		;# MATRIX_MCFG - REMAP all masters
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9_sdramc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9_sdramc.cfg
new file mode 100644
index 0000000..658b6c3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9_sdramc.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# SDRAM Controller (SDRAMC) registers
+set AT91_SDRAMC_MR		[expr {$AT91_SDRAMC + 0x00}]	;# SDRAM Controller Mode Register
+set		AT91_SDRAMC_MODE	[expr {0xf << 0}]	;# Command Mode
+set			AT91_SDRAMC_MODE_NORMAL		0
+set			AT91_SDRAMC_MODE_NOP		1
+set			AT91_SDRAMC_MODE_PRECHARGE	2
+set			AT91_SDRAMC_MODE_LMR		3
+set			AT91_SDRAMC_MODE_REFRESH	4
+set			AT91_SDRAMC_MODE_EXT_LMR	5
+set			AT91_SDRAMC_MODE_DEEP		6
+
+set AT91_SDRAMC_TR		[expr {$AT91_SDRAMC + 0x04}]	;# SDRAM Controller Refresh Timer Register
+set		AT91_SDRAMC_COUNT	[expr {0xfff << 0}]		;# Refresh Timer Counter
+
+set AT91_SDRAMC_CR		[expr {$AT91_SDRAMC + 0x08}]	;# SDRAM Controller Configuration Register
+set		AT91_SDRAMC_NC		[expr {3 << 0}]		;# Number of Column Bits
+set			AT91_SDRAMC_NC_8	[expr {0 << 0}]
+set			AT91_SDRAMC_NC_9	[expr {1 << 0}]
+set			AT91_SDRAMC_NC_10	[expr {2 << 0}]
+set			AT91_SDRAMC_NC_11	[expr {3 << 0}]
+set		AT91_SDRAMC_NR		[expr {3 << 2}]		;# Number of Row Bits
+set			AT91_SDRAMC_NR_11	[expr {0 << 2}]
+set			AT91_SDRAMC_NR_12	[expr {1 << 2}]
+set			AT91_SDRAMC_NR_13	[expr {2 << 2}]
+set		AT91_SDRAMC_NB		[expr {1 << 4}]		;# Number of Banks
+set			AT91_SDRAMC_NB_2	[expr {0 << 4}]
+set			AT91_SDRAMC_NB_4	[expr {1 << 4}]
+set		AT91_SDRAMC_CAS		[expr {3 << 5}]		;# CAS Latency
+set			AT91_SDRAMC_CAS_1	[expr {1 << 5}]
+set			AT91_SDRAMC_CAS_2	[expr {2 << 5}]
+set			AT91_SDRAMC_CAS_3	[expr {3 << 5}]
+set		AT91_SDRAMC_DBW		[expr {1 << 7}]		;# Data Bus Width
+set			AT91_SDRAMC_DBW_32	[expr {0 << 7}]
+set			AT91_SDRAMC_DBW_16	[expr {1 << 7}]
+set		AT91_SDRAMC_TWR		[expr {0xf <<  8}]		;# Write Recovery Delay
+set		AT91_SDRAMC_TRC		[expr {0xf << 12}]		;# Row Cycle Delay
+set		AT91_SDRAMC_TRP		[expr {0xf << 16}]		;# Row Precharge Delay
+set		AT91_SDRAMC_TRCD	[expr {0xf << 20}]		;# Row to Column Delay
+set		AT91_SDRAMC_TRAS	[expr {0xf << 24}]		;# Active to Precharge Delay
+set		AT91_SDRAMC_TXSR	[expr {0xf << 28}]		;# Exit Self Refresh to Active Delay
+
+set AT91_SDRAMC_LPR		[expr {$AT91_SDRAMC + 0x10}]	;# SDRAM Controller Low Power Register
+set		AT91_SDRAMC_LPCB		[expr {3 << 0}]	;# Low-power Configurations
+set			AT91_SDRAMC_LPCB_DISABLE		0
+set			AT91_SDRAMC_LPCB_SELF_REFRESH		1
+set			AT91_SDRAMC_LPCB_POWER_DOWN		2
+set			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
+set		AT91_SDRAMC_PASR		[expr {7 << 4}]	;# Partial Array Self Refresh
+set		AT91_SDRAMC_TCSR		[expr {3 << 8}]	;# Temperature Compensated Self Refresh
+set		AT91_SDRAMC_DS			[expr {3 << 10}]	;# Drive Strength
+set		AT91_SDRAMC_TIMEOUT		[expr {3 << 12}]	;# Time to define when Low Power Mode is enabled
+set			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	[expr {0 << 12}]
+set			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	[expr {1 << 12}]
+set			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	[expr {2 << 12}]
+
+set AT91_SDRAMC_IER		[expr {$AT91_SDRAMC + 0x14}]	;# SDRAM Controller Interrupt Enable Register
+set AT91_SDRAMC_IDR		[expr {$AT91_SDRAMC + 0x18}]	;# SDRAM Controller Interrupt Disable Register
+set AT91_SDRAMC_IMR		[expr {$AT91_SDRAMC + 0x1C}]	;# SDRAM Controller Interrupt Mask Register
+set AT91_SDRAMC_ISR		[expr {$AT91_SDRAMC + 0x20}]	;# SDRAM Controller Interrupt Status Register
+set		AT91_SDRAMC_RES		[expr {1 << 0}]		;# Refresh Error Status
+
+set AT91_SDRAMC_MDR		[expr {$AT91_SDRAMC + 0x24}]	;# SDRAM Memory Device Register
+set		AT91_SDRAMC_MD		[expr {3 << 0}]		;# Memory Device Type
+set			AT91_SDRAMC_MD_SDRAM		0
+set			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9_smc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9_smc.cfg
new file mode 100644
index 0000000..c096c4a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/at91sam9_smc.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set		AT91_SMC_READMODE	[expr {1 <<  0}]		;# Read Mode
+set		AT91_SMC_WRITEMODE	[expr {1 <<  1}]		;# Write Mode
+set		AT91_SMC_EXNWMODE	[expr {3 <<  4}]		;# NWAIT Mode
+set			AT91_SMC_EXNWMODE_DISABLE	[expr {0 << 4}]
+set			AT91_SMC_EXNWMODE_FROZEN	[expr {2 << 4}]
+set			AT91_SMC_EXNWMODE_READY		[expr {3 << 4}]
+set		AT91_SMC_BAT		[expr {1 <<  8}]		;# Byte Access Type
+set			AT91_SMC_BAT_SELECT		[expr {0 << 8}]
+set			AT91_SMC_BAT_WRITE		[expr {1 << 8}]
+set		AT91_SMC_DBW		[expr {3 << 12}]		;# Data Bus Width */
+set			AT91_SMC_DBW_8			[expr {0 << 12}]
+set			AT91_SMC_DBW_16			[expr {1 << 12}]
+set			AT91_SMC_DBW_32			[expr {2 << 12}]
+set		AT91_SMC_TDFMODE	[expr {1 << 20}]		;# TDF Optimization - Enabled
+set		AT91_SMC_PMEN		[expr {1 << 24}]		;# Page Mode Enabled
+set		AT91_SMC_PS		[expr {3 << 28}]		;# Page Size
+set			AT91_SMC_PS_4			[expr {0 << 28}]
+set			AT91_SMC_PS_8			[expr {1 << 28}]
+set			AT91_SMC_PS_16			[expr {2 << 28}]
+set			AT91_SMC_PS_32			[expr {3 << 28}]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/hardware.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/hardware.cfg
new file mode 100644
index 0000000..069d4b7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/hardware.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# External Memory Map
+set AT91_CHIPSELECT_0	0x10000000
+set AT91_CHIPSELECT_1	0x20000000
+set AT91_CHIPSELECT_2	0x30000000
+set AT91_CHIPSELECT_3	0x40000000
+set AT91_CHIPSELECT_4	0x50000000
+set AT91_CHIPSELECT_5	0x60000000
+set AT91_CHIPSELECT_6	0x70000000
+set AT91_CHIPSELECT_7	0x80000000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/pmc.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/pmc.tcl
new file mode 100644
index 0000000..0f997ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/pmc.tcl
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if [info exists AT91C_MAINOSC_FREQ] {
+    # user set this... let it be.
+} {
+    # 18.432mhz is a common thing...
+    set AT91C_MAINOSC_FREQ 18432000
+}
+global AT91C_MAINOSC_FREQ
+
+if [info exists AT91C_SLOWOSC_FREQ] {
+    # user set this... let it be.
+} {
+    # 32khz is the norm
+    set AT91C_SLOWOSC_FREQ 32768
+}
+global AT91C_SLOWOSC_FREQ
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/rtt.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/rtt.tcl
new file mode 100644
index 0000000..1ef8373
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/rtt.tcl
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}]
+set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}]
+set RTTC_RTVR [expr {$AT91C_BASE_RTTC + 0x08}]
+set RTTC_RTSR [expr {$AT91C_BASE_RTTC + 0x0c}]
+global RTTC_RTMR
+global RTTC_RTAR
+global RTTC_RTVR
+global RTTC_RTSR
+
+proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
+    set rtpres [expr {$VAL & 0x0ffff}]
+    global BIT16 BIT17
+    if { $rtpres == 0 } {
+	set rtpres 65536;
+    }
+    global AT91C_SLOWOSC_FREQ
+    # Nasty hack, make this a float by tacking a .0 on the end
+    # otherwise, jim makes the value an integer
+    set f [expr "$AT91C_SLOWOSC_FREQ.0 / $rtpres.0"]
+    echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
+    if { $VAL & $BIT16 } {
+	echo "\tBit16 -> Alarm IRQ Enabled"
+    } else {
+	echo "\tBit16 -> Alarm IRQ Disabled"
+    }
+    if { $VAL & $BIT17 } {
+	echo "\tBit17 -> RTC Inc IRQ Enabled"
+    } else {
+	echo "\tBit17 -> RTC Inc IRQ Disabled"
+    }
+    # Bit 18 is write only.
+}
+
+proc show_RTTC_RTSR_helper { NAME ADDR VAL } {
+    global BIT0 BIT1
+    if { $VAL & $BIT0 } {
+	echo "\tBit0 -> ALARM PENDING"
+    } else {
+	echo "\tBit0 -> alarm not pending"
+    }
+    if { $VAL & $BIT1 } {
+	echo "\tBit0 -> RTINC PENDING"
+    } else {
+	echo "\tBit0 -> rtinc not pending"
+    }
+}
+
+proc show_RTTC { } {
+
+    show_mmr32_reg RTTC_RTMR
+    show_mmr32_reg RTTC_RTAR
+    show_mmr32_reg RTTC_RTVR
+    show_mmr32_reg RTTC_RTSR
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/sam9_smc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/sam9_smc.cfg
new file mode 100644
index 0000000..87880c7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/sam9_smc.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Setup register
+#
+# ncs_read_setup
+# nrd_setup
+# ncs_write_setup
+# set nwe_setup
+#
+#
+# Pulse register
+#
+# ncs_read_pulse
+# nrd_pulse
+# ncs_write_pulse
+# nwe_pulse
+#
+#
+# Cycle register
+#
+# read_cycle 0
+# write_cycle 0
+#
+#
+# Mode register
+#
+# mode
+# tdf_cycles
+proc sam9_smc_config { cs smc_config } {
+	;# Setup Register for CS n
+	set AT91_SMC_SETUP [expr {$::AT91_SMC + 0x00 + $cs * 0x10}]
+	set val [expr {$smc_config(nwe_setup) << 0}]
+	set val [expr {$val | $smc_config(ncs_write_setup) << 8}]
+	set val [expr {$val | $smc_config(nrd_setup)) << 16}]
+	set val [expr {$val | $smc_config(ncs_read_setup) << 24}]
+	mww $AT91_SMC_SETUP $val
+
+	;# Pulse Register for CS n
+	set AT91_SMC_PULSE [expr {$::AT91_SMC + 0x04 + $cs * 0x10}]
+	set val [expr {$smc_config(nwe_pulse) << 0}]
+	set val [expr {$val | $smc_config(ncs_write_pulse) << 8}]
+	set val [expr {$val | $smc_config(nrd_pulse) << 16}]
+	set val [expr {$val | $smc_config(ncs_read_pulse) << 24}]
+	mww $AT91_SMC_PULSE $val
+
+	;# Cycle Register for CS n
+	set AT91_SMC_CYCLE [expr {$::AT91_SMC + 0x08 + $cs * 0x10}]
+	set val [expr {$smc_config(write_cycle) << 0}]
+	set val [expr {$val | $smc_config(read_cycle) << 16}]
+	mww $AT91_SMC_CYCLE $val
+
+	;# Mode Register for CS n
+	set AT91_SMC_MODE [expr {$::AT91_SMC + 0x0c + $cs * 0x10}]
+	set val [expr {$smc_config(mode) << 0}]
+	set val [expr {$val | $smc_config(tdf_cycles) << 16}]
+	mww $AT91_SMC_MODE $val
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/usarts.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/usarts.tcl
new file mode 100644
index 0000000..62a651b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/atmel/at91/usarts.tcl
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# the DBGU and USARTs are 'almost' indentical'
+set DBGU_CR         [expr {$AT91C_BASE_DBGU + 0x00000000}]
+set DBGU_MR         [expr {$AT91C_BASE_DBGU + 0x00000004}]
+set DBGU_IER        [expr {$AT91C_BASE_DBGU + 0x00000008}]
+set DBGU_IDR        [expr {$AT91C_BASE_DBGU + 0x0000000C}]
+set DBGU_IMR        [expr {$AT91C_BASE_DBGU + 0x00000010}]
+set DBGU_CSR        [expr {$AT91C_BASE_DBGU + 0x00000014}]
+set DBGU_RHR        [expr {$AT91C_BASE_DBGU + 0x00000018}]
+set DBGU_THR        [expr {$AT91C_BASE_DBGU + 0x0000001C}]
+set DBGU_BRGR       [expr {$AT91C_BASE_DBGU + 0x00000020}]
+# no RTOR
+# no TTGR
+# no FIDI
+# no NER
+set DBGU_CIDR       [expr {$AT91C_BASE_DBGU + 0x00000040}]
+set DBGU_EXID       [expr {$AT91C_BASE_DBGU + 0x00000044}]
+set DBGU_FNTR       [expr {$AT91C_BASE_DBGU + 0x00000048}]
+
+
+set USx_CR           0x00000000
+set USx_MR           0x00000004
+set USx_IER          0x00000008
+set USx_IDR          0x0000000C
+set USx_IMR          0x00000010
+set USx_CSR          0x00000014
+set USx_RHR          0x00000018
+set USx_THR          0x0000001C
+set USx_BRGR         0x00000020
+set USx_RTOR         0x00000024
+set USx_TTGR         0x00000028
+set USx_FIDI         0x00000040
+set USx_NER          0x00000044
+set USx_IF           0x0000004C
+
+# Create all the uarts that exist..
+# we blow up if there are >9
+
+
+proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
+    # First - just print it
+
+    set x [show_normalize_bitfield $VAL 3 0]
+    if { $x == 0 } {
+	echo "\tNormal operation"
+    } else {
+	echo [format "\tNon Normal operation mode: 0x%02x" $x]
+    }
+
+    set x [show_normalize_bitfield $VAL 11 9]
+    set s "unknown"
+    switch -exact $x {
+	0 { set s "Even" }
+	1 { set s "Odd" }
+	2 { set s "Force=0" }
+	3 { set s "Force=1" }
+	* {
+	    set $x [expr {$x & 6}]
+	    switch -exact $x {
+		4 { set s "None" }
+		6 { set s "Multidrop Mode" }
+	    }
+	}
+    }
+    echo [format "\tParity: %s " $s]
+
+    set x [expr {5 + [show_normalize_bitfield $VAL 7 6]}]
+    echo [format "\tDatabits: %d" $x]
+
+    set x [show_normalize_bitfield $VAL 13 12]
+    switch -exact $x {
+	0 { echo "\tStop bits: 1" }
+	1 { echo "\tStop bits: 1.5" }
+	2 { echo "\tStop bits: 2" }
+	3 { echo "\tStop bits: Illegal/Reserved" }
+    }
+}
+
+# For every possbile usart...
+foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } {
+    set n AT91C_BASE_[set WHO]
+    set str ""
+
+    # Only if it exists on the chip
+    if [ info exists $n ] {
+	# Hence: $n - is like AT91C_BASE_USx
+	# For every sub-register
+	foreach REG {CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER IF}	{
+	    # vn = variable name
+	    set vn [set WHO]_[set REG]
+	    # vn = USx_IER
+	    # vv = variable value
+	    set vv [expr "$$n + [set USx_[set REG]]"]
+	    # And VV is the address in memory of that register
+
+
+	    # make that VN a GLOBAL so others can find it
+	    global $vn
+	    set $vn $vv
+
+	    # Create a command for this specific register.
+	    proc show_$vn { } "show_mmr32_reg $vn"
+
+	    # Add this command to the Device(as a whole) command
+	    set str "$str\nshow_$vn"
+	}
+	# Now - create the DEVICE(as a whole) command
+	set fn show_$WHO
+	proc $fn { } $str
+    }
+}
+
+# The Debug Uart is special..
+set str ""
+
+
+# For every sub-register
+foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR
+    DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} {
+
+    # Create a command for this specific register.
+    proc show_$REG { } "show_mmr32_reg $REG"
+
+    # Add this command to the Device(as a whole) command
+    set str "$str\nshow_$REG"
+}
+
+# Now - create the DEVICE(as a whole) command
+proc show_DBGU { } $str
+
+unset str
+
+proc show_DBGU_MR_helper { NAME ADDR VAL } { show_mmr_USx_MR_helper $NAME $ADDR $VAL }
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/spear/quirk_no_srst.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/spear/quirk_no_srst.tcl
new file mode 100644
index 0000000..e8640f4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/spear/quirk_no_srst.tcl
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Quirks to bypass missing SRST on JTAG connector
+# EVALSPEAr310 Rev. 2.0
+# http://www.st.com/spear
+#
+# Date:      2010-08-17
+# Author:    Antonio Borneo 
+
+# For boards that have JTAG SRST not connected.
+# We use "arm9 vector_catch reset" to catch button reset event.
+
+
+$_TARGETNAME configure -event reset-assert sp_reset_assert
+$_TARGETNAME configure -event reset-deassert-post sp_reset_deassert_post
+
+# keeps the name of the SPEAr target
+global sp_target_name
+set sp_target_name $_TARGETNAME
+
+# Keeps the argument of "reset" command (run, init, halt).
+global sp_reset_mode
+set sp_reset_mode ""
+
+# Helper procedure. Returns 0 is target is halted.
+proc sp_is_halted {} {
+	global sp_target_name
+
+	return [expr {[string compare [$sp_target_name curstate] "halted" ] == 0}]
+}
+
+# wait for reset button to be pressed, causing CPU to get halted
+proc sp_reset_deassert_post {} {
+	global sp_reset_mode
+
+	set bar(0) |
+	set bar(1) /
+	set bar(2) -
+	set bar(3) \\
+
+	poll on
+	echo "====> Press reset button on the board <===="
+	for {set i 0} { [sp_is_halted] == 0 } { set i [expr {$i + 1}]} {
+		echo -n "$bar([expr {$i & 3}])\r"
+		sleep 200
+	}
+
+	# Remove catch reset event
+	arm9 vector_catch none
+
+	# CPU is halted, but we typed "reset run" ...
+	if { [string compare $sp_reset_mode "run"] == 0 } {
+		resume
+	}
+}
+
+# Override reset-assert, since no SRST available
+# Catch reset event
+proc sp_reset_assert {} {
+	arm9 vector_catch reset
+}
+
+# Override default init_reset{mode} to catch parameter "mode"
+proc init_reset {mode} {
+	global sp_reset_mode
+
+	set sp_reset_mode $mode
+
+	# We need to detect CPU get halted, so exit from halt
+	if { [sp_is_halted] } {
+		echo "Resuming CPU to detect reset"
+		resume
+	}
+
+	# Execute default init_reset{mode}
+	jtag arp_init-reset
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/spear/spear3xx.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/spear/spear3xx.tcl
new file mode 100644
index 0000000..474ebe3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/spear/spear3xx.tcl
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Generic init scripts for all ST SPEAr3xx family
+# http://www.st.com/spear
+#
+# Date:      2010-09-23
+# Author:    Antonio Borneo 
+
+
+# Initialize internal clock
+# Default:
+# - Crystal =  24 MHz
+# - PLL1    = 332 MHz
+# - PLL2    = 332 MHz
+# - CPU_CLK = 332 MHz
+# - DDR_CLK = 332 MHz async
+# - HCLK    = 166 MHz
+# - PCLK    =  83 MHz
+proc sp3xx_clock_default {} {
+	mww 0xfca00000 0x00000002	;# set sysclk slow
+	mww 0xfca00014 0x0ffffff8	;# set pll timeout to minimum (100us ?!?)
+
+	# DDRCORE disable to change frequency
+	set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}]
+	mww 0xfca8002c $val
+	mww 0xfca8002c $val ;# Yes, write twice!
+
+	# programming PLL1
+	mww 0xfca8000c 0xa600010c	;# M=166 P=1 N=12
+	mww 0xfca80008 0x00001c0a	;# power down
+	mww 0xfca80008 0x00001c0e	;# enable
+	mww 0xfca80008 0x00001c06	;# strobe
+	mww 0xfca80008 0x00001c0e
+	while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 }
+
+	# programming PLL2
+	mww 0xfca80018 0xa600010c	;# M=166, P=1, N=12
+	mww 0xfca80014 0x00001c0a	;# power down
+	mww 0xfca80014 0x00001c0e	;# enable
+	mww 0xfca80014 0x00001c06	;# strobe
+	mww 0xfca80014 0x00001c0e
+	while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 }
+
+	mww 0xfca80028 0x00000082	;# enable plltimeen
+	mww 0xfca80024 0x00000511	;# set hclkdiv="/2" & pclkdiv="/2"
+
+	mww 0xfca00000 0x00000004	;# setting SYSCTL to NORMAL mode
+	while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 }
+
+	# Select source of DDR clock
+	#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
+	mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2
+
+	# DDRCORE enable after change frequency
+	mmw 0xfca8002c 0x20000000 0x00000000
+}
+
+proc sp3xx_common_init {} {
+	mww 0xfca8002c 0xfffffff8	;# enable clock of all peripherals
+	mww 0xfca80038 0x00000000	;# remove reset of all peripherals
+
+	mww 0xfca80034 0x0000ffff	;# enable all RAS clocks
+	mww 0xfca80040 0x00000000	;# remove all RAS resets
+
+	mww 0xfca800e4 0x78000008	;# COMP1V8_REG
+	mww 0xfca800ec 0x78000008	;# COMP3V3_REG
+
+	mww 0xfc000000 0x10000f5f	;# init SMI and set HW mode
+	mww 0xfc000000 0x00000f5f
+
+	# Initialize Bus Interconnection Matrix
+	# All ports Round-Robin and lowest priority
+	mww 0xfca8007c 0x80000007
+	mww 0xfca80080 0x80000007
+	mww 0xfca80084 0x80000007
+	mww 0xfca80088 0x80000007
+	mww 0xfca8008c 0x80000007
+	mww 0xfca80090 0x80000007
+	mww 0xfca80094 0x80000007
+	mww 0xfca80098 0x80000007
+	mww 0xfca8009c 0x80000007
+}
+
+
+# Specific init scripts for ST SPEAr300
+proc sp300_init {} {
+	mww 0x99000000 0x00003fff	;# RAS function enable
+}
+
+
+# Specific init scripts for ST SPEAr310
+proc sp310_init {} {
+	mww 0xb4000008 0x00002ff4	;# RAS function enable
+
+	mww 0xfca80050 0x00000001	;# Enable clk mem port 1
+
+	mww 0xfca8013c 0x2f7bc210	;# plgpio_pad_drv
+	mww 0xfca80140 0x017bdef6
+}
+
+proc sp310_emi_init {} {
+	# set EMI pad strength
+	mmw 0xfca80134 0x0e000000 0x00000000
+	mmw 0xfca80138 0x0e739ce7 0x00000000
+	mmw 0xfca8013c 0x00039ce7 0x00000000
+
+	# set safe EMI timing as in BootROM
+	#mww 0x4f000000 0x0000000f	;# tAP_0_reg
+	#mww 0x4f000004 0x00000000	;# tSDP_0_reg
+	#mww 0x4f000008 0x000000ff	;# tDPw_0_reg
+	#mww 0x4f00000c 0x00000111	;# tDPr_0_reg
+	#mww 0x4f000010 0x00000002	;# tDCS_0_reg
+
+	# set fast EMI timing as in Linux
+	mww 0x4f000000 0x00000010	;# tAP_0_reg
+	mww 0x4f000004 0x00000005	;# tSDP_0_reg
+	mww 0x4f000008 0x0000000a	;# tDPw_0_reg
+	mww 0x4f00000c 0x0000000a	;# tDPr_0_reg
+	mww 0x4f000010 0x00000005	;# tDCS_0_re
+
+	# 32bit wide, 8/16/32bit access
+	mww 0x4f000014 0x0000000e	;# control_0_reg
+	mww 0x4f000094 0x0000003f	;# ack_reg
+}
+
+
+# Specific init scripts for ST SPEAr320
+proc sp320_init {} {
+	mww 0xb300000c 0xffffac04	;# RAS function enable
+	mww 0xb3000010 0x00000001	;# RAS mode select
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/spear/spear3xx_ddr.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/spear/spear3xx_ddr.tcl
new file mode 100644
index 0000000..0696221
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/spear/spear3xx_ddr.tcl
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Init scripts to configure DDR controller of SPEAr3xx
+# http://www.st.com/spear
+# Original values taken from XLoader source code
+#
+# Date:      2010-09-23
+# Author:    Antonio Borneo 
+
+
+proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
+	if { $ddr_chips != 1 && $ddr_chips != 2 } {
+		error "Only 1 or 2 DDR chips permitted. Wrong value $ddr_chips"
+	}
+
+	if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
+		ddr_spr3xx_mt47h64m16_3_333_cl5_async $ddr_chips
+		set ddr_size 0x08000000
+	## add here new DDR chip definition. Prototype:
+	#} elseif { $ddr_type == "?????" } {
+	#	????? $ddr_chips
+	#	set ddr_size 0x?????
+	} else {
+		error "sp3xx_ddr_init: unrecognized DDR type $ddr_type"
+	}
+
+	# MPMC START
+	mww 0xfc60001c 0x01000100
+
+	if { $ddr_chips == 2 } {
+		echo [format \
+			"Double chip DDR memory. Total memory size 0x%08x byte" \
+			[expr {2 * $ddr_size}]]
+	} else {
+		echo [format \
+			"Single chip DDR memory. Memory size 0x%08x byte" \
+			$ddr_size]
+	}
+}
+
+
+# from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S
+proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {ddr_chips} {
+	# DDR_PAD_REG
+	mww 0xfca800f0 0x00003aa5
+
+	# Use "1:2 sync" only when DDR clock source is PLL1 and
+	# HCLK is half of PLL1
+	mww 0xfc600000 0x00000001	;# MEMCTL_AHB_SET_00 # This is async
+	mww 0xfc600004 0x00000000	;# MEMCTL_AHB_SET_01
+#	mww 0xfc600000 0x02020201	;# MEMCTL_AHB_SET_00 # This is 1:2 sync
+#	mww 0xfc600004 0x02020202	;# MEMCTL_AHB_SET_01
+
+	mww 0xfc600008 0x01000000	;# MEMCTL_RFSH_SET_00
+	mww 0xfc60000c 0x00000101	;# MEMCTL_DLL_SET_00
+	mww 0xfc600010 0x00000101	;# MEMCTL_GP_00
+	mww 0xfc600014 0x01000000	;# MEMCTL_GP_01
+	mww 0xfc600018 0x00010001	;# MEMCTL_GP_02
+	mww 0xfc60001c 0x00000100	;# MEMCTL_GP_03
+	mww 0xfc600020 0x00010001	;# MEMCTL_GP_04
+	if { $ddr_chips == 2 } {
+		mww 0xfc600024 0x01020203	;# MEMCTL_GP_05
+		mww 0xfc600028 0x01000102	;# MEMCTL_GP_06
+		mww 0xfc60002c 0x02000202	;# MEMCTL_AHB_SET_02
+	} else {
+		mww 0xfc600024 0x00000201	;# MEMCTL_GP_05
+		mww 0xfc600028 0x02000001	;# MEMCTL_GP_06
+		mww 0xfc60002c 0x02000201	;# MEMCTL_AHB_SET_02
+	}
+	mww 0xfc600030 0x04040105	;# MEMCTL_AHB_SET_03
+	mww 0xfc600034 0x03030302	;# MEMCTL_AHB_SET_04
+	mww 0xfc600038 0x02040101	;# MEMCTL_AHB_SET_05
+	mww 0xfc60003c 0x00000002	;# MEMCTL_AHB_SET_06
+	mww 0xfc600044 0x03000405	;# MEMCTL_DQS_SET_0
+	mww 0xfc600048 0x03040002	;# MEMCTL_TIME_SET_01
+	mww 0xfc60004c 0x04000305	;# MEMCTL_TIME_SET_02
+	mww 0xfc600050 0x0505053f	;# MEMCTL_AHB_RELPR_00
+	mww 0xfc600054 0x05050505	;# MEMCTL_AHB_RELPR_01
+	mww 0xfc600058 0x04040405	;# MEMCTL_AHB_RELPR_02
+	mww 0xfc60005c 0x04040404	;# MEMCTL_AHB_RELPR_03
+	mww 0xfc600060 0x03030304	;# MEMCTL_AHB_RELPR_04
+	mww 0xfc600064 0x03030303	;# MEMCTL_AHB_RELPR_05
+	mww 0xfc600068 0x02020203	;# MEMCTL_AHB_RELPR_06
+	mww 0xfc60006c 0x02020202	;# MEMCTL_AHB_RELPR_07
+	mww 0xfc600070 0x01010102	;# MEMCTL_AHB_RELPR_08
+	mww 0xfc600074 0x01010101	;# MEMCTL_AHB_RELPR_09
+	mww 0xfc600078 0x00000001	;# MEMCTL_AHB_RELPR_10
+	mww 0xfc600088 0x0a0c0a00	;# MEMCTL_DQS_SET_1
+	mww 0xfc60008c 0x0000023f	;# MEMCTL_GP_07
+	mww 0xfc600090 0x00050a00	;# MEMCTL_GP_08
+	mww 0xfc600094 0x11000000	;# MEMCTL_GP_09
+	mww 0xfc600098 0x00001302	;# MEMCTL_GP_10
+	mww 0xfc60009c 0x00001c1c	;# MEMCTL_DLL_SET_01
+	mww 0xfc6000a0 0x7c000000	;# MEMCTL_DQS_OUT_SHIFT
+	mww 0xfc6000a4 0x005c0000	;# MEMCTL_WR_DQS_SHIFT
+	mww 0xfc6000a8 0x2b050e00	;# MEMCTL_TIME_SET_03
+	mww 0xfc6000ac 0x00640064	;# MEMCTL_AHB_PRRLX_00
+	mww 0xfc6000b0 0x00640064	;# MEMCTL_AHB_PRRLX_01
+	mww 0xfc6000b4 0x00000064	;# MEMCTL_AHB_PRRLX_02
+	mww 0xfc6000b8 0x00000000	;# MEMCTL_OUTRANGE_LGTH
+	mww 0xfc6000bc 0x00200020	;# MEMCTL_AHB_RW_SET_00
+	mww 0xfc6000c0 0x00200020	;# MEMCTL_AHB_RW_SET_01
+	mww 0xfc6000c4 0x00200020	;# MEMCTL_AHB_RW_SET_02
+	mww 0xfc6000c8 0x00200020	;# MEMCTL_AHB_RW_SET_03
+	mww 0xfc6000cc 0x00200020	;# MEMCTL_AHB_RW_SET_04
+	mww 0xfc6000d8 0x00000a24	;# MEMCTL_TREF
+	mww 0xfc6000dc 0x00000000	;# MEMCTL_EMRS3_DATA
+	mww 0xfc6000e0 0x5b1c00c8	;# MEMCTL_TIME_SET_04
+	mww 0xfc6000e4 0x00c8002e	;# MEMCTL_TIME_SET_05
+	mww 0xfc6000e8 0x00000000	;# MEMCTL_VERSION
+	mww 0xfc6000ec 0x0001046b	;# MEMCTL_TINIT
+	mww 0xfc6000f0 0x00000000	;# MEMCTL_OUTRANGE_ADDR_01
+	mww 0xfc6000f4 0x00000000	;# MEMCTL_OUTRANGE_ADDR_02
+	mww 0xfc600104 0x001c0000	;# MEMCTL_DLL_DQS_DELAY_BYPASS_0
+	mww 0xfc600108 0x0019001c	;# MEMCTL_DLL_SET_02
+	mww 0xfc60010c 0x00100000	;# MEMCTL_DLL_SET_03
+	mww 0xfc600110 0x001e007a	;# MEMCTL_DQS_SET_2
+	mww 0xfc600188 0x00000000	;# MEMCTL_USER_DEF_REG_0
+	mww 0xfc60018c 0x00000000	;# MEMCTL_USER_DEF_REG_1
+	mww 0xfc600190 0x01010001	;# MEMCTL_GP_11
+	mww 0xfc600194 0x01000000	;# MEMCTL_GP_12
+	mww 0xfc600198 0x00000001	;# MEMCTL_GP_13
+	mww 0xfc60019c 0x00400000	;# MEMCTL_GP_14
+	mww 0xfc6001a0 0x00000000	;# MEMCTL_EMRS2_DATA_X
+	mww 0xfc6001a4 0x00000000	;# MEMCTL_LWPWR_CNT
+	mww 0xfc6001a8 0x00000000	;# MEMCTL_LWPWR_REG
+	mww 0xfc6001ac 0x00860000	;# MEMCTL_GP_15
+	mww 0xfc6001b0 0x00000002	;# MEMCTL_TPDEX
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/stm32/stm32.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/stm32/stm32.tcl
new file mode 100644
index 0000000..3826a57
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/stm32/stm32.tcl
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find bitsbytes.tcl]
+source [find cpu/arm/cortex_m3.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+source [find chip/st/stm32/stm32_regs.tcl]
+source [find chip/st/stm32/stm32_rcc.tcl]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/stm32/stm32_rcc.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/stm32/stm32_rcc.tcl
new file mode 100644
index 0000000..afa4cbf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/stm32/stm32_rcc.tcl
@@ -0,0 +1,291 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set RCC_CR            [expr {$RCC_BASE + 0x00}]
+set RCC_CFGR          [expr {$RCC_BASE + 0x04}]
+set RCC_CIR           [expr {$RCC_BASE + 0x08}]
+set RCC_APB2RSTR      [expr {$RCC_BASE + 0x0c}]
+set RCC_APB1RSTR      [expr {$RCC_BASE + 0x10}]
+set RCC_AHBENR        [expr {$RCC_BASE + 0x14}]
+set RCC_APB2ENR       [expr {$RCC_BASE + 0x18}]
+set RCC_APB1ENR       [expr {$RCC_BASE + 0x1c}]
+set RCC_BDCR          [expr {$RCC_BASE + 0x20}]
+set RCC_CSR           [expr {$RCC_BASE + 0x24}]
+
+
+proc show_RCC_CR { } {
+    if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {
+	error $msg
+    }
+
+    show_mmr_bitfield  0  0 $val HSI      { OFF ON }
+    show_mmr_bitfield  1  1 $val HSIRDY   { NOTRDY RDY  }
+    show_mmr_bitfield  7  3 $val HSITRIM  { _NUMBER_ }
+    show_mmr_bitfield 15  8 $val HSICAL   { _NUMBER_ }
+    show_mmr_bitfield 16 16 $val HSEON    { OFF ON }
+    show_mmr_bitfield 17 17 $val HSERDY   { NOTRDY RDY  }
+    show_mmr_bitfield 18 18 $val HSEBYP   { NOTBYPASSED BYPASSED }
+    show_mmr_bitfield 19 19 $val CSSON    { OFF ON }
+    show_mmr_bitfield 24 24 $val PLLON    { OFF ON }
+    show_mmr_bitfield 25 25 $val PLLRDY   { NOTRDY RDY }
+}
+
+proc show_RCC_CFGR { } {
+    if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
+	error $msg
+    }
+
+
+    show_mmr_bitfield  1  0 $val  SW     { HSI HSE PLL ILLEGAL }
+    show_mmr_bitfield  3  2 $val  SWS    { HSI HSE PLL ILLEGAL }
+    show_mmr_bitfield  7  4 $val  HPRE   { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }
+    show_mmr_bitfield 10  8 $val  PPRE1  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
+    show_mmr_bitfield 13 11 $val  PPRE2  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
+    show_mmr_bitfield 15 14 $val  ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }
+    show_mmr_bitfield 16 16 $val  PLLSRC { HSI_div_2 HSE }
+    show_mmr_bitfield 17 17 $val  PLLXTPRE { hse_div1 hse_div2 }
+    show_mmr_bitfield 21 18 $val  PLLMUL { x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }
+    show_mmr_bitfield 22 22 $val  USBPRE { div1 div1_5 }
+    show_mmr_bitfield 26 24 $val  MCO    { none none none none SysClk HSI HSE PLL_div2 }
+}
+
+
+proc show_RCC_CIR { } {
+    if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
+	error $msg
+    }
+
+}
+
+proc show_RCC_APB2RSTR { } {
+    if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {
+	error $msg
+    }
+    for { set x 0 } { $x < 32 } { incr x } {
+	set bits($x) xxx
+    }
+    set bits(15) adc3
+    set bits(14) usart1
+    set bits(13) tim8
+    set bits(12) spi1
+    set bits(11) tim1
+    set bits(10) adc2
+    set bits(9) adc1
+    set bits(8) iopg
+    set bits(7) iopf
+    set bits(6) iope
+    set bits(5) iopd
+    set bits(4) iopc
+    set bits(3) iopb
+    set bits(2) iopa
+    set bits(1) xxx
+    set bits(0) afio
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC_APB1RSTR { } {
+    if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {
+	error $msg
+    }
+    set bits(31) xxx
+    set bits(30) xxx
+    set bits(29) dac
+    set bits(28) pwr
+    set bits(27) bkp
+    set bits(26) xxx
+    set bits(25) can
+    set bits(24) xxx
+    set bits(23) usb
+    set bits(22) i2c2
+    set bits(21) i2c1
+    set bits(20) uart5
+    set bits(19) uart4
+    set bits(18) uart3
+    set bits(17) uart2
+    set bits(16) xxx
+    set bits(15) spi3
+    set bits(14) spi2
+    set bits(13) xxx
+    set bits(12) xxx
+    set bits(11) wwdg
+    set bits(10) xxx
+    set bits(9) xxx
+    set bits(8) xxx
+    set bits(7) xxx
+    set bits(6) xxx
+    set bits(5) tim7
+    set bits(4) tim6
+    set bits(3) tim5
+    set bits(2) tim4
+    set bits(1) tim3
+    set bits(0) tim2
+    show_mmr32_bits bits $val
+
+}
+
+proc show_RCC_AHBENR   { } {
+    if [ catch { set val [ show_mmr32_reg RCC_AHBENR  ] } msg ] {
+	error $msg
+    }
+    set bits(31) xxx
+    set bits(30) xxx
+    set bits(29) xxx
+    set bits(28) xxx
+    set bits(27) xxx
+    set bits(26) xxx
+    set bits(25) xxx
+    set bits(24) xxx
+    set bits(23) xxx
+    set bits(22) xxx
+    set bits(21) xxx
+    set bits(20) xxx
+    set bits(19) xxx
+    set bits(18) xxx
+    set bits(17) xxx
+    set bits(16) xxx
+    set bits(15) xxx
+    set bits(14) xxx
+    set bits(13) xxx
+    set bits(12) xxx
+    set bits(11) xxx
+    set bits(10) sdio
+    set bits(9) xxx
+    set bits(8) fsmc
+    set bits(7) xxx
+    set bits(6) crce
+    set bits(5) xxx
+    set bits(4) flitf
+    set bits(3) xxx
+    set bits(2) sram
+    set bits(1) dma2
+    set bits(0) dma1
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC_APB2ENR  { } {
+    if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {
+	error $msg
+    }
+    set bits(31) xxx
+    set bits(30) xxx
+    set bits(29) xxx
+    set bits(28) xxx
+    set bits(27) xxx
+    set bits(26) xxx
+    set bits(25) xxx
+    set bits(24) xxx
+    set bits(23) xxx
+    set bits(22) xxx
+    set bits(21) xxx
+    set bits(20) xxx
+    set bits(19) xxx
+    set bits(18) xxx
+    set bits(17) xxx
+    set bits(16) xxx
+    set bits(15) adc3
+    set bits(14) usart1
+    set bits(13) tim8
+    set bits(12) spi1
+    set bits(11) tim1
+    set bits(10) adc2
+    set bits(9) adc1
+    set bits(8) iopg
+    set bits(7) iopf
+    set bits(6) iope
+    set bits(5) iopd
+    set bits(4) iopc
+    set bits(3) iopb
+    set bits(2) iopa
+    set bits(1) xxx
+    set bits(0) afio
+    show_mmr32_bits bits $val
+
+}
+
+proc show_RCC_APB1ENR  { } {
+    if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {
+	error $msg
+    }
+    set bits(31) xxx
+    set bits(30) xxx
+    set bits(29) dac
+    set bits(28) pwr
+    set bits(27) bkp
+    set bits(26) xxx
+    set bits(25) can
+    set bits(24) xxx
+    set bits(23) usb
+    set bits(22) i2c2
+    set bits(21) i2c1
+    set bits(20) usart5
+    set bits(19) usart4
+    set bits(18) usart3
+    set bits(17) usart2
+    set bits(16) xxx
+    set bits(15) spi3
+    set bits(14) spi2
+    set bits(13) xxx
+    set bits(12) xxx
+    set bits(11) wwdg
+    set bits(10) xxx
+    set bits(9) xxx
+    set bits(8) xxx
+    set bits(7) xxx
+    set bits(6) xxx
+    set bits(5) tim7
+    set bits(4) tim6
+    set bits(3) tim5
+    set bits(2) tim4
+    set bits(1) tim3
+    set bits(0) tim2
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC_BDCR     { } {
+    if [ catch { set val [ show_mmr32_reg RCC_BDCR    ] } msg ] {
+	error $msg
+    }
+    for { set x 0 } { $x < 32 } { incr x } {
+	set bits($x) xxx
+    }
+    set bits(0) lseon
+    set bits(1) lserdy
+    set bits(2) lsebyp
+    set bits(8) rtcsel0
+    set bits(9) rtcsel1
+    set bits(15) rtcen
+    set bits(16) bdrst
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC_CSR      { } {
+    if [ catch { set val [ show_mmr32_reg RCC_CSR     ] } msg ] {
+	error $msg
+    }
+    for { set x 0 } { $x < 32 } { incr x } {
+	set bits($x) xxx
+    }
+    set bits(0) lsion
+    set bits(1) lsirdy
+    set bits(24) rmvf
+    set bits(26) pin
+    set bits(27) por
+    set bits(28) sft
+    set bits(29) iwdg
+    set bits(30) wwdg
+    set bits(31) lpwr
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC { } {
+
+    show_RCC_CR
+    show_RCC_CFGR
+    show_RCC_CIR
+    show_RCC_APB2RSTR
+    show_RCC_APB1RSTR
+    show_RCC_AHBENR
+    show_RCC_APB2ENR
+    show_RCC_APB1ENR
+    show_RCC_BDCR
+    show_RCC_CSR
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/stm32/stm32_regs.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/stm32/stm32_regs.tcl
new file mode 100644
index 0000000..07ff1aa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/st/stm32/stm32_regs.tcl
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# /* Peripheral and SRAM base address in the alias region */
+set PERIPH_BB_BASE        0x42000000
+set SRAM_BB_BASE          0x22000000
+
+# /*Peripheral and SRAM base address in the bit-band region */
+set SRAM_BASE             0x20000000
+set PERIPH_BASE           0x40000000
+
+# /*FSMC registers base address */
+set FSMC_R_BASE           0xA0000000
+
+# /*Peripheral memory map */
+set APB1PERIPH_BASE       [set PERIPH_BASE]
+set APB2PERIPH_BASE       [expr {$PERIPH_BASE + 0x10000}]
+set AHBPERIPH_BASE        [expr {$PERIPH_BASE + 0x20000}]
+
+set TIM2_BASE             [expr {$APB1PERIPH_BASE + 0x0000}]
+set TIM3_BASE             [expr {$APB1PERIPH_BASE + 0x0400}]
+set TIM4_BASE             [expr {$APB1PERIPH_BASE + 0x0800}]
+set TIM5_BASE             [expr {$APB1PERIPH_BASE + 0x0C00}]
+set TIM6_BASE             [expr {$APB1PERIPH_BASE + 0x1000}]
+set TIM7_BASE             [expr {$APB1PERIPH_BASE + 0x1400}]
+set RTC_BASE              [expr {$APB1PERIPH_BASE + 0x2800}]
+set WWDG_BASE             [expr {$APB1PERIPH_BASE + 0x2C00}]
+set IWDG_BASE             [expr {$APB1PERIPH_BASE + 0x3000}]
+set SPI2_BASE             [expr {$APB1PERIPH_BASE + 0x3800}]
+set SPI3_BASE             [expr {$APB1PERIPH_BASE + 0x3C00}]
+set USART2_BASE           [expr {$APB1PERIPH_BASE + 0x4400}]
+set USART3_BASE           [expr {$APB1PERIPH_BASE + 0x4800}]
+set UART4_BASE            [expr {$APB1PERIPH_BASE + 0x4C00}]
+set UART5_BASE            [expr {$APB1PERIPH_BASE + 0x5000}]
+set I2C1_BASE             [expr {$APB1PERIPH_BASE + 0x5400}]
+set I2C2_BASE             [expr {$APB1PERIPH_BASE + 0x5800}]
+set CAN_BASE              [expr {$APB1PERIPH_BASE + 0x6400}]
+set BKP_BASE              [expr {$APB1PERIPH_BASE + 0x6C00}]
+set PWR_BASE              [expr {$APB1PERIPH_BASE + 0x7000}]
+set DAC_BASE              [expr {$APB1PERIPH_BASE + 0x7400}]
+
+set AFIO_BASE             [expr {$APB2PERIPH_BASE + 0x0000}]
+set EXTI_BASE             [expr {$APB2PERIPH_BASE + 0x0400}]
+set GPIOA_BASE            [expr {$APB2PERIPH_BASE + 0x0800}]
+set GPIOB_BASE            [expr {$APB2PERIPH_BASE + 0x0C00}]
+set GPIOC_BASE            [expr {$APB2PERIPH_BASE + 0x1000}]
+set GPIOD_BASE            [expr {$APB2PERIPH_BASE + 0x1400}]
+set GPIOE_BASE            [expr {$APB2PERIPH_BASE + 0x1800}]
+set GPIOF_BASE            [expr {$APB2PERIPH_BASE + 0x1C00}]
+set GPIOG_BASE            [expr {$APB2PERIPH_BASE + 0x2000}]
+set ADC1_BASE             [expr {$APB2PERIPH_BASE + 0x2400}]
+set ADC2_BASE             [expr {$APB2PERIPH_BASE + 0x2800}]
+set TIM1_BASE             [expr {$APB2PERIPH_BASE + 0x2C00}]
+set SPI1_BASE             [expr {$APB2PERIPH_BASE + 0x3000}]
+set TIM8_BASE             [expr {$APB2PERIPH_BASE + 0x3400}]
+set USART1_BASE           [expr {$APB2PERIPH_BASE + 0x3800}]
+set ADC3_BASE             [expr {$APB2PERIPH_BASE + 0x3C00}]
+
+set SDIO_BASE             [expr {$PERIPH_BASE + 0x18000}]
+
+set DMA1_BASE             [expr {$AHBPERIPH_BASE + 0x0000}]
+set DMA1_Channel1_BASE    [expr {$AHBPERIPH_BASE + 0x0008}]
+set DMA1_Channel2_BASE    [expr {$AHBPERIPH_BASE + 0x001C}]
+set DMA1_Channel3_BASE    [expr {$AHBPERIPH_BASE + 0x0030}]
+set DMA1_Channel4_BASE    [expr {$AHBPERIPH_BASE + 0x0044}]
+set DMA1_Channel5_BASE    [expr {$AHBPERIPH_BASE + 0x0058}]
+set DMA1_Channel6_BASE    [expr {$AHBPERIPH_BASE + 0x006C}]
+set DMA1_Channel7_BASE    [expr {$AHBPERIPH_BASE + 0x0080}]
+set DMA2_BASE             [expr {$AHBPERIPH_BASE + 0x0400}]
+set DMA2_Channel1_BASE    [expr {$AHBPERIPH_BASE + 0x0408}]
+set DMA2_Channel2_BASE    [expr {$AHBPERIPH_BASE + 0x041C}]
+set DMA2_Channel3_BASE    [expr {$AHBPERIPH_BASE + 0x0430}]
+set DMA2_Channel4_BASE    [expr {$AHBPERIPH_BASE + 0x0444}]
+set DMA2_Channel5_BASE    [expr {$AHBPERIPH_BASE + 0x0458}]
+set RCC_BASE              [expr {$AHBPERIPH_BASE + 0x1000}]
+set CRC_BASE              [expr {$AHBPERIPH_BASE + 0x3000}]
+
+# /*Flash registers base address */
+set FLASH_R_BASE          [expr {$AHBPERIPH_BASE + 0x2000}]
+# /*Flash Option Bytes base address */
+set OB_BASE               0x1FFFF800
+
+# /*FSMC Bankx registers base address */
+set FSMC_Bank1_R_BASE     [expr {$FSMC_R_BASE + 0x0000}]
+set FSMC_Bank1E_R_BASE    [expr {$FSMC_R_BASE + 0x0104}]
+set FSMC_Bank2_R_BASE     [expr {$FSMC_R_BASE + 0x0060}]
+set FSMC_Bank3_R_BASE     [expr {$FSMC_R_BASE + 0x0080}]
+set FSMC_Bank4_R_BASE     [expr {$FSMC_R_BASE + 0x00A0}]
+
+# /*Debug MCU registers base address */
+set DBGMCU_BASE           0xE0042000
+
+# /*System Control Space memory map */
+set SCS_BASE              0xE000E000
+
+set SysTick_BASE          [expr {$SCS_BASE + 0x0010}]
+set NVIC_BASE             [expr {$SCS_BASE + 0x0100}]
+set SCB_BASE              [expr {$SCS_BASE + 0x0D00}]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/ti/lm3s/lm3s.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/ti/lm3s/lm3s.tcl
new file mode 100644
index 0000000..324aad0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/ti/lm3s/lm3s.tcl
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find chip/ti/lm3s/lm3s_regs.tcl]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/ti/lm3s/lm3s_regs.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/ti/lm3s/lm3s_regs.tcl
new file mode 100644
index 0000000..1e86e29
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/chip/ti/lm3s/lm3s_regs.tcl
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#*****************************************************************************
+#
+# The following are defines for the System Control register addresses.
+#
+#*****************************************************************************
+
+set SYSCTL_DID0             0x400FE000  ;# Device Identification 0
+set SYSCTL_DID1             0x400FE004  ;# Device Identification 1
+set SYSCTL_DC0              0x400FE008  ;# Device Capabilities 0
+set SYSCTL_DC1              0x400FE010  ;# Device Capabilities 1
+set SYSCTL_DC2              0x400FE014  ;# Device Capabilities 2
+set SYSCTL_DC3              0x400FE018  ;# Device Capabilities 3
+set SYSCTL_DC4              0x400FE01C  ;# Device Capabilities 4
+set SYSCTL_DC5              0x400FE020  ;# Device Capabilities 5
+set SYSCTL_DC6              0x400FE024  ;# Device Capabilities 6
+set SYSCTL_DC7              0x400FE028  ;# Device Capabilities 7
+set SYSCTL_DC8              0x400FE02C  ;# Device Capabilities 8 ADC
+                                        ;# Channels
+set SYSCTL_PBORCTL          0x400FE030  ;# Brown-Out Reset Control
+set SYSCTL_LDOPCTL          0x400FE034  ;# LDO Power Control
+set SYSCTL_SRCR0            0x400FE040  ;# Software Reset Control 0
+set SYSCTL_SRCR1            0x400FE044  ;# Software Reset Control 1
+set SYSCTL_SRCR2            0x400FE048  ;# Software Reset Control 2
+set SYSCTL_RIS              0x400FE050  ;# Raw Interrupt Status
+set SYSCTL_IMC              0x400FE054  ;# Interrupt Mask Control
+set SYSCTL_MISC             0x400FE058  ;# Masked Interrupt Status and
+                                        ;# Clear
+set SYSCTL_RESC             0x400FE05C  ;# Reset Cause
+set SYSCTL_RCC              0x400FE060  ;# Run-Mode Clock Configuration
+set SYSCTL_PLLCFG           0x400FE064  ;# XTAL to PLL Translation
+set SYSCTL_GPIOHSCTL        0x400FE06C  ;# GPIO High-Speed Control
+set SYSCTL_GPIOHBCTL        0x400FE06C  ;# GPIO High-Performance Bus
+                                        ;# Control
+set SYSCTL_RCC2             0x400FE070  ;# Run-Mode Clock Configuration 2
+set SYSCTL_MOSCCTL          0x400FE07C  ;# Main Oscillator Control
+set SYSCTL_RCGC0            0x400FE100  ;# Run Mode Clock Gating Control
+                                        ;# Register 0
+set SYSCTL_RCGC1            0x400FE104  ;# Run Mode Clock Gating Control
+                                        ;# Register 1
+set SYSCTL_RCGC2            0x400FE108  ;# Run Mode Clock Gating Control
+                                        ;# Register 2
+set SYSCTL_SCGC0            0x400FE110  ;# Sleep Mode Clock Gating Control
+                                        ;# Register 0
+set SYSCTL_SCGC1            0x400FE114  ;# Sleep Mode Clock Gating Control
+                                        ;# Register 1
+set SYSCTL_SCGC2            0x400FE118  ;# Sleep Mode Clock Gating Control
+                                        ;# Register 2
+set SYSCTL_DCGC0            0x400FE120  ;# Deep Sleep Mode Clock Gating
+                                        ;# Control Register 0
+set SYSCTL_DCGC1            0x400FE124  ;# Deep-Sleep Mode Clock Gating
+                                        ;# Control Register 1
+set SYSCTL_DCGC2            0x400FE128  ;# Deep Sleep Mode Clock Gating
+                                        ;# Control Register 2
+set SYSCTL_DSLPCLKCFG       0x400FE144  ;# Deep Sleep Clock Configuration
+set SYSCTL_CLKVCLR          0x400FE150  ;# Clock Verification Clear
+set SYSCTL_PIOSCCAL         0x400FE150  ;# Precision Internal Oscillator
+                                        ;# Calibration
+set SYSCTL_PIOSCSTAT        0x400FE154  ;# Precision Internal Oscillator
+                                        ;# Statistics
+set SYSCTL_LDOARST          0x400FE160  ;# Allow Unregulated LDO to Reset
+                                        ;# the Part
+set SYSCTL_I2SMCLKCFG       0x400FE170  ;# I2S MCLK Configuration
+set SYSCTL_DC9              0x400FE190  ;# Device Capabilities 9 ADC
+                                        ;# Digital Comparators
+set SYSCTL_NVMSTAT          0x400FE1A0  ;# Non-Volatile Memory Information
+
+set SYSCTL_RCC_USESYSDIV    0x00400000  ;# Enable System Clock Divider
+set SYSCTL_RCC2_BYPASS2     0x00000800  ;# PLL Bypass 2
+set SYSCTL_RCC_MOSCDIS      0x00000001  ;# Main Oscillator Disable
+
+set SYSCTL_SRCR0            0x400FE040  ;# Software Reset Control 0
+set SYSCTL_SRCR1            0x400FE044  ;# Software Reset Control 1
+set SYSCTL_SRCR2            0x400FE048  ;# Software Reset Control 2
+
+set SYSCTL_MISC             0x400FE058  ;# Masked Interrupt Status and Clear
+
+set FLASH_FMA               0x400FD000  ;# Flash Memory Address
+set FLASH_FMD               0x400FD004  ;# Flash Memory Data
+set FLASH_FMC               0x400FD008  ;# Flash Memory Control
+set FLASH_FCRIS             0x400FD00C  ;# Flash Controller Raw Interrupt Status
+set FLASH_FCIM              0x400FD010  ;# Flash Controller Interrupt Mask
+set FLASH_FCMISC            0x400FD014  ;# Flash Controller Masked Interrupt Status and Clear
+set FLASH_FMC2              0x400FD020  ;#  Flash Memory Control 2
+set FLASH_FWBVAL            0x400FD030  ;# Flash Write Buffer Valid
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-5m570z-cpld.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-5m570z-cpld.cfg
new file mode 100644
index 0000000..4504a80
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-5m570z-cpld.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# file altera-5m570z-cpld.cfg replaced by altera-maxv.cfg
+echo "DEPRECATED: use altera-maxv.cfg instead of deprecated altera-5m570z-cpld.cfg"
+
+#just to be backward compatible:
+#tap will be 5m570z.tap instead of maxv.tap:
+set CHIPNAME 5m570z
+source [find cpld/altera-maxv.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-epm240.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-epm240.cfg
new file mode 100644
index 0000000..185925a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-epm240.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# file altera-epm240.cfg replaced by altera-maxii.cfg
+echo "DEPRECATED: use altera-maxii.cfg instead of deprecated altera-epm240.cfg"
+
+#just to be backward compatible:
+#tap will be epm240.tap instead of maxii.tap:
+set CHIPNAME epm240
+source [find cpld/altera-maxii.cfg]
+
+# 200ns seems like a good speed
+# c.f. Table 5-34: MAX II JTAG Timing Parameters
+adapter speed 5000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-max10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-max10.cfg
new file mode 100644
index 0000000..a2ed00a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-max10.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# see MAX 10 FPGA Device Architecture
+# Table 3-1: IDCODE Information for MAX 10 Devices
+# Intel MAX 10M02 0x31810dd
+# Intel MAX 10M04 0x318a0dd
+# Intel MAX 10M08 0x31820dd
+# Intel MAX 10M16 0x31830dd
+# Intel MAX 10M25 0x31840dd
+# Intel MAX 10M40 0x318d0dd
+# Intel MAX 10M50 0x31850dd
+# Intel MAX 10M02 0x31010dd
+# Intel MAX 10M04 0x310a0dd
+# Intel MAX 10M08 0x31020dd
+# Intel MAX 10M16 0x31030dd
+# Intel MAX 10M25 0x31040dd
+# Intel MAX 10M40 0x310d0dd
+# Intel MAX 10M50 0x31050dd
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME max10
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \
+	-expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \
+	-expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \
+	-expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \
+	-expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-maxii.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-maxii.cfg
new file mode 100644
index 0000000..2dee37f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-maxii.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Altera MAXII CPLD
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME maxii
+}
+
+# see MAX II Device Handbook
+# Table 3-3: 32-Bit MAX II Device IDCODE
+# Version     Part Number             Manuf. ID        LSB
+# 0000        0010 0000 1010 0001     000 0110 1110    1
+jtag newtap $_CHIPNAME tap -irlen 10 \
+	-expected-id 0x020a10dd \
+	-expected-id 0x020a20dd \
+	-expected-id 0x020a30dd \
+	-expected-id 0x020a40dd \
+	-expected-id 0x020a50dd \
+	-expected-id 0x020a60dd
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-maxv.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-maxv.cfg
new file mode 100644
index 0000000..03fad07
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/altera-maxv.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Altera MAXV 5M24OZ/5M570Z CPLD
+# see MAX V Device Handbook
+# Table 6-3: 32-Bit MAX V Device IDCODE
+# 5M40Z 5M80Z 5M160Z 5M240Z: 0x020A50DD
+# 5M570Z:                    0x020A60DD
+# 5M1270Z:                   0x020A30DD
+# 5M1270Z 5M2210Z:           0x020A40DD
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME maxv
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 \
+  -expected-id 0x020A50DD -expected-id 0x020A60DD \
+  -expected-id 0x020A30DD -expected-id 0x020A40DD
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/jtagspi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/jtagspi.cfg
new file mode 100644
index 0000000..a7f02b9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/jtagspi.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _USER1 0x02
+
+if { [info exists JTAGSPI_IR] } {
+	set _JTAGSPI_IR $JTAGSPI_IR
+} elseif {[info exists JTAGSPI_CHAIN_ID]} {
+	set _JTAGSPI_CHAIN_ID $JTAGSPI_CHAIN_ID
+} else {
+	set _JTAGSPI_IR $_USER1
+}
+
+if { [info exists TARGETNAME] } {
+	set _TARGETNAME $TARGETNAME
+} else {
+	set _TARGETNAME $_CHIPNAME.proxy
+}
+
+if { [info exists FLASHNAME] } {
+	set _FLASHNAME $FLASHNAME
+} else {
+	set _FLASHNAME $_CHIPNAME.spi
+}
+
+target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
+if { [info exists _JTAGSPI_IR] } {
+	flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
+} else {
+    flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID
+}
+
+# initialize jtagspi flash
+# chain_id: identifier of pld (you can get a list with 'pld devices')
+# proxy_bit: file with bitstream connecting JTAG and SPI interface in the PLD.
+# release_from_pwr_down_cmd: optional, command sent to spi flash before probing.
+#                            ex: 0xAB to release from power-dowm.
+#                            Just omit it to not send a command.
+
+proc jtagspi_init {chain_id proxy_bit {release_from_pwr_down_cmd -1}} {
+	# load proxy bitstream $proxy_bit and probe spi flash
+	global _FLASHNAME
+	if { $proxy_bit ne "" } {
+		pld load $chain_id $proxy_bit
+	}
+	reset halt
+	if {$release_from_pwr_down_cmd != -1} {
+		jtagspi cmd $_FLASHNAME 0 $release_from_pwr_down_cmd
+	}
+	flash probe $_FLASHNAME
+}
+
+proc jtagspi_program {bin addr} {
+	# write and verify binary file $bin at offset $addr
+	global _FLASHNAME
+	flash write_image erase $bin $addr
+	flash verify_bank $_FLASHNAME $bin $addr
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/lattice-lc4032ze.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/lattice-lc4032ze.cfg
new file mode 100644
index 0000000..479180f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/lattice-lc4032ze.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Lattice ispMACH 4000ZE family, device LC4032ZE
+# just configure a tap
+jtag newtap LC4032ZE tap -irlen 8 -expected-id  0x01806043
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc3s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc3s.cfg
new file mode 100644
index 0000000..a886739
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc3s.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx spartan3
+# https://docs.xilinx.com/v/u/en-US/ug332
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc3s
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x01414093 \
+	-expected-id 0x0141C093 \
+	-expected-id 0x01428093 \
+	-expected-id 0x01434093 \
+	-expected-id 0x01440093 \
+	-expected-id 0x01448093 \
+	-expected-id 0x01450093 \
+	-expected-id 0x01C10093 \
+	-expected-id 0x01C1A093 \
+	-expected-id 0x01C22093 \
+	-expected-id 0x01C2E093 \
+	-expected-id 0x01C3A093 \
+	-expected-id 0x0140C093 \
+	-expected-id 0x02210093 \
+	-expected-id 0x02218093 \
+	-expected-id 0x02220093 \
+	-expected-id 0x02228093 \
+	-expected-id 0x02230093 \
+	-expected-id 0x02610093 \
+	-expected-id 0x02618093 \
+	-expected-id 0x02620093 \
+	-expected-id 0x02628093 \
+	-expected-id 0x02630093 \
+	-expected-id 0x03840093 \
+	-expected-id 0x0384e093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc4v.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc4v.cfg
new file mode 100644
index 0000000..3eb46eb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc4v.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 4
+# https://docs.xilinx.com/v/u/en-US/ug071
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc4v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+	-expected-id 0x01658093 \
+	-expected-id 0x01E58093 \
+	-expected-id 0x0167C093 \
+	-expected-id 0x02068093 \
+	-expected-id 0x01E64093 \
+	-expected-id 0x016A4093 \
+	-expected-id 0x02088093 \
+	-expected-id 0x016B4093 \
+	-expected-id 0x020B0093 \
+	-expected-id 0x016D8093 \
+	-expected-id 0x01700093 \
+	-expected-id 0x01718093 \
+	-expected-id 0x01734093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg
new file mode 100644
index 0000000..14dde02
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 4
+# https://docs.xilinx.com/v/u/en-US/ug071
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc4vfx
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \
+	-expected-id 0x01E8C093 \
+	-expected-id 0x01EB4093 \
+	-expected-id 0x01EE4093 \
+	-expected-id 0x01F14093 \
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc5v.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc5v.cfg
new file mode 100644
index 0000000..f88bbc1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc5v.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 5
+# https://docs.xilinx.com/v/u/en-US/ug191
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc5v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+	-expected-id 0x0286E093 \
+	-expected-id 0x02896093 \
+	-expected-id 0x028AE093 \
+	-expected-id 0x028D6093 \
+	-expected-id 0x028EC093 \
+	-expected-id 0x0290C093 \
+	-expected-id 0x0295C093 \
+	-expected-id 0x02A56093 \
+	-expected-id 0x02A6E093 \
+	-expected-id 0x02A96093 \
+	-expected-id 0x02AAE093 \
+	-expected-id 0x02AD6093 \
+	-expected-id 0x02AEC093 \
+	-expected-id 0x02B0C093 \
+	-expected-id 0x02B5C093 \
+	-expected-id 0x02E72093 \
+	-expected-id 0x02E9A093 \
+	-expected-id 0x02ECE093 \
+	-expected-id 0x02F3E093 \
+	-expected-id 0x03276093 \
+	-expected-id 0x032C6093 \
+	-expected-id 0x04502093 \
+	-expected-id 0x0453E093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg
new file mode 100644
index 0000000..7420233
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 5
+# https://docs.xilinx.com/v/u/en-US/ug191
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc5vfx
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \
+	-expected-id 0x032D8093 \
+	-expected-id 0x03300093 \
+	-expected-id 0x03334093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc6s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc6s.cfg
new file mode 100644
index 0000000..862c4aa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc6s.cfg
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx spartan6
+# http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc6s
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x04000093 \
+	-expected-id 0x04001093 \
+	-expected-id 0x04002093 \
+	-expected-id 0x04004093 \
+	-expected-id 0x04024093 \
+	-expected-id 0x04008093 \
+	-expected-id 0x04028093 \
+	-expected-id 0x0400E093 \
+	-expected-id 0x0402E093 \
+	-expected-id 0x04011093 \
+	-expected-id 0x04031093 \
+	-expected-id 0x0401D093 \
+	-expected-id 0x0403D093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x1A 0x1B
+
+set XC6S_CFG_IN 0x05
+set XC6S_JSHUTDOWN 0x0d
+set XC6S_JPROGRAM 0x0b
+set XC6S_JSTART 0x0c
+set XC6S_BYPASS 0x3f
+
+proc xc6s_program {tap} {
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program'"
+	global XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS
+	irscan $tap $XC6S_JSHUTDOWN
+	irscan $tap $XC6S_JPROGRAM
+	irscan $tap $XC6S_JSTART
+	irscan $tap $XC6S_BYPASS
+}
+
+#xtp038 and xc3sprog approach
+proc xc6s_program_iprog {tap} {
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program_iprog'"
+	global XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN
+	irscan $tap $XC6S_JSHUTDOWN
+	runtest 16
+	irscan $tap $XC6S_CFG_IN
+	# xtp038 IPROG 16bit flipped
+	drscan $tap 16 0xffff 16 0x9955 16 0x66aa 16 0x850c 16 0x7000 16 0x0004
+	irscan $tap $XC6S_JSTART
+	runtest 32
+	irscan $tap $XC6S_BYPASS
+	runtest 1
+}
+
+set XC6S_ISC_ENABLE 0x10
+set XC6S_ISC_DISABLE 0x16
+set XC6S_ISC_DNA 0x30
+
+# Get the "Device DNA" from the Spartan 6.
+# Most Xilinx FPGA devices contain an embedded, unique device identifier called
+# the "Device DNA". The identifier is nonvolatile, permanently programmed into
+# the FPGA, and is unchangeable providing a great serial / tracking number.
+proc xc6s_get_dna {tap} {
+	global XC6S_ISC_ENABLE XC6S_ISC_DISABLE XC6S_ISC_DNA
+	irscan $tap $XC6S_ISC_ENABLE
+	runtest 64
+	irscan $tap $XC6S_ISC_DNA
+	# Device DNA is 57 bits long, but we can only read 32bits at a time
+	# with OpenOCD.
+	set dna [drscan $tap 16 0 16 0 16 0 9 0]
+	runtest 64
+	irscan $tap $XC6S_ISC_DISABLE
+	runtest 64
+
+	# Convert the binary data into the order impact uses
+	scan $dna "%x %x %x %x" v1 v2 v3 v4
+	set bin_dna [string reverse [concat [format "%09b" $v4][format "%016b" $v3][format "%016b" $v2][format "%016b" $v1]]]
+
+	# Return a hex version of binary
+	scan [format "0b%s" $bin_dna] "%i" hex_dna
+	return $hex_dna
+}
+
+# Print out the "Device DNA" in the same format that impact uses.
+proc xc6s_print_dna {tap} {
+	set hex_dna [xc6s_get_dna $tap]
+
+	puts [format "DNA = %57b (0x%x)\n" $hex_dna $hex_dna]
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc6v.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc6v.cfg
new file mode 100644
index 0000000..d37439c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc6v.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 6
+# https://www.xilinx.com/support/documentation/user_guides/ug360.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc6v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+	-expected-id 0x042A2093 \
+	-expected-id 0x042A4093 \
+	-expected-id 0x042A8093 \
+	-expected-id 0x042AC093 \
+	-expected-id 0x04244093 \
+	-expected-id 0x0424A093 \
+	-expected-id 0x0424C093 \
+	-expected-id 0x04250093 \
+	-expected-id 0x04252093 \
+	-expected-id 0x04256093 \
+	-expected-id 0x0423A093 \
+	-expected-id 0x04286093 \
+	-expected-id 0x04288093 \
+	-expected-id 0x042C4093 \
+	-expected-id 0x042CA093 \
+	-expected-id 0x042CC093 \
+	-expected-id 0x042D0093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7.cfg
new file mode 100644
index 0000000..6f8f4ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7.cfg
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (spartan, artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7
+}
+
+# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x03622093 \
+	-expected-id 0x03620093 \
+	-expected-id 0x037C4093 \
+	-expected-id 0x0362F093 \
+	-expected-id 0x037C8093 \
+	-expected-id 0x037C7093 \
+	-expected-id 0x037C3093 \
+	-expected-id 0x0362E093 \
+	-expected-id 0x037C2093 \
+	-expected-id 0x0362D093 \
+	-expected-id 0x0362C093 \
+	-expected-id 0x03632093 \
+	-expected-id 0x03631093 \
+	-expected-id 0x03636093 \
+	-expected-id 0x03647093 \
+	-expected-id 0x0364C093 \
+	-expected-id 0x03651093 \
+	-expected-id 0x03747093 \
+	-expected-id 0x03656093 \
+	-expected-id 0x03752093 \
+	-expected-id 0x03751093 \
+	-expected-id 0x03671093 \
+	-expected-id 0x03667093 \
+	-expected-id 0x03682093 \
+	-expected-id 0x03687093 \
+	-expected-id 0x03692093 \
+	-expected-id 0x03691093 \
+	-expected-id 0x03696093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x22 0x23
+
+set XC7_JSHUTDOWN 0x0d
+set XC7_JPROGRAM 0x0b
+set XC7_JSTART 0x0c
+set XC7_BYPASS 0x3f
+
+proc xc7_program {tap} {
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc7_program'"
+	global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
+	irscan $tap $XC7_JSHUTDOWN
+	irscan $tap $XC7_JPROGRAM
+	runtest 60000
+	#JSTART prevents this from working...
+	#irscan $tap $XC7_JSTART
+	runtest 2000
+	irscan $tap $XC7_BYPASS
+	runtest 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7v.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7v.cfg
new file mode 100644
index 0000000..8385948
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7v.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# https://bsdl.info/view.htm?sid=08e275a0cd3ac38988ca59b002289d77
+# https://bsdl.info/view.htm?sid=44dae65d3cf9593188ca59b002289d77
+#
+# this config file is for XC7VX1140T and XC7V2000T only.
+# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7vh870t.cfg or xilinx-xc7.cfg
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7v
+}
+
+#0x036D5093: XC7VX1140T
+#0x036By093: XC7V2000T
+#y = xx11 = 3, 7, B or F
+
+jtag newtap $_CHIPNAME tap -irlen 24 -ignore-version \
+	-expected-id 0x036B3093 -expected-id 0x036B7093 \
+	-expected-id 0x036BB093 -expected-id 0x036BF093 \
+	-expected-id 0x036D5093
+
+#CFG_OUT_SLR0 0x124924
+#CFG_IN_SLR0  0x164924
+#CFG_OUT_SLR1 0x904924
+#CFG_IN_SLR1  0x905924
+#CFG_OUT_SLR2 0x924124
+#CFG_IN_SLR2  0x924164
+#CFG_OUT_SLR3 0x924904
+#CFG_IN_SLR3  0x924905
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+# cfg_out cfg_in jprogb jstart jshutdown
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x2CB2CB 0x30C30C 0x34D34D
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7vh580t.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7vh580t.cfg
new file mode 100644
index 0000000..3748049
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7vh580t.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# https://bsdl.info/view.htm?sid=65c6b2cfe1467b4988ca59b002289d77
+#
+# this config file is for xc7vh580t only.
+# for other virtex-7 devices use xilinx-xc7vh870t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7vh580t
+}
+
+jtag newtap $_CHIPNAME tap -irlen 22 -ignore-version -expected-id 0x036D9093
+
+#CFG_OUT_SLR0 0x0492A0
+#CFG_IN_SLR0  0x0592A0
+#CFG_OUT_SLR1 0x2412A0
+#CFG_IN_SLR1  0x2416A0
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+# cfg_out cfg_in jprogb jstart jshutdown
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x0B2EA0 0x0C32A0 0x0D36A0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7vh870t.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7vh870t.cfg
new file mode 100644
index 0000000..25e2e63
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xc7vh870t.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# https://bsdl.info/view.htm?sid=d9ff0bb764df004588ca59b002289d77
+#
+# this config file is for xc7vh870t only.
+# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7vh870t
+}
+
+jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093
+
+#CFG_OUT_SLR0 0x0492A092A0
+#CFG_IN_SLR0  0x0592A092A0
+#CFG_OUT_SLR1 0x2412A092A0
+#CFG_IN_SLR1  0x2416A092A0
+#CFG_OUT_SLR2 0x2492A012A0
+#CFG_IN_SLR2  0x2492A016A0
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+# cfg_out cfg_in jprogb jstart jshutdown
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFFFFFF 0x3FFFFFFFFF 0x0B2EA02EA0 0x0C32A032A0 0x0D36A036A0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcf-p.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcf-p.cfg
new file mode 100644
index 0000000..7b6d384
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcf-p.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xcf
+}
+
+# IDs acquired from Xilinx's DS123.pdf
+# XCF08P 5057093
+# XCF16P 5058093
+# XCF32P 5059093
+# The 4 top bits (28:31) are the device revision. Ignore it.
+jtag newtap $_CHIPNAME flash -irlen 16 -ignore-version \
+	-expected-id 0x05057093 \
+	-expected-id 0x05058093 \
+	-expected-id 0x05059093
+
+target create xcf.flash testee -chain-position $_CHIPNAME.flash
+flash bank XCF_P xcf 0 0 0 0 xcf.flash
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcf-s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcf-s.cfg
new file mode 100644
index 0000000..417ecff
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcf-s.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xcf
+}
+
+# IDs acquired from Xilinx's DS123.pdf
+# XCF01S 5044093
+# XCF02S 5045093
+# XCF04S 5046093
+# The 4 top bits (28:31) are the device revision. Ignore it.
+jtag newtap $_CHIPNAME flash -irlen 8 -ignore-version \
+	-expected-id 0x05044093 \
+	-expected-id 0x05045093 \
+	-expected-id 0x05046093
+
+target create xcf.flash testee -chain-position $_CHIPNAME.flash
+flash bank XCF_S xcf 0 0 0 0 xcf.flash
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcr3256.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcr3256.cfg
new file mode 100644
index 0000000..4668e54
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcr3256.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#xilinx coolrunner xcr3256
+#simple device - just configure a tap
+jtag newtap xcr tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id  0x0494c093
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcu.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcu.cfg
new file mode 100644
index 0000000..63a67da
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpld/xilinx-xcu.cfg
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx Ultrascale (Kintex, Virtex, Zynq)
+# https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xcu
+}
+
+# The various chips in the Ultrascale family have different IR length.
+# Set $CHIP before including this file to determine the device.
+array set _XCU_DATA {
+	XCKU025         {0x03824093  6}
+	XCKU035         {0x03823093  6}
+	XCKU040         {0x03822093  6}
+	XCKU060         {0x03919093  6}
+	XCKU060_CIV     {0x0381b093  6}
+	XCKU095         {0x03844093  6}
+	XCKU095_CIV     {0x03845093  6}
+	XCKU3P          {0x04A63093  6}
+	XCKU5P          {0x04A62093  6}
+	XCKU9P          {0x0484A093  6}
+	XCKU11P         {0x04A4E093  6}
+	XCKU11P_CIV     {0x04A51093  6}
+	XCKU13P         {0x04A52093  6}
+	XCKU15P         {0x04A56093  6}
+	XCKU15P_CIV     {0x04A59093  6}
+	XCVU065         {0x03939093  6}
+	XCVU065_CIV     {0x0393b093  6}
+	XCVU080         {0x03843093  6}
+	XCVU080_CIV     {0x03845093  6}
+	XCVU095         {0x03842093  6}
+	XCVU2P          {0x04aea093  6}
+	XCVU3P          {0x04B39093  6}
+	XCVU3P_CIV      {0x04b3d093  6}
+	XCAU10P         {0x04AC4033  6}
+	XCAU10P_FFVB676 {0x04AC4093  6}
+	XCAU15P         {0x04AC2033  6}
+	XCAU15P_FFVB676 {0x04AC2093  6}
+	XCAU20P         {0x04A65093  6}
+	XCAU25P         {0x04A64093  6}
+	XCKU5P_CIV      {0x04A64093  6}
+	XCKU19P         {0x04ACF093  6}
+	XCKU19P_CIV     {0x04AD3093  6}
+	XCKU085         {0x0380F093 12}
+	XCKU115         {0x0390D093 12}
+	XCVU125         {0x0392D093 12}
+	XCVU125_CIV     {0x0392f093 12}
+	XCVU5P          {0x04B2B093 12}
+	XCVU5P_CIV      {0x04b2f093 12}
+	XCVU7P          {0x04B29093 12}
+	XCVU7P_CIV      {0x04b2d093 12}
+	XCVU160         {0x03933093 18}
+	XCVU190         {0x03931093 18}
+	XCVU440         {0x0396D093 18}
+	XCVU440_CIV     {0x0396f093 18}
+	XCVU9P          {0x04B31093 18}
+	XCVU9P_CIV      {0x04b35093 18}
+	XCVU11P         {0x04B49093 18}
+	XCVU11P_CIV     {0x04b4f093 18}
+	XCU200_FSGD2104 {0x04b37093 18}
+	XCU250          {0x04b57093 24}
+	XCVU13P         {0x04B51093 24}
+	XCVU13P_CIV     {0x04b55093 24}
+	XCVU15P         {0x04ba3093 24}
+	XCVU19P         {0x04ba1093 24}
+	XCVU19P_CIV     {0x04ba5093 24}
+}
+
+if { ![info exists CHIP] } {
+	error "set CHIP to one of "[concat [array names _XCU_DATA]]
+}
+
+if { ![llength [array names _XCU_DATA $CHIP]] } {
+	error "unknown CHIP: "$CHIP
+}
+
+set _EXPID [lindex $_XCU_DATA($CHIP) 0]
+set _IRLEN [lindex $_XCU_DATA($CHIP) 1]
+
+# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
+jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+
+# set the correct instruction codes for jtag hub and
+# at least the right code for jprogb, jstart and jshutdown for SSI devices
+if { $_IRLEN == 6 } {
+	virtex2 set_user_codes $_CHIPNAME.pld 0x2 0x3 0x22 0x23
+} elseif {$_IRLEN == 12 } {
+	puts "loading bitstream through jtag will not work, but reprogram (refresh)"
+	virtex2 set_instr_codes $_CHIPNAME.pld 0x905 0x904 0x2cb 0x30c 0x34d
+	virtex2 set_user_codes $_CHIPNAME.pld 0x0a4 0x0e4 0x8a4 0x8e4
+} elseif {$_IRLEN == 18 } {
+	puts "loading bitstream through jtag will not work, but reprogram (refresh)"
+	virtex2 set_instr_codes $_CHIPNAME.pld 0x24905 0x24904 0x0b2cb 0x0c30c 0x0d34d
+	virtex2 set_user_codes $_CHIPNAME.pld 0x000a4 0x000e4 0x008a4 0x008e4
+} else {
+	puts "loading bitstream through jtag will not work, but reprogram (refresh)"
+	virtex2 set_instr_codes $_CHIPNAME.pld 0x924905 0x924904 0x2cb2cb 0x30c30c 0x34d34d
+	virtex2 set_user_codes $_CHIPNAME.pld 0x0a4924 0x0e4924 0x8a4924 0x8e4924
+}
+
+set XCU_JSHUTDOWN 0x0d
+set XCU_JPROGRAM 0x0b
+set XCU_JSTART 0x0c
+set XCU_BYPASS 0x3f
+
+proc xcu_program {tap} {
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xcu_program'"
+	global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS
+	irscan $tap $XCU_JSHUTDOWN
+	irscan $tap $XCU_JPROGRAM
+	runtest 60000
+	#JSTART prevents this from working...
+	#irscan $tap $XCU_JSTART
+	runtest 2000
+	irscan $tap $XCU_BYPASS
+	runtest 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/common.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/common.tcl
new file mode 100644
index 0000000..e0de70b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/common.tcl
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+# Things common to all ARCs
+
+# It is assumed that target is already halted.
+proc arc_common_reset { {target ""} } {
+        if { $target != "" } {
+                targets $target
+        }
+
+        halt
+
+        # 1. Interrupts are disabled (STATUS32.IE)
+        # 2. The status register flags are cleared.
+        # All fields, except the H bit, are set to 0 when the processor is Reset.
+
+        arc jtag set-aux-reg 0xA 0x1
+
+        # 3. The loop count, loop start, and loop end registers are cleared.
+        arc jtag set-core-reg 60 0
+        arc jtag set-aux-reg 0x2 0
+        arc jtag set-aux-reg 0x3 0
+
+        # Program execution begins at the address referenced by the four byte reset
+        # vector located at the interrupt vector base address, which is the first
+        # entry (offset 0x00) in the vector table.
+        set int_vector_base [arc jtag get-aux-reg 0x25]
+        set start_pc [read_memory $int_vector_base 32 1]
+        arc jtag set-aux-reg 0x6 $start_pc
+
+        # It is OK to do uncached writes - register cache will be invalidated by
+        # the reset_assert() function.
+}
+
+# vim:expandtab:
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/em.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/em.tcl
new file mode 100644
index 0000000..13c5b43
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/em.tcl
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+source [find cpu/arc/v2.tcl]
+
+proc arc_em_examine_target { {target ""} } {
+	# Will set current target
+	arc_v2_examine_target $target
+}
+
+proc arc_em_init_regs { } {
+	arc_v2_init_regs
+
+	[target current] configure \
+		-event examine-end "arc_em_examine_target [target current]"
+}
+
+# Scripts in "target" folder should call this function instead of direct
+# invocation of arc_common_reset.
+proc arc_em_reset { {target ""} } {
+	arc_v2_reset $target
+
+	# Set DEBUG.ED bit to enable clock in actionpoint module.
+	# This is specific to ARC EM.
+	set debug [arc jtag get-aux-reg 5]
+	if { !($debug & (1 << 20)) } {
+		arc jtag set-aux-reg 5 [expr {$debug | (1 << 20)}]
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/hs.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/hs.tcl
new file mode 100644
index 0000000..28e04f9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/hs.tcl
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+source [find cpu/arc/v2.tcl]
+
+proc arc_hs_examine_target { target } {
+	# Will set current target for us.
+	arc_v2_examine_target $target
+}
+
+proc arc_hs_init_regs { } {
+	arc_v2_init_regs
+
+	[target current] configure \
+		-event examine-end "arc_hs_examine_target [target current]"
+}
+
+# Scripts in "target" folder should call this function instead of direct
+# invocation of arc_common_reset.
+proc arc_hs_reset { {target ""} } {
+	arc_v2_reset $target
+
+	# Invalidate L2 cache if there is one.
+	set l2_config [$target arc jtag get-aux-reg 0x901]
+	# Will return 0, if cache is not present and register doesn't exist.
+	set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+	if { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } {
+		puts "L2 cache is present and not disabled"
+
+		# Wait until BUSY bit is 0.
+		puts "Invalidating L2 cache..."
+		$target arc jtag set-aux-reg 0x905 1
+		# Dummy read of SLC_AUX_CACHE_CTRL bit, as described in:
+		# https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854
+		set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+		set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+		while { ($l2_ctrl & 0x100) != 0 } {
+			set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+		}
+
+		# Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate
+		# operation already flushed everything.
+		if { ($l2_ctrl & 0x40) == 0 } {
+			puts "Flushing L2 cache..."
+			$target arc jtag set-aux-reg 0x904 1
+			set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+			set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+			while { [expr {$l2_ctrl & 0x100}] != 0 } {
+				set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+			}
+		}
+
+		puts "L2 cache has been flushed and invalidated."
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/v2.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/v2.tcl
new file mode 100644
index 0000000..b24a67d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arc/v2.tcl
@@ -0,0 +1,346 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+source [find cpu/arc/common.tcl]
+
+# Currently 'examine_target' can only read JTAG registers and set properties -
+# but it shouldn't write any of registers - writes will be cached, but cache
+# will be invalidated before flushing after examine_target, and changes will be
+# lost.  Perhaps that would be fixed later - perhaps writes shouldn't be cached
+# after all.  But if write to register is really needed from TCL - then it
+# should be done via "arc jtag" for now.
+proc arc_v2_examine_target { {target ""} } {
+	# Set current target, because OpenOCD event handlers don't do this for us.
+	if { $target != "" } {
+		targets $target
+	}
+
+	# Those registers always exist. DEBUG and DEBUGI are formally optional,
+	# however they come with JTAG interface, and so far there is no way
+	# OpenOCD can communicate with target without JTAG interface.
+	arc set-reg-exists identity pc status32 bta debug lp_start lp_end \
+		eret erbta erstatus ecr efa
+
+	# 32 core registers
+	arc set-reg-exists \
+		r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10 r11 r12 \
+		r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 \
+		gp fp sp ilink r30 blink lp_count pcl
+
+	# Actionpoints
+	if { [arc get-reg-field ap_build version] == 5 } {
+		set ap_build_type [arc get-reg-field ap_build type]
+		# AP_BUILD.TYPE > 0b0110 is reserved in current ISA.
+		# Current ISA supports up to 8 actionpoints.
+		if { $ap_build_type < 8 } {
+			# Two LSB bits of AP_BUILD.TYPE define amount of actionpoints:
+			# 0b00 - 2 actionpoints
+			# 0b01 - 4 actionpoints
+			# 0b10 - 8 actionpoints
+			# 0b11 - reserved.
+			set ap_num [expr {0x2 << ($ap_build_type & 3)}]
+			# Expression on top may produce 16 action points - which is a
+			# reserved value for now.
+			if { $ap_num < 16 } {
+				# Enable actionpoint registers
+				for {set i 0} {$i < $ap_num} {incr i} {
+					arc set-reg-exists ap_amv$i ap_amm$i ap_ac$i
+				}
+
+				# Set amount of actionpoints
+				arc num-actionpoints $ap_num
+			}
+		}
+	}
+
+	# DCCM
+	set dccm_version [arc get-reg-field dccm_build version]
+	if { $dccm_version == 3 || $dccm_version == 4 } {
+		arc set-reg-exists aux_dccm
+	}
+
+	# ICCM
+	if { [arc get-reg-field iccm_build version] == 4 } {
+		arc set-reg-exists aux_iccm
+	}
+
+	# MPU
+	if { [arc get-reg-field mpu_build version] >= 2 &&
+		 [arc get-reg-field mpu_build version] <= 4 } {
+		arc set-reg-exists mpu_en mpu_ecr
+		set mpu_regions [arc get-reg-field mpu_build regions]
+		for {set i 0} {$i < $mpu_regions} {incr i} {
+			arc set-reg-exists mpu_rdp$i mpu_rdb$i
+		}
+
+		# Secure MPU
+		if { [arc get-reg-field mpu_build version] == 4 } {
+			arc set-reg-exists mpu_index mpu_rstart mpu_rend mpu_rper
+		}
+	}
+}
+
+proc arc_v2_init_regs { } {
+	# XML features
+	set core_feature "org.gnu.gdb.arc.core.v2"
+	set aux_min_feature "org.gnu.gdb.arc.aux-minimal"
+	set aux_other_feature "org.gnu.gdb.arc.aux-other"
+
+	# Describe types
+	# Types are sorted alphabetically according to their name.
+	arc add-reg-type-struct -name ap_build_t -bitfield version 0 7 \
+		-bitfield type 8 11
+	arc add-reg-type-struct -name ap_control_t -bitfield at 0 3 -bitfield tt 4 5 \
+		-bitfield m 6 6 -bitfield p 7 7 -bitfield aa 8 8 -bitfield q 9 9
+	# Cycles field added in version 4.
+	arc add-reg-type-struct -name dccm_build_t -bitfield version 0 7 \
+		-bitfield size0 8 11 -bitfield size1 12 15 -bitfield cycles 17 19
+
+	arc add-reg-type-struct -name debug_t \
+		-bitfield fh 1 1   -bitfield ah 2 2   -bitfield asr 3 10 \
+		-bitfield is 11 11 -bitfield ep 19 19 -bitfield ed 20 20 \
+		-bitfield eh 21 21 -bitfield ra 22 22 -bitfield zz 23 23 \
+		-bitfield sm 24 26 -bitfield ub 28 28 -bitfield bh 29 29 \
+		-bitfield sh 30 30 -bitfield ld 31 31
+
+	arc add-reg-type-struct -name ecr_t \
+		-bitfield parameter 0 7 \
+		-bitfield cause 8 15 \
+		-bitfield vector 16 23 \
+		-bitfield U 30 30 \
+		-bitfield P 31 31
+	arc add-reg-type-struct -name iccm_build_t -bitfield version 0 7 \
+		-bitfield iccm0_size0  8 11 -bitfield iccm1_size0 12 15 \
+		-bitfield iccm0_size1 16 19 -bitfield iccm1_size1 20 23
+	arc add-reg-type-struct -name identity_t \
+		-bitfield arcver 0 7 -bitfield arcnum 8 15 -bitfield chipid 16 31
+	arc add-reg-type-struct -name isa_config_t -bitfield version 0 7 \
+		-bitfield pc_size 8 11 -bitfield lpc_size 12 15 -bitfield addr_size 16 19 \
+		-bitfield b 20 20 -bitfield a 21 21 -bitfield n 22 22 -bitfield l 23 23 \
+		-bitfield c 24 27 -bitfield d 28 31
+	arc add-reg-type-struct -name mpu_build_t -bitfield version 0 7 \
+		-bitfield regions 8 15 \
+		-bitfield s 16 16 \
+		-bitfield i 17 17
+	arc add-reg-type-struct -name mpu_ecr_t \
+		-bitfield MR 0 7 \
+		-bitfield VT 8 9 \
+		-bitfield EC_CODE 16 31
+	arc add-reg-type-struct -name mpu_en_t \
+		-bitfield UE  3  3 -bitfield UW   4  4 -bitfield UR 5 5 \
+		-bitfield KE  6  6 -bitfield KW   7  7 -bitfield KR 8 8 \
+		-bitfield S  15 15 -bitfield SID 16 23 \
+		-bitfield EN 30 30
+	arc add-reg-type-struct -name mpu_index_t \
+		-bitfield I 0 3 -bitfield M 30 30 -bitfield D 31 31
+	arc add-reg-type-struct -name mpu_rper_t \
+		-bitfield V 0 0 \
+		-bitfield UE 3 3 -bitfield UW 4 4 -bitfield UR 5 5 \
+		-bitfield KE 6 6 -bitfield KW 7 7 -bitfield KR 8 8 \
+		-bitfield S 15 15 -bitfield SID 16 23
+	arc add-reg-type-flags -name status32_t \
+		-flag   H  0 -flag E0   1 -flag E1   2 -flag E2  3 \
+		-flag  E3  4 -flag AE   5 -flag DE   6 -flag  U  7 \
+		-flag   V  8 -flag  C   9 -flag  N  10 -flag  Z 11 \
+		-flag   L 12 -flag DZ  13 -flag SC  14 -flag ES 15 \
+		-flag RB0 16 -flag RB1 17 -flag RB2 18 \
+		-flag  AD 19 -flag US  20 -flag IE  31
+
+	# Core registers
+	set core_regs {
+		r0       0  uint32
+		r1       1  uint32
+		r2       2  uint32
+		r3       3  uint32
+		r4       4  uint32
+		r5       5  uint32
+		r6       6  uint32
+		r7       7  uint32
+		r8       8  uint32
+		r9       9  uint32
+		r10      10 uint32
+		r11      11 uint32
+		r12      12 uint32
+		r13      13 uint32
+		r14      14 uint32
+		r15      15 uint32
+		r16      16 uint32
+		r17      17 uint32
+		r18      18 uint32
+		r19      19 uint32
+		r20      20 uint32
+		r21      21 uint32
+		r22      22 uint32
+		r23      23 uint32
+		r24      24 uint32
+		r25      25 uint32
+		gp       26 data_ptr
+		fp       27 data_ptr
+		sp       28 data_ptr
+		ilink    29 code_ptr
+		r30      30 uint32
+		blink    31 code_ptr
+		r32      32 uint32
+		r33      33 uint32
+		r34      34 uint32
+		r35      35 uint32
+		r36      36 uint32
+		r37      37 uint32
+		r38      38 uint32
+		r39      39 uint32
+		r40      40 uint32
+		r41      41 uint32
+		r42      42 uint32
+		r43      43 uint32
+		r44      44 uint32
+		r45      45 uint32
+		r46      46 uint32
+		r47      47 uint32
+		r48      48 uint32
+		r49      49 uint32
+		r50      50 uint32
+		r51      51 uint32
+		r52      52 uint32
+		r53      53 uint32
+		r54      54 uint32
+		r55      55 uint32
+		r56      56 uint32
+		r57      57 uint32
+		accl     58 uint32
+		acch     59 uint32
+		lp_count 60 uint32
+		limm     61 uint32
+		reserved 62 uint32
+		pcl      63 code_ptr
+	}
+	foreach {reg count type} $core_regs {
+		arc add-reg -name $reg -num $count -core -type $type -g \
+			-feature $core_feature
+	}
+
+	# AUX min
+	set aux_min {
+		0x6 pc       code_ptr
+		0x2 lp_start code_ptr
+		0x3 lp_end   code_ptr
+		0xA status32 status32_t
+	}
+	foreach {num name type} $aux_min {
+		arc add-reg -name $name -num $num -type $type -feature $aux_min_feature -g
+	}
+
+	# AUX other
+	set aux_other {
+		0x004 identity	identity_t
+		0x005 debug		debug_t
+		0x018 aux_dccm	int
+		0x208 aux_iccm	int
+
+		0x220 ap_amv0	uint32
+		0x221 ap_amm0	uint32
+		0x222 ap_ac0	ap_control_t
+		0x223 ap_amv1	uint32
+		0x224 ap_amm1	uint32
+		0x225 ap_ac1	ap_control_t
+		0x226 ap_amv2	uint32
+		0x227 ap_amm2	uint32
+		0x228 ap_ac2	ap_control_t
+		0x229 ap_amv3	uint32
+		0x22A ap_amm3	uint32
+		0x22B ap_ac3	ap_control_t
+		0x22C ap_amv4	uint32
+		0x22D ap_amm4	uint32
+		0x22E ap_ac4	ap_control_t
+		0x22F ap_amv5	uint32
+		0x230 ap_amm5	uint32
+		0x231 ap_ac5	ap_control_t
+		0x232 ap_amv6	uint32
+		0x233 ap_amm6	uint32
+		0x234 ap_ac6	ap_control_t
+		0x235 ap_amv7	uint32
+		0x236 ap_amm7	uint32
+		0x237 ap_ac7	ap_control_t
+
+		0x400 eret		code_ptr
+		0x401 erbta		code_ptr
+		0x402 erstatus	status32_t
+		0x403 ecr		ecr_t
+		0x404 efa		data_ptr
+
+		0x409 mpu_en	mpu_en_t
+
+		0x412 bta		code_ptr
+
+		0x420 mpu_ecr	mpu_ecr_t
+		0x422 mpu_rdb0	int
+		0x423 mpu_rdp0	int
+		0x424 mpu_rdb1	int
+		0x425 mpu_rdp1	int
+		0x426 mpu_rdb2	int
+		0x427 mpu_rdp2	int
+		0x428 mpu_rdb3	int
+		0x429 mpu_rdp3	int
+		0x42A mpu_rdb4	int
+		0x42B mpu_rdp4	int
+		0x42C mpu_rdb5	int
+		0x42D mpu_rdp5	int
+		0x42E mpu_rdb6	int
+		0x42F mpu_rdp6	int
+		0x430 mpu_rdb7	int
+		0x431 mpu_rdp7	int
+		0x432 mpu_rdb8	int
+		0x433 mpu_rdp8	int
+		0x434 mpu_rdb9	int
+		0x435 mpu_rdp9	int
+		0x436 mpu_rdb10	int
+		0x437 mpu_rdp10	int
+		0x438 mpu_rdb11	int
+		0x439 mpu_rdp11	int
+		0x43A mpu_rdb12	int
+		0x43B mpu_rdp12	int
+		0x43C mpu_rdb13	int
+		0x43D mpu_rdp13	int
+		0x43E mpu_rdb14	int
+		0x43F mpu_rdp14	int
+		0x440 mpu_rdb15	int
+		0x441 mpu_rdp15	int
+		0x448 mpu_index	mpu_index_t
+		0x449 mpu_rstart uint32
+		0x44A mpu_rend	uint32
+		0x44B mpu_rper	mpu_rper_t
+		0x44C mpu_probe uint32
+	}
+	foreach {num name type} $aux_other {
+		arc add-reg -name $name -num $num -type $type -feature $aux_other_feature
+	}
+
+	# AUX BCR
+	set bcr {
+		0x6D mpu_build
+		0x74 dccm_build
+		0x76 ap_build
+		0x78 iccm_build
+		0xC1 isa_config
+	}
+	foreach {num reg} $bcr {
+		arc add-reg -name $reg -num $num -type ${reg}_t -bcr -feature $aux_other_feature
+	}
+
+	[target current] configure \
+		-event examine-end "arc_v2_examine_target [target current]"
+}
+
+proc arc_v2_reset { {target ""} } {
+	arc_common_reset $target
+
+	# Disable all actionpoints.  Cannot write via regcache yet, because it will
+	# not be flushed and all changes to registers will get lost.  Therefore has
+	# to write directly via JTAG layer...
+	set num_ap [arc num-actionpoints]
+	for {set i 0} {$i < $num_ap} {incr i} {
+		arc jtag set-aux-reg [expr {0x222 + $i * 3}] 0
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm7tdmi.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm7tdmi.tcl
new file mode 100644
index 0000000..e407a23
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm7tdmi.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   arm7tdmi
+set CPU_ARCH   armv4t
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm920.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm920.tcl
new file mode 100644
index 0000000..1c5a8ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm920.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   arm920
+set CPU_ARCH   armv4t
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm946.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm946.tcl
new file mode 100644
index 0000000..602d4d7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm946.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   arm946
+set CPU_ARCH   armv5te
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm966.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm966.tcl
new file mode 100644
index 0000000..0e64312
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/arm966.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   arm966
+set CPU_ARCH   armv5te
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/cortex_m3.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/cortex_m3.tcl
new file mode 100644
index 0000000..0791664
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/arm/cortex_m3.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   cortex_m3
+set CPU_ARCH   armv7
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/nuclei/cpuinfo.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/nuclei/cpuinfo.tcl
new file mode 100644
index 0000000..db69983
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/cpu/nuclei/cpuinfo.tcl
@@ -0,0 +1,376 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc get_register {reg} {
+	set reg_info [get_reg $reg]
+	return [lindex $reg_info 1]
+}
+
+proc get_memory {addr} {
+	return [read_memory $addr 32 1]
+}
+
+proc extract_field {val which} {
+	set part_a [expr $val&$which]
+	set part_b [expr $which&[expr ~[expr $which-1]]]
+	return [expr $part_a/$part_b]
+}
+
+proc pow_of_two {n} {
+	return [expr 1<<$n]
+}
+
+proc linesz {n} {
+	switch $n {
+		"0" {
+			return 0
+		}
+		default {
+			pow_of_two [expr $n-1]
+		}
+	}
+}
+
+proc show_safety_mechanism {safetyMode} {
+	switch $safetyMode {
+		"0" {
+			puts -nonewline " No-Safety-Mechanism"
+		}
+		"1" {
+			puts -nonewline " Lockstep"
+		}
+		"2" {
+			puts -nonewline " Lockstep+SplitMode"
+		}
+		"3" {
+			puts -nonewline " ASIL-B"
+		}
+	}
+}
+
+proc show_vpu_degree {degree} {
+	switch $degree {
+		"0" {
+			puts -nonewline " DLEN=VLEN/2"
+		}
+		"1" {
+			puts -nonewline " DLEN=VLEN"
+		}
+	}
+}
+
+proc format_display {bytes} {
+	if [expr $bytes/[expr 1024*1024*1024]] {
+		puts -nonewline [format " %dGB" [expr $bytes/[expr 1024*1024*1024]]]
+	} elseif [expr $bytes/[expr 1024*1024]] {
+		puts -nonewline [format " %dMB" [expr $bytes/[expr 1024*1024]]]
+	} elseif [expr $bytes/[expr 1024]] {
+		puts -nonewline [format " %dKB" [expr $bytes/[expr 1024]]]
+	} else {
+		puts -nonewline [format " %dByte" $bytes]
+	}
+}
+
+proc show_cache_info {set way lsize ecc} {
+	format_display [expr $set*$way*$lsize]
+	puts -nonewline [format "(set=%d," $set]
+	puts -nonewline [format "way=%d," $way]
+	puts -nonewline [format "lsize=%d," $lsize]
+	puts -nonewline [format "ecc=%d)" [expr !!$ecc]]
+}
+
+proc nuclei_cpuinfo {} {
+
+	set riscv_info [riscv info]
+	dict for {key value} $riscv_info {
+		if {$key == "hart.xlen"} {
+			set xlen $value
+		}
+	}
+
+	puts "-----Nuclei RISC-V CPU Configuration Information-----"
+
+	set marchid [get_register marchid]
+	if {$marchid != 0} {
+		puts [format "         MARCHID: %lx" $marchid]
+	}
+
+	set mimpid [get_register mimpid]
+	if {$mimpid != 0} {
+		puts [format "          MIMPID: %lx" $mimpid]
+	}
+
+	set misa [get_register misa]
+	if {$misa != 0} {
+		puts -nonewline "             ISA:"
+		if {$xlen == 32} {
+			puts -nonewline " RV32"
+		} else {
+			puts -nonewline " RV64"
+		}
+		for {set i 0}  {$i < 26} {incr i} {
+			if [expr 1&[expr $misa>>$i]] {
+				if {88 == [expr 65+$i]} {
+					puts -nonewline " NICE"
+				} else {
+					puts -nonewline [format " %c" [expr 65+$i]]
+				}
+			}
+		}
+	}
+
+	set mcfg_info [get_register mcfg_info]
+	if [expr $mcfg_info&[expr 1<<12]] {
+		puts -nonewline " Xxldspn1x"
+	}
+	if [expr $mcfg_info&[expr 1<<13]] {
+		puts -nonewline " Xxldspn2x"
+	}
+	if [expr $mcfg_info&[expr 1<<14]] {
+		puts -nonewline " Xxldspn3x"
+	}
+	if [expr $mcfg_info&[expr 1<<15]] {
+		puts -nonewline " Zc Xxlcz"
+	}
+	if [expr $mcfg_info&[expr 1<<19]] {
+		puts -nonewline " Smwg"
+	}
+	puts ""
+
+	if {$mcfg_info != 0} {
+		puts -nonewline "            MCFG:"
+		if [expr $mcfg_info&[expr 1<<0]] {
+			puts -nonewline " TEE"
+		}
+		if [expr $mcfg_info&[expr 1<<1]] {
+			puts -nonewline " ECC"
+		}
+		if [expr $mcfg_info&[expr 1<<2]] {
+			puts -nonewline " ECLIC"
+		}
+		if [expr $mcfg_info&[expr 1<<3]] {
+			puts -nonewline " PLIC"
+		}
+		if [expr $mcfg_info&[expr 1<<4]] {
+			puts -nonewline " FIO"
+		}
+		if [expr $mcfg_info&[expr 1<<5]] {
+			puts -nonewline " PPI"
+		}
+		if [expr $mcfg_info&[expr 1<<6]] {
+			puts -nonewline " NICE"
+		}
+		if [expr $mcfg_info&[expr 1<<7]] {
+			puts -nonewline " ILM"
+		}
+		if [expr $mcfg_info&[expr 1<<8]] {
+			puts -nonewline " DLM"
+		}
+		if [expr $mcfg_info&[expr 1<<9]] {
+			puts -nonewline " ICACHE"
+		}
+		if [expr $mcfg_info&[expr 1<<10]] {
+			puts -nonewline " DCACHE"
+		}
+		if [expr $mcfg_info&[expr 1<<11]] {
+			puts -nonewline " SMP"
+		}
+		if [expr $mcfg_info&[expr 1<<12]] {
+			puts -nonewline " DSP-N1"
+		}
+		if [expr $mcfg_info&[expr 1<<13]] {
+			puts -nonewline " DSP-N2"
+		}
+		if [expr $mcfg_info&[expr 1<<14]] {
+			puts -nonewline " DSP-N3"
+		}
+		if [expr $mcfg_info&[expr 1<<15]] {
+			puts -nonewline " ZC_XLCZ_EXT"
+		}
+		if [expr $mcfg_info&[expr 1<<16]] {
+			puts -nonewline " IREGION"
+		}
+		if [expr $mcfg_info&[expr 1<<19]] {
+			puts -nonewline " SEC_MODE"
+		}
+		if [expr $mcfg_info&[expr 1<<20]] {
+			puts -nonewline " ETRACE"
+		}
+		if [expr $mcfg_info&[expr 1<<23]] {
+			puts -nonewline " VNICE"
+		}
+		show_safety_mechanism [extract_field $mcfg_info [expr 0x3<<21]]
+		show_vpu_degree [extract_field $mcfg_info [expr 0x3<<17]]
+		puts ""
+
+		if [expr $mcfg_info&[expr 1<<7]] {
+			set micfg_info [get_register micfg_info]
+			if {$micfg_info != 0} {
+				puts -nonewline "             ILM:"
+				format_display [expr [pow_of_two [expr [extract_field $micfg_info [expr 0x1F<<16]]-1]]*256]
+				if [expr $micfg_info&[expr 1<<21]] {
+					puts -nonewline " execute-only"
+				}
+				if [expr $micfg_info&[expr 1<<22]] {
+					puts -nonewline " has-ecc"
+				}
+				puts ""
+			}
+		}
+
+		if [expr $mcfg_info&[expr 1<<8]] {
+			set mdcfg_info [get_register mdcfg_info]
+			if {$mdcfg_info != 0} {
+				puts -nonewline "             DLM:"
+				format_display [expr [pow_of_two [expr [extract_field $mdcfg_info [expr 0x1F<<16]]-1]]*256]
+				if [expr $mdcfg_info&[expr 1<<21]] {
+					puts -nonewline " has-ecc"
+				}
+				puts ""
+			}
+		}
+
+		if [expr $mcfg_info&[expr 1<<9]] {
+			set micfg_info [get_register micfg_info]
+			if {$micfg_info != 0} {
+				puts -nonewline "          ICACHE:"
+				show_cache_info [pow_of_two [expr [extract_field $micfg_info 0xF]+3]] \
+								[expr [extract_field $micfg_info [expr 7<<4]]+1] \
+								[pow_of_two [expr [extract_field $micfg_info [expr 7<<7]]+2]] \
+								[extract_field $mcfg_info [expr 0x1<<1]]
+				puts ""
+			}
+		}
+
+		if [expr $mcfg_info&[expr 1<<10]] {
+			set mdcfg_info [get_register mdcfg_info]
+			if {$mdcfg_info != 0} {
+				puts -nonewline "          DCACHE:"
+				show_cache_info [pow_of_two [expr [extract_field $mdcfg_info 15]+3]] \
+								[expr [extract_field $mdcfg_info [expr 7<<4]]+1] \
+								[pow_of_two [expr [extract_field $mdcfg_info [expr 7<<7]]+2]] \
+								[extract_field $mcfg_info [expr 0x1<<1]]
+				puts ""
+			}
+		}
+
+		if [expr $mcfg_info&[expr 1<<3]] {
+			set mtlbcfg_info [get_register mtlbcfg_info]
+			puts -nonewline "             TLB:"
+			puts -nonewline [format " MainTLB(set=%lu" [pow_of_two [expr [extract_field $mtlbcfg_info 0xF]+3]]]
+			puts -nonewline [format " way=%lu" [expr [extract_field $mtlbcfg_info [expr 0x7<<4]]+1]]
+			puts -nonewline [format " entry=%lu" [linesz [extract_field $mtlbcfg_info [expr 0x7<<7]]]]
+			puts -nonewline [format " ecc=%lu)" [extract_field $mtlbcfg_info [expr 0x1<<10]]]
+			puts -nonewline [format " ITLB(entry=%lu)" [linesz [extract_field $mtlbcfg_info [expr 0x7<<16]]]]
+			puts -nonewline [format " DTLB(entry=%lu)" [linesz [extract_field $mtlbcfg_info [expr 0x7<<19]]]]
+			puts ""
+		}
+
+		if [expr $mcfg_info&[expr 1<<16]] {
+			set mirgb_info [get_register mirgb_info]
+			puts -nonewline "         IREGION:"
+			set iregion_base [expr $mirgb_info&[expr ~0x3FF]]
+			puts -nonewline [format " 0x%lx" $iregion_base]
+			format_display [expr [pow_of_two [expr [extract_field $mirgb_info [expr 0x1F<<1]]-1]]*1024]
+			puts ""
+			puts "                  Unit        Size        Address"
+			puts [format "                  INFO        64KB        0x%lx" $iregion_base]
+			puts [format "                  DEBUG       64KB        0x%lx" [expr $iregion_base+0x10000]]
+			if [expr $mcfg_info&[expr 1<<2]] {
+				puts [format "                  ECLIC       64KB        0x%lx" [expr $iregion_base+0x20000]]
+			}
+			puts [format "                  TIMER       64KB        0x%lx" [expr $iregion_base+0x30000]]
+			if [expr $mcfg_info&[expr 1<<11]] {
+				puts [format "                  SMP         64KB        0x%lx" [expr $iregion_base+0x40000]]
+			}
+			set smp_cfg [get_memory [expr $iregion_base+0x40004]]
+			if [expr $mcfg_info&[expr 1<<2]] {
+				if {[extract_field $smp_cfg [expr 31<<1]] >= 2} {
+					puts [format "                  CIDU        64KB        0x%lx" [expr $iregion_base+0x50000]]
+				}
+			}
+			if [expr $mcfg_info&[expr 1<<3]] {
+				puts [format "                  PLIC        64MB        0x%lx" [expr $iregion_base+0x4000000]]
+			}
+
+			if [expr $mcfg_info&[expr 1<<11]] {
+				puts -nonewline "         SMP_CFG:"
+				puts -nonewline [format " CC_PRESENT=%ld" [extract_field $smp_cfg 0x1]]
+				puts -nonewline [format " SMP_CORE_NUM=%ld" [extract_field $smp_cfg [expr 0x3F<<1]]]
+				puts -nonewline [format " IOCP_NUM=%ld" [extract_field $smp_cfg [expr 0x3F<<7]]]
+				puts [format " PMON_NUM=%ld" [extract_field $smp_cfg [expr 0x3F<<13]]]
+			}
+
+			if [expr $mcfg_info&[expr 1<<2]] {
+				set clic_base [expr $iregion_base+0x20000]
+				set clic_cfg [expr $clic_base+0x0]
+				set clic_info [expr $clic_base+0x4]
+				set clic_mth [expr $clic_base+0x8]
+				set clic_cfg_value [get_memory $clic_cfg]
+				set clic_info_value [get_memory $clic_info]
+				set clic_mth_value [get_memory $clic_mth]
+				puts -nonewline "         ECLIC:"
+				puts -nonewline [format " VERSION=0x%x" [extract_field $clic_info_value [expr 0xFF<<13]]]
+				puts -nonewline [format " NUM_INTERRUPT=%x" [extract_field $clic_info_value [expr 0xFFF<<0]]]
+				puts -nonewline [format " CLICINTCTLBITS=%x" [extract_field $clic_info_value [expr 0xF<<21]]]
+				puts -nonewline [format " MTH=%x" [extract_field $clic_mth_value [expr 0xFF<<24]]]
+				puts [format " NLBITS=%x" [extract_field $clic_cfg_value [expr 0xF<<1]]]
+			}
+
+			if [expr $smp_cfg&1] {
+				puts -nonewline "         L2CACHE:"
+				set cc_cfg [get_memory [expr $iregion_base+0x40008]]
+				show_cache_info [pow_of_two [extract_field $cc_cfg 0xF]] \
+								[expr [extract_field $cc_cfg [expr 0xF<<4]]+1] \
+								[pow_of_two [expr [extract_field $cc_cfg [expr 0x7<<8]]+2]] \
+								[extract_field $cc_cfg [expr 0x1<<11]]
+				puts ""
+			}
+
+			puts "     INFO-Detail:"
+			set mpasize [get_memory $iregion_base]
+			puts [format "                  mpasize : %ld" $mpasize]
+			set cmo_info [get_memory [expr $iregion_base+4]]
+			if [expr $cmo_info&1] {
+				puts [format "                  cbozero : %dByte" \
+					[pow_of_two [expr [extract_field $cmo_info [expr 0xF<<6]]+2]]]
+				puts [format "                  cmo     : %dByte" \
+					[pow_of_two [expr [extract_field $cmo_info [expr 0xF<<2]]+2]]]
+				if [expr $cmo_info&2] {
+					puts "                  has_prefecth"
+				}
+			}
+			set mcppi_cfg_lo [get_memory [expr $iregion_base+0x80]]
+			set mcppi_cfg_hi [get_memory [expr $iregion_base+0x84]]
+			if [expr $mcppi_cfg_lo&1] {
+				if {$xlen == 32} {
+					puts -nonewline [format "                  cppi    : 0x%lx" \
+						[expr $mcppi_cfg_lo&[expr ~0x3FF]]]
+				} else {
+					puts -nonewline [format "                  cppi    : 0x%lx" \
+						[expr [expr $mcppi_cfg_hi<<32]|[expr $mcppi_cfg_lo&[expr ~0x3FF]]]]
+				}
+				format_display [expr [pow_of_two [expr [extract_field $mcppi_cfg_lo [expr 0x1F<<1]-1]]]*1024]
+				puts " "
+			}
+			puts ""
+		}
+
+		if [expr $mcfg_info&[expr 1<<4]] {
+			set mfiocfg_info [get_register mfiocfg_info]
+			puts -nonewline "             FIO:"
+			puts -nonewline [format " 0x%lx" [expr $mfiocfg_info&[expr ~0x3FF]]]
+			format_display [expr [pow_of_two [expr [extract_field $mfiocfg_info [expr 0x1F<<1]]-1]]*1024]
+			puts ""
+		}
+
+		if [expr $mcfg_info&[expr 1<<5]] {
+			set mppicfg_info [get_register mppicfg_info]
+			puts -nonewline "             PPI:"
+			puts -nonewline [format " 0x%lx" [expr $mppicfg_info&[expr ~0x3FF]]]
+			format_display [expr [pow_of_two [expr [extract_field $mppicfg_info [expr 0x1F<<1]]-1]]*1024]
+			puts ""
+		}
+	}
+
+	puts "----End of cpuinfo-----"
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-10m50.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-10m50.cfg
new file mode 100644
index 0000000..94228d2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-10m50.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# file altera-10m50.cfg replaced by altera-max10.cfg
+echo "DEPRECATED: use altera-max10.cfg instead of deprecated altera-10m50.cfg"
+
+#just to be backward compatible:
+#tap will be 10m50.tap instead of max10.tap:
+set CHIPNAME 10m50
+source [find cpld/altera-max10.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-arriaii.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-arriaii.cfg
new file mode 100644
index 0000000..9cf680d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-arriaii.cfg
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Arria II FPGA
+# Arria II Device Handbook
+# Table 11–2. 32-Bit IDCODE for Arria II Devices
+
+#GX:
+#EP2AGX45:  0x025120dd
+#EP2AGX65:  0x025020dd
+#EP2AGX95:  0x025130dd
+#EP2AGX125: 0x025030dd
+#EP2AGX190: 0x025140dd
+#EP2AGX260: 0x025040dd
+#EP2AGZ225: 0x024810dd
+#EP2AGZ300: 0x0240a0dd
+#EP2AGZ350: 0x024820dd
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME arriaii
+}
+
+array set _ARRIA_2_DATA {
+  0x025120dd {1227 1174 EP2AGX45}
+  0x025020dd {1227   -1 EP2AGX65}
+  0x025130dd {1467   -1 EP2AGX95}
+  0x025030dd {1467   -1 EP2AGX125}
+  0x025140dd {1971   -1 EP2AGX190}
+  0x025040dd {1971   -1 EP2AGX260}
+  0x024810dd {2274   -1 EP2AGZ225}
+  0x0240a0dd {2682   -1 EP2AGZ300}
+  0x024820dd {2682   -1 EP2AGZ350}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _ARRIA_2_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_ARRIA_2_DATA}"
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cyclone10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cyclone10.cfg
new file mode 100644
index 0000000..0898c74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cyclone10.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone 10 FPGA
+# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html
+# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cyclone10
+}
+
+array set _CYCLONE_10_DATA {
+  0x020f10dd { 603 226 10cl006_10cl010}
+  0x020f20dd {1080 409 10cl016}
+  0x020f30dd { 732 286 10cl025}
+  0x020f40dd {1632 604 10cl040}
+  0x020f50dd {1164 442 10cl055}
+  0x020f60dd {1314 502 10cl080}
+  0x020f70dd {1620 613 10cl120}
+  0x02e120dd {1339  -1 GX085}
+  0x02e320dd {1339  -1 GX105}
+  0x02e720dd {1339  -1 GX150}
+  0x02ef20dd {1339  -1 GX220}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_10_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclone10
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_10_DATA}"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cycloneiii.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cycloneiii.cfg
new file mode 100644
index 0000000..b0da418
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cycloneiii.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone III FPGA
+# see Cyclone III Device Handbook
+# Table 12-2: Device IDCODE for Cyclone III Device Family
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cycloneiii
+}
+
+array set _CYCLONE_3_DATA {
+  0x020f10dd { 603 226 EP3C5_EP3C10}
+  0x020f20dd {1080 409 EP3C16}
+  0x020f30dd { 732 286 EP3C25}
+  0x020f40dd {1632 604 EP3C40}
+  0x020f50dd {1164 442 EP3C55}
+  0x020f60dd {1314 502 EP3C80}
+  0x020f70dd {1620 613 EP3C120}
+  0x027010dd {1314 226 EP3CLS70}
+  0x027000dd {1314 226 EP3CLS100}
+  0x027030dd {1314 409 EP3CLS150}
+  0x027020dd {1314 409 EP3CLS200}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_3_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_3_DATA}"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cycloneiv.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cycloneiv.cfg
new file mode 100644
index 0000000..44eb89d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cycloneiv.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone IV FPGA
+# see Cyclone IV Device Handbook
+# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cycloneiv
+}
+
+array set _CYCLON_4_DATA {
+  0x020f10dd { 603  226 EP4CE6_EP4CE10}
+  0x020f20dd {1080  409 EP4CE15}
+  0x020f30dd { 732  286 EP4CE22}
+  0x020f40dd {1632  604 EP4CE30_EP4CE40}
+  0x020f50dd {1164  442 EP4CE55}
+  0x020f60dd {1314  502 EP4CE75}
+  0x020f70dd {1620  613 EP4CE115}
+  0x028010dd { 260  229 EP4CGX15}
+  0x028120dd { 494  463 EP4CGX22}
+  0x028020dd { 494  463 EP4CGX30}
+  0x028230dd {1006  943 EP4CGX30}
+  0x028130dd {1006  943 EP4CGX50}
+  0x028030dd {1006  943 EP4CGX75}
+  0x028140dd {1495 1438 EP4CGX110}
+  0x028040dd {1495 1438 EP4CGX150}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLON_4_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_4_DATA}"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cyclonev.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cyclonev.cfg
new file mode 100644
index 0000000..8d19cd8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-cyclonev.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone 5 FPGA
+# see Cyclone V Device Handbook
+# Table 9-1: IDCODE Information for Cyclone V Devices
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cyclonev
+}
+
+array set _CYCLONE_5_DATA {
+  0x02b150dd { 864 163 5CEA2}
+  0x02d020dd {1485  19 5CSEA6_5CSXC6_5CSTD6}
+  0x02b040dd {1728  -1 5CGXC9_5CGTD9}
+  0x02b050dd { 864 163 5CEA4}
+  0x02b030dd {1488  19 5CGXC7_5CGTD7}
+  0x02d120dd {1485  -1 5CSEA5_5CSXC5_5CSTD5}
+  0x02b220dd {1104  19 5CEA5}
+  0x02b020dd {1104  19 5CGXC5_5CGTD5}
+  0x02d010dd {1197  -1 5CSEA4_5CSXC4}
+  0x02b120dd {1104  19 5CGXC4}
+  0x02b140dd {1728  -1 5CEA9}
+  0x02b010dd { 720  19 5CGXC3}
+  0x02b130dd {1488  19 5CEA7}
+  0x02d110dd {1197  -1 5CSEA2_5CSXC2}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_5_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_5_DATA}"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-ep3c10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-ep3c10.cfg
new file mode 100644
index 0000000..d7a92d7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera-ep3c10.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# file altera-ep3c10.cfg replaced by altera-cycloneiii.cfg
+echo "DEPRECATED: use altera-cycloneiii.cfg instead of deprecated altera-ep3c10.cfg"
+
+#just to be backward compatible:
+#tap will be ep3c10.tap instead of cycloneiii.tap:
+set CHIPNAME ep3c10
+source [find fpga/altera-cycloneiii.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera_common_init.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera_common_init.cfg
new file mode 100644
index 0000000..683a844
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/altera_common_init.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc set_bscan_checkpos_on_setup {chipname data} {
+  set tapid_w_version [jtag cget $chipname.tap -idcode]
+  set version_mask 0x0fffffff
+  set tapid [format 0x%08x [expr {$tapid_w_version & $version_mask}]]
+  intel set_bscan $chipname.pld [lindex $data($tapid) 0]
+  intel set_check_pos $chipname.pld [lindex $data($tapid) 1]
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/efinix_titanium.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/efinix_titanium.cfg
new file mode 100644
index 0000000..3c2cdd7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/efinix_titanium.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# efinix titanium
+# https://www.efinixinc.com/docs/an048-jtag-bst-titanium-v1.0.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME titanium
+}
+
+jtag newtap $_CHIPNAME tap -irlen 5 -ignore-version \
+	-expected-id 0x10661A79 \
+	-expected-id 0x00360A79 \
+	-expected-id 0x10660A79 \
+	-expected-id 0x00681A79 \
+	-expected-id 0x00688A79 \
+	-expected-id 0x00682A79 \
+	-expected-id 0x0068CA79 \
+	-expected-id 0x00680A79 \
+	-expected-id 0x00684A79
+
+pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family titanium
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/efinix_trion.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/efinix_trion.cfg
new file mode 100644
index 0000000..1c789f5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/efinix_trion.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# efinix trion
+# https://www.efinixinc.com/docs/an021-jtag-bst-trion-v1.0.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME trion
+}
+
+jtag newtap $_CHIPNAME tap -irlen 4 -ignore-version \
+	-expected-id 0x00210A79 \
+	-expected-id 0x00240A79 \
+	-expected-id 0x00220A79
+
+pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family trion
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/gatemate.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/gatemate.cfg
new file mode 100644
index 0000000..e8f3382
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/gatemate.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# GateMateTM FPGA
+# https://www.colognechip.com/programmable-logic/gatemate/
+# https://colognechip.com/docs/ds1001-gatemate1-datasheet-latest.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME gatemate
+}
+
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x20000001
+
+pld create $_CHIPNAME.pld gatemate -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/gowin_gw1n.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/gowin_gw1n.cfg
new file mode 100644
index 0000000..5e85066
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/gowin_gw1n.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Gowin FPGA IDCODEs
+# from JTAG Programming and Configuration Guide
+# http://cdn.gowinsemi.com.cn/TN653E.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME gw1n
+}
+
+jtag newtap $_CHIPNAME tap -irlen 8 -ignore-version \
+	-expected-id 0x0900281B \
+	-expected-id 0x0900381B \
+	-expected-id 0x0100681B \
+	-expected-id 0x0300081B \
+	-expected-id 0x0300181B \
+	-expected-id 0x0120681B \
+	-expected-id 0x0100381B \
+	-expected-id 0x1100381B \
+	-expected-id 0x0100981B \
+	-expected-id 0x1100581B \
+	-expected-id 0x1100481B \
+	-expected-id 0x0100181B \
+	-expected-id 0x1100181B \
+	-expected-id 0x0100481B
+
+pld create $_CHIPNAME.pld gowin -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_certus.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_certus.cfg
new file mode 100644
index 0000000..9ddb7d8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_certus.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME certus
+}
+
+# Lattice Certus
+#
+# Certus NX LFD2NX-17     0x310f0043
+# Certus NX LFD2NX-40     0x310f1043
+
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+	-expected-id 0x310F1043 -expected-id 0x310F0043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_certuspro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_certuspro.cfg
new file mode 100644
index 0000000..acaaa57
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_certuspro.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME certuspro
+}
+
+# Lattice CertusPro
+#
+# 0x010f4043 - LFCPNX-100
+# 0x     043 - LFCPNX-50
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+	-expected-id 0x010f4043
+#    -expected-id 0x01112043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_ecp2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_ecp2.cfg
new file mode 100644
index 0000000..5b01787
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_ecp2.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ecp2
+}
+
+# Lattice ECP2 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP2M
+#
+# LFE2M20E: 0x01279043
+# LFE2M35E: 0x0127A043
+# LFE2M50E: 0x0127B043
+# LFE2M70E: 0x0127C043
+# LFE2M100E: 0x0127D043
+# LFEC2_6E: 0x01270043
+# LFEC2_12E: 0x01271043
+# LFEC2_20E: 0x01272043
+# LFEC2_35E: 0x01274043
+# LFEC2_50E: 0x01273043
+# LFEC2_70E: 0x01275043
+
+jtag newtap $_CHIPNAME tap -irlen 8  \
+	-expected-id 0x01279043 -expected-id 0x0127A043 -expected-id 0x0127B043 \
+	-expected-id 0x0127C043 -expected-id 0x0127D043 -expected-id 0x01270043 \
+	-expected-id 0x01271043 -expected-id 0x01272043 -expected-id 0x01274043 \
+	-expected-id 0x01273043 -expected-id 0x01275043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_ecp3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_ecp3.cfg
new file mode 100644
index 0000000..21c8ffa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_ecp3.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ecp3
+}
+
+# Lattice ECP3 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP3
+#
+# LFE3_17:  0x01010043
+# LFE3_35:  0x01012043
+# LFE3_95:  0x01014043 and LFE3_70
+# LFE3_150: 0x01015043
+
+jtag newtap $_CHIPNAME tap -irlen 8  \
+	-expected-id 0x01010043 -expected-id 0x01012043 \
+	-expected-id 0x01014043 -expected-id 0x01015043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_ecp5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_ecp5.cfg
new file mode 100644
index 0000000..cdc63f0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_ecp5.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ecp5
+}
+
+# Lattice ECP5 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/ECP5
+#
+# 0x01111043 - LAE5UM_25F/LFE5UM_25F
+# 0x01112043 - LAE5UM_45F/LFE5UM_45F
+# 0x01113043 - LAE5UM_85F/LFE5UM_85
+# 0x21111043 - LFE5U_12F
+# 0x41111043 - LFE5U_25F
+# 0x41112043 - LFE5U_45F
+# 0x41113043 - LFE5U_85F
+# 0x81111043 - LFE5UM5G-25
+# 0x81112043 - LFE5UM5G-45
+# 0x81113043 - LFE5UM5G-85
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+	-expected-id 0x01111043 -expected-id 0x01112043 -expected-id 0x01113043 \
+	-expected-id 0x21111043 -expected-id 0x41111043 -expected-id 0x41112043 \
+	-expected-id 0x41113043 -expected-id 0x81111043 -expected-id 0x81112043 \
+	-expected-id 0x81113043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_machxo3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_machxo3.cfg
new file mode 100644
index 0000000..37fa054
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/lattice_machxo3.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME machxo3
+}
+
+# Lattice MachXO3 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/MachXO3
+#
+# 0x412b2043 - LCMXO3L_1300E_XXUWG36/XXMG121
+# 0x412b3043 - LCMXO3L_2100E_XXMG121/XXMG256/XXUWG49
+# 0x412b4043 - LCMXO3L_4300E_XXMG121/XXMG324/XXUWG81
+# 0x412b5043 - LCMXO3L_6900E_XXMG256/XXMG324
+# 0x412b6043 - LCMXO3L_9400E_XXBG256/XXMG256
+# 0x412bb043 - LCMXO3L_2100C_XXBG256
+# 0x412bc043 - LCMXO3L_4300C_XXBG256/XXBG324
+# 0x412bd043 - LCMXO3L_6900C_XXBG256/XXBG324/XXBG400
+# 0x412be043 - LCMXO3L_9400C_XXBG256/XXBG400/XXBG484
+# 0x612b2043 - LCMXO3LF_1300E_XXMG121/XXUWG36
+# 0x612b3043 - LCMXO3LF_2100E_XXMG121/XXMG256/XXUWG49
+# 0x612b4043 - LCMXO3LF_4300E_XXMG121/XXMG256/XXMG324/XXUWG81
+# 0x612b5043 - LCMXO3LF_6900E_XXMG256/XXMG324
+# 0x612b6043 - LCMXO3LF_9400E_XXBG256/XXMG256
+# 0x612bb043 - LCMXO3LF_2100C_XXBG256
+# 0x612bc043 - LCMXO3LF_4300C_XXBG256/XXBG324
+# 0x612bd043 - LCMXO3LF_6900C_XXBG256/XXBG324/XXBG400
+# 0x612be043 - LCMXO3LF_9400C_XXBG256/XXBG400/XXBG484
+# 0xc12b2043 - LCMXO3L_640E_XXMG121
+# 0xc12b4043 - LCMXO3L_2100E_XXMG324
+# 0xc12bb043 - LCMXO3L_1300C_XXBG256/XXMG256
+# 0xc12bc043 - LCMXO3L_2100C_XXBG324
+# 0xc12bd043 - LCMXO3L_4300C_XXBG400
+# 0xe12b2043 - LCMXO3LF_640E_XXMG121
+# 0xe12b3043 - LCMXO3LF_1300E_XXMG256
+# 0xe12b4043 - LCMXO3LF_2100E_XXMG324
+# 0xe12bb043 - LCMXO3LF_1300C_XXBG256
+# 0xe12bc043 - LCMXO3LF_2100C_XXBG324
+# 0xe12bd043 - LCMXO3LF_4300C_XXBG400
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+	-expected-id 0x412b2043 -expected-id 0x412b3043 -expected-id 0x412b4043 \
+	-expected-id 0x412b5043 -expected-id 0x412b6043 -expected-id 0x412bb043 \
+	-expected-id 0x412bc043 -expected-id 0x412bd043 -expected-id 0x412be043 \
+	-expected-id 0x612b2043 -expected-id 0x612b3043 -expected-id 0x612b4043 \
+	-expected-id 0x612b5043 -expected-id 0x612b6043 -expected-id 0x612bb043 \
+	-expected-id 0x612bc043 -expected-id 0x612bd043 -expected-id 0x612be043 \
+	-expected-id 0xc12b2043 -expected-id 0xc12b4043 -expected-id 0xc12bb043 \
+	-expected-id 0xc12bc043 -expected-id 0xc12bd043 -expected-id 0xe12b2043 \
+	-expected-id 0xe12b3043 -expected-id 0xe12b4043 -expected-id 0xe12bb043 \
+	-expected-id 0xe12bc043 -expected-id 0xe12bd043
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/xilinx-dna.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/xilinx-dna.cfg
new file mode 100644
index 0000000..6b16b78
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/xilinx-dna.cfg
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Spartan3: Table 9-5 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
+proc xilinx_dna_addr {chip} {
+	array set addrs {
+		Spartan3 0x31
+		Spartan6 0x30
+		Series7 0x17
+	}
+	return $addrs($chip)
+}
+
+# Get the "Device DNA".
+# Most Xilinx FPGA devices contain an embedded, unique device identifier.
+# The identifier is nonvolatile, permanently programmed into
+# the FPGA, and is unchangeable providing a great serial / tracking number.
+# This function returns the DNA as a 64 bit integer with the 7 LSBs zeroed.
+# This is compatible with the FUSE DNA which contains all 64 bits.
+proc xilinx_get_dna {tap chip} {
+	set XC7_ISC_ENABLE 0x10
+	set XC7_ISC_DISABLE 0x16
+	set XC7_ISC_DNA [xilinx_dna_addr $chip]
+
+	irscan $tap $XC7_ISC_ENABLE
+	runtest 64
+	irscan $tap $XC7_ISC_DNA
+	scan [drscan $tap 32 0 32 0] "%08x %08x" hi lo
+	runtest 64
+	irscan $tap $XC7_ISC_DISABLE
+	runtest 64
+	# openocd interprets DR scans as LSB first, bit-reverse it
+	return [scan [string reverse [format "%032b%032bb0" $lo $hi]] "%i"]
+}
+
+# Print out the "Device DNA" in the same format that impact uses.
+proc xilinx_print_dna {dna} {
+	set dna [expr {$dna >> 64 - 57}]
+	echo [format "DNA = %057b (0x%016x)" $dna $dna]
+}
+
+proc xc7_get_dna {tap} {
+	return [xilinx_get_dna $tap Series7]
+}
+
+proc xc6s_get_dna {tap} {
+	return [xilinx_get_dna $tap Spartan6]
+}
+
+proc xc3s_get_dna {tap} {
+	return [xilinx_get_dna $tap Spartan3]
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/xilinx-xadc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/xilinx-xadc.cfg
new file mode 100644
index 0000000..fdaf3a9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/xilinx-xadc.cfg
@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx XADC support for 7 Series FPGAs
+#
+# The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
+# temperature, internal power supply rail voltages as well as external
+# voltages. The XADC is available both from fabric as well as through the
+# JTAG TAP.
+#
+# This code implements access through the JTAG TAP.
+#
+# https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
+
+# build a 32 bit DRP command for the XADC DR
+proc xadc_cmd {cmd addr data} {
+	array set cmds {
+		NOP 0x00
+		READ 0x01
+		WRITE 0x02
+	}
+	return [expr {($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)}]
+}
+
+# XADC register addresses
+# Some addresses (status registers 0-3) have special function when written to.
+proc XADC {key} {
+	array set addrs {
+		TEMP 0x00
+		LOCK 0x00
+		VCCINT 0x01
+		VCCAUX 0x02
+		VAUXEN 0x02
+		VPVN 0x03
+		RESET 0x03
+		VREFP 0x04
+		VREFN 0x05
+		VCCBRAM 0x06
+		SUPAOFFS 0x08
+		ADCAOFFS 0x09
+		ADCAGAIN 0x0a
+		VCCPINT 0x0d
+		VCCPAUX 0x0e
+		VCCODDR 0x0f
+		VAUX0 0x10
+		VAUX1 0x11
+		VAUX2 0x12
+		VAUX3 0x13
+		VAUX4 0x14
+		VAUX5 0x15
+		VAUX6 0x16
+		VAUX7 0x17
+		VAUX8 0x18
+		VAUX9 0x19
+		VAUX10 0x1a
+		VAUX11 0x1b
+		VAUX12 0x1c
+		VAUX13 0x1d
+		VAUX14 0x1e
+		VAUX15 0x1f
+		SUPBOFFS 0x30
+		ADCBOFFS 0x31
+		ADCBGAIN 0x32
+		FLAG 0x3f
+		CFG0 0x40
+		CFG1 0x41
+		CFG2 0x42
+		SEQ0 0x48
+		SEQ1 0x49
+		SEQ2 0x4a
+		SEQ3 0x4b
+		SEQ4 0x4c
+		SEQ5 0x4d
+		SEQ6 0x4e
+		SEQ7 0x4f
+		ALARM0 0x50
+		ALARM1 0x51
+		ALARM2 0x52
+		ALARM3 0x53
+		ALARM4 0x54
+		ALARM5 0x55
+		ALARM6 0x56
+		ALARM7 0x57
+		ALARM8 0x58
+		ALARM9 0x59
+		ALARM10 0x5a
+		ALARM11 0x5b
+		ALARM12 0x5c
+		ALARM13 0x5d
+		ALARM14 0x5e
+		ALARM15 0x5f
+	}
+	return $addrs($key)
+}
+
+# Select the XADC DR
+proc xadc_select {tap} {
+	set XADC_IR 0x37
+	irscan $tap $XADC_IR
+	runtest 10
+}
+
+# XADC transfer
+proc xadc_xfer {tap cmd addr data} {
+	set ret [drscan $tap 32 [xadc_cmd $cmd $addr $data]]
+	runtest 10
+	return [expr "0x$ret"]
+}
+
+# XADC register write
+proc xadc_write {tap addr data} {
+	xadc_xfer $tap WRITE $addr $data
+}
+
+# XADC register read, non-pipelined
+proc xadc_read {tap addr} {
+	xadc_xfer $tap READ $addr 0
+	return [xadc_xfer $tap NOP 0 0]
+}
+
+# convert 16 bit register code from ADC measurement on
+# external voltages (VAUX) to Volt
+proc xadc_volt {code} {
+	return [expr {$code * 1./(1 << 16)}]
+}
+
+# convert 16 bit temperature measurement to Celsius
+proc xadc_temp {code} {
+	return [expr {$code * 503.975/(1 << 16) - 273.15}]
+}
+
+# convert 16 bit suppply voltage measurement to Volt
+proc xadc_sup {code} {
+	return [expr {$code * 3./(1 << 16)}]
+}
+
+# perform a single channel measurement using default settings
+proc xadc_single {tap ch} {
+	set cfg0 [xadc_read $tap [XADC CFG0]]
+	set cfg1 [xadc_read $tap [XADC CFG1]]
+	# set channel
+	xadc_write $tap [XADC CFG0] $cfg0
+	# single channel, disable the sequencer
+	xadc_write $tap [XADC CFG1] 0x3000
+	# leave some time for the conversion
+	runtest 100
+	set ret [xadc_read $tap [XADC $ch]]
+	# restore CFG0/1
+	xadc_write $tap [XADC CFG0] $cfg0
+	xadc_write $tap [XADC CFG1] $cfg1
+	return $ret
+}
+
+# measure all internal voltages
+proc xadc_report {tap} {
+	xadc_select $tap
+	echo "TEMP [format %.2f [xadc_temp [xadc_single $tap TEMP]]] C"
+	foreach ch [list VCCINT VCCAUX VCCBRAM VPVN VREFP VREFN \
+		VCCPINT VCCPAUX VCCODDR] {
+		echo "$ch [format %.3f [xadc_sup [xadc_single $tap $ch]]] V"
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/xilinx-xc3s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/xilinx-xc3s.cfg
new file mode 100644
index 0000000..7c17206
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/fpga/xilinx-xc3s.cfg
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx Spartan3 generation
+# https://www.xilinx.com/support/documentation/user_guides/ug331.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc3s
+}
+
+# Table 12-4 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
+# the 4 top bits (28:31) are the die stepping, ignore them.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x02210093 \
+	-expected-id 0x02218093 \
+	-expected-id 0x02220093 \
+	-expected-id 0x02228093 \
+	-expected-id 0x02230093 \
+	-expected-id 0x02610093 \
+	-expected-id 0x02618093 \
+	-expected-id 0x02620093 \
+	-expected-id 0x02628093 \
+	-expected-id 0x02630093 \
+	-expected-id 0x03840093 \
+	-expected-id 0x0384E093 \
+	-expected-id 0x01C10093 \
+	-expected-id 0x01C1A093 \
+	-expected-id 0x01C22093 \
+	-expected-id 0x01C2E093 \
+	-expected-id 0x01C3A093 \
+	-expected-id 0x0140C093 \
+	-expected-id 0x01414093 \
+	-expected-id 0x0141C093 \
+	-expected-id 0x01428093 \
+	-expected-id 0x01434093 \
+	-expected-id 0x01440093 \
+	-expected-id 0x01448093 \
+	-expected-id 0x01450093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+
+source [find fpga/xilinx-dna.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/altera-usb-blaster.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/altera-usb-blaster.cfg
new file mode 100644
index 0000000..cc6057b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/altera-usb-blaster.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Altera USB-Blaster
+#
+# http://www.altera.com/literature/ug/ug_usb_blstr.pdf
+#
+
+adapter driver usb_blaster
+usb_blaster lowlevel_driver ftdi
+# These are already the defaults.
+# usb_blaster vid_pid 0x09FB 0x6001
+# usb_blaster device_desc "USB-Blaster"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/altera-usb-blaster2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/altera-usb-blaster2.cfg
new file mode 100644
index 0000000..93f9809
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/altera-usb-blaster2.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Altera USB-Blaster II
+#
+
+adapter driver usb_blaster
+usb_blaster vid_pid 0x09fb 0x6010 0x09fb 0x6810
+usb_blaster lowlevel_driver ublast2
+usb_blaster firmware /path/to/quartus/blaster_6810.hex
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/angie.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/angie.cfg
new file mode 100644
index 0000000..26cbe39
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/angie.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2023 by NanoXplore, France - all rights reserved
+#
+# configuration file for ANGIE Adapter from NanoXplore.
+#
+
+adapter driver angie
+adapter speed 10000
+reset_config trst_and_srst trst_push_pull srst_open_drain
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/arm-jtag-ew.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/arm-jtag-ew.cfg
new file mode 100644
index 0000000..a064a42
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/arm-jtag-ew.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-JTAG-EW
+#
+# http://www.olimex.com/dev/arm-jtag-ew.html
+#
+
+adapter driver arm-jtag-ew
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ast2600-gpiod.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ast2600-gpiod.cfg
new file mode 100644
index 0000000..5cad02f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ast2600-gpiod.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Use AST2600 GPIO through linuxgpiod
+#
+# +-----------+-------------+-------------+
+# | signal    | GPIO name   | gpio offset |
+# +-----------+-------------+-------------+
+# | TCK/SWCLK | GPIOI2      | 66          |
+# | TMS/SWDIO | GPIOI3      | 67          |
+# | TDI       | GPIOI1      | 65          |
+# | TDO       | GPIOI4      | 68          |
+# | nTRST     | GPIOI0      | 64          |
+# +-----------+-------------+-------------+
+
+adapter driver linuxgpiod
+
+adapter gpio trst 64 -chip 0
+adapter gpio tdi 65 -chip 0
+adapter gpio tck 66 -chip 0
+adapter gpio swclk 66 -chip 0
+adapter gpio tms 67 -chip 0
+adapter gpio swdio 67 -chip 0
+adapter gpio tdo 68 -chip 0
+
+reset_config trst_only separate trst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/at91rm9200.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/at91rm9200.cfg
new file mode 100644
index 0000000..caef997
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/at91rm9200.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Various Atmel AT91RM9200 boards
+#
+# TODO: URL?
+#
+
+adapter driver at91rm9200
+at91rm9200_device rea_ecr
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/beaglebone-jtag-native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/beaglebone-jtag-native.cfg
new file mode 100644
index 0000000..0240e5d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/beaglebone-jtag-native.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# BeagleBone native GPIO interface for JTAG
+#
+# This is best used with a fast buffer but it is also suitable for a direct
+# connection if the target voltage matches the host's IO voltage (typically
+# 3.3V) and the cable is short.
+#
+# DO NOT APPLY VOLTAGE TO THE GPIO PINS UNTIL SYS_RESETN IS HIGH.
+#
+# Do not forget the GND connection.
+
+adapter driver am335xgpio
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on the system clock, calibrated for stock 1 GHz BeagleBoneBlack
+# am335xgpio speed SPEED_COEFF SPEED_OFFSET
+am335xgpio speed_coeffs 600000 575
+
+# BeagleBone pin P9_41
+adapter gpio tdo 20 -chip 0
+
+# BeagleBone pin P9_12
+adapter gpio tdi 28 -chip 1
+
+# BeagleBone pin P9_18
+adapter gpio tms 4 -chip 0
+
+# BeagleBone pin P9_22
+adapter gpio tck 2 -chip 0
+
+# BeagleBone pin P9_16
+adapter gpio led 19 -chip 1
+
+# BeagleBone pin P8_18
+adapter gpio srst 1 -chip 2
+reset_config srst_only srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/beaglebone-swd-native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/beaglebone-swd-native.cfg
new file mode 100644
index 0000000..6c40849
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/beaglebone-swd-native.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# BeagleBone native GPIO interface for SWD
+#
+# This is best used with a fast buffer but it is also suitable for a direct
+# connection if the target voltage matches the host's IO voltage (typically
+# 3.3V) and the cable is short.
+#
+# DO NOT APPLY VOLTAGE TO THE GPIO PINS UNTIL SYS_RESETN IS HIGH.
+#
+# Do not forget the GND connection.
+
+adapter driver am335xgpio
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on the system clock, calibrated for stock 1 GHz BeagleBoneBlack
+# am335xgpio speed SPEED_COEFF SPEED_OFFSET
+am335xgpio speed_coeffs 600000 575
+
+# BeagleBone pin P9_22
+adapter gpio swclk 2 -chip 0
+
+# BeagleBone pin P9_18
+adapter gpio swdio 4 -chip 0
+
+# BeagleBone pin P9_12
+adapter gpio swdio_dir 28 -chip 1
+
+# USR0 LED
+adapter gpio led 21 -chip 1
+
+# BeagleBone pin P8_18
+adapter gpio srst 1 -chip 2
+reset_config srst_only srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/buspirate.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/buspirate.cfg
new file mode 100644
index 0000000..8f613a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/buspirate.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Buspirate with OpenOCD support
+#
+# http://dangerousprototypes.com/bus-pirate-manual/
+#
+
+adapter driver buspirate
+
+# you need to specify port on which BP lives
+#buspirate port /dev/ttyUSB0
+
+# communication speed setting
+buspirate speed normal ;# or fast
+
+# voltage regulator Enabled = 1 Disabled = 0
+#buspirate vreg 0
+
+# pin mode normal or open-drain (jtag only)
+#buspirate mode normal
+
+# pullup state Enabled = 1 Disabled = 0
+#buspirate pullup 0
+
+# this depends on the cable, you are safe with this option
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/chameleon.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/chameleon.cfg
new file mode 100644
index 0000000..b73d129
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/chameleon.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Amontec Chameleon POD
+#
+# http://www.amontec.com/chameleon.shtml
+#
+
+adapter driver parport
+parport cable chameleon
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/cmsis-dap.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/cmsis-dap.cfg
new file mode 100644
index 0000000..15efe80
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/cmsis-dap.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# ARM CMSIS-DAP compliant adapter
+#
+# http://www.keil.com/support/man/docs/dapdebug/
+#
+
+adapter driver cmsis-dap
+
+# Optionally specify the serial number of CMSIS-DAP usb device.
+# adapter serial 02200201E6661E601B98E3B9
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/dln-2-gpiod.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/dln-2-gpiod.cfg
new file mode 100644
index 0000000..c9e3388
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/dln-2-gpiod.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Use DLN-2 GPIO through linuxgpiod
+#
+# +-----------+-------------+-------------+
+# | signal    | DLN-2       | gpio offset |
+# +-----------+-------------+-------------+
+# | nSRST     | J3.1  (PA0) | 0           |
+# | TDO       | J3.2  (PA1) | 1           |
+# | TCK/SWCLK | J3.3  (PA2) | 2           |
+# | TMS/SWDIO | J3.4  (PA3) | 3           |
+# | TDI       | J3.5  (PA4) | 4           |
+# | nTRST     | J3.6  (PA5) | 5           |
+# | LED       | J3.7  (PA6) | 6           |
+# | GND       | J3.12 (GND) |             |
+# +-----------+-------------+-------------+
+
+adapter driver linuxgpiod
+
+adapter gpio srst 0 -chip 0
+adapter gpio tdo 1 -chip 0
+adapter gpio tck 2 -chip 0
+adapter gpio swclk 2 -chip 0
+adapter gpio tms 3 -chip 0
+adapter gpio swdio 3 -chip 0
+adapter gpio tdi 4 -chip 0
+adapter gpio trst 5 -chip 0
+adapter gpio led 6 -chip 0
+
+reset_config trst_and_srst separate srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/dummy.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/dummy.cfg
new file mode 100644
index 0000000..34e6558
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/dummy.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Dummy interface (for testing purposes)
+#
+
+adapter driver dummy
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/esp_usb_bridge.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/esp_usb_bridge.cfg
new file mode 100644
index 0000000..9342239
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/esp_usb_bridge.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# ESP USB Bridge jtag adapter
+#
+
+adapter driver esp_usb_jtag
+
+espusbjtag vid_pid 0x303a 0x1002
+espusbjtag caps_descriptor 0x030A  # string descriptor index:10
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/esp_usb_jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/esp_usb_jtag.cfg
new file mode 100644
index 0000000..40427d0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/esp_usb_jtag.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Espressif builtin USB-JTAG adapter
+#
+
+adapter driver esp_usb_jtag
+
+espusbjtag vid_pid 0x303a 0x1001
+espusbjtag caps_descriptor 0x2000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/estick.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/estick.cfg
new file mode 100644
index 0000000..1daaf7c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/estick.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# eStick
+#
+# http://code.google.com/p/estick-jtag/
+#
+
+adapter driver opendous
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/flashlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/flashlink.cfg
new file mode 100644
index 0000000..d552c50
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/flashlink.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# ST FlashLINK JTAG parallel cable
+#
+# http://www.st.com/internet/evalboard/product/94023.jsp
+# http://www.st.com/stonline/products/literature/um/7889.pdf
+#
+
+if { [info exists PARPORTADDR] } {
+   set _PARPORTADDR $PARPORTADDR
+} else {
+   set _PARPORTADDR 0
+}
+
+adapter driver parport
+parport port $_PARPORTADDR
+parport cable flashlink
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ft232r.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ft232r.cfg
new file mode 100644
index 0000000..94eed02
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ft232r.cfg
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter driver ft232r
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ft232r/radiona_ulx3s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ft232r/radiona_ulx3s.cfg
new file mode 100644
index 0000000..3fc3d71
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ft232r/radiona_ulx3s.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# This adapter is integrated in to Radiona ULX3S board:
+# 	board/radiona_ulx3s.cfg
+# See schematics for the ft232r layout:
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf
+
+adapter driver ft232r
+adapter speed 1000
+ft232r vid_pid 0x0403 0x6015
+ft232r tck_num DSR
+ft232r tms_num DCD
+ft232r tdi_num RI
+ft232r tdo_num CTS
+ft232r trst_num RTS
+ft232r srst_num DTR
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/100ask-openjtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/100ask-openjtag.cfg
new file mode 100644
index 0000000..5ab9252
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/100ask-openjtag.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# www.100ask.org OpenJTAG
+#
+# http://www.100ask.net/OpenJTAG.html
+#
+# Schematics are available from
+# https://blog.matthiasbock.net/wp-content/uploads/2015/04/100ask-JTAGv3.pdf
+#
+
+adapter driver ftdi
+ftdi device_desc "USB<=>JTAG&RS232"
+ftdi vid_pid 0x1457 0x5118
+
+ftdi layout_init 0x0f08 0x0f1b
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/arty-onboard-ftdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/arty-onboard-ftdi.cfg
new file mode 100644
index 0000000..0edc615
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/arty-onboard-ftdi.cfg
@@ -0,0 +1,7 @@
+interface ftdi
+# ftdi_device_desc "Arty On-board FTDI interface"
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+ftdi layout_init 0x0088 0x008b
+reset_config none
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg
new file mode 100644
index 0000000..6256aa0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Ashling Opella-LD
+#
+# https://www.ashling.com/Opella-LD/
+#
+
+adapter driver ftdi
+ftdi device_desc "Opella-LD Debug Probe"
+ftdi vid_pid 0x0B6B 0x0040
+ftdi tdo_sample_edge falling
+ftdi layout_init 0x0A68 0xFF7B
+ftdi channel 0
+ftdi layout_signal JTAGOE -ndata 0x0010
+ftdi layout_signal nTRST -data 0x0020
+ftdi layout_signal nSRST -data 0x0040
+ftdi layout_signal SWD_EN -data 0x0100
+ftdi layout_signal SWDIO_OE -data 0x0200
+ftdi layout_signal LED -ndata 0x0800
+transport select jtag
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ashling-opella-ld-swd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ashling-opella-ld-swd.cfg
new file mode 100644
index 0000000..4a4e4e0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ashling-opella-ld-swd.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Ashling Opella-LD
+#
+# https://www.ashling.com/Opella-LD/
+#
+
+adapter driver ftdi
+ftdi device_desc "Opella-LD Debug Probe"
+ftdi vid_pid 0x0B6B 0x0040
+ftdi layout_init 0x0860 0x0b7b
+ftdi channel 0
+ftdi layout_signal JTAGOE -data 0x0010
+ftdi layout_signal nTRST -data 0x0020
+ftdi layout_signal nSRST -data 0x0040
+ftdi layout_signal SWD_EN -data 0x0100
+ftdi layout_signal SWDIO_OE -data 0x0200
+ftdi layout_signal LED -ndata 0x0800
+transport select swd
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/axm0432.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/axm0432.cfg
new file mode 100644
index 0000000..5008399
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/axm0432.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Axiom axm0432
+#
+# http://www.axman.com
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Symphony SoundBite"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0c08 0x0c2b
+ftdi layout_signal nTRST -data 0x0800
+ftdi layout_signal nSRST -data 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/c232hm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/c232hm.cfg
new file mode 100644
index 0000000..23c8f3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/c232hm.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# FTDI USB Hi-Speed to MPSSE Cable
+#
+# http://www.ftdichip.com/Products/Cables/USBMPSSE.htm
+#
+# C232HM-DDHSL-0 and C232HM-EDSL-0 provide 3.3V and 5V on pin 1 (Red),
+# respectively.
+#
+# Adapter: http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_C232HM_MPSSE_CABLE.PDF
+# Chip: http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf
+# See pinout/colors at end of this file.
+#
+# Tech notes:
+# http://www.ftdichip.com/Support/Documents/AppNotes/AN_135_MPSSE_Basics.pdf
+# http://www.ftdichip.com/Support/Documents/AppNotes/AN_129_FTDI_Hi_Speed_USB_To_JTAG_Example.pdf
+
+adapter driver ftdi
+#ftdi device_desc "C232HM-DDHSL-0"
+#ftdi device_desc "C232HM-EDHSL-0"
+
+# Common PID for FT232H
+ftdi vid_pid 0x0403 0x6014
+
+# Layout
+# High data byte 0x40 configures red LED on ACBUS6 initially high (unlit, since active-low)
+# Low data byte 0x08 configures TMS on ACBUS3 initially high (asserted); TCK, TDI low
+# High direction byte 0x40 configures red LED on ACBUS6 as high (output)
+# Low direction byte 0x0b configures TDO on ACBUS2 as low (input)
+ftdi layout_init 0x4008 0x400b
+
+# ---A*BUS-------CCCCCCCC|DDDDDDDD
+# --------\______76543210|76543210
+# LED	0x4000 = 01000000|00000000 = ACBUS6
+#GPIOL0	0x0010 = 00000000|00010000 = ADBUS4
+#GPIOL1	0x0020 = 00000000|00100000 = ADBUS5
+#GPIOL2	0x0040 = 00000000|01000000 = ADBUS6
+#GPIOL3	0x0080 = 00000000|10000000 = ADBUS7
+# -ndata treats the LED as active-low for expected behavior (toggle when transferring)
+ftdi layout_signal LED -ndata 0x4000
+# Available for aliasing as desired
+ftdi layout_signal GPIOL0 -data 0x0010 -oe 0x0010
+ftdi layout_signal GPIOL1 -data 0x0020 -oe 0x0020
+ftdi layout_signal GPIOL2 -data 0x0040 -oe 0x0040
+ftdi layout_signal GPIOL3 -data 0x0080 -oe 0x0080
+
+# C232HM		FT232H	JTAG/Other
+# Num	Color	Name	Func
+# 1		Red		VCC		Optionally, can power the board if it is not using its own power supply.
+# 2		Orange	ADBUS0	TCK
+# 3		Yellow  ADBUS1	TDI
+# 4		Green	ADBUS2	TDO
+# 5		Brown   ADBUS3	TMS
+# 6		Grey	ADBUS4	GPIOL0
+# 7		Purple	ADBUS5	GPIOL1
+# 8		White	ADBUS6	GPIOL2
+# 9		Blue	ADBUS7	GPIOL3
+# 10	Black	GND		Connect to ground
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/cortino.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/cortino.cfg
new file mode 100644
index 0000000..8bc8d6e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/cortino.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hitex Cortino
+#
+# http://www.hitex.com/index.php?id=cortino
+#
+
+adapter driver ftdi
+ftdi device_desc "Cortino"
+ftdi vid_pid 0x0640 0x0032
+
+ftdi layout_init 0x0108 0x010b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200 -oe 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent-hs1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent-hs1.cfg
new file mode 100644
index 0000000..6a632ed
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent-hs1.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# this supports JTAG-HS1 and JTAG-SMT1
+# (the later being the OEM on-board version)
+
+adapter driver ftdi
+ftdi device_desc "Digilent Adept USB Device"
+ftdi vid_pid 0x0403 0x6010
+# channel 1 does not have any functionality
+ftdi channel 0
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0088 0x008b
+reset_config none
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent-hs2-cjtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent-hs2-cjtag.cfg
new file mode 100644
index 0000000..3daf461
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent-hs2-cjtag.cfg
@@ -0,0 +1,17 @@
+adapter driver ftdi
+ftdi device_desc "Digilent Adept USB Device"
+ftdi vid_pid 0x0403 0x6014
+
+ftdi channel 0
+ftdi layout_init 0x60e8 0x60eb
+
+reset_config none
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -ndata 0x6000 -oe 0x6000
+
+ftdi layout_signal TMSC_EN -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent-hs2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent-hs2.cfg
new file mode 100644
index 0000000..89c9e4b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent-hs2.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# this supports JTAG-HS2 (and apparently Nexys4 as well)
+
+# ADBUS5 controls TMS tri-state buffer enable
+# ACBUS6=SEL_TMS controls mux to TMS output buffer: 0=TMS 1=TDI
+# ACBUS5=SEL_TDO controls mux to TDO input: 0=TDO 1=TMS
+
+adapter driver ftdi
+ftdi device_desc "Digilent Adept USB Device"
+ftdi vid_pid 0x0403 0x6014
+
+ftdi channel 0
+ftdi layout_init 0x00e8 0x60eb
+ftdi layout_signal SWD_EN -data 0x6000
+ftdi layout_signal SWDIO_OE -data 0x20
+
+reset_config none
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent_jtag_hs3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent_jtag_hs3.cfg
new file mode 100644
index 0000000..78a233f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent_jtag_hs3.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent JTAG-HS3
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6014
+ftdi device_desc "Digilent USB Device"
+
+# From Digilent support:
+# The SRST pin is [...] 0x20 and 0x10 is the /OE (active low output enable)
+
+ftdi layout_init 0x2088 0x308b
+ftdi layout_signal nSRST -data 0x2000 -noe 0x1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent_jtag_smt2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent_jtag_smt2.cfg
new file mode 100644
index 0000000..ac623a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent_jtag_smt2.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent JTAG-SMT2
+#
+# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,1053&Prod=JTAG-SMT2
+#
+# Config is based on data from
+# http://electronix.ru/forum/index.php?showtopic=114633&view=findpost&p=1215497 and ZedBoard schematics
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6014
+
+ftdi layout_init 0x20e8 0x3feb
+ftdi layout_signal nSRST -data 0x2000
+ftdi layout_signal GPIO2 -data 0x2000
+ftdi layout_signal GPIO1 -data 0x0200
+ftdi layout_signal GPIO0 -data 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg
new file mode 100644
index 0000000..38236bc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent JTAG-SMT2-NC
+#
+# http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/
+# https://reference.digilentinc.com/_media/jtag_smt2nc/jtag-smt2-nc_rm.pdf
+#
+# Based on reference sheet (above) and Xilinx KCU105 schematics
+# https://www.xilinx.com/products/boards-and-kits/kcu105.html#documentation
+#
+# Note that the digilent_jtag_smt2 layout does not work and hangs while
+# the ftdi device_desc from digilent_hs2 is wrong.
+
+adapter driver ftdi
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6014
+ftdi channel 0
+ftdi layout_init 0x00e8 0x60eb
+reset_config none
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/dlp-usb1232h.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/dlp-usb1232h.cfg
new file mode 100644
index 0000000..67fee6b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/dlp-usb1232h.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# DLP Design DLP-USB1232H USB-to-UART/FIFO interface module
+#
+# http://www.dlpdesign.com/usb/usb1232h.shtml
+#
+# Schematics for OpenOCD usage:
+# http://randomprojects.org/wiki/DLP-USB1232H_and_OpenOCD_based_JTAG_adapter
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on schematics and code"
+echo "in ft2232.c. Please report your experience with this file to openocd-devel"
+echo "mailing list, so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/dp_busblaster.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/dp_busblaster.cfg
new file mode 100644
index 0000000..373e122
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/dp_busblaster.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Dangerous Prototypes - Bus Blaster
+#
+# The Bus Blaster has a configurable buffer between the FTDI FT2232H and the
+# JTAG header which allows it to emulate various debugger types. It comes
+# configured as a JTAGkey device.
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+
+echo "Info : If you need SWD support, flash KT-Link buffer from https://github.com/bharrisau/busblaster
+and use dp_busblaster_kt-link.cfg instead"
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/dp_busblaster_kt-link.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/dp_busblaster_kt-link.cfg
new file mode 100644
index 0000000..222ca38
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/dp_busblaster_kt-link.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Dangerous Prototypes - Bus Blaster (with KT-Link buffer)
+#
+# The Bus Blaster has a configurable buffer between the FTDI FT2232H
+# and the JTAG header which allows it to emulate various debugger
+# types. This config works with KT-Link compatible implementation from
+# https://github.com/bharrisau/busblaster and is SWD-enabled.
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x8c28 0xff3b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+ftdi layout_signal LED -ndata 0x8000
+ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000
+ftdi layout_signal SWDIO_OE -ndata 0x1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/esp32_devkitj_v1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/esp32_devkitj_v1.cfg
new file mode 100644
index 0000000..1b455a9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/esp32_devkitj_v1.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Driver for the FT2232H JTAG chip on the Espressif DevkitJ board
+# (and most other FT2232H and FT232H based boards)
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010 0x0403 0x6014
+
+# interface 1 is the uart
+ftdi channel 0
+
+# TCK, TDI, TDO, TMS: ADBUS0-3
+# LEDs: ACBUS4-7
+
+ftdi layout_init 0x0008 0xf00b
+ftdi layout_signal LED -data 0x1000
+ftdi layout_signal LED2 -data 0x2000
+ftdi layout_signal LED3 -data 0x4000
+ftdi layout_signal LED4 -data 0x8000
+
+# ESP32 series chips do not have a TRST input, and the SRST line is connected to the EN pin.
+# The target code doesn't handle SRST reset properly yet, so this is commented out:
+# ftdi layout_signal nSRST -oe 0x0020
+# reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg
new file mode 100644
index 0000000..1880bcb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Driver for the FT2232H JTAG chip on the Espressif Kaluga-1 ESP32-S2 board
+# (and most other FT2232H and FT232H based boards)
+#
+# JTAG DIP switch (labelled SW5 in the schematic) should be "ON" for lines
+# labelled TCK, TDO, TDI and TWS, to connect the FT2232H to the ESP32-S2.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010 0x0403 0x6014
+
+# interface 1 is the uart
+ftdi channel 0
+
+# TCK, TDI, TDO, TMS: ADBUS0-3
+# TRST/SRST: ADBUS5 (unused for now)
+# LEDs: ACBUS3-4 (inverted)
+
+ftdi layout_init 0x0008 0x180b
+ftdi layout_signal LED -ndata 0x0800
+ftdi layout_signal LED2 -ndata 0x1000
+
+# ESP32* series chips do not have a TRST input, and the SRST line is connected
+# to the EN pin.
+# The target code doesn't handle SRST reset properly yet, so this is
+# commented out:
+# ftdi layout_signal nSRST -oe 0x0020
+# reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flossjtag-noeeprom.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flossjtag-noeeprom.cfg
new file mode 100644
index 0000000..1008e1a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flossjtag-noeeprom.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# FlossJTAG
+#
+# http://github.com/esden/floss-jtag
+#
+# This is the pre v0.3 Floss-JTAG compatible config file. It can also be used
+# for newer versions of Floss-JTAG with empty or not populated EEPROM. If you
+# have several Floss-JTAG connected you have to use the USB ID to select a
+# specific one.
+#
+# If you have a Floss-JTAG WITH EEPROM that is programmed, use the
+# flossjtag.cfg file.
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flossjtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flossjtag.cfg
new file mode 100644
index 0000000..90ba63a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flossjtag.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# FlossJTAG
+#
+# http://github.com/esden/floss-jtag
+#
+# This is the v0.3 and v1.0 Floss-JTAG compatible config file. It relies on the
+# existence of an EEPROM on Floss-JTAG containing a name. If you have several
+# Floss-JTAG adapters connected you can use the serial number to select a
+# specific device.
+#
+# If your Floss-JTAG does not have an EEPROM, or the EEPROM is empty, use the
+# flossjtag-noeeprom.cfg file.
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+ftdi device_desc "FLOSS-JTAG"
+# adapter serial "FJ000001"
+
+ftdi layout_init 0x0008 0x180b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
+ftdi layout_signal LED -data 0x0800
+ftdi layout_signal LED2 -data 0x1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flyswatter.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flyswatter.cfg
new file mode 100644
index 0000000..8bce00d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flyswatter.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TinCanTools Flyswatter
+#
+# http://web.archive.org/web/20150419072034/http://www.tincantools.com/JTAG/Flyswatter.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Flyswatter"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0818 0x0cfb
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -oe 0x0020
+ftdi layout_signal LED -data 0x0c00
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flyswatter2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flyswatter2.cfg
new file mode 100644
index 0000000..ebc00fe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/flyswatter2.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TinCanTools Flyswatter2
+#
+# https://www.tincantools.com/product/flyswatter2/
+#
+
+adapter driver ftdi
+ftdi device_desc "Flyswatter2"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0538 0x057b
+ftdi layout_signal LED -ndata 0x0400
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -data 0x0020 -noe 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ft232h-module-swd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ft232h-module-swd.cfg
new file mode 100644
index 0000000..d09ccf1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ft232h-module-swd.cfg
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# ADAFRUIT FTDI FT232H as a SWD direct connect interface
+# Any FT232H based board may work
+#
+# http://www.ftdichip.com/Products/ICs/FT232H.htm
+#
+#
+
+adapter driver ftdi
+
+ftdi vid_pid 0x0403 0x6014
+
+# data MSB..LSB       direction (1:out) MSB..LSB
+# 0000'0000'0011'0000 0000'0000'0011'1011
+ftdi layout_init 0x0030 0x003b
+# 0xfff8 0xfffb
+# Those signal are only required on some platforms or may required to be
+# enabled explicitly (e.g. nrf5x chips).
+ftdi layout_signal nSRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nTRST -data 0x0020 -oe 0x0020
+
+# swd enable
+ftdi layout_signal SWD_EN -data 0
+# tri-state (configure as input) TDO/TIO when reading
+ftdi layout_signal SWDIO_OE -data 0
+
+transport select swd
+
+# re-configure TDO as tri-state
+#ftdi layout_signal TDO -data 0x0002 -oe 0x0002
+#ftdi layout_signal TDI -data 0x0004
+
+# Adafruit      FT232H    JTAG       SWD
+# Name  Pin     Name      Func       Func
+#  D0   J1-3    ADBUS0    TCK        SWDCLK
+#  D1   J1-4    ADBUS1    TDO/DI     SWDIO
+#  D2   J1-5    ADBUS2    TDI/DO     SWDIO
+#  D3   J1-6    ADBUS3    TMS        N/A
+#  D4   J1-7    ADBUS4    (GPIOL0)   /nSRST  optional module reset
+#  D5   J1-8    ADBUS5    (GPIOL1)   /nTRST  optional target reset
+#  D6   J1-9    ADBUS6    (GPIOL2)
+#  D7   J1-10   ADBUS7    (GPIOL3)
+#  C0   J2-1    ACBUS0    (GPIOH0)
+#  C1   J2-2    ACBUS1    (GPIOH1)
+#  C2   J2-3    ACBUS2    (GPIOH2)
+#  C3   J2-4    ACBUS3    (GPIOH3)
+#  C4   J2-5    ACBUS4    (GPIOH4)
+#  C5   J2-6    ACBUS5    (GPIOH5)
+#  C6   J2-7    ACBUS6    (GPIOH6)
+#  C7   J2-8    ACBUS7    (GPIOH7)
+#  C8   J2-9    ACBUS8
+#  C9   J2-10   ACBUS9
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/gw16042.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/gw16042.cfg
new file mode 100644
index 0000000..326a88f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/gw16042.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Gateworks GW16042 JTAG Dongle
+#
+# http://www.gateworks.com/
+#
+# Layout:  FTDI FT2232H
+#   ADBUS0 TCK
+#   ADBUS1 TDI
+#   ADBUS2 TDO (input)
+#   ADBUS3 TMS
+#   ADBUS4 nTRST
+#   ADBUS5 nSRST
+#   ADBUS6 OE (active high) for TRST, TDI, TMS, TCK
+#   ADBUS7 NC
+#   ACBUS0-7 NC
+#   BDBUS0 RXD
+#   BDBUS1 TXD (input)
+#
+
+adapter driver ftdi
+ftdi device_desc "USB-JTAG"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0058 0x007b
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hie-jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hie-jtag.cfg
new file mode 100644
index 0000000..6694df0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hie-jtag.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Hofstädtler Industrie-Electronic (HIE) JTAG Debugger
+#
+# https://www.hofstaedtler.com/jtag
+#
+
+adapter driver ftdi
+ftdi channel 0
+ftdi vid_pid 0x0403 0x6014
+ftdi device_desc "HIE JTAG Debugger"
+
+ftdi layout_init 0x0c08 0x4f1b
+
+# define both Reset signals
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+
+# Toggle USB LED
+ftdi layout_signal LED -ndata 0x4000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg
new file mode 100644
index 0000000..d5d24e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 10-ETM
+#
+# http://de.hilscher.com/products_details_hardware.html?p_id=P_4ce145a5983e6
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX 10-ETM"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg
new file mode 100644
index 0000000..003b9df
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 500-ETM
+#
+# http://de.hilscher.com/files_design/8/NXHX500-ETM_description_Rev01_EN.pdf
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX 500-ETM"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx500_re.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx500_re.cfg
new file mode 100644
index 0000000..97ad380
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx500_re.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 500-RE
+#
+# http://de.hilscher.com/products_details_hardware.html?p_id=P_461ff2053bad1&bs=20
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX 500-RE"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg
new file mode 100644
index 0000000..06280c1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 50-ETM
+#
+# http://de.hilscher.com/files_design/8/NXHX50-ETM_description_Rev01_EN.pdf
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX 50-ETM"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx50_re.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx50_re.cfg
new file mode 100644
index 0000000..f14be62
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hilscher_nxhx50_re.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 50-RE
+#
+# http://de.hilscher.com/products_details_hardware.html?p_id=P_483c0f582ad36&bs=20
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX50-RE"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hitex_lpc1768stick.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hitex_lpc1768stick.cfg
new file mode 100644
index 0000000..91bd5a8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hitex_lpc1768stick.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hitex LPC1768-Stick
+#
+# http://www.hitex.com/?id=1602
+#
+
+
+adapter driver ftdi
+ftdi device_desc "LPC1768-Stick"
+ftdi vid_pid 0x0640 0x0026
+
+ftdi layout_init 0x0388 0x038b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0080 -noe 0x200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hitex_str9-comstick.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hitex_str9-comstick.cfg
new file mode 100644
index 0000000..f698677
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/hitex_str9-comstick.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hitex STR9-comStick
+#
+# http://www.hitex.com/index.php?id=383
+#
+
+adapter driver ftdi
+ftdi device_desc "STR9-comStick"
+ftdi vid_pid 0x0640 0x002c
+
+ftdi layout_init 0x0108 0x010b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200 -oe 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/icebear.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/icebear.cfg
new file mode 100644
index 0000000..4a76399
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/icebear.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Section5 ICEBear
+#
+# http://section5.ch/icebear
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "ICEbear JTAG adapter"
+ftdi vid_pid 0x0403 0xc140
+
+ftdi layout_init 0x0028 0x002b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/imx8mp-evk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/imx8mp-evk.cfg
new file mode 100644
index 0000000..02564dc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/imx8mp-evk.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration file for NXP MC-IMX8MP-EVK on-board internal JTAG
+#
+# Using this interface requires enabling "remote mode" for the board using the
+# NXP bcu tool (see https://github.com/NXPmicro/bcu)
+#
+#	bcu set_gpio remote_en 1 -board=imx8mpevk
+#
+# The REMOTE_EN gpio is accessible through the same FTDI adapter but it's
+# behind an I2C GPIO expander.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6011
+ftdi channel 0
+
+ftdi layout_init 0x00f8 0x000b
+
+ftdi layout_signal RESET_B	-data 0x0010 -oe 0x0010
+# Called SYS_nRST in schematics
+ftdi layout_signal nSRST	-data 0x0020 -oe 0x0020
+ftdi layout_signal IO_nRST	-data 0x0040 -oe 0x0040
+ftdi layout_signal ONOFF_B	-data 0x0080 -oe 0x0080
+
+ftdi layout_signal GPIO1	-data 0x0100 -oe 0x0100
+ftdi layout_signal GPIO2	-data 0x0200 -oe 0x0200
+ftdi layout_signal GPIO3	-data 0x0400 -oe 0x0400
+ftdi layout_signal GPIO4	-data 0x0800 -oe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/incircuit-icprog.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/incircuit-icprog.cfg
new file mode 100644
index 0000000..81f2872
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/incircuit-icprog.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# In-Circuit's ICprog OpenOCD JTAG Adapter
+# https://shop.in-circuit.de/product_info.php?products_id=112
+#
+# Schematics available at
+# http://wiki.in-circuit.de/images/0/06/610000158A_openocd.pdf
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nSRST -noe 0x0400 -data 0x0800
+ftdi layout_signal nTRST -noe 0x0100 -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/iotlab-usb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/iotlab-usb.cfg
new file mode 100644
index 0000000..b7a004e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/iotlab-usb.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is the integrated adapter as found on the IoT-LAB boards
+# https://github.com/iot-lab/iot-lab/wiki
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/isodebug.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/isodebug.cfg
new file mode 100644
index 0000000..0a6e080
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/isodebug.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# isodebug v1
+# 5 kV isolated JTAG/SWD + UART adapter by Unjo AB
+
+adapter driver ftdi
+ftdi vid_pid 0x22b7 0x150d
+
+ftdi layout_init 0x0ff8 0xfffb
+
+ftdi layout_signal LED -ndata 0x0100
+ftdi layout_signal nTRST -data 0x0200
+ftdi layout_signal nSRST -noe 0x0400
+ftdi layout_signal SWDIO_OE -data 0x0008
+
+# Mode signals, either of these needs to be high to drive the JTAG/SWD pins.
+# The power-on state is low for both signals but the init setting above sets
+# JTAG_EN high.
+ftdi layout_signal SWD_EN -data 0x1000
+ftdi layout_signal JTAG_EN -data 0x0800
+
+# In SWD mode, the JTAG_EN signal doubles as SWO_EN_N which switches the
+# second FTDI channel UART RxD to the SWO pin instead of the separate RxD
+# pin. Note that the default init state has this pin high so when OpenOCD
+# starts in SWD mode, SWO is by default disabled. To enable SWO tracing,
+# issue the command 'ftdi set_signal SWO_EN 1' where tracing is configured.
+# To switch back to using the separate UART, SWO_EN needs to be disabled
+# before exiting OpenOCD, or the adapter replugged.
+ftdi layout_signal SWO_EN -nalias JTAG_EN
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg
new file mode 100644
index 0000000..ea60dcf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# DISTORTEC JTAG-lock-pick Tiny 2
+#
+# http://www.distortec.com
+#
+
+adapter driver ftdi
+ftdi device_desc "JTAG-lock-pick Tiny 2"
+ftdi vid_pid 0x0403 0x8220
+
+ftdi layout_init 0x8c28 0xff3b
+ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+ftdi layout_signal SWDIO_OE -ndata 0x1000
+ftdi layout_signal LED -ndata 0x8000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtagkey.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtagkey.cfg
new file mode 100644
index 0000000..1c1c09d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtagkey.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Amontec JTAGkey
+#
+# http://www.amontec.com/jtagkey.shtml
+#
+
+adapter driver ftdi
+ftdi device_desc "Amontec JTAGkey"
+ftdi vid_pid 0x0403 0xcff8
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtagkey2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtagkey2.cfg
new file mode 100644
index 0000000..80df347
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtagkey2.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Amontec JTAGkey2
+#
+# http://www.amontec.com/jtagkey2.shtml
+#
+
+adapter driver ftdi
+ftdi device_desc "Amontec JTAGkey-2"
+ftdi vid_pid 0x0403 0xcff8
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtagkey2p.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtagkey2p.cfg
new file mode 100644
index 0000000..3a76bd0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/jtagkey2p.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Amontec JTAGkey2P
+#
+# http://www.amontec.com/jtagkey2p.shtml
+#
+
+adapter driver ftdi
+ftdi device_desc "Amontec JTAGkey-2P"
+ftdi vid_pid 0x0403 0xcff8
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/kt-link.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/kt-link.cfg
new file mode 100644
index 0000000..61c6b83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/kt-link.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Kristech KT-Link
+#
+# http://www.kristech.eu
+#
+
+adapter driver ftdi
+ftdi device_desc "KT-LINK"
+ftdi vid_pid 0x0403 0xbbe2
+
+ftdi layout_init 0x8c28 0xff3b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+ftdi layout_signal LED -data 0x8000
+ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000
+ftdi layout_signal SWDIO_OE -ndata 0x1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg
new file mode 100644
index 0000000..df4955f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# This adapter is integrated in to LambdaConcept ECPIX-5 board:
+# 	interface/ftdi/lambdaconcept_ecpix-5.cfg
+# See schematics for the ftdi layout:
+# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF
+
+adapter driver ftdi
+adapter speed 10000
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0xfff8 0xfffb
+transport select jtag
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/lisa-l.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/lisa-l.cfg
new file mode 100644
index 0000000..75c5cbe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/lisa-l.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Lisa/L
+#
+# http://paparazzi.enac.fr/wiki/Lisa
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on schematics and code"
+echo "in ft2232.c. Please report your experience with this file to openocd-devel"
+echo "mailing list, so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Lisa/L"
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 1
+
+ftdi layout_init 0x0008 0x180b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
+ftdi layout_signal LED -data 0x1800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/luminary-icdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/luminary-icdi.cfg
new file mode 100644
index 0000000..9142503
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/luminary-icdi.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Luminary Micro Stellaris LM3S9B9x Evaluation Kits
+# In-Circuit Debug Interface (ICDI) Board
+#
+# Essentially all Luminary debug hardware is the same, (with both
+# JTAG and SWD support compatible with ICDI boards.  This ICDI adapter
+# configuration is JTAG-only, but the same hardware handles SWD too.
+#
+# This is a discrete ftdi based debug board which supports ARM's
+# JTAG/SWD connectors in both backwards-compatible 20-pin format and
+# in the new-style compact 10-pin.  There's also an 8-pin connector
+# with serial port support.  It's included with LM3S9B9x eval boards.
+#
+# http://www.luminarymicro.com/products/ek-lm3s9b90.html
+# http://www.luminarymicro.com/products/ek-lm3s9b92.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Luminary Micro ICDI Board"
+ftdi vid_pid 0x0403 0xbcda
+
+ftdi layout_init 0x00a8 0x00eb
+ftdi layout_signal nSRST -noe 0x0020
+ftdi layout_signal SWD_EN -ndata 0x0080
+ftdi layout_signal SWDIO_OE -data 0x0008
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/luminary-lm3s811.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/luminary-lm3s811.cfg
new file mode 100644
index 0000000..98be166
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/luminary-lm3s811.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Luminary Micro Stellaris LM3S811 Evaluation Kit
+#
+# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html
+#
+# NOTE:  this is only for boards *before* Rev C, which adds support
+# for SWO tracing with ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN signals.
+# The "evb_lm3s811" layout doesn't set up those signals.
+#
+# Rev C boards work more like the other Stellaris eval boards.  They
+# need to use the "luminary_icdi" layout to work correctly.
+#
+
+adapter driver ftdi
+ftdi device_desc "LM3S811 Evaluation Board"
+ftdi vid_pid 0x0403 0xbcd9
+
+ftdi layout_init 0x0088 0x008b
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
+ftdi layout_signal SWD_EN -ndata 0x0080
+ftdi layout_signal SWDIO_OE -data 0x0008
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/luminary.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/luminary.cfg
new file mode 100644
index 0000000..27d9a9d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/luminary.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Luminary Micro Stellaris Evaluation Kits
+#
+# http://www.luminarymicro.com/products/evaluation_kits.html
+#
+# There are a number of evaluation kits for Stellaris Cortex-M3 chips.
+# Currently they all bundle ftdi based debug support.  When that is
+# used (instead of an external adapter), use this config file in one
+# of these two modes:
+#
+# - Eval board debug ... debug of the Stellaris chip via port A.
+#
+# - Other board debug ... same thing, but the board acts as a debug
+#   adapter for another board (using a standard ARM JTAG connector).
+#   The Stellaris chip stays in reset.
+#
+# Those support both JTAG and SWD.  SWD is an ARM-only two-wire debug
+# protocol; in 2009, OpenOCD does not support SWD.
+#
+# Port B of the ftdi chip is normally used as a serial link to the
+# Stellaris chip.  On most boards (but not older LM3S811 eval boards),
+# when SWD is used Port B may instead be used to read low-bandwidth
+# "SWO trace" data, including so-called "printf style" output from
+# firmware via the ITM module as well as profile data.
+#
+
+adapter driver ftdi
+ftdi device_desc "Stellaris Evaluation Board"
+ftdi vid_pid 0x0403 0xbcd9
+
+ftdi layout_init 0x00a8 0x00eb
+ftdi layout_signal nSRST -noe 0x0020
+ftdi layout_signal SWD_EN -ndata 0x0080
+ftdi layout_signal SWDIO_OE -data 0x0008
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/m53evk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/m53evk.cfg
new file mode 100644
index 0000000..2d9c304
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/m53evk.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# DENX M53EVK
+#
+# http://www.denx-cs.de/?q=M53EVK
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/mbftdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/mbftdi.cfg
new file mode 100644
index 0000000..09cec9f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/mbftdi.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# MBFTDI
+#
+# http://www.marsohod.org/prodmbftdi
+#
+# Also the Marsohod2 and the Marsohod3 boards
+# include a built-in MBFTDI for FPGA programming.
+# See http://www.marsohod.org/prodmarsohod2
+# and http://www.marsohod.org/plata-marsokhod3 for details.
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x000b
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/minimodule-swd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/minimodule-swd.cfg
new file mode 100644
index 0000000..3eb2f53
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/minimodule-swd.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Supports SWD using the FT2232H or FT4232H minimodule.
+# Each can support 2 SWD interfaces.
+#
+# FT2232H or FT4232H minimodule channel 0 (Channel A)
+# Connector  FTDI              Target
+# Pin        Name
+# ---------  ------            ------
+# CN2-11     VIO               VDD_IO (Or connect to CN2-5 on the minimodule instead for a 3V3 interface)
+# CN2-2      GND               GND
+# CN2-7      ADBUS0 (TCK)      SWCLK
+# CN2-9      ADBUS2 (TDI/TDO)  SWDIO
+# CN2-10     ADBUS1 (TDO/TDI)  SWDIO
+# CN2-14     ADBUS4 (GPIOL0)   nRESET
+#
+# FT2232H minimodule channel 1 (Channel B)
+# FTDI       Target
+# ----       ------
+# CN2-11  -  VDD_IO
+# CN2-2   -  GND
+# CN3-26  -  SWCLK
+# CN3-25  -  SWDIO
+# CN3-24  -  SWDIO
+# CN3-21  -  nRESET
+#
+# FT4232H minimodule channel 1 (Channel B)
+# FTDI       Target
+# ----       ------
+# CN2-11  -  VDD_IO
+# CN2-2   -  GND
+# CN2-18  -  SWCLK
+# CN2-17  -  SWDIO
+# CN2-20  -  SWDIO
+# CN2-22  -  nRESET
+#
+
+adapter driver ftdi
+
+#Select your module type and channel
+
+#ftdi device_desc "FT2232H MiniModule"
+ftdi vid_pid 0x0403 0x6010
+#ftdi channel 1
+
+#ftdi device_desc "FT4232H MiniModule"
+#ftdi vid_pid 0x0403 0x6011
+#ftdi channel 1
+
+ftdi layout_init 0x0000 0x000b
+ftdi layout_signal nSRST -data 0x0010 -oe 0x0010
+ftdi layout_signal SWD_EN -data 0
+ftdi layout_signal SWDIO_OE -data 0
+
+transport select swd
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/minimodule.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/minimodule.cfg
new file mode 100644
index 0000000..825d7c1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/minimodule.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# FTDI MiniModule
+#
+# http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf
+#
+
+adapter driver ftdi
+ftdi device_desc "FT2232H MiniModule"
+ftdi vid_pid 0x0403 0x6010
+
+# Every pin set as high impedance except TCK, TDI, TDO and TMS
+ftdi layout_init 0x0008 0x000b
+
+# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
+# This choice is arbitrary. Use other GPIO pin if desired.
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/minispartan6.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/minispartan6.cfg
new file mode 100644
index 0000000..f12bae6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/minispartan6.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# https://www.scarabhardware.com/minispartan6/
+# https://github.com/scarabhardware/miniSpartan6-plus/raw/master/miniSpartan6%2B_Rev_B.pdf
+adapter driver ftdi
+# The miniSpartan6+ sadly doesn't have a custom device description, so we just
+# have to hope you got it right.
+#ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+# interface 1 is the uart
+ftdi channel 0
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0008 0x000b
+reset_config none
+# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
+# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
+adapter speed 30000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/miniwiggler.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/miniwiggler.cfg
new file mode 100644
index 0000000..ebaa979
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/miniwiggler.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Infineon DAP miniWiggler V3
+#
+# https://www.infineon.com/cms/en/product/evaluation-boards/kit_miniwiggler_3_usb/
+#
+# Layout:  FTDI FT2232
+#   ADBUS0 TCK
+#   ADBUS1 TDI
+#   ADBUS2 TDO
+#   ADBUS3 TMS
+#   ADBUS4 nOE (output enable)
+#   ADBUS5
+#   ADBUS6
+#   ADBUS7 Blue LED
+#
+#   ACBUS0 nTRST
+#   ACBUS1 nSRST
+#   ACUBS2
+#   ACBUS3
+#   ACBUS4
+#   ACBUS5
+#   ACBUS6
+#   ACBUS7
+#
+
+adapter driver ftdi
+ftdi device_desc "DAS JDS miniWiggler V3.1"
+ftdi vid_pid 0x058b 0x0043
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal nSRST -data 0x0200 -oe 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/neodb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/neodb.cfg
new file mode 100644
index 0000000..d3b3541
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/neodb.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Openmoko USB JTAG/RS232 adapter
+#
+# http://wiki.openmoko.org/wiki/Debug_Board_v3
+#
+
+adapter driver ftdi
+ftdi device_desc "Debug Board for Neo1973"
+ftdi vid_pid 0x1457 0x5118
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
+ftdi layout_signal nNOR_WP -data 0x0010 -oe 0x0010
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ngxtech.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ngxtech.cfg
new file mode 100644
index 0000000..635333f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ngxtech.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NGX ARM USB JTAG
+#
+# http://shop.ngxtechnologies.com/product_info.php?cPath=26&products_id=30
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, but is assumed to work as this"
+echo "interface uses the same layout as configs that were verified. Please report your"
+echo "experience with this file to openocd-devel mailing list, so it could be marked"
+echo "as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NGX JTAG"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-jtag-cjtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-jtag-cjtag.cfg
new file mode 100644
index 0000000..6939d00
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-jtag-cjtag.cfg
@@ -0,0 +1,27 @@
+#
+# Olimex ARM JTAG SWD adapter
+# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
+#
+
+#
+# Olimex ARM-USB-TINY-H
+#
+# http://www.olimex.com/dev/arm-usb-tiny-h.html
+#
+
+interface ftdi
+ftdi oscan1_mode on
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi vid_pid 0x15ba 0x002a
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+# oscan1_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg
new file mode 100644
index 0000000..6aa13af
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM JTAG SWD adapter
+# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
+#
+
+transport select swd
+
+ftdi layout_signal SWD_EN -nalias nTRST
+ftdi layout_signal SWDIO_OE -alias TMS
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg
new file mode 100644
index 0000000..36ac587
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg
@@ -0,0 +1,22 @@
+#
+# Olimex ARM-USB-OCD-H (using cJTAG)
+#
+# http://www.olimex.com/dev/arm-usb-ocd-h.html
+#
+
+interface ftdi
+ftdi oscan1_mode on
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
+ftdi vid_pid 0x15ba 0x002b
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+# oscan1_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg
new file mode 100644
index 0000000..cd11ad8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-USB-OCD-H
+#
+# http://www.olimex.com/dev/arm-usb-ocd-h.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
+ftdi vid_pid 0x15ba 0x002b
+
+ftdi layout_init 0x0908 0x0b1b
+ftdi layout_signal nSRST -oe 0x0200
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal LED -data 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg
new file mode 100644
index 0000000..d2261e2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-USB-OCD
+#
+# http://www.olimex.com/dev/arm-usb-ocd.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Olimex OpenOCD JTAG"
+ftdi vid_pid 0x15ba 0x0003
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nSRST -oe 0x0200
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal LED -data 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg
new file mode 100644
index 0000000..13378b3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg
@@ -0,0 +1,27 @@
+#
+# Olimex ARM JTAG SWD adapter
+# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
+#
+
+#
+# Olimex ARM-USB-TINY-H (using cJTAG)
+#
+# http://www.olimex.com/dev/arm-usb-tiny-h.html
+#
+
+interface ftdi
+ftdi oscan1_mode on
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi vid_pid 0x15ba 0x002a
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+# oscan1_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg
new file mode 100644
index 0000000..a2b3e3e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-USB-TINY-H
+#
+# http://www.olimex.com/dev/arm-usb-tiny-h.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi vid_pid 0x15ba 0x002a
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-jtag-tiny.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-jtag-tiny.cfg
new file mode 100644
index 0000000..7d8e81d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/olimex-jtag-tiny.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-USB-TINY
+#
+# http://www.olimex.com/dev/arm-usb-tiny.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Olimex OpenOCD JTAG TINY"
+ftdi vid_pid 0x15ba 0x0004
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/oocdlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/oocdlink.cfg
new file mode 100644
index 0000000..0e99b67
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/oocdlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Joern Kaipf's OOCDLink
+#
+# http://www.joernonline.de/contrexx2/cms/index.php?page=126
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, but is assumed to work as this"
+echo "interface uses the same layout as configs that were verified. Please report your"
+echo "experience with this file to openocd-devel mailing list, so it could be marked"
+echo "as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "OOCDLink"
+ftdi vid_pid 0x0403 0xbaf8
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/opendous_ftdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/opendous_ftdi.cfg
new file mode 100644
index 0000000..5d6f5ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/opendous_ftdi.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Opendous
+#
+# http://code.google.com/p/opendous/wiki/JTAG
+#
+# According to the website, it is similar to jtagkey, but it uses channel B
+# (and it has a different pid number).
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 1
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/openocd-usb-hs.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/openocd-usb-hs.cfg
new file mode 100644
index 0000000..af1f61c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/openocd-usb-hs.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# embedded projects openocd usb adapter v3
+#
+# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/openocd-usb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/openocd-usb.cfg
new file mode 100644
index 0000000..c333d65
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/openocd-usb.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hubert Hoegl's USB to JTAG
+#
+# http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/openrd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/openrd.cfg
new file mode 100644
index 0000000..b6b2d1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/openrd.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marvell OpenRD
+#
+# http://www.marvell.com/products/embedded_processors/developer/kirkwood/openrd.jsp
+#
+
+adapter driver ftdi
+ftdi device_desc "OpenRD JTAGKey FT2232D B"
+ftdi vid_pid 0x0403 0x9e90
+ftdi channel 0
+
+ftdi layout_init 0x0608 0x0f1b
+ftdi layout_signal nTRST -data 0x0200
+ftdi layout_signal nSRST -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/pipistrello.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/pipistrello.cfg
new file mode 100644
index 0000000..29ecd12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/pipistrello.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://pipistrello.saanlima.com/
+# http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdf
+adapter driver ftdi
+ftdi device_desc "Pipistrello LX45"
+ftdi vid_pid 0x0403 0x6010
+# interface 1 is the uart
+ftdi channel 0
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0008 0x000b
+reset_config none
+# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
+# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
+adapter speed 10000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/pls_spc5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/pls_spc5.cfg
new file mode 100644
index 0000000..3b3c2d6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/pls_spc5.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# PLS SPC5-UDESTK
+#
+# https://www.st.com/en/development-tools/spc5-udestk.html
+#
+# Reference the SPC56D Discovery schematics.
+#
+# Layout:  FTDI FT2232
+#   ADBUS0 TCK
+#   ADBUS1 TDI
+#   ADBUS2 TDO
+#   ADBUS3 TMS
+#   ADBUS4 TMS
+#   ADBUS5 RTCK
+#   ADBUS6
+#   ADBUS7 LED1
+#
+#   ACBUS0 nTRST
+#   ACBUS1 nSRST (external pull-down)
+#   ACUBS2
+#   ACBUS3
+#   ACBUS4
+#   ACBUS5 nSRST direction (input=L, output=H, external pull-down)
+#   ACBUS6 TMS direction (input=L, output=H, external pull-up)
+#   ACBUS7 LED2
+#
+
+adapter driver ftdi
+ftdi device_desc "PLS USB/JTAG Adapter for SPC5xxx"
+ftdi vid_pid 0x263d 0x4001
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal nSRST -ndata 0x2000 -oe 0x2000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/redbee-econotag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/redbee-econotag.cfg
new file mode 100644
index 0000000..d0d3d83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/redbee-econotag.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Redwire Redbee-Econotag
+#
+# http://www.redwirellc.com/store/node/1
+#
+# The Redbee-Econotag has an onboard FT2232H with:
+#  - FT2232H channel A wired to mc13224v JTAG
+#  - FT2232H channel B wired to mc13224v UART1
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0c08 0x0c2b
+ftdi layout_signal nTRST -data 0x0800
+ftdi layout_signal nSRST -data 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/redbee-usb.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/redbee-usb.cfg
new file mode 100644
index 0000000..9880553
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/redbee-usb.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Redwire Redbee-USB
+#
+# http://www.redwirellc.com
+#
+# The Redbee-USB has an onboard FT2232H with:
+#  - FT2232H channel B wired to mc13224v JTAG
+#  - FT2232H channel A wired to mc13224v UART1
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 1
+
+ftdi layout_init 0x0c08 0x0c2b
+ftdi layout_signal nTRST -data 0x0800
+ftdi layout_signal nSRST -data 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/rowley-cc-arm-swd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/rowley-cc-arm-swd.cfg
new file mode 100644
index 0000000..585d589
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/rowley-cc-arm-swd.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Rowley ARM SWD Adapter
+# http://sites.fastspring.com/rowley/product/armswdadapter
+# https://drive.google.com/file/d/0Bzv7UpKpOQhnTUNNdzI5OUR4WGs/edit?usp=sharing
+#
+
+transport select swd
+
+ftdi layout_signal SWD_EN -nalias nTRST
+ftdi layout_signal SWDIO_OE -alias TMS
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/sheevaplug.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/sheevaplug.cfg
new file mode 100644
index 0000000..29c8688
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/sheevaplug.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marvel SheevaPlug Development Kit
+#
+# http://www.marvell.com/products/embedded_processors/developer/kirkwood/sheevaplug.jsp
+#
+
+adapter driver ftdi
+ftdi device_desc "SheevaPlug JTAGKey FT2232D B"
+ftdi vid_pid 0x9e88 0x9e8f
+ftdi channel 0
+
+ftdi layout_init 0x0608 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/signalyzer-lite.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/signalyzer-lite.cfg
new file mode 100644
index 0000000..e6c3839
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/signalyzer-lite.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xverve Signalyzer LITE (DT-USB-SLITE)
+#
+# http://www.signalyzer.com
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Signalyzer LITE"
+ftdi vid_pid 0x0403 0xbca1
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/signalyzer.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/signalyzer.cfg
new file mode 100644
index 0000000..fa7a7ed
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/signalyzer.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xverve Signalyzer Tool (DT-USB-ST)
+#
+# http://www.signalyzer.com
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Signalyzer"
+ftdi vid_pid 0x0403 0xbca0
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/sipeed-rv-debugger.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/sipeed-rv-debugger.cfg
new file mode 100644
index 0000000..ca65398
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/sipeed-rv-debugger.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Interface file for BL702-based SIPEED RV Debugger
+#
+
+adapter driver ftdi
+adapter speed 6000
+
+ftdi device_desc "JTAG Debugger"
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/sipeed-usb-jtag-debugger.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/sipeed-usb-jtag-debugger.cfg
new file mode 100644
index 0000000..8a804ec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/sipeed-usb-jtag-debugger.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Sipeed USB-JTAG/TTL RISC-V Debugger
+#
+# https://www.seeedstudio.com/Sipeed-USB-JTAG-TTL-RISC-V-Debugger-p-2910.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232"
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+
+# Every pin set as high impedance except TCK, TDI, TDO, TMS and RST
+ftdi layout_init 0x0028 0x002b
+
+transport select jtag
+
+# nSRST defined on pin RST of the Debugger (pin ADBUS5 [AD5] on the FT2232D chip)
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/snps_sdp.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/snps_sdp.cfg
new file mode 100644
index 0000000..eb2aecc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/snps_sdp.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys SDP Mainboard has embdded FT2232 chip, which is similar to Digilent
+# HS-1, except that it uses channel B for JTAG communication, instead of
+# channel A.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x0088 0x008b
+ftdi channel 1
+
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/steppenprobe.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/steppenprobe.cfg
new file mode 100644
index 0000000..f84efe6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/steppenprobe.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Steppenprobe
+# https://github.com/diegoherranz/steppenprobe
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+# Initial Layout
+ftdi layout_init 0x0058 0x99fb
+# Signal        Data    Direction       Notes
+# TCK           0       1 (out)
+# TDI           0       1 (out)
+# TDO           0       0 (in)
+# TMS           1       1 (out)         JTAG IEEE std recommendation
+# LED           1       1 (out)         LED off
+# SWD_EN        0       1 (out)         OpenOCD sets this high for SWD
+# SWDIO_OE      1       1 (out)         Ext. buffer tristated
+# SRST          0       1 (out)         Translates to nSRST=Z
+
+# Unused        0       1 (out)
+# GPIO_A        0       0 (in)
+# GPIO_B        0       0 (in)
+# Unused        0       1 (out)
+# Unused        0       1 (out)
+# GPIO_C        0       0 (in)
+# GPIO_D        0       0 (in)
+# Unused        0       1 (out)
+
+# Signals definition
+ftdi layout_signal LED -ndata 0x0010
+ftdi layout_signal SWD_EN -data 0x0020
+ftdi layout_signal SWDIO_OE -ndata 0x0040
+ftdi layout_signal nSRST -oe 0x0080
+
+ftdi layout_signal GPIO_A -data 0x0200 -oe 0x0200 -input 0x0200
+ftdi layout_signal GPIO_B -data 0x0400 -oe 0x0400 -input 0x0400
+ftdi layout_signal GPIO_C -data 0x2000 -oe 0x2000 -input 0x2000
+ftdi layout_signal GPIO_D -data 0x4000 -oe 0x4000 -input 0x4000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/stm32-stick.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/stm32-stick.cfg
new file mode 100644
index 0000000..1d72d20
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/stm32-stick.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hitex STM32-PerformanceStick
+#
+# http://www.hitex.com/index.php?id=340
+#
+
+adapter driver ftdi
+ftdi device_desc "STM32-PerformanceStick"
+ftdi vid_pid 0x0640 0x002d
+
+ftdi layout_init 0x0388 0x038b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0080 -noe 0x200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/swd-resistor-hack.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/swd-resistor-hack.cfg
new file mode 100644
index 0000000..d9e7158
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/swd-resistor-hack.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Connect TDI to SWDIO via a suitable series resistor (220-470 Ohm or
+# so depending on the drive capability of the target and adapter);
+# connect TDO directly to SWDIO.
+#
+# You also need to have reliable GND connection between the target and
+# adapter. Vref of the adapter should be supplied with a voltage equal
+# to the target's (preferably connect it to Vcc). You can also
+# optionally connect nSRST. Leave everything else unconnected.
+#
+# FTDI                          Target
+# ----                          ------
+# 1  - Vref   ----------------- Vcc
+# 3  - nTRST  -
+# 4  - GND    ----------------- GND
+# 5  - TDI    ---/\470 Ohm/\--- SWDIO
+# 7  - TMS    -
+# 9  - TCK    ----------------- SWCLK
+# 11 - RTCK   -
+# 13 - TDO    ----------------- SWDIO
+# 15 - nSRST  - - - - - - - - - nRESET
+#
+
+transport select swd
+
+ftdi layout_signal SWD_EN -data 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ti-icdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ti-icdi.cfg
new file mode 100644
index 0000000..964de76
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/ti-icdi.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is an FTDI-based debugging solution as found on some TI boards,
+# e.g. CC3200 LaunchPad.
+#
+# The schematics are identical to luminary-icdi (including SWD
+# support) but the USB IDs are different.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0451 0xc32a
+
+ftdi layout_init 0x00a8 0x00eb
+ftdi layout_signal nSRST -noe 0x0020
+ftdi layout_signal SWD_EN -ndata 0x0080
+ftdi layout_signal SWDIO_OE -data 0x0008
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/tigard.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/tigard.cfg
new file mode 100644
index 0000000..43ce0ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/tigard.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Tigard: An FTDI FT2232H-based multi-protocol tool for hardware hacking.
+# https://github.com/tigard-tools/tigard
+
+adapter driver ftdi
+
+ftdi device_desc "Tigard V1.1"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 1
+
+ftdi layout_init 0x0038 0x003b
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -data 0x0020
+
+# This board doesn't support open-drain reset modes since its output buffer is
+# always enabled.
+reset_config srst_push_pull trst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/tumpa-lite.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/tumpa-lite.cfg
new file mode 100644
index 0000000..e3f12e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/tumpa-lite.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TIAO USB Multi-Protocol Adapter (TUMPA) Lite
+#
+# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-lite-jtag-spi-i2c-serial.html
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x8a99
+
+ftdi layout_init 0x0038 0x087b
+ftdi layout_signal nTRST -data 0x0020 -oe 0x0020
+ftdi layout_signal nSRST -data 0x0010 -oe 0x0010
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/tumpa.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/tumpa.cfg
new file mode 100644
index 0000000..db4311b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/tumpa.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TIAO USB Multi-Protocol Adapter (TUMPA)
+#
+# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-jtag-spi-i2c-serial.html
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x8a98 0x0403 0x6010
+
+ftdi layout_init 0x0038 0x087b
+ftdi layout_signal nTRST -data 0x0020
+ftdi layout_signal nSRST -data 0x0010
+
+reset_config srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/turtelizer2-revB.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/turtelizer2-revB.cfg
new file mode 100644
index 0000000..f90fc58
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/turtelizer2-revB.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# egnite Turtelizer 2 rev B (with SRST only)
+#
+# http://www.ethernut.de/en/hardware/turtelizer/index.html
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on schematics and code"
+echo "in ft2232.c. Please report your experience with this file to openocd-devel"
+echo "mailing list, so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Turtelizer JTAG/RS232 Adapter"
+ftdi vid_pid 0x0403 0xbdc8
+
+ftdi layout_init 0x0008 0x0c5b
+ftdi layout_signal nSRST -oe 0x0040
+ftdi layout_signal LED -data 0x0c00
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/turtelizer2-revC.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/turtelizer2-revC.cfg
new file mode 100644
index 0000000..94617a1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/turtelizer2-revC.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# egnite Turtelizer 2 revC (with TRST and SRST)
+#
+# http://www.ethernut.de/en/hardware/turtelizer/index.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Turtelizer JTAG/RS232 Adapter"
+ftdi vid_pid 0x0403 0xbdc8
+
+ftdi layout_init 0x0008 0x0c7b
+ftdi layout_signal nTRST -oe 0x0020
+ftdi layout_signal nSRST -oe 0x0040
+ftdi layout_signal LED -ndata 0x0c00
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/um232h.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/um232h.cfg
new file mode 100644
index 0000000..6be08b5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/um232h.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# FTDI UM232H as a JTAG interface
+#
+# http://www.ftdichip.com/Products/Modules/DevelopmentModules.htm#UM232H
+#
+# This should also work with a UM232H-B, but that has not been tested.
+# Note that UM232H and UM232H-B are 3.3V only.
+#
+
+adapter driver ftdi
+#ftdi device_desc "UM232H"
+ftdi vid_pid 0x0403 0x6014
+
+ftdi layout_init 0xfff8 0xfffb
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal nSRST -data 0x0200 -oe 0x0200
+
+# UM232H        FT232H    JTAG
+# Name  Pin     Name      Func
+# AD0   J2-6    ADBUS0    TCK
+# AD1   J2-7    ADBUS1    TDI
+# AD2   J2-8    ADBUS2    TDO
+# AD3   J2-9    ADBUS3    TMS
+# AD4   J2-10   ADBUS4    (GPIOL0)
+# AD5   J2-11   ADBUS5    (GPIOL1)
+# AD6   J2-12   ADBUS6    (GPIOL2)
+# AD7   J2-13   ADBUS7    (GPIOL3)
+# AD0   J1-14   ACBUS0    /TRST
+# AD1   J1-13   ACBUS1    /SRST
+# AD2   J1-12   ACBUS2    (GPIOH2)
+# AD3   J1-11   ACBUS3    (GPIOH3)
+# AD4   J1-10   ACBUS4    (GPIOH4)
+# AD5   J1-9    ACBUS5    (GPIOH5)
+# AD6   J1-8    ACBUS6    (GPIOH6)
+# AD7   J1-7    ACBUS7    (GPIOH7)
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/vpaclink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/vpaclink.cfg
new file mode 100644
index 0000000..ff508f2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/vpaclink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Voipac VPACLink
+#
+# http://voipac.com/27M-JTG-000
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, but is assumed to work as this"
+echo "interface uses the same layout as configs that were verified. Please report your"
+echo "experience with this file to openocd-devel mailing list, so it could be marked"
+echo "as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "VPACLink"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/xds100v2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/xds100v2.cfg
new file mode 100644
index 0000000..373df4f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/xds100v2.cfg
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments XDS100v2
+#
+# http://processors.wiki.ti.com/index.php/XDS100#XDS100v2_Features
+#
+# Detailed documentation is available only as CPLD verilog source code
+# to the registered TI users.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0xa6d0 0x0403 0x6010
+
+ftdi layout_init 0x0038 0x597b
+
+#  8000 z - unused
+#  4000 0 > CPLD loopback          (all target side pins high-Z)
+#  2000 z < !( cable connected )   (open drain on CPLD side for $reasons)
+#  1000 0 > EMU1_oe
+#
+#   800 0 > PWR_RST = clear power-loss flag on rising edge
+#   400 z < !( power-loss flag )
+#   200 z < nSRST
+#   100 0 > nSRST_oe
+#
+#    80 z < RTCK
+#    40 0 > EMU0_oe
+#    20 1 > EMU_EN
+#    10 1 > nTRST
+#
+#     8 1 > TMS
+#     4 z < TDO
+#     2 0 > TDI
+#     1 0 > TCK
+#
+# As long as the power-loss flag is set, all target-side pins are
+# high-Z except the EMU-pins for which the opposite holds unless
+# EMU_EN is high.
+#
+# To use wait-in-reset, drive EMU0 low at power-on reset. If the
+# target normally reuses EMU0 for other purposes, clear EMU_EN to
+# keep the EMU pins high-Z until the target is power-cycled.
+#
+# The LED only turns off at USB suspend, which is also the only way to
+# set the power-loss flag manually. (Can be done in software e.g. by
+# changing the USB configuration to zero.)
+#
+
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -oe 0x0100
+ftdi layout_signal EMU_EN -data 0x0020
+ftdi layout_signal EMU0 -oe 0x0040
+ftdi layout_signal EMU1 -oe 0x1000
+ftdi layout_signal PWR_RST -data 0x0800
+ftdi layout_signal LOOPBACK -data 0x4000
+
+echo "\nInfo : to use this adapter you MUST add ``init; ftdi set_signal PWR_RST 1; jtag arp_init'' to the end of your config file!\n"
+# note: rising edge on PWR_RST is also needed after power-cycling the
+# target
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/xds100v3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/xds100v3.cfg
new file mode 100644
index 0000000..dc72233
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/xds100v3.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments XDS100 ver 3.0
+#
+# http://processors.wiki.ti.com/index.php/XDS100
+#
+
+# Version 3.0 is the same as 2.0 as far as OpenOCD is concerned
+source [find interface/ftdi/xds100v2.cfg]
+
+# The USB ids are different.
+ftdi vid_pid 0x0403 0xa6d1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/xt_kc705_ml605.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/xt_kc705_ml605.cfg
new file mode 100644
index 0000000..dda8c0a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ftdi/xt_kc705_ml605.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Xilinx KC705 / ML605 with Xtensa daughtercard; onboard USB/FT2232
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+# Specify "adapter serial " here as needed
+
+ftdi layout_init 0x0010 0x007b
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -ndata 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/imx-native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/imx-native.cfg
new file mode 100644
index 0000000..01e42e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/imx-native.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Config for using NXP IMX CPU
+#
+# This is best used with a fast enough buffer but also
+# is suitable for direct connection if the target voltage
+# matches to host voltage and the cable is short enough.
+#
+#
+
+adapter driver imx_gpio
+
+# For most IMX processors 0x0209c000
+imx_gpio_peripheral_base 0x0209c000
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on system clock, calibrated for IMX6UL@528MHz
+# imx_gpio_speed SPEED_COEFF SPEED_OFFSET
+imx_gpio_speed_coeffs 50000 50
+
+# Each of the JTAG lines need a gpio number set: tck tms tdi tdo.
+# Example configuration:
+# imx_gpio_jtag_nums 6 7 8 9
+
+# SWD interface pins: swclk swdio
+# Example configuration:
+imx_gpio_swd_nums 1 6
+
+# imx_gpio_trst_num 10
+# reset_config trst_only
+
+# imx_gpio_srst_num 11
+# reset_config srst_only srst_push_pull
+
+# or if you have both connected,
+# reset_config trst_and_srst srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jlink.cfg
new file mode 100644
index 0000000..181c2cc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jlink.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# SEGGER J-Link
+#
+# http://www.segger.com/jlink.html
+#
+
+adapter driver jlink
+
+# The serial number can be used to select a specific device in case more than
+# one is connected to the host.
+#
+# Example: Select J-Link with serial number 123456789
+#
+# adapter serial 123456789
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jtag_dpi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jtag_dpi.cfg
new file mode 100644
index 0000000..225d4d5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jtag_dpi.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Provide support for the Cadence JTAG BFM
+#
+# Copyright (c) 2020, Ampere Computing LLC
+#
+
+adapter driver jtag_dpi
+
+# Set the DPI JTAG server port
+if { [info exists DPI_PORT] } {
+   set _DPI_PORT $DPI_PORT
+} else {
+   set _DPI_PORT 5555
+}
+
+# Set the DPI JTAG server address
+if { [info exists DPI_ADDRESS] } {
+   set _DPI_ADDRESS $DPI_ADDRESS
+} else {
+   set _DPI_ADDRESS "127.0.0.1"
+}
+
+jtag_dpi set_port $_DPI_PORT
+jtag_dpi set_address $_DPI_ADDRESS
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jtag_hat_rpi2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jtag_hat_rpi2.cfg
new file mode 100644
index 0000000..cd1cbfb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jtag_hat_rpi2.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Blinkinlabs JTAG_Hat
+#
+# https://github.com/blinkinlabs/jtag_hat
+#
+
+adapter driver bcm2835gpio
+
+bcm2835gpio peripheral_base 0x3F000000
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on system clock, calibrated for stock 700MHz
+# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET
+bcm2835gpio speed_coeffs 146203 36
+
+# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
+# Header pin numbers: 23 22 19 21
+adapter gpio tck -chip 0 11
+adapter gpio tms -chip 0 25
+adapter gpio tdi -chip 0 10
+adapter gpio tdo -chip 0 9
+
+# Each of the SWD lines need a gpio number set: swclk swdio
+# Header pin numbers: 23 22
+adapter gpio swclk -chip 0 11
+adapter gpio swdio -chip 0 25
+
+# Direction pin for SWDIO level shifting buffer
+adapter gpio swdio_dir -chip 0 6
+
+# If you define trst or srst, use appropriate reset_config
+# Header pin numbers: TRST - 26, SRST - 18
+
+adapter gpio trst -chip 0 7
+#reset_config trst_only
+
+adapter gpio srst -chip 0 24
+#reset_config srst_only
+
+# or if you have both connected
+#reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jtag_vpi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jtag_vpi.cfg
new file mode 100644
index 0000000..e8164ab
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/jtag_vpi.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter driver jtag_vpi
+
+# Set the VPI JTAG server port
+if { [info exists VPI_PORT] } {
+   set _VPI_PORT $VPI_PORT
+} else {
+   set _VPI_PORT 5555
+}
+
+# Set the VPI JTAG server address
+if { [info exists VPI_ADDRESS] } {
+   set _VPI_ADDRESS $VPI_ADDRESS
+} else {
+   set _VPI_ADDRESS "127.0.0.1"
+}
+
+jtag_vpi set_port $_VPI_PORT
+jtag_vpi set_address $_VPI_ADDRESS
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/kitprog.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/kitprog.cfg
new file mode 100644
index 0000000..eb9ad98
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/kitprog.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Cypress Semiconductor KitProg
+#
+# Note: This is the driver for the proprietary KitPtog protocol. If the
+# KitProg is in CMSIS-DAP mode, you should either use the cmsis-dap
+# interface driver or switch the KitProg to KitProg mode.
+#
+
+adapter driver kitprog
+
+# Optionally specify the serial number of the KitProg you want to use.
+# adapter serial 1926402735485200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/nulink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/nulink.cfg
new file mode 100644
index 0000000..48dc20e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/nulink.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nuvoton Nu-Link in-circuit debugger/programmer
+#
+
+adapter driver hla
+hla layout nulink
+hla device_desc "Nu-Link"
+hla vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201
+
+# Only swd is supported
+transport select hla_swd
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/opendous.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/opendous.cfg
new file mode 100644
index 0000000..9c5a804
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/opendous.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# opendous-jtag
+#
+# http://code.google.com/p/opendous-jtag/
+#
+
+adapter driver opendous
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/openjtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/openjtag.cfg
new file mode 100644
index 0000000..1602352
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/openjtag.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# OpenJTAG
+#
+# www.openjtag.org
+#
+
+adapter driver openjtag
+openjtag device_desc "Open JTAG Project"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/osbdm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/osbdm.cfg
new file mode 100644
index 0000000..e21848d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/osbdm.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# P&E Micro OSBDM (aka OSJTAG) interface
+#
+# http://pemicro.com/osbdm/
+#
+adapter driver osbdm
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport.cfg
new file mode 100644
index 0000000..8fb1c14
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Parallel port wiggler (many clones available) on port 0x378
+#
+# Addresses: 0x378/LPT1 or 0x278/LPT2 ...
+#
+echo "DEPRECATED: use interface/parport/wiggler.cfg instead of deprecated interface/parport.cfg"
+
+source [find interface/parport/wiggler.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport/dlc5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport/dlc5.cfg
new file mode 100644
index 0000000..24acea7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport/dlc5.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xilinx Parallel Cable III 'DLC 5' (and various clones)
+#
+# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html
+#
+
+if { [info exists PARPORTADDR] } {
+   set _PARPORTADDR $PARPORTADDR
+} else {
+   set _PARPORTADDR 0
+}
+
+adapter driver parport
+parport port $_PARPORTADDR
+parport cable dlc5
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport/wiggler.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport/wiggler.cfg
new file mode 100644
index 0000000..b9fceeb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport/wiggler.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Parallel port wiggler (many clones available) on port 0x378
+#
+# Addresses: 0x378/LPT1 or 0x278/LPT2 ...
+#
+
+if { [info exists PARPORTADDR] } {
+   set _PARPORTADDR $PARPORTADDR
+} else {
+   if {$tcl_platform(platform) eq "windows"} {
+      set _PARPORTADDR 0x378
+   } {
+      set _PARPORTADDR 0
+   }
+}
+
+adapter driver parport
+parport port $_PARPORTADDR
+parport cable wiggler
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport_dlc5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport_dlc5.cfg
new file mode 100644
index 0000000..83f3b56
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/parport_dlc5.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xilinx Parallel Cable III 'DLC 5' (and various clones)
+#
+# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html
+#
+echo "DEPRECATED: use interface/parport/dlc5.cfg instead of deprecated interface/parport_dlc5.cfg"
+
+source [find interface/parport/dlc5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi-gpio-connector.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi-gpio-connector.cfg
new file mode 100644
index 0000000..af7266b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi-gpio-connector.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Config for Raspberry Pi GPIO header
+#
+# This is best used with a fast enough buffer but also
+# is suitable for direct connection if the target voltage
+# matches RPi's 3.3V and the cable is short enough.
+#
+# Do not forget the GND connection, e.g. pin 20 of the GPIO header.
+#
+
+if { [info exists GPIO_CHIP] } {
+    set _GPIO_CHIP $GPIO_CHIP
+} else {
+    set _GPIO_CHIP 0
+}
+
+# GPIO 25 (pin 22) previously used for TMS/SWDIO is pulled-down by default.
+# The JTAG/SWD specification requires pull-up at the target board
+# for either signal. Connecting the signal pulled-up on the target
+# to the pull-down on the adapter is not a good idea.
+# GPIO 8 is pulled-up by default.
+echo "Warn : TMS/SWDIO moved to GPIO 8 (pin 24). Check the wiring please!"
+
+# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
+# Header pin numbers: 23 24 19 21
+adapter gpio tck -chip $_GPIO_CHIP 11
+adapter gpio tms -chip $_GPIO_CHIP 8
+adapter gpio tdi -chip $_GPIO_CHIP 10
+adapter gpio tdo -chip $_GPIO_CHIP 9
+
+# Each of the SWD lines need a gpio number set: swclk swdio
+# Header pin numbers: 23 24
+adapter gpio swclk -chip $_GPIO_CHIP 11
+adapter gpio swdio -chip $_GPIO_CHIP 8
+
+# If you define trst or srst, use appropriate reset_config
+# Header pin numbers: TRST - 26, SRST - 18
+
+# adapter gpio trst -chip $_GPIO_CHIP 7
+# reset_config trst_only
+
+# adapter gpio srst -chip $_GPIO_CHIP 24
+# reset_config srst_only srst_push_pull
+
+# or if you have both connected,
+# reset_config trst_and_srst srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi-native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi-native.cfg
new file mode 100644
index 0000000..c80f90a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi-native.cfg
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Raspberry Pi used as a bitbang adapter.
+# https://www.raspberrypi.com/documentation/computers/raspberry-pi.html
+
+# Supports all models with 40-pin or 26-pin GPIO connector up to Raspberry Pi 4 B
+# also supports Raspberry Pi Zero, Zero W and Zero 2 W.
+
+# Adapter speed calibration is computed from cpufreq/scaling_max_freq.
+# Adjusts automatically if CPU is overclocked.
+
+adapter driver bcm2835gpio
+
+proc read_file { name } {
+	if {[catch {open $name r} fd]} {
+		return ""
+	}
+	set result [read $fd]
+	close $fd
+	return $result
+}
+
+proc measure_clock {} {
+	set result [exec vcgencmd measure_clock arm]
+	set clock_hz [lindex [split $result "="] 1]
+	expr { $clock_hz / 1000 }
+}
+
+proc get_max_cpu_clock { default } {
+	set clock [read_file /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq]
+	if { $clock > 100000 } {
+		return $clock
+	}
+
+	# cpufreq not available. As the last resort try Broadcom's proprietary utility
+	if {![catch measure_clock clock] && $clock > 100000} {
+		return $clock
+	}
+
+	echo "Warn : Host CPU clock unknown."
+	echo "Warn : Using the highest possible value $default kHz as a safe default."
+	echo "Warn : Expect JTAG/SWD clock significantly slower than requested."
+
+	return $default
+}
+
+set compat [read_file /proc/device-tree/compatible]
+set clocks_per_timing_loop 4
+
+if {[string match *bcm2711* $compat]} {
+	set speed_offset 52
+} elseif {[string match *bcm2837* $compat] || [string match *bcm2710* $compat]} {
+	set speed_offset 34
+} elseif {[string match *bcm2836* $compat] || [string match *bcm2709* $compat]} {
+	set speed_offset 36
+} elseif {[string match *bcm2835* $compat] || [string match *bcm2708* $compat]} {
+	set clocks_per_timing_loop 6
+	set speed_offset 32
+} elseif {[string match *bcm2712* $compat]} {
+	echo "Error: Raspberrypi Pi 5 has moved GPIOs to PCIe connected RP1 chip."
+	echo "Error: Native GPIO handling is not supported, use 'raspberrypi5-gpiod.cfg'"
+	shutdown
+} else {
+	set speed_offset 32
+	echo "Warn : Unknown type of the host SoC. Expect JTAG/SWD clock slower than requested."
+}
+
+set clock [get_max_cpu_clock 2000000]
+set speed_coeff [expr { $clock / $clocks_per_timing_loop }]
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# The coefficients depend on system clock and CPU frequency scaling.
+bcm2835gpio speed_coeffs $speed_coeff $speed_offset
+
+source [find interface/raspberrypi-gpio-connector.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi2-native.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi2-native.cfg
new file mode 100644
index 0000000..fe9186f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi2-native.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/raspberrypi2-native.cfg is deprecated."
+echo "WARNING: Please use interface/raspberrypi-native.cfg for all Raspberry Pi models."
+
+source [find interface/raspberrypi-native.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi5-gpiod.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi5-gpiod.cfg
new file mode 100644
index 0000000..9624ad5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/raspberrypi5-gpiod.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Raspberry Pi 5 used as a bitbang adapter.
+# https://www.raspberrypi.com/documentation/computers/raspberry-pi.html
+
+# Raspberry Pi 5 is not compatible with bcm2835gpio native GPIO driver.
+# The linuxgpiod driver without configurable adapter speed runs at approximately
+# 800 kHz (SWD writes) and 360 kHz (SWD reads)
+
+adapter driver linuxgpiod
+
+proc read_file { name } {
+	if {[catch {open $name r} fd]} {
+		return ""
+	}
+	set result [read $fd]
+	close $fd
+	return $result
+}
+
+set pcie_aspm [read_file /sys/module/pcie_aspm/parameters/policy]
+if {![string match {*\[performance\]*} $pcie_aspm]} {
+	echo "Warn : Switch PCIe power saving off or the first couple of pulses gets clocked as fast as 20 MHz"
+	echo "Warn : Issue 'echo performance | sudo tee /sys/module/pcie_aspm/parameters/policy'"
+}
+
+set GPIO_CHIP 4
+source [find interface/raspberrypi-gpio-connector.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/rlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/rlink.cfg
new file mode 100644
index 0000000..7671a3b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/rlink.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Raisonance RLink
+#
+# http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html
+#
+
+adapter driver rlink
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/rshim.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/rshim.cfg
new file mode 100644
index 0000000..1d5da59
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/rshim.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# BlueField SoC in-circuit debugger/programmer
+#
+
+adapter driver rshim
+transport select dapdirect_swd
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-dap.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-dap.cfg
new file mode 100644
index 0000000..009fdb7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-dap.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/stlink-dap.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-hla.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-hla.cfg
new file mode 100644
index 0000000..5c4adb8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-hla.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
+# debugger/programmer
+#
+
+echo "DEPRECATED: OpenOCD support for ST-Link HLA transport will be dropped soon!"
+echo "Consider updating your ST-Link firmware to a version >= V2J24 (2015)"
+
+adapter driver hla
+hla layout stlink
+hla device_desc "ST-LINK"
+hla vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
+
+# Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2
+# devices seem to have serial numbers with unreadable characters.  ST-LINK/V2
+# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
+# number reset issues.
+# eg.
+# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-v1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-v1.cfg
new file mode 100644
index 0000000..96ed088
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-v1.cfg
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/stlink-v1.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-v2-1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-v2-1.cfg
new file mode 100644
index 0000000..d2baad4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-v2-1.cfg
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-v2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-v2.cfg
new file mode 100644
index 0000000..400411e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink-v2.cfg
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink.cfg
new file mode 100644
index 0000000..99c81c1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/stlink.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
+# debugger/programmer
+#
+# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect"
+# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect"
+#
+# SWIM transport is natively supported
+#
+
+adapter driver st-link
+st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
+
+# transport select dapdirect_jtag
+# transport select dapdirect_swd
+# transport select swim
+
+# Optionally specify the serial number of usb device
+# e.g.
+# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/sysfsgpio-raspberrypi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/sysfsgpio-raspberrypi.cfg
new file mode 100644
index 0000000..d2095a9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/sysfsgpio-raspberrypi.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Config for using RaspberryPi's expansion header
+#
+# This is best used with a fast enough buffer but also
+# is suitable for direct connection if the target voltage
+# matches RPi's 3.3V
+#
+# Do not forget the GND connection, pin 6 of the expansion header.
+#
+
+adapter driver sysfsgpio
+
+# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
+# Header pin numbers: 23 22 19 21
+sysfsgpio jtag_nums 11 25 10 9
+
+# Each of the SWD lines need a gpio number set: swclk swdio
+# Header pin numbers: 23 22
+sysfsgpio swd_nums 11 25
+
+# If you define trst or srst, use appropriate reset_config
+# Header pin numbers: TRST - 26, SRST - 18
+
+# sysfsgpio trst_num 7
+# reset_config trst_only
+
+# sysfsgpio srst_num 24
+# reset_config srst_only srst_push_pull
+
+# or if you have both connected,
+# reset_config trst_and_srst srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ti-icdi.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ti-icdi.cfg
new file mode 100644
index 0000000..c13d27e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ti-icdi.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Stellaris In-Circuit Debug Interface (ICDI) Board
+#
+# This is the propriety ICDI interface used on newer boards such as
+# LM4F232 Evaluation Kit - http://www.ti.com/tool/ek-lm4f232
+# Stellaris Launchpad - http://www.ti.com/stellaris-launchpad
+# http://www.ti.com/tool/ek-lm4f232
+#
+
+adapter driver hla
+hla layout ti-icdi
+hla vid_pid 0x1cbe 0x00fd
+
+# Optionally specify the serial number of TI-ICDI devices, for when using
+# multiple devices. Serial numbers can be obtained using lsusb -v
+# Ex.
+# adapter serial "0F003065"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ulink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ulink.cfg
new file mode 100644
index 0000000..89a02e9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/ulink.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Keil ULINK running OpenULINK firmware.
+#
+# http://www.keil.com/ulink1/
+# http://article.gmane.org/gmane.comp.debugging.openocd.devel/17362
+#
+
+adapter driver ulink
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/usb-jtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/usb-jtag.cfg
new file mode 100644
index 0000000..039c748
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/usb-jtag.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ixo-usb-jtag - Emulation of a Altera Bus Blaster I on a Cypress FX2 IC.
+#
+# The ixo-usb-jtag firmware can be loaded onto a bunch of different hardware
+# including;
+#  * Xilinx USB Platform Cable
+#  * Many Digilent boards such as the Nexys, Nexys 2 and Atlys boards
+#  * Many fpga4fun.com boards from such as the Saxo and Xylo boards
+#  * The Numato Opsis
+#
+# Original version - http://www.ixo.de/info/usb_jtag/
+#  Updated version - http://ixo-jtag.sourceforge.net/
+#   Newest version - http://github.com/mithro/ixo-usb-jtag
+#
+# Procedure for using is;
+#  * Get the ixo-usb-jtag firmware for your hardware (or build it yourself).
+#  * Load the firmware using the fxload tool.
+#  * Use openocd.
+#
+# Unless you burn the firmware into the EEPROM on your device, power cycling
+# will require you to reload the firmware using the fxload tool. This can be
+# automated by using udev rules (which can be found in the firmware
+# repository).
+#
+# Ubuntu packages built from mithro's version (with prebuilt firmware and udev
+# rules) can be found at
+# https://launchpad.net/~timvideos/+archive/ubuntu/fpga-support
+#
+# TODO: Refactor the usb_blaster driver to allow loading firmware using any low
+# level driver. Loading firmware is currently only supported on the ublast2
+# driver but ixo-usb-jtag requires the ftdi driver.
+
+adapter driver usb_blaster
+usb_blaster vid_pid 0x16C0 0x06AD
+usb_blaster device_desc "Van Ooijen Technische Informatica"
+# ixo-usb-jtag is only compatible with the ublast1 protocol implemented via the
+# ftdi modes, using ublast2 will cause openocd to hang.
+usb_blaster lowlevel_driver ftdi
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/usbprog.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/usbprog.cfg
new file mode 100644
index 0000000..4f04b14
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/usbprog.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Embedded Projects USBprog
+#
+# http://embedded-projects.net/index.php?page_id=135
+#
+
+adapter driver usbprog
+# USBprog is broken w/short TMS sequences, this is a workaround
+# until the C code can be fixed.
+tms_sequence long
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/vdebug.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/vdebug.cfg
new file mode 100644
index 0000000..63a5955
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/vdebug.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+
+if { [info exists VDEBUGHOST] } {
+	set _VDEBUGHOST $VDEBUGHOST
+} else {
+	set _VDEBUGHOST localhost
+}
+if { [info exists VDEBUGPORT] } {
+	set _VDEBUGPORT $VDEBUGPORT
+} else {
+	set _VDEBUGPORT 8192
+}
+
+adapter driver vdebug
+# vdebug server:port
+vdebug server $_VDEBUGHOST:$_VDEBUGPORT
+
+# example config debug level and log
+#debug_level 3
+#log_output vd_ocd.log
+
+# example config listen on all interfaces, disable tcl/telnet server
+bindto 0.0.0.0
+#gdb port 3333
+#telnet port disabled
+tcl port disabled
+
+# transaction batching: 0 - no batching, 1 - (default) wr, 2 - rw
+vdebug batching 1
+
+# Polling values
+vdebug polling 100 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/vsllink.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/vsllink.cfg
new file mode 100644
index 0000000..f780c89
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/vsllink.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Versaloon Link -- VSLLink
+#
+# http://www.versaloon.com/
+#
+
+adapter driver vsllink
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/xds110.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/xds110.cfg
new file mode 100644
index 0000000..aff0f38
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/interface/xds110.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments XDS110
+#
+# http://processors.wiki.ti.com/index.php/XDS110
+# http://processors.wiki.ti.com/index.php/Emulation_Software_Package#XDS110_Support_Utilities
+#
+
+adapter driver xds110
+
+# Use serial number option to use a specific XDS110
+# when more than one are connected to the host.
+# adapter serial 00000000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/mem_helper.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/mem_helper.tcl
new file mode 100644
index 0000000..0229d54
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/mem_helper.tcl
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Helper for common memory read/modify/write procedures
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+	return [read_memory $reg 32 1]
+}
+
+add_usage_text mrw "address"
+add_help_text mrw "Returns value of word in memory."
+
+# mrh: "memory read halfword", returns value of $reg
+proc mrh {reg} {
+	return [read_memory $reg 16 1]
+}
+
+add_usage_text mrh "address"
+add_help_text mrh "Returns value of halfword in memory."
+
+# mrb: "memory read byte", returns value of $reg
+proc mrb {reg} {
+	return [read_memory $reg 8 1]
+}
+
+add_usage_text mrb "address"
+add_help_text mrb "Returns value of byte in memory."
+
+# mmw: "memory modify word", updates value of $reg
+#       $reg <== ((value & ~$clearbits) | $setbits)
+proc mmw {reg setbits clearbits} {
+	set old [mrw $reg]
+	set new [expr {($old & ~$clearbits) | $setbits}]
+	mww $reg $new
+}
+
+add_usage_text mmw "address setbits clearbits"
+add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/memory.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/memory.tcl
new file mode 100644
index 0000000..8b93b51
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/memory.tcl
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MEMORY
+#
+# All Memory regions have two components.
+#    (1) A count of regions, in the form N_NAME
+#    (2) An array within info about each region.
+#
+# The ARRAY
+#
+#       (  RegionNumber ,  ATTRIBUTE )
+#
+# Where  is one of:
+#
+#     N_FLASH  & FLASH   (internal memory)
+#     N_RAM    & RAM     (internal memory)
+#     N_MMREGS & MMREGS  (for memory mapped registers)
+#     N_XMEM   & XMEM    (off chip memory, ie: flash on cs0, sdram on cs2)
+# or  N_UNKNOWN & UNKNOWN for things that do not exist.
+#
+# We have 1 unknown region.
+set N_UNKNOWN 1
+# All MEMORY regions must have these attributes
+#     CS          - chip select (if internal, use -1)
+set UNKNOWN(0,CHIPSELECT) -1
+#     BASE        - base address in memory
+set UNKNOWN(0,BASE)       0
+#     LEN         - length in bytes
+set UNKNOWN(0,LEN)        $CPU_MAX_ADDRESS
+#     HUMAN       - human name of the region
+set UNKNOWN(0,HUMAN) "unknown"
+#     TYPE        - one of:
+#                       flash, ram, mmr, unknown
+#                    For harvard arch:
+#                       iflash, dflash, iram, dram
+set UNKNOWN(0,TYPE)       "unknown"
+#     RWX         - access ablity
+#                       unix style chmod bits
+#                           0 - no access
+#                           1 - execute
+#                           2 - write
+#                           4 - read
+#                       hence: 7 - readwrite execute
+set RWX_NO_ACCESS     0
+set RWX_X_ONLY        $BIT0
+set RWX_W_ONLY        $BIT1
+set RWX_R_ONLY        $BIT2
+set RWX_RW            [expr {$RWX_R_ONLY + $RWX_W_ONLY}]
+set RWX_R_X           [expr {$RWX_R_ONLY + $RWX_X_ONLY}]
+set RWX_RWX           [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}]
+set UNKNOWN(0,RWX)     $RWX_NO_ACCESS
+
+#     WIDTH       - access width
+#                      8,16,32 [0 means ANY]
+set ACCESS_WIDTH_NONE 0
+set ACCESS_WIDTH_8    $BIT0
+set ACCESS_WIDTH_16   $BIT1
+set ACCESS_WIDTH_32   $BIT2
+set ACCESS_WIDTH_ANY  [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}]
+set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
+
+proc iswithin { ADDRESS BASE LEN } {
+    return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]
+}
+
+proc address_info { ADDRESS } {
+
+    foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
+	if { [info exists $WHERE] } {
+	    set lmt [set N_[set WHERE]]
+	    for { set region 0 } { $region < $lmt } { incr region } {
+		if { [iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN)] } {
+		    return  "$WHERE $region";
+		}
+	    }
+	}
+    }
+
+    # Return the 'unknown'
+    return "UNKNOWN 0"
+}
+
+proc memread32 {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 32 1] } msg ] {
+	return $foo
+    } else {
+	error "memread32: $msg"
+    }
+}
+
+proc memread16 {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 16 1] } msg ] {
+	return $foo
+    } else {
+	error "memread16: $msg"
+    }
+}
+
+proc memread8 {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 8 1] } msg ] {
+	return $foo
+    } else {
+	error "memread8: $msg"
+    }
+}
+
+proc memwrite32 {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 32 $DATA } msg ] {
+	return $DATA
+    } else {
+	error "memwrite32: $msg"
+    }
+}
+
+proc memwrite16 {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 16 $DATA } msg ] {
+	return $DATA
+    } else {
+	error "memwrite16: $msg"
+    }
+}
+
+proc memwrite8 {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 8 $DATA } msg ] {
+	return $DATA
+    } else {
+	error "memwrite8: $msg"
+    }
+}
+
+proc memread32_phys {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 32 1 phys] } msg ] {
+	return $foo
+    } else {
+	error "memread32: $msg"
+    }
+}
+
+proc memread16_phys {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 16 1 phys] } msg ] {
+	return $foo
+    } else {
+	error "memread16: $msg"
+    }
+}
+
+proc memread8_phys {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 8 1 phys] } msg ] {
+	return $foo
+    } else {
+	error "memread8: $msg"
+    }
+}
+
+proc memwrite32_phys {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 32 $DATA phys } msg ] {
+	return $DATA
+    } else {
+	error "memwrite32: $msg"
+    }
+}
+
+proc memwrite16_phys {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 16 $DATA phys } msg ] {
+	return $DATA
+    } else {
+	error "memwrite16: $msg"
+    }
+}
+
+proc memwrite8_phys {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 8 $DATA phys } msg ] {
+	return $DATA
+    } else {
+	error "memwrite8: $msg"
+    }
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/mmr_helpers.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/mmr_helpers.tcl
new file mode 100644
index 0000000..5c37fcf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/mmr_helpers.tcl
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc proc_exists { NAME } {
+    set n [info commands $NAME]
+    set l [string length $n]
+    return [expr {$l != 0}]
+}
+
+# Give: REGISTER name - must be a global variable.
+proc show_mmr32_reg { NAME } {
+
+    global $NAME
+    # we want $($NAME)
+    set a [set [set NAME]]
+
+    if ![catch { set v [memread32 $a] } msg ] {
+	echo [format "%15s: (0x%08x): 0x%08x" $NAME $a $v]
+
+	# Was a helper defined?
+	set fn show_${NAME}_helper
+	if [ proc_exists $fn ] {
+	    # Then call it
+	    $fn $NAME $a $v
+	}
+	return $v;
+    } else {
+	error [format "%s (%s)" $msg $NAME ]
+    }
+}
+
+
+# Give: NAMES - an array of names accessible
+#               in the callers symbol-scope.
+#       VAL - the bits to display.
+
+proc show_mmr32_bits { NAMES VAL } {
+
+    upvar $NAMES MYNAMES
+
+    set w 5
+    foreach {IDX N} $MYNAMES {
+	set l [string length $N]
+	if { $l > $w } { set w $l }
+    }
+
+    for { set x 24 } { $x >= 0 } { incr x -8 } {
+	echo -n "  "
+	for { set y 7 } { $y >= 0 } { incr y -1 } {
+	    set s $MYNAMES([expr {$x + $y}])
+	    echo -n [format "%2d: %-*s | " [expr {$x + $y}] $w $s ]
+	}
+	echo ""
+
+	echo -n "  "
+	for { set y 7 } { $y >= 0 } { incr y -1 } {
+	    echo -n [format "    %d%*s | " [expr {!!($VAL & (1 << ($x + $y)))}] [expr {$w -1}] ""]
+	}
+	echo ""
+    }
+}
+
+
+proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } {
+    set width [expr {(($MSB - $LSB + 1) + 7) / 4}]
+    set nval [show_normalize_bitfield $VAL $MSB $LSB ]
+    set name0 [lindex $FIELDVALUES 0 ]
+    if [ string compare $name0 _NUMBER_ ] {
+	set sval [lindex $FIELDVALUES $nval]
+    } else {
+	set sval ""
+    }
+    echo [format "%-15s: %d (0x%0*x) %s" $FIELDNAME $nval $width $nval $sval ]
+}
+
+# Give: ADDR - address of the register.
+#       BIT - bit's number.
+
+proc get_mmr_bit { ADDR BIT } {
+	set val [memread32 $ADDR]
+	set bit_val [expr {$val & [expr {1 << $BIT}]}]
+	return $bit_val
+}
+
+
+# Give: ADDR - address of the register.
+#       MSB - MSB bit's number.
+#       LSB - LSB bit's number.
+
+proc get_mmr_bitfield { ADDR MSB LSB } {
+	set rval [memread32 $ADDR]
+	return normalize_bitfield $rval $MSB $LSB
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/1986Be1T.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/1986Be1T.cfg
new file mode 100644
index 0000000..a3172cc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/1986Be1T.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# 1986ВЕ1Т
+# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=236&cntnt01returnid=68
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME 1986ве1т
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      # SWD IDCODE
+      set _CPUTAPID 0x2ba01477
+   }
+}
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# use AHB-Lite SRAM for work area
+$_TARGETNAME configure -work-area-phys 0x20100000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# can't handle overlapping memory regions
+if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
+   flash bank ${_CHIPNAME}_info.flash mdr 0x00000000 0x01000 0 0 $_TARGETNAME 1 1 4
+} else {
+   flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 0 0 $_TARGETNAME 0 32 4
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/K1879x61R.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/K1879x61R.cfg
new file mode 100644
index 0000000..8dd330d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/K1879x61R.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# СБИС К1879ХБ1Я
+# http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/
+
+adapter speed 1000
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME к1879хб1я
+}
+
+if { [info exists ENDIAN] } {
+    set _ENDIAN $ENDIAN
+} else {
+    set _ENDIAN little
+}
+
+if { [info exists DSP_TAPID] } {
+    set _DSP_TAPID $DSP_TAPID
+} else {
+    set _DSP_TAPID 0x2b900f0f
+}
+
+jtag newtap $_CHIPNAME dsp -irlen 4 -expected-id $_DSP_TAPID
+
+if { [info exists CPU_TAPID] } {
+    set _CPU_TAPID $CPU_TAPID
+} else {
+    set _CPU_TAPID 0x07b76f0f
+}
+
+jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
+
+set _TARGETNAME $_CHIPNAME.arm
+target create $_TARGETNAME arm11 -chain-position $_CHIPNAME.arm
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/adsp-sc58x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/adsp-sc58x.cfg
new file mode 100644
index 0000000..3dcfc91
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/adsp-sc58x.cfg
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Analog Devices ADSP-SC58x (ARM Cortex-A5 plus one or two SHARC+ DSPs)
+#
+
+# Evaluation boards by Analog Devices (and designs derived from them) use a
+# non-standard 10-pin 0.05" ARM Cortex Debug Connector.  In this bastardized
+# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST.
+#
+# As a result, a standards-compliant debug pod will force /TRST active,
+# putting the processor's debug interface into reset and preventing usage.
+#
+# A connector adapter must be employed on these boards to isolate or remap
+# /TRST so that it is only asserted when intended.
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ADSP-SC58x
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x3BA02477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create ap0.mem mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -event examine-end {
+   global _TARGETNAME
+   sc58x_enabledebug
+}
+
+proc sc58x_enabledebug {} {
+   # Enable debugging functionality by setting bits in the TAPC_DBGCTL register
+   # it is not possible to halt the target unless these bits have been set
+   ap0.mem mww 0x31131000 0xFFFF
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/aduc702x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/aduc702x.cfg
new file mode 100644
index 0000000..c903710
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/aduc702x.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME aduc702x
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   # This config file was defaulting to big endian..
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+## JTAG scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+##
+## Target configuration
+##
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# allocate the entire SRAM as working area
+$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
+
+## flash configuration
+# only target number is needed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
+
+## If you use the watchdog, the following code makes sure that the board
+## doesn't reboot when halted via JTAG.  Yes, on the older generation
+## AdUC702x, timer3 continues running even when the CPU is halted.
+
+proc watchdog_service {} {
+    global watchdog_hdl
+    mww 0xffff036c 0
+#    echo "watchdog!!"
+    set watchdog_hdl [after 500 watchdog_service]
+}
+
+$_TARGETNAME configure -event reset-halt-post {  watchdog_service }
+$_TARGETNAME configure -event resume-start { global watchdog_hdl; after cancel $watchdog_hdl }
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/aducm360.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/aducm360.cfg
new file mode 100644
index 0000000..5cfb483
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/aducm360.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This file was created using as references the stm32f1x.cfg and aduc702x.cfg
+#
+source [find target/swj-dp.tcl]
+
+# Chip name
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME aducm360
+}
+
+# Endianness
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# Eventually, the whole SRAM of ADuCM360 will be used (8kB)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x2000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# SWD/JTAG speed
+adapter speed 1000
+
+##
+## Target configuration
+##
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# allocate the working area
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME
+
+adapter srst delay 100
+
+cortex_m reset_config sysresetreq
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/allwinner_v3s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/allwinner_v3s.cfg
new file mode 100644
index 0000000..6c3435e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/allwinner_v3s.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the config for an Allwinner V3/V3s (sun8iw8).
+#
+# Notes:
+# - Single core ARM Cortex-A7 with a maximum frequency of 1.2 GHz.
+# - Thumb-2 Technology
+# - Support NEON Advanced SIMD(Single Instruction Multiple Data)instruction
+#   for acceleration of media and signal processing functions
+# - Support Large Physical Address Extensions(LPAE)
+# - VFPv4 Floating Point Unit
+# - 32KB L1 Instruction cache and 32KB L1 Data cache
+# - 128KB L2 cache
+# - has some integrated DDR2 RAM.
+#
+# Pins related for debug and bootstrap:
+#   JTAG
+# JTAG_TMS	PF0, SDC0_D1
+# JTAG_TDI	PF1, SDC0_D0
+# JTAG_TDO	PF3, SDC0_CMD
+# JTAG_TCK	PF5, SDC0_D2
+#   UART
+# None of UART ports seems to be enabled by ROM.
+# UART0_TX	PF2, SDC0_CLK		Per default disabled
+# UART0_RX	PF4, SDC0_D3 		Per default disabled
+# UART1_TX	PE21			Per default disabled
+# UART1_RX	PE22	 		Per default disabled
+# UART2_TX	PB0			Per default disabled
+# UART2_RX	PB1	 		Per default disabled
+#
+# JTAG is enabled by default after power-on on listed JTAG_* pins. So far the
+# boot sequence is:
+# Time		Action
+# 0000ms	Power ON
+# 0200ms	JTAG enabled
+# 0220ms	JTAG pins switched to SD mode
+#
+# The time frame of 20ms can be not enough to init and halt the CPU. In this
+# case I would recommend to set: "adapter speed 15000"
+# To get more or less precise timings, the board should provide reset pin,
+# or some bench power supply with remote function. In my case I used
+# EEZ H24005 with this command to power on and halt the target:
+# "exec  echo "*TRG" > /dev/ttyACM0; sleep 220; reset halt"
+# After this it is possible to enable JTAG mode again from boot loader or OS.
+# Following DAPs are available:
+# dap[0]->MEM-AP AHB
+# dap[1]->MEM-AP APB->CA7[0]
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME v3s
+}
+
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+# No NRST or SRST is present on the SoC. Boards may provide
+# some sort of Power cycle reset for complete board or SoC.
+# For this case we provide srst_pulls_trst so the board config
+# only needs to set srst_only.
+reset_config none srst_pulls_trst
+
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# Add Cortex A7 core
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/alphascale_asm9260t.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/alphascale_asm9260t.cfg
new file mode 100644
index 0000000..735555e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/alphascale_asm9260t.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME asm9260t
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x079264F3
+}
+
+# And srst_pulls_trst by chip design.
+reset_config srst_pulls_trst
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/altera_fpgasoc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/altera_fpgasoc.cfg
new file mode 100644
index 0000000..a98b346
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/altera_fpgasoc.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Altera cyclone V SoC family, 5Cxxx
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME fpgasoc
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# Subsidiary TAP: fpga
+if { [info exists FPGA_TAPID] } {
+   set _FPGA_TAPID $FPGA_TAPID
+} else {
+   set _FPGA_TAPID 0x02d020dd
+}
+jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID
+
+
+#
+# Cortex-A9 target
+#
+
+# GDB target: Cortex-A9, using DAP, configuring only one core
+# Base addresses of cores:
+# core 0  -  0x80110000
+# core 1  -  0x80112000
+
+# Slow speed to be sure it will work
+adapter speed 1000
+
+set _TARGETNAME1 $_CHIPNAME.cpu.0
+set _TARGETNAME2 $_CHIPNAME.cpu.1
+
+# A9 core 0
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x80110000
+
+$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
+$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
+
+
+# A9 core 1
+#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
+#        -coreid 1 -dbgbase 0x80112000
+
+#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
+#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
+
+proc cycv_dbginit {target} {
+        # General Cortex-A8/A9 debug initialisation
+        cortex_a dbginit
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/altera_fpgasoc_arria10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/altera_fpgasoc_arria10.cfg
new file mode 100644
index 0000000..fe58379
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/altera_fpgasoc_arria10.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel (Altera) Arria10 FPGA SoC
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME arria10
+}
+
+# ARM CoreSight Debug Access Port (dap HPS)
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID
+
+# Subsidiary TAP: fpga (tap)
+# See Intel Arria 10 Handbook
+# https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
+# Intel Arria 10 GX 160  0x02ee20dd
+# Intel Arria 10 GX 220  0x02e220dd
+# Intel Arria 10 GX 270  0x02ee30dd
+# Intel Arria 10 GX 320  0x02e230dd
+# Intel Arria 10 GX 480  0x02e240dd
+# Intel Arria 10 GX 570  0x02ee50dd
+# Intel Arria 10 GX 660  0x02e250dd
+# Intel Arria 10 GX 900  0x02ee60dd
+# Intel Arria 10 GX 1150 0x02e660dd
+# Intel Arria 10 GT 900  0x02e260dd
+# Intel Arria 10 GT 1150 0x02e060dd
+# Intel Arria 10 SX 160  0x02e620dd
+# Intel Arria 10 SX 220  0x02e020dd
+# Intel Arria 10 SX 270  0x02e630dd
+# Intel Arria 10 SX 320  0x02e030dd
+# Intel Arria 10 SX 480  0x02e040dd
+# Intel Arria 10 SX 570  0x02e650dd
+# Intel Arria 10 SX 660  0x02e050dd
+jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \
+	-expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \
+	-expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \
+	-expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \
+	-expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \
+	-expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \
+	-expected-id 0x02e050dd
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+#
+# Cortex-A9 target
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0
+target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \
+	-defer-examine
+target smp $_TARGETNAME.0 $_TARGETNAME.1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/am335x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/am335x.cfg
new file mode 100644
index 0000000..208ebf5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/am335x.cfg
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/icepick.cfg]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME am335x
+}
+
+# set the taps to be enabled by default. this can be overridden
+# by setting DEFAULT_TAPS in a separate configuration file
+# or directly on the command line.
+if { [info exists DEFAULT_TAPS] } {
+	set _DEFAULT_TAPS "$DEFAULT_TAPS"
+} else {
+	set _DEFAULT_TAPS "$_CHIPNAME.tap"
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+#
+# M3 DAP
+#
+if { [info exists M3_DAP_TAPID] } {
+	set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+	set _M3_DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m3_tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
+dap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap
+
+#
+# ICEpick-D (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID 0x0b94402f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+jtag configure $_CHIPNAME.jrc -event setup {
+	global _DEFAULT_TAPS
+	enable_default_taps $_DEFAULT_TAPS
+}
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+#
+# helper function that enables all taps passed as argument
+#
+proc enable_default_taps { taps } {
+	foreach tap $taps {
+		jtag tapenable $tap
+	}
+}
+
+#
+# Cortex-M3 target
+#
+set _TARGETNAME_2 $_CHIPNAME.m3
+target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap
+
+#
+# Cortex-A8 target
+#
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000
+
+# SRAM: 64K at 0x4030.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
+
+
+# when putting the target into 'reset halt', we need to disable the watchdog as
+# it would otherwise trigger while we're in JTAG
+# FIXME: unify with target/am437x.cfg
+source [find mem_helper.tcl]
+set  WDT1_BASE_ADDR                  0x44e35000
+set  WDT1_W_PEND_WSPR                [expr       {$WDT1_BASE_ADDR     +  0x0034}]
+set  WDT1_WSPR                       [expr       {$WDT1_BASE_ADDR     +  0x0048}]
+proc disable_watchdog { } {
+	global WDT1_WSPR
+	global WDT1_W_PEND_WSPR
+	global _TARGETNAME
+
+	set curstate [$_TARGETNAME curstate]
+
+	if { [string compare $curstate halted] == 0 } {
+		set WDT_DISABLE_SEQ1	0xaaaa
+		set WDT_DISABLE_SEQ2	0x5555
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
+
+		# Empty body to make sure this executes as fast as possible.
+		# We don't want any delays here otherwise romcode might start
+		# executing and end up changing state of certain IPs.
+		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
+		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
+	}
+}
+$_TARGETNAME configure -event reset-end { disable_watchdog }
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/am437x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/am437x.cfg
new file mode 100644
index 0000000..5350927
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/am437x.cfg
@@ -0,0 +1,1003 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/icepick.cfg]
+source [find mem_helper.tcl]
+
+###############################################################################
+##				AM437x Registers			     ##
+###############################################################################
+set  PRCM_BASE_ADDR                  0x44df0000
+set  REVISION_PRM                    [expr       {$PRCM_BASE_ADDR     +  0x0000}]
+set  PRM_IRQSTATUS_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0004}]
+set  PRM_IRQENABLE_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0008}]
+set  PRM_IRQSTATUS_M3                [expr       {$PRCM_BASE_ADDR     +  0x000c}]
+set  PRM_IRQENABLE_M3                [expr       {$PRCM_BASE_ADDR     +  0x0010}]
+set  PM_MPU_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0300}]
+set  PM_MPU_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0304}]
+set  RM_MPU_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0314}]
+set  RM_MPU_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0324}]
+set  PM_GFX_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0400}]
+set  PM_GFX_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0404}]
+set  RM_GFX_RSTCTRL                  [expr       {$PRCM_BASE_ADDR     +  0x0410}]
+set  RM_GFX_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0414}]
+set  RM_GFX_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0424}]
+set  RM_RTC_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0524}]
+set  RM_WKUP_RSTCTRL                 [expr       {$PRCM_BASE_ADDR     +  0x2010}]
+set  RM_WKUP_RSTST                   [expr       {$PRCM_BASE_ADDR     +  0x2014}]
+set  CM_L3_AON_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x2800}]
+set  CM_WKUP_DEBUGSS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2820}]
+set  CM_L3S_TSC_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2900}]
+set  CM_WKUP_ADC_TSC_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2920}]
+set  CM_L4_WKUP_AON_CLKSTCTRL        [expr       {$PRCM_BASE_ADDR     +  0x2a00}]
+set  CM_WKUP_L4WKUP_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2a20}]
+set  CM_WKUP_WKUP_M3_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a28}]
+set  CM_WKUP_SYNCTIMER_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a30}]
+set  CM_WKUP_CLKDIV32K_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a38}]
+set  CM_WKUP_USBPHY0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a40}]
+set  CM_WKUP_USBPHY1_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a48}]
+set  CM_WKUP_CLKSTCTRL               [expr       {$PRCM_BASE_ADDR     +  0x2b00}]
+set  CM_WKUP_TIMER0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b20}]
+set  CM_WKUP_TIMER1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b28}]
+set  CM_WKUP_WDT0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b30}]
+set  CM_WKUP_WDT1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b38}]
+set  CM_WKUP_I2C0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b40}]
+set  CM_WKUP_UART0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b48}]
+set  CM_WKUP_SMARTREFLEX0_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b50}]
+set  CM_WKUP_SMARTREFLEX1_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b58}]
+set  CM_WKUP_CONTROL_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2b60}]
+set  CM_WKUP_GPIO0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b68}]
+set  CM_CLKMODE_DPLL_CORE            [expr       {$PRCM_BASE_ADDR     +  0x2d20}]
+set  CM_IDLEST_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d24}]
+set  CM_CLKSEL_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d2c}]
+set  CM_DIV_M4_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d38}]
+set  CM_DIV_M5_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d3c}]
+set  CM_DIV_M6_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d40}]
+set  CM_SSC_DELTAMSTEP_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d48}]
+set  CM_SSC_MODFREQDIV_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d4c}]
+set  CM_CLKMODE_DPLL_MPU             [expr       {$PRCM_BASE_ADDR     +  0x2d60}]
+set  CM_IDLEST_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d64}]
+set  CM_CLKSEL_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d6c}]
+set  CM_DIV_M2_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d70}]
+set  CM_SSC_DELTAMSTEP_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d88}]
+set  CM_SSC_MODFREQDIV_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d8c}]
+set  CM_CLKMODE_DPLL_DDR             [expr       {$PRCM_BASE_ADDR     +  0x2da0}]
+set  CM_IDLEST_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2da4}]
+set  CM_CLKSEL_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2dac}]
+set  CM_DIV_M2_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db0}]
+set  CM_DIV_M4_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db8}]
+set  CM_SSC_DELTAMSTEP_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dc8}]
+set  CM_SSC_MODFREQDIV_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dcc}]
+set  CM_CLKMODE_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2de0}]
+set  CM_IDLEST_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2de4}]
+set  CM_CLKSEL_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2dec}]
+set  CM_DIV_M2_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2df0}]
+set  CM_CLKSEL2_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2e04}]
+set  CM_SSC_DELTAMSTEP_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e08}]
+set  CM_SSC_MODFREQDIV_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e0c}]
+set  CM_CLKDCOLDO_DPLL_PER           [expr       {$PRCM_BASE_ADDR     +  0x2e14}]
+set  CM_CLKMODE_DPLL_DISP            [expr       {$PRCM_BASE_ADDR     +  0x2e20}]
+set  CM_IDLEST_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e24}]
+set  CM_CLKSEL_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e2c}]
+set  CM_DIV_M2_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e30}]
+set  CM_SSC_DELTAMSTEP_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e48}]
+set  CM_SSC_MODFREQDIV_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e4c}]
+set  CM_CLKMODE_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e60}]
+set  CM_IDLEST_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e64}]
+set  CM_CLKSEL_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e6c}]
+set  CM_DIV_M2_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e70}]
+set  CM_CLKSEL2_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e84}]
+set  CM_SSC_DELTAMSTEP_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e88}]
+set  CM_SSC_MODFREQDIV_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e8c}]
+set  CM_SHADOW_FREQ_CONFIG1          [expr       {$PRCM_BASE_ADDR     +  0x2fa0}]
+set  CM_SHADOW_FREQ_CONFIG2          [expr       {$PRCM_BASE_ADDR     +  0x2fa4}]
+set  CM_CLKOUT1_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4100}]
+set  CM_DLL_CTRL                     [expr       {$PRCM_BASE_ADDR     +  0x4104}]
+set  CM_CLKOUT2_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4108}]
+set  CLKSEL_TIMER1MS_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4200}]
+set  CLKSEL_TIMER2_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4204}]
+set  CLKSEL_TIMER3_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4208}]
+set  CLKSEL_TIMER4_CLK               [expr       {$PRCM_BASE_ADDR     +  0x420c}]
+set  CLKSEL_TIMER5_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4210}]
+set  CLKSEL_TIMER6_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4214}]
+set  CLKSEL_TIMER7_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4218}]
+set  CLKSEL_TIMER8_CLK               [expr       {$PRCM_BASE_ADDR     +  0x421c}]
+set  CLKSEL_TIMER9_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4220}]
+set  CLKSEL_TIMER10_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4224}]
+set  CLKSEL_TIMER11_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4228}]
+set  CLKSEL_WDT1_CLK                 [expr       {$PRCM_BASE_ADDR     +  0x422c}]
+set  CLKSEL_SYNCTIMER_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4230}]
+set  CLKSEL_MAC_CLK                  [expr       {$PRCM_BASE_ADDR     +  0x4234}]
+set  CLKSEL_CPTS_RFT_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4238}]
+set  CLKSEL_GFX_FCLK                 [expr       {$PRCM_BASE_ADDR     +  0x423c}]
+set  CLKSEL_GPIO0_DBCLK              [expr       {$PRCM_BASE_ADDR     +  0x4240}]
+set  CLKSEL_LCDC_PIXEL_CLK           [expr       {$PRCM_BASE_ADDR     +  0x4244}]
+set  CLKSEL_ICSS_OCP_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4248}]
+set  CLKSEL_DLL_AGING_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4250}]
+set  CLKSEL_USBPHY32KHZ_GCLK         [expr       {$PRCM_BASE_ADDR     +  0x4260}]
+set  CM_MPU_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8300}]
+set  CM_MPU_MPU_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8320}]
+set  CM_GFX_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8400}]
+set  CM_GFX_GFX_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8420}]
+set  CM_RTC_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8500}]
+set  CM_RTC_RTC_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8520}]
+set  CM_PER_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8800}]
+set  CM_PER_L3_CLKCTRL               [expr       {$PRCM_BASE_ADDR     +  0x8820}]
+set  CM_PER_AES0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8828}]
+set  CM_PER_DES_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8830}]
+set  CM_PER_CRYPTODMA_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8838}]
+set  CM_PER_L3_INSTR_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8840}]
+set  CM_PER_MSTR_EXPS_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8848}]
+set  CM_PER_OCMCRAM_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8850}]
+set  CM_PER_SHA0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8858}]
+set  CM_PER_SLV_EXPS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8860}]
+set  CM_PER_VPFE0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8868}]
+set  CM_PER_VPFE1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8870}]
+set  CM_PER_TPCC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8878}]
+set  CM_PER_TPTC0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8880}]
+set  CM_PER_TPTC1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8888}]
+set  CM_PER_TPTC2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8890}]
+set  CM_PER_DLL_AGING_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8898}]
+set  CM_PER_L4HS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a0}]
+set  CM_PER_L4FW_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a8}]
+set  CM_PER_L3S_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8a00}]
+set  CM_PER_GPMC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a20}]
+set  CM_PER_IEEE5000_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8a28}]
+set  CM_PER_MCASP0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a38}]
+set  CM_PER_MCASP1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a40}]
+set  CM_PER_MMC2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a48}]
+set  CM_PER_QSPI_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a58}]
+set  CM_PER_USB_OTG_SS0_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a60}]
+set  CM_PER_USB_OTG_SS1_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a68}]
+set  CM_PER_ICSS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8b00}]
+set  CM_PER_ICSS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8b20}]
+set  CM_PER_L4LS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8c00}]
+set  CM_PER_L4LS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8c20}]
+set  CM_PER_DCAN0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c28}]
+set  CM_PER_DCAN1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c30}]
+set  CM_PER_EPWMSS0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c38}]
+set  CM_PER_EPWMSS1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c40}]
+set  CM_PER_EPWMSS2_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c48}]
+set  CM_PER_EPWMSS3_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c50}]
+set  CM_PER_EPWMSS4_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c58}]
+set  CM_PER_EPWMSS5_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c60}]
+set  CM_PER_ELM_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8c68}]
+set  CM_PER_GPIO1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c78}]
+set  CM_PER_GPIO2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c80}]
+set  CM_PER_GPIO3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c88}]
+set  CM_PER_GPIO4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c90}]
+set  CM_PER_GPIO5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c98}]
+set  CM_PER_HDQ1W_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8ca0}]
+set  CM_PER_I2C1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8ca8}]
+set  CM_PER_I2C2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cb0}]
+set  CM_PER_MAILBOX0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8cb8}]
+set  CM_PER_MMC0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc0}]
+set  CM_PER_MMC1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc8}]
+set  CM_PER_PKA_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8cd0}]
+set  CM_PER_RNG_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8ce0}]
+set  CM_PER_SPARE0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8ce8}]
+set  CM_PER_SPARE1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8cf0}]
+set  CM_PER_SPI0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d00}]
+set  CM_PER_SPI1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d08}]
+set  CM_PER_SPI2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d10}]
+set  CM_PER_SPI3_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d18}]
+set  CM_PER_SPI4_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d20}]
+set  CM_PER_SPINLOCK_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8d28}]
+set  CM_PER_TIMER2_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d30}]
+set  CM_PER_TIMER3_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d38}]
+set  CM_PER_TIMER4_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d40}]
+set  CM_PER_TIMER5_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d48}]
+set  CM_PER_TIMER6_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d50}]
+set  CM_PER_TIMER7_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d58}]
+set  CM_PER_TIMER8_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d60}]
+set  CM_PER_TIMER9_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d68}]
+set  CM_PER_TIMER10_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d70}]
+set  CM_PER_TIMER11_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d78}]
+set  CM_PER_UART1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d80}]
+set  CM_PER_UART2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d88}]
+set  CM_PER_UART3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d90}]
+set  CM_PER_UART4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d98}]
+set  CM_PER_UART5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8da0}]
+set  CM_PER_USBPHYOCP2SCP0_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8db8}]
+set  CM_PER_USBPHYOCP2SCP1_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8dc0}]
+set  CM_PER_EMIF_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8f00}]
+set  CM_PER_EMIF_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8f20}]
+set  CM_PER_DLL_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8f28}]
+set  CM_PER_EMIF_FW_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8f30}]
+set  CM_PER_OTFA_EMIF_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8f38}]
+set  CM_PER_DSS_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9200}]
+set  CM_PER_DSS_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x9220}]
+set  CM_PER_CPSW_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x9300}]
+set  CM_PER_CPGMAC0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x9320}]
+set  CM_PER_OCPWP_L3_CLKSTCTRL       [expr       {$PRCM_BASE_ADDR     +  0x9400}]
+set  CM_PER_OCPWP_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9420}]
+
+set  CONTROL_BASE_ADDR               0x44e10000
+set  CONTROL_STATUS                  [expr       {$CONTROL_BASE_ADDR  +  0x0040}]
+set  DEVICE_ID                       [expr       {$CONTROL_BASE_ADDR  +  0x0600}]
+set  DEV_FEATURE                     [expr       {$CONTROL_BASE_ADDR  +  0x0604}]
+set  DEV_ATTRIBUTE                   [expr       {$CONTROL_BASE_ADDR  +  0x0610}]
+set  MAC_ID0_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0630}]
+set  MAC_ID0_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x0634}]
+set  MAC_ID1_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0638}]
+set  MAC_ID1_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x063c}]
+set  USB_VID_PID                     [expr       {$CONTROL_BASE_ADDR  +  0x07f4}]
+set  CONTROL_CONF_ECAP0_IN_PWM0_OUT  [expr       {$CONTROL_BASE_ADDR  +  0x0964}]
+set  CONTROL_CONF_SPI4_CS0           [expr       {$CONTROL_BASE_ADDR  +  0x0a5c}]
+set  CONTROL_CONF_SPI2_SCLK          [expr       {$CONTROL_BASE_ADDR  +  0x0a60}]
+set  CONTROL_CONF_SPI2_D0            [expr       {$CONTROL_BASE_ADDR  +  0x0a64}]
+set  CONTROL_CONF_XDMA_EVENT_INTR0   [expr       {$CONTROL_BASE_ADDR  +  0x0a70}]
+set  CONTROL_CONF_XDMA_EVENT_INTR1   [expr       {$CONTROL_BASE_ADDR  +  0x0a74}]
+set  CONTROL_CONF_GPMC_A0            [expr       {$CONTROL_BASE_ADDR  +  0x0840}]
+set  DDR_IO_CTRL                     [expr       {$CONTROL_BASE_ADDR  +  0x0e04}]
+set  VTP_CTRL_REG                    [expr       {$CONTROL_BASE_ADDR  +  0x0e0c}]
+set  VREF_CTRL                       [expr       {$CONTROL_BASE_ADDR  +  0x0e14}]
+set  DDR_CKE_CTRL                    [expr       {$CONTROL_BASE_ADDR  +  0x131c}]
+set  DDR_ADDRCTRL_IOCTRL             [expr       {$CONTROL_BASE_ADDR  +  0x1404}]
+set  DDR_ADDRCTRL_WD0_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x1408}]
+set  DDR_ADDRCTRL_WD1_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x140c}]
+set  DDR_DATA0_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1440}]
+set  DDR_DATA1_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1444}]
+set  DDR_DATA2_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1448}]
+set  DDR_DATA3_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x144c}]
+set  EMIF_SDRAM_CONFIG_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1460}]
+set  EMIF_SDRAM_STATUS_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1464}]
+
+set  GPIO0_BASE_ADDR                 0x44e07000
+set  GPIO0_SYSCONFIG                 [expr       {$GPIO0_BASE_ADDR    +  0x0010}]
+set  GPIO0_SYSSTATUS                 [expr       {$GPIO0_BASE_ADDR    +  0x0114}]
+set  GPIO0_CTRL                      [expr       {$GPIO0_BASE_ADDR    +  0x0130}]
+set  GPIO0_OE                        [expr       {$GPIO0_BASE_ADDR    +  0x0134}]
+set  GPIO0_CLEARDATAOUT              [expr       {$GPIO0_BASE_ADDR    +  0x0190}]
+set  GPIO0_SETDATAOUT                [expr       {$GPIO0_BASE_ADDR    +  0x0194}]
+
+set  GPIO5_BASE_ADDR                 0x48322000
+set  GPIO5_SYSCONFIG                 [expr       {$GPIO5_BASE_ADDR    +  0x0010}]
+set  GPIO5_SYSSTATUS                 [expr       {$GPIO5_BASE_ADDR    +  0x0114}]
+set  GPIO5_CTRL                      [expr       {$GPIO5_BASE_ADDR    +  0x0130}]
+set  GPIO5_OE                        [expr       {$GPIO5_BASE_ADDR    +  0x0134}]
+set  GPIO5_CLEARDATAOUT              [expr       {$GPIO5_BASE_ADDR    +  0x0190}]
+set  GPIO5_SETDATAOUT                [expr       {$GPIO5_BASE_ADDR    +  0x0194}]
+
+set  GPIO1_BASE_ADDR                 0x4804c000
+set  GPIO1_SYSCONFIG                 [expr       {$GPIO1_BASE_ADDR    +  0x0010}]
+set  GPIO1_SYSSTATUS                 [expr       {$GPIO1_BASE_ADDR    +  0x0114}]
+set  GPIO1_CTRL                      [expr       {$GPIO1_BASE_ADDR    +  0x0130}]
+set  GPIO1_OE                        [expr       {$GPIO1_BASE_ADDR    +  0x0134}]
+set  GPIO1_CLEARDATAOUT              [expr       {$GPIO1_BASE_ADDR    +  0x0190}]
+set  GPIO1_SETDATAOUT                [expr       {$GPIO1_BASE_ADDR    +  0x0194}]
+
+set  EMIF_BASE_ADDR                  0x4c000000
+set  EMIF_STATUS                     [expr       {$EMIF_BASE_ADDR     +  0x0004}]
+set  EMIF_SDRAM_CONFIG               [expr       {$EMIF_BASE_ADDR     +  0x0008}]
+set  EMIF_SDRAM_CONFIG_2             [expr       {$EMIF_BASE_ADDR     +  0x000c}]
+set  EMIF_SDRAM_REF_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0010}]
+set  EMIF_SDRAM_REF_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0014}]
+set  EMIF_SDRAM_TIM_1                [expr       {$EMIF_BASE_ADDR     +  0x0018}]
+set  EMIF_SDRAM_TIM_1_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x001c}]
+set  EMIF_SDRAM_TIM_2                [expr       {$EMIF_BASE_ADDR     +  0x0020}]
+set  EMIF_SDRAM_TIM_2_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x0024}]
+set  EMIF_SDRAM_TIM_3                [expr       {$EMIF_BASE_ADDR     +  0x0028}]
+set  EMIF_SDRAM_TIM_3_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x002c}]
+set  EMIF_LPDDR2_NVM_TIM             [expr       {$EMIF_BASE_ADDR     +  0x0030}]
+set  EMIF_LPDDR2_NVM_TIM_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0034}]
+set  EMIF_PWR_MGMT_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x0038}]
+set  EMIF_PWR_MGMT_CTRL_SHDW         [expr       {$EMIF_BASE_ADDR     +  0x003c}]
+set  EMIF_LPDDR2_MODE_REG_DATA       [expr       {$EMIF_BASE_ADDR     +  0x0040}]
+set  EMIF_LPDDR2_MODE_REG_CFG        [expr       {$EMIF_BASE_ADDR     +  0x0050}]
+set  EMIF_OCP_CONFIG                 [expr       {$EMIF_BASE_ADDR     +  0x0054}]
+set  EMIF_OCP_CFG_VAL_1              [expr       {$EMIF_BASE_ADDR     +  0x0058}]
+set  EMIF_OCP_CFG_VAL_2              [expr       {$EMIF_BASE_ADDR     +  0x005c}]
+set  EMIF_IODFT_TLGC                 [expr       {$EMIF_BASE_ADDR     +  0x0060}]
+set  EMIF_IODFT_CTRL_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0064}]
+set  EMIF_IODFT_ADDR_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0068}]
+set  EMIF_IODFT_DATA_MISR_RSLT_1     [expr       {$EMIF_BASE_ADDR     +  0x006c}]
+set  EMIF_IODFT_DATA_MISR_RSLT_2     [expr       {$EMIF_BASE_ADDR     +  0x0070}]
+set  EMIF_IODFT_DATA_MISR_RSLT_3     [expr       {$EMIF_BASE_ADDR     +  0x0074}]
+set  EMIF_PERF_CNT_1                 [expr       {$EMIF_BASE_ADDR     +  0x0080}]
+set  EMIF_PERF_CNT_2                 [expr       {$EMIF_BASE_ADDR     +  0x0084}]
+set  EMIF_PERF_CNT_CFG               [expr       {$EMIF_BASE_ADDR     +  0x0088}]
+set  EMIF_PERF_CNT_SEL               [expr       {$EMIF_BASE_ADDR     +  0x008c}]
+set  EMIF_PERF_CNT_TIM               [expr       {$EMIF_BASE_ADDR     +  0x0090}]
+set  EMIF_MISC_REG                   [expr       {$EMIF_BASE_ADDR     +  0x0094}]
+set  EMIF_DLL_CALIB_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0098}]
+set  EMIF_DLL_CALIB_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x009c}]
+set  EMIF_IRQ_EOI                    [expr       {$EMIF_BASE_ADDR     +  0x00a0}]
+set  EMIF_IRQSTATUS_RAW_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00a4}]
+set  EMIF_IRQSTATUS_SYS              [expr       {$EMIF_BASE_ADDR     +  0x00ac}]
+set  EMIF_IRQENABLE_SET_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00b4}]
+set  EMIF_IRQENABLE_CLR_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00bc}]
+set  EMIF_ZQ_CONFIG                  [expr       {$EMIF_BASE_ADDR     +  0x00c8}]
+set  EMIF_TEMP_ALERT_CONFIG          [expr       {$EMIF_BASE_ADDR     +  0x00cc}]
+set  EMIF_OCP_ERR_LOG                [expr       {$EMIF_BASE_ADDR     +  0x00d0}]
+set  EMIF_RDWR_LVL_RMP_WIN           [expr       {$EMIF_BASE_ADDR     +  0x00d4}]
+set  EMIF_RDWR_LVL_RMP_CTRL          [expr       {$EMIF_BASE_ADDR     +  0x00d8}]
+set  EMIF_RDWR_LVL_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x00dc}]
+set  EMIF_DDR_PHY_CTRL_1             [expr       {$EMIF_BASE_ADDR     +  0x00e4}]
+set  EMIF_DDR_PHY_CTRL_1_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x00e8}]
+set  EMIF_DDR_PHY_CTRL_2             [expr       {$EMIF_BASE_ADDR     +  0x00ec}]
+set  EMIF_PRI_COS_MAP                [expr       {$EMIF_BASE_ADDR     +  0x0100}]
+set  EMIF_CONNID_COS_1_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0104}]
+set  EMIF_CONNID_COS_2_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0108}]
+set  ECC_CTRL                        [expr       {$EMIF_BASE_ADDR     +  0x0110}]
+set  ECC_ADDR_RNG_1                  [expr       {$EMIF_BASE_ADDR     +  0x0114}]
+set  ECC_ADDR_RNG_2                  [expr       {$EMIF_BASE_ADDR     +  0x0118}]
+set  EMIF_RD_WR_EXEC_THRSH           [expr       {$EMIF_BASE_ADDR     +  0x0120}]
+set  COS_CONFIG                      [expr       {$EMIF_BASE_ADDR     +  0x0124}]
+
+set  PHY_STATUS_1                    [expr       {$EMIF_BASE_ADDR     +  0x0144}]
+set  PHY_STATUS_2                    [expr       {$EMIF_BASE_ADDR     +  0x0148}]
+set  PHY_STATUS_3                    [expr       {$EMIF_BASE_ADDR     +  0x014c}]
+set  PHY_STATUS_4                    [expr       {$EMIF_BASE_ADDR     +  0x0150}]
+set  PHY_STATUS_5                    [expr       {$EMIF_BASE_ADDR     +  0x0154}]
+set  PHY_STATUS_6                    [expr       {$EMIF_BASE_ADDR     +  0x0158}]
+set  PHY_STATUS_7                    [expr       {$EMIF_BASE_ADDR     +  0x015c}]
+set  PHY_STATUS_8                    [expr       {$EMIF_BASE_ADDR     +  0x0160}]
+set  PHY_STATUS_9                    [expr       {$EMIF_BASE_ADDR     +  0x0164}]
+set  PHY_STATUS_10                   [expr       {$EMIF_BASE_ADDR     +  0x0168}]
+set  PHY_STATUS_11                   [expr       {$EMIF_BASE_ADDR     +  0x016c}]
+set  PHY_STATUS_12                   [expr       {$EMIF_BASE_ADDR     +  0x0170}]
+set  PHY_STATUS_13                   [expr       {$EMIF_BASE_ADDR     +  0x0174}]
+set  PHY_STATUS_14                   [expr       {$EMIF_BASE_ADDR     +  0x0178}]
+set  PHY_STATUS_15                   [expr       {$EMIF_BASE_ADDR     +  0x017c}]
+set  PHY_STATUS_16                   [expr       {$EMIF_BASE_ADDR     +  0x0180}]
+set  PHY_STATUS_17                   [expr       {$EMIF_BASE_ADDR     +  0x0184}]
+set  PHY_STATUS_18                   [expr       {$EMIF_BASE_ADDR     +  0x0188}]
+set  PHY_STATUS_19                   [expr       {$EMIF_BASE_ADDR     +  0x018c}]
+set  PHY_STATUS_20                   [expr       {$EMIF_BASE_ADDR     +  0x0190}]
+set  PHY_STATUS_21                   [expr       {$EMIF_BASE_ADDR     +  0x0194}]
+set  PHY_STATUS_22                   [expr       {$EMIF_BASE_ADDR     +  0x0198}]
+set  PHY_STATUS_23                   [expr       {$EMIF_BASE_ADDR     +  0x019c}]
+set  PHY_STATUS_24                   [expr       {$EMIF_BASE_ADDR     +  0x01a0}]
+set  PHY_STATUS_25                   [expr       {$EMIF_BASE_ADDR     +  0x01a4}]
+set  PHY_STATUS_26                   [expr       {$EMIF_BASE_ADDR     +  0x01a8}]
+set  PHY_STATUS_27                   [expr       {$EMIF_BASE_ADDR     +  0x01ac}]
+set  PHY_STATUS_28                   [expr       {$EMIF_BASE_ADDR     +  0x01b0}]
+
+set  EXT_PHY_CTRL_1                  [expr       {$EMIF_BASE_ADDR     +  0x0200}]
+set  EXT_PHY_CTRL_1_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0204}]
+set  EXT_PHY_CTRL_2                  [expr       {$EMIF_BASE_ADDR     +  0x0208}]
+set  EXT_PHY_CTRL_2_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x020c}]
+set  EXT_PHY_CTRL_3                  [expr       {$EMIF_BASE_ADDR     +  0x0210}]
+set  EXT_PHY_CTRL_3_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0214}]
+set  EXT_PHY_CTRL_4                  [expr       {$EMIF_BASE_ADDR     +  0x0218}]
+set  EXT_PHY_CTRL_4_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x021c}]
+set  EXT_PHY_CTRL_5                  [expr       {$EMIF_BASE_ADDR     +  0x0220}]
+set  EXT_PHY_CTRL_5_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0224}]
+set  EXT_PHY_CTRL_6                  [expr       {$EMIF_BASE_ADDR     +  0x0228}]
+set  EXT_PHY_CTRL_6_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x022c}]
+set  EXT_PHY_CTRL_7                  [expr       {$EMIF_BASE_ADDR     +  0x0230}]
+set  EXT_PHY_CTRL_7_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0234}]
+set  EXT_PHY_CTRL_8                  [expr       {$EMIF_BASE_ADDR     +  0x0238}]
+set  EXT_PHY_CTRL_8_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x023c}]
+set  EXT_PHY_CTRL_9                  [expr       {$EMIF_BASE_ADDR     +  0x0240}]
+set  EXT_PHY_CTRL_9_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0244}]
+set  EXT_PHY_CTRL_10                 [expr       {$EMIF_BASE_ADDR     +  0x0248}]
+set  EXT_PHY_CTRL_10_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x024c}]
+set  EXT_PHY_CTRL_11                 [expr       {$EMIF_BASE_ADDR     +  0x0250}]
+set  EXT_PHY_CTRL_11_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0254}]
+set  EXT_PHY_CTRL_12                 [expr       {$EMIF_BASE_ADDR     +  0x0258}]
+set  EXT_PHY_CTRL_12_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x025c}]
+set  EXT_PHY_CTRL_13                 [expr       {$EMIF_BASE_ADDR     +  0x0260}]
+set  EXT_PHY_CTRL_13_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0264}]
+set  EXT_PHY_CTRL_14                 [expr       {$EMIF_BASE_ADDR     +  0x0268}]
+set  EXT_PHY_CTRL_14_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x026c}]
+set  EXT_PHY_CTRL_15                 [expr       {$EMIF_BASE_ADDR     +  0x0270}]
+set  EXT_PHY_CTRL_15_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0274}]
+set  EXT_PHY_CTRL_16                 [expr       {$EMIF_BASE_ADDR     +  0x0278}]
+set  EXT_PHY_CTRL_16_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x027c}]
+set  EXT_PHY_CTRL_17                 [expr       {$EMIF_BASE_ADDR     +  0x0280}]
+set  EXT_PHY_CTRL_17_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0284}]
+set  EXT_PHY_CTRL_18                 [expr       {$EMIF_BASE_ADDR     +  0x0288}]
+set  EXT_PHY_CTRL_18_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x028c}]
+set  EXT_PHY_CTRL_19                 [expr       {$EMIF_BASE_ADDR     +  0x0290}]
+set  EXT_PHY_CTRL_19_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0294}]
+set  EXT_PHY_CTRL_20                 [expr       {$EMIF_BASE_ADDR     +  0x0298}]
+set  EXT_PHY_CTRL_20_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x029c}]
+set  EXT_PHY_CTRL_21                 [expr       {$EMIF_BASE_ADDR     +  0x02a0}]
+set  EXT_PHY_CTRL_21_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02a4}]
+set  EXT_PHY_CTRL_22                 [expr       {$EMIF_BASE_ADDR     +  0x02a8}]
+set  EXT_PHY_CTRL_22_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ac}]
+set  EXT_PHY_CTRL_23                 [expr       {$EMIF_BASE_ADDR     +  0x02b0}]
+set  EXT_PHY_CTRL_23_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02b4}]
+set  EXT_PHY_CTRL_24                 [expr       {$EMIF_BASE_ADDR     +  0x02b8}]
+set  EXT_PHY_CTRL_24_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02bc}]
+set  EXT_PHY_CTRL_25                 [expr       {$EMIF_BASE_ADDR     +  0x02c0}]
+set  EXT_PHY_CTRL_25_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02c4}]
+set  EXT_PHY_CTRL_26                 [expr       {$EMIF_BASE_ADDR     +  0x02c8}]
+set  EXT_PHY_CTRL_26_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02cc}]
+set  EXT_PHY_CTRL_27                 [expr       {$EMIF_BASE_ADDR     +  0x02d0}]
+set  EXT_PHY_CTRL_27_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02d4}]
+set  EXT_PHY_CTRL_28                 [expr       {$EMIF_BASE_ADDR     +  0x02d8}]
+set  EXT_PHY_CTRL_28_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02dc}]
+set  EXT_PHY_CTRL_29                 [expr       {$EMIF_BASE_ADDR     +  0x02e0}]
+set  EXT_PHY_CTRL_29_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02e4}]
+set  EXT_PHY_CTRL_30                 [expr       {$EMIF_BASE_ADDR     +  0x02e8}]
+set  EXT_PHY_CTRL_30_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ec}]
+set  EXT_PHY_CTRL_31                 [expr       {$EMIF_BASE_ADDR     +  0x02f0}]
+set  EXT_PHY_CTRL_31_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02f4}]
+set  EXT_PHY_CTRL_32                 [expr       {$EMIF_BASE_ADDR     +  0x02f8}]
+set  EXT_PHY_CTRL_32_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02fc}]
+set  EXT_PHY_CTRL_33                 [expr       {$EMIF_BASE_ADDR     +  0x0300}]
+set  EXT_PHY_CTRL_33_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0304}]
+set  EXT_PHY_CTRL_34                 [expr       {$EMIF_BASE_ADDR     +  0x0308}]
+set  EXT_PHY_CTRL_34_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x030c}]
+set  EXT_PHY_CTRL_35                 [expr       {$EMIF_BASE_ADDR     +  0x0310}]
+set  EXT_PHY_CTRL_35_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0314}]
+set  EXT_PHY_CTRL_36                 [expr       {$EMIF_BASE_ADDR     +  0x0318}]
+set  EXT_PHY_CTRL_36_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x031c}]
+
+set  WDT1_BASE_ADDR                  0x44e35000
+set  WDT1_W_PEND_WSPR                [expr       {$WDT1_BASE_ADDR     +  0x0034}]
+set  WDT1_WSPR                       [expr       {$WDT1_BASE_ADDR     +  0x0048}]
+
+set  RTC_BASE_ADDR                   0x44e3e000
+set  RTC_KICK0R                      [expr       {$RTC_BASE_ADDR      +  0x6c}]
+set  RTC_KICK1R                      [expr       {$RTC_BASE_ADDR      +  0x70}]
+
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME am437x
+}
+
+set JRC_MODULE		icepick_d
+set DEBUGSS_MODULE	debugss
+set M3_MODULE		m3_wakeupss
+
+set JRC_NAME		$_CHIPNAME.$JRC_MODULE
+set DEBUGSS_NAME	$_CHIPNAME.$DEBUGSS_MODULE
+set M3_NAME		$_CHIPNAME.$M3_MODULE
+set _TARGETNAME		$_CHIPNAME.mpuss
+
+#
+# M3 WakeupSS DAP
+#
+if { [info exists M3_DAP_TAPID] } {
+	set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+	set _M3_DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
+jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0"
+dap create $M3_NAME.dap -chain-position $M3_NAME
+
+#
+# DebugSS DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x46b6902f
+}
+jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0"
+dap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME
+
+#
+# ICEpick-D (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b98c02f
+}
+jtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME"
+ # some TCK tycles are required to activate the DEBUG power domain
+jtag configure $JRC_NAME -event post-reset "runtest 100"
+
+#
+# Cortex-A9 target
+#
+target create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000
+
+
+# SRAM: 256K at 0x4030.0000
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000
+
+# Disables watchdog timer after reset otherwise board won't stay in
+# halted state.
+proc disable_watchdog { } {
+	global WDT1_WSPR
+	global WDT1_W_PEND_WSPR
+	global _TARGETNAME
+
+	set curstate [$_TARGETNAME curstate]
+
+	if { [string compare $curstate halted] == 0 } {
+		set WDT_DISABLE_SEQ1	0xaaaa
+		set WDT_DISABLE_SEQ2	0x5555
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
+
+		# Empty body to make sure this executes as fast as possible.
+		# We don't want any delays here otherwise romcode might start
+		# executing and end up changing state of certain IPs.
+		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
+		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
+	}
+}
+
+proc ceil { x y } {
+	return [ expr {($x + $y - 1) / $y} ]
+}
+
+proc device_type { } {
+	global CONTROL_STATUS
+
+	set tmp [ mrw $CONTROL_STATUS ]
+	set tmp [ expr {$tmp & 0x700} ]
+	set tmp [ expr {$tmp >> 8} ]
+
+	return $tmp
+}
+
+proc get_input_clock_frequency { } {
+	global CONTROL_STATUS
+
+	if { [ device_type ] != 3 } {
+		error "Unknown device type\n"
+		return -1
+	}
+
+	set freq [ mrw $CONTROL_STATUS ]
+	set freq [ expr {$freq & 0x00c00000} ]
+	set freq [ expr {$freq >> 22} ]
+
+	switch $freq {
+		0 {
+			set CLKIN 19200000
+		}
+
+		1 {
+			set CLKIN 24000000
+		}
+
+		2 {
+			set CLKIN 25000000
+		}
+
+		3 {
+			set CLKIN 26000000
+		}
+	}
+
+	return $CLKIN
+}
+
+proc mpu_pll_config { CLKIN N M M2 } {
+	global CM_CLKMODE_DPLL_MPU
+	global CM_CLKSEL_DPLL_MPU
+	global CM_DIV_M2_DPLL_MPU
+	global CM_IDLEST_DPLL_MPU
+
+	set clksel [ mrw $CM_CLKSEL_DPLL_MPU ]
+	set div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ]
+
+	mww $CM_CLKMODE_DPLL_MPU 0x4
+	while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { }
+
+	set clksel [ expr {$clksel & (~0x7ffff)} ]
+	set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
+	mww $CM_CLKSEL_DPLL_MPU $clksel
+
+	set div_m2 [ expr {$div_m2 & (~0x1f)} ]
+	set div_m2 [ expr {$div_m2 | $M2} ]
+	mww $CM_DIV_M2_DPLL_MPU $div_m2
+
+	mww $CM_CLKMODE_DPLL_MPU 0x7
+	while { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { }
+
+	echo "MPU DPLL locked"
+}
+
+proc core_pll_config { CLKIN N M M4 M5 M6 } {
+	global CM_CLKMODE_DPLL_CORE
+	global CM_CLKSEL_DPLL_CORE
+	global CM_DIV_M4_DPLL_CORE
+	global CM_DIV_M5_DPLL_CORE
+	global CM_DIV_M6_DPLL_CORE
+	global CM_IDLEST_DPLL_CORE
+
+	set clksel [ mrw $CM_CLKSEL_DPLL_CORE ]
+
+	mww $CM_CLKMODE_DPLL_CORE 0x4
+	while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { }
+
+	set clksel [ expr {$clksel & (~0x7ffff)} ]
+	set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
+	mww $CM_CLKSEL_DPLL_CORE $clksel
+	mww $CM_DIV_M4_DPLL_CORE $M4
+	mww $CM_DIV_M5_DPLL_CORE $M5
+	mww $CM_DIV_M6_DPLL_CORE $M6
+
+	mww $CM_CLKMODE_DPLL_CORE 0x7
+	while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { }
+
+	echo "CORE DPLL locked"
+}
+
+proc per_pll_config { CLKIN N M M2 } {
+	global CM_CLKMODE_DPLL_PER
+	global CM_CLKSEL_DPLL_PER
+	global CM_DIV_M2_DPLL_PER
+	global CM_IDLEST_DPLL_PER
+
+	set x [ expr {$M * $CLKIN / 1000000} ]
+	set y [ expr {($N + 1) * 250} ]
+	set sd [ ceil $x $y ]
+
+	set clksel [ mrw $CM_CLKSEL_DPLL_PER ]
+	set div_m2 [ mrw $CM_DIV_M2_DPLL_PER ]
+
+	mww $CM_CLKMODE_DPLL_PER 0x4
+	while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { }
+
+	set clksel [ expr {$clksel & (~0xff0fffff)} ]
+	set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
+	set clksel [ expr {$clksel | ($sd << 24)} ]
+	mww $CM_CLKSEL_DPLL_PER $clksel
+
+	set div_m2 [ expr {0xffffff80 | $M2} ]
+
+	mww $CM_CLKMODE_DPLL_PER 0x7
+	while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { }
+
+	echo "PER DPLL locked"
+}
+
+proc ddr_pll_config { CLKIN N M M2 M4 } {
+	global CM_CLKMODE_DPLL_DDR
+	global CM_CLKSEL_DPLL_DDR
+	global CM_DIV_M2_DPLL_DDR
+	global CM_DIV_M4_DPLL_DDR
+	global CM_IDLEST_DPLL_DDR
+
+	set clksel [ mrw $CM_CLKSEL_DPLL_DDR ]
+	set div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ]
+
+	mww $CM_CLKMODE_DPLL_DDR 0x4
+	while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { }
+
+	set clksel [ expr {$clksel & (~0x7ffff)} ]
+	set clksel [ expr {$clksel | ($M << 8) | $N} ]
+	mww $CM_CLKSEL_DPLL_DDR $clksel
+
+	set div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ]
+	mww $CM_DIV_M2_DPLL_DDR $div_m2
+	mww $CM_DIV_M4_DPLL_DDR $M4
+
+	mww $CM_CLKMODE_DPLL_DDR 0x7
+	while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { }
+
+	echo "DDR DPLL Locked"
+}
+
+proc config_opp100 { } {
+	set CLKIN [ get_input_clock_frequency ]
+
+	if { $CLKIN == -1 } {
+		return -1
+	}
+
+	switch $CLKIN {
+		24000000 {
+			mpu_pll_config   $CLKIN  0  25   1
+			core_pll_config  $CLKIN  2  125  10  8  4
+			per_pll_config   $CLKIN  9  400  5
+			ddr_pll_config   $CLKIN  2  50   1   2
+		}
+
+		25000000 {
+			mpu_pll_config   $CLKIN  0  24   1
+			core_pll_config  $CLKIN  0  40   10  8  4
+			per_pll_config   $CLKIN  9  384  5
+			ddr_pll_config   $CLKIN  0  16   1   2
+		}
+
+		26000000 {
+			mpu_pll_config   $CLKIN  12  300  1
+			core_pll_config  $CLKIN  12  500  10  8  4
+			per_pll_config   $CLKIN  12  480  5
+			ddr_pll_config   $CLKIN  12  200  1   2
+		}
+
+		19200000 {
+			mpu_pll_config   $CLKIN  3   125  1
+			core_pll_config  $CLKIN  11  625  10  8  4
+			per_pll_config   $CLKIN  7   400  5
+			ddr_pll_config   $CLKIN  2   125  1   2
+		}
+	}
+}
+
+proc emif_prcm_clk_enable { } {
+	global CM_PER_EMIF_FW_CLKCTRL
+	global CM_PER_EMIF_CLKCTRL
+
+	mww $CM_PER_EMIF_FW_CLKCTRL 0x02
+	mww $CM_PER_EMIF_CLKCTRL 0x02
+
+	while { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { }
+}
+
+proc vtp_enable { } {
+	global VTP_CTRL_REG
+
+	set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }]
+	mww $VTP_CTRL_REG $vtp
+
+	set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }]
+	mww $VTP_CTRL_REG $vtp
+
+	set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }]
+	mww $VTP_CTRL_REG $vtp
+
+}
+
+proc config_ddr_ioctrl { } {
+	global DDR_ADDRCTRL_IOCTRL
+	global DDR_ADDRCTRL_WD0_IOCTRL
+	global DDR_ADDRCTRL_WD1_IOCTRL
+	global DDR_CKE_CTRL
+	global DDR_DATA0_IOCTRL
+	global DDR_DATA1_IOCTRL
+	global DDR_DATA2_IOCTRL
+	global DDR_DATA3_IOCTRL
+	global DDR_IO_CTRL
+
+	mww $DDR_ADDRCTRL_IOCTRL	0x84
+	mww $DDR_ADDRCTRL_WD0_IOCTRL	0x00
+	mww $DDR_ADDRCTRL_WD1_IOCTRL	0x00
+	mww $DDR_DATA0_IOCTRL		0x84
+	mww $DDR_DATA1_IOCTRL		0x84
+	mww $DDR_DATA2_IOCTRL		0x84
+	mww $DDR_DATA3_IOCTRL		0x84
+
+	mww $DDR_IO_CTRL		0x00
+	mww $DDR_CKE_CTRL		0x03
+}
+
+proc config_ddr_phy { } {
+	global EMIF_DDR_PHY_CTRL_1
+	global EMIF_DDR_PHY_CTRL_1_SHDW
+
+	global EXT_PHY_CTRL_1
+	global EXT_PHY_CTRL_1_SHDW
+	global EXT_PHY_CTRL_2
+	global EXT_PHY_CTRL_2_SHDW
+	global EXT_PHY_CTRL_3
+	global EXT_PHY_CTRL_3_SHDW
+	global EXT_PHY_CTRL_4
+	global EXT_PHY_CTRL_4_SHDW
+	global EXT_PHY_CTRL_5
+	global EXT_PHY_CTRL_5_SHDW
+	global EXT_PHY_CTRL_6
+	global EXT_PHY_CTRL_6_SHDW
+	global EXT_PHY_CTRL_7
+	global EXT_PHY_CTRL_7_SHDW
+	global EXT_PHY_CTRL_8
+	global EXT_PHY_CTRL_8_SHDW
+	global EXT_PHY_CTRL_9
+	global EXT_PHY_CTRL_9_SHDW
+	global EXT_PHY_CTRL_10
+	global EXT_PHY_CTRL_10_SHDW
+	global EXT_PHY_CTRL_11
+	global EXT_PHY_CTRL_11_SHDW
+	global EXT_PHY_CTRL_12
+	global EXT_PHY_CTRL_12_SHDW
+	global EXT_PHY_CTRL_13
+	global EXT_PHY_CTRL_13_SHDW
+	global EXT_PHY_CTRL_14
+	global EXT_PHY_CTRL_14_SHDW
+	global EXT_PHY_CTRL_15
+	global EXT_PHY_CTRL_15_SHDW
+	global EXT_PHY_CTRL_16
+	global EXT_PHY_CTRL_16_SHDW
+	global EXT_PHY_CTRL_17
+	global EXT_PHY_CTRL_17_SHDW
+	global EXT_PHY_CTRL_18
+	global EXT_PHY_CTRL_18_SHDW
+	global EXT_PHY_CTRL_19
+	global EXT_PHY_CTRL_19_SHDW
+	global EXT_PHY_CTRL_20
+	global EXT_PHY_CTRL_20_SHDW
+	global EXT_PHY_CTRL_21
+	global EXT_PHY_CTRL_21_SHDW
+	global EXT_PHY_CTRL_22
+	global EXT_PHY_CTRL_22_SHDW
+	global EXT_PHY_CTRL_23
+	global EXT_PHY_CTRL_23_SHDW
+	global EXT_PHY_CTRL_24
+	global EXT_PHY_CTRL_24_SHDW
+	global EXT_PHY_CTRL_25
+	global EXT_PHY_CTRL_25_SHDW
+	global EXT_PHY_CTRL_26
+	global EXT_PHY_CTRL_26_SHDW
+	global EXT_PHY_CTRL_27
+	global EXT_PHY_CTRL_27_SHDW
+	global EXT_PHY_CTRL_28
+	global EXT_PHY_CTRL_28_SHDW
+	global EXT_PHY_CTRL_29
+	global EXT_PHY_CTRL_29_SHDW
+	global EXT_PHY_CTRL_30
+	global EXT_PHY_CTRL_30_SHDW
+	global EXT_PHY_CTRL_31
+	global EXT_PHY_CTRL_31_SHDW
+	global EXT_PHY_CTRL_32
+	global EXT_PHY_CTRL_32_SHDW
+	global EXT_PHY_CTRL_33
+	global EXT_PHY_CTRL_33_SHDW
+	global EXT_PHY_CTRL_34
+	global EXT_PHY_CTRL_34_SHDW
+	global EXT_PHY_CTRL_35
+	global EXT_PHY_CTRL_35_SHDW
+	global EXT_PHY_CTRL_36
+	global EXT_PHY_CTRL_36_SHDW
+
+	mww $EMIF_DDR_PHY_CTRL_1	0x8009
+	mww $EMIF_DDR_PHY_CTRL_1_SHDW	0x8009
+
+	set slave_ratio		0x80
+	set gatelvl_init_ratio	0x20
+	set wr_dqs_slave_delay	0x60
+	set rd_dqs_slave_delay	0x60
+	set dq_offset		0x40
+	set gatelvl_init_mode	0x01
+	set wr_data_slave_delay	0x80
+	set gatelvl_num_dq0 0x0f
+	set wrlvl_num_dq0 0x0f
+
+	mww $EXT_PHY_CTRL_1        [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
+	mww $EXT_PHY_CTRL_1_SHDW   [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
+	mww $EXT_PHY_CTRL_26       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_26_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_27       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_27_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_28       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_28_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_29       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_29_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_30       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_30_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_31       0x00
+	mww $EXT_PHY_CTRL_31_SHDW  0x00
+	mww $EXT_PHY_CTRL_32       0x00
+	mww $EXT_PHY_CTRL_32_SHDW  0x00
+	mww $EXT_PHY_CTRL_33       0x00
+	mww $EXT_PHY_CTRL_33_SHDW  0x00
+	mww $EXT_PHY_CTRL_34       0x00
+	mww $EXT_PHY_CTRL_34_SHDW  0x00
+	mww $EXT_PHY_CTRL_35       0x00
+	mww $EXT_PHY_CTRL_35_SHDW  0x00
+	mww $EXT_PHY_CTRL_22       0x00
+	mww $EXT_PHY_CTRL_22_SHDW  0x00
+	mww $EXT_PHY_CTRL_23       [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]
+	mww $EXT_PHY_CTRL_23_SHDW  [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]
+	mww $EXT_PHY_CTRL_24       [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ]
+	mww $EXT_PHY_CTRL_24_SHDW  [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ]
+	mww $EXT_PHY_CTRL_25       [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
+	mww $EXT_PHY_CTRL_25_SHDW  [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
+	mww $EXT_PHY_CTRL_36       [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
+	mww $EXT_PHY_CTRL_36_SHDW  [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
+}
+
+proc config_ddr_timing { } {
+	global EMIF_SDRAM_TIM_1
+	global EMIF_SDRAM_TIM_2
+	global EMIF_SDRAM_TIM_3
+	global EMIF_SDRAM_TIM_1_SHDW
+	global EMIF_SDRAM_TIM_2_SHDW
+	global EMIF_SDRAM_TIM_3_SHDW
+	global EMIF_ZQ_CONFIG
+
+	mww $EMIF_SDRAM_TIM_1		0xeaaad4db
+	mww $EMIF_SDRAM_TIM_1_SHDW	0xeaaad4db
+
+	mww $EMIF_SDRAM_TIM_2		0x266b7fda
+	mww $EMIF_SDRAM_TIM_2_SHDW	0x266b7fda
+
+	mww $EMIF_SDRAM_TIM_3		0x107f8678
+	mww $EMIF_SDRAM_TIM_3_SHDW	0x107f8678
+
+	mww $EMIF_ZQ_CONFIG		0x50074be4
+}
+
+proc config_ddr_pm { } {
+	global EMIF_PWR_MGMT_CTRL
+	global EMIF_PWR_MGMT_CTRL_SHDW
+	global EMIF_DLL_CALIB_CTRL
+	global EMIF_DLL_CALIB_CTRL_SHDW
+	global EMIF_TEMP_ALERT_CONFIG
+
+	mww $EMIF_PWR_MGMT_CTRL		0x00
+	mww $EMIF_PWR_MGMT_CTRL_SHDW	0x00
+	mww $EMIF_DLL_CALIB_CTRL	0x00050000
+	mww $EMIF_DLL_CALIB_CTRL_SHDW	0x00050000
+	mww $EMIF_TEMP_ALERT_CONFIG	0x00
+}
+
+proc config_ddr_priority { } {
+	global EMIF_PRI_COS_MAP
+	global EMIF_CONNID_COS_1_MAP
+	global EMIF_CONNID_COS_2_MAP
+	global EMIF_RD_WR_EXEC_THRSH
+	global COS_CONFIG
+
+	mww $EMIF_PRI_COS_MAP       0x00
+	mww $EMIF_CONNID_COS_1_MAP  0x00
+	mww $EMIF_CONNID_COS_2_MAP  0x0
+	mww $EMIF_RD_WR_EXEC_THRSH  0x0405
+	mww $COS_CONFIG             0x00ffffff
+}
+
+proc config_ddr3 { SDRAM_CONFIG } {
+	global CM_DLL_CTRL
+	global EMIF_IODFT_TLGC
+	global EMIF_RDWR_LVL_CTRL
+	global EMIF_RDWR_LVL_RMP_CTRL
+	global EMIF_SDRAM_CONFIG
+	global EMIF_SDRAM_CONFIG_EXT
+	global EMIF_SDRAM_REF_CTRL
+	global EMIF_SDRAM_REF_CTRL_SHDW
+	global EMIF_STATUS
+	global EXT_PHY_CTRL_36
+	global EXT_PHY_CTRL_36_SHDW
+
+	emif_prcm_clk_enable
+	vtp_enable
+
+	set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }]
+	mww $CM_DLL_CTRL $dll
+	while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }
+
+	config_ddr_ioctrl
+
+	mww $EMIF_SDRAM_CONFIG_EXT	0xc163
+	mww $EMIF_IODFT_TLGC		0x2011
+	mww $EMIF_IODFT_TLGC		0x2411
+	mww $EMIF_IODFT_TLGC		0x2011
+	mww $EMIF_SDRAM_REF_CTRL	0x80003000
+
+	config_ddr_phy
+
+	mww $EMIF_IODFT_TLGC		0x2011
+	mww $EMIF_IODFT_TLGC		0x2411
+	mww $EMIF_IODFT_TLGC		0x2011
+
+	config_ddr_timing
+	config_ddr_pm
+	config_ddr_priority
+
+	mww $EMIF_SDRAM_REF_CTRL	0x3000
+	mww $EMIF_SDRAM_CONFIG		$SDRAM_CONFIG
+
+	mww $EMIF_SDRAM_REF_CTRL	0x0c30
+	mww $EMIF_SDRAM_REF_CTRL_SHDW	0x0c30
+
+	sleep 10
+
+	set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }]
+	mww $EXT_PHY_CTRL_36		$tmp
+	mww $EXT_PHY_CTRL_36_SHDW	$tmp
+
+	mww $EMIF_RDWR_LVL_RMP_CTRL	0x80000000
+	mww $EMIF_RDWR_LVL_CTRL		0x80000000
+
+	while { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { }
+
+	if { [ mrw $EMIF_STATUS ]  & 0x70 } {
+		error "DDR3 Hardware Leveling incomplete!!!"
+	}
+}
+
+proc init_platform { SDRAM_CONFIG } {
+	config_opp100
+	config_ddr3 $SDRAM_CONFIG
+}
+
+$_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 }
+$_TARGETNAME configure -event reset-end { disable_watchdog }
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/amdm37x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/amdm37x.cfg
new file mode 100644
index 0000000..d9adae9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/amdm37x.cfg
@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Copyright (C)   2010-2011   by Karl Kurbjun
+# Copyright (C)   2009-2011   by Øyvind Harboe
+# Copyright (C)   2009        by David Brownell
+# Copyright (C)   2009        by Magnus Lundin
+#
+# TI AM/DM37x Technical Reference Manual (Version R)
+#  http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf
+#
+# This script is based on the AM3517 initialization.  It should be considered
+# preliminary since it needs more complete testing and only the basic
+# operations work.
+#
+
+###############################################################################
+# User modifiable parameters
+###############################################################################
+
+# This script uses the variable CHIPTYPE to determine whether this is an AM35x
+# or DM37x target. If CHIPTYPE is not set it will error out.
+if { [info exists CHIPTYPE] } {
+
+   if { [info exists CHIPNAME] } {
+      set _CHIPNAME $CHIPNAME
+   } else {
+      set _CHIPNAME $CHIPTYPE
+   }
+
+   switch $CHIPTYPE {
+      dm37x {
+         # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
+         set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"
+      }
+      am35x {
+         # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
+         set _JRC_TAPID "-expected-id 0x0b7ae02f -expected-id 0x0b86802f"
+      }
+      default {
+         error "ERROR: CHIPTYPE was set, but it was not set to a valid value.  Acceptable values are \"dm37x\" or \"am35x\"."
+      }
+   }
+} else {
+  error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
+}
+
+# Run the adapter at the fastest acceptable speed with the slowest possible
+# core clock.
+adapter speed 10
+
+###############################################################################
+# JTAG setup
+# The OpenOCD commands are described in the TAP Declaration section
+#  http://openocd.org/doc/html/TAP-Declaration.html
+###############################################################################
+
+# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More
+#  can be read about this module in sprugn4r in chapter 27:  "Debug and
+#  Emulation".  The module is used to route the JTAG chain to the various
+#  subsystems in the chip.
+source [find target/icepick.cfg]
+
+# The TAP order should be described from the TDO connection in OpenOCD to the
+#  TDI pin.  The OpenOCD FAQ describes this in more detail:
+#  http://openocd.org/doc/html/FAQ.html
+
+# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO:
+#
+#  Device   |  TAP number
+#  ---------|------------
+#  DAP      |  3
+#  Sequencer|  2   Note: The sequencer is an ARM968
+#  DSP      |  1
+#  D2D      |  0
+#
+# Right now the only secondary tap enabled is the DAP so the rest are left
+# undescribed.
+
+######
+# Start of Chain Description
+# The Secondary TAPs all have enable functions defined for use with the ICEPick
+# Only the DAP is enabled.  The AM37xx does not have the Sequencer or DSP but
+# the TAP numbers for ICEPick do not change.
+#
+# TODO: A disable function should also be added.
+######
+
+# Secondary TAP: DAP is closest to the TDO output
+# The TAP enable event also needs to be described
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+   "icepick_c_tapenable $_CHIPNAME.jrc 3"
+
+# These taps are only present in the DM37x series.
+if { $CHIPTYPE == "dm37x" } {
+   # Secondary TAP: Sequencer (ARM968) it is not in the chain by default
+   # The ICEPick can be used to enable it in the chain.
+   jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
+   jtag configure $_CHIPNAME.arm2 -event tap-enable \
+      "icepick_c_tapenable $_CHIPNAME.jrc 2"
+
+   # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
+   # The ICEPick can be used to enable it in the chain.
+   jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
+   jtag configure $_CHIPNAME.dsp -event tap-enable \
+      "icepick_c_tapenable $_CHIPNAME.jrc 1"
+}
+
+# Secondary TAP: D2D it is not in the chain by default (-disable)
+# The ICEPick can be used to enable it in the chain.
+# This IRLEN is probably incorrect - not sure where the documentation is.
+jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
+jtag configure $_CHIPNAME.d2d -event tap-enable \
+   "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEPick - it is closest to TDI so last in the chain
+eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
+
+######
+# End of Chain Description
+######
+
+######
+# Start JTAG TAP events
+######
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+# Enable the DAP TAP
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+
+######
+# End JTAG TAP events
+######
+
+###############################################################################
+# Target Setup:
+# This section is described in the OpenOCD documentation under CPU Configuration
+#  http://openocd.org/doc/html/CPU-Configuration.html
+###############################################################################
+
+# Create the CPU target to be used with GDB:  Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+# The DM37x has 64K of SRAM starting at address 0x4020_0000.  Allow the first
+# 16K to be used as a scratchpad for OpenOCD.
+
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
+
+######
+# Start Target Reset Event Setup:
+######
+
+# Set the JTAG clock down to 10 kHz to be sure that it will work with the
+#  slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
+#  *after* PLL and clock tree setup.
+
+$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
+
+# Describe the reset assert process for openocd - this is asserted with the
+# ICEPick
+$_TARGETNAME configure -event "reset-assert" {
+
+   global _CHIPNAME
+
+   # assert warm system reset through ICEPick
+   icepick_c_wreset $_CHIPNAME.jrc
+}
+
+# After the reset is asserted we need to re-initialize debugging and speed up
+# the JTAG clock.
+
+$_TARGETNAME configure -event reset-assert-post {
+
+   global _TARGETNAME
+   amdm37x_dbginit $_TARGETNAME
+   adapter speed 1000
+}
+
+$_TARGETNAME configure -event gdb-attach {
+
+   global _TARGETNAME
+   amdm37x_dbginit $_TARGETNAME
+
+   echo "Halting target"
+   halt
+}
+
+######
+# End Target Reset Event Setup:
+######
+
+###############################################################################
+# Target Functions
+# Add any functions needed for the target here
+###############################################################################
+
+# Run this to enable invasive debugging.  This is run automatically in the
+# reset sequence.
+proc amdm37x_dbginit {target} {
+   # General Cortex-A8 debug initialisation
+   cortex_a dbginit
+
+   # Enable DBGEN signal.  This signal is described in the ARM v7 TRM, but
+   # access to the signal appears to be implementation specific.  TI does not
+   # describe this register much except a quick line that states DBGEM (sic) is
+   # at this address and this bit.
+   $target mww phys 0x5401d030 0x00002000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ampere_emag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ampere_emag.cfg
new file mode 100644
index 0000000..fd68fcd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ampere_emag.cfg
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# OpenOCD Target Configuration for eMAG ARMv8 Processor
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+#
+
+#
+# Configure defaults for target
+# Can be overridden in board configuration file
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME emag
+}
+
+if { [info exists NUMCORES] } {
+	set _NUMCORES $NUMCORES
+} else {
+	set _NUMCORES 32
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4BA00477
+}
+
+#
+# Configure JTAG TAP
+#
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_CPUTAPID
+set _TAPNAME $_CHIPNAME.cpu
+
+set _DAPNAME ${_TAPNAME}_dap
+set _APNUM 1
+dap create $_DAPNAME -chain-position $_TAPNAME
+$_DAPNAME apsel $_APNUM
+
+# Create the DAP AP0 MEM-AP AHB-AP target
+target create AHB mem_ap -endian $_ENDIAN -dap $_DAPNAME -ap-num 0
+
+# Create the DAP AP1 MEM-AP APB-AP target
+target create APB mem_ap -endian $_ENDIAN -dap $_DAPNAME -ap-num 1
+
+#
+# Configure target CPUs
+#
+
+# Build string used to enable smp mode
+set _SMP_STR "target smp"
+
+for {set _i 0} {$_i < $_NUMCORES} {incr _i} {
+	# Format a string to reference which CPU target to use
+	set _TARGETNAME [format "${_TAPNAME}_%02d" $_i]
+
+	# Create and configure Cross Trigger Interface (CTI) - required for halt and resume
+	set _CTINAME $_TARGETNAME.cti
+	cti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr {0xFC020000 + ($_i << 20)}]
+
+	# Create the target
+	target create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_DAPNAME -ap-num $_APNUM -cti $_CTINAME -coreid $_i
+	set _SMP_STR "$_SMP_STR $_TARGETNAME"
+
+	# Clear CTI output/input enables that are not configured by OpenOCD for aarch64
+	$_TARGETNAME configure -event examine-start [subst {
+		$_CTINAME write INEN0 0x00000000
+		$_CTINAME write INEN1 0x00000000
+		$_CTINAME write INEN2 0x00000000
+		$_CTINAME write INEN3 0x00000000
+		$_CTINAME write INEN4 0x00000000
+		$_CTINAME write INEN5 0x00000000
+		$_CTINAME write INEN6 0x00000000
+		$_CTINAME write INEN7 0x00000000
+		$_CTINAME write INEN8 0x00000000
+
+		$_CTINAME write OUTEN2 0x00000000
+		$_CTINAME write OUTEN3 0x00000000
+		$_CTINAME write OUTEN4 0x00000000
+		$_CTINAME write OUTEN5 0x00000000
+		$_CTINAME write OUTEN6 0x00000000
+		$_CTINAME write OUTEN7 0x00000000
+		$_CTINAME write OUTEN8 0x00000000
+	}]
+
+	# Enable OpenOCD HWTHREAD RTOS feature for GDB thread (CPU) selection support
+	# This feature presents CPU cores ("hardware threads") in an SMP system as threads to GDB
+	$_TARGETNAME configure -rtos hwthread
+}
+eval $_SMP_STR
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ampere_qs_mq.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ampere_qs_mq.cfg
new file mode 100644
index 0000000..0e83766
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ampere_qs_mq.cfg
@@ -0,0 +1,333 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# OpenOCD Target Configuration for Ampere Altra ("Quicksilver") and
+# Ampere Altra Max ("Mystique") processors
+#
+# Copyright (c) 2019-2022, Ampere Computing LLC
+
+# Command Line Argument Description
+#
+# SPLITSMP
+# Only used for dual socket systems. Do not use for a single socket setup.
+# Option pertains to the ARMv8 target core naming in a dual socket setup.
+# If specified, name all ARMv8 cores per socket as individual SMP sessions.
+# If not specified, name ARMv8 cores from both sockets as one SMP session.
+# This option is used in conjunction with the SMP_STR board file option.
+# Syntax: -c "set SPLITSMP {}"
+#
+# PHYS_IDX
+# Enable OpenOCD ARMv8 core target physical indexing.
+# If not specified, defaults to OpenOCD ARMv8 core target logical indexing.
+# Syntax: -c "set PHYS_IDX {}"
+#
+# CHIPNAME
+# Specifies the name of the chip.
+# Will typically be either qs, qs0, qs1, mq, mq0 or mq1.
+# If not specified, defaults to qs.
+# Syntax: -c "set CHIPNAME {qs}"
+#
+# SYSNAME
+# Specifies the name of the system.
+# Will typically be either qs or mq.
+# If not specified, defaults to qs.
+# Syntax: -c "set SYSNAME {qs}"
+#
+# Life-Cycle State (LCS)
+# If not specified, defaults to "Secure LCS".
+# LCS=0, "Secure LCS"
+# LCS=1, "Chip Manufacturing LCS"
+# Syntax: -c "set LCS {0}"
+# Syntax: -c "set LCS {1}"
+#
+# CORELIST
+# Specify available physical cores by number.
+# Example syntax to connect to physical cores 16 and 17.
+# Syntax: -c "set CORELIST {16 17}"
+#
+# COREMASK_LO
+# Specify available physical cores 0-63 by mask.
+# Example syntax to connect to physical cores 16 and 17.
+# Syntax: -c "set COREMASK_LO {0x0000000000030000}"
+#
+# COREMASK_HI
+# Specify available physical cores 64 and above by mask.
+# Example syntax to connect to physical cores 94 and 95.
+# Syntax: -c "set COREMASK_HI {0x00000000C0000000}"
+#
+# ARMV8_TAPID
+# Can override the ARMV8 TAPID default value if necessary.
+# Experimental Use. Most users will not use this option.
+# Syntax: -c "set ARMV8_TAPID {0x3BA06477}"
+#
+# SMPMPRO_TAPID
+# Can override the SMPMPRO TAPID default value if necessary.
+# Experimental Use. Most users will not use this option.
+# Syntax: -c "set SMPMPRO_TAPID {0x4BA00477}"
+#
+#
+# Board File Argument Description
+# These optional arguments are defined in the board file and
+# referenced by the target file. See the corresponding board
+# files for examples of their use.
+#
+# SMP_STR
+# This option is used primarily for a dual socket system and it is not
+# recommended for a single socket setup. This option configures whether
+# the SMP ARMv8 core grouping is maintained at the board or target cfg level.
+# Specify the option if the SMP core grouping is defined at the board level.
+# Do not specify if the SMP core grouping is defined at the chip level.
+# If not specified, defaults to SMP core grouping defined per socket.
+# If specified, "SMP_STR=target smp", the SMP core grouping is maintained
+# at the board cfg level.
+# Used in conjunction with the SPLITSMP option to group two chips into
+# a single SMP configuration or maintain as two separate SMP sessions.
+#
+# CORE_INDEX_OFFSET
+# Specifies the starting logical core index value.
+# Used for dual-socket systems.
+# For socket #0, set to 0.
+# For socket #1, set the starting logical core based from
+# the last logical core on socket #0.
+# If not specified, defaults to 0.
+#
+
+#
+# Configure defaults for target.
+# Can be overridden in board configuration file.
+#
+
+if { [info exists SMP_STR] } {
+	# SMP configured at the dual socket board level
+	set _SMP_STR $SMP_STR
+} else {
+	# SMP configured at the single socket target level
+	set _SMP_STR "target smp"
+}
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME qs
+}
+
+if { [info exists SYSNAME] } {
+	set _SYSNAME $SYSNAME
+} else {
+	set _SYSNAME qs
+}
+
+if { [info exists CORE_INDEX_OFFSET] } {
+	set _CORE_INDEX_OFFSET $CORE_INDEX_OFFSET
+} else {
+	set _CORE_INDEX_OFFSET 0
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists ARMV8_TAPID] } {
+	set _ARMV8_TAPID $ARMV8_TAPID
+} else {
+	if { [info exists MQ_ENABLE] } {
+		# Configure for Mystique
+		set _ARMV8_TAPID 0x3BA06477
+		set _MAX_CORE 128
+	} else {
+		# Configure for Quicksilver
+		set _ARMV8_TAPID 0x2BA06477
+		set _MAX_CORE 80
+	}
+}
+
+if { [info exists SMPMPRO_TAPID] } {
+	set _SMPMPRO_TAPID $SMPMPRO_TAPID
+} else {
+	set _SMPMPRO_TAPID 0x4BA00477
+}
+
+if { [info exists CORELIST] } {
+	set _CORELIST $CORELIST
+} else {
+	if { [info exists COREMASK_LO] } {
+		set _COREMASK_LO $COREMASK_LO
+	} else {
+		set _COREMASK_LO 0x0
+	}
+
+	if { [info exists COREMASK_HI] } {
+		set _COREMASK_HI $COREMASK_HI
+	} else {
+		set _COREMASK_HI 0x0
+	}
+
+	set _CORELIST {}
+
+	set _MASK 0x1
+	for {set i 0} {$i < 64} {incr i} {
+		if { [expr {$_COREMASK_LO & $_MASK}] != 0x0 } {
+			set _CORELIST "$_CORELIST $i"
+		}
+		set _MASK [expr {$_MASK << 0x1}]
+	}
+
+	set _MASK 0x1
+	for {} {$i < $_MAX_CORE} {incr i} {
+		if { [expr {$_COREMASK_HI & $_MASK}] != 0x0 } {
+			set _CORELIST "$_CORELIST $i"
+		}
+		set _MASK [expr {$_MASK << 0x1}]
+	}
+}
+
+#
+# Definition of target names
+#
+set _TARGETNAME_PMPRO pmpro
+set _TARGETNAME_SMPRO smpro
+set _TARGETNAME_ARMV8 armv8
+
+#
+# Configure JTAG TAPs - TAP chain declaration order is important
+#
+
+jtag newtap $_CHIPNAME pmpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
+set _TAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.tap
+
+jtag newtap $_CHIPNAME smpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
+set _TAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.tap
+
+jtag newtap $_CHIPNAME armv8.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_ARMV8_TAPID
+set _TAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.tap
+
+set _DAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.dap
+set _DAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.dap
+set _DAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.dap
+
+set _AP_PMPRO_AHB 0
+set _AP_SMPRO_AHB 0
+set _AP_ARMV8_APB 0x00010000
+set _AP_ARMV8_AXI 0x00020000
+
+#
+# Configure JTAG DAPs
+#
+
+dap create $_DAPNAME_PMPRO -chain-position $_TAPNAME_PMPRO -adiv5
+dap create $_DAPNAME_SMPRO -chain-position $_TAPNAME_SMPRO -adiv5
+dap create $_DAPNAME_ARMV8 -chain-position $_TAPNAME_ARMV8 -adiv6
+
+if { [info exists LCS] && [expr {"$LCS"!="0"}] } {
+	#
+	# Create the DAP AHB-AP MEM-AP target for the PMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_PMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
+
+	#
+	# Configure target PMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_PMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
+
+	#
+	# Create the DAP AHB-AP MEM-AP target for the SMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_SMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
+
+	#
+	# Configure target SMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_SMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
+}
+
+# Create the DAP APB-AP MEM-AP target for the ARMV8 cores
+target create $_CHIPNAME.$_TARGETNAME_ARMV8.apb mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB
+
+# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores
+target create $_CHIPNAME.$_TARGETNAME_ARMV8.axi mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_AXI
+
+# Set CSW register value default correctly for AXI accessible device memory:
+# Select the correct Access Port Number
+$_DAPNAME_ARMV8 apsel $_AP_ARMV8_AXI
+# First set the CSW to OpenOCD's internal default
+$_DAPNAME_ARMV8 apcsw default
+# Set Domain[1:0]=b'11  (CSW[14:13]=b'11)
+# Set Cache[3:0]=b'0000 (CSW[27:24]=b'0000)
+# Porter Cfg registers require secure access, AxPROT[1] (CSW[29]) must be b'0'.
+# Set AxPROT[2:0]=b'000 (CSW[30:28]=b'000) for an Unpriveleged, Secure, Data access.
+$_DAPNAME_ARMV8 apcsw 0x00006000 0x7F006000
+
+#
+# Configure target CPUs
+#
+
+set logical_index $_CORE_INDEX_OFFSET
+
+foreach physical_index $_CORELIST {
+	if { [info exists PHYS_IDX] } {
+		set logical_index [expr {$physical_index + $_CORE_INDEX_OFFSET}]
+	}
+
+	# Format a string to reference which CPU target to use
+	if { [info exists SPLITSMP] } {
+		eval "set _TARGETNAME $_CHIPNAME.${_TARGETNAME_ARMV8}_$logical_index"
+	} else {
+		eval "set _TARGETNAME $_SYSNAME.${_TARGETNAME_ARMV8}_$logical_index"
+	}
+
+	# Create and configure Cross Trigger Interface (CTI) - required for halt and resume
+	set _CTINAME $_TARGETNAME.cti
+	set _offset [expr {(0x00100000 * $physical_index) + (0x00200000 * ($physical_index>>1))}]
+	cti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr {0xA0220000 + $_offset}]
+
+	# Create the target
+	target create $_TARGETNAME aarch64 -endian $_ENDIAN \
+		-dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr {0xA0210000 + $_offset}] \
+		-rtos hwthread -cti $_CTINAME -coreid $logical_index
+
+	# Build string used to enable SMP mode for the ARMv8 CPU cores
+	set _SMP_STR "$_SMP_STR $_TARGETNAME"
+
+	# Clear CTI output/input enables that are not configured by OpenOCD for aarch64
+	$_TARGETNAME configure -event reset-init [subst {
+		$_CTINAME write INEN0 0x00000000
+		$_CTINAME write INEN1 0x00000000
+		$_CTINAME write INEN2 0x00000000
+		$_CTINAME write INEN3 0x00000000
+		$_CTINAME write INEN4 0x00000000
+		$_CTINAME write INEN5 0x00000000
+		$_CTINAME write INEN6 0x00000000
+		$_CTINAME write INEN7 0x00000000
+		$_CTINAME write INEN8 0x00000000
+
+		$_CTINAME write OUTEN0 0x00000000
+		$_CTINAME write OUTEN1 0x00000000
+		$_CTINAME write OUTEN2 0x00000000
+		$_CTINAME write OUTEN3 0x00000000
+		$_CTINAME write OUTEN4 0x00000000
+		$_CTINAME write OUTEN5 0x00000000
+		$_CTINAME write OUTEN6 0x00000000
+		$_CTINAME write OUTEN7 0x00000000
+		$_CTINAME write OUTEN8 0x00000000
+	}]
+
+	incr logical_index
+}
+
+if { [info exists SMP_STR] } {
+	# Return updated SMP configuration string back to board level
+	set SMP_STR $_SMP_STR
+} else {
+	# For single socket per SMP configuration, evaluate the string
+	eval $_SMP_STR
+}
+
+if { [info exists CORE_INDEX_OFFSET] } {
+	# For multi-socket, return total number of cores back to board level
+	set CORE_INDEX_OFFSET $logical_index
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ar71xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ar71xx.cfg
new file mode 100644
index 0000000..792b68f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ar71xx.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Atheros AR71xx MIPS 24Kc SoC.
+# tested on PB44 refererence board
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+reset_config trst_and_srst
+
+set CHIPNAME ar71xx
+
+jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
+
+set _TARGETNAME $CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-halt-post {
+	#setup PLL to lowest common denominator 300/300/150 setting
+	mww 0xb8050000 0x000f40a3	;# reset val + CPU:3 DDR:3 AHB:0
+	mww 0xb8050000 0x800f40a3	;# send to PLL
+
+	#next command will reset for PLL changes to take effect
+	mww 0xb8050008 3		;# set reset_switch and clock_switch (resets SoC)
+}
+
+$_TARGETNAME configure -event reset-init {
+	#complete pll initialization
+	mww 0xb8050000 0x800f0080	;# set sw_update bit
+	mww 0xb8050008 0		;# clear reset_switch bit
+	mww 0xb8050000 0x800f00e8       ;# clr pwrdwn & bypass
+	mww 0xb8050008 1		;# set clock_switch bit
+	sleep 1                         ;# wait for lock
+
+	# Setup DDR config and flash mapping
+	mww 0xb8000000 0xefbc8cd0       ;# DDR cfg cdl val (rst: 0x5bfc8d0)
+	mww 0xb8000004 0x8e7156a2       ;# DDR cfg2 cdl val (rst: 0x80d106a8)
+
+	mww 0xb8000010 8		;# force precharge all banks
+	mww 0xb8000010 1 		;# force EMRS update cycle
+	mww 0xb800000c 0                ;# clr ext. mode register
+	mww 0xb8000010 2 		;# force auto refresh all banks
+	mww 0xb8000010 8		;# force precharge all banks
+	mww 0xb8000008 0x31             ;# set DDR mode value CAS=3
+	mww 0xb8000010 1 		;# force EMRS update cycle
+	mww 0xb8000014 0x461b           ;# DDR refresh value
+	mww 0xb8000018 0xffff           ;# DDR Read Data This Cycle value (16bit: 0xffff)
+	mww 0xb800001c 0x7              ;# delay added to the DQS line (normal = 7)
+	mww 0xb8000020 0
+	mww 0xb8000024 0
+	mww 0xb8000028 0
+}
+
+# setup working area somewhere in RAM
+$_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
+
+# serial SPI capable flash
+# flash bank     
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/arm_corelink_sse200.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/arm_corelink_sse200.cfg
new file mode 100644
index 0000000..7327d05
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/arm_corelink_sse200.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs.
+#
+
+global TARGET
+set TARGET $_CHIPNAME
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+#
+# SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB
+# We will configure work area assuming 8-KB bank size in SRAM bank 1.
+# Also SRAM start addresses defaults to secure mode alias.
+# These values can be overridden as per board configuration
+#
+
+global _WORKAREASIZE_CPU0
+if { [info exists WORKAREASIZE_CPU0] } {
+	set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0
+} else {
+	set _WORKAREASIZE_CPU0 0x1000
+}
+
+global _WORKAREAADDR_CPU0
+if { [info exists WORKAREAADDR_CPU0] } {
+	set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0
+} else {
+	set _WORKAREAADDR_CPU0 0x30008000
+}
+
+#
+# Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200
+# Core 0 is the boot core and will always be configured.
+#
+
+target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
+
+${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0
+
+${TARGET}.CPU0 cortex_m reset_config sysresetreq
+
+#
+# Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200
+# Core 1 is optional and locked at boot until core 0 unlocks it.
+#
+
+if { $_ENABLE_CPU1 } {
+	global _WORKAREASIZE_CPU1
+	if { [info exists WORKAREASIZE_CPU1] } {
+		set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1
+	} else {
+		set _WORKAREASIZE_CPU1 0x1000
+	}
+
+	global _WORKAREAADDR_CPU1
+	if { [info exists WORKAREAADDR_CPU1] } {
+		set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1
+	} else {
+		set _WORKAREAADDR_CPU1 0x30009000
+	}
+
+	target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
+
+	${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0
+
+	${TARGET}.CPU1 cortex_m reset_config vectreset
+}
+
+# Make sure the default target is the boot core
+targets ${TARGET}.CPU0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/armada370.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/armada370.cfg
new file mode 100644
index 0000000..ccf4b36
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/armada370.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# armada370 -- support for the Marvell Armada/370 CPU family
+#
+# gerg@uclinux.org, OCT-2013
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME armada370
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+proc armada370_dbginit {target} {
+     cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-assert-post "armada370_dbginit $_TARGETNAME"
+
+dap apsel 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at32ap7000.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at32ap7000.cfg
new file mode 100644
index 0000000..bbae247
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at32ap7000.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Atmel AT32AP7000
+#
+# This is the only core in the now-inactive high end AVR32 product line,
+# with MMU, Java Acceleration, and "pixel coprocessor".  The AP7 line
+# is for "Application Processors" (AP) with 7-stage pipelines.
+#
+# Most current AVR32 parts are in the UC3 flash based microcontroller (UC)
+# product line with 3-stage pipelines and without those extras.
+#
+# All AVR32 parts provide the Nexus Class 3 on-chip debug interfaces
+# through their JTAG interfaces.
+
+jtag newtap ap7 nexus -irlen 5 -expected-id 0x21e8203f
+
+# REVISIT declare an avr32 target ... needs OpenOCD infrastructure
+# for both Nexus (generic) and AVR32 (Atmel-specific).
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91r40008.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91r40008.cfg
new file mode 100644
index 0000000..66d32ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91r40008.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# AT91R40008 target configuration file
+
+# TRST is tied to SRST on the AT91X40 family.
+reset_config srst_only srst_pulls_trst
+
+
+if {[info exists CHIPNAME]} {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91r40008
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Setup the JTAG scan chain.
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91rm9200.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91rm9200.cfg
new file mode 100644
index 0000000..1bc1287
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91rm9200.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Atmel AT91rm9200
+# http://atmel.com/products/at91/
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91rm9200
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x05b0203f
+}
+
+# Never allow the following!
+if { $_CPUTAPID == 0x15b0203f } {
+   echo "-------------------------------------------------------"
+   echo "- ERROR:                                              -"
+   echo "- ERROR: TapID 0x15b0203f is wrong for at91rm9200     -"
+   echo "- ERROR: The chip/board has a JTAG select pin/jumper  -"
+   echo "- ERROR:                                              -"
+   echo "- ERROR: In one position (0x05b0203f) it selects the  -"
+   echo "- ERROR: ARM CPU, in the other position (0x1b0203f)   -"
+   echo "- ERROR: it selects boundary-scan not the ARM         -"
+   echo "- ERROR:                                              -"
+   echo "-------------------------------------------------------"
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# AT91RM9200 has a 16K block of sram @ 0x0020.0000
+$_TARGETNAME configure -work-area-phys 0x00200000 \
+		-work-area-size 0x4000 -work-area-backup 1
+
+# This chip has a DCC ... use it
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3XXX.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3XXX.cfg
new file mode 100644
index 0000000..ba1c3c5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3XXX.cfg
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam3, a Cortex-M3 chip
+#
+# at91sam3u4e
+# at91sam3u2e
+# at91sam3u1e
+# at91sam3u4c
+# at91sam3u2c
+# at91sam3u1c
+#
+# at91sam3s4c
+# at91sam3s4b
+# at91sam3s4a
+# at91sam3s2c
+# at91sam3s2b
+# at91sam3s2a
+# at91sam3s1c
+# at91sam3s1b
+# at91sam3s1a
+#
+# at91sam3A4C
+# at91sam3A8C
+# at91sam3X4C
+# at91sam3X4E
+# at91sam3X8C
+# at91sam3X8E
+# at91sam3X8H
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME sam3
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# 16K is plenty, the smallest chip has this much
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+$_TARGETNAME configure -event gdb-flash-erase-start {
+    halt
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3ax_4x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3ax_4x.cfg
new file mode 100644
index 0000000..4e0cf79
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3ax_4x.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3ax_xx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
+# This is a 256K chip - it has the 2nd bank
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam3 0x0000A0000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3ax_8x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3ax_8x.cfg
new file mode 100644
index 0000000..46d580d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3ax_8x.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3ax_xx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
+# This is a 512K chip - it has the 2nd bank
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3ax_xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3ax_xx.cfg
new file mode 100644
index 0000000..7837f69
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3ax_xx.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam3, a Cortex-M3 chip
+#
+# at91sam3A4C
+# at91sam3A8C
+# at91sam3X4C
+# at91sam3X4E
+# at91sam3X8C
+# at91sam3X8E
+# at91sam3X8H
+source [find target/at91sam3XXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3nXX.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3nXX.cfg
new file mode 100644
index 0000000..9b20373
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3nXX.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration for Atmel's SAM3N series
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME at91sam3n
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3sXX.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3sXX.cfg
new file mode 100644
index 0000000..a2afda2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3sXX.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam3, a Cortex-M3 chip
+#
+# at91sam3s4c
+# at91sam3s4b
+# at91sam3s4a
+# at91sam3s2c
+# at91sam3s2b
+# at91sam3s2a
+# at91sam3s1c
+# at91sam3s1b
+# at91sam3s1a
+
+source [find target/at91sam3XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x00400000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u1c.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u1c.cfg
new file mode 100644
index 0000000..b26662b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u1c.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u1e.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u1e.cfg
new file mode 100644
index 0000000..b26662b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u1e.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u2c.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u2c.cfg
new file mode 100644
index 0000000..b26662b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u2c.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u2e.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u2e.cfg
new file mode 100644
index 0000000..b26662b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u2e.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u4c.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u4c.cfg
new file mode 100644
index 0000000..fb1eeaa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u4c.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
+# This is a 256K chip, it has the 2nd bank
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u4e.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u4e.cfg
new file mode 100644
index 0000000..1c75f82
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3u4e.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
+# This is a 256K chip - it has the 2nd bank
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3uxx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3uxx.cfg
new file mode 100644
index 0000000..f084b9b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam3uxx.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam3, a Cortex-M3 chip
+#
+# at91sam3u4e
+# at91sam3u2e
+# at91sam3u1e
+# at91sam3u4c
+# at91sam3u2c
+# at91sam3u1c
+
+source [find target/at91sam3XXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4XXX.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4XXX.cfg
new file mode 100644
index 0000000..9c30ddf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4XXX.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# script for ATMEL sam4, a Cortex-M4 chip
+#
+
+#
+# sam4 devices can support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME sam4
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# 16K is plenty, the smallest chip has this much
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4c32x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4c32x.cfg
new file mode 100644
index 0000000..ddcdd12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4c32x.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4c32, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam4 0x01100000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4cXXX.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4cXXX.cfg
new file mode 100644
index 0000000..a0206ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4cXXX.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4c, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4lXX.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4lXX.cfg
new file mode 100644
index 0000000..0910e30
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4lXX.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4l, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME
+
+# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N
+# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3).
+#
+# smap_reset_deassert configures whether we want to run or halt out of reset,
+# then instruct the SMAP to let us out of reset.
+$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert"
+
+# SRST (wired to RESET_N) resets debug circuitry
+# srst_pulls_trst is not configured here to avoid an error raised in reset halt
+reset_config srst_gates_jtag
+
+# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed.
+# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
+# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
+# but your mileage may vary.
+adapter speed 50
+
+# System RC oscillator RCSYS starts in 3 cycles
+adapter srst delay 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4sXX.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4sXX.cfg
new file mode 100644
index 0000000..2ceca00
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4sXX.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4sd32x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4sd32x.cfg
new file mode 100644
index 0000000..24e25e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam4sd32x.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4sd32, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam4 0x00500000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7a2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7a2.cfg
new file mode 100644
index 0000000..f8090c7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7a2.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91sam7a2
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7se512.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7se512.cfg
new file mode 100644
index 0000000..2972494
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7se512.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ATMEL sam7se512
+# Example: the "Elektor Internet Radio" - EIR
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME sam7se512
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # Force an error until we get a good number.
+   set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# The target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank       [      ]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7sx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7sx.cfg
new file mode 100644
index 0000000..fee4e9a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7sx.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91sam7s
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -event reset-init {
+        soft_reset_halt
+        # RSTC_CR : Reset peripherals
+        mww 0xfffffd00 0xa5000004
+        # disable watchdog
+	mww 0xfffffd44 0x00008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=73)
+	mww 0xffffff60 0x00490100
+	sleep 100
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank       [      ]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7x256.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7x256.cfg
new file mode 100644
index 0000000..2ebbf22
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7x256.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME sam7x256
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	# disable watchdog
+	mww 0xfffffd44 0x00008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=60)
+	mww 0xffffff60 0x003c0100
+	sleep 100
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank       [      ]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7x512.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7x512.cfg
new file mode 100644
index 0000000..ccdcfa7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam7x512.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME sam7x512
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	# disable watchdog
+	mww 0xfffffd44 0x00008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=60)
+	mww 0xffffff60 0x003c0100
+	sleep 100
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank       [      ]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME.0 at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
+flash bank $_FLASHNAME.1 at91sam7 0 0 0 0 $_TARGETNAME 1 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9.cfg
new file mode 100644
index 0000000..bc90d37
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9
+######################################
+
+if { [info exists AT91_CHIPNAME] } {
+	set _CHIPNAME $AT91_CHIPNAME
+} else {
+	error "you must specify a chip name"
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x0792603f
+}
+
+reset_config trst_and_srst separate trst_push_pull srst_open_drain
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+adapter srst delay 300
+jtag_ntrst_delay 200
+
+adapter speed 3
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9260.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9260.cfg
new file mode 100644
index 0000000..3f74d96
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9260.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9260
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9260
+}
+
+source [find target/at91sam9.cfg]
+
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9260 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
+# Both areas are 4 kB long.
+
+#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x1000 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg
new file mode 100644
index 0000000..47117e9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9260
+######################################
+
+source [find target/at91sam9261.cfg]
+
+reset_config trst_and_srst
+
+adapter speed 4
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+scan_chain
+$_TARGETNAME configure -event reset-start {
+	# at reset chip runs at 32khz
+	adapter speed 8
+}
+
+$_TARGETNAME configure -event reset-init {at91sam_init}
+
+# Flash configuration
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
+
+# Faster memory downloads. This is disabled automatically during
+# reset init since all reset init sequences are too short for
+# fast memory access
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+proc at91sam_init { } {
+	mww 0xfffffd08 0xa5000501         ;# RSTC_MR : enable user reset
+	mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+	sleep 20                          ;# wait 20 ms
+	mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+	sleep 10                          ;# wait 10 ms
+	mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
+	sleep 20                          ;# wait 20 ms
+	mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler
+	sleep 10                          ;# wait 10 ms
+	mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected
+	sleep 10                          ;# wait 10 ms
+
+	# Now run at anything fast... ie: 10mhz!
+	adapter speed 10000               ;# Increase JTAG Speed to 6 MHz
+
+	mww 0xffffec00 0x0a0a0a0a         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+	mww 0xffffec04 0x0b0b0b0b         ;# SMC_PULSE0
+	mww 0xffffec08 0x00160016         ;# SMC_CYCLE0
+	mww 0xffffec0c 0x00161003         ;# SMC_MODE0
+
+	mww 0xfffff870 0xffff0000         ;# PIO_ASR : Select peripheral function for D15..D31
+	mww 0xfffff804 0xffff0000         ;# PIO_PDR : Disable PIO function for D15..D31
+
+	mww 0xffffef1c 0x2                ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+	#mww 0xffffea08 0x85227254         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x5d2              ;# SDRAMC_TR : Set refresh timer count to 15us
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9261.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9261.cfg
new file mode 100644
index 0000000..07456b2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9261.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9261
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9261
+}
+
+source [find target/at91sam9.cfg]
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x28000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9263.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9263.cfg
new file mode 100644
index 0000000..3e2585c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9263.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9263
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9263
+}
+
+source [find target/at91sam9.cfg]
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9263 has two SRAM areas,
+# one starting at 0x00300000 of 80KiB
+# and the other  starting at 0x00500000 of 16KiB.
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x14000 -work-area-backup 1
+#$_TARGETNAME configure -work-area-phys 0x00500000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9g10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9g10.cfg
new file mode 100644
index 0000000..6836773
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9g10.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9G10
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9g10
+}
+
+source [find target/at91sam9.cfg]
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9G10 has one SRAM area at 0x00300000 of 16KiB
+
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9g20.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9g20.cfg
new file mode 100644
index 0000000..4fc2048
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9g20.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9G20
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9g20
+}
+
+source [find target/at91sam9.cfg]
+
+# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
+
+adapter speed 5
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
+# Both areas are 16 kB long.
+
+#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9g45.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9g45.cfg
new file mode 100644
index 0000000..5e6e818
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9g45.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9G45
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9g45
+}
+
+source [find target/at91sam9.cfg]
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9G45 has one SRAM area starting at 0x00300000 of 64 KiB.
+
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x200000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9rl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9rl.cfg
new file mode 100644
index 0000000..b253427
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sam9rl.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9RL
+######################################
+
+if { [info exists CHIPNAME] } {
+   set AT91_CHIPNAME $CHIPNAME
+} else {
+   set AT91_CHIPNAME at91sam9rl
+}
+
+source [find target/at91sam9.cfg]
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x10000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sama5d2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sama5d2.cfg
new file mode 100644
index 0000000..30ddc92
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91sama5d2.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# SAMA5D2 devices support both JTAG and SWD transports.
+#
+# The JTAG connection is disabled at reset, and during the ROM Code execution.
+# It is re-enabled when the ROM code jumps in the boot file copied from an
+# external Flash memory into the internalSRAM, or when the ROM code launches
+# the SAM-BA monitor, when no boot file has been found in any external Flash
+# memory.
+# For more JTAG related information see, :
+# https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-sheet-ds60001476G.pdf
+#
+# If JTAGSEL pin:
+# - if enabled, boundary Scan mode is activated. JTAG ID Code value is 0x05B3F03F.
+# - if disabled, ICE mode is activated. Debug Port JTAG IDCODE value is 0x5BA00477
+#
+
+source [find target/swj-dp.tcl]
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x5ba00477
+	} else {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x5ba02477
+	}
+}
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME at91sama5d2
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Cortex-A5 target
+set _TARGETNAME $_CHIPNAME.cpu_a5
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91samdXX.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91samdXX.cfg
new file mode 100644
index 0000000..5132109
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91samdXX.cfg
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip
+#
+
+#
+# samdXX devices only support SWD transports.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91samd
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# SAMD DSU will hold the CPU in reset if TCK is low when RESET_N
+# deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2)
+#
+# dsu_reset_deassert configures whether we want to run or halt out of reset,
+# then instruct the DSU to let us out of reset.
+$_TARGETNAME configure -event reset-deassert-post {
+        at91samd dsu_reset_deassert
+}
+
+# SRST (wired to RESET_N) resets debug circuitry
+# srst_pulls_trst is not configured here to avoid an error raised in reset halt
+reset_config srst_gates_jtag
+
+# Do not use a reset button with other SWD adapter than Atmel's EDBG.
+# DSU usually locks MCU in reset state until you issue a reset command
+# in OpenOCD.
+
+# SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset.
+# Other members of family usually use SYSCLK = 4 MHz after reset.
+# Datasheet does not specify SYSCLK to SWD clock ratio.
+# Usually used SYSCLK/6 is slow, testing shows that debugging can
+# work @ SYSCLK/2 but your mileage may vary.
+# This limit is most probably imposed by incorrectly handled SWD WAIT
+# on some SWD adapters.
+
+adapter speed 400
+
+# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
+# without problem at maximal clock speed. Atmel recommends
+# adapter speed less than 10 * CPU clock.
+# adapter speed 5000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91samg5x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91samg5x.cfg
new file mode 100644
index 0000000..cbe25f6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/at91samg5x.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for the ATMEL samg5x Cortex-M4F chip family
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar2313.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar2313.cfg
new file mode 100644
index 0000000..aa962b4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar2313.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar2313
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x00000001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar2315.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar2315.cfg
new file mode 100644
index 0000000..3836763
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar2315.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar2315
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x00000001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar9331.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar9331.cfg
new file mode 100644
index 0000000..931ac10
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar9331.cfg
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Atheros AR9331 is a highly integrated and cost effective
+# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless
+# local area network (WLAN) AP and router platforms.
+#
+# Notes:
+# - MIPS Processor ID (PRId): 0x00019374
+# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
+#   operating at up to 400 MHz
+# - External 16-bit DDR1, DDR2, or SDRAM memory interface
+# - TRST is not available.
+# - EJTAG PrRst signal is not supported
+# - RESET_L pin A72 on the SoC will reset internal JTAG logic.
+#
+
+# Pins related for debug and bootstrap:
+# Name		Pin		Description
+#   JTAG
+# JTAG_TCK	GPIO0, (A27)	Software configurable, default JTAG
+# JTAG_TDI	GPIO6, (B46)	Software configurable, default JTAG
+# JTAG_TDO	GPIO7, (A54)	Software configurable, default JTAG
+# JTAG_TMS	GPIO8, (A52)	Software configurable, default JTAG
+#   Reset
+# RESET_L	-, (A72)	Input only
+# SYS_RST_L	????????	Output reset request or GPIO
+#   Bootstrap
+# MEM_TYPE[1]	GPIO28, (A74)	0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM
+# MEM_TYPE[0]	GPIO12, (A56)
+# FW_DOWNLOAD	GPIO16, (A75)	Used if BOOT_FROM_SPI = 0. 0 - boot from USB
+#                               1 - boot from MDIO.
+# JTAG_MODE(JS)	GPIO11, (B48)	0 - JTAG (Default); 1 - EJTAG
+# BOOT_FROM_SPI	GPIO1, (A77)	0 - ROM boot; 1 - SPI boot
+# SEL_25M_40M	GPIO0, (A78)	0 - 25MHz; 1 - 40MHz
+#   UART
+# UART0_SOUT	GPIO10, (A79)
+# UART0_SIN	GPIO9, (B68)
+
+# Per default we need to use "none" variant to be able properly "reset init"
+# or "reset halt" the CPU.
+reset_config none srst_pulls_trst
+
+# For SRST based variant we still need proper timings.
+# For ETH part the reset should be asserted at least for 10ms
+# Since there is no other information let's take 100ms to be sure.
+adapter srst pulse_width 100
+
+# according to the SoC documentation it should take at least 5ms from
+# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
+# to live.
+adapter srst delay 8
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar9331
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+# provide watchdog helper.
+proc disable_watchdog { } {
+	mww 0xb8060008 0x0
+}
+
+$_TARGETNAME configure -event halted { disable_watchdog }
+
+# Since PrRst is not supported and SRST will reset complete chip
+# with JTAG engine, we need to reset CPU from CPU itself.
+$_TARGETNAME configure -event reset-assert-pre {
+	halt
+}
+
+$_TARGETNAME configure -event reset-assert {
+	catch "mww 0xb806001C 0x01000000"
+}
+
+# To be able to trigger complete chip reset, in case JTAG is blocked
+# or CPU not responding, we still can use this helper.
+proc full_reset { } {
+	reset_config srst_only
+	reset
+	halt
+	reset_config none
+}
+
+proc disable_watchdog { } {
+	;# disable watchdog
+	mww 0xb8060008 0x0
+}
+
+$_TARGETNAME configure -event reset-end { disable_watchdog }
+
+# Section with helpers which can be used by boards
+proc ar9331_25mhz_pll_init {} {
+	mww 0xb8050008 0x00018004	;# bypass PLL; AHB_POST_DIV - ratio 4
+	mww 0xb8050004 0x00000352	;# 34000(ns)/40ns(25MHz) = 0x352 (850)
+	mww 0xb8050000 0x40818000	;# Power down control for CPU PLL
+					;# OUTDIV | REFDIV | DIV_INT
+	mww 0xb8050010 0x001003e8	;# CPU PLL Dither FRAC Register
+					;# (disabled?)
+	mww 0xb8050000 0x00818000	;# Power on | OUTDIV | REFDIV | DIV_INT
+	mww 0xb8050008 0x00008000	;# remove bypass;
+					;# AHB_POST_DIV - ratio 2
+}
+
+proc ar9331_ddr1_init {} {
+	mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
+	mww 0xb8000004 0x9dd0e6a8	;# DDR_CONFIG2 - more DRAM confs
+
+	mww 0xb8000010 0x8	;# Forces a PRECHARGE ALL cycle
+	mww 0xb8000008 0x133	;# mode reg: 0x133 - default
+	mww 0xb8000010 0x1	;# Forces an MRS update cycl
+	mww 0xb800000c 0x2	;# Extended mode register value.
+				;# default 0x2 - Reset to weak driver, DLL on
+	mww 0xb8000010 0x2	;# Forces an EMRS update cycle
+	mww 0xb8000010 0x8	;# Forces a PRECHARGE ALL cycle
+	mww 0xb8000008 0x33	;# mode reg: remove some bit?
+	mww 0xb8000010 0x1	;# Forces an MRS update cycl
+	mww 0xb8000014 0x4186	;# enable refres: bit(14) - set refresh rate
+	mww 0xb800001c 0x8	;# This register is used along with DQ Lane 0,
+				;# DQ[7:0], DQS_0
+	mww 0xb8000020 0x9	;# This register is used along with DQ Lane 1,
+				;# DQ[15:8], DQS_1.
+	mww 0xb8000018 0xff	;# DDR read and capture bit mask.
+				;# Each bit represents a cycle of valid data.
+}
+
+proc ar9331_ddr2_init {} {
+	mww 0xb8000000 0x7fbc8cd0	;# DDR_CONFIG - lots of DRAM confs
+	mww 0xb8000004 0x9dd0e6a8	;# DDR_CONFIG2 - more DRAM confs
+
+	mww 0xb800008c 0x00000a59
+	mww 0xb8000010 0x00000008	;# PRECHARGE ALL cycle
+
+	mww 0xb8000090 0x00000000
+	mww 0xb8000010 0x00000010	;# EMR2S update cycle
+
+	mww 0xb8000094 0x00000000
+	mww 0xb8000010 0x00000020	;# EMR3S update cycle
+
+	mww 0xb800000c 0x00000000
+	mww 0xb8000010 0x00000002	;# EMRS update cycle
+
+	mww 0xb8000008 0x00000100
+	mww 0xb8000010 0x00000001	;# MRS update cycle
+
+	mww 0xb8000010 0x00000008	;# PRECHARGE ALL cycle
+
+	mww 0xb8000010 0x00000004
+	mww 0xb8000010 0x00000004	;# AUTO REFRESH cycle
+
+	mww 0xb8000008 0x00000a33
+	mww 0xb8000010 0x00000001	;# MRS update cycle
+
+	mww 0xb800000c 0x00000382
+	mww 0xb8000010 0x00000002	;# EMRS update cycle
+
+	mww 0xb800000c 0x00000402
+	mww 0xb8000010 0x00000002	;# EMRS update cycle
+
+	mww 0xb8000014 0x00004186	;# DDR_REFRESH
+	mww 0xb800001c 0x00000008	;# DDR_TAP_CTRL0
+	mww 0xb8000020 0x00000009	;# DDR_TAP_CTRL1
+
+	;# DDR read and capture bit mask.
+	;# Each bit represents a cycle of valid data.
+	;# 0xff: use 16-bit DDR
+	mww 0xb8000018 0x000000ff
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar9344.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar9344.cfg
new file mode 100644
index 0000000..d22bb5f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atheros_ar9344.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar9344
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x00000001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+proc test_ar9344_uart0_tx {} {
+	echo "configuring uart0.."
+	mww 0xb802000c 0x87
+	mww 0xb8020000 0x15
+	mww 0xb8020004 0
+	mww 0xb802000c 7
+	mww 0xb8020004 0
+
+	echo "send message: hallo world"
+	mww 0xb8020000 0x68
+	mww 0xb8020000 0x65
+	mww 0xb8020000 0x6c
+	mww 0xb8020000 0x6c
+	mww 0xb8020000 0x6f
+	mww 0xb8020000 0x20
+	mww 0xb8020000 0x77
+	mww 0xb8020000 0x6f
+	mww 0xb8020000 0x72
+	mww 0xb8020000 0x6c
+	mww 0xb8020000 0x64
+	mww 0xb8020000 0x0a
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atmega128.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atmega128.cfg
new file mode 100644
index 0000000..c946919
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atmega128.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# for avr
+
+   set _CHIPNAME avr
+   set _ENDIAN little
+
+# jtag speed
+adapter speed 4500
+
+reset_config srst_only
+adapter srst delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x8970203F
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
+
+#to use it, script will be like:
+#init
+#adapter speed 4500
+#reset init
+#verify_ircapture disable
+#
+#halt
+#wait halt
+#poll
+#avr mass_erase 0
+#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
+#reset run
+#shutdown
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atmega128rfa1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atmega128rfa1.cfg
new file mode 100644
index 0000000..96a83fe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atmega128rfa1.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME avr
+set _ENDIAN little
+
+# jtag speed
+adapter speed 4500
+
+# avr jtag docs never connect RSTN
+reset_config none
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0a70103f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atmega32u4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atmega32u4.cfg
new file mode 100644
index 0000000..9199c74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atmega32u4.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ATmega32U4
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME avr
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4958703f
+}
+
+adapter speed 4500
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atsame5x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atsame5x.cfg
new file mode 100644
index 0000000..5093d41
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atsame5x.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Microchip (former Atmel) SAM E54, E53, E51 and D51 devices
+# with a Cortex-M4 core
+#
+
+#
+# Devices only support SWD transports.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME atsame5
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 32kB (the smallest RAM size is 128kB)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# SAM DSU will hold the CPU in reset if TCK is low when RESET_N
+# deasserts
+#
+# dsu_reset_deassert configures whether we want to run or halt out of reset,
+# then instruct the DSU to let us out of reset.
+$_TARGETNAME configure -event reset-deassert-post {
+        atsame5 dsu_reset_deassert
+}
+
+# SRST (wired to RESET_N) resets debug circuitry
+# srst_pulls_trst is not configured here to avoid an error raised in reset halt
+reset_config srst_gates_jtag
+
+# Do not use a reset button with other SWD adapter than Atmel's EDBG.
+# DSU usually locks MCU in reset state until you issue a reset command
+# in OpenOCD.
+
+# SAM E5x/D51 runs at SYSCLK = 48 MHz from RC oscillator after reset.
+# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
+# without problem at clock speed over 5000 khz. Atmel recommends
+# adapter speed less than 10 * CPU clock.
+adapter speed 2000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atsaml1x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atsaml1x.cfg
new file mode 100644
index 0000000..5a1b8f8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atsaml1x.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Microchip (formerly Atmel) SAM L1x target
+#
+# Note: These devices support SWD only.
+#
+
+transport select swd
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME saml1x
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+swd newdap $_CHIPNAME cpu -expected-id 0x0bf11477
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if {![using_hla]} {
+    cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atsamv.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atsamv.cfg
new file mode 100644
index 0000000..7e9f6c5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/atsamv.cfg
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts
+# The chips are very similar; the SAMV series just has
+# more peripherals and seems like the "flagship" of the
+# family. This script will work for all of them.
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME samv
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bd11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+adapter speed 1800
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/avr32.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/avr32.cfg
new file mode 100644
index 0000000..e16d114
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/avr32.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME avr32
+set _ENDIAN big
+
+set _CPUTAPID 0x21e8203f
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+reset_config trst_and_srst separate
+
+# jtag scan chain
+# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2711.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2711.cfg
new file mode 100644
index 0000000..f8d2b3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2711.cfg
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Broadcom BCM2711 used in Raspberry Pi 4
+# No documentation was found on Broadcom website
+
+# Partial information is available in raspberry pi website:
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm2711
+}
+
+if { [info exists CHIPCORES] } {
+	set _cores $CHIPCORES
+} else {
+	set _cores 4
+}
+
+if { [info exists USE_SMP] } {
+	set _USE_SMP $USE_SMP
+} else {
+	set _USE_SMP 0
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
+adapter speed 4000
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# MEM-AP for direct access
+target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# these addresses are obtained from the ROM table via 'dap info 0' command
+set _DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+	set _CTINAME $_CHIPNAME.cti$_core
+	set _TARGETNAME $_CHIPNAME.cpu$_core
+
+	cti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 0 -baseaddr [lindex $_CTIBASE $_core]
+	target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME
+
+	set _smp_command "$_smp_command $_TARGETNAME"
+}
+
+if {$_USE_SMP} {
+	eval $_smp_command
+}
+
+# default target is cpu0
+targets $_CHIPNAME.cpu0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm281xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm281xx.cfg
new file mode 100644
index 0000000..a70a9c5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm281xx.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BCM281xx
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm281xx
+}
+
+
+# Main CPU DAP
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
+
+
+# Dual Cortex-A9
+set _TARGETNAME0 $_CHIPNAME.cpu0
+set _TARGETNAME1 $_CHIPNAME.cpu1
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000
+target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000
+target smp $_TARGETNAME0 $_TARGETNAME1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2835.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2835.cfg
new file mode 100644
index 0000000..32a0366
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2835.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the Broadcom chip used in the Raspberry Pi Model A, B, B+,
+# the Compute Module, and the Raspberry Pi Zero.
+
+# Partial information is available in raspberry pi website:
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm2835
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x07b7617F
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 5
+adapter speed 4000
+
+target create $_CHIPNAME.cpu0 arm11 -chain-position $_CHIPNAME.cpu
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2836.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2836.cfg
new file mode 100644
index 0000000..0492131
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2836.cfg
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Broadcom chip used in the Raspberry Pi 2 Model B
+
+# Partial information is available in raspberry pi website:
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm2836
+}
+
+if { [info exists CHIPCORES] } {
+	set _cores $CHIPCORES
+} else {
+	set _cores 4
+}
+
+if { [info exists USE_SMP] } {
+	set _USE_SMP $USE_SMP
+} else {
+	set _USE_SMP 0
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
+adapter speed 4000
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# MEM-AP for direct access
+target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# these addresses are obtained from the ROM table via 'dap info 0' command
+set _DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000}
+
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+	set _TARGETNAME $_CHIPNAME.cpu$_core
+
+	target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -coreid $_core -dbgbase [lindex $_DBGBASE $_core]
+	$_TARGETNAME configure -event reset-assert-post { cortex_a dbginit }
+
+	set _smp_command "$_smp_command $_CHIPNAME.cpu$_core"
+}
+
+if {$_USE_SMP} {
+	eval $_smp_command
+}
+
+# default target is cpu0
+targets $_CHIPNAME.cpu0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2837.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2837.cfg
new file mode 100644
index 0000000..749de31
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm2837.cfg
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the Broadcom chip used in the Raspberry Pi 3,
+# and in later models of the Raspberry Pi 2.
+
+# Partial information is available in raspberry pi website:
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837b0
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm2837
+}
+
+if { [info exists CHIPCORES] } {
+	set _cores $CHIPCORES
+} else {
+	set _cores 4
+}
+
+if { [info exists USE_SMP] } {
+	set _USE_SMP $USE_SMP
+} else {
+	set _USE_SMP 0
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
+adapter speed 4000
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# MEM-AP for direct access
+target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# these addresses are obtained from the ROM table via 'dap info 0' command
+set _DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000}
+set _CTIBASE {0x80018000 0x80019000 0x8001a000 0x8001b000}
+
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+	set _CTINAME $_CHIPNAME.cti$_core
+	set _TARGETNAME $_CHIPNAME.cpu$_core
+
+	cti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 0 -baseaddr [lindex $_CTIBASE $_core]
+	target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME
+	$_TARGETNAME configure -event reset-assert-post { aarch64  dbginit }
+
+	set _smp_command "$_smp_command $_TARGETNAME"
+}
+
+if {$_USE_SMP} {
+	eval $_smp_command
+}
+
+# default target is cpu0
+targets $_CHIPNAME.cpu0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm4706.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm4706.cfg
new file mode 100644
index 0000000..e5d8d19
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm4706.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME bcm4706
+set _CPUID 0x1008c17f
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm4718.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm4718.cfg
new file mode 100644
index 0000000..cc21a5e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm4718.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME bcm4718
+set _LVTAPID 0x1471617f
+set _CPUID 0x0008c17f
+
+source [find target/bcm47xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm47xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm47xx.cfg
new file mode 100644
index 0000000..b5365e0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm47xx.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed"
+reset_config none
+
+jtag newtap $_CHIPNAME-lv tap -irlen 32 -ircapture 0x1 -irmask 0x1f -expected-id $_LVTAPID -expected-id $_CPUID
+jtag configure $_CHIPNAME-lv.tap -event setup "jtag tapenable $_CHIPNAME.cpu"
+jtag configure $_CHIPNAME-lv.tap -event tap-disable {}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "switch_lv_to_ejtag"
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
+
+proc switch_lv_to_ejtag {} {
+    global _CHIPNAME
+    poll 0
+    irscan $_CHIPNAME-lv.tap 0x143ff3a
+    drscan $_CHIPNAME-lv.tap 32 1
+    jtag tapdisable $_CHIPNAME-lv.tap
+    poll 1
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm5352e.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm5352e.cfg
new file mode 100644
index 0000000..084ce04
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm5352e.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME bcm5352e
+set _CPUID 0x0535217f
+
+jtag newtap $_CHIPNAME cpu -irlen 8 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm6348.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm6348.cfg
new file mode 100644
index 0000000..b9d4448
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bcm6348.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME bcm6348
+set _CPUID 0x0634817f
+
+adapter speed 1000
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bl702.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bl702.cfg
new file mode 100644
index 0000000..5046cd1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bl702.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Bouffalo Labs BL702, BL704 and BL706 target
+#
+# https://en.bouffalolab.com/product/?type=detail&id=8
+#
+# Default JTAG pins: (if not changed by eFuse configuration)
+# TMS - GPIO0
+# TDI - GPIO1
+# TCK - GPIO2
+# TDO - GPIO9
+#
+
+source [find mem_helper.tcl]
+
+transport select jtag
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME bl702
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_mem_access sysbus
+
+$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1
+
+# Internal RC ticks on 32 MHz, so this speed should be safe to use.
+adapter speed 4000
+
+# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
+# CTRL_PWRON_RESET triggers full "power-on like" reset.
+# This means that pinmux configuration to access JTAG is reset as well, and configured back early
+# in BootROM.
+$_TARGETNAME configure -event reset-assert-pre {
+	halt
+
+	# Switch clock to internal RC32M
+	# In HBN_GLB, set ROOT_CLK_SEL = 0
+	mmw 0x4000f030 0x0 0x00000003
+	# Wait for clock switch
+	sleep 10
+
+	# GLB_REG_BCLK_DIS_FALSE
+	mww 0x40000ffc 0x0
+
+	# HCLK is RC32M, so BCLK/HCLK doesn't need divider
+	# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
+	mmw 0x40000000 0x0 0x00FFFF00
+	# Wait for clock to stabilize
+	sleep 10
+
+	# Do reset
+	# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
+	mmw 0x40000018 0x0 0x00000007
+
+	# Since this full software reset resets GPIO pinmux as well, we will lose access
+	# to JTAG right away after writing to register. This chip doesn't support abstract
+	# memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
+	# if write was successful or not, and will print error about that. Since receiving of
+	# this error is expected, we will turn off log printing for a moment,
+	set lvl [lindex [debug_level] 1]
+	debug_level -1
+	# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
+	catch {mmw 0x40000018 0x7 0x0}
+	debug_level $lvl
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bluefield.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bluefield.cfg
new file mode 100644
index 0000000..30ed527
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bluefield.cfg
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BlueField SoC Target
+
+set _CHIPNAME bluefield
+
+# Specify the target device
+#rshim device /dev/rshim0/rshim
+
+# Main DAP
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4ba00477
+}
+
+adapter speed 1500
+
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Initialize the target name and command variable.
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+# CTI relative address
+set $_TARGETNAME.cti(0) 0xC4020000
+set $_TARGETNAME.cti(1) 0xC4120000
+set $_TARGETNAME.cti(2) 0xC8020000
+set $_TARGETNAME.cti(3) 0xC8120000
+set $_TARGETNAME.cti(4) 0xCC020000
+set $_TARGETNAME.cti(5) 0xCC120000
+set $_TARGETNAME.cti(6) 0xD0020000
+set $_TARGETNAME.cti(7) 0xD0120000
+set $_TARGETNAME.cti(8) 0xD4020000
+set $_TARGETNAME.cti(9) 0xD4120000
+set $_TARGETNAME.cti(10) 0xD8020000
+set $_TARGETNAME.cti(11) 0xD8120000
+set $_TARGETNAME.cti(12) 0xDC020000
+set $_TARGETNAME.cti(13) 0xDC120000
+set $_TARGETNAME.cti(14) 0xE0020000
+set $_TARGETNAME.cti(15) 0xE0120000
+
+# Create debug targets for a number of cores starting from core '_core_start'.
+# Adjust the numbers according to board configuration.
+set _core_start 0
+set _cores 16
+
+# Create each core
+for { set _core $_core_start } { $_core < $_core_start + $_cores } { incr _core 1 } {
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
+
+    if { $_core != $_core_start } {
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+# Configure SMP
+if { $_cores > 1 } {
+    eval $_smp_command
+}
+
+# Make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# Examine remaining cores
+	foreach _core $args {
+		${_TARGETNAME}$_core arp_examine
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bluenrg-x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bluenrg-x.cfg
new file mode 100644
index 0000000..afa1b51
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/bluenrg-x.cfg
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# bluenrg-1/2 and bluenrg-lp devices support only SWD transports.
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME bluenrg-1
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 24kB-256bytes
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x5F00
+}
+
+adapter speed 4000
+
+swj_newdap $_CHIPNAME cpu -expected-id 0x0bb11477 -expected-id 0x0bc11477
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+set WDOG_VALUE 0
+set WDOG_VALUE_SET 0
+
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000100 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
+
+# In BlueNRG-X reset pin is actually a shutdown (power-off), so define reset as none
+reset_config none
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+set JTAG_IDCODE_B2 0x0200A041
+set JTAG_IDCODE_B1 0x0
+
+$_TARGETNAME configure -event halted {
+    global WDOG_VALUE
+    global WDOG_VALUE_SET
+    set _JTAG_IDCODE [mrw 0x40000004]
+    if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
+        # Stop watchdog during halt, if enabled. Only Bluenrg-1/2
+        set WDOG_VALUE [mrw 0x40700008]
+        if [expr {$WDOG_VALUE & (1 << 1)}] {
+            set WDOG_VALUE_SET 1
+            mww 0x40700008 [expr {$WDOG_VALUE & 0xFFFFFFFD}]
+        }
+    }
+}
+$_TARGETNAME configure -event resumed {
+    global WDOG_VALUE
+    global WDOG_VALUE_SET
+    set _JTAG_IDCODE [mrw 0x40000004]
+    if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
+        if {$WDOG_VALUE_SET} {
+            # Restore watchdog enable value after resume. Only Bluenrg-1/2
+            mww 0x40700008 $WDOG_VALUE
+            set WDOG_VALUE_SET 0
+           }
+   }
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100.cfg
new file mode 100644
index 0000000..c268ba3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# c100 config.
+# This is ARM1136 dual core
+# this script only configures one core (that is used to run Linux)
+
+# assume no PLL lock, start slowly
+adapter speed 100
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME c100
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x27b3645b
+}
+
+if { [info exists DSPTAPID] } {
+   set _DSPTAPID $DSPTAPID
+} else {
+   set _DSPTAPID 0x27b3645b
+}
+
+jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_DSPTAPID
+
+
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# C100's ARAM 64k SRAM
+$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100config.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100config.tcl
new file mode 100644
index 0000000..2545fa7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100config.tcl
@@ -0,0 +1,413 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# board(-config) specific parameters file.
+
+# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
+proc config {label} {
+    return [dict get [configC100] $label ]
+}
+
+# show the value for the param. with label
+proc showconfig {label} {
+    echo [format "0x%x" [dict get [configC100] $label ]]
+}
+
+# Telo board config
+# when there are more then one board config
+# use soft links to c100board-config.tcl
+# so that only the right board-config gets
+# included (just like include/configs/board-configs.h
+# in u-boot.
+proc configC100 {} {
+    # xtal freq. 24MHz
+    dict set configC100 CFG_REFCLKFREQ	         24000000
+
+    # Amba Clk 165MHz
+    dict set configC100 CONFIG_SYS_HZ_CLOCK      165000000
+    dict set configC100 w_amba 1
+    dict set configC100 x_amba 1
+    # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
+    dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
+
+    # Arm Clk 450MHz, must be a multiple of 25 MHz
+    dict set configC100 CFG_ARM_CLOCK      450000000
+    dict set configC100 w_arm 0
+    dict set configC100 x_arm 1
+    # y = arm_clk * (w+1)*(x+1)*2/xtal_clk
+    dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
+
+
+}
+
+# This should be called for reset init event handler
+proc setupTelo {} {
+
+    # setup GPIO used as control signals for C100
+    setupGPIO
+    # This will allow access to lower 8MB or NOR
+    lowGPIO5
+    # setup NOR size,timing,etc.
+    setupNOR
+    # setup internals + PLL + DDR2
+    initC100
+}
+
+
+proc setupNOR {} {
+    echo "Setting up NOR: 16MB, 16-bit wide bus, CS0"
+    # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
+    set EX_CSEN_REG	    [regs EX_CSEN_REG ]
+    set EX_CS0_SEG_REG	    [regs EX_CS0_SEG_REG ]
+    set EX_CS0_CFG_REG	    [regs EX_CS0_CFG_REG ]
+    set EX_CS0_TMG1_REG	    [regs EX_CS0_TMG1_REG ]
+    set EX_CS0_TMG2_REG	    [regs EX_CS0_TMG2_REG ]
+    set EX_CS0_TMG3_REG	    [regs EX_CS0_TMG3_REG ]
+    set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
+    set EX_MFSM_REG	    [regs EX_MFSM_REG ]
+    set EX_CSFSM_REG	    [regs EX_CSFSM_REG ]
+    set EX_WRFSM_REG	    [regs EX_WRFSM_REG ]
+    set EX_RDFSM_REG	    [regs EX_RDFSM_REG ]
+
+    # enable Expansion Bus Clock + CS0 (NOR)
+    mww $EX_CSEN_REG 0x3
+    # set the address space for CS0=16MB
+    mww $EX_CS0_SEG_REG 0x7ff
+    # set the CS0 bus width to 16-bit
+    mww $EX_CS0_CFG_REG 0x202
+    # set timings to NOR
+    mww $EX_CS0_TMG1_REG 0x03034006
+    mww $EX_CS0_TMG2_REG 0x04040002
+    #mww $EX_CS0_TMG3_REG
+    # set EBUS clock 165/5=33MHz
+    mww $EX_CLOCK_DIV_REG 0x5
+    # everything else is OK with default
+}
+
+proc bootNOR {} {
+    set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
+    set BLOCK_RESET_REG	       [regs BLOCK_RESET_REG]
+    set DDR_RST		       [regs DDR_RST]
+
+    # put DDR controller in reset (so that it comes reset in u-boot)
+    mmw $BLOCK_RESET_REG 0x0 $DDR_RST
+    # setup CS0 controller for NOR
+    setupNOR
+    # make sure we are accessing the lower part of NOR
+    lowGPIO5
+    # set PC to start of NOR (at boot 0x20000000 = 0x0)
+    reg pc $EXP_CS0_BASEADDR
+    # run
+    resume
+}
+proc setupGPIO {} {
+    echo "Setting up GPIO block for Telo"
+    # This is current setup for Telo (see sch. for details):
+    #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
+    #GPIO1 irq line for FXS-FXO
+    #GPIO5 addr22 for NOR flash (access to upper 8MB)
+    #GPIO17 reset for DECT module.
+    #GPIO29 CS_n for NAND
+
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
+    set GPIO_OE_REG		    [regs GPIO_OE_REG]
+
+    # set GPIO29=GPIO17=1, GPIO5=0
+    mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}]
+    # enable [as output] GPIO29,GPIO17,GPIO5
+    mww $GPIO_OE_REG [expr  {1<<29 | 1<<17 | 1<<5}]
+}
+
+proc highGPIO5 {} {
+    echo "GPIO5 high"
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
+    # set GPIO5=1
+    mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0
+}
+
+proc lowGPIO5 {} {
+    echo "GPIO5 low"
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
+    # set GPIO5=0
+    mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}]
+}
+
+proc boardID {id} {
+    # so far built:
+    # 4'b1111
+    dict set boardID 15 name "EVT1"
+    dict set boardID 15 ddr2size 128M
+    # dict set boardID 15 nandsize 1G
+    # dict set boardID 15 norsize 16M
+    # 4'b0000
+    dict set boardID 0 name "EVT2"
+    dict set boardID 0 ddr2size 128M
+    # 4'b0001
+    dict set boardID 1 name "EVT3"
+    dict set boardID 1 ddr2size 256M
+    # 4'b1110
+    dict set boardID 14 name "EVT3_old"
+    dict set boardID 14 ddr2size 128M
+    # 4'b0010
+    dict set boardID 2 name "EVT4"
+    dict set boardID 2 ddr2size 256M
+
+    return $boardID
+}
+
+
+# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
+# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
+proc ooma_board_detect {} {
+    set GPIO_BOOTSTRAP_REG	[regs GPIO_BOOTSTRAP_REG]
+
+    # read the current value of the BOOTSTRAP pins
+    set tmp [mrw $GPIO_BOOTSTRAP_REG]
+    echo [format "GPIO_BOOTSTRAP_REG  (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
+    # extract the GPBP bits
+    set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}]
+
+    # display board ID
+    echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
+    # show it on serial console
+    putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
+    # return the ddr2 size, used to configure DDR2 on a given board.
+    return [dict get [boardID $gpbt] $gpbt ddr2size]
+}
+
+proc configureDDR2regs_256M {} {
+
+    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
+    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
+    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
+    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
+    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
+    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
+    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
+    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
+    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
+    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
+    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
+    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
+    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
+    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
+    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
+    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
+    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
+    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
+    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
+    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
+    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
+
+    set DENALI_CTL_02_VAL 0x0100000000010100
+    set DENALI_CTL_11_VAL 0x433a32164a560a00
+
+    mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
+    # 01_DATA mod [40]=1, enable BA2
+    mw64bit $DENALI_CTL_01_DATA  0x0100010100000001
+    mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
+    mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
+    mw64bit $DENALI_CTL_04_DATA  0x0000010100000001
+    mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
+    mw64bit $DENALI_CTL_06_DATA  0x060a020200020202
+    mw64bit $DENALI_CTL_07_DATA  0x0000000300000206
+    mw64bit $DENALI_CTL_08_DATA  0x6400003f3f0a0209
+    mw64bit $DENALI_CTL_09_DATA  0x1a000000001a1a1a
+    mw64bit $DENALI_CTL_10_DATA  0x0120202020191a18
+    # 11_DATA mod [39-32]=16,more refresh
+    mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
+    mw64bit $DENALI_CTL_12_DATA  0x0000000000000800
+    mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
+    mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
+    mw64bit $DENALI_CTL_15_DATA  0x04f8000000000000
+    mw64bit $DENALI_CTL_16_DATA  0x000000002cca0000
+    mw64bit $DENALI_CTL_17_DATA  0x0000000000000000
+    mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
+    mw64bit $DENALI_CTL_19_DATA  0x00001300c8030600
+    mw64bit $DENALI_CTL_20_DATA  0x0000000081fe00c8
+
+    set wr_dqs_shift 0x40
+    # start DDRC
+    mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]
+    # wait int_status[2] (DRAM init complete)
+    echo -n "Waiting for DDR2 controller to init..."
+    set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+    while { [expr {$tmp & 0x040000}] == 0 } {
+	sleep 1
+	set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+    }
+    echo "done."
+
+    # do ddr2 training sequence
+    # TBD (for now, if you need it, run trainDDR command)
+}
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
+# The values are computed based on Mindspeed and Nanya datasheets
+proc configureDDR2regs_128M {} {
+
+    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
+    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
+    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
+    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
+    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
+    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
+    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
+    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
+    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
+    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
+    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
+    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
+    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
+    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
+    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
+    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
+    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
+    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
+    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
+    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
+    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
+
+
+    set DENALI_CTL_02_VAL 0x0100010000010100
+    set DENALI_CTL_11_VAL 0x433A42124A650A37
+    # set some default values
+    mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
+    mw64bit $DENALI_CTL_01_DATA  0x0100000100000101
+    mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
+    mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
+    mw64bit $DENALI_CTL_04_DATA  0x0201010100000201
+    mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
+    mw64bit $DENALI_CTL_06_DATA  0x050A020200020202
+    mw64bit $DENALI_CTL_07_DATA  0x000000030E0B0205
+    mw64bit $DENALI_CTL_08_DATA  0x6427003F3F0A0209
+    mw64bit $DENALI_CTL_09_DATA  0x1A00002F00001A00
+    mw64bit $DENALI_CTL_10_DATA  0x01202020201A1A1A
+    mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
+    mw64bit $DENALI_CTL_12_DATA  0x0000080000000800
+    mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
+    mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
+    mw64bit $DENALI_CTL_15_DATA  0x0508000000000000
+    mw64bit $DENALI_CTL_16_DATA  0x000020472D200000
+    mw64bit $DENALI_CTL_17_DATA  0x0000000008000000
+    mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
+    mw64bit $DENALI_CTL_19_DATA  0x00001400C8030604
+    mw64bit $DENALI_CTL_20_DATA  0x00000000823600C8
+
+    set wr_dqs_shift 0x40
+    # start DDRC
+    mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]
+    # wait int_status[2] (DRAM init complete)
+    echo -n "Waiting for DDR2 controller to init..."
+    set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+    while { [expr {$tmp & 0x040000}] == 0 } {
+	sleep 1
+	set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+    }
+    # This is not necessary
+    #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL  & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ]
+    echo "done."
+
+    # do ddr2 training sequence
+    # TBD (for now, if you need it, run trainDDR command)
+}
+
+
+
+proc setupUART0 {} {
+    # configure UART0 to 115200, 8N1
+    set GPIO_LOCK_REG      [regs GPIO_LOCK_REG]
+    set GPIO_IOCTRL_REG    [regs GPIO_IOCTRL_REG]
+    set GPIO_IOCTRL_VAL    [regs GPIO_IOCTRL_VAL]
+    set GPIO_IOCTRL_UART0  [regs GPIO_IOCTRL_UART0]
+    set UART0_LCR	            [regs UART0_LCR]
+    set LCR_DLAB		    [regs LCR_DLAB]
+    set UART0_DLL		    [regs UART0_DLL]
+    set UART0_DLH		    [regs UART0_DLH]
+    set UART0_IIR		    [regs UART0_IIR]
+    set UART0_IER		    [regs UART0_IER]
+    set LCR_ONE_STOP		    [regs LCR_ONE_STOP]
+    set LCR_CHAR_LEN_8		    [regs LCR_CHAR_LEN_8]
+    set FCR_XMITRES		    [regs FCR_XMITRES]
+    set FCR_RCVRRES		    [regs FCR_RCVRRES]
+    set FCR_FIFOEN		    [regs FCR_FIFOEN]
+    set IER_UUE			    [regs IER_UUE]
+
+    # unlock writing to IOCTRL register
+    mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
+    # enable UART0
+    mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
+    # baudrate  115200
+    # This should really be amba_clk/(16*115200) but amba_clk=165MHz
+    set tmp 89
+    # Enable Divisor Latch access
+    mmw  $UART0_LCR $LCR_DLAB 0x0
+    # set the divisor to $tmp
+    mww $UART0_DLL [expr {$tmp & 0xff}]
+    mww $UART0_DLH [expr {$tmp >> 8}]
+    # Disable Divisor Latch access
+    mmw  $UART0_LCR 0x0 $LCR_DLAB
+    # set the UART to 8N1
+    mmw  $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0
+    # reset FIFO
+    mmw  $UART0_IIR [expr {$FCR_XMITRES  | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0
+    #  enable FFUART
+    mww $UART0_IER $IER_UUE
+}
+
+proc putcUART0 {char} {
+
+    set UART0_LSR	    [regs UART0_LSR]
+    set UART0_THR	    [regs UART0_THR]
+    set LSR_TEMT	    [regs LSR_TEMT]
+
+    # convert the 'char' to digit
+    set tmp [ scan $char %c ]
+    # /* wait for room in the tx FIFO on FFUART */
+    while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 }
+    mww $UART0_THR $tmp
+    if { $char == "\n" } { putcUART0 \r }
+}
+
+proc putsUART0 {str} {
+    set index 0
+    set len [string length $str]
+    while { $index < $len } {
+	putcUART0 [string index $str $index]
+	set index [expr {$index + 1}]
+    }
+}
+
+
+proc trainDDR2 {} {
+    set ARAM_BASEADDR	[regs ARAM_BASEADDR]
+
+    # you must have run 'reset init' or u-boot
+    # load the training code to ARAM
+    load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
+    # set PC to start of NOR (at boot 0x20000000 = 0x0)
+    reg pc $ARAM_BASEADDR
+    # run
+    resume
+}
+
+proc flashUBOOT {file} {
+    # this will update uboot on NOR partition
+    set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
+
+    # setup CS0 controller for NOR
+    setupNOR
+    # make sure we are accessing the lower part of NOR
+    lowGPIO5
+    flash probe 0
+    echo "Erasing sectors 0-3 for uboot"
+    putsUART0 "Erasing sectors 0-3 for uboot\n"
+    flash erase_sector 0 0 3
+    echo "Programming u-boot"
+    putsUART0 "Programming u-boot..."
+    arm11 memwrite burst enable
+    flash write_image $file $EXP_CS0_BASEADDR
+    arm11 memwrite burst disable
+    putsUART0 "done.\n"
+    putsUART0 "Rebooting, please wait!\n"
+    reboot
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100helper.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100helper.tcl
new file mode 100644
index 0000000..ba0e4fe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100helper.tcl
@@ -0,0 +1,505 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc helpC100 {} {
+    echo "List of useful functions for C100 processor:"
+    echo "1)  reset init:        will set up your Telo board"
+    echo "2)  setupNOR:          will setup NOR access"
+    echo "3)  showNOR:           will show current NOR config registers for 16-bit, 16MB NOR"
+    echo "4)  setupGPIO:         will setup GPIOs for Telo board"
+    echo "5)  showGPIO:          will show current GPIO config registers"
+    echo "6)  highGPIO5:         will set GPIO5=NOR_addr22=1 to access upper 8MB"
+    echo "7)  lowGPIO5:          will set GPIO5=NOR_addr22=0 to access lower 8MB"
+    echo "8)  showAmbaClk:       will show current config registers for Amba Bus Clock"
+    echo "9)  setupAmbaClk:      will setup Amba Bus Clock=165MHz"
+    echo "10) showArmClk:        will show current config registers for Arm Bus Clock"
+    echo "11) setupArmClk:       will setup Amba Bus Clock=450MHz"
+    echo "12) ooma_board_detect: will show which version of Telo you have"
+    echo "13) setupDDR2:         will configure DDR2 controller, you must have PLLs configured"
+    echo "14) showDDR2:          will show DDR2 config registers"
+    echo "15) showWatchdog:      will show current register config for watchdog"
+    echo "16) reboot:            will trigger watchdog and reboot Telo (hw reset)"
+    echo "17) bootNOR:           will boot Telo from NOR"
+    echo "18) setupUART0:        will configure UART0 for 115200 8N1, PLLs have to be configured"
+    echo "19) putcUART0:         will print a character on UART0"
+    echo "20) putsUART0:         will print a string on UART0"
+    echo "21) trainDDR2:         will run DDR2 training program"
+    echo "22) flashUBOOT:        will program NOR sectors 0-3 with u-boot.bin"
+}
+
+source [find mem_helper.tcl]
+
+# read a 64-bit register (memory mapped)
+proc mr64bit {reg} {
+    return [read_memory $reg 32 2]
+}
+
+
+# write a 64-bit register (memory mapped)
+proc mw64bit {reg value} {
+    set high [expr {$value >> 32}]
+    set low  [expr {$value & 0xffffffff}]
+    #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
+    mww $reg $low
+    mww [expr {$reg+4}] $high
+}
+
+
+proc showNOR {} {
+    echo "This is the current NOR setup"
+    set EX_CSEN_REG	    [regs EX_CSEN_REG ]
+    set EX_CS0_SEG_REG	    [regs EX_CS0_SEG_REG ]
+    set EX_CS0_CFG_REG	    [regs EX_CS0_CFG_REG ]
+    set EX_CS0_TMG1_REG	    [regs EX_CS0_TMG1_REG ]
+    set EX_CS0_TMG2_REG	    [regs EX_CS0_TMG2_REG ]
+    set EX_CS0_TMG3_REG	    [regs EX_CS0_TMG3_REG ]
+    set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
+    set EX_MFSM_REG	    [regs EX_MFSM_REG ]
+    set EX_CSFSM_REG	    [regs EX_CSFSM_REG ]
+    set EX_WRFSM_REG	    [regs EX_WRFSM_REG ]
+    set EX_RDFSM_REG	    [regs EX_RDFSM_REG ]
+
+    echo [format "EX_CSEN_REG      (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
+    echo [format "EX_CS0_SEG_REG   (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
+    echo [format "EX_CS0_CFG_REG   (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
+    echo [format "EX_CS0_TMG1_REG  (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
+    echo [format "EX_CS0_TMG2_REG  (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
+    echo [format "EX_CS0_TMG3_REG  (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
+    echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
+    echo [format "EX_MFSM_REG      (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
+    echo [format "EX_CSFSM_REG     (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
+    echo [format "EX_WRFSM_REG     (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
+    echo [format "EX_RDFSM_REG     (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
+}
+
+
+
+proc showGPIO {} {
+    echo "This is the current GPIO register setup"
+    # GPIO outputs register
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
+    # GPIO Output Enable register
+    set GPIO_OE_REG		    [regs GPIO_OE_REG]
+    set GPIO_HI_INT_ENABLE_REG	    [regs GPIO_HI_INT_ENABLE_REG]
+    set GPIO_LO_INT_ENABLE_REG	    [regs GPIO_LO_INT_ENABLE_REG]
+    # GPIO input register
+    set GPIO_INPUT_REG		    [regs GPIO_INPUT_REG]
+    set APB_ACCESS_WS_REG	    [regs APB_ACCESS_WS_REG]
+    set MUX_CONF_REG		    [regs MUX_CONF_REG]
+    set SYSCONF_REG		    [regs SYSCONF_REG]
+    set GPIO_ARM_ID_REG		    [regs GPIO_ARM_ID_REG]
+    set GPIO_BOOTSTRAP_REG	    [regs GPIO_BOOTSTRAP_REG]
+    set GPIO_LOCK_REG		    [regs GPIO_LOCK_REG]
+    set GPIO_IOCTRL_REG		    [regs GPIO_IOCTRL_REG]
+    set GPIO_DEVID_REG		    [regs GPIO_DEVID_REG]
+
+    echo [format "GPIO_OUTPUT_REG       (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
+    echo [format "GPIO_OE_REG           (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
+    echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
+    echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
+    echo [format "GPIO_INPUT_REG        (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
+    echo [format "APB_ACCESS_WS_REG     (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
+    echo [format "MUX_CONF_REG          (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
+    echo [format "SYSCONF_REG           (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
+    echo [format "GPIO_ARM_ID_REG       (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
+    echo [format "GPIO_BOOTSTRAP_REG    (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
+    echo [format "GPIO_LOCK_REG         (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
+    echo [format "GPIO_IOCTRL_REG       (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
+    echo [format "GPIO_DEVID_REG        (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
+}
+
+
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
+proc showAmbaClk {} {
+    set CFG_REFCLKFREQ		     [config CFG_REFCLKFREQ]
+    set CLKCORE_AHB_CLK_CNTRL	     [regs CLKCORE_AHB_CLK_CNTRL]
+    set PLL_CLK_BYPASS	             [regs PLL_CLK_BYPASS]
+
+    echo [format "CLKCORE_AHB_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
+    set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1]
+    # see if the PLL is in bypass mode
+    set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
+    echo [format "PLL bypass bit: %d" $bypass]
+    if {$bypass == 1} {
+	echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
+    } else {
+	# nope, extract x,y,w and compute the PLL output freq.
+	set x [expr {($value & 0x0001F0000) >> 16}]
+	echo [format "x: %d" $x]
+	set y [expr {($value & 0x00000007F)}]
+	echo [format "y: %d" $y]
+	set w [expr {($value & 0x000000300) >> 8}]
+	echo [format "w: %d" $w]
+	echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
+    }
+}
+
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
+# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
+proc setupAmbaClk {} {
+    set CLKCORE_PLL_STATUS           [regs CLKCORE_PLL_STATUS]
+    set CLKCORE_AHB_CLK_CNTRL	     [regs CLKCORE_AHB_CLK_CNTRL]
+    set ARM_PLL_BY_CTRL	    [regs ARM_PLL_BY_CTRL]
+    set ARM_AHB_BYP	    [regs ARM_AHB_BYP]
+    set PLL_DISABLE	    [regs PLL_DISABLE]
+    set PLL_CLK_BYPASS	    [regs PLL_CLK_BYPASS]
+    set AHB_PLL_BY_CTRL	    [regs AHB_PLL_BY_CTRL]
+    set DIV_BYPASS	    [regs DIV_BYPASS]
+    set AHBCLK_PLL_LOCK	    [regs AHBCLK_PLL_LOCK]
+    set CFG_REFCLKFREQ		 [config CFG_REFCLKFREQ]
+    set CONFIG_SYS_HZ_CLOCK      [config CONFIG_SYS_HZ_CLOCK]
+    set w    [config w_amba]
+    set x    [config x_amba]
+    set y    [config y_amba]
+
+    echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]]
+    #echo [format "setupAmbaClk: w= %d" $w]
+    #echo [format "setupAmbaClk: x= %d" $x]
+    #echo [format "setupAmbaClk: y= %d" $y]
+    # set PLL into BYPASS mode using MUX
+    mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
+    # do an internal PLL bypass
+    mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
+    # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
+    # openocd smallest resolution is 1ms so, wait 1ms
+    sleep 1
+    # disable the PLL
+    mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
+    # wait 1ms
+    sleep 1
+    # enable the PLL
+    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
+    sleep 1
+    # set X, W and X
+    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
+    mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
+    # wait for PLL to lock
+    echo "Waiting for Amba PLL to lock"
+    while {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK == 0} { sleep 1 }
+    # remove the internal PLL bypass
+    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
+    # remove PLL from BYPASS mode using MUX
+    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
+}
+
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
+proc showArmClk {} {
+    set CFG_REFCLKFREQ		[config CFG_REFCLKFREQ]
+    set CLKCORE_ARM_CLK_CNTRL	[regs CLKCORE_ARM_CLK_CNTRL]
+    set PLL_CLK_BYPASS	        [regs PLL_CLK_BYPASS]
+
+    echo [format "CLKCORE_ARM_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
+    set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1]
+    # see if the PLL is in bypass mode
+    set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
+    echo [format "PLL bypass bit: %d" $bypass]
+    if {$bypass == 1} {
+	echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
+    } else {
+	# nope, extract x,y,w and compute the PLL output freq.
+	set x [expr {($value & 0x0001F0000) >> 16}]
+	echo [format "x: %d" $x]
+	set y [expr {($value & 0x00000007F)}]
+	echo [format "y: %d" $y]
+	set w [expr {($value & 0x000000300) >> 8}]
+	echo [format "w: %d" $w]
+	echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
+    }
+}
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
+# Arm Clock is used by two ARM1136 cores
+proc setupArmClk {} {
+    set CLKCORE_PLL_STATUS        [regs CLKCORE_PLL_STATUS]
+    set CLKCORE_ARM_CLK_CNTRL	  [regs CLKCORE_ARM_CLK_CNTRL]
+    set ARM_PLL_BY_CTRL	          [regs ARM_PLL_BY_CTRL]
+    set ARM_AHB_BYP	          [regs ARM_AHB_BYP]
+    set PLL_DISABLE	          [regs PLL_DISABLE]
+    set PLL_CLK_BYPASS	          [regs PLL_CLK_BYPASS]
+    set AHB_PLL_BY_CTRL	          [regs AHB_PLL_BY_CTRL]
+    set DIV_BYPASS	          [regs DIV_BYPASS]
+    set FCLK_PLL_LOCK	          [regs FCLK_PLL_LOCK]
+    set CFG_REFCLKFREQ		[config CFG_REFCLKFREQ]
+    set CFG_ARM_CLOCK		[config CFG_ARM_CLOCK]
+    set w    [config w_arm]
+    set x    [config x_arm]
+    set y    [config y_arm]
+
+    echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]]
+    #echo [format "setupArmClk: w= %d" $w]
+    #echo [format "setupArmaClk: x= %d" $x]
+    #echo [format "setupArmaClk: y= %d" $y]
+    # set PLL into BYPASS mode using MUX
+    mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
+    # do an internal PLL bypass
+    mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
+    # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
+    # openocd smallest resolution is 1ms so, wait 1ms
+    sleep 1
+    # disable the PLL
+    mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
+    # wait 1ms
+    sleep 1
+    # enable the PLL
+    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
+    sleep 1
+    # set X, W and X
+    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
+    mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
+    # wait for PLL to lock
+    echo "Waiting for Amba PLL to lock"
+    while {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK == 0} { sleep 1 }
+    # remove the internal PLL bypass
+    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
+    # remove PLL from BYPASS mode using MUX
+    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
+}
+
+
+
+proc setupPLL {} {
+    echo "PLLs setup"
+    setupAmbaClk
+    setupArmClk
+}
+
+# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
+proc setupDDR2 {} {
+    echo "Configuring DDR2"
+
+    set MEMORY_BASE_ADDR	    [regs  MEMORY_BASE_ADDR]
+    set MEMORY_MAX_ADDR	            [regs  MEMORY_MAX_ADDR]
+    set MEMORY_CR 		    [regs  MEMORY_CR]
+    set BLOCK_RESET_REG		    [regs  BLOCK_RESET_REG]
+    set DDR_RST		            [regs  DDR_RST]
+
+    # put DDR controller in reset (so that it is reset and correctly configured)
+    # this is only necessary if DDR was previously confiured
+    # and not reset.
+    mmw $BLOCK_RESET_REG 0x0 $DDR_RST
+
+    set M [expr {1024 * 1024}]
+    set DDR_SZ_1024M	[expr {1024 * $M}]
+    set DDR_SZ_256M	[expr {256 * $M}]
+    set DDR_SZ_128M	[expr {128 * $M}]
+    set DDR_SZ_64M	[expr {64 * $M}]
+    # ooma_board_detect returns DDR2 memory size
+    set tmp [ooma_board_detect]
+    if {$tmp == "128M"} {
+	echo "DDR2 size 128MB"
+	set ddr_size $DDR_SZ_128M
+    } elseif {$tmp == "256M"} {
+	echo "DDR2 size 256MB"
+	set ddr_size $DDR_SZ_256M
+    } else {
+	echo "Don't know how to handle this DDR2 size?"
+    }
+
+    # Memory setup register
+    mww $MEMORY_MAX_ADDR  [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}]
+    # disable ROM remap
+    mww $MEMORY_CR 0x0
+    # Take DDR controller out of reset
+    mmw $BLOCK_RESET_REG $DDR_RST 0x0
+    # min. 20 ops delay
+    sleep 1
+
+    # This will setup Denali DDR2 controller
+    if {$tmp == "128M"} {
+	configureDDR2regs_128M
+    } elseif {$tmp == "256M"} {
+	configureDDR2regs_256M
+    } else {
+	echo "Don't know how to configure DDR2 setup?"
+    }
+}
+
+
+
+proc showDDR2 {} {
+
+    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
+    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
+    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
+    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
+    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
+    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
+    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
+    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
+    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
+    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
+    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
+    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
+    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
+    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
+    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
+    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
+    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
+    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
+    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
+    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
+    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
+
+    set tmp [mr64bit $DENALI_CTL_00_DATA]
+    echo [format "DENALI_CTL_00_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_01_DATA]
+    echo [format "DENALI_CTL_01_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_02_DATA]
+    echo [format "DENALI_CTL_02_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_03_DATA]
+    echo [format "DENALI_CTL_03_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_04_DATA]
+    echo [format "DENALI_CTL_04_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_05_DATA]
+    echo [format "DENALI_CTL_05_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_06_DATA]
+    echo [format "DENALI_CTL_06_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_07_DATA]
+    echo [format "DENALI_CTL_07_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_08_DATA]
+    echo [format "DENALI_CTL_08_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_09_DATA]
+    echo [format "DENALI_CTL_09_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_10_DATA]
+    echo [format "DENALI_CTL_10_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_11_DATA]
+    echo [format "DENALI_CTL_11_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_12_DATA]
+    echo [format "DENALI_CTL_12_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_13_DATA]
+    echo [format "DENALI_CTL_13_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_14_DATA]
+    echo [format "DENALI_CTL_14_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_15_DATA]
+    echo [format "DENALI_CTL_15_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_16_DATA]
+    echo [format "DENALI_CTL_16_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_17_DATA]
+    echo [format "DENALI_CTL_17_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_18_DATA]
+    echo [format "DENALI_CTL_18_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_19_DATA]
+    echo [format "DENALI_CTL_19_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_20_DATA]
+    echo [format "DENALI_CTL_20_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
+
+}
+
+proc initC100 {} {
+    # this follows u-boot/cpu/arm1136/start.S
+    set GPIO_LOCK_REG		    [regs GPIO_LOCK_REG]
+    set GPIO_IOCTRL_REG		    [regs GPIO_IOCTRL_REG]
+    set GPIO_IOCTRL_VAL	            [regs GPIO_IOCTRL_VAL]
+    set APB_ACCESS_WS_REG           [regs APB_ACCESS_WS_REG]
+    set ASA_ARAM_BASEADDR	    [regs ASA_ARAM_BASEADDR]
+    set ASA_ARAM_TC_CR_REG	    [regs ASA_ARAM_TC_CR_REG]
+    set ASA_EBUS_BASEADDR	    [regs ASA_EBUS_BASEADDR]
+    set ASA_EBUS_TC_CR_REG	    [regs ASA_EBUS_TC_CR_REG]
+    set ASA_TC_REQIDMAEN	    [regs ASA_TC_REQIDMAEN]
+    set ASA_TC_REQTDMEN	            [regs ASA_TC_REQTDMEN]
+    set ASA_TC_REQIPSECUSBEN        [regs ASA_TC_REQIPSECUSBEN]
+    set ASA_TC_REQARM0EN	    [regs ASA_TC_REQARM0EN]
+    set ASA_TC_REQARM1EN	    [regs ASA_TC_REQARM1EN]
+    set ASA_TC_REQMDMAEN	    [regs ASA_TC_REQMDMAEN]
+    set INTC_ARM1_CONTROL_REG       [regs INTC_ARM1_CONTROL_REG]
+
+
+    # unlock writing to IOCTRL register
+    mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
+    # enable address lines A15-A21
+    mmw $GPIO_IOCTRL_REG 0xf 0x0
+    # set ARM into supervisor mode (SVC32)
+    # disable IRQ, FIQ
+    # Do I need this in JTAG mode?
+    # it really should be done as 'and ~0x1f | 0xd3 but
+    # openocd does not support this yet
+    reg cpsr 0xd3
+    #	/*
+    #	 * flush v4 I/D caches
+    #	 */
+    #	mov	r0, #0
+    #	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+    arm mcr 15 0 7 7 0 0x0
+    #	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+    arm mcr 15 0 8 7 0 0x0
+
+    #	/*
+    #	 * disable MMU stuff and caches
+    #	 */
+    #	mrc	p15, 0, r0, c1, c0, 0
+    arm mrc 15 0 1 0 0
+    #	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+    #	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+    #	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+    #	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+    #	orr	r0, r0, #0x00400000	@ set bit 22 (U)
+    #	mcr	p15, 0, r0, c1, c0, 0
+    arm mcr 15 0 1 0 0 0x401002
+    # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
+    # APB init
+    #    	// Setting APB Bus Wait states to 1, set post write
+    #	(*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
+    mww $APB_ACCESS_WS_REG 0x40
+    # AHB init
+    #	// enable all 6 masters for ARAM
+    mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
+    #	// enable all 6 masters for EBUS
+    mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
+
+    # ARAM init
+    #	// disable pipeline mode in ARAM
+    # I don't think this is documented anywhere?
+    mww $INTC_ARM1_CONTROL_REG 0x1
+    # configure clocks
+    setupPLL
+    # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.
+    setupUART0
+    # enable cache
+    # ? (u-boot does nothing here)
+    # DDR2 memory init
+    setupDDR2
+    putsUART0 "C100 initialization complete.\n"
+    echo "C100 initialization complete."
+}
+
+# show current state of watchdog timer
+proc showWatchdog {} {
+    set TIMER_WDT_HIGH_BOUND	[regs TIMER_WDT_HIGH_BOUND]
+    set TIMER_WDT_CONTROL	[regs TIMER_WDT_CONTROL]
+    set TIMER_WDT_CURRENT_COUNT	[regs TIMER_WDT_CURRENT_COUNT]
+
+    echo [format "TIMER_WDT_HIGH_BOUND    (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
+    echo [format "TIMER_WDT_CONTROL       (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
+    echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
+}
+
+# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
+# this will trigger watchdog reset
+# the sw. reset does not work on C100
+# watchdog reset effectively works as hw. reset
+proc reboot {} {
+    set TIMER_WDT_HIGH_BOUND	[regs TIMER_WDT_HIGH_BOUND]
+    set TIMER_WDT_CONTROL	[regs TIMER_WDT_CONTROL]
+    set TIMER_WDT_CURRENT_COUNT	[regs TIMER_WDT_CURRENT_COUNT]
+
+    # allow the counter to count to high value  before triggering
+    # this is because register writes are slow over JTAG and
+    # I don't want to miss the high_bound==curr_count condition
+    mww $TIMER_WDT_HIGH_BOUND  0xffffff
+    mww $TIMER_WDT_CURRENT_COUNT 0x0
+    echo "JTAG speed lowered to 100kHz"
+    adapter speed 100
+    mww $TIMER_WDT_CONTROL 0x1
+    # wait until the reset
+    echo -n "Waiting for watchdog to trigger..."
+    #while {[mrw $TIMER_WDT_CONTROL] == 1} {
+    #    echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
+    #    sleep 1
+    #
+    #}
+    while {[c100.cpu curstate] != "running"} { sleep 1}
+    echo "done."
+    echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100regs.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100regs.tcl
new file mode 100644
index 0000000..7be8939
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/c100regs.tcl
@@ -0,0 +1,495 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Note that I basically converted
+# u-boot/include/asm-arm/arch/comcerto_100.h
+# defines
+
+# this is a work-around for 'global' not working under Linux
+# access registers by calling this routine.
+# For example:
+# set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]
+proc regs {reg} {
+    return [dict get [regsC100] $reg ]
+}
+
+proc showreg {reg} {
+    echo [format "0x%x" [dict get [regsC100] $reg ]]
+}
+
+proc regsC100 {} {
+#/* memcore */
+#/* device memory base addresses */
+#// device memory sizes
+#/* ARAM SIZE=64K */
+dict set regsC100 ARAM_SIZE		0x00010000
+dict set regsC100 ARAM_BASEADDR	0x0A000000
+
+#/* Hardware Interface Units */
+dict set regsC100 APB_BASEADDR	0x10000000
+#/* APB_SIZE=16M address range */
+dict set regsC100 APB_SIZE		0x01000000
+
+dict set regsC100 EXP_CS0_BASEADDR       0x20000000
+dict set regsC100 EXP_CS1_BASEADDR       0x24000000
+dict set regsC100 EXP_CS2_BASEADDR       0x28000000
+dict set regsC100 EXP_CS3_BASEADDR       0x2C000000
+dict set regsC100 EXP_CS4_BASEADDR       0x30000000
+
+dict set regsC100 DDR_BASEADDR           0x80000000
+
+dict set regsC100 TDM_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x000000}]
+dict set regsC100 PHI_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x010000}]
+dict set regsC100 TDMA_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x020000}]
+dict set regsC100 ASA_DDR_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x040000}]
+dict set regsC100 ASA_ARAM_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x048000}]
+dict set regsC100 TIMER_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x050000}]
+dict set regsC100 ASD_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x060000}]
+dict set regsC100 GPIO_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x070000}]
+dict set regsC100 UART0_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x090000}]
+dict set regsC100 UART1_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x094000}]
+dict set regsC100 SPI_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x098000}]
+dict set regsC100 I2C_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x09C000}]
+dict set regsC100 INTC_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0A0000}]
+dict set regsC100 CLKCORE_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}]
+dict set regsC100 PUI_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}]
+dict set regsC100 GEMAC_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0D0000}]
+dict set regsC100 IDMA_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0E0000}]
+dict set regsC100 MEMCORE_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0F0000}]
+dict set regsC100 ASA_EBUS_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x100000}]
+dict set regsC100 ASA_AAB_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x108000}]
+dict set regsC100 GEMAC1_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x190000}]
+dict set regsC100 EBUS_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x1A0000}]
+dict set regsC100 MDMA_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x1E0000}]
+
+
+#////////////////////////////////////////////////////////////
+#//	AHB block											    //
+#////////////////////////////////////////////////////////////
+dict set regsC100 ASA_ARAM_PRI_REG	[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00}]
+dict set regsC100 ASA_ARAM_TC_REG	[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04}]
+dict set regsC100 ASA_ARAM_TC_CR_REG	[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08}]
+dict set regsC100 ASA_ARAM_STAT_REG	[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C}]
+
+dict set regsC100 ASA_EBUS_PRI_REG	[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00}]
+dict set regsC100 ASA_EBUS_TC_REG	[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04}]
+dict set regsC100 ASA_EBUS_TC_CR_REG	[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08}]
+dict set regsC100 ASA_EBUS_STAT_REG	[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C}]
+
+dict set regsC100 IDMA_MASTER		0
+dict set regsC100 TDMA_MASTER		1
+dict set regsC100 USBIPSEC_MASTER	2
+dict set regsC100 ARM0_MASTER		3
+dict set regsC100 ARM1_MASTER		4
+dict set regsC100 MDMA_MASTER		5
+
+#define IDMA_PRIORITY(level) (level)
+#define TDM_PRIORITY(level) (level << 4)
+#define USBIPSEC_PRIORITY(level) (level << 8)
+#define ARM0_PRIORITY(level) (level << 12)
+#define ARM1_PRIORITY(level) (level << 16)
+#define MDMA_PRIORITY(level) (level << 20)
+
+dict set regsC100 ASA_TC_REQIDMAEN	 [expr {1<<18}]
+dict set regsC100 ASA_TC_REQTDMEN	 [expr {1<<19}]
+dict set regsC100 ASA_TC_REQIPSECUSBEN [expr {1<<20}]
+dict set regsC100 ASA_TC_REQARM0EN	 [expr {1<<21}]
+dict set regsC100 ASA_TC_REQARM1EN	 [expr {1<<22}]
+dict set regsC100 ASA_TC_REQMDMAEN	 [expr {1<<23}]
+
+dict set regsC100 MEMORY_BASE_ADDR	0x80000000
+dict set regsC100 MEMORY_MAX_ADDR	[expr {[dict get $regsC100 ASD_BASEADDR ] + 0x10}]
+dict set regsC100 MEMORY_CR 		[expr {[dict get $regsC100 ASD_BASEADDR ] + 0x14}]
+dict set regsC100 ROM_REMAP_EN	0x1
+
+#define HAL_asb_priority(level) \
+#*(volatile unsigned *)ASA_PRI_REG = level
+
+#define HAL_aram_priority(level) \
+#*(volatile unsigned *)ASA_ARAM_PRI_REG = level
+
+#define HAL_aram_arbitration(arbitration_mask) \
+#*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask
+
+#define HAL_aram_defmaster(mask) \
+#*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24)
+
+#////////////////////////////////////////////////////////////
+#// INTC block						  //
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 INTC_ARM1_CONTROL_REG	[expr {[dict get $regsC100 INTC_BASEADDR ] + 0x18}]
+
+#////////////////////////////////////////////////////////////
+#// TIMER block						  //
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 TIMER0_CNTR_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x00}]
+dict set regsC100 TIMER0_CURR_COUNT	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x04}]
+dict set regsC100 TIMER1_CNTR_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x08}]
+dict set regsC100 TIMER1_CURR_COUNT	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x0C}]
+
+dict set regsC100 TIMER2_CNTR_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x18}]
+dict set regsC100 TIMER2_LBOUND_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x10}]
+dict set regsC100 TIMER2_HBOUND_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x14}]
+dict set regsC100 TIMER2_CURR_COUNT	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x1C}]
+
+dict set regsC100 TIMER3_LOBND	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x20}]
+dict set regsC100 TIMER3_HIBND	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x24}]
+dict set regsC100 TIMER3_CTRL		[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x28}]
+dict set regsC100 TIMER3_CURR_COUNT	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x2C}]
+
+dict set regsC100 TIMER_MASK		[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x40}]
+dict set regsC100 TIMER_STATUS	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}]
+dict set regsC100 TIMER_ACK		[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}]
+dict set regsC100 TIMER_WDT_HIGH_BOUND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD0}]
+dict set regsC100 TIMER_WDT_CONTROL	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD4}]
+dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD8}]
+
+
+
+#////////////////////////////////////////////////////////////
+#//  EBUS block
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 EX_SWRST_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x00}]
+dict set regsC100 EX_CSEN_REG		        [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x04}]
+dict set regsC100 EX_CS0_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x08}]
+dict set regsC100 EX_CS1_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x0C}]
+dict set regsC100 EX_CS2_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x10}]
+dict set regsC100 EX_CS3_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x14}]
+dict set regsC100 EX_CS4_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x18}]
+dict set regsC100 EX_CS0_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x1C}]
+dict set regsC100 EX_CS1_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x20}]
+dict set regsC100 EX_CS2_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x24}]
+dict set regsC100 EX_CS3_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x28}]
+dict set regsC100 EX_CS4_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x2C}]
+dict set regsC100 EX_CS0_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x30}]
+dict set regsC100 EX_CS1_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x34}]
+dict set regsC100 EX_CS2_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x38}]
+dict set regsC100 EX_CS3_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x3C}]
+dict set regsC100 EX_CS4_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x40}]
+dict set regsC100 EX_CS0_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x44}]
+dict set regsC100 EX_CS1_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x48}]
+dict set regsC100 EX_CS2_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x4C}]
+dict set regsC100 EX_CS3_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x50}]
+dict set regsC100 EX_CS4_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x54}]
+dict set regsC100 EX_CS0_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x58}]
+dict set regsC100 EX_CS1_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x5C}]
+dict set regsC100 EX_CS2_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x60}]
+dict set regsC100 EX_CS3_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x64}]
+dict set regsC100 EX_CS4_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x68}]
+dict set regsC100 EX_CLOCK_DIV_REG	        [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x6C}]
+
+dict set regsC100 EX_MFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}]
+dict set regsC100 EX_MFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}]
+dict set regsC100 EX_CSFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x104}]
+dict set regsC100 EX_WRFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x108}]
+dict set regsC100 EX_RDFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x10C}]
+
+
+dict set regsC100 EX_CLK_EN		0x00000001
+dict set regsC100 EX_CSBOOT_EN	0x00000002
+dict set regsC100 EX_CS0_EN		0x00000002
+dict set regsC100 EX_CS1_EN		0x00000004
+dict set regsC100 EX_CS2_EN		0x00000008
+dict set regsC100 EX_CS3_EN		0x00000010
+dict set regsC100 EX_CS4_EN		0x00000020
+
+dict set regsC100 EX_MEM_BUS_8	0x00000000
+dict set regsC100 EX_MEM_BUS_16       0x00000002
+dict set regsC100 EX_MEM_BUS_32	0x00000004
+dict set regsC100 EX_CS_HIGH		0x00000008
+dict set regsC100 EX_WE_HIGH		0x00000010
+dict set regsC100 EX_RE_HIGH		0x00000020
+dict set regsC100 EX_ALE_MODE		0x00000040
+dict set regsC100 EX_STRB_MODE	0x00000080
+dict set regsC100 EX_DM_MODE		0x00000100
+dict set regsC100 EX_NAND_MODE	0x00000200
+dict set regsC100 EX_RDY_EN		0x00000400
+dict set regsC100 EX_RDY_EDGE		0x00000800
+
+#////////////////////////////////////////////////////////////
+#//  GPIO block
+#////////////////////////////////////////////////////////////
+
+# GPIO outputs register
+dict set regsC100 GPIO_OUTPUT_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x00}]
+# GPIO Output Enable register
+dict set regsC100 GPIO_OE_REG		        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x04}]
+dict set regsC100 GPIO_HI_INT_ENABLE_REG	[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x08}]
+dict set regsC100 GPIO_LO_INT_ENABLE_REG	[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x0C}]
+# GPIO input register
+dict set regsC100 GPIO_INPUT_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x10}]
+dict set regsC100 APB_ACCESS_WS_REG	        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x14}]
+dict set regsC100 MUX_CONF_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x18}]
+dict set regsC100 SYSCONF_REG		        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x1C}]
+dict set regsC100 GPIO_ARM_ID_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x30}]
+dict set regsC100 GPIO_BOOTSTRAP_REG	        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x40}]
+dict set regsC100 GPIO_LOCK_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x38}]
+dict set regsC100 GPIO_IOCTRL_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x44}]
+dict set regsC100 GPIO_DEVID_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x50}]
+
+dict set regsC100 GPIO_IOCTRL_A15A16	0x00000001
+dict set regsC100 GPIO_IOCTRL_A17A18	0x00000002
+dict set regsC100 GPIO_IOCTRL_A19A21	0x00000004
+dict set regsC100 GPIO_IOCTRL_TMREVT0	0x00000008
+dict set regsC100 GPIO_IOCTRL_TMREVT1	0x00000010
+dict set regsC100 GPIO_IOCTRL_GPBT3	0x00000020
+dict set regsC100 GPIO_IOCTRL_I2C	0x00000040
+dict set regsC100 GPIO_IOCTRL_UART0	0x00000080
+dict set regsC100 GPIO_IOCTRL_UART1	0x00000100
+dict set regsC100 GPIO_IOCTRL_SPI	0x00000200
+dict set regsC100 GPIO_IOCTRL_HBMODE	0x00000400
+
+dict set regsC100 GPIO_IOCTRL_VAL	0x55555555
+
+dict set regsC100 GPIO_0			0x01
+dict set regsC100 GPIO_1			0x02
+dict set regsC100 GPIO_2			0x04
+dict set regsC100 GPIO_3			0x08
+dict set regsC100 GPIO_4			0x10
+dict set regsC100 GPIO_5			0x20
+dict set regsC100 GPIO_6			0x40
+dict set regsC100 GPIO_7			0x80
+
+dict set regsC100 GPIO_RISING_EDGE	1
+dict set regsC100 GPIO_FALLING_EDGE	2
+dict set regsC100 GPIO_BOTH_EDGES	3
+
+#////////////////////////////////////////////////////////////
+#// UART
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 UART0_RBR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]
+dict set regsC100 UART0_THR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]
+dict set regsC100 UART0_DLL		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]
+dict set regsC100 UART0_IER		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}]
+dict set regsC100 UART0_DLH		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}]
+dict set regsC100 UART0_IIR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}]
+dict set regsC100 UART0_FCR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}]
+dict set regsC100 UART0_LCR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x0C}]
+dict set regsC100 UART0_MCR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x10}]
+dict set regsC100 UART0_LSR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x14}]
+dict set regsC100 UART0_MSR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x18}]
+dict set regsC100 UART0_SCR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x1C}]
+
+dict set regsC100 UART1_RBR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]
+dict set regsC100 UART1_THR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]
+dict set regsC100 UART1_DLL		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]
+dict set regsC100 UART1_IER		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}]
+dict set regsC100 UART1_DLH		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}]
+dict set regsC100 UART1_IIR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}]
+dict set regsC100 UART1_FCR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}]
+dict set regsC100 UART1_LCR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x0C}]
+dict set regsC100 UART1_MCR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x10}]
+dict set regsC100 UART1_LSR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x14}]
+dict set regsC100 UART1_MSR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x18}]
+dict set regsC100 UART1_SCR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x1C}]
+
+# /* default */
+dict set regsC100 LCR_CHAR_LEN_5		0x00
+dict set regsC100 LCR_CHAR_LEN_6		0x01
+dict set regsC100 LCR_CHAR_LEN_7		0x02
+dict set regsC100 LCR_CHAR_LEN_8		0x03
+#/* One stop bit! - default */
+dict set regsC100 LCR_ONE_STOP		0x00
+#/* Two stop bit! */
+dict set regsC100 LCR_TWO_STOP		0x04
+#/* Parity Enable */
+dict set regsC100 LCR_PEN			0x08
+dict set regsC100 LCR_PARITY_NONE		0x00
+#/* Even Parity Select */
+dict set regsC100 LCR_EPS			0x10
+#/* Enable Parity  Stuff */
+dict set regsC100 LCR_PS			0x20
+#/* Start Break */
+dict set regsC100 LCR_SBRK		        0x40
+#/* Parity Stuff Bit */
+dict set regsC100 LCR_PSB			0x80
+#/* UART 16550 Divisor Latch Assess */
+dict set regsC100 LCR_DLAB		        0x80
+
+#/* FIFO Error Status */
+dict set regsC100 LSR_FIFOE		[expr {1 << 7}]
+#/* Transmitter Empty */
+dict set regsC100 LSR_TEMT		[expr {1 << 6}]
+#/* Transmit Data Request */
+dict set regsC100 LSR_TDRQ		[expr {1 << 5}]
+#/* Break Interrupt */
+dict set regsC100 LSR_BI			[expr {1 << 4}]
+#/* Framing Error */
+dict set regsC100 LSR_FE			[expr {1 << 3}]
+#/* Parity Error */
+dict set regsC100 LSR_PE			[expr {1 << 2}]
+#/* Overrun Error */
+dict set regsC100 LSR_OE			[expr {1 << 1}]
+#/* Data Ready */
+dict set regsC100 LSR_DR			[expr {1 << 0}]
+
+#/* DMA Requests Enable */
+dict set regsC100 IER_DMAE		        [expr {1 << 7}]
+#/* UART Unit Enable */
+dict set regsC100 IER_UUE			[expr {1 << 6}]
+#/* NRZ coding Enable */
+dict set regsC100 IER_NRZE		        [expr {1 << 5}]
+#/* Receiver Time Out Interrupt Enable */
+dict set regsC100 IER_RTIOE		        [expr {1 << 4}]
+#/* Modem Interrupt Enable */
+dict set regsC100 IER_MIE			[expr {1 << 3}]
+#/* Receiver Line Status Interrupt Enable */
+dict set regsC100 IER_RLSE		        [expr {1 << 2}]
+#/* Transmit Data request Interrupt Enable */
+dict set regsC100 IER_TIE			[expr {1 << 1}]
+#/* Receiver Data Available Interrupt Enable */
+dict set regsC100 IER_RAVIE		        [expr {1 << 0}]
+
+#/* FIFO Mode Enable Status */
+dict set regsC100 IIR_FIFOES1		        [expr {1 << 7}]
+#/* FIFO Mode Enable Status */
+dict set regsC100 IIR_FIFOES0		        [expr {1 << 6}]
+#/* Time Out Detected */
+dict set regsC100 IIR_TOD			[expr {1 << 3}]
+#/* Interrupt Source Encoded */
+dict set regsC100 IIR_IID2		        [expr {1 << 2}]
+#/* Interrupt Source Encoded */
+dict set regsC100 IIR_IID1		        [expr {1 << 1}]
+#/* Interrupt Pending (active low) */
+dict set regsC100 IIR_IP			[expr {1 << 0}]
+
+#/* UART 16550 FIFO Control Register */
+dict set regsC100 FCR_FIFOEN		0x01
+dict set regsC100 FCR_RCVRRES		0x02
+dict set regsC100 FCR_XMITRES		0x04
+
+#/* Interrupt Enable Register */
+#// UART 16550
+#// Enable Received Data Available Interrupt
+dict set regsC100 IER_RXTH		0x01
+#// Enable Transmitter Empty Interrupt
+dict set regsC100 IER_TXTH		0x02
+
+
+
+#////////////////////////////////////////////////////////////
+#// CLK  + RESET block
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 CLKCORE_ARM_CLK_CNTRL	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x00}]
+dict set regsC100 CLKCORE_AHB_CLK_CNTRL	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x04}]
+dict set regsC100 CLKCORE_PLL_STATUS	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x08}]
+dict set regsC100 CLKCORE_CLKDIV_CNTRL	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C}]
+dict set regsC100 CLKCORE_TDM_CLK_CNTRL	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x10}]
+dict set regsC100 CLKCORE_FSYNC_CNTRL	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x14}]
+dict set regsC100 CLKCORE_CLK_PWR_DWN	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x18}]
+dict set regsC100 CLKCORE_RNG_CNTRL	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C}]
+dict set regsC100 CLKCORE_RNG_STATUS	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x20}]
+dict set regsC100 CLKCORE_ARM_CLK_CNTRL2	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x24}]
+dict set regsC100 CLKCORE_TDM_REF_DIV_RST	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x40}]
+
+dict set regsC100 ARM_PLL_BY_CTRL	0x80000000
+dict set regsC100 ARM_AHB_BYP		0x04000000
+dict set regsC100 PLL_DISABLE		0x02000000
+dict set regsC100 PLL_CLK_BYPASS	0x01000000
+
+dict set regsC100 AHB_PLL_BY_CTRL	0x80000000
+dict set regsC100 DIV_BYPASS		0x40000000
+dict set regsC100 SYNC_MODE		0x20000000
+
+dict set regsC100 EPHY_CLKDIV_BYPASS	0x00200000
+dict set regsC100 EPHY_CLKDIV_RATIO_SHIFT	16
+dict set regsC100 PUI_CLKDIV_BYPASS	0x00004000
+dict set regsC100 PUI_CLKDIV_SRCCLK	0x00002000
+dict set regsC100 PUI_CLKDIV_RATIO_SHIFT	8
+dict set regsC100 PCI_CLKDIV_BYPASS	0x00000020
+dict set regsC100 PCI_CLKDIV_RATIO_SHIFT	0
+
+dict set regsC100 ARM0_CLK_PD		0x00200000
+dict set regsC100 ARM1_CLK_PD		0x00100000
+dict set regsC100 EPHY_CLK_PD		0x00080000
+dict set regsC100 TDM_CLK_PD		0x00040000
+dict set regsC100 PUI_CLK_PD		0x00020000
+dict set regsC100 PCI_CLK_PD		0x00010000
+dict set regsC100 MDMA_AHBCLK_PD	0x00000400
+dict set regsC100 I2CSPI_AHBCLK_PD	0x00000200
+dict set regsC100 UART_AHBCLK_PD	0x00000100
+dict set regsC100 IPSEC_AHBCLK_PD	0x00000080
+dict set regsC100 TDM_AHBCLK_PD	0x00000040
+dict set regsC100 USB1_AHBCLK_PD	0x00000020
+dict set regsC100 USB0_AHBCLK_PD	0x00000010
+dict set regsC100 GEMAC1_AHBCLK_PD	0x00000008
+dict set regsC100 GEMAC0_AHBCLK_PD	0x00000004
+dict set regsC100 PUI_AHBCLK_PD	0x00000002
+dict set regsC100 HIF_AHBCLK_PD	0x00000001
+
+dict set regsC100 ARM1_DIV_BP		0x00001000
+dict set regsC100 ARM1_DIV_VAL_SHIFT	8
+dict set regsC100 ARM0_DIV_BP		0x00000010
+dict set regsC100 ARM0_DIV_VAL_SHIFT	0
+
+dict set regsC100 AHBCLK_PLL_LOCK	0x00000002
+dict set regsC100 FCLK_PLL_LOCK	0x00000001
+
+
+#// reset block
+dict set regsC100 BLOCK_RESET_REG		[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x100}]
+dict set regsC100 CSP_RESET_REG		[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x104}]
+
+dict set regsC100 RNG_RST		0x1000
+dict set regsC100 IPSEC_RST		0x0800
+dict set regsC100 DDR_RST		0x0400
+dict set regsC100 USB1_PHY_RST	0x0200
+dict set regsC100 USB0_PHY_RST	0x0100
+dict set regsC100 USB1_RST		0x0080
+dict set regsC100 USB0_RST		0x0040
+dict set regsC100 GEMAC1_RST		0x0020
+dict set regsC100 GEMAC0_RST		0x0010
+dict set regsC100 TDM_RST		0x0008
+dict set regsC100 PUI_RST		0x0004
+dict set regsC100 HIF_RST		0x0002
+dict set regsC100 PCI_RST		0x0001
+
+#////////////////////////////////////////////////////////////////
+#//	DDR  CONTROLLER block
+#////////////////////////////////////////////////////////////////
+
+dict set regsC100 DDR_CONFIG_BASEADDR	0x0D000000
+dict set regsC100 DENALI_CTL_00_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00}]
+dict set regsC100 DENALI_CTL_01_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08}]
+dict set regsC100 DENALI_CTL_02_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10}]
+dict set regsC100 DENALI_CTL_03_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18}]
+dict set regsC100 DENALI_CTL_04_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20}]
+dict set regsC100 DENALI_CTL_05_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28}]
+dict set regsC100 DENALI_CTL_06_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30}]
+dict set regsC100 DENALI_CTL_07_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38}]
+dict set regsC100 DENALI_CTL_08_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40}]
+dict set regsC100 DENALI_CTL_09_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48}]
+dict set regsC100 DENALI_CTL_10_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50}]
+dict set regsC100 DENALI_CTL_11_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58}]
+dict set regsC100 DENALI_CTL_12_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60}]
+dict set regsC100 DENALI_CTL_13_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68}]
+dict set regsC100 DENALI_CTL_14_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70}]
+dict set regsC100 DENALI_CTL_15_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78}]
+dict set regsC100 DENALI_CTL_16_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80}]
+dict set regsC100 DENALI_CTL_17_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88}]
+dict set regsC100 DENALI_CTL_18_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90}]
+dict set regsC100 DENALI_CTL_19_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98}]
+dict set regsC100 DENALI_CTL_20_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0}]
+
+# 32-bit value
+dict set regsC100 DENALI_READY_CHECK         [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44}]
+# 8-bit
+dict set regsC100 DENALI_WR_DQS              [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D}]
+# 8-bit
+dict set regsC100 DENALI_DQS_OUT             [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A}]
+# 8-bit
+dict set regsC100 DENALI_DQS_DELAY0          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F}]
+# 8-bit
+dict set regsC100 DENALI_DQS_DELAY1          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50}]
+# 8-bit
+dict set regsC100 DENALI_DQS_DELAY2          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51}]
+# 8-bit
+dict set regsC100 DENALI_DQS_DELAY3          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52}]
+
+
+# end of proc regsC100
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/cavium_cn61xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/cavium_cn61xx.cfg
new file mode 100644
index 0000000..60b56a5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/cavium_cn61xx.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Cavium Octeon II CN61xx (PrID 0x000D9301)
+
+jtag newtap cpu tap0 -irlen 5
+jtag newtap cpu tap1 -irlen 5
+
+target create cpu.core0 mips_mips64 -chain-position cpu.tap0 -endian big -rtos hwthread -coreid 0
+target create cpu.core1 mips_mips64 -chain-position cpu.tap1 -endian big -rtos hwthread -coreid 1
+target smp cpu.core0 cpu.core1
+
+cpu.core0 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000
+cpu.core1 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000
+
+targets cpu.core0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/cc2538.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/cc2538.cfg
new file mode 100644
index 0000000..e4fb02a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/cc2538.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Texas Instruments low power RF SoC CC2538
+# http://www.ti.com/lit/pdf/swru319
+
+adapter speed 100
+
+source [find target/icepick.cfg]
+source [find target/ti-cjtag.cfg]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cc2538
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x8B96402F
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+#
+# ICEpick-C (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID 0x8B96402F
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+# A start sequence is needed to change from cJTAG (Compact JTAG) to
+# 4-pin JTAG before talking via JTAG commands
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
+jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
+
+#
+# Cortex-M3 target
+#
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/cs351x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/cs351x.cfg
new file mode 100644
index 0000000..e67540a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/cs351x.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME cs351x
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x00526fa1
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# There is 16K of SRAM on this chip
+# FIXME: flash programming is not working by using this work area. So comment this out for now.
+#$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1
+
+# This chip has a DCC ... use it
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/davinci.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/davinci.cfg
new file mode 100644
index 0000000..54afb64
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/davinci.cfg
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Utility code for DaVinci-family chips
+#
+
+# davinci_pinmux: assigns PINMUX$reg <== $value
+proc davinci_pinmux {soc reg value} {
+	mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value
+}
+
+source [find mem_helper.tcl]
+
+#
+# pll_setup: initialize PLL
+#  - pll_addr ... physical addr of controller
+#  - mult ... pll multiplier
+#  - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
+#
+# For PLLs that don't have a given register (e.g. plldiv8), or where a
+# given divider is non-programmable, caller provides *NO* config mapping.
+#
+
+# PLL version 0x02: tested on dm355
+# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
+proc pll_v02_setup {pll_addr mult config} {
+	set pll_ctrl_addr [expr {$pll_addr + 0x100}]
+	set pll_ctrl [mrw $pll_ctrl_addr]
+
+	# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
+	# NOTE: this assumes we should clear that bit
+	set pll_ctrl [expr {$pll_ctrl & ~0x0100}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 2 - clear PLLENSRC (bit 5)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 3 - clear PLLEN (bit 0) ... enter bypass mode
+	set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 4 - wait at least 4 refclk cycles
+	sleep 1
+
+	# 5 - set PLLRST (bit 3)
+	set pll_ctrl [expr {$pll_ctrl | 0x0008}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 6 - set PLLDIS (bit 4)
+	set pll_ctrl [expr {$pll_ctrl | 0x0010}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 7 - clear PLLPWRDN (bit 1)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 8 - clear PLLDIS (bit 4)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0010}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 9 - optional: write prediv, postdiv, and pllm
+	# NOTE: for dm355 PLL1, postdiv is controlled via MISC register
+	mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}]
+	if { [dict exists $config prediv] } {
+		set div [dict get $config prediv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0114}] $div
+	}
+	if { [dict exists $config postdiv] } {
+		set div [dict get $config postdiv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0128}] $div
+	}
+
+	# 10 - optional: set plldiv1, plldiv2, ...
+	# NOTE:  this assumes some registers have their just-reset values:
+	#	- PLLSTAT.GOSTAT is clear when we enter
+	#	- ALNCTL has everything set
+	set go 0
+	if { [dict exists $config div1] } {
+		set div [dict get $config div1]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0118}] $div
+		set go 1
+	}
+	if { [dict exists $config div2] } {
+		set div [dict get $config div2]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x011c}] $div
+		set go 1
+	}
+	if { [dict exists $config div3] } {
+		set div [dict get $config div3]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0120}] $div
+		set go 1
+	}
+	if { [dict exists $config div4] } {
+		set div [dict get $config div4]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0160}] $div
+		set go 1
+	}
+	if { [dict exists $config div5] } {
+		set div [dict get $config div5]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0164}] $div
+		set go 1
+	}
+	if {$go != 0} {
+		# write pllcmd.GO; poll pllstat.GO
+		mww [expr {$pll_addr + 0x0138}] 0x01
+		set pllstat [expr {$pll_addr + 0x013c}]
+		while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
+	}
+	mww [expr {$pll_addr + 0x0138}] 0x00
+
+	# 11 - wait at least 5 usec for reset to finish
+	# (assume covered by overheads including JTAG messaging)
+
+	# 12 - clear PLLRST (bit 3)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 13 - wait at least 8000 refclk cycles for PLL to lock
+	# if we assume 24 MHz (slowest osc), that's 1/3 msec
+	sleep 3
+
+	# 14 - set PLLEN (bit 0) ... leave bypass mode
+	set pll_ctrl [expr {$pll_ctrl | 0x0001}]
+	mww $pll_ctrl_addr $pll_ctrl
+}
+
+# PLL version 0x03: tested on dm365
+proc pll_v03_setup {pll_addr mult config} {
+	set pll_ctrl_addr [expr {$pll_addr + 0x100}]
+	set pll_secctrl_addr [expr {$pll_addr + 0x108}]
+	set pll_ctrl [mrw $pll_ctrl_addr]
+
+	# 1 - power up the PLL
+	set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 2 - clear PLLENSRC (bit 5)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 2 - clear PLLEN (bit 0) ... enter bypass mode
+	set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 3 - wait at least 4 refclk cycles
+	sleep 1
+
+	# 4 - set PLLRST (bit 3)
+	set pll_ctrl [expr {$pll_ctrl | 0x0008}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 5 - wait at least 5 usec
+	sleep 1
+
+	# 6 - clear PLLRST (bit 3)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 9 - optional: write prediv, postdiv, and pllm
+	mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}]
+	if { [dict exists $config prediv] } {
+		set div [dict get $config prediv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0114}] $div
+	}
+	if { [dict exists $config postdiv] } {
+		set div [dict get $config postdiv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0128}] $div
+	}
+
+	# 10 - write start sequence to PLLSECCTL
+	mww $pll_secctrl_addr 0x00470000
+	mww $pll_secctrl_addr 0x00460000
+	mww $pll_secctrl_addr 0x00400000
+	mww $pll_secctrl_addr 0x00410000
+
+	# 11 - optional: set plldiv1, plldiv2, ...
+	# NOTE: this assumes some registers have their just-reset values:
+	#	- PLLSTAT.GOSTAT is clear when we enter
+	set aln 0
+	if { [dict exists $config div1] } {
+		set div [dict get $config div1]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0118}] $div
+		set aln [expr {$aln | 0x1}]
+	} else {
+		mww [expr {$pll_addr + 0x0118}] 0
+	}
+	if { [dict exists $config div2] } {
+		set div [dict get $config div2]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x011c}] $div
+		set aln [expr {$aln | 0x2}]
+	} else {
+		mww [expr {$pll_addr + 0x011c}] 0
+	}
+	if { [dict exists $config div3] } {
+		set div [dict get $config div3]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0120}] $div
+		set aln [expr {$aln | 0x4}]
+	} else {
+		mww [expr {$pll_addr + 0x0120}] 0
+	}
+	if { [dict exists $config oscdiv] } {
+		set div [dict get $config oscdiv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0124}] $div
+	} else {
+		mww [expr {$pll_addr + 0x0124}] 0
+	}
+	if { [dict exists $config div4] } {
+		set div [dict get $config div4]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0160}] $div
+		set aln [expr {$aln | 0x8}]
+	} else {
+		mww [expr {$pll_addr + 0x0160}] 0
+	}
+	if { [dict exists $config div5] } {
+		set div [dict get $config div5]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0164}] $div
+		set aln [expr {$aln | 0x10}]
+	} else {
+		mww [expr {$pll_addr + 0x0164}] 0
+	}
+	if { [dict exists $config div6] } {
+		set div [dict get $config div6]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0168}] $div
+		set aln [expr {$aln | 0x20}]
+	} else {
+		mww [expr {$pll_addr + 0x0168}] 0
+	}
+	if { [dict exists $config div7] } {
+		set div [dict get $config div7]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x016c}] $div
+		set aln [expr {$aln | 0x40}]
+	} else {
+		mww [expr {$pll_addr + 0x016c}] 0
+	}
+	if { [dict exists $config div8] } {
+		set div [dict get $config div8]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0170}] $div
+		set aln [expr {$aln | 0x80}]
+	} else {
+		mww [expr {$pll_addr + 0x0170}] 0
+	}
+	if { [dict exists $config div9] } {
+		set div [dict get $config div9]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0174}] $div
+		set aln [expr {$aln | 0x100}]
+	} else {
+		mww [expr {$pll_addr + 0x0174}] 0
+	}
+	if {$aln != 0} {
+		# clear pllcmd.GO
+		mww [expr {$pll_addr + 0x0138}] 0x00
+		# write alignment flags
+		mww [expr {$pll_addr + 0x0140}] $aln
+		# write pllcmd.GO; poll pllstat.GO
+		mww [expr {$pll_addr + 0x0138}] 0x01
+		set pllstat [expr {$pll_addr + 0x013c}]
+		while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
+	}
+	mww [expr {$pll_addr + 0x0138}] 0x00
+	set addr [dict get $config ctladdr]
+	while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 }
+
+	# 12 - set PLLEN (bit 0) ... leave bypass mode
+	set pll_ctrl [expr {$pll_ctrl | 0x0001}]
+	mww $pll_ctrl_addr $pll_ctrl
+}
+
+# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
+# modules can be enabled.
+
+# prepare a non-DSP module to be enabled; finish with psc_go
+proc psc_enable {module} {
+	set psc_addr 0x01c41000
+	# write MDCTL
+	mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f
+}
+
+# prepare a non-DSP module to be reset; finish with psc_go
+proc psc_reset {module} {
+	set psc_addr 0x01c41000
+	# write MDCTL
+	mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f
+}
+
+# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
+proc psc_go {} {
+	set psc_addr 0x01c41000
+	set ptstat_addr [expr {$psc_addr + 0x0128}]
+
+	# just in case PTSTAT.go isn't clear
+	while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
+
+	# write PTCMD.go ... ignoring any DSP power domain
+	mww [expr {$psc_addr + 0x0120}] 1
+
+	# wait for PTSTAT.go to clear (again ignoring DSP power domain)
+	while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
+}
+
+#
+# A reset using only SRST is a "Warm Reset", resetting everything in the
+# chip except ARM emulation (and everything _outside_ the chip that hooks
+# up to SRST).  But many boards don't expose SRST via their JTAG connectors
+# (it's not present on TI-14 headers).
+#
+# From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except
+# without any board-wide side effects, since it's triggered using JTAG using
+# either (a) ARM watchdog timer, or (b) ICEpick.
+#
+proc davinci_wdog_reset {} {
+	set timer2_phys 0x01c21c00
+
+	# NOTE -- on entry
+	#   - JTAG communication with the ARM *must* be working OK; this
+	#     may imply using adaptive clocking or disabling WFI-in-idle
+	#   - current target must be the DaVinci ARM
+	#   - that ARM core must be halted
+	#   - timer2 clock is still enabled (PSC 29 on most chips)
+
+	#
+	# Part I -- run regardless of being halted via JTAG
+	#
+	# NOTE:  for now, we assume there's no DSP that could control the
+	# watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog
+	# suspend signal is controlled via ARM emulation suspend.
+	#
+
+	# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
+	mww phys [expr {$timer2_phys + 0x28}] 0x00004000
+
+	#
+	# Part II -- in case watchdog hasn't been set up
+	#
+
+	# TCR: disable, force internal clock source
+	mww phys [expr {$timer2_phys + 0x20}] 0
+
+	# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
+	mww phys [expr {$timer2_phys + 0x24}] 0
+	mww phys [expr {$timer2_phys + 0x24}] 0x110b
+
+	# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
+	# so watchdog triggers ASAP
+	mww phys [expr {$timer2_phys + 0x10}] 0
+	mww phys [expr {$timer2_phys + 0x14}] 0
+	mww phys [expr {$timer2_phys + 0x18}] 0
+	mww phys [expr {$timer2_phys + 0x1c}] 0
+
+	# WDTCR: put into pre-active state, then active
+	mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000
+	mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000
+
+	#
+	# Part III -- it's ready to rumble
+	#
+
+	# WDTCR: write invalid WDKEY to trigger reset
+	mww phys [expr {$timer2_phys + 0x28}] 0x00004000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dragonite.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dragonite.cfg
new file mode 100644
index 0000000..249de25
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dragonite.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Marvell Dragonite CPU core
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dragonite
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x121003d3
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
+
+reset_config trst_and_srst
+adapter srst delay 200
+jtag_ntrst_delay 200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dsp56321.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dsp56321.cfg
new file mode 100644
index 0000000..fac0ccc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dsp56321.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Script for freescale DSP56321
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dsp56321
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a big endian
+   set _ENDIAN big
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1181501d
+}
+
+#jtag speed
+adapter speed 4500
+
+#has only srst
+reset_config srst_only
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id $_CPUTAPID
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dsp563xx -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#working area at base of ram
+$_TARGETNAME configure -work-area-virt 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dsp568013.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dsp568013.cfg
new file mode 100644
index 0000000..5cf5c02
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dsp568013.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Script for freescale DSP568013
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dsp568013
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a big endian
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x01f2401d
+}
+
+#jtag speed
+adapter speed 800
+
+reset_config srst_only
+
+#MASTER tap
+jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
+
+#CORE tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
+
+#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Setup the interesting tap
+# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations require certain instruction to be in the IR register during reset, and polling would change this)
+jtag configure $_CHIPNAME.chp -event setup "
+     jtag tapenable $_TARGETNAME
+     poll off
+"
+
+#select CORE tap by modifying the TLM register.
+#to be used when MASTER tap is selected.
+jtag configure $_TARGETNAME -event tap-enable "
+     irscan $_CHIPNAME.chp 0x05;
+     drscan $_CHIPNAME.chp 4 0x02;
+     jtag tapdisable $_CHIPNAME.chp;
+"
+
+#select MASTER tap by modifying the TLM register.
+#to be used when CORE tap is selected.
+jtag configure $_CHIPNAME.chp -event tap-enable "
+     irscan $_TARGETNAME 0x08;
+     drscan $_TARGETNAME 4 0x1;
+     jtag tapdisable $_TARGETNAME;
+"
+
+#disables the master tap
+jtag configure $_TARGETNAME -event tap-disable "
+"
+#TODO FIND SMARTER WAY.
+
+jtag configure $_CHIPNAME.chp -event tap-disable "
+"
+#TODO FIND SMARTER WAY.
+
+
+#working area at base of ram
+$_TARGETNAME configure -work-area-virt 0
+
+#setup flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dsp568037.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dsp568037.cfg
new file mode 100644
index 0000000..5d86811
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/dsp568037.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Script for freescale DSP568037
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dsp568037
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a big endian
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x01f2801d
+}
+
+#jtag speed
+adapter speed 800
+
+reset_config srst_only
+
+#MASTER tap
+jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
+
+#CORE tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
+
+#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Setup the interesting tap
+jtag configure $_CHIPNAME.chp -event setup "jtag tapenable $_TARGETNAME"
+
+#select CORE tap by modifying the TLM register.
+#to be used when MASTER tap is selected.
+jtag configure $_TARGETNAME -event tap-enable "
+     irscan $_CHIPNAME.chp 0x05;
+     drscan $_CHIPNAME.chp 4 0x02;
+     jtag tapdisable $_CHIPNAME.chp;
+"
+
+#select MASTER tap by modifying the TLM register.
+#to be used when CORE tap is selected.
+jtag configure $_CHIPNAME.chp -event tap-enable "
+     irscan $_TARGETNAME 0x08;
+     drscan $_TARGETNAME 4 0x1;
+     jtag tapdisable $_TARGETNAME;
+"
+
+#disables the master tap
+jtag configure $_TARGETNAME -event tap-disable "
+"
+#TODO FIND SMARTER WAY.
+
+jtag configure $_CHIPNAME.chp -event tap-disable "
+"
+#TODO FIND SMARTER WAY.
+
+
+#working area at base of ram
+$_TARGETNAME configure -work-area-virt 0
+
+#setup flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/efm32.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/efm32.cfg
new file mode 100644
index 0000000..2187c0a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/efm32.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Silicon Labs (formerly Energy Micro) EFM32 target
+#
+# Note: All EFM32 chips have SWD support, but only newer series 1
+# chips have JTAG support.
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME efm32
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+adapter speed 1000
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
+flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
+flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/em357.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/em357.cfg
new file mode 100644
index 0000000..ddefa28
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/em357.cfg
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Target configuration for the Silicon Labs EM357 chips
+#
+
+#
+# em357 family supports JTAG and SWD transports
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME em357
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x3ba00477
+   } else {
+      set _CPUTAPID 0x1ba00477
+   }
+}
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+  set _BSTAPID 0x069a962b
+}
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME em358
+}
+
+if { [info exists FLASHSIZE] } {
+    set _FLASHSIZE $FLASHSIZE
+} else {
+    set _FLASHSIZE 0x30000
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+if { [using_jtag] } {
+    jtag newtap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME em357 0x08000000 $_FLASHSIZE 0 0 $_TARGETNAME
+
+if { ![using_hla]} {
+# according to errata, we need to use vectreset rather than sysresetreq to avoid lockup
+# There is a bug in the chip, which means that when using external debuggers the chip
+# may lock up in certain CPU clock modes. Affected modes are operating the CPU at
+# 24MHz derived from the 24MHz crystal, or 12MHz derived from the high frequency RC
+# oscillator. If an external debugger tool asserts SYSRESETREQ, the chip will lock up and
+# require a pin reset or power cycle.
+#
+# for details, refer to:
+# http://www.silabs.com/Support%20Documents/TechnicalDocs/EM35x-Errata.pdf
+    cortex_m reset_config vectreset
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/em358.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/em358.cfg
new file mode 100644
index 0000000..63f4088
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/em358.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Silicon Labs EM358 chips
+
+#
+# em357 family supports JTAG and SWD transports
+#
+
+if { ![info exists CHIPNAME] } {
+   set CHIPNAME em358
+}
+
+if { ![info exists BSTAPID] } {
+  set BSTAPID 0x069aa62b
+}
+
+# 512K of flash in the em358 chips
+set FLASHSIZE 0x80000
+source [find target/em357.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/eos_s3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/eos_s3.cfg
new file mode 100644
index 0000000..150ef4e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/eos_s3.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# QuickLogic EOS S3
+# https://www.quicklogic.com/products/soc/eos-s3-microcontroller/
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME eos_s3
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x80000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# For now we use SRAM only for software upload
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+adapter speed 4000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/epc9301.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/epc9301.cfg
new file mode 100644
index 0000000..41021d5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/epc9301.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME ep9301
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # Force an error until we get a good number.
+   set _CPUTAPID 0xffffffff
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
+
+#flash configuration
+#flash bank      [driver_options ...]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x60000000 0x1000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esi32xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esi32xx.cfg
new file mode 100644
index 0000000..d29c636
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esi32xx.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# EnSilica eSi-32xx SoC (eSi-RISC Family)
+# http://www.ensilica.com/risc-ip/
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME esi32xx
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x11234001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME esirisc -chain-position $_CHIPNAME.cpu
+
+# Targets with the UNIFIED_ADDRESS_SPACE option disabled should set
+# CACHEARCH to 'harvard'. By default, 'von_neumann' is assumed.
+if { [info exists CACHEARCH] } {
+    $_TARGETNAME esirisc cache_arch $CACHEARCH
+}
+
+adapter speed 2000
+
+reset_config none
+
+# The default linker scripts provided by the eSi-RISC toolchain do not
+# specify attributes on memory regions, which results in incorrect
+# application of software breakpoints by GDB.
+gdb breakpoint_override hard
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32.cfg
new file mode 100644
index 0000000..b30a170
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"esp32"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH 					"xtensa"
+set _ONLYCPU					3
+set _FLASH_VOLTAGE 				3.3
+set _ESP_SMP_TARGET				1
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG 	0x3ff5A004
+
+if { [info exists ESP32_ONLYCPU] } {
+	set _ONLYCPU $ESP32_ONLYCPU
+}
+
+if { [info exists ESP32_FLASH_VOLTAGE] } {
+	set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
+}
+
+proc esp32_memprot_is_enabled { } {
+	return 0
+}
+
+proc esp32_soc_reset { } {
+	soft_reset_halt
+}
+
+create_esp_target $_ESP_ARCH
+
+source [find target/xtensa-core-esp32.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32c2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32c2.cfg
new file mode 100644
index 0000000..42aeb0a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32c2.cfg
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x0000cc25
+set _ESP_ARCH 					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60008840
+
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
+    # Halt event can occur during config phase (before "init" is done).
+    # Ignore it since mww commands don't work at that time.
+    if { [string compare [command mode] config] == 0 } {
+        return
+    }
+
+    # Timer Group 0 WDT
+    mww 0x6001f064 0x50D83AA1
+    mww 0x6001F048 0
+    # RTC WDT
+    mww 0x6000809C 0x50D83AA1
+    mww 0x60008084 0
+    # SWD
+    mww 0x600080A4 0x8F1D312A
+    mww 0x600080A0 0x84B00000
+}
+
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL
+
+    # This procedure does "digital system reset", i.e. resets
+    # all the peripherals except for the RTC block.
+    # It is called from reset-assert-post target event callback,
+    # after assert_reset procedure was called.
+    # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
+    # temporarily take it out of reset. Save the dmcontrol state before
+    # doing so.
+    riscv dmi_write $_RISCV_DMCONTROL 0x80000001
+    # Trigger the reset
+    mww 0x60008000 0x9c00a000
+    # Workaround for stuck in cpu start during calibration.
+    # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
+    mww 0x6001F068 0
+    # Wait for the reset to happen
+    sleep 10
+    poll
+    # Disable the watchdogs again
+    riscv_wdt_disable
+
+    # Here debugger reads allresumeack and allhalted bits as set (0x330a2)
+    # We will clean allhalted state by resuming the core.
+    riscv dmi_write $_RISCV_DMCONTROL 0x40000001
+
+    # Put the hart back into reset state. Note that we need to keep haltreq set.
+    riscv dmi_write $_RISCV_DMCONTROL 0x80000003
+}
+
+proc riscv_memprot_is_enabled { } {
+	global _RISCV_ABS_CMD _RISCV_ABS_DATA0
+
+	# PMPADDR 0-1 covers entire valid IRAM range and PMPADDR 2-3 covers entire DRAM region
+	# pmpcfg0 holds the configuration for the PMP 0-3 address registers
+
+	# read pmpcfg0 and extract into 8-bit variables.
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203a0
+	set pmpcfg0 [riscv dmi_read $_RISCV_ABS_DATA0]
+
+	set pmp0cfg [expr {($pmpcfg0 >> (8 * 0)) & 0xFF}]
+	set pmp1cfg [expr {($pmpcfg0 >> (8 * 1)) & 0xFF}]
+	set pmp2cfg [expr {($pmpcfg0 >> (8 * 2)) & 0xFF}]
+	set pmp3cfg [expr {($pmpcfg0 >> (8 * 3)) & 0xFF}]
+
+	# read PMPADDR 0-3
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b0
+	set pmpaddr0 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b1
+	set pmpaddr1 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b2
+	set pmpaddr2 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b3
+	set pmpaddr3 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+
+	set IRAM_LOW 	0x40380000
+	set IRAM_HIGH 	0x403C0000
+	set DRAM_LOW 	0x3FCA0000
+	set DRAM_HIGH 	0x3FCE0000
+	set PMP_RWX     0x07
+	set PMP_RW     	0x03
+
+	# The lock bit remains unset during the execution of the 2nd stage bootloader.
+	# Thus we do not perform a lock bit check for IRAM and DRAM regions.
+
+	# Check OpenOCD can write and execute from IRAM.
+	if {$pmpaddr0 >= $IRAM_LOW && $pmpaddr1 <= $IRAM_HIGH} {
+    	if {($pmp0cfg & $PMP_RWX) != 0 || ($pmp1cfg & $PMP_RWX) != $PMP_RWX} {
+			return 1
+		}
+	}
+
+	# Check OpenOCD can read/write entire DRAM region.
+	if {$pmpaddr2 >= $DRAM_LOW && $pmpaddr3 <= $DRAM_HIGH} {
+    	if {($pmp2cfg & $PMP_RW) != 0 && ($pmp3cfg & $PMP_RW) != $PMP_RW} {
+			return 1
+		}
+	}
+
+	return 0
+}
+
+create_esp_target $_ESP_ARCH
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32c3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32c3.cfg
new file mode 100644
index 0000000..d266ad5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32c3.cfg
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x00005c25
+set _ESP_ARCH					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60008844
+
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
+    # Halt event can occur during config phase (before "init" is done).
+    # Ignore it since mww commands don't work at that time.
+    if { [string compare [command mode] config] == 0 } {
+        return
+    }
+
+    # Timer Group 0 & 1 WDTs
+    mww 0x6001f064 0x50D83AA1
+    mww 0x6001F048 0
+    mww 0x60020064 0x50D83AA1
+    mww 0x60020048 0
+    # RTC WDT
+    mww 0x600080a8 0x50D83AA1
+    mww 0x60008090 0
+    # SWD
+    mww 0x600080b0 0x8F1D312A
+    mww 0x600080ac 0x84B00000
+}
+
+# This is almost identical with the esp32c2_soc_reset.
+# Will be refactored with the other common settings.
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL
+
+    # This procedure does "digital system reset", i.e. resets
+    # all the peripherals except for the RTC block.
+    # It is called from reset-assert-post target event callback,
+    # after assert_reset procedure was called.
+    # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
+    # temporarily take it out of reset. Save the dmcontrol state before
+    # doing so.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000001
+    # Trigger the reset
+    mww 0x60008000 0x9c00a000
+    # Workaround for stuck in cpu start during calibration.
+    # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
+    mww 0x6001F068 0
+    # Wait for the reset to happen
+    sleep 10
+    poll
+    # Disable the watchdogs again
+    riscv_wdt_disable
+
+    # Here debugger reads allresumeack and allhalted bits as set (0x330a2)
+    # We will clean allhalted state by resuming the core.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x40000001
+
+    # Put the hart back into reset state. Note that we need to keep haltreq set.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000003
+}
+
+proc riscv_memprot_is_enabled { } {
+    # IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+    if { [get_mmr_bit 0x600C10A8 0] != 0 } {
+        return 1
+    }
+    # DRAM0 PMS lock, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+    if { [get_mmr_bit 0x600C10C0 0] != 0 } {
+        return 1
+    }
+    return 0
+}
+
+create_esp_target $_ESP_ARCH
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32c6.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32c6.cfg
new file mode 100644
index 0000000..e1ef10a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32c6.cfg
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x0000dc25
+set _ESP_ARCH					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x600B0844
+
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
+    # Halt event can occur during config phase (before "init" is done).
+    # Ignore it since mww commands don't work at that time.
+    if { [string compare [command mode] config] == 0 } {
+        return
+    }
+
+    # Timer Group 0 & 1 WDTs
+    mww 0x60008064 0x50D83AA1
+    mww 0x60008048 0
+    mww 0x60009064 0x50D83AA1
+    mww 0x60009048 0
+    # LP_WDT_RTC
+    mww 0x600b1c18 0x50D83AA1
+    mww 0x600B1C00 0
+    # LP_WDT_SWD
+    mww 0x600b1c20 0x50D83AA1
+    mww 0x600b1c1c 0x40000000
+}
+
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0
+
+    riscv dmi_write $_RISCV_DMCONTROL 		0x80000001
+    riscv dmi_write $_RISCV_SB_CS 			0x48000
+    riscv dmi_write $_RISCV_SB_ADDR0 		0x600b1034
+    riscv dmi_write $_RISCV_SB_DATA0		0x80000000
+    # clear dmactive to clear sbbusy otherwise debug module gets stuck
+    riscv dmi_write $_RISCV_DMCONTROL 		0
+
+    riscv dmi_write $_RISCV_SB_CS 			0x48000
+    riscv dmi_write $_RISCV_SB_ADDR0 		0x600b1038
+    riscv dmi_write $_RISCV_SB_DATA0 		0x10000000
+
+    # clear dmactive to clear sbbusy otherwise debug module gets stuck
+    riscv dmi_write $_RISCV_DMCONTROL 		0
+    riscv dmi_write $_RISCV_DMCONTROL 		0x40000001
+    # Here debugger reads dmstatus as 0xc03a2
+
+    # Wait for the reset to happen
+    sleep 10
+    poll
+    # Here debugger reads dmstatus as 0x3a2
+
+    # Disable the watchdogs again
+    riscv_wdt_disable
+
+    # Here debugger reads anyhalted and allhalted bits as set (0x3a2)
+    # We will clean allhalted state by resuming the core.
+    riscv dmi_write $_RISCV_DMCONTROL 		0x40000001
+
+    # Put the hart back into reset state. Note that we need to keep haltreq set.
+    riscv dmi_write $_RISCV_DMCONTROL 		0x80000003
+}
+
+proc riscv_memprot_is_enabled { } {
+	global _RISCV_ABS_CMD _RISCV_ABS_DATA0
+
+	# If IRAM/DRAM split is enabled TOR address match mode is used.
+    # If IRAM/DRAM split is disabled NAPOT mode is used.
+	# In order to determine if the IRAM/DRAM regions are protected against RWX/RW,
+	# it is necessary to first read the mode and then apply the appropriate method for checking.
+	# We can understand the mode reading pmp5cfg in pmpcfg1 register.
+	# If it is none we know that pmp6cfg and pmp7cfg is in TOR mode.
+
+	# Read pmpcfg1 and extract into 8-bit variables.
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203a1
+	set pmpcfg1 [riscv dmi_read $_RISCV_ABS_DATA0]
+
+	set pmp5cfg [expr {($pmpcfg1 >> (8 * 1)) & 0xFF}]
+	set pmp6cfg [expr {($pmpcfg1 >> (8 * 2)) & 0xFF}]
+	set pmp7cfg [expr {($pmpcfg1 >> (8 * 3)) & 0xFF}]
+
+	set IRAM_LOW 	0x40800000
+	set IRAM_HIGH 	0x40880000
+	set DRAM_LOW 	0x40800000
+	set DRAM_HIGH 	0x40880000
+	set PMP_RWX     0x07
+	set PMP_RW     	0x03
+	set PMP_A		[expr {($pmp5cfg >> 3) & 0x03}]
+
+	if {$PMP_A == 0} {
+		# TOR mode used to protect valid address space.
+
+		# Read PMPADDR 5-7
+		riscv dmi_write $_RISCV_ABS_CMD 0x2203b5
+		set pmpaddr5 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+		riscv dmi_write $_RISCV_ABS_CMD 0x2203b6
+		set pmpaddr6 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+		riscv dmi_write $_RISCV_ABS_CMD 0x2203b7
+		set pmpaddr7 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+
+		# The lock bit remains unset during the execution of the 2nd stage bootloader.
+		# Thus we do not perform a lock bit check for IRAM and DRAM regions.
+
+		# Check OpenOCD can write and execute from IRAM.
+		if {$pmpaddr5 >= $IRAM_LOW && $pmpaddr6 <= $IRAM_HIGH} {
+			if {($pmp5cfg & $PMP_RWX) != 0 || ($pmp6cfg & $PMP_RWX) != $PMP_RWX} {
+				return 1
+			}
+		}
+
+		# Check OpenOCD can read/write  entire DRAM region.
+		if {$pmpaddr7 >= $DRAM_LOW && $pmpaddr7 <= $DRAM_HIGH} {
+			if {($pmp7cfg & $PMP_RW) != $PMP_RW} {
+				return 1
+			}
+		}
+	} elseif {$PMP_A == 3} {
+		# NAPOT mode used to protect valid address space.
+
+		# Read PMPADDR 5
+		riscv dmi_write $_RISCV_ABS_CMD 0x2203b5
+		set pmpaddr5 [expr {[riscv dmi_read $_RISCV_ABS_DATA0]}]
+
+		# Expected value written to the pmpaddr5
+		set pmpaddr_napot [expr {($IRAM_LOW | (($IRAM_HIGH - $IRAM_LOW - 1) >> 1)) >> 2}]
+		if {($pmpaddr_napot != $pmpaddr5) ||  ($pmp5cfg & $PMP_RWX) != $PMP_RWX} {
+			return 1
+		}
+	}
+
+	return 0
+}
+
+create_esp_target $_ESP_ARCH
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32h2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32h2.cfg
new file mode 100644
index 0000000..45f598f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32h2.cfg
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x00010c25
+set _ESP_ARCH					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x600B0844
+
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
+    # Halt event can occur during config phase (before "init" is done).
+    # Ignore it since mww commands don't work at that time.
+    if { [string compare [command mode] config] == 0 } {
+        return
+    }
+
+    # Timer Group 0 & 1 WDTs
+    mww 0x60009064 0x50D83AA1
+    mww 0x60009048 0
+    mww 0x6000A064 0x50D83AA1
+    mww 0x6000A048 0
+    # WDT_RTC
+    #mww 0x600b1c18 0x50D83AA1
+    #mww 0x600B1C00 0
+    # WDT_SWD
+    #mww 0x600b1c20 0x8F1D312A
+    #mww 0x600b1c1c 0x84B00000
+}
+
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0
+
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000001
+    riscv dmi_write $_RISCV_SB_CS 		0x48000
+    riscv dmi_write $_RISCV_SB_ADDR0 	0x600b1034
+    riscv dmi_write $_RISCV_SB_DATA0 	0x80000000
+    # clear dmactive to clear sbbusy otherwise debug module gets stuck
+    riscv dmi_write $_RISCV_DMCONTROL 	0
+
+    riscv dmi_write $_RISCV_SB_CS 		0x48000
+    riscv dmi_write $_RISCV_SB_ADDR0 	0x600b1038
+    riscv dmi_write $_RISCV_SB_DATA0 	0x10000000
+
+    # clear dmactive to clear sbbusy otherwise debug module gets stuck
+    riscv dmi_write $_RISCV_DMCONTROL 	0
+    riscv dmi_write $_RISCV_DMCONTROL 	0x40000001
+    # Here debugger reads dmstatus as 0xc03a2
+
+    # Wait for the reset to happen
+    sleep 10
+    poll
+    # Here debugger reads dmstatus as 0x3a2
+
+    # Disable the watchdogs again
+    riscv_wdt_disable
+
+    # Here debugger reads anyhalted and allhalted bits as set (0x3a2)
+    # We will clean allhalted state by resuming the core.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x40000001
+
+    # Put the hart back into reset state. Note that we need to keep haltreq set.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000003
+}
+
+proc riscv_memprot_is_enabled { } {
+	global _RISCV_ABS_CMD _RISCV_ABS_DATA0
+	# If IRAM/DRAM split is enabled, PMPADDR 5-6 will cover valid IRAM region and PMPADDR 7 will cover valid DRAM region
+	# Only TOR mode is used for IRAM and DRAM protections.
+
+	# Read pmpcfg1 and extract into 8-bit variables.
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203a1
+	set pmpcfg1 [riscv dmi_read $_RISCV_ABS_DATA0]
+
+	set pmp5cfg [expr {($pmpcfg1 >> (8 * 1)) & 0xFF}]
+	set pmp6cfg [expr {($pmpcfg1 >> (8 * 2)) & 0xFF}]
+	set pmp7cfg [expr {($pmpcfg1 >> (8 * 3)) & 0xFF}]
+
+	# Read PMPADDR 5-7
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b5
+	set pmpaddr5 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b6
+	set pmpaddr6 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b7
+	set pmpaddr7 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+
+	set IRAM_LOW 	0x40800000
+	set IRAM_HIGH 	0x40850000
+	set DRAM_LOW 	0x40800000
+	set DRAM_HIGH 	0x40850000
+
+	set PMP_RWX     0x07
+	set PMP_RW     	0x03
+
+	# The lock bit remains unset during the execution of the 2nd stage bootloader.
+	# Thus, we do not perform a lock bit check for IRAM and DRAM regions.
+
+	# Check OpenOCD can write and execute from IRAM.
+	if {$pmpaddr5 >= $IRAM_LOW && $pmpaddr6 <= $IRAM_HIGH} {
+		if {($pmp5cfg & $PMP_RWX) != 0 || ($pmp6cfg & $PMP_RWX) != $PMP_RWX} {
+			return 1
+		}
+	}
+
+	# Check OpenOCD can read/write  entire DRAM region.
+	# If IRAM/DRAM split is disabled, pmpaddr7 will be zero, checking only IRAM region is enough.
+	if {$pmpaddr7 != 0 && $pmpaddr7 >= $DRAM_LOW && $pmpaddr7 <= $DRAM_HIGH} {
+		if {($pmp7cfg & $PMP_RW) != $PMP_RW} {
+			return 1
+		}
+	}
+
+	return 0
+}
+
+create_esp_target $_ESP_ARCH
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32s2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32s2.cfg
new file mode 100644
index 0000000..4c1362a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32s2.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"esp32s2"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH					"xtensa"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG  	0x3f41A004
+
+proc esp32s2_memprot_is_enabled { } {
+	# IRAM0, DPORT_PMS_PRO_IRAM0_0_REG
+	if { [get_mmr_bit 0x3f4c1010 0] != 0 } {
+		return 1
+	}
+	# DRAM0, DPORT_PMS_PRO_DRAM0_0_REG
+	if { [get_mmr_bit 0x3f4c1028 0] != 0 } {
+		return 1
+	}
+	# PERI1, DPORT_PMS_PRO_DPORT_0_REG
+	if { [get_mmr_bit 0x3f4c103c 0] != 0 } {
+		return 1
+	}
+	# PERI2, DPORT_PMS_PRO_AHB_0_REG
+	if { [get_mmr_bit 0x3f4c105c 0] != 0 } {
+		return 1
+	}
+	return 0
+}
+
+proc esp32s2_soc_reset { } {
+	soft_reset_halt
+}
+
+create_esp_target $_ESP_ARCH
+
+source [find target/xtensa-core-esp32s2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32s3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32s3.cfg
new file mode 100644
index 0000000..12c166c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp32s3.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"esp32s3"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH 					"xtensa"
+set _ONLYCPU					3
+set _ESP_SMP_TARGET				1
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60007044
+
+if { [info exists ESP32_S3_ONLYCPU] } {
+	set _ONLYCPU $ESP32_S3_ONLYCPU
+}
+
+proc esp32s3_memprot_is_enabled { } {
+	# SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C10C0 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C1124 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C11D0 0] != 0 } {
+		return 1
+	}
+	# IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C10D8 0] != 0 } {
+		return 1
+	}
+	# DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C10FC 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C10E4 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C10F0 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C1104 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C1114 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C119C 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C1248 0] != 0 } {
+		return 1
+	}
+	return 0
+}
+
+proc esp32s3_soc_reset { } {
+	soft_reset_halt
+}
+
+create_esp_target $_ESP_ARCH
+
+source [find target/xtensa-core-esp32s3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp_common.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp_common.cfg
new file mode 100644
index 0000000..5ea9bc8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/esp_common.cfg
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+source [find bitsbytes.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+# Riscv Debug Module Registers which are used around esp configuration files.
+set _RISCV_ABS_DATA0	0x04
+set _RISCV_DMCONTROL	0x10
+set _RISCV_ABS_CMD		0x17
+set _RISCV_SB_CS		0x38
+set _RISCV_SB_ADDR0		0x39
+set _RISCV_SB_DATA0		0x3C
+
+# Common ESP chips definitions
+
+# Espressif supports only NuttX in the upstream.
+# FreeRTOS support is not upstreamed yet.
+set _RTOS "hwthread"
+if { [info exists ESP_RTOS] } {
+	set _RTOS "$ESP_RTOS"
+}
+
+# by default current dir (when OOCD has been started)
+set _SEMIHOST_BASEDIR "."
+if { [info exists ESP_SEMIHOST_BASEDIR] } {
+	set _SEMIHOST_BASEDIR $ESP_SEMIHOST_BASEDIR
+}
+
+proc set_esp_common_variables { } {
+	global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET
+	global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1
+	global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED
+
+	# For now we support dual core at most.
+	if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} {
+		set _TARGETNAME_0 				$_CHIPNAME
+		set _CPUNAME_0					cpu
+		set _TAPNAME_0 					$_CHIPNAME.$_CPUNAME_0
+	} else {
+		set _CPUNAME_0 					cpu0
+		set _CPUNAME_1 					cpu1
+		set _TARGETNAME_0 				$_CHIPNAME.$_CPUNAME_0
+		set _TARGETNAME_1 				$_CHIPNAME.$_CPUNAME_1
+		set _TAPNAME_0 					$_TARGETNAME_0
+		set _TAPNAME_1 					$_TARGETNAME_1
+	}
+
+	set _ESP_WDT_DISABLE 			"${_CHIPNAME}_wdt_disable"
+	set _ESP_SOC_RESET 				"${_CHIPNAME}_soc_reset"
+	set _ESP_MEMPROT_IS_ENABLED 	"${_CHIPNAME}_memprot_is_enabled"
+}
+
+proc create_esp_jtag { } {
+	global _CHIPNAME _CPUNAME_0 _CPUNAME_1 _CPUTAPID _ONLYCPU
+	jtag newtap $_CHIPNAME $_CPUNAME_0 -irlen 5 -expected-id $_CPUTAPID
+	if { $_ONLYCPU != 1 } {
+		jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -expected-id $_CPUTAPID
+	} elseif [info exists _CPUNAME_1] {
+		jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -disable -expected-id $_CPUTAPID
+	}
+}
+
+proc create_openocd_targets  { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU
+
+	target create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS
+	if { $_ONLYCPU != 1 } {
+		target create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS
+		target smp $_TARGETNAME_0 $_TARGETNAME_1
+	}
+}
+
+proc create_esp_target { ARCH } {
+	set_esp_common_variables
+	create_esp_jtag
+	create_openocd_targets
+	configure_openocd_events $ARCH
+
+	if { $ARCH == "xtensa"} {
+		configure_esp_xtensa_default_settings
+	} else {
+		configure_esp_riscv_default_settings
+	}
+}
+
+#################### Set event handlers and default settings  ####################
+
+proc configure_event_examine_end { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
+
+	$_TARGETNAME_0 configure -event examine-end {
+		# Need to enable to set 'semihosting_basedir'
+		arm semihosting enable
+		arm semihosting_resexit enable
+		if { [info exists _SEMIHOST_BASEDIR] } {
+			if { $_SEMIHOST_BASEDIR != "" } {
+				arm semihosting_basedir $_SEMIHOST_BASEDIR
+			}
+		}
+	}
+
+	if { $_ONLYCPU != 1 } {
+		$_TARGETNAME_1 configure -event examine-end {
+			# Need to enable to set 'semihosting_basedir'
+			arm semihosting enable
+			arm semihosting_resexit enable
+			if { [info exists _SEMIHOST_BASEDIR] } {
+				if { $_SEMIHOST_BASEDIR != "" } {
+					arm semihosting_basedir $_SEMIHOST_BASEDIR
+				}
+			}
+		}
+	}
+}
+
+proc configure_event_reset_assert_post { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
+
+	$_TARGETNAME_0 configure -event reset-assert-post {
+		global _ESP_SOC_RESET
+		$_ESP_SOC_RESET
+	}
+
+	if { $_ONLYCPU != 1 } {
+		$_TARGETNAME_1 configure -event reset-assert-post {
+			global _ESP_SOC_RESET
+			$_ESP_SOC_RESET
+		}
+	}
+}
+
+proc configure_event_halted { } {
+	global _TARGETNAME_0
+
+	$_TARGETNAME_0 configure -event halted {
+		global _ESP_WDT_DISABLE
+	    $_ESP_WDT_DISABLE
+	}
+}
+
+proc configure_event_gdb_attach { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
+
+	$_TARGETNAME_0 configure -event gdb-attach {
+		if { $_ESP_SMP_BREAK != 0 } {
+			$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+		}
+		# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
+		halt 1000
+		if { [$_ESP_MEMPROT_IS_ENABLED] } {
+			# 'reset halt' to disable memory protection and allow flasher to work correctly
+			echo "Memory protection is enabled. Reset target to disable it..."
+			reset halt
+		}
+	}
+
+	if { $_ONLYCPU != 1 } {
+		$_TARGETNAME_1 configure -event gdb-attach {
+			if { $_ESP_SMP_BREAK != 0 } {
+				$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
+			}
+			# necessary to auto-probe flash bank when GDB is connected
+			halt 1000
+			if { [$_ESP_MEMPROT_IS_ENABLED] } {
+				# 'reset halt' to disable memory protection and allow flasher to work correctly
+				echo "Memory protection is enabled. Reset target to disable it..."
+				reset halt
+			}
+		}
+	}
+}
+
+proc configure_openocd_events { ARCH } {
+	if { $ARCH == "riscv" } {
+		configure_event_halted
+	}
+	configure_event_examine_end
+	configure_event_reset_assert_post
+	configure_event_gdb_attach
+}
+
+proc configure_esp_riscv_default_settings { } {
+	gdb_breakpoint_override hard
+	riscv set_reset_timeout_sec 2
+	riscv set_command_timeout_sec 5
+	riscv set_mem_access sysbus progbuf abstract
+	riscv set_ebreakm on
+	riscv set_ebreaks on
+	riscv set_ebreaku on
+}
+
+proc configure_esp_xtensa_default_settings { } {
+	global _TARGETNAME_0 _ESP_SMP_BREAK _FLASH_VOLTAGE _CHIPNAME
+
+	$_TARGETNAME_0 xtensa maskisr on
+	if { $_ESP_SMP_BREAK != 0 } {
+		$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+	}
+
+	gdb breakpoint_override hard
+
+	if { [info exists _FLASH_VOLTAGE] } {
+		$_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/exynos5250.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/exynos5250.cfg
new file mode 100644
index 0000000..a565022
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/exynos5250.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Samsung Exynos 5250 - dual-core ARM Cortex-A15
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME exynos5250
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap
+target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap
+
+target smp ${_TARGETNAME}0 ${_TARGETNAME}1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/faux.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/faux.cfg
new file mode 100644
index 0000000..71cb8b7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/faux.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#Script for faux target - used for testing
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91eb40a
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x00000000
+}
+
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#dummy flash driver
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/feroceon.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/feroceon.cfg
new file mode 100644
index 0000000..593569d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/feroceon.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Marvell Feroceon CPU core
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME feroceon
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x20a023d3
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
+
+reset_config trst_and_srst
+adapter srst delay 200
+jtag_ntrst_delay 200
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm3.cfg
new file mode 100644
index 0000000..0caf629
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm3.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MB9BF506
+# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME mb9bfxx6
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+# delays on reset lines
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+# Fujitsu Cortex-M3 reset configuration
+reset_config trst_only
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# MB9BF506 has 64kB of SRAM on its main system bus
+$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
+
+# MB9BF506 has 512kB internal FLASH
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
+
+# 4MHz / 6 = 666kHz, so use 500
+adapter speed 500
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm4.cfg
new file mode 100644
index 0000000..4318f2e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm4.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion FM4 (ARM Cortex-M4)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME fm4
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CPUTAPID] } {
+	set _CPU_TAPID $CPUTAPID
+} elseif { [using_jtag] } {
+	set _CPU_TAPID 0x4ba00477
+} else {
+	set _CPU_TAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+adapter speed 500
+
+if {![using_hla]} {
+	cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm4_mb9bf.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm4_mb9bf.cfg
new file mode 100644
index 0000000..4bc579c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm4_mb9bf.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion FM4 MB9BFxxx (ARM Cortex-M4)
+#
+
+source [find target/fm4.cfg]
+
+# MB9BF566 M/N/R have 32 KB SRAM0
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x8000
+}
+
+$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm4_s6e2cc.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm4_s6e2cc.cfg
new file mode 100644
index 0000000..7417d38
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/fm4_s6e2cc.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion FM4 S6E2CC (ARM Cortex-M4)
+#
+
+source [find target/fm4.cfg]
+
+# S6E2CC8 H/J/L have 96 KB SRAM0
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x18000
+}
+
+$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank ${_FLASHNAME}0 fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES
+flash bank ${_FLASHNAME}1 fm4 0x00100000 0 0 0 $_TARGETNAME $CHIPSERIES
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gd32e23x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gd32e23x.cfg
new file mode 100644
index 0000000..2504274
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gd32e23x.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for GigaDevice gd32e23x Cortex-M23 Series
+
+# https://www.gigadevice.com/microcontroller/gd32e230c8t6/
+
+#
+# gd32e23x devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME gd32e23x
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB (as found on some GD32E230s)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # this is the SW-DP tap id not the jtag tap id
+   set _CPUTAPID 0x0bf11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# SWD speed (may be updated to higher value in board config file)
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Debug clock enable
+	# RCU_APB2EN |= DBGMCUEN
+	mmw 0x40021018 0x00400000 0
+
+	# Stop watchdog counters during halt
+	# DBG_CTL0 |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD
+	mmw 0x40015804 0x00000307 0
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gd32vf103.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gd32vf103.cfg
new file mode 100644
index 0000000..77fdff7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gd32vf103.cfg
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# GigaDevice GD32VF103 target
+#
+# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
+#
+
+adapter speed 1000
+source [find mem_helper.tcl]
+
+transport select jtag
+
+reset_config srst_nogate
+
+# The smallest RAM size 6kB (GD32VF103C4/T4/R4)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1800
+}
+
+set _CHIPNAME gd32vf103
+# The vendor's configuration expects an ID of 0x1e200a6d, but this one is what
+# I have on my board (Sipeed Longan Nano, GD32VF103CBT6).
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME riscv set_enable_virt2phys off
+
+proc default_mem_access {} {
+	riscv set_mem_access progbuf
+}
+
+default_mem_access
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+# Address 0 is only aliased to main flash when the chip is not running its
+# built-in bootloader. When it is, it's instead aliased to a read only section
+# of flash at 0x1fffb000. However, we can't detect or dynamically switch this,
+# so just pretend it's always aliased to main flash. We need to tell OpenOCD
+# about this alias because otherwise we'll try to use software breakpoints on
+# code in flash, which don't work because flash mappings are read-only.
+flash bank $_CHIPNAME.flashalias virtual 0x0 0 0 0 $_TARGETNAME $_FLASHNAME
+
+# On this chip, ndmreset (the debug module bit that triggers a software reset)
+# doesn't work. So for JTAG connections without an SRST, we need to trigger a
+# reset manually. This is an undocumented reset sequence that's used by the
+# JTAG flashing script in the vendor-supplied GD32VF103 PlatformIO plugin:
+#
+#   https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2
+#
+$_TARGETNAME configure -event reset-assert {
+	set dmcontrol 		0x10
+	set dmcontrol_dmactive	[expr 1 << 0]
+	set dmcontrol_haltreq	[expr 1 << 31]
+
+	global _RESETMODE
+	global _TARGETNAME
+
+	# Halt the core so that we can write to memory. We do this first so
+	# that it doesn't clobber our dmcontrol configuration.
+	halt
+
+	# Set haltreq appropriately for the type of reset we're doing. This
+	# replicates what the generic RISC-V reset_assert() function would
+	# do if we weren't overriding it. The $_RESETMODE hack sucks, but
+	# it's the least invasive way to determine whether we need to halt,
+	# and psoc6.cfg already uses the same trick. (reset_deassert(), which
+	# does run, also does this, but at that point it may be too late: the
+	# reset has already been triggered, so there's a race between it and
+	# the haltreq write.)
+	#
+	# If we didn't override the generic handler, we'd actually still have
+	# to do this: the default handler sets ndmreset, which prevents memory
+	# access even though it doesn't actually trigger a reset on this chip.
+	# So we'd need to unset it here, which involves a write to dmcontrol,
+	# Since haltreq is write-only and there's no way to leave it unchanged,
+	# we'd have to figure out its proper value anyway.
+	set val $dmcontrol_dmactive
+	if {$_RESETMODE ne "run"} {
+		set val [expr $val | $dmcontrol_haltreq]
+	}
+	$_TARGETNAME riscv dmi_write $dmcontrol $val
+
+	# Unlock 0xe0042008 so that the next write triggers a reset
+	$_TARGETNAME mww 0xe004200c 0x4b5a6978
+
+	# We need to trigger the reset using abstract memory access, since
+	# progbuf access tries to read a status code out of a core register
+	# after the write happens, which fails when the core is in reset.
+	riscv set_mem_access abstract
+
+	# Go!
+	$_TARGETNAME mww 0xe0042008 0x1
+
+	# Put the memory access mode back to what it was.
+	default_mem_access
+}
+
+# Capture the mode of a given reset so that we can use it later in the
+# reset-assert handler.
+proc init_reset { mode } {
+	global _RESETMODE
+	set _RESETMODE $mode
+
+	if {[using_jtag]} {
+		jtag arp_init-reset
+	}
+}
+
+# On this chip, ndmreset (the debug module bit that triggers a software reset)
+# doesn't work. So for JTAG connections without an SRST, we need to trigger a
+# reset manually. This is an undocumented reset sequence that's used by the
+# JTAG flashing script in the vendor-supplied GD32VF103 PlatformIO plugin:
+#
+#   https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2
+#
+$_TARGETNAME configure -event reset-assert {
+	set dmcontrol 		0x10
+	set dmcontrol_dmactive	[expr {1 << 0}]
+	set dmcontrol_ackhavereset [expr {1 << 28}]
+	set dmcontrol_haltreq	[expr {1 << 31}]
+
+	global _RESETMODE
+
+	# If hardware NRST signal is connected and configured (reset_config srst_only)
+	# the device has been recently reset in 'jtag arp_init-reset', therefore
+	# DM_DMSTATUS_ANYHAVERESET reads 1.
+	# The following 'halt' command checks this status bit
+	# and shows 'Hart 0 unexpectedly reset!' if set.
+	# Prevent this message by sending an acknowledge first.
+	set val [expr {$dmcontrol_dmactive | $dmcontrol_ackhavereset}]
+	riscv dmi_write $dmcontrol $val
+
+	# Halt the core so that we can write to memory. We do this first so
+	# that it doesn't clobber our dmcontrol configuration.
+	halt
+
+	# Set haltreq appropriately for the type of reset we're doing. This
+	# replicates what the generic RISC-V reset_assert() function would
+	# do if we weren't overriding it. The $_RESETMODE hack sucks, but
+	# it's the least invasive way to determine whether we need to halt.
+	#
+	# If we didn't override the generic handler, we'd actually still have
+	# to do this: the default handler sets ndmreset, which prevents memory
+	# access even though it doesn't actually trigger a reset on this chip.
+	# So we'd need to unset it here, which involves a write to dmcontrol,
+	# Since haltreq is write-only and there's no way to leave it unchanged,
+	# we'd have to figure out its proper value anyway.
+	set val $dmcontrol_dmactive
+	if {$_RESETMODE ne "run"} {
+		set val [expr {$val | $dmcontrol_haltreq}]
+	}
+	riscv dmi_write $dmcontrol $val
+
+	# Unlock 0xe0042008 so that the next write triggers a reset
+	mww 0xe004200c 0x4b5a6978
+
+	# We need to trigger the reset using abstract memory access, since
+	# progbuf access tries to read a status code out of a core register
+	# after the write happens, which fails when the core is in reset.
+	riscv set_mem_access abstract
+
+	# Go!
+	mww 0xe0042008 0x1
+
+	# Put the memory access mode back to what it was.
+	default_mem_access
+}
+
+# Capture the mode of a given reset so that we can use it later in the
+# reset-assert handler.
+proc init_reset { mode } {
+	global _RESETMODE
+	set _RESETMODE $mode
+
+	if {[using_jtag]} {
+		jtag arp_init-reset
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gd32vw55x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gd32vw55x.cfg
new file mode 100644
index 0000000..b44aab9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gd32vw55x.cfg
@@ -0,0 +1,35 @@
+#
+# GigaDevice GD32VW55x target
+#
+#
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10307a6d
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 20480 -work-area-backup 0
+
+
+# Work-area is a space in RAM used for flash programming
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x5000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME gd32vw55x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+riscv set_reset_timeout_sec 1
+init
+
+halt
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/geehy/apm32f0x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/geehy/apm32f0x.cfg
new file mode 100644
index 0000000..502c092
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/geehy/apm32f0x.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F0x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F0x devices support SWD transport only.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f0x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 1 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/geehy/apm32f1x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/geehy/apm32f1x.cfg
new file mode 100644
index 0000000..dc42e06
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/geehy/apm32f1x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F1x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F1x devices support JTAG and SWD transport.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f1x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/geehy/apm32f4x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/geehy/apm32f4x.cfg
new file mode 100644
index 0000000..3ed58d1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/geehy/apm32f4x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F4x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F4x devices support JTAG and SWD transport.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f4x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+     set _CPUTAPID 0x4ba00477
+   } else {
+     set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if { [using_jtag] } {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gp326xxxa.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gp326xxxa.cfg
new file mode 100644
index 0000000..447460b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/gp326xxxa.cfg
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Support for General Plus GP326XXXA chips
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME gp326xxxa
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4f1f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Use internal SRAM as a work area
+$_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0
+
+# The chip has both lines connected together
+reset_config trst_and_srst srst_pulls_trst
+# This delay is needed otherwise communication with the target would
+# be unreliable
+adapter srst delay 100
+
+# Set the adapter speed ridiculously low just in case we are
+# running off of a 32kHz clock
+adapter speed 2
+
+proc gp32xxxa_halt_and_reset_control_registers {} {
+	# System control registers
+	set P_SYSTEM_CTRL_NEW       0xD0000008
+	set P_SYSTEM_CTRL           0xD000000C
+	set P_SYSTEM_CLK_EN0        0xD0000010
+	set P_SYSTEM_CLK_EN1        0xD0000014
+	set P_SYSTEM_RESET_FLAG     0xD0000018
+	set P_SYSTEM_CLK_CTRL       0xD000001C
+	set P_SYSTEM_LVR_CTRL       0xD0000020
+	set P_SYSTEM_WATCHDOG_CTRL  0xD0000024
+	set P_SYSTEM_PLLEN          0xD000005C
+
+	# Since we can't use SRST without pulling TRST
+	# we can't assume the state of the clock configuration
+	# or watchdog settings. So reset them before porceeding
+
+	# Set the adapter speed ridiculously low just in case we are
+	# running off of a 32kHz clock
+	adapter speed 2
+
+	# Disable any advanced features at this stage
+	arm7_9 dcc_downloads disable
+	arm7_9 fast_memory_access disable
+
+	# Do a "soft reset"
+	soft_reset_halt
+	# Reset all system control registers to their default "after-reset" values
+	mwh $P_SYSTEM_WATCHDOG_CTRL  0x0000
+	mwh $P_SYSTEM_LVR_CTRL       0x0000
+
+	mwh $P_SYSTEM_CTRL_NEW       0x0001
+	mwh $P_SYSTEM_CTRL           0x0001
+	# Clear all reset flags by writing 1's
+	mwh $P_SYSTEM_RESET_FLAG     0x001C
+
+	mwh $P_SYSTEM_CLK_CTRL       0x8000
+	mwh $P_SYSTEM_CLK_EN0        0xFFFF
+	mwh $P_SYSTEM_CLK_EN1        0xFFFF
+	mwh $P_SYSTEM_PLLEN          0x0010
+
+	# Unfortunately there's no register that would allow us to
+	# know if PLL is locked. So just wait for 100ms in hopes that
+	# it would be enough.
+	sleep 100
+
+	# Now that we know that we are running at 48Mhz
+	# Increase JTAG speed and enable speed optimization features
+	adapter speed 5000
+	arm7_9 dcc_downloads enable
+	arm7_9 fast_memory_access enable
+}
+
+$_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers }
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hi3798.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hi3798.cfg
new file mode 100644
index 0000000..722305d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hi3798.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hisilicon Hi3798 Target
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME hi3798
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x5ba00477
+}
+
+# declare the one JTAG tap to access the DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+# declare the 4 main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+set $_TARGETNAME.cti(0) 0x80020000
+set $_TARGETNAME.cti(1) 0x80120000
+set $_TARGETNAME.cti(2) 0x80220000
+set $_TARGETNAME.cti(3) 0x80320000
+
+set _cores 4
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        #set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hi6220.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hi6220.cfg
new file mode 100644
index 0000000..5b03899
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hi6220.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hisilicon Hi6220 Target
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME hi6220
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4ba00477
+}
+
+# declare the one JTAG tap to access the DAP
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# declare the 8 main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+set $_TARGETNAME.cti(0) 0x80198000
+set $_TARGETNAME.cti(1) 0x80199000
+set $_TARGETNAME.cti(2) 0x8019A000
+set $_TARGETNAME.cti(3) 0x8019B000
+set $_TARGETNAME.cti(4) 0x801D8000
+set $_TARGETNAME.cti(5) 0x801D9000
+set $_TARGETNAME.cti(6) 0x801DA000
+set $_TARGETNAME.cti(7) 0x801DB000
+
+set _cores 8
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+cti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80003000
+
+# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin)
+target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+
+# declare the auxiliary Cortex-A7 core
+target create ${_TARGETNAME}.a7 cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hilscher_netx10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hilscher_netx10.cfg
new file mode 100644
index 0000000..054cac8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hilscher_netx10.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+#Hilscher netX 10 CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME netx10
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966021
+}
+
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# that TAP is associated with a target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hilscher_netx50.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hilscher_netx50.cfg
new file mode 100644
index 0000000..e8ba015
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hilscher_netx50.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+#Hilscher netX 50 CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME netx50
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966021
+}
+
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# that TAP is associated with a target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# On netX50 SDRAM is not accessible at offset 0xDEAD0-0xDEADF as it is busy from
+# DMA controller at init. This function will setup a dummy DMA to free this ares
+# and must be called before using SDRAM
+proc sdram_fix { } {
+
+  mww 0x1c005830 0x00000001
+
+  mww 0x1c005104 0xBFFFFFFC
+  mww 0x1c00510c 0x00480001
+  mww 0x1c005110 0x00000001
+
+  sleep 100
+
+  mww 0x1c00510c 0
+  mww 0x1c005110 0
+  mww 0x1c005830 0x00000000
+
+	puts "SDRAM Fix executed!"
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hilscher_netx500.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hilscher_netx500.cfg
new file mode 100644
index 0000000..d838a6b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/hilscher_netx500.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#Hilscher netX 500 CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME netx500
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926021
+}
+
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# that TAP is associated with a target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+proc mread32 {addr} {
+  return [read_memory $addr 32 1]
+}
+
+# This function must be called on netX100/500 right after halt
+# If it is called later the needed register cannot be written anymore
+proc sdram_fix { } {
+
+  set accesskey [mread32 0x00100070]
+  mww 0x00100070 $accesskey
+  mww 0x0010002c 0x00000001
+
+  if {[expr {[mread32 0x0010002c] & 0x07}] == 0x07} {
+	 puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!"
+  } else {
+	 puts "SDRAM Fix succeeded!"
+  }
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/icepick.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/icepick.cfg
new file mode 100644
index 0000000..e5d5706
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/icepick.cfg
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Copyright (C)   2011        by Karl Kurbjun
+# Copyright (C)   2009        by David Brownell
+#
+
+# Utilities for TI ICEpick-C/D used in most TI SoCs
+# Details about the ICEPick are available in the TRM for each SoC
+# and http://processors.wiki.ti.com/index.php/ICEPICK
+
+# create "constants"
+proc CONST { key } {
+
+	array set constant {
+		# define ICEPick instructions
+		IR_BYPASS   0x00
+		IR_ROUTER   0x02
+		IR_CONNECT  0x07
+		IF_BYPASS   0x3F
+	}
+	return $constant($key)
+}
+
+# Instruction to connect to the icepick module
+proc icepick_c_connect {jrc} {
+
+	# Send CONNECT instruction in IR state
+	irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
+
+	# Send write and connect key
+	drscan $jrc 8 0x89 -endstate DRPAUSE
+}
+
+# Instruction to disconnect to the icepick module
+proc icepick_c_disconnect {jrc} {
+
+	# Send CONNECT instruction in IR state
+	irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
+
+	# Send write and connect key
+	drscan $jrc 8 0x86 -endstate DRPAUSE
+}
+
+#
+# icepick_c_router:
+#  this function is for sending router commands
+# arguments are:
+#  jrc:        TAP name for the ICEpick
+#  rw:         read/write (0 for read, 1 for write)
+#  block:      icepick or DAP
+#  register:   which register to read/write
+#  payload:    value to read/write
+# this function is for sending router commands
+#
+proc icepick_c_router {jrc rw block register payload} {
+
+	set new_dr_value \
+		[expr { ( ($rw & 0x1) << 31)        | ( ($block & 0x7) << 28) | \
+				( ($register & 0xF) << 24)  | ( $payload & 0xFFFFFF ) } ]
+
+#	echo "\tNew router value:\t0x[format %x $new_dr_value]"
+
+	# select router
+	irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
+
+	# ROUTER instructions are 32 bits wide
+	set old_dr_value 0x[drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+#	echo "\tOld router value:\t0x[format %x $old_dr_value]"
+}
+
+# Configure the icepick control register
+proc icepick_c_setup {jrc} {
+
+	# send a router write, block is 0, register is 1, value is 0x2100
+	icepick_c_router $jrc 1 0x0 0x1 0x001000
+}
+
+# jrc	== TAP name for the ICEpick
+# port	== a port number, 0..15 for debug tap, 16..31 for test tap
+proc icepick_c_tapenable {jrc port} {
+
+	if { ($port >= 0) && ($port < 16) } {
+		# Debug tap"
+		set tap $port
+		set block 0x2
+	} elseif { $port < 32 } {
+		# Test tap
+		set tap [expr {$port - 16}]
+		set block 0x1
+	} else {
+		echo "ERROR: Invalid ICEPick C port number: $port"
+		return
+	}
+
+	# First CONNECT to the ICEPick
+#	echo "Connecting to ICEPick"
+	icepick_c_connect $jrc
+
+#	echo "Configuring the ICEpick"
+	icepick_c_setup $jrc
+
+	# NOTE: it's important not to enter RUN/IDLE state until
+	# done sending these instructions and data to the ICEpick.
+	# And never to enter RESET, which will disable the TAPs.
+
+	# first enable power and clock for TAP
+	icepick_c_router $jrc 1 $block $tap 0x110048
+
+	# TRM states that the register should be read back here, skipped for now
+
+	# enable debug "default" mode
+	icepick_c_router $jrc 1 $block $tap 0x112048
+
+	# TRM states that debug enable and debug mode should be read back and
+	# confirmed - skipped for now
+
+	# Finally select the tap
+	icepick_c_router $jrc 1 $block $tap 0x112148
+
+	# Enter the bypass state
+	irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
+	runtest 10
+}
+
+# jrc	== TAP name for the ICEpick
+# coreid== core id number 0..15 (not same as port number!)
+proc icepick_d_set_core_control {jrc coreid value } {
+	icepick_c_router $jrc 1 0x6 $coreid $value
+}
+
+# jrc	== TAP name for the ICEpick
+# port	== a port number, 0..15
+# Follow the sequence described in
+# http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
+proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
+
+	# First CONNECT to the ICEPick
+	icepick_c_connect $jrc
+	icepick_c_setup $jrc
+
+	# Select the port
+	icepick_c_router $jrc 1 0x2 $port 0x2108
+
+	# Set icepick core control for $coreid
+	icepick_d_set_core_control $jrc $coreid $value
+
+	# Enter the bypass state
+	irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE
+	runtest 10
+}
+
+# This function uses the ICEPick to send a warm system reset
+proc icepick_c_wreset {jrc} {
+
+	# send a router write, block is 0, register is 1, value is 0x2100
+	icepick_c_router $jrc 1 0x0 0x1 0x002101
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx.cfg
new file mode 100644
index 0000000..d76f60e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# utility fn's for Freescale i.MX series
+
+global TARGETNAME
+set TARGETNAME $_TARGETNAME
+
+# rewrite commands of the form below to arm11 mcr...
+#	Data.Set c15:0x042f %long 0x40000015
+proc setc15 {regs value} {
+	global TARGETNAME
+
+	echo [format "set p15 0x%04x, 0x%08x" $regs $value]
+
+	arm mcr 15 [expr {($regs>>12)&0x7}] [expr {($regs>>0)&0xf}] [expr {($regs>>4)&0xf}] [expr {($regs>>8)&0x7}] $value
+}
+
+
+proc imx3x_reset {} {
+	# this reset script comes from the Freescale PDK
+	#
+	# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
+
+	echo "Target Setup: initialize DRAM controller and peripherals"
+
+#	Data.Set c15:0x01 %long 0x00050078
+	setc15 0x01 0x00050078
+
+	echo "configuring CP15 for enabling the peripheral bus"
+#	Data.Set c15:0x042f %long 0x40000015
+	setc15 0x042f 0x40000015
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx21.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx21.cfg
new file mode 100644
index 0000000..7c9cca3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx21.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+#
+# Hmmm.... should srst_pulls_trst be used here like i.MX27???
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx21
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+
+# Note above there is 1 tap
+
+# The CPU tap
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0792611f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx25.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx25.cfg
new file mode 100644
index 0000000..ed94cc0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx25.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# imx25 config
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx25
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x1b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0x0f -expected-id $_ETBTAPID
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id 0x0
+
+if { [info exists SDMATAPID] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x0882301d
+}
+jtag newtap $_CHIPNAME sdma -irlen 5 -expected-id $_SDMATAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN \
+		-chain-position $_TARGETNAME
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx27.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx27.cfg
new file mode 100644
index 0000000..c79d85e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx27.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# page 3-34 of "MCIMC27 Multimedia Applications Processor Reference Manual, Rev 0.3"
+# SRST pulls TRST
+#
+# Without setting these options correctly you'll see all sorts
+# of weird errors, e.g. MOE=0xe, invalid cpsr values, reset
+# failing, etc.
+reset_config trst_and_srst srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx27
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+
+# Note above there are 2 taps
+
+# trace buffer
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x1b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
+
+# The CPU tap
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926121
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+# REVISIT what operating environment sets up this virtual address mapping?
+$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \
+	-work-area-size 0x8000 -work-area-backup 1
+# Internal to the chip, there is 45K of SRAM
+#
+
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx28.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx28.cfg
new file mode 100644
index 0000000..d52fc4e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx28.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# i.MX28 config file.
+# based off of the imx21.cfg file.
+
+reset_config trst_and_srst
+
+#jtag nTRST and nSRST delay
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx28
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+
+# Note above there is 1 tap
+
+# The CPU tap
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x079264f3
+}
+jtag newtap $_CHIPNAME cpu  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx31.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx31.cfg
new file mode 100644
index 0000000..10e9fef
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx31.cfg
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# imx31 config
+#
+
+reset_config trst_and_srst srst_gates_jtag
+
+adapter srst delay 5
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx31
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07b3601d
+}
+
+if { [info exists SDMATAPID] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x2190101d
+}
+
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x2b900f0f
+}
+
+#========================================
+
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
+
+# The "SDMA" - mart  controller debug tap
+# Based on some IO pins - this can be disabled & removed
+# See diagram: 6-14
+#   SIGNAL NAME:
+#    SJC_MOD - controls multiplexer - disables ARM1136
+#    SDMA_BYPASS - disables SDMA    -
+#
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+# No IDCODE for this TAP
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
+
+# Per section 40.17.1, table 40-85 the IR register is 4 bits
+# But this conflicts with Diagram 6-13, "3bits ir and drs"
+jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx35.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx35.cfg
new file mode 100644
index 0000000..fa173bb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx35.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# imx35 config
+#
+
+reset_config trst_and_srst srst_gates_jtag
+jtag_ntrst_delay 100
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx35
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07b3601d
+}
+
+if { [info exists SDMATAPID] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x0882601d
+}
+
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x2b900f0f
+}
+
+#========================================
+
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+# No IDCODE for this TAP
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0
+
+jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx51.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx51.cfg
new file mode 100644
index 0000000..fc3dfa9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx51.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Freescale i.MX51
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx51
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x1ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+        -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
+
+# SJC
+if { [info exists SJC_TAPID] } {
+   set _SJC_TAPID SJC_TAPID
+} else {
+   set _SJC_TAPID 0x0190c01d
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
+        -expected-id $_SJC_TAPID -ignore-version
+
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
+
+proc imx51_dbginit {target} {
+     # General Cortex-A8 debug initialisation
+     cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx53.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx53.cfg
new file mode 100644
index 0000000..855a6ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx53.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Freescale i.MX53
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx53
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x1ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+        -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
+
+# SJC
+if { [info exists SJC_TAPID] } {
+   set _SJC_TAPID SJC_TAPID
+} else {
+   set _SJC_TAPID 0x0190d01d
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
+        -expected-id $_SJC_TAPID -ignore-version
+
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
+
+proc imx53_dbginit {target} {
+     # General Cortex-A8 debug initialisation
+     cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-assert-post "imx53_dbginit $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx6.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx6.cfg
new file mode 100644
index 0000000..c9b6acf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx6.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale i.MX6 series
+#
+# Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
+#
+# Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx6
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
+
+# System JTAG Controller
+
+# List supported SJC TAPIDs from imx reference manuals:
+set _SJC_TAPID_6Q   0x0191c01d
+set _SJC_TAPID_6D   0x0191e01d
+set _SJC_TAPID_6QP  0x3191c01d
+set _SJC_TAPID_6DP  0x3191d01d
+set _SJC_TAPID_6DL  0x0891a01d
+set _SJC_TAPID_6S   0x0891b01d
+set _SJC_TAPID_6SL  0x0891f01d
+set _SJC_TAPID_6SLL 0x088c201d
+
+# Allow external override of the first SJC TAPID
+if { [info exists SJC_TAPID] } {
+    set _SJC_TAPID $SJC_TAPID
+} else {
+    set _SJC_TAPID $_SJC_TAPID_6Q
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
+        -ignore-version \
+        -expected-id $_SJC_TAPID \
+        -expected-id $_SJC_TAPID_6QP \
+        -expected-id $_SJC_TAPID_6DP \
+        -expected-id $_SJC_TAPID_6D \
+        -expected-id $_SJC_TAPID_6DL \
+        -expected-id $_SJC_TAPID_6S \
+        -expected-id $_SJC_TAPID_6SL \
+        -expected-id $_SJC_TAPID_6SLL
+
+# GDB target: Cortex-A9, using DAP, configuring only one core
+# Base addresses of cores:
+# core 0  -  0x82150000
+# core 1  -  0x82152000
+# core 2  -  0x82154000
+# core 3  -  0x82156000
+set _TARGETNAME $_CHIPNAME.cpu.0
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x82150000
+
+# some TCK cycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
+
+proc imx6_dbginit {target} {
+        # General Cortex-A8/A9 debug initialisation
+        cortex_a dbginit
+}
+
+# Slow speed to be sure it will work
+adapter speed 1000
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
+
+$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx6sx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx6sx.cfg
new file mode 100644
index 0000000..3d4240a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx6sx.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale i.MX6SoloX
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME imx6sx
+}
+
+# 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4
+
+jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
+
+# System JTAG Controller
+if { [info exists SJC_TAPID] } {
+    set _SJC_TAPID $SJC_TAPID
+} else {
+    set _SJC_TAPID 0x0891c01d
+}
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
+        -expected-id $_SJC_TAPID -ignore-version
+
+# Cortex-A9 (boot core)
+target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \
+        -coreid 0 -dbgbase 0x82150000
+
+# Cortex-M4 (default off)
+target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \
+        -ap-num 0 -defer-examine
+
+# AHB mem-ap target
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0
+
+# Default target is Cortex-A9
+targets $_CHIPNAME.cpu_a9
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx6ul.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx6ul.cfg
new file mode 100644
index 0000000..354745e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx6ul.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale i.MX6UltraLite series: 6UL 6ULL 6ULZ
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME imx6ul
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
+
+# System JTAG Controller
+set _SJC_TAPID_6UL  0x0891d01d
+set _SJC_TAPID_6ULL 0x0891e01d
+set _SJC_TAPID_6ULZ 0x1891e01d
+
+# Allow external override of the first SJC TAPID
+if { [info exists SJC_TAPID] } {
+    set _SJC_TAPID $SJC_TAPID
+} else {
+    set _SJC_TAPID $_SJC_TAPID_6UL
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
+        -ignore-version \
+        -expected-id $_SJC_TAPID \
+        -expected-id $_SJC_TAPID_6ULL \
+        -expected-id $_SJC_TAPID_6ULZ \
+
+# Create DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Main AHB bus
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# Cortex-A7 single core
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x82130000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx7.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx7.cfg
new file mode 100644
index 0000000..bd9e3dd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx7.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx7
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+#
+# Cortex-A7 target
+#
+# GDB target: Cortex-A7, using DAP, configuring only one core
+# Base addresses of cores:
+# core 0  -  0x80070000
+# core 1  -  0x80072000
+set _TARGETNAME $_CHIPNAME.cpu_a7
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x80070000
+
+target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap \
+        -coreid 1 -dbgbase 0x80072000 -defer-examine
+#
+# Cortex-M4 target
+#
+set _TARGETNAME_2 $_CHIPNAME.cpu_m4
+target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.dap -ap-num 4 \
+        -defer-examine
+
+#
+# AHB mem-ap target
+#
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+targets $_TARGETNAME.0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx7ulp.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx7ulp.cfg
new file mode 100644
index 0000000..1467f7c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx7ulp.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP i.MX7ULP: Cortex-A7 + Cortex-M4
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME imx7ulp
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    # TAPID is from FreeScale!
+    set _DAP_TAPID 0x188e101d
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Cortex-A7
+target create $_CHIPNAME.cpu_a7 cortex_a -dap $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x80030000
+
+# Cortex-M4
+# Boots by default so don't defer examination
+target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap -ap-num 3
+
+# AHB main soc bus
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# Default is Cortex-A7
+targets $_CHIPNAME.cpu_a7
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx8m.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx8m.cfg
new file mode 100644
index 0000000..6938090
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx8m.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for NXP i.MX8M family of SoCs
+#
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx8m
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 1
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+# the DAP tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+
+set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -baseaddr [lindex $CTIBASE $_core]
+
+    set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command $_TARGETNAME.$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp $_TARGETNAME.$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+# declare the auxiliary Cortex-M4 core on AP #4
+target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \
+               -defer-examine
+
+# AHB-AP for direct access to soc bus
+target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# default target is A53 core 0
+targets $_TARGETNAME.0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx8mp.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx8mp.cfg
new file mode 100644
index 0000000..bddbcfd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx8mp.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for NXP i.MX8M Plus SoCs
+#
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx8m
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 1
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+# the DAP tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+
+set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -baseaddr [lindex $CTIBASE $_core]
+
+    target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core
+}
+
+# declare the auxiliary Cortex-M7 core on AP #4
+target create ${_CHIPNAME}.m7 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4
+
+# AHB-AP for direct access to soc bus
+target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# default target is A53 core 0
+targets $_TARGETNAME.0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx8qm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx8qm.cfg
new file mode 100644
index 0000000..33f9ca1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/imx8qm.cfg
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP i.MX8QuadMax
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx8qm
+}
+
+# CoreSight Debug Access Port (DAP)
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    # TAPID is from FreeScale!
+    set _DAP_TAPID 0x1890101d
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# AXI: Main SOC bus on AP #0
+target create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# 4x Cortex-A53 on AP #6
+set _A53_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set _A53_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+cti create $_CHIPNAME.a53_cti.0 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 0]
+cti create $_CHIPNAME.a53_cti.1 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 1]
+cti create $_CHIPNAME.a53_cti.2 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 2]
+cti create $_CHIPNAME.a53_cti.3 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 3]
+target create $_CHIPNAME.a53.0 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a53_cti.0 -dbgbase [lindex $_A53_DBGBASE 0]
+target create $_CHIPNAME.a53.1 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a53_cti.1 -dbgbase [lindex $_A53_DBGBASE 1] -defer-examine
+target create $_CHIPNAME.a53.2 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a53_cti.2 -dbgbase [lindex $_A53_DBGBASE 2] -defer-examine
+target create $_CHIPNAME.a53.3 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a53_cti.3 -dbgbase [lindex $_A53_DBGBASE 3] -defer-examine
+
+# 2x Cortex-A72 on AP #6
+set _A72_DBGBASE {0x80210000 0x80310000}
+set _A72_CTIBASE {0x80220000 0x80220000}
+
+cti create $_CHIPNAME.a72_cti.0 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 0]
+cti create $_CHIPNAME.a72_cti.1 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 1]
+target create $_CHIPNAME.a72.0 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a72_cti.0 -dbgbase [lindex $_A72_DBGBASE 0] -defer-examine
+target create $_CHIPNAME.a72.1 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a72_cti.1 -dbgbase [lindex $_A72_DBGBASE 1] -defer-examine
+
+# All Cortex-A in SMP
+target smp \
+        $_CHIPNAME.a53.0 \
+        $_CHIPNAME.a53.1 \
+        $_CHIPNAME.a53.2 \
+        $_CHIPNAME.a53.3 \
+        $_CHIPNAME.a72.0 \
+        $_CHIPNAME.a72.1
+
+# SCU: Cortex-M4 core
+# always running imx SC firmware
+target create ${_CHIPNAME}.scu cortex_m -dap ${_CHIPNAME}.dap -ap-num 1
+
+# AHB from SCU perspective
+target create ${_CHIPNAME}.scu_ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 4
+
+# Cortex-M4 M4_0 core on AP #2 (default off)
+target create ${_CHIPNAME}.m4_0 cortex_m -dap ${_CHIPNAME}.dap -ap-num 2 \
+        -defer-examine
+
+# Cortex-M4 M4_1 core on AP #3 (default off)
+target create ${_CHIPNAME}.m4_1 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3 \
+        -defer-examine
+
+# Debug APB bus
+target create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 6
+
+# Default target is boot core a53.0
+targets $_CHIPNAME.a53.0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/infineon/tle987x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/infineon/tle987x.cfg
new file mode 100644
index 0000000..ac3db6c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/infineon/tle987x.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon TLE987x family (Arm Cortex-M3 @ up to 40 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME tle987x
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x2BA01477
+}
+
+if { [using_jtag] } {
+	# JTAG not supported, only SWD
+	set _CPU_TAPID 0
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME dap -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/is5114.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/is5114.cfg
new file mode 100644
index 0000000..d0b1d92
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/is5114.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Insilica IS-5114
+# AKA: Atmel AT76C114 - an ARM946 chip
+# ATMEL sold his product line to Insilica...
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME is5114
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a little endian
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # Force an error until we get a good number.
+   set _CPUTAPID 0xffffffff
+}
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+adapter speed 16
+
+reset_config trst_and_srst
+
+# Do not specify a tap id here...
+jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1
+# This is the "arm946" chip.
+jtag newtap $_CHIPNAME cpu      -irlen 4 -ircapture 0x0e -irmask 0xf
+jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
+
+
+#arm946e-s and
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	adapter speed 3000
+}
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ixp42x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ixp42x.cfg
new file mode 100644
index 0000000..5c8e903
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ixp42x.cfg
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#xscale ixp42x CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME ixp42x
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a bigendian
+   set _ENDIAN big
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x19274013
+}
+set _CPUTAPID2 0x19275013
+set _CPUTAPID3 0x19277013
+set _CPUTAPID4 0x29274013
+set _CPUTAPID5 0x29275013
+set _CPUTAPID6 0x29277013
+
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
+
+
+# register constants for IXP42x SDRAM controller
+global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
+global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
+set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD	0x0000
+set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD	0x0001
+
+global IXP42x_SDRAM_CL3
+global IXP42x_SDRAM_CL2
+set IXP42x_SDRAM_CL3			0x0008
+set IXP42x_SDRAM_CL2			0x0000
+
+global IXP42x_SDRAM_8MB_2Mx32_1BANK
+global IXP42x_SDRAM_16MB_2Mx32_2BANK
+global IXP42x_SDRAM_16MB_4Mx16_1BANK
+global IXP42x_SDRAM_32MB_4Mx16_2BANK
+global IXP42x_SDRAM_32MB_8Mx16_1BANK
+global IXP42x_SDRAM_64MB_8Mx16_2BANK
+global IXP42x_SDRAM_64MB_16Mx16_1BANK
+global IXP42x_SDRAM_128MB_16Mx16_2BANK
+global IXP42x_SDRAM_128MB_32Mx16_1BANK
+global IXP42x_SDRAM_256MB_32Mx16_2BANK
+
+set IXP42x_SDRAM_8MB_2Mx32_1BANK	0x0030
+set IXP42x_SDRAM_16MB_2Mx32_2BANK	0x0031
+set IXP42x_SDRAM_16MB_4Mx16_1BANK	0x0032
+set IXP42x_SDRAM_32MB_4Mx16_2BANK	0x0033
+set IXP42x_SDRAM_32MB_8Mx16_1BANK	0x0010
+set IXP42x_SDRAM_64MB_8Mx16_2BANK	0x0011
+set IXP42x_SDRAM_64MB_16Mx16_1BANK	0x0012
+set IXP42x_SDRAM_128MB_16Mx16_2BANK	0x0013
+set IXP42x_SDRAM_128MB_32Mx16_1BANK	0x0014
+set IXP42x_SDRAM_256MB_32Mx16_2BANK	0x0015
+
+
+# helper function to init SDRAM on IXP42x.
+# SDRAM_CFG: one of IXP42X_SDRAM_xxx
+# REFRESH: refresh counter reload value (integer)
+# CASLAT: 2 or 3
+proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
+
+    switch $CASLAT {
+	2 {
+	    set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL2} ]
+	    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
+	}
+	3 {
+	    set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL3} ]
+	    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
+	}
+	default { error [format "unsupported cas latency \"%s\" " $CASLAT] }
+    }
+    echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH]
+
+    mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3
+    mww 0xCC000004          0 ;# disable refresh
+    mww 0xCC000008          3 ;# NOP
+    sleep 100
+    mww 0xCC000004   $REFRESH ;# set refresh counter
+    mww 0xCC000008          2 ;# Precharge All Banks
+    sleep 100
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008    $CASCMD ;# Mode Select CL2/CL3
+}
+
+proc ixp42x_set_bigendian { } {
+    reg XSCALE_CTRL 0xF8
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/k1921vk01t.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/k1921vk01t.cfg
new file mode 100644
index 0000000..a9500ef
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/k1921vk01t.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# K1921VK01T
+# http://niiet.ru/chips/nis?id=354
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME k1921vk01t
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      # SWD IDCODE
+      set _CPUTAPID 0x2ba01477
+   }
+}
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME
+
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/k40.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/k40.cfg
new file mode 100644
index 0000000..33e8235
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/k40.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis K40 devices
+#
+
+set CHIPNAME k40
+source [find target/kx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/k60.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/k60.cfg
new file mode 100644
index 0000000..3b89102
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/k60.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis K60 devices
+#
+
+set CHIPNAME k60
+source [find target/kx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ke0x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ke0x.cfg
new file mode 100644
index 0000000..b357767
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ke0x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis KE0x and KEAx series devices
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME ke
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+
+   # It is important that "kinetis_ke mdm check_security" is called for
+   # 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start'
+   # causes "kinetis_ke mdm check_security" to fail the first time openocd
+   # calls it when it tries to connect after the CPU has been power-cycled.
+   $_CHIPNAME.cpu configure -event examine-end {
+      kinetis_ke mdm check_security
+   }
+
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ke1xf.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ke1xf.cfg
new file mode 100644
index 0000000..86a1f3b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ke1xf.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP (Freescale) Kinetis KE1xF devices
+#
+
+set CHIPNAME ke
+
+source [find target/kx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ke1xz.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ke1xz.cfg
new file mode 100644
index 0000000..9e91542
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ke1xz.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP (Freescale) Kinetis KE1xZ devices
+#
+
+set CHIPNAME ke
+
+source [find target/klx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/kl25.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/kl25.cfg
new file mode 100644
index 0000000..916edf6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/kl25.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis KL25 devices
+#
+
+set CHIPNAME kl25
+source [find target/klx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/kl46.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/kl46.cfg
new file mode 100644
index 0000000..bf6b244
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/kl46.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis KL46 devices
+#
+
+set CHIPNAME kl46
+source [find target/klx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/klx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/klx.cfg
new file mode 100644
index 0000000..cd236b3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/klx.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP (former Freescale) Kinetis KL series devices
+# Also used for Cortex-M0+ equipped members of KVx and KE1xZ series
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME klx
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1KiB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.pflash
+flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
+kinetis create_banks
+
+# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
+# specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;
+# Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {[using_hla]} {
+   echo ""
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions."
+   echo " A high level adapter (like a ST-Link) you are currently using cannot access"
+   echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your"
+   echo " configuration. Also security locked state of the device will not be reported."
+   echo ""
+   echo " Be very careful as you can lock the device though there is no way to unlock"
+   echo " it without mass erase. Don't set write protection on the first block."
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo ""
+} else {
+   # Detect secured MCU
+   $_TARGETNAME configure -event examine-fail {
+      kinetis mdm check_security
+   }
+
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+# Disable watchdog not to disturb OpenOCD algorithms running on MCU
+# (e.g. armv7m_checksum_memory() in verify_image)
+# Flash driver also disables watchdog before FTFA flash programming.
+$_TARGETNAME configure -event reset-init {
+   kinetis disable_wdog
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ks869x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ks869x.cfg
new file mode 100644
index 0000000..06e710b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ks869x.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ARM920T CPU
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME ks869x
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set  _CPUTAPID $CPUTAPID
+} else {
+   set  _CPUTAPID 0x00922f0f
+}
+
+adapter speed 6000
+
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/kx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/kx.cfg
new file mode 100644
index 0000000..c87116b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/kx.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP (former Freescale) Kinetis Kx series devices
+# Also used for Cortex-M4 equipped members of KVx and KE1xF series
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME kx
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.pflash
+flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
+kinetis create_banks
+
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {[using_hla]} {
+   echo ""
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions."
+   echo " A high level adapter (like a ST-Link) you are currently using cannot access"
+   echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your"
+   echo " configuration. Also security locked state of the device will not be reported."
+   echo " Expect problems connecting to a blank device without boot ROM."
+   echo ""
+   echo " Be very careful as you can lock the device though there is no way to unlock"
+   echo " it without mass erase. Don't set write protection on the first block."
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo ""
+} else {
+   # Detect secured MCU or boot lock-up in RESET/WDOG loop
+   $_TARGETNAME configure -event examine-fail {
+      kinetis mdm check_security
+   }
+   # During RESET/WDOG loop the target is sometimes falsely examined
+   $_TARGETNAME configure -event examine-end {
+      kinetis mdm check_security
+   }
+
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+# Disable watchdog not to disturb OpenOCD algorithms running on MCU
+# (e.g. armv7m_checksum_memory() in verify_image)
+# Flash driver also disables watchdog before FTFA flash programming.
+$_TARGETNAME configure -event reset-init {
+   kinetis disable_wdog
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc11xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc11xx.cfg
new file mode 100644
index 0000000..d288e2a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc11xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC11xx Cortex-M0 with at least 1kB SRAM
+set CHIPNAME lpc11xx
+set CHIPSERIES lpc1100
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x400
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc12xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc12xx.cfg
new file mode 100644
index 0000000..ace5e06
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc12xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC12xx Cortex-M0 with at least 4kB SRAM
+set CHIPNAME lpc12xx
+set CHIPSERIES lpc1200
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x1000
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc13xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc13xx.cfg
new file mode 100644
index 0000000..5ac29d3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc13xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC13xx Cortex-M3 with at least 4kB SRAM
+set CHIPNAME lpc13xx
+set CHIPSERIES lpc1300
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x1000
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc17xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc17xx.cfg
new file mode 100644
index 0000000..35d8bad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc17xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC17xx Cortex-M3 with at least 8kB SRAM
+set CHIPNAME lpc17xx
+set CHIPSERIES lpc1700
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x2000
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc1850.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc1850.cfg
new file mode 100644
index 0000000..6dd1ab7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc1850.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/swj-dp.tcl]
+
+adapter speed 500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME lpc1850
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+#
+# M3 JTAG mode TAP
+#
+if { [info exists M3_JTAG_TAPID] } {
+   set _M3_JTAG_TAPID $M3_JTAG_TAPID
+} else {
+   set _M3_JTAG_TAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.m3
+
+set _TARGETNAME $_CHIPNAME.m3
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc1xxx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc1xxx.cfg
new file mode 100644
index 0000000..70d26d2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc1xxx.cfg
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
+#
+# !!!!!!
+#
+# This file should not be included directly, rather by the lpc11xx.cfg,
+# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
+# appropriate values.
+#
+# !!!!!!
+
+# LPC8xx chips support only SWD transport.
+# LPC11xx chips support only SWD transport.
+# LPC12xx chips support only SWD transport.
+# LPC11Uxx chips support only SWD transports.
+# LPC13xx chips support only SWD transports.
+# LPC17xx chips support both JTAG and SWD transports.
+# LPC40xx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
+}
+
+if { [info exists CHIPSERIES] } {
+	# Validate chip series is supported
+	if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700"  && $CHIPSERIES != "lpc4000" } {
+		error "Unsupported LPC1xxx chip series specified."
+	}
+	set _CHIPSERIES $CHIPSERIES
+} else {
+	error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
+}
+
+# After reset, the chip is clocked by an internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK] } {
+	# Allow user override
+	set _CCLK $CCLK
+} else {
+	# LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
+	if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
+		set _CCLK 12000
+	} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+		set _CCLK 4000
+	}
+}
+
+if { [info exists CPUTAPID] } {
+	# Allow user override
+	set _CPUTAPID $CPUTAPID
+} else {
+	# LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
+	if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
+		set _CPUTAPID 0x0bb11477
+	} elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+		if { [using_jtag] } {
+			set _CPUTAPID 0x4ba00477
+		} {
+			set _CPUTAPID 0x2ba01477
+		}
+	}
+}
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
+
+# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
+# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
+# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
+# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
+# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
+# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
+#
+# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
+# (same cmd51 destination boundary alignment, and all three support 256 byte
+# transfers).
+#
+# flash bank  lpc2000   0 0    [calc checksum] [iap entry]
+set _IAP_ENTRY 0
+if { [info exists IAP_ENTRY] } {
+	set _IAP_ENTRY $IAP_ENTRY
+}
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
+	auto $_CCLK calc_checksum $_IAP_ENTRY
+
+if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
+	# Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
+	# Bit Symbol Value Description
+	# 1:0 MAP          System memory remap
+	#            0x0   Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
+	#            0x1   User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
+	#            0x2   User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
+	# 31:2 -     -     Reserved.
+	$_TARGETNAME configure -event reset-init {
+		mww 0x40048000 0x02
+	}
+} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+	# Bit Symbol Value Description Reset
+	# value
+	# 0 MAP Memory map control. 0
+	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+	# 1 User mode. The on-chip Flash memory is mapped to address 0.
+	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+	#
+	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+	$_TARGETNAME configure -event reset-init {
+		mww 0x400FC040 0x01
+	}
+}
+
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+adapter speed 10
+
+# delays on reset lines
+adapter srst delay 200
+if {[using_jtag]} {
+ jtag_ntrst_delay 200
+}
+
+# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
+# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
+# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
+# LPC40xx (Cortex-M4F core) support SYSRESETREQ
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2103.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2103.cfg
new file mode 100644
index 0000000..c49b0e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2103.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2103 ARM7TDMI-S with 32kB flash and 8kB SRAM, clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2103 {core_freq_khz adapter_freq_khz} {
+	# 32kB flash and 8kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2103 0x4f1f0f0f 0x8000 lpc2000_v2 0x2000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2103  
+	setup_lpc2103 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2124.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2124.cfg
new file mode 100644
index 0000000..053ebeb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2124.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2124 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2124 {core_freq_khz adapter_freq_khz} {
+	# 256kB flash and 16kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2124 0x4f1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2124  
+	setup_lpc2124 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2129.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2129.cfg
new file mode 100644
index 0000000..88ee20f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2129.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2129 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2129 {core_freq_khz adapter_freq_khz} {
+	# 256kB flash and 16kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2129 0xcf1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2129  
+	setup_lpc2129 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2148.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2148.cfg
new file mode 100644
index 0000000..fda622f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2148.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2148 ARM7TDMI-S with 512kB flash (12kB used by bootloader) and 40kB SRAM (8kB for USB DMA), clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2148 {core_freq_khz adapter_freq_khz} {
+	# 500kB flash and 32kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2148 "0x3f0f0f0f 0x4f1f0f0f" 0x7d000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2148  
+	setup_lpc2148 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2294.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2294.cfg
new file mode 100644
index 0000000..7537a65
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2294.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2294 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
+	# 256kB flash and 16kB SRAM
+	# setup_lpc2xxx       
+
+	# !! TAPID unknown !!
+	setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2294  
+	setup_lpc2294 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2378.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2378.cfg
new file mode 100644
index 0000000..59e41c9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2378.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2378 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 56kB SRAM (16kB for ETH, 8kB for DMA), clocked with 4MHz internal oscillator
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2378 {core_freq_khz adapter_freq_khz} {
+	# 504kB flash and 32kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2378 0x4f1f0f0f 0x7e000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 4MHz internal oscillator
+	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2378  
+	setup_lpc2378 4000 500
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2460.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2460.cfg
new file mode 100644
index 0000000..59b6466
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2460.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2460 ARM7TDMI-S with 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2460 {core_freq_khz adapter_freq_khz} {
+	# 64kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2460 0x4f1f0f0f 0 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 4MHz internal oscillator
+	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2460  
+	setup_lpc2460 4000 500
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2478.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2478.cfg
new file mode 100644
index 0000000..e4fd49d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2478.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2478 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2478 {core_freq_khz adapter_freq_khz} {
+	# 504kB flash and 64kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2478 0x4f1f0f0f 0x7e000 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 4MHz internal oscillator
+	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2478  
+	setup_lpc2478 4000 500
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2900.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2900.cfg
new file mode 100644
index 0000000..67e3c92
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2900.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME lpc2900
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x0596802B
+}
+
+if { [info exists HAS_ETB] } {
+} else {
+    # Set default (no ETB).
+    # Show a warning, because this should have been configured explicitly.
+    set HAS_ETB 0
+    # TODO: warning?
+}
+
+if { [info exists ETBTAPID] } {
+    set _ETBTAPID $ETBTAPID
+} else {
+    set _ETBTAPID 0x1B900F0F
+}
+
+# TRST and SRST both exist, and can be controlled independently
+reset_config trst_and_srst separate
+
+# Define the _TARGETNAME
+set _TARGETNAME $_CHIPNAME.cpu
+
+# Include the ETB tap controller if asked for.
+# Has to be done manually for newer devices (not an "old" LPC2917/2919).
+if { $HAS_ETB == 1 } {
+    # Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
+    set HAS_ETB 0
+
+    # Add the ETB tap controller and the ARM9 core debug tap
+    jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
+    jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+    # Create the ".cpu" target
+    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
+
+    # Configure ETM and ETB
+    etm config $_TARGETNAME 8 normal full etb
+    etb config $_TARGETNAME $_CHIPNAME.etb
+
+} else {
+    # Add the ARM9 core debug tap
+    jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+    # Create the ".cpu" target
+    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
+}
+
+arm7_9 dbgrq enable
+arm7_9 dcc_downloads enable
+
+# Flash bank configuration:
+# Flash: flash bank lpc2900 0 0 0 0  
+# Flash base address, total flash size, and number of sectors are all configured automatically.
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2xxx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2xxx.cfg
new file mode 100644
index 0000000..bc5e600
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc2xxx.cfg
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Common setup for the LPC2xxx parts
+
+# parameters:
+# - chip_name - name of the chip, e.g. lpc2103
+# - cputapids - TAP IDs of the core, should be quoted if more than one, e.g. 0x4f1f0f0f or "0x3f0f0f0f 0x4f1f0f0f"
+# - flash_size - size of on-chip flash (available for code, not including the bootloader) in bytes, e.g. 0x8000
+# - flash_variant - "type" of LPC2xxx device, lpc2000_v1 (LPC22xx and older LPC21xx) or lpc2000_v2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
+# - workarea_size - size of work-area in RAM for flashing procedures, must not exceed the size of RAM available at 0x40000000, e.g. 0x2000
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size core_freq_khz adapter_freq_khz} {
+	reset_config trst_and_srst
+
+	# reset delays
+	adapter srst delay 100
+	jtag_ntrst_delay 100
+
+	adapter speed $adapter_freq_khz
+
+	foreach i $cputapids {
+		append expected_ids "-expected-id " $i " "
+	}
+
+	eval "jtag newtap $chip_name cpu -irlen 4 -ircapture 0x1 -irmask 0xf $expected_ids"
+
+	global _TARGETNAME
+	set _TARGETNAME $chip_name.cpu
+	target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
+
+	$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size $workarea_size -work-area-backup 0
+
+	if { $flash_size > 0 } {
+		# flash bank  lpc2000   0 0    [calc checksum]
+		set _FLASHNAME $chip_name.flash
+		flash bank $_FLASHNAME lpc2000 0x0 $flash_size 0 0 $_TARGETNAME $flash_variant $core_freq_khz calc_checksum
+	}
+}
+
+proc init_targets {} {
+	# FIX!!! read out CPUTAPID here and choose right setup. In addition to the
+	# CPUTAPID some querying of the target would be required.
+	return -error "This is a generic LPC2xxx configuration file, use a specific target file."
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc3131.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc3131.cfg
new file mode 100644
index 0000000..09d698a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc3131.cfg
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    NXP lpc3131
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lpc3131
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# ARM926EJS core
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926f0f
+}
+
+# Scan Tap
+# Wired to separate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
+# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
+if { [info exists SJCTAPID] } {
+   set _SJCTAPID $SJCTAPID
+} else {
+   set _SJCTAPID 0x1541E02B
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+##################################################################
+# various symbol definitions, to avoid hard-wiring addresses
+##################################################################
+
+global lpc313x
+set lpc313x [ dict create ]
+
+# Physical addresses for controllers and memory
+dict set lpc313x sram0			0x11028000
+dict set lpc313x sram1			0x11040000
+dict set lpc313x uart			0x15001000
+dict set lpc313x cgu			0x13004000
+dict set lpc313x ioconfig		0x13003000
+dict set lpc313x sysconfig		0x13002800
+dict set lpc313x wdt			0x13002400
+
+##################################################################
+# Target configuration
+##################################################################
+
+adapter srst delay 1000
+jtag_ntrst_delay 0
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME invoke-event halted
+
+$_TARGETNAME configure -work-area-phys [dict get $lpc313x sram0] -work-area-size 0x30000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+	echo "\nRunning reset init script for LPC3131\n"
+	halt
+	wait_halt
+	reg cpsr 0xa00000d3	;#Supervisor mode
+	reg pc 0x11029000
+	poll
+	sleep 500
+}
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc3250.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc3250.cfg
new file mode 100644
index 0000000..244d981
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc3250.cfg
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# lpc3250 config
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lpc3250
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x17900f0f
+}
+
+if { [info exists CPUTAPID_REV_A0] } {
+   set _CPUTAPID_REV_A0 $CPUTAPID_REV_A0
+} else {
+   set _CPUTAPID_REV_A0 0x17926f0f
+}
+
+if { [info exists SJCTAPID] } {
+   set _SJCTAPID $SJCTAPID
+} else {
+   set _SJCTAPID 0x1b900f0f
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID \
+     -expected-id $_CPUTAPID_REV_A0
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0
+
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc40xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc40xx.cfg
new file mode 100644
index 0000000..f0be5a1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc40xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC40xx Cortex-M4F with at least 16kB SRAM
+set CHIPNAME lpc40xx
+set CHIPSERIES lpc4000
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x4000
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc4350.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc4350.cfg
new file mode 100644
index 0000000..453306a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc4350.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/swj-dp.tcl]
+
+adapter speed 500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME lpc4350
+}
+
+#
+# M4 JTAG mode TAP
+#
+if { [info exists M4_JTAG_TAPID] } {
+	set _M4_JTAG_TAPID $M4_JTAG_TAPID
+} else {
+	set _M4_JTAG_TAPID 0x4ba00477
+}
+
+#
+# M4 SWD mode TAP
+#
+if { [info exists M4_SWD_TAPID] } {
+	set _M4_SWD_TAPID $M4_SWD_TAPID
+} else {
+	set _M4_SWD_TAPID 0x2ba01477
+}
+
+if { [using_jtag] } {
+	set _M4_TAPID $_M4_JTAG_TAPID
+} {
+	set _M4_TAPID $_M4_SWD_TAPID
+}
+
+#
+# M0 TAP
+#
+if { [info exists M0_JTAG_TAPID] } {
+	set _M0_JTAG_TAPID $M0_JTAG_TAPID
+} else {
+	set _M0_JTAG_TAPID 0x0ba01477
+}
+
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+				-expected-id $_M4_TAPID
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
+
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
+				-expected-id $_M0_JTAG_TAPID
+	dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0
+	target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap
+}
+
+# LPC4350 has 96+32 KB SRAM
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x20000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
+			-work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if {![using_hla]} {
+   # on this CPU we should use VECTRESET to perform a soft reset and
+   # manually reset the periphery
+   # SRST or SYSRESETREQ disable the debug interface for the time of
+   # the reset and will not fit our requirements for a consistent debug
+   # session
+   cortex_m reset_config vectreset
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc4357.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc4357.cfg
new file mode 100644
index 0000000..f783505
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc4357.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP LPC4357
+#
+
+if { ![info exists CHIPNAME] } {
+	set CHIPNAME lpc4357
+}
+set WORKAREASIZE 0x8000
+source [find target/lpc4350.cfg]
+
+flash bank $_CHIPNAME.flasha lpc2000 0x1A000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum
+flash bank $_CHIPNAME.flashb lpc2000 0x1B000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc4370.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc4370.cfg
new file mode 100644
index 0000000..fe9e76b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc4370.cfg
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
+#
+
+adapter speed 500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME lpc4370
+}
+
+#
+# M4 JTAG mode TAP
+#
+if { [info exists M4_JTAG_TAPID] } {
+	set _M4_JTAG_TAPID $M4_JTAG_TAPID
+} else {
+	set _M4_JTAG_TAPID 0x4ba00477
+}
+
+#
+# M4 SWD mode TAP
+#
+if { [info exists M4_SWD_TAPID] } {
+	set _M4_SWD_TAPID $M4_SWD_TAPID
+} else {
+	set _M4_SWD_TAPID 0x2ba01477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+	set _M4_TAPID $_M4_JTAG_TAPID
+} else {
+	set _M4_TAPID $_M4_SWD_TAPID
+}
+
+#
+# M0 TAP
+#
+if { [info exists M0_JTAG_TAPID] } {
+	set _M0_JTAG_TAPID $M0_JTAG_TAPID
+} else {
+	set _M0_JTAG_TAPID 0x0ba01477
+}
+
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+				-expected-id $_M4_TAPID
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
+
+# LPC4370 has 96+32 KB contiguous SRAM
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x20000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
+                        -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \
+					-expected-id $_M0_JTAG_TAPID
+	jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
+					-expected-id $_M0_JTAG_TAPID
+
+	dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
+	dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
+	target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
+	target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
+
+	# 32+8+32 KB SRAM
+	$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
+	                           -work-area-size 0x92000 -work-area-backup 0
+
+	# 16+2 KB M0 subsystem SRAM
+	$_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \
+	                           -work-area-size 0x4800 -work-area-backup 0
+
+	# Default to the Cortex-M4
+	targets $_CHIPNAME.m4
+}
+
+if { ![using_hla] } {
+	cortex_m reset_config vectreset
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc84x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc84x.cfg
new file mode 100644
index 0000000..af26f27
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc84x.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC84x Cortex-M0+ with at least 8kB SRAM
+if { ![info exists CHIPNAME] } {
+	set CHIPNAME lpc84x
+}
+set CHIPSERIES lpc800
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x1fe0
+}
+
+set IAP_ENTRY 0x0F001FF1
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc8nxx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc8nxx.cfg
new file mode 100644
index 0000000..859e99b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc8nxx.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM
+# Copyright (C) 2018 by Jean-Christian de Rivaz
+# Based on NXP proposal https://community.nxp.com/message/1011149
+# Many thanks to Dries Moors from NXP support.
+# SWD only transport
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME lpc8nxx
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+if {![using_hla]} {
+	# If srst is not fitted use SYSRESETREQ to  perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+adapter srst delay 100
+
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
+
+flash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500
+
+echo "*********************************************************************************"
+echo "*         !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!"
+echo "* When this IC is in power-off or peep power down mode, the SWD HW block is also"
+echo "* unpowered. These modes can be entered by firmware. The default firmware image"
+echo "* (flashed in production) makes use of this. Best is to avoid these power modes"
+echo "* during development, and only later add them when the functionality is complete."
+echo "* Hardware reset or NFC field are the only ways to connect in case the SWD is"
+echo "* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST"
+echo "* signal to the chip RESETN pin and add the following in your configuration:"
+echo "*     reset_config srst_only; flash init; catch init; reset"
+echo "* But if the actual firmware immediately set the power down mode after reset,"
+echo "* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In"
+echo "* that case the only solution is to apply a NFC field to keep the SWD powered."
+echo "*********************************************************************************"
+
+# Using soft-reset 'reset_config none' is strongly discouraged.
+# RESETN sets the system clock to 500 kHz. Unlike soft-reset does not.
+# Set the system clock to 500 kHz before reset to simulate the functionality of hw reset.
+#
+proc set_sysclk_500khz {} {
+	set SYSCLKCTRL 0x40048020
+	set SYSCLKUEN 0x40048024
+	mww $SYSCLKUEN 0
+	mmw $SYSCLKCTRL 0x8 0xe
+	mww $SYSCLKUEN 1
+	echo "Notice: sysclock set to 500kHz."
+}
+
+# Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
+# Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
+# Bit Symbol  Value   Description
+# 0   map         -   interrupt vector remap. 0 after boot.
+#                 0   interrupt vector reside in Flash
+#                 1   interrupt vector reside in SRAM
+# 5:1 offset      -   system memory remap offset. 00000b after boot.
+#            00000b   interrupt vectors in flash or remapped to SRAM but no offset
+#            00001b -
+#            00111b   interrupt vectors offset in flash or SRAM to 1K word segment
+#            01000b -
+#            11111b   interrupt vectors offset in flash to 1K word segment 8 to 31
+# 31:6                reserved
+#
+proc set_no_remap {} {
+	mww 0x40048000 0x00
+	echo "Notice: interrupt vector set to no remap."
+}
+
+$_TARGETNAME configure -event reset-init {
+	set_sysclk_500khz
+	set_no_remap
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc8xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc8xx.cfg
new file mode 100644
index 0000000..4c54a2a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lpc8xx.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC8xx Cortex-M0+ with at least 1kB SRAM
+if { ![info exists CHIPNAME] } {
+	set CHIPNAME lpc8xx
+}
+set CHIPSERIES lpc800
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x400
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1012a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1012a.cfg
new file mode 100644
index 0000000..7333ea8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1012a.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP LS1012A
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ls1012a
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x5ba00477
+}
+
+if { [info exists SAP_TAPID] } {
+	set _SAP_TAPID $SAP_TAPID
+} else {
+	set _SAP_TAPID 0x06b2001d
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80420000
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase 0x80410000 -cti $_CHIPNAME.cti
+
+target smp $_TARGETNAME
+
+adapter speed 2000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1028a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1028a.cfg
new file mode 100644
index 0000000..463ec7d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1028a.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1028A
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ls1028a
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x6ba00477
+}
+
+set _CPUS 2
+
+source [find target/lsch3_common.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1046a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1046a.cfg
new file mode 100644
index 0000000..3d96a99
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1046a.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1046A
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ls1046a
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x5ba00477
+}
+
+if { [info exists SAP_TAPID] } {
+	set _SAP_TAPID $SAP_TAPID
+} else {
+	set _SAP_TAPID 0x06b3001d
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+set _CPU_BASE 0x80400000
+set _CPU_STRIDE 0x100000
+set _CPU_DBGOFF 0x10000
+set _CPU_CTIOFF 0x20000
+
+set _TARGETS {}
+for {set i 0} {$i < 4} {incr i} {
+	set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
+	cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 1 \
+		-baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
+	target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
+		-cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
+		-coreid $i {*}[expr {$i ? {-defer-examine} : {-rtos hwthread} }]
+	lappend _TARGETS $_CHIPNAME.cpu$i
+}
+
+target smp {*}$_TARGETS
+
+jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID
+target create $_CHIPNAME.sap ls1_sap -chain-position $_CHIPNAME.sap -endian big
+
+proc core_up { args } {
+    foreach core $args {
+        $::_CHIPNAME.cpu$core arp_examine
+    }
+}
+
+targets $_CHIPNAME.cpu0
+
+adapter speed 10000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1088a.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1088a.cfg
new file mode 100644
index 0000000..193d6dd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ls1088a.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1088A
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ls1088a
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x5ba00477
+}
+
+set _CPUS 8
+
+source [find target/lsch3_common.cfg]
+
+# Seems to work OK in testing
+adapter speed 10000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lsch3_common.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lsch3_common.cfg
new file mode 100644
index 0000000..f48d59b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/lsch3_common.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This contains common configuration for NXP Layerscape chassis generation 3
+
+if { ![info exists _CPUS] } {
+	error "_CPUS must be set to the number of cores"
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1
+
+set _CPU_BASE 0x81000000
+set _CPU_STRIDE 0x100000
+set _CPU_DBGOFF 0x10000
+set _CPU_CTIOFF 0x20000
+
+set _TARGETS {}
+for {set i 0} {$i < $_CPUS} {incr i} {
+	set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
+	cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \
+		-baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
+	target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
+		-cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
+		{*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }]
+	lappend _TARGETS $_CHIPNAME.cpu$i
+}
+
+target smp {*}$_TARGETS
+
+# Service processor
+target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
+
+# Normally you will not need to call this, but if you are using the hard-coded
+# Reset Configuration Word (RCW) you will need to call this manually. The CPU's
+# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
+# instructions. This will cause the CPU to almost immediately execute an
+# illegal instruction.
+#
+# This code is idempotent; releasing a released CPU has no effect, although it
+# will halt/resume the service processor.
+add_help_text release_cpu "Release a cpu which is held off"
+proc release_cpu {cpu} {
+	set RST_BRRL 0x1e60060
+
+	set old [target current]
+	targets $::_CHIPNAME.sp
+	set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
+	if {$not_halted} {
+		halt
+	}
+
+	# Release the cpu; it will start executing something bogus
+	mem2array regs 32 $RST_BRRL 1
+	mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
+
+	if {$not_halted} {
+		resume
+	}
+	targets $old
+}
+
+targets $_CHIPNAME.cpu0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/88f3710.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/88f3710.cfg
new file mode 100644
index 0000000..dcc4516
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/88f3710.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell Armada 3710
+
+set CORES 1
+
+source [find target/marvell/88f37x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/88f3720.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/88f3720.cfg
new file mode 100644
index 0000000..7c29378
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/88f3720.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell Armada 3720
+
+set CORES 2
+
+source [find target/marvell/88f37x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/88f37x0.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/88f37x0.cfg
new file mode 100644
index 0000000..738d221
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/88f37x0.cfg
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Main file for Marvell Armada 3700 series targets
+#
+# !!!!!!
+#
+# This file should not be included directly. Instead, please include
+# either marvell/88f3710.cfg or marvell/88f3720.cfg, which set the needed
+# variables to the appropriate values.
+#
+# !!!!!!
+
+# Armada 3700 supports both JTAG and SWD transports.
+source [find target/swj-dp.tcl]
+
+if { [info exists CORES] } {
+    set _cores $CORES
+} else {
+    error "CORES not set. Please do not include marvell/88f37x0.cfg directly, but the specific chip configuration file (marvell/88f3710.cfg, marvell/88f3720.cfg, etc.)."
+}
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME [format a37%s0 $_cores]
+}
+
+set _ctis {0x80820000 0x80920000}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+# declare the one JTAG tap to access the DAP
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# declare the main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [lindex $_ctis $_core] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core \
+                         -cti cti$_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+# declare the auxiliary Cortex-M3 core on AP #3
+target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+
+targets ${_TARGETNAME}0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/cn9130.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/cn9130.cfg
new file mode 100644
index 0000000..23e472f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/marvell/cn9130.cfg
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# cn9130 -- support for the Marvell Octeon TX2 / CN9130 CPU family
+#
+# henrik.nordstorm@addiva.se, Nov 2023
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME cn9130
+}
+
+if { [info exists MASTERTAPID] } {
+   set _MASTERTAPID $MASTERTAPID
+} else {
+   set _MASTERTAPID 0x07025357
+}
+
+if { [info exists APTAPID] } {
+   set _APTAPID $APTAPID
+} else {
+   set _APTAPID 0x4ba00477
+}
+
+if { [info exists SBTAPID] } {
+   set _SBTAPID $SBTAPID
+} else {
+   set _SBTAPID 0x4ba00477
+}
+
+if { [info exists CORES] } {
+   set _CORES $CORES
+} else {
+   set _CORES 4
+}
+
+# CTI base address should be possible to read from the CoreSight
+# ROM table like how the DBG base address is when not specified.
+if { [info exists CTIBASE] } {
+   set _CTIBASE $CTIBASE
+} else {
+   set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+}
+
+# CN9130 is a multi-die chip and has a multi level hierarchical
+# JTAG TAP, where all the DAPs are disabled at reset, requiring
+# both configuration to enable access to the chip DAPs, and a
+# vendor specific bypass IR instruction to access the slave TAPs
+# via the master TAP. In addition there is a number of sample
+# bits that should be ignored.
+#
+# The default BYPASS instruction in the master TAP bypasses the
+# whole chip and not only the master TAP. And similarly on
+# IDCODE the master TAP only responds with it's own ID and
+# bypasses the other TAPs on the chip, while OpenOCD expects
+# ID from all enabled TAPs in the chain.
+
+# Bootstrap with the default boundary scan oriented TAP configuration
+# where the master,ap,sb TAPs are seen as one big fat TAP, which matches
+# what OpenOCD expects from IDCODE and BYPASS.
+
+jtag newtap $_CHIPNAME bs  -irlen 19 -enable -expected-id $_MASTERTAPID
+
+# Declare the full JTAG chain, but in disabled state during setup
+
+jtag newtap $_CHIPNAME sample4 -irlen 1 -disable
+jtag newtap $_CHIPNAME sample3 -irlen 1 -disable
+jtag newtap $_CHIPNAME sample2 -irlen 1 -disable
+jtag newtap $_CHIPNAME ap.cpu  -irlen 4 -disable -expected-id $_APTAPID
+jtag newtap $_CHIPNAME ap      -irlen 5 -disable
+jtag newtap $_CHIPNAME sample1 -irlen 1 -disable
+jtag newtap $_CHIPNAME sb.cpu  -irlen 4 -disable -expected-id $_SBTAPID
+jtag newtap $_CHIPNAME sb      -irlen 5 -disable
+jtag newtap $_CHIPNAME master  -irlen 5 -disable -ir-bypass 0x11 -expected-id $_MASTERTAPID
+
+# Once the iniial IDCODE scan has completed switch to more detailed
+# scan chain giving access to the individual chip TAPs.
+
+jtag configure $_CHIPNAME.bs -event setup "cn9130_enable_full_chain $_CHIPNAME"
+
+proc cn9130_enable_full_chain { _CHIPNAME } {
+   # Switch to detailed TAP declaration
+   jtag tapdisable $_CHIPNAME.bs
+   jtag tapenable $_CHIPNAME.master
+   jtag tapenable $_CHIPNAME.sb
+   jtag tapenable $_CHIPNAME.sample1
+   jtag tapenable $_CHIPNAME.ap
+   jtag tapenable $_CHIPNAME.sample2
+   jtag tapenable $_CHIPNAME.sample3
+   jtag tapenable $_CHIPNAME.sample4
+}
+
+# AP & SB TAPs have a config register to enable/disable access to
+# the auxilary DAP TAP. Default off which hides the DAP TAP from
+# the scan chain.
+proc cn9130_dap_config { chip tap state } {
+   irscan $chip.$tap 0x12
+   drscan $chip.$tap 32 $state
+}
+
+jtag configure $_CHIPNAME.bs -event tap-disable ""
+jtag configure $_CHIPNAME.bs -event tap-enable ""
+jtag configure $_CHIPNAME.sample4 -event tap-enable ""
+jtag configure $_CHIPNAME.sample3 -event tap-enable ""
+jtag configure $_CHIPNAME.sample2 -event tap-enable ""
+jtag configure $_CHIPNAME.ap.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME ap 0"
+jtag configure cn9130.ap.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME ap 1"
+jtag configure $_CHIPNAME.ap -event tap-enable ""
+jtag configure $_CHIPNAME.sample1 -event tap-enable ""
+jtag configure $_CHIPNAME.sb.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME sb 0"
+jtag configure cn9130.sb.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME sb 1"
+jtag configure $_CHIPNAME.sb -event tap-enable ""
+jtag configure $_CHIPNAME.master -event tap-enable ""
+
+dap create $_CHIPNAME.ap.dap -chain-position $_CHIPNAME.ap.cpu
+
+# Main bus
+target create $_CHIPNAME.ap.axi mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 0
+
+# Periperials bus
+target create $_CHIPNAME.ap.apb mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 1
+
+# MSS bus
+target create $_CHIPNAME.ap.ahb mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 2
+
+# AP A72 CPU cores
+set _smp_command ""
+for { set _core 0 } { $_core < $_CORES } { incr _core 1 } {
+   cti create $_CHIPNAME.ap.cti.$_core \
+      -dap $_CHIPNAME.ap.dap \
+      -baseaddr [ lindex $_CTIBASE $_core ]  \
+      -ap-num 1
+
+   if { $_core == 0 } {
+      target create $_CHIPNAME.ap.a72.$_core aarch64 \
+         -dap $_CHIPNAME.ap.dap \
+         -ap-num 1 \
+         -cti $_CHIPNAME.ap.cti.$_core \
+         -coreid $_core \
+         -rtos hwthread
+      set _smp_command "target smp $_CHIPNAME.ap.a72.$_core"
+   } else {
+      # Defer non-boot cores. Held hard in reset until
+      # SMP is activated.
+      target create $_CHIPNAME.ap.a72.$_core aarch64 \
+         -dap $_CHIPNAME.ap.dap \
+         -ap-num 1 \
+         -cti $_CHIPNAME.ap.cti.$_core \
+         -coreid $_core \
+         -defer-examine
+      set _smp_command "$_smp_command $_CHIPNAME.ap.a72.$_core"
+   }
+
+}
+
+# Set up the A72 cluster as SMP
+# Note: Only the boot core is active by default. The other core DAPs can
+# be enabled by arp_examine after they have been released from hard reset.
+eval $_smp_command
+
+# AP MSS M3 CPU core. Defer as it is held in reset until firmware is loaded.
+target create $_CHIPNAME.ap.mss cortex_m -dap $_CHIPNAME.ap.dap -ap-num 2 -defer-examine
+
+# Why is this needed? reset fails with "Debug regions are unpowered" otherwise
+$_CHIPNAME.ap.axi configure -event examine-start "dap init"
+
+# Automate enabling the AP A72 DAP once the full scan chain is enabled
+proc cn9130_ap_setup { _CHIPNAME } {
+   jtag tapenable $_CHIPNAME.ap.cpu
+   targets $_CHIPNAME.ap.a72.0
+}
+jtag configure $_CHIPNAME.ap -event setup "cn9130_ap_setup $_CHIPNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/max32620.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/max32620.cfg
new file mode 100644
index 0000000..f3a9f84
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/max32620.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Maxim Integrated MAX32620 OpenOCD target configuration file
+# www.maximintegrated.com
+
+# adapter speed
+adapter speed 4000
+
+# reset pin configuration
+reset_config srst_only
+
+if {[using_jtag]} {
+    jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
+    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
+} else {
+    swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
+}
+
+dap create max32620.dap -chain-position max32620.cpu
+
+# target configuration
+target create max32620.cpu cortex_m -dap max32620.dap
+max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+
+# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
+#   flash bank  max32xxx   0 0     
+#   max32620 flash base address   0x00000000
+#   max32620 flash size           0x200000 (2MB)
+#   max32620 FLC base address     0x40002000
+#   max32620 sector (page) size   0x2000 (8kB)
+#   max32620 clock speed          96 (MHz)
+flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/max32625.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/max32625.cfg
new file mode 100644
index 0000000..90eb392
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/max32625.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Maxim Integrated MAX32625 OpenOCD target configuration file
+# www.maximintegrated.com
+
+# adapter speed
+adapter speed 4000
+
+# reset pin configuration
+reset_config srst_only
+
+if {[using_jtag]} {
+    jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
+    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version
+} else {
+    swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
+}
+
+dap create max32625.dap -chain-position max32625.cpu
+
+# target configuration
+target create max32625.cpu cortex_m -dap max32625.dap
+max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+
+# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
+#   flash bank  max32xxx   0 0     
+#   max32625 flash base address   0x00000000
+#   max32625 flash size           0x80000 (512k)
+#   max32625 FLC base address     0x40002000
+#   max32625 sector (page) size   0x2000 (8kB)
+#   max32625 clock speed          96 (MHz)
+flash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/max3263x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/max3263x.cfg
new file mode 100644
index 0000000..852e04a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/max3263x.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Maxim Integrated MAX3263X OpenOCD target configuration file
+# www.maximintegrated.com
+
+# adapter speed
+adapter speed 4000
+
+# reset pin configuration
+reset_config srst_only
+
+if {[using_jtag]} {
+    jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
+    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version
+} else {
+    swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
+}
+
+dap create max3263x.dap -chain-position max3263x.cpu
+
+# target configuration
+target create max3263x.cpu cortex_m -dap max3263x.dap
+max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+
+# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
+#   flash bank  max32xxx   0 0     
+#   max3263x flash base address   0x00000000
+#   max3263x flash size           0x200000 (2MB)
+#   max3263x FLC base address     0x40002000
+#   max3263x sector (page) size   0x2000 (8kB)
+#   max3263x clock speed          96 (MHz)
+flash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/mc13224v.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/mc13224v.cfg
new file mode 100644
index 0000000..29e4d9d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/mc13224v.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find bitsbytes.tcl]
+source [find cpu/arm/arm7tdmi.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+set CHIP_MAKER             freescale
+set CHIP_FAMILY            mc1322x
+set CHIP_NAME              mc13224
+set N_RAM                  1
+set RAM(0,BASE)            0x00400000
+set RAM(0,LEN)             0x18000
+set RAM(0,HUMAN)           "internal SRAM"
+set RAM(0,TYPE)            "ram"
+set RAM(0,RWX)             $RWX_RWX
+set RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# I AM LAZY... I create 1 region for all MMRs.
+set N_MMREGS                  1
+set MMREGS(0,CHIPSELECT)      -1
+set MMREGS(0,BASE)            0x80000000
+set MMREGS(0,LEN)             0x00030000
+set MMREGS(0,HUMAN)           "mm-regs"
+set MMREGS(0,TYPE)            "mmr"
+set MMREGS(0,RWX)             $RWX_RW
+set MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+set N_XMEM 0
+
+set _CHIPNAME mc13224v
+set _CPUTAPID 0x1f1f001d
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+reset_config srst_only
+jtag_ntrst_delay 200
+
+# rclk hasn't been working well. This maybe the mc13224v or something else.
+#adapter speed 2000
+adapter speed 2000
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
+
+# Internal sram memory
+$_TARGETNAME configure -work-area-phys 0x00408000 \
+                       -work-area-size 0x1000     \
+                       -work-area-backup 1
+
+# flash support is pending (should be straightforward to implement)
+#flash bank mc1322x 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/mdr32f9q2i.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/mdr32f9q2i.cfg
new file mode 100644
index 0000000..6e958c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/mdr32f9q2i.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MDR32F9Q2I (1986ВЕ92У)
+# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME mdr32f9q2i
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      # SWD IDCODE
+      set _CPUTAPID 0x2ba01477
+   }
+}
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# can't handle overlapping memory regions
+if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
+   flash bank ${_CHIPNAME}_info.flash mdr 0x08000000 0x01000 0 0 $_TARGETNAME 1 1 4
+} else {
+   flash bank $_CHIPNAME.flash mdr 0x08000000 0x20000 0 0 $_TARGETNAME 0 32 4
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nds32v5.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nds32v5.cfg
new file mode 100644
index 0000000..56b5fed
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nds32v5.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Andes Core
+#
+# http://www.andestech.com
+#
+
+set _CHIPNAME nds
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563D
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp304.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp304.cfg
new file mode 100644
index 0000000..27c30a0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp304.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP304 processor by NetLogic Microsystems
+#
+
+set XLP_NT 4
+source [find target/netl_xlp3xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp308.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp308.cfg
new file mode 100644
index 0000000..c3ba11e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp308.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP308 processor by NetLogic Microsystems
+#
+
+set XLP_NT 8
+source [find target/netl_xlp3xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp316.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp316.cfg
new file mode 100644
index 0000000..961b67f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp316.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP316 processor by NetLogic Microsystems
+#
+
+set XLP_NT 16
+source [find target/netl_xlp3xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp3xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp3xx.cfg
new file mode 100644
index 0000000..2366503
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/netl_xlp3xx.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP 300-series processors by NetLogic Microsystems
+#
+# See http://www.broadcom.com/products/Processors/Enterprise/XLP300-Series
+#
+# Use xlp304.cfg, xlp308.cfg, xlp316.cfg for particular processor model.
+#
+
+transport select jtag
+
+global XLP_NT
+
+for {set i $XLP_NT} {$i > 0} {incr i -1} {
+	jtag newtap xlp cpu_$i -irlen 5 -disable
+	if {$i != 1} {
+		jtag configure xlp.cpu_$i -event tap-enable {}
+	}
+}
+jtag newtap xlp jrc -irlen 16 -expected-id 0x00011449
+
+jtag configure xlp.cpu_1 -event tap-enable {
+	global XLP_NT
+	irscan xlp.jrc 0xe0
+	drscan xlp.jrc 1 1
+	for {set i $XLP_NT} {$i > 1} {incr i -1} {
+		jtag tapenable xlp.cpu_$i
+	}
+}
+
+proc chipreset {} {
+	irscan xlp.jrc 0xab
+	drscan xlp.jrc 1 1
+	drscan xlp.jrc 1 0
+}
+
+jtag configure xlp.jrc -event setup "jtag tapenable xlp.cpu_1"
+
+target create xlp.cpu_1 mips_mips64 -endian big -chain-position xlp.cpu_1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ngultra.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ngultra.cfg
new file mode 100644
index 0000000..956fdbb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ngultra.cfg
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2022 by NanoXplore, France - all rights reserved
+#
+# configuration file for NG-Ultra SoC from NanoXplore.
+# NG-Ultra is a quad-core Cortex-R52 SoC + an FPGA.
+#
+transport select jtag
+adapter speed 10000
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME NGULTRA
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 4
+}
+
+set DBGBASE {0x88210000 0x88310000 0x88410000 0x88510000}
+set CTIBASE {0x88220000 0x88320000 0x88420000 0x88520000}
+
+# Coresight access to the SoC
+jtag newtap $_CHIPNAME.coresight cpu      -irlen 4 -expected-id 0x6BA00477
+
+# Misc TAP devices
+jtag newtap $_CHIPNAME.soc       cpu      -irlen 7 -expected-id 0xFAAA0555
+jtag newtap $_CHIPNAME.pmb       unknown1 -irlen 5 -expected-id 0xBA20A005
+jtag newtap $_CHIPNAME.fpga      fpga     -irlen 4 -ignore-version -ignore-bypass
+
+# Create the Coresight DAP
+dap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+    cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \
+        -baseaddr [lindex $CTIBASE $_core]
+# Cores are armv8-r but works with aarch64 (since armv8-r not directly supported by openocd yet).
+    if { $_core == 0} {
+        target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \
+            -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core
+    } else {
+        target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \
+            -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine
+    }
+}
+
+# Create direct APB and AXI interfaces
+target create APB mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 0
+target create AXI mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nhs31xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nhs31xx.cfg
new file mode 100644
index 0000000..7e4bc4c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nhs31xx.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP NHS31xx Cortex-M0+ with 8kB SRAM
+
+set CHIPNAME nhs31xx
+source [find target/lpc8nxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/npcx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/npcx.cfg
new file mode 100644
index 0000000..84bb0b7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/npcx.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Nuvoton NPCX Cortex-M4 Series
+
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# Set Chipname
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME npcx
+}
+
+# SWD DAP ID of Nuvoton NPCX Cortex-M4.
+if { [info exists CPUDAPID ] } {
+   set _CPUDAPID $CPUDAPID
+} else {
+   set _CPUDAPID 0x4BA00477
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 32kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+if { [info exists FIUNAME]} {
+   set _FIUNAME $FIUNAME
+} else {
+   set _FIUNAME npcx.fiu
+}
+
+# Debug Adapter Target Settings
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# Initial JTAG/SWD speed
+# For safety purposes, set for the lowest cpu clock configuration
+# 4MHz / 6 = 666KHz, so use 600KHz for it
+adapter speed 600
+
+# For safety purposes, set for the lowest cpu clock configuration
+$_TARGETNAME configure -event reset-start {adapter speed 600}
+
+# use sysresetreq to perform a system reset
+cortex_m reset_config sysresetreq
+
+# flash configuration
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME $_FIUNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf51.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf51.cfg
new file mode 100644
index 0000000..3781ecc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf51.cfg
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# script for Nordic nRF51 series, a Cortex-M0 chip
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME nrf51
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if {![using_hla]} {
+   # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
+   cortex_m reset_config sysresetreq
+}
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME
+
+#  The chip should start up from internal 16Mhz RC, so setting adapter
+#  clock to 1Mhz should be OK
+adapter speed 1000
+
+proc enable_all_ram {} {
+	# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
+	# are reliably enabled after reset on some revisions (contrary to spec.) So after
+	# resetting we enable all banks via the RAMON register
+	mww 0x40000524 0xF
+}
+$_TARGETNAME configure -event reset-init {  enable_all_ram }
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf52.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf52.cfg
new file mode 100644
index 0000000..0703b18
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf52.cfg
@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME nrf52
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+adapter speed 1000
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { [using_hla] } {
+	echo ""
+	echo "nRF52 device has a CTRL-AP dedicated to recover the device from AP lock."
+	echo "A high level adapter (like a ST-Link) you are currently using cannot access"
+	echo "the CTRL-AP so 'nrf52_recover' command will not work."
+	echo "Do not enable UICR APPROTECT."
+	echo ""
+} else {
+	cortex_m reset_config sysresetreq
+
+	$_TARGETNAME configure -event examine-fail nrf52_check_ap_lock
+}
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
+
+# Test if MEM-AP is locked by UICR APPROTECT
+proc nrf52_check_ap_lock {} {
+	set dap [[target current] cget -dap]
+	set err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}]
+	if {$err == 0 && $APPROTECTSTATUS != 1} {
+		echo "****** WARNING ******"
+		echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)."
+		echo "Debug access is denied."
+		echo "Use 'nrf52_recover' to erase and unlock the device."
+		echo ""
+		poll off
+	}
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)
+# http://www.ebyte.com produces modules with nRF52 locked by default,
+# use nrf52_recover to enable flashing and debug.
+proc nrf52_recover {} {
+	set target [target current]
+	set dap [$target cget -dap]
+
+	set IDR [$dap apreg 1 0xfc]
+	if {$IDR != 0x02880000} {
+		echo "Error: Cannot access nRF52 CTRL-AP!"
+		return
+	}
+
+	poll off
+
+	# Reset and trigger ERASEALL task
+	$dap apreg 1 4 0
+	$dap apreg 1 4 1
+
+	for {set i 0} {1} {incr i} {
+		set ERASEALLSTATUS [$dap apreg 1 8]
+		if {$ERASEALLSTATUS == 0} {
+			echo "$target device has been successfully erased and unlocked."
+			break
+		}
+		if {$i == 0} {
+			echo "Waiting for chip erase..."
+		}
+		if {$i >= 150} {
+			echo "Error: $target recovery failed."
+			break
+		}
+		sleep 100
+	}
+
+	# Assert reset
+	$dap apreg 1 0 1
+
+	# Deassert reset
+	$dap apreg 1 0 0
+
+	# Reset ERASEALL task
+	$dap apreg 1 4 0
+
+	sleep 100
+	$target arp_examine
+	poll on
+}
+
+add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
+	targets $_targetname
+
+	# Read FICR.INFO.PART
+	set PART [mrw 0x10000100]
+
+	switch $PART {
+		0x52840 -
+		0x52833 -
+		0x52832 {
+			# Configuration values for all supported trace port speeds, see
+			# TRACECONFIG.TRACEPORTSPEED
+			set trace_port_speeds {
+				32000000 0
+				16000000 1
+				8000000  2
+				4000000  3
+			}
+
+			# Note that trace port clock stands for what is referred to as
+			# TRACECLKIN in the Arm CoreSight documentation.
+			set trace_port_clock [$_chipname.tpiu cget -traceclk]
+
+			if { ![dict exists $trace_port_speeds $trace_port_clock] } {
+				error "Trace clock speed is not supported"
+			}
+
+			# Set TRACECONFIG.TRACEPORTSPEED
+			mmw 0x4000055C [dict get $trace_port_speeds $trace_port_clock] 0x3
+
+			if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+				if { [$_chipname.tpiu cget -port-width] != 4 } {
+					error "Device only supports 4-bit sync traces"
+				}
+
+				# Set TRACECONFIG.TRACEMUX to enable synchronous trace
+				mmw 0x4000055C 0x00020000 0x00010000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00020000 0x00010000
+				}
+			} else {
+				# Set TRACECONFIG.TRACEMUX to enable SWO
+				mmw 0x4000055C 0x00010000 0x00020000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00010000 0x00020000
+				}
+			}
+		}
+		0x52820 -
+		0x52811 -
+		0x52810 -
+		0x52805 {
+			error "Device does not support TPIU"
+		}
+		default {
+			error "Unknown device, cannot configure TPIU"
+		}
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME $_CHIPNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf53.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf53.cfg
new file mode 100644
index 0000000..307df90
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf53.cfg
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF53 series: dual ARM Cortex-M33, multidrop SWD
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME nrf53
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x6ba02477
+}
+
+# Configurable instance ID resides in application UICR TINSTANCE
+if { [info exists SWD_INSTANCE_ID] } {
+	set _SWD_INSTANCE_ID $SWD_INSTANCE_ID
+} else {
+	set _SWD_INSTANCE_ID 0
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+if { [info exists SWD_MULTIDROP] } {
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0070289 -instance-id $_SWD_INSTANCE_ID
+} else {
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+}
+
+set _TARGETNAME_APP $_CHIPNAME.cpuapp
+target create $_TARGETNAME_APP cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME_APP configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# The network core is not accessible over HLA
+if { ![using_hla] } {
+	set _TARGETNAME_NET $_CHIPNAME.cpunet
+	target create $_TARGETNAME_NET cortex_m -dap $_CHIPNAME.dap -ap-num 1 -defer-examine
+
+	targets $_TARGETNAME_APP
+
+	$_TARGETNAME_NET configure -work-area-phys 0x21000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+}
+
+# Keep adapter speed less or equal 2000 kHz or flash programming fails!
+adapter speed 1000
+
+source [find target/nrf_common.cfg]
+
+flash bank $_CHIPNAME.app.flash nrf5 0x00000000 0 0 0 $_TARGETNAME_APP
+flash bank $_CHIPNAME.app.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME_APP
+
+if { ![using_hla] } {
+
+	flash bank $_CHIPNAME.net.flash nrf5 0x01000000 0 0 0 $_TARGETNAME_NET
+	flash bank $_CHIPNAME.net.uicr nrf5 0x01FF8000 0 0 0 $_TARGETNAME_NET
+
+	# System reset sets NETWORK.FORCEOFF which keeps the network core in reset
+	# Don't touch network core during reset
+	$_TARGETNAME_NET configure -event reset-assert {}
+	# and start it after application core reset is finished to make all flash accessible
+	$_TARGETNAME_APP configure -event reset-init "nrf53_cpunet_release $_CHIPNAME"
+
+	$_TARGETNAME_APP cortex_m reset_config sysresetreq
+	$_TARGETNAME_NET cortex_m reset_config sysresetreq
+
+	$_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 3 }
+	$_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 3 }
+
+	$_TARGETNAME_NET configure -event gdb-attach "_nrf53_cpunet_gdb_attach $_CHIPNAME"
+
+	proc _nrf53_cpunet_gdb_attach { _CHIPNAME } {
+		set _TARGETNAME_APP $_CHIPNAME.cpuapp
+		set _TARGETNAME_NET $_CHIPNAME.cpunet
+		set RESET_NETWORK_FORCEOFF 0x50005614
+
+		set is_off [$_TARGETNAME_APP read_memory $RESET_NETWORK_FORCEOFF 32 1]
+		if { $is_off } {
+			nrf53_cpunet_release $_CHIPNAME
+			$_TARGETNAME_NET arp_poll
+			$_TARGETNAME_NET arp_waitstate halted 100
+		} else {
+			if { ![$_TARGETNAME_NET was_examined] } {
+				$_TARGETNAME_NET arp_examine
+				$_TARGETNAME_NET arp_poll
+			}
+			set s [$_TARGETNAME_NET curstate]
+			if { ![string compare $s "halted"] } {
+				halt
+			}
+		}
+	}
+	lappend _telnet_autocomplete_skip _nrf53_cpunet_gdb_attach
+
+	# Release the network core
+	proc nrf53_cpunet_release { {_CHIPNAME nrf53} } {
+		set _TARGETNAME_APP $_CHIPNAME.cpuapp
+		set _TARGETNAME_NET $_CHIPNAME.cpunet
+		set RESET_NETWORK_FORCEOFF 0x50005614
+		set RESET_NETWORK_WORKAROUND 0x50005618
+		set CORTEX_M_DCB_DEMCR 0xE000EDFC
+
+		$_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 1
+		$_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
+		$_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 1
+		set err [catch {$_TARGETNAME_NET arp_examine}]
+		if { $err } {
+			if { ![_nrf_check_ap_lock 3 3] } {
+				echo "Error: \[$_TARGETNAME_NET\] examination failed"
+			}
+			return
+		}
+		# set TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET
+		$_TARGETNAME_NET mww $CORTEX_M_DCB_DEMCR 0x01000501
+		# Write DEMCR directly intead of permanetly setting by cortex_m vector_catch reset
+		# following cortex_m_endreset_event() restores the original DEMCR value
+		$_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
+		$_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 0
+	}
+
+	# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2 or #3)
+	proc nrf53_cpuapp_recover {} {
+		_nrf_ctrl_ap_recover 2
+	}
+	add_help_text nrf53_cpuapp_recover "Mass erase flash and unlock nRF53 application CPU"
+
+	proc nrf53_recover {} {
+		_nrf_ctrl_ap_recover 3 1
+	}
+	add_help_text nrf53_recover "Mass erase all device flash and unlock nRF53"
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf91.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf91.cfg
new file mode 100644
index 0000000..e0ff4e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf91.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF91 series: ARM Cortex-M33, SWD only
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME nrf91
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x6ba02477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+# Contrary to the product specification at least nRF9161 supports multidrop SWD.
+# The instance ID is fixed, no more than one nRF91 can be connected to one SWD bus.
+if { [info exists SWD_MULTIDROP] } {
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0090289 -instance-id 0
+} else {
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# Keep adapter speed less or equal 2000 kHz or flash programming fails!
+adapter speed 1000
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+source [find target/nrf_common.cfg]
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME
+
+if { ![using_hla] } {
+	$_TARGETNAME cortex_m reset_config sysresetreq
+
+	$_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 3 }
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #4)
+proc nrf91_recover {} {
+	_nrf_ctrl_ap_recover 4
+}
+add_help_text nrf91_recover "Mass erase and unlock nRF91 device"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf_common.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf_common.cfg
new file mode 100644
index 0000000..2ae5011
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nrf_common.cfg
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF52, nRF53 and nRF91 CTRL-AP handling
+#
+
+if { [using_hla] } {
+	echo ""
+	echo "nRF device has a CTRL-AP dedicated to recover the device from AP lock."
+	echo "A high level adapter (like a ST-Link) you are currently using cannot access"
+	echo "the CTRL-AP so 'nrfxx_recover' command will not work."
+	echo "Do not enable UICR APPROTECT."
+	echo ""
+} else {
+
+	# Test if debug/MEM-AP is locked by UICR APPROTECT
+	proc _nrf_check_ap_lock { ctrl_ap_num unlocked_value } {
+		set target [target current]
+		set dap [$target cget -dap]
+		set err [catch {set APPROTECTSTATUS [$dap apreg $ctrl_ap_num 0xc]}]
+		if {$err == 0 && $APPROTECTSTATUS < $unlocked_value} {
+			echo ""
+			echo "****** WARNING ******"
+			echo "\[$target\] device has AP lock engaged (see UICR APPROTECT register)."
+			echo "Debug access is denied."
+			echo "Use 'nrfxx_recover' to erase and unlock the device."
+			echo ""
+			poll off
+			return 1
+		}
+		return 0
+	}
+
+	# Mass erase and unlock the device using proprietary nRF CTRL-AP
+	proc _nrf_ctrl_ap_recover { ctrl_ap_num {is_cpunet 0} } {
+		set target [target current]
+		set dap [$target cget -dap]
+
+		set IDR [$dap apreg $ctrl_ap_num 0xfc]
+		if {$IDR != 0x12880000} {
+			echo "Error: Cannot access nRF CTRL-AP!"
+			return
+		}
+
+		poll off
+
+		# Reset and trigger ERASEALL task
+		$dap apreg $ctrl_ap_num 4 0
+		$dap apreg $ctrl_ap_num 4 1
+
+		for {set i 0} {1} {incr i} {
+			set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 8]
+			if {$ERASEALLSTATUS == 0} {
+				echo "\[$target\] device has been successfully erased and unlocked."
+				break
+			}
+			if {$i == 0} {
+				echo "Waiting for chip erase..."
+			}
+			if {$i >= 150} {
+				echo "Error: \[$target\] recovery failed."
+				break
+			}
+			sleep 100
+		}
+
+		# Assert reset
+		$dap apreg $ctrl_ap_num 0 1
+
+		# Deassert reset
+		$dap apreg $ctrl_ap_num 0 0
+
+		# Reset ERASEALL task
+		$dap apreg $ctrl_ap_num 4 0
+
+		if { $is_cpunet } {
+			reset init
+		} else {
+			sleep 100
+			$target arp_examine
+			poll on
+		}
+	}
+
+	lappend _telnet_autocomplete_skip _nrf_check_ap_lock _nrf_ctrl_ap_recover
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nuc910.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nuc910.cfg
new file mode 100644
index 0000000..31a3ac6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/nuc910.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nuvoton nuc910 (previously W90P910) based soc
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME nuc910
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # set useful default
+   set _CPUTAPID 0x07926f0f
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/numicro.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/numicro.cfg
new file mode 100644
index 0000000..29077f3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/numicro.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Nuvoton MuMicro Cortex-M0 Series
+
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# Set Chipname
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME NuMicro
+}
+
+# SWD DP-ID Nuvoton NuMicro Cortex-M0 has SWD Transport only.
+if { [info exists CPUDAPID] } {
+	set _CPUDAPID $CPUDAPID
+} else {
+	set _CPUDAPID 0x0BB11477
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+
+# Debug Adapter Target Settings
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash bank  numicro   0 0 
+#set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash_aprom
+flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_data
+flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_ldrom
+flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_config
+flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
+
+# set default SWCLK frequency
+adapter speed 1000
+
+# set default srst setting "none"
+reset_config none
+
+# HLA doesn't have cortex_m commands
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/numicro_m4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/numicro_m4.cfg
new file mode 100644
index 0000000..1302515
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/numicro_m4.cfg
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Nuvoton MuMicro Cortex-M4 Series
+
+source [find target/swj-dp.tcl]
+
+# Set Chipname
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME NuMicro
+}
+
+# SWD DP-ID Nuvoton NuMicro Cortex-M4 has SWD Transport only.
+if { [info exists CPUDAPID] } {
+	set _CPUDAPID $CPUDAPID
+} else {
+	set _CPUDAPID 0x2BA01477
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+
+# Debug Adapter Target Settings
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash bank  numicro   0 0 
+#set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash_aprom
+flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_data
+flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_ldrom
+flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_config
+flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
+
+# set default SWCLK frequency
+adapter speed 1000
+
+# set default srst setting "none"
+reset_config none
+
+# HLA doesn't have cortex_m commands
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap2420.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap2420.cfg
new file mode 100644
index 0000000..3e31baf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap2420.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Texas Instruments OMAP 2420
+#	http://www.ti.com/omap
+# as seen in Nokia N8x0 tablets
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omap2420
+}
+
+# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
+reset_config srst_nogate
+
+# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
+jtag newtap $_CHIPNAME iva -irlen 4 -disable
+
+# Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
+jtag newtap $_CHIPNAME dsp -irlen 38 -disable
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
+
+# Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07b3602f
+}
+jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
+
+# Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x01ce4801
+}
+jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
+
+# GDB target: the ARM.
+set _TARGETNAME $_CHIPNAME.arm
+target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
+
+# scratch: framebuffer, may be initially unavailable in some chips
+$_TARGETNAME configure -work-area-phys 0x40210000
+$_TARGETNAME configure -work-area-size 0x00081000
+$_TARGETNAME configure -work-area-backup 0
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
+
+# RM_RSTCTRL_WKUP.RST.GS - Trigger a global software reset, and
+# give it a chance to finish before we talk to the chip again.
+set RM_RSTCTRL_WKUP 0x48008450
+$_TARGETNAME configure -event reset-assert \
+	"halt; $_TARGETNAME mww $RM_RSTCTRL_WKUP 2; sleep 200"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap3530.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap3530.cfg
new file mode 100644
index 0000000..bd8b111
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap3530.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TI OMAP3530
+# http://focus.ti.com/docs/prod/folders/print/omap3530.html
+# Other OMAP3 chips remove DSP and/or the OpenGL support
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omap3530
+}
+
+# ICEpick-C ... used to route Cortex, DSP, and more not shown here
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
+jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
+
+# Subsidiary TAP: CoreSight Debug Access Port (DAP)
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x0b6d602f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 3"
+
+# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b7ae02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID
+
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+# SRAM: 64K at 0x4020.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
+
+###################
+
+# the reset sequence is event-driven
+# and kind of finicky...
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+
+proc omap3_dbginit {target} {
+     # General Cortex-A8 debug initialisation
+     cortex_a dbginit
+     # Enable DBGU signal for OMAP353x
+     $target mww phys 0x5401d030 0x00002000
+}
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
+# OK to speed up *after* PLL and clock tree setup.
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
+# would issue.  RST_DPLL3 (4) is a cold reset.
+set PRM_RSTCTRL 0x48307250
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
+
+$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap4430.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap4430.cfg
new file mode 100644
index 0000000..4bc7fe1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap4430.cfg
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OMAP4430
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME omap4430
+}
+
+
+# Although the OMAP4430 supposedly has an ICEpick-D, only the
+# ICEpick-C router commands seem to work.
+# See http://processors.wiki.ti.com/index.php/ICEPICK
+source [find target/icepick.cfg]
+
+
+#
+# A9 DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x3BA00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 9"
+
+
+#
+# M3 DAPs, one per core
+#
+if { [info exists M3_DAP_TAPID] } {
+	set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+	set _M3_DAP_TAPID 0x4BA00477
+}
+
+jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m31 -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 5"
+
+jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m30 -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 4"
+
+
+#
+# ICEpick-D JRC (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID  0x3b95c02f
+	set _JRC_TAPID2 0x1b85202f
+}
+
+# PandaBoard REV EA1 (PEAP platforms)
+if { [info exists JRC_TAPID2] } {
+	set _JRC_TAPID2 $JRC_TAPID2
+} else {
+	set _JRC_TAPID2 0x1b85202f
+}
+
+
+
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
+
+# Required by ICEpick to power-up the debug domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
+
+
+#
+# GDB target: Cortex-A9, using DAP
+#
+# The debugger can connect to either core of the A9, but currently
+# not both simultaneously.  Change -coreid to 1 to connect to the
+# second core.
+#
+set _TARGETNAME $_CHIPNAME.cpu
+
+# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
+# 0x80000000 is cpu0 coresight region
+#
+#
+# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
+# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
+
+set _coreid 0
+set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
+echo "Using dbgbase = [format 0x%x $_dbgbase]"
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
+  -coreid 0 -dbgbase $_dbgbase
+
+# SRAM: 56KiB at 0x4030.0000
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
+
+
+#
+# M3 targets, separate TAP/DAP for each core
+#
+dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
+dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
+target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
+
+
+# Once the JRC is up, enable our TAPs
+jtag configure $_CHIPNAME.jrc -event setup "
+	jtag tapenable $_CHIPNAME.cpu
+	jtag tapenable $_CHIPNAME.m30
+	jtag tapenable $_CHIPNAME.m31
+"
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  1 is a warm reset, 2 a cold reset.
+set PRM_RSTCTRL 0x4A307B00
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
+$_CHIPNAME.m30 configure -event reset-assert { }
+$_CHIPNAME.m31 configure -event reset-assert { }
+
+# Soft breakpoints don't currently work due to broken cache handling
+gdb breakpoint_override hard
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap4460.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap4460.cfg
new file mode 100644
index 0000000..85ba96c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap4460.cfg
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OMAP4460
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME omap4460
+}
+
+
+# Although the OMAP4430 supposedly has an ICEpick-D, only the
+# ICEpick-C router commands seem to work.
+# See http://processors.wiki.ti.com/index.php/ICEPICK
+source [find target/icepick.cfg]
+
+
+#
+# A9 DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x3BA00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 9"
+
+
+#
+# M3 DAPs, one per core
+#
+if { [info exists M3_DAP_TAPID] } {
+	set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+	set _M3_DAP_TAPID 0x4BA00477
+}
+
+jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m31 -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 5"
+
+jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m30 -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 4"
+
+
+#
+# ICEpick-D JRC (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID  0x2b94e02f
+	set _JRC_TAPID2 0x1b85202f
+}
+
+# PandaBoard REV EA1 (PEAP platforms)
+if { [info exists JRC_TAPID2] } {
+	set _JRC_TAPID2 $JRC_TAPID2
+} else {
+	set _JRC_TAPID2 0x1b85202f
+}
+
+
+
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
+
+# Required by ICEpick to power-up the debug domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
+
+
+#
+# GDB target: Cortex-A9, using DAP
+#
+# The debugger can connect to either core of the A9, but currently
+# not both simultaneously.  Change -coreid to 1 to connect to the
+# second core.
+#
+set _TARGETNAME $_CHIPNAME.cpu
+
+# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
+# 0x80000000 is cpu0 coresight region
+#
+#
+# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
+# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
+
+set _coreid 0
+set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
+echo "Using dbgbase = [format 0x%x $_dbgbase]"
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
+  -coreid 0 -dbgbase $_dbgbase
+
+# SRAM: 56KiB at 0x4030.0000
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
+
+
+#
+# M3 targets, separate TAP/DAP for each core
+#
+dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
+dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
+target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
+
+
+# Once the JRC is up, enable our TAPs
+jtag configure $_CHIPNAME.jrc -event setup "
+	jtag tapenable $_CHIPNAME.cpu
+	jtag tapenable $_CHIPNAME.m30
+	jtag tapenable $_CHIPNAME.m31
+"
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  1 is a warm reset, 2 a cold reset.
+set PRM_RSTCTRL 0x4A307B00
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
+$_CHIPNAME.m30 configure -event reset-assert { }
+$_CHIPNAME.m31 configure -event reset-assert { }
+
+# Soft breakpoints don't currently work due to broken cache handling
+gdb breakpoint_override hard
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap5912.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap5912.cfg
new file mode 100644
index 0000000..783f460
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omap5912.cfg
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TI OMAP5912 dual core processor
+# http://focus.ti.com/docs/prod/folders/print/omap5912.html
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omap5912
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # NOTE: validated with XOMAP5912 part
+   set _CPUTAPID 0x0692602f
+}
+
+adapter srst delay 100
+
+# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
+# its standalone siblings (like TMS320VC5502) of the same era
+
+#jtag scan chain
+jtag newtap $_CHIPNAME dsp -irlen 38 -expected-id 0x03df1d81
+jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME unknown -irlen 8
+
+set _TARGETNAME $_CHIPNAME.arm
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+
+proc omap5912_reset {} {
+	#
+	# halt target
+	#
+	poll
+	sleep 1
+	halt
+	wait_halt
+	#
+	# disable wdt
+	#
+	mww 0xfffec808 0x000000f5
+	mww 0xfffec808 0x000000a0
+
+	mww 0xfffeb048 0x0000aaaa
+	sleep 500
+	mww 0xfffeb048 0x00005555
+	sleep 500
+}
+
+# omap5912 lcd frame buffer as working area
+$_TARGETNAME configure -work-area-phys 0x20000000 \
+	-work-area-size 0x3e800 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omapl138.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omapl138.cfg
new file mode 100644
index 0000000..78c456d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/omapl138.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments DaVinci family: OMAPL138
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omapl138
+}
+
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID -disable
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 3"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07926001
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID -disable
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 2"
+
+# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b7d102f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
+# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
+# and the ETB memory (4K) are other options, while trace is unused.
+# Little-endian; use the OpenOCD default.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
+
+gdb breakpoint_override hard
+arm7_9 dbgrq enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/or1k.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/or1k.cfg
new file mode 100644
index 0000000..ddd4fa2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/or1k.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set  _ENDIAN big
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME or1k
+}
+
+if { [info exists TAP_TYPE] } {
+   set _TAP_TYPE $TAP_TYPE
+} else {
+   puts "You need to select a tap type"
+   shutdown
+}
+
+# Configure the target
+if { [string compare $_TAP_TYPE "VJTAG"] == 0 } {
+	if { [info exists FPGATAPID] } {
+	   set _FPGATAPID $FPGATAPID
+	} else {
+	   puts "You need to set your FPGA JTAG ID"
+		shutdown
+	}
+
+	jtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID
+
+	set _TARGETNAME $_CHIPNAME.cpu
+	target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
+
+	# Select the TAP core we are using
+	tap_select vjtag
+
+} elseif { [string compare $_TAP_TYPE "XILINX_BSCAN"] == 0 } {
+
+	if { [info exists FPGATAPID] } {
+	   set _FPGATAPID $FPGATAPID
+	} else {
+	   puts "You need to set your FPGA JTAG ID"
+		shutdown
+	}
+
+	jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_FPGATAPID
+
+	set _TARGETNAME $_CHIPNAME.cpu
+	target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
+
+	# Select the TAP core we are using
+	tap_select xilinx_bscan
+} else {
+	# OpenCores Mohor JTAG TAP ID
+	set _CPUTAPID  0x14951185
+
+	jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+	set _TARGETNAME $_CHIPNAME.cpu
+	target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
+
+	# Select the TAP core we are using
+	tap_select mohor
+}
+
+# Select the debug unit core we are using. This debug unit as an option.
+
+set ADBG_USE_HISPEED		1
+set ENABLE_JSP_SERVER		2
+set ENABLE_JSP_MULTI		4
+
+# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
+# on burst reads and writes to improve download speeds.
+# This option must match the RTL configured option.
+
+du_select adv [expr {$ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI}]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pec930.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pec930.cfg
new file mode 100644
index 0000000..312a212
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pec930.cfg
@@ -0,0 +1,131 @@
+
+adapter speed 5000
+reset_config srst_only
+adapter srst pulse_width 100
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+proc _get_loader {patt} {
+    set _orig_pwd [pwd]
+    set _patt_loader $patt
+    set _loader_bin 0
+    set _level 0
+
+    while {1} {
+        if {[file exists $_patt_loader]} {
+            set _loader_bin [pwd]
+            append _loader_bin "/" $patt
+            break
+        }
+
+        cd ..
+        incr _level 1
+        if {$_level > 20} {
+            set _loader_bin ""
+            break
+        }
+    }
+    cd $_orig_pwd
+    return $_loader_bin
+}
+
+set _2WIRE_ICE 1
+if { $_2WIRE_ICE == 0 } {
+    # jTag 4-wire
+    echo "=> Use 4-wires jTag..."
+    ftdi nscan1_mode off
+} else {
+    # cJtag 2-wire
+    echo "=> Use 2-wires cJTag..."
+    ftdi nscan1_mode on
+}
+
+#/*
+# * bindto 0.0.0.0 can be used to cover all available interfaces.
+# * Uncomment bindto line to enable remote machine debug
+# */
+# bindto 0.0.0.0
+
+#/*
+# * If ftdi device_desc not specified, the device description is ignored during device selection.
+# * So if you want to specify a dedicated FTDI device, you can select following device description:
+# * "Dual RS232-HS" is for Nuclei HummingBird Debugger V1
+# * "USB <-> JTAG-DEBUGGER" is for Nuclei HummingBird Debugger V2
+# * Uncomment one which match your device description
+# */
+# ftdi device_desc "Dual RS232-HS"
+# ftdi device_desc "USB <-> JTAG-DEBUGGER"
+#/* you can also specify adapter serial to select a ftdi chip */
+# adapter serial "FT6S9RD6"
+
+# Bind JTAG with specified serial number passed by JTAGSN
+if { [ info exists JTAGSN ] } {
+    puts "Bind JTAG with serial number $JTAGSN"
+    adapter serial $JTAGSN
+}
+
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
+#/* These signals are used for cJTAG escape sequence on initialization only */
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
+transport select jtag
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+#/* Work-area is a space in RAM used for flash programming */
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREA_SIZE $WORKAREASIZE
+} else {
+   set _WORKAREA_SIZE 0x600
+}
+
+set _WORKAREA_BASE 0x20000A00
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys $_WORKAREA_BASE -work-area-size $_WORKAREA_SIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+
+
+
+#/*
+# * Use external flash-loader 'loader.bin'
+# */
+
+set _BURN_DEV_BASE      0x0
+set _BURN_DEV_SIZE      0x8000
+
+# eflash
+echo "=> Burn Data to eFlash ..."
+set _LOADER_BIN [_get_loader ./flashloader/loader.bin]
+flash bank $_FLASHNAME custom $_BURN_DEV_BASE $_BURN_DEV_SIZE 0 0 $_TARGETNAME 0x4000F800 $_LOADER_BIN sectorsize=512
+
+
+
+#/*
+# * Expose Nuclei self-defined CSRS range
+# * See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
+# * Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
+# * no need to expose since Nuclei OpenOCD 2022
+# */
+#riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
+
+#/* expose N100 customized csr 0xbd0 -> 0xbdc, mainly irqc and timer csrs */
+# riscv expose_csrs 3024-3036
+
+riscv set_reset_timeout_sec 1
+
+init
+
+halt
+
+flash protect 0 0 last off
+
+arm semihosting enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pic32mx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pic32mx.cfg
new file mode 100644
index 0000000..df68e80
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pic32mx.cfg
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME pic32mx
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x30938053
+}
+
+# default working area is 16384
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#
+# At reset the pic32mx does not allow code execution from RAM
+# we have to setup the BMX registers to allow this.
+# One limitation is that we loose the first 2k of RAM.
+#
+
+global _PIC32MX_DATASIZE
+global _WORKAREASIZE
+set _PIC32MX_DATASIZE 0x800
+set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}]
+
+$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
+$_TARGETNAME configure -event reset-init {
+	#
+	# from reset the pic32 cannot execute code in ram - enable ram execution
+	# minimum offset from start of ram is 2k
+	#
+	global _PIC32MX_DATASIZE
+	global _WORKAREASIZE
+
+	# BMXCON	set 0 wait state option by clearing BMXWSDRM bit, bit 6
+	mww 0xbf882000 0x001f0000
+	# BMXDKPBA: 2k kernel data @ 0xa0000000
+	mww 0xbf882010 $_PIC32MX_DATASIZE
+	# BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
+	mww 0xbf882020 $_WORKAREASIZE
+	# BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
+	mww 0xbf882030 $_WORKAREASIZE
+
+	#
+	# Set system clock to 8Mhz if the default clock configuration is set
+	#
+
+	# SYSKEY register, make sure OSCCON is locked
+	mww 0xbf80f230 0x0
+	# SYSKEY register, write unlock sequence
+	mww 0xbf80f230 0xaa996655
+	mww 0xbf80f230 0x556699aa
+	# OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
+	mww 0xbf80f004 0x07000000
+	# SYSKEY register, relock OSCCON
+	mww 0xbf80f230 0x0
+}
+
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/psoc4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/psoc4.cfg
new file mode 100644
index 0000000..baa2c83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/psoc4.cfg
@@ -0,0 +1,218 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Cypress PSoC 4 devices
+
+#
+# PSoC 4 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME psoc4
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
+
+adapter speed 1500
+
+# Reset, bloody PSoC 4 reset
+#
+# 1) XRES (nSRST) resets also SWD DP so SWD line reset and DP reinit is needed.
+# High level adapter stops working after SRST and needs OpenOCD restart.
+# If your hw does not use SRST for other circuits, use sysresetreq instead
+#
+# 2) PSoC 4 executes initialization code from system ROM after reset.
+# This code subsequently jumps to user flash reset vector address.
+# Unfortunately the system ROM code is protected from reading and debugging.
+# Protection breaks vector catch VC_CORERESET used for "reset halt" by cortex_m.
+#
+# Cypress uses TEST_MODE flag to loop CPU in system ROM before executing code
+# from user flash. Programming specifications states that TEST_MODE flag must be
+# set in time frame 400 usec delayed about 1 msec from reset.
+#
+# OpenOCD have no standard way how to set TEST_MODE in specified time frame.
+# As a workaround the TEST_MODE flag is set before reset instead.
+# It worked for the oldest family PSoC4100/4200 even though it is not guaranteed
+# by specification.
+#
+# Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE
+# clear TEST_MODE flag during device reset so workaround is not possible.
+# Use a KitProg adapter for these devices or "reset halt" will not stop
+# before executing user code.
+#
+# 3) SWD cannot be connected during system initialization after reset.
+# This might be a reason for unconnecting ST-Link v2 when deasserting reset.
+# As a workaround arp_reset deassert is not called for hla
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc psoc4_get_family_id {} {
+	set err [catch {set romtable_pid [read_memory 0xF0000FE0 32 3]}]
+	if { $err } {
+		return 0
+	}
+	if { [expr {[lindex $romtable_pid 0] & 0xffffff00 }]
+	  || [expr {[lindex $romtable_pid 1] & 0xffffff00 }]
+	  || [expr {[lindex $romtable_pid 2] & 0xffffff00 }] } {
+		echo "Unexpected data in ROMTABLE"
+		return 0
+	}
+	set designer_id [expr {(( [lindex $romtable_pid 1] & 0xf0 ) >> 4) | (( [lindex $romtable_pid 2] & 0xf ) << 4 ) }]
+	if { $designer_id != 0xb4 } {
+		echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id]
+		return 0
+	}
+	set family_id [expr {( [lindex $romtable_pid 0] & 0xff ) | (( [lindex $romtable_pid 1] & 0xf ) << 8 ) }]
+	return $family_id
+}
+
+proc ocd_process_reset_inner { MODE } {
+	global PSOC4_USE_ACQUIRE PSOC4_TEST_MODE_WORKAROUND
+	global _TARGETNAME
+
+	if { 0 != [string compare $_TARGETNAME [target names]] } {
+		return -code error "PSoC 4 reset can handle only one $_TARGETNAME target";
+	}
+	set t $_TARGETNAME
+
+	# If this target must be halted...
+	set halt -1
+	if { 0 == [string compare $MODE halt] } {
+		set halt 1
+	}
+	if { 0 == [string compare $MODE init] } {
+		set halt 1;
+	}
+	if { 0 == [string compare $MODE run ] } {
+		set halt 0;
+	}
+	if { $halt < 0 } {
+		return -code error "Invalid mode: $MODE, must be one of: halt, init, or run";
+	}
+
+	if { ! [info exists PSOC4_USE_ACQUIRE] } {
+		if { 0 == [string compare [adapter name] kitprog ] } {
+			set PSOC4_USE_ACQUIRE 1
+		} else {
+			set PSOC4_USE_ACQUIRE 0
+		}
+	}
+	if { $PSOC4_USE_ACQUIRE } {
+		set PSOC4_TEST_MODE_WORKAROUND 0
+	} elseif { ! [info exists PSOC4_TEST_MODE_WORKAROUND] } {
+		if { [psoc4_get_family_id] == 0x93 } {
+			set PSOC4_TEST_MODE_WORKAROUND 1
+		} else {
+			set PSOC4_TEST_MODE_WORKAROUND 0
+		}
+	}
+
+	#$t invoke-event reset-start
+	$t invoke-event reset-assert-pre
+
+	if { $halt && $PSOC4_USE_ACQUIRE } {
+		catch { [adapter name] acquire_psoc }
+		$t arp_examine
+	} else {
+		if { $PSOC4_TEST_MODE_WORKAROUND } {
+			set TEST_MODE 0x40030014
+			if { $halt == 1 } {
+				catch { mww $TEST_MODE 0x80000000 }
+			} else {
+				catch { mww $TEST_MODE 0 }
+			}
+		}
+
+		$t arp_reset assert 0
+	}
+
+	$t invoke-event reset-assert-post
+	$t invoke-event reset-deassert-pre
+	if {![using_hla]} {	# workaround ST-Link v2 fails and forcing reconnect
+		$t arp_reset deassert 0
+	}
+	$t invoke-event reset-deassert-post
+
+	# Pass 1 - Now wait for any halt (requested as part of reset
+	# assert/deassert) to happen.  Ideally it takes effect without
+	# first executing any instructions.
+	if { $halt } {
+		# Now PSoC CPU should loop in system ROM
+		$t arp_waitstate running 200
+		$t arp_halt
+
+		# Catch, but ignore any errors.
+		catch { $t arp_waitstate halted 1000 }
+
+		# Did we succeed?
+		set s [$t curstate]
+
+		if { 0 != [string compare $s "halted" ] } {
+			return -code error [format "TARGET: %s - Not halted" $t]
+		}
+
+		# Check if PSoC CPU is stopped in system ROM
+		set pc [reg pc]
+		regsub {pc[^:]*: } $pc "" pc
+		if { $pc < 0x10000000 || $pc > 0x1000ffff } {
+			set hint ""
+			set family_id [psoc4_get_family_id]
+			if { $family_id == 0x93 } {
+				set hint ", use 'reset_config none'"
+			} elseif { $family_id > 0x93 } {
+				set hint ", use a KitProg adapter"
+			}
+			return -code error [format "TARGET: %s - Not halted in system ROM%s" $t $hint]
+		}
+
+		# Set registers to reset vector values
+		set value [read_memory 0x0 32 2]
+		reg pc [expr {[lindex $value 1] & 0xfffffffe}]
+		reg msp [lindex $value 0]
+
+		if { $PSOC4_TEST_MODE_WORKAROUND } {
+			catch { mww $TEST_MODE 0 }
+		}
+	}
+
+	#Pass 2 - if needed "init"
+	if { 0 == [string compare init $MODE] } {
+		set err [catch "$t arp_waitstate halted 5000"]
+
+		# Did it halt?
+		if { $err == 0 } {
+			$t invoke-event reset-init
+		}
+	}
+
+	$t invoke-event reset-end
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/psoc5lp.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/psoc5lp.cfg
new file mode 100644
index 0000000..fe44174
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/psoc5lp.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Cypress PSoC 5LP
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME psoc5lp
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPU_TAPID $CPUTAPID
+} else {
+	set _CPU_TAPID 0x4BA00477
+}
+
+if { [using_jtag] } {
+	set _CPU_DAP_ID $_CPU_TAPID
+} else {
+	set _CPU_DAP_ID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x2000
+}
+
+$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+source [find mem_helper.tcl]
+
+$_TARGETNAME configure -event reset-init {
+	# Configure Target Device (PSoC 5LP Device Programming Specification 5.2)
+
+	set PANTHER_DBG_CFG 0x4008000C
+	set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}]
+	mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0
+
+	set PM_ACT_CFG0 0x400043A0
+	mww $PM_ACT_CFG0 0xBF
+
+	set FASTCLK_IMO_CR 0x40004200
+	set FASTCLK_IMO_CR_F_RANGE_2    [expr {2 << 0}]
+	set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}]
+	mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+	cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/psoc6.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/psoc6.cfg
new file mode 100644
index 0000000..52b04f5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/psoc6.cfg
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
+# PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+source [find target/swj-dp.tcl]
+
+adapter speed 1000
+
+global _CHIPNAME
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME psoc6
+}
+
+global TARGET
+set TARGET $_CHIPNAME.cpu
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Is CM0 Debugging enabled ?
+global _ENABLE_CM0
+if { [info exists ENABLE_CM0] } {
+	set _ENABLE_CM0 $ENABLE_CM0
+} else {
+	set _ENABLE_CM0 1
+}
+
+# Is CM4 Debugging enabled ?
+global _ENABLE_CM4
+if { [info exists ENABLE_CM4] } {
+	set _ENABLE_CM4 $ENABLE_CM4
+} else {
+	set _ENABLE_CM4 1
+}
+
+global _WORKAREASIZE_CM0
+if { [info exists WORKAREASIZE_CM0] } {
+	set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
+} else {
+	set _WORKAREASIZE_CM0 0x4000
+}
+
+global _WORKAREASIZE_CM4
+if { [info exists WORKAREASIZE_CM4] } {
+	set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
+} else {
+	set _WORKAREASIZE_CM4 0x4000
+}
+
+global _WORKAREAADDR_CM0
+if { [info exists WORKAREAADDR_CM0] } {
+	set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
+} else {
+	set _WORKAREAADDR_CM0 0x08000000
+}
+
+global _WORKAREAADDR_CM4
+if { [info exists WORKAREAADDR_CM4] } {
+	set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
+} else {
+	set _WORKAREAADDR_CM4 0x08000000
+}
+
+proc init_reset { mode } {
+	global RESET_MODE
+	set RESET_MODE $mode
+
+	if {[using_jtag]} {
+		jtag arp_init-reset
+	}
+}
+
+# Utility to make 'reset halt' work as reset;halt on a target
+# It does not prevent running code after reset
+proc psoc6_deassert_post { target } {
+	# PSoC6 cleared AP registers including TAR during reset
+	# Force examine to synchronize OpenOCD target status
+	$target arp_examine
+
+	global RESET_MODE
+	global TARGET
+
+	if { $RESET_MODE ne "run" } {
+		$target arp_poll
+		$target arp_poll
+		set st [$target curstate]
+
+		if { $st eq "reset" } {
+			# we assume running state follows
+			# if reset accidentally halts, waiting is useless
+			catch { $target arp_waitstate running 100 }
+			set st [$target curstate]
+		}
+
+		if { $st eq "running" } {
+			echo "$target: Ran after reset and before halt..."
+			if { $target eq "${TARGET}.cm0" } {
+				# Try to cleanly reset whole system
+				# and halt the CM0 at entry point
+				psoc6 reset_halt
+				$target arp_waitstate halted 100
+			} else {
+				$target arp_halt
+			}
+		}
+	}
+}
+
+if { $_ENABLE_CM0 } {
+	target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1
+	${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
+
+	flash bank main_flash_cm0		psoc6 0x10000000 0 0 0 ${TARGET}.cm0
+	flash bank work_flash_cm0		psoc6 0x14000000 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_user_cm0	psoc6 0x16000800 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_nar_cm0	psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_key_cm0	psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_toc2_cm0	psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
+
+	${TARGET}.cm0 cortex_m reset_config sysresetreq
+	${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
+}
+
+if { $_ENABLE_CM4 } {
+	target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2
+	${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
+
+	flash bank main_flash_cm4		psoc6 0x10000000 0 0 0 ${TARGET}.cm4
+	flash bank work_flash_cm4		psoc6 0x14000000 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_user_cm4	psoc6 0x16000800 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_nar_cm4	psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_key_cm4	psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_toc2_cm4	psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
+
+	${TARGET}.cm4 cortex_m reset_config vectreset
+	${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
+}
+
+if { $_ENABLE_CM0 } {
+	# Use CM0+ by default on dual-core devices
+	targets ${TARGET}.cm0
+}
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pxa255.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pxa255.cfg
new file mode 100644
index 0000000..14ee13c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pxa255.cfg
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
+# This chip is now at end-of-life.  Final orders have been taken.
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME pxa255
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x69264013
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME xscale -endian $_ENDIAN \
+	-chain-position $_CHIPNAME.cpu
+
+# PXA255 comes out of reset using 3.6864 MHz oscillator.
+# Until the PLL kicks in, keep the JTAG clock slow enough
+# that we get no errors.
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
+
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
+
+# reset processing that works with PXA
+proc init_reset {mode} {
+	# assert both resets; equivalent to power-on reset
+	adapter assert trst assert srst
+
+	# drop TRST after at least 32 cycles
+	sleep 1
+	adapter deassert trst assert srst
+
+	# minimum 32 TCK cycles to wake up the controller
+	runtest 50
+
+	# now the TAP will be responsive; validate scanchain
+	jtag arp_init
+
+	# ... and take it out of reset
+	adapter deassert trst deassert srst
+}
+
+proc jtag_init {} {
+	init_reset startup
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pxa270.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pxa270.cfg
new file mode 100644
index 0000000..3121e96
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pxa270.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#Marvell/Intel PXA270 Script
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME pxa270
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+#IDs for pxa270. Are there more?
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # set useful default
+   set _CPUTAPID 0x49265013
+}
+
+if { [info exists CPUTAPID2] } {
+   set _CPUTAPID2 $CPUTAPID2
+} else {
+  # set useful default
+   set _CPUTAPID2 0x79265013
+}
+
+if { [info exists CPUTAPID3] } {
+   set _CPUTAPID2 $CPUTAPID3
+} else {
+  # set useful default
+   set _CPUTAPID3 0x89265013
+}
+
+# set adapter srst delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+adapter srst delay 260
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 250
+
+set _TARGETNAME $_CHIPNAME.cpu
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3
+
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
+# maps to PXA internal RAM. If you are using a PXA255
+# you must initialize SDRAM or leave this option off
+$_TARGETNAME configure -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pxa3xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pxa3xx.cfg
new file mode 100644
index 0000000..d670c84
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/pxa3xx.cfg
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell PXA3xx
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME pxa3xx
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# IDs for all currently known PXA3xx chips
+if { [info exists CPUTAPID_PXA30X_A0] } {
+   set _CPUTAPID_PXA30X_A0 $CPUTAPID_PXA30X_A0
+} else {
+   set _CPUTAPID_PXA30X_A0 0x0E648013
+}
+if { [info exists CPUTAPID_PXA30X_A1] } {
+   set _CPUTAPID_PXA30X_A1 $CPUTAPID_PXA30X_A1
+} else {
+   set _CPUTAPID_PXA30X_A1 0x1E648013
+}
+if { [info exists CPUTAPID_PXA31X_A0] } {
+   set _CPUTAPID_PXA31X_A0 $CPUTAPID_PXA31X_A0
+} else {
+   set _CPUTAPID_PXA31X_A0 0x0E649013
+}
+if { [info exists CPUTAPID_PXA31X_A1] } {
+   set _CPUTAPID_PXA31X_A1 $CPUTAPID_PXA31X_A1
+} else {
+   set _CPUTAPID_PXA31X_A1 0x1E649013
+}
+if { [info exists CPUTAPID_PXA31X_A2] } {
+   set _CPUTAPID_PXA31X_A2 $CPUTAPID_PXA31X_A2
+} else {
+   set _CPUTAPID_PXA31X_A2 0x2E649013
+}
+if { [info exists CPUTAPID_PXA31X_B0] } {
+   set _CPUTAPID_PXA31X_B0 $CPUTAPID_PXA31X_B0
+} else {
+   set _CPUTAPID_PXA31X_B0 0x3E649013
+}
+if { [info exists CPUTAPID_PXA32X_B1] } {
+   set _CPUTAPID_PXA32X_B1 $CPUTAPID_PXA32X_B1
+} else {
+   set _CPUTAPID_PXA32X_B1 0x5E642013
+}
+if { [info exists CPUTAPID_PXA32X_B2] } {
+   set _CPUTAPID_PXA32X_B2 $CPUTAPID_PXA32X_B2
+} else {
+   set _CPUTAPID_PXA32X_B2 0x6E642013
+}
+if { [info exists CPUTAPID_PXA32X_C0] } {
+   set _CPUTAPID_PXA32X_C0 $CPUTAPID_PXA32X_C0
+} else {
+   set _CPUTAPID_PXA32X_C0 0x7E642013
+}
+
+# set adapter srst delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+adapter srst delay 260
+
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 250
+
+set _TARGETNAME $_CHIPNAME.cpu
+jtag newtap $_CHIPNAME cpu -irlen 11 -ircapture 0x1 -irmask 0x7f \
+	-expected-id $_CPUTAPID_PXA30X_A0 \
+	-expected-id $_CPUTAPID_PXA30X_A1 \
+	-expected-id $_CPUTAPID_PXA31X_A0 \
+	-expected-id $_CPUTAPID_PXA31X_A1 \
+	-expected-id $_CPUTAPID_PXA31X_A2 \
+	-expected-id $_CPUTAPID_PXA31X_B0 \
+	-expected-id $_CPUTAPID_PXA32X_B1 \
+	-expected-id $_CPUTAPID_PXA32X_B2 \
+	-expected-id $_CPUTAPID_PXA32X_C0
+
+target create $_TARGETNAME xscale -endian $_ENDIAN \
+	-chain-position $_TARGETNAME
+
+# work area in internal RAM.
+$_TARGETNAME configure -work-area-phys 0x5c030000 -work-area-size 0x10000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/qn908x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/qn908x.cfg
new file mode 100644
index 0000000..ac3e06b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/qn908x.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP QN908x Cortex-M4F with 128 KiB SRAM
+
+source [find target/swj-dp.tcl]
+
+set CHIPNAME qn908x
+set CHIPSERIES qn9080
+if { ![info exists WORKAREASIZE] } {
+  set WORKAREASIZE 0x20000
+}
+
+# SWD IDCODE (Cortex M4).
+set CPUTAPID 0x2ba01477
+
+swj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID
+dap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu
+
+set TARGETNAME $CHIPNAME.cpu
+target create $TARGETNAME cortex_m -dap $CHIPNAME.dap
+
+# SRAM is mapped at 0x04000000.
+$TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE
+
+# flash bank  qn908x   0 0  [calc_checksum]
+# The base must be set as 0x01000000, and the size parameter is unused.
+set FLASHNAME $CHIPNAME.flash
+flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
+
+# We write directly to flash memory over this adapter interface. For debugging
+# this could in theory be faster (the Core clock on reset is normally at 32MHz),
+# but for flashing 1MHz is more reliable.
+adapter speed 1000
+
+# Delay on reset line.
+adapter srst delay 200
+
+cortex_m reset_config sysresetreq
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/qualcomm_qca4531.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/qualcomm_qca4531.cfg
new file mode 100644
index 0000000..be0c8fa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/qualcomm_qca4531.cfg
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable
+# Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT).
+#
+# Product page:
+# https://www.qualcomm.com/products/qca4531
+#
+# Notes:
+# - MIPS Processor ID (PRId): 0x00019374
+# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
+#   operating at up to 650 MHz
+# - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up
+#   to 300 MHz
+# - TRST is not available.
+# - EJTAG PrRst signal is not supported
+# - RESET_L pin B56 on the SoC will reset internal JTAG logic.
+#
+# Pins related for debug and bootstrap:
+# Name		Pin		Description
+#   JTAG
+# JTAG_TCK	GPIO0, (A27)	Software configurable, default JTAG
+# JTAG_TDI	GPIO1, (B23)	Software configurable, default JTAG
+# JTAG_TDO	GPIO2, (A28)	Software configurable, default JTAG
+# JTAG_TMS	GPIO3, (A29)	Software configurable, default JTAG
+#   Reset
+# RESET_L	-, (B56)	Input only
+# SYS_RST_L	GPIO17, (A79)	Output reset request or GPIO
+#   Bootstrap
+# JTAG_MODE	GPIO16, (A78)	0 - JTAG (Default); 1 - EJTAG
+# DDR_SELECT	GPIO10, (A57)	0 - DDR2; 1 - DDR1
+#   UART
+# UART0_SOUT	GPIO10, (A57)
+# UART0_SIN	GPIO9, (B49)
+
+# Per default we need to use "none" variant to be able properly "reset init"
+# or "reset halt" the CPU.
+reset_config none srst_pulls_trst
+
+# For SRST based variant we still need proper timings.
+# For ETH part the reset should be asserted at least for 10ms
+# Since there is no other information let's take 100ms to be sure.
+adapter srst pulse_width 100
+
+# according to the SoC documentation it should take at least 5ms from
+# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
+# to live.
+adapter srst delay 8
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME qca4531
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+# provide watchdog helper.
+proc disable_watchdog { } {
+	mww 0xb8060008 0x0
+}
+
+$_TARGETNAME configure -event halted { disable_watchdog }
+
+# Since PrRst is not supported and SRST will reset complete chip
+# with JTAG engine, we need to reset CPU from CPU itself.
+$_TARGETNAME configure -event reset-assert-pre {
+	halt
+}
+
+$_TARGETNAME configure -event reset-assert {
+	catch "mww 0xb806001C 0x01000000"
+}
+
+# To be able to trigger complete chip reset, in case JTAG is blocked
+# or CPU not responding, we still can use this helper.
+proc full_reset { } {
+	reset_config srst_only
+	reset
+	halt
+	reset_config none
+}
+
+# Section with helpers which can be used by boards
+proc qca4531_ddr2_550_550_init {} {
+	# Clear reset flags for different SoC components
+	mww 0xb806001c 0xfeceffff
+	mww 0xb806001c 0xeeceffff
+	mww 0xb806001c 0xe6ceffff
+
+	# PMU configurations
+	# Internal Switcher
+	mww 0xb8116c40 0x633c8176
+	# Increase the DDR voltage
+	mww 0xb8116c44 0x10200000
+	# XTAL Configurations
+	mww 0xb81162c0 0x4b962100
+	mww 0xb81162c4 0x480
+	mww 0xb81162c8 0x04000144
+	# Recommended PLL configurations
+	mww 0xb81161c4 0x54086000
+	mww 0xb8116244 0x54086000
+
+	# PLL init
+	mww 0xb8050008 0x0131001c
+	mww 0xb8050000 0x40001580
+	mww 0xb8050004 0x40015800
+	mww 0xb8050008 0x0131001c
+	mww 0xb8050000 0x00001580
+	mww 0xb8050004 0x00015800
+	mww 0xb8050008 0x01310000
+	mww 0xb8050044 0x781003ff
+	mww 0xb8050048 0x003c103f
+
+	# DDR2 init
+	mww 0xb8000108 0x401f0042
+	mww 0xb80000b8 0x0000166d
+	mww 0xb8000000 0xcfaaf33b
+	mww 0xb800015c 0x0000000f
+	mww 0xb8000004 0xa272efa8
+	mww 0xb8000018 0x0000ffff
+	mww 0xb80000c4 0x74444444
+	mww 0xb80000c8 0x00000444
+	mww 0xb8000004 0xa210ee28
+	mww 0xb8000004 0xa2b2e1a8
+	mww 0xb8000010 0x8
+	mww 0xb80000bc 0x0
+	mww 0xb8000010 0x10
+	mww 0xb80000c0 0x0
+	mww 0xb8000010 0x40
+	mww 0xb800000c 0x2
+	mww 0xb8000010 0x2
+	mww 0xb8000008 0xb43
+	mww 0xb8000010 0x1
+	mww 0xb8000010 0x8
+	mww 0xb8000010 0x4
+	mww 0xb8000010 0x4
+	mww 0xb8000008 0xa43
+	mww 0xb8000010 0x1
+	mww 0xb800000c 0x382
+	mww 0xb8000010 0x2
+	mww 0xb800000c 0x402
+	mww 0xb8000010 0x2
+	mww 0xb8000014 0x40be
+	mww 0xb800001C 0x20
+	mww 0xb8000020 0x20
+	mww 0xb80000cc 0xfffff
+
+	# UART GPIO programming
+	mww 0xb8040000 0xff30b
+	mww 0xb8040044 0x908
+	mww 0xb8040034 0x160000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/quark_d20xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/quark_d20xx.cfg
new file mode 100644
index 0000000..ca8f440
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/quark_d20xx.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x38289013
+}
+
+jtag newtap quark_d20xx quark -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable
+jtag newtap quark_d20xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e786013 -enable
+
+proc quark_d20xx_tapenable {} {
+	echo "enabling quark core tap"
+	irscan quark_d20xx.cltap 0x11
+	drscan quark_d20xx.cltap 12 1
+	runtest 10
+}
+
+proc quark_d20xx_tapdisable {} {
+	echo "disabling quark core tap"
+	irscan quark_d20xx.cltap 0x11
+	drscan quark_d20xx.cltap 12 0
+	runtest 10
+}
+
+proc quark_d20xx_setup {} {
+	jtag tapenable quark_d20xx.quark
+}
+
+jtag configure quark_d20xx.quark -event tap-enable \
+   "quark_d20xx_tapenable"
+
+jtag configure quark_d20xx.quark -event tap-disable \
+   "quark_d20xx_tapdisable"
+
+target create quark_d20xx.quark quark_d20xx -endian little -chain-position quark_d20xx.quark
+
+quark_d20xx.quark configure -event reset-start {
+	# need to halt the target to write to memory
+	if {[quark_d20xx.quark curstate] ne "halted"} { halt }
+	# set resetbreak via the core tap
+	irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x1
+	# trigger a warm reset
+	mww 0xb0800570 0x2
+	# clear resetbreak
+	irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x0
+}
+
+jtag configure quark_d20xx.quark -event setup \
+   "quark_d20xx_setup"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/quark_x10xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/quark_x10xx.cfg
new file mode 100644
index 0000000..6463f21
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/quark_x10xx.cfg
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME quark_x10xx
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x18289013
+}
+
+jtag newtap quark_x10xx cpu   -irlen 8  -irmask 0xff  -expected-id   $_CPUTAPID  -disable
+jtag newtap quark_x10xx cltap -irlen 8  -irmask 0xff  -expected-id   0x0e681013  -enable
+
+#openocd puts tap at front of chain not end of chain
+proc quark_x10xx_tapenable {} {
+	echo "enabling core tap"
+	irscan quark_x10xx.cltap 0x11
+	drscan quark_x10xx.cltap 64 1
+	runtest 10
+}
+
+proc quark_x10xx_tapdisable {} {
+	echo "disabling core tap"
+	irscan quark_x10xx.cltap 0x11
+	drscan quark_x10xx.cltap 64 0
+	runtest 10
+}
+
+proc quark_x10xx_setup {} {
+	jtag tapenable quark_x10xx.cpu
+}
+
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+   "quark_x10xx_tapenable"
+
+jtag configure $_CHIPNAME.cpu -event tap-disable \
+   "quark_x10xx_tapdisable"
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create quark_x10xx.cpu quark_x10xx -endian $_ENDIAN -chain-position quark_x10xx.cpu
+
+jtag configure $_CHIPNAME.cpu -event setup \
+   "quark_x10xx_setup"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/readme.txt b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/readme.txt
new file mode 100644
index 0000000..deec5b5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/readme.txt
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+Prerequisites:
+The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands
+do the same thing across all the targets.
+
+Rules to follow when writing scripts:
+
+1. The configuration script should be defined such as , for example, the following sequences are working:
+	reset
+	flash info 
+and
+	reset
+	flash erase_address  
+and
+	reset init
+	load
+
+In most cases this can be accomplished by specifying the default startup mode as reset_init (target command
+in the configuration file).
+
+2. If the target is correctly configured, flash must be writable without any other helper commands. It is
+assumed that all write-protect mechanisms should be disabled.
+
+3. The configuration scripts should be defined such as the binary that was written to flash verifies
+(turn off remapping, checksums, etc...)
+
+flash write_image [file] 
+verify_image [file] 
+
+4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked
+multiple times only the last setting is used.
+
+interface/xxx.cfg files are always executed *before* target/xxx.cfg
+files, so any adapter speed in interface/xxx.cfg will be overridden by
+target/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively,
+set the default JTAG speed.
+
+Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
+so one can create target subtype configurations where e.g. only
+amount of DRAM, oscillator speeds differ and having a single
+config file for the default/common settings.
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_r7s72100.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_r7s72100.cfg
new file mode 100644
index 0000000..dc9a1d8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_r7s72100.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ/A1H
+# https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME r7s72100
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
+
+# Configuring only one core using DAP.
+# Base addresses of cores:
+#  core 0  -  0x80030000
+set _TARGETNAME $_CHIPNAME.ca9
+dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
+target create ${_TARGETNAME} cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x80030000
+
+targets ${_TARGETNAME}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rcar_gen2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rcar_gen2.cfg
new file mode 100644
index 0000000..31ba156
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rcar_gen2.cfg
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car Generation 2 SOCs
+# - There are a combination of Cortex-A15s and Cortex-A7s for each Gen2 SOC
+# - Each SOC can boot through any of the, up to 2, core types that it has
+#   e.g. H2 can boot through Cortex-A15 or Cortex-A7
+
+# Supported Gen2 SOCs and their cores:
+# H2:  Cortex-A15 x 4, Cortex-A7 x 4
+# M2:  Cortex-A15 x 2
+# V2H: Cortex-A15 x 2
+# M2N: Cortex-A15 x 2
+# E2:                  Cortex-A7 x 2
+
+# Usage:
+# There are 2 configuration options:
+# SOC:       Selects the supported SOC. (Default 'H2')
+# BOOT_CORE: Selects the booting core. 'CA15', or 'CA7'
+#            Defaults to 'CA15' if the SOC has one, else defaults to 'CA7'
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc H2
+}
+
+# Set configuration for each SOC and the default 'BOOT_CORE'
+switch $_soc {
+	H2 {
+		set _CHIPNAME r8a7790
+		set _num_ca15 4
+		set _num_ca7 4
+		set _boot_core CA15
+	}
+	M2 {
+		set _CHIPNAME r8a7791
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	V2H {
+		set _CHIPNAME r8a7792
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	M2N {
+		set _CHIPNAME r8a7793
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	E2 {
+		set _CHIPNAME r8a7794
+		set _num_ca15 0
+		set _num_ca7 2
+		set _boot_core CA7
+	}
+	default {
+		error "'$_soc' is invalid!"
+	}
+}
+
+# If configured, override the default 'CHIPNAME'
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+}
+
+# If configured, override the default 'BOOT_CORE'
+if { [info exists BOOT_CORE] } {
+	set _boot_core $BOOT_CORE
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+echo "\t$_soc - $_num_ca15 CA15(s), $_num_ca7 CA7(s)"
+echo "\tBoot Core - $_boot_core\n"
+
+set _DAPNAME $_CHIPNAME.dap
+
+# TAP and DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
+dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+
+set CA15_DBGBASE {0x800B0000 0x800B2000 0x800B4000 0x800B6000}
+set CA7_DBGBASE  {0x800F0000 0x800F2000 0x800F4000 0x800F6000}
+
+set _targets ""
+set smp_targets ""
+
+proc setup_ca {core_name dbgbase num boot} {
+	global _CHIPNAME
+	global _DAPNAME
+	global smp_targets
+	global _targets
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $_CHIPNAME.$core_name.$_core
+		set _CTINAME $_TARGETNAME.cti
+		set _command "target create $_TARGETNAME cortex_a -dap $_DAPNAME \
+			-coreid $_core -dbgbase [lindex $dbgbase $_core]"
+		if { $_core == 0  && $boot == 1 } {
+			set _targets "$_TARGETNAME"
+		} else {
+			set _command "$_command -defer-examine"
+		}
+		set smp_targets "$smp_targets $_TARGETNAME"
+		eval $_command
+	}
+}
+
+# Organize target list based on the boot core
+if { [string equal $_boot_core CA15] } {
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 1
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 0
+} elseif { [string equal $_boot_core CA7] } {
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 1
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+} else {
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 0
+}
+
+source [find target/renesas_rcar_reset_common.cfg]
+
+eval "target smp $smp_targets"
+targets $_targets
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rcar_gen3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rcar_gen3.cfg
new file mode 100644
index 0000000..73b3003
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rcar_gen3.cfg
@@ -0,0 +1,207 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car Generation 3 SOCs
+# - There are a combination of Cortex-A57s, Cortex-A53s, and Cortex-R7 for each Gen3 SOC
+# - Each SOC can boot through any of the, up to 3, core types that it has
+#   e.g. H3 can boot through Cortex-A57, Cortex-A53, or Cortex-R7
+
+# Supported Gen3 SOCs and their cores:
+#  H3: Cortex-A57 x 4, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
+# M3W: Cortex-A57 x 2, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
+# M3N: Cortex-A57 x 2,                 Cortex-R7 x 2 (Lock-Step)
+# V3U:                 Cortex-A76 x 8, Cortex-R52 x2 (Lock-Step)
+# V3H:                 Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
+# V3M:                 Cortex-A53 x 2, Cortex-R7 x 2 (Lock-Step)
+#  E3:                 Cortex-A53 x 1, Cortex-R7 x 2 (Lock-Step)
+#  D3:                 Cortex-A53 x 1
+
+# Usage:
+# There are 2 configuration options:
+# SOC:       Selects the supported SOC. (Default 'H3')
+# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', or 'CR7'
+#            Defaults to 'CA57' if the SOC has one, else defaults to 'CA53'
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc H3
+}
+
+set _num_ca53 0
+set _num_ca57 0
+set _num_ca76 0
+set _num_cr52 0
+set _num_cr7 0
+
+# Set configuration for each SOC and the default 'BOOT_CORE'
+switch $_soc {
+	H3 {
+		set _CHIPNAME r8a77950
+		set _num_ca57 4
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+	}
+	M3W {
+		set _CHIPNAME r8a77960
+		set _num_ca57 2
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+	}
+	M3N {
+		set _CHIPNAME r8a77965
+		set _num_ca57 2
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+	}
+	V3M {
+		set _CHIPNAME r8a77970
+		set _num_ca57 0
+		set _num_ca53 2
+		set _num_cr7 1
+		set _boot_core CA53
+	}
+	V3H {
+		set _CHIPNAME r8a77980
+		set _num_ca57 0
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA53
+	}
+	E3 {
+		set _CHIPNAME r8a77990
+		set _num_ca57 0
+		set _num_ca53 1
+		set _num_cr7 1
+		set _boot_core CA53
+	}
+	D3 {
+		set _CHIPNAME r8a77995
+		set _num_ca57 0
+		set _num_ca53 1
+		set _num_cr7 0
+		set _boot_core CA53
+	}
+	V3U {
+		set _CHIPNAME r8a779a0
+		set _num_ca76 8
+		set _num_cr52 1
+		set _boot_core CA76
+	}
+	default {
+		error "'$_soc' is invalid!"
+	}
+}
+
+# If configured, override the default 'CHIPNAME'
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+}
+
+# If configured, override the default 'BOOT_CORE'
+if { [info exists BOOT_CORE] } {
+	set _boot_core $BOOT_CORE
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x5ba00477
+}
+
+echo "\t$_soc - $_num_ca76 CA76(s), $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr52 CR52(s), $_num_cr7 CR7(s)"
+echo "\tBoot Core - $_boot_core\n"
+
+set _DAPNAME $_CHIPNAME.dap
+
+# TAP and DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
+dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+
+set CA76_DBGBASE {0x81410000 0x81510000 0x81610000 0x81710000 0x81c10000 0x81d10000 0x81e10000 0x81f10000}
+set CA76_CTIBASE {0x81420000 0x81520000 0x81620000 0x81720000 0x81c20000 0x81d20000 0x81e20000 0x81f20000}
+set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
+set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
+set CR52_DBGBASE 0x80c10000
+set CR52_CTIBASE 0x80c20000
+set  CR7_DBGBASE 0x80910000
+set  CR7_CTIBASE 0x80918000
+
+set _targets ""
+set smp_targets ""
+
+proc setup_a5x {core_name dbgbase ctibase num boot} {
+	global _CHIPNAME
+	global _DAPNAME
+	global smp_targets
+	global _targets
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $_CHIPNAME.$core_name.$_core
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $_DAPNAME -ap-num 1 \
+			-baseaddr [lindex $ctibase $_core]
+		set _command "target create $_TARGETNAME aarch64 -dap $_DAPNAME \
+			-ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME"
+		if { $_core == 0  && $boot == 1 } {
+			set _targets "$_TARGETNAME"
+		} else {
+			set _command "$_command -defer-examine"
+		}
+		set smp_targets "$smp_targets $_TARGETNAME"
+		eval $_command
+	}
+}
+
+proc setup_crx {core_name dbgbase ctibase num boot} {
+	global _CHIPNAME
+	global _DAPNAME
+	global _targets
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $_CHIPNAME.$core_name
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
+		if { $core_name == "r52" } {
+			set _command "target create $_TARGETNAME armv8r -dap $_DAPNAME \
+				-ap-num 1 -dbgbase $dbgbase -cti $_CTINAME"
+		} else {
+			set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
+				-ap-num 1 -dbgbase $dbgbase"
+		}
+		if { $boot == 1 } {
+			set _targets "$_TARGETNAME"
+		} else {
+			set _command "$_command -defer-examine"
+		}
+		eval $_command
+	}
+}
+
+# Organize target list based on the boot core
+if { [string equal $_boot_core CA76] } {
+	setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 1
+	setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0
+} elseif { [string equal $_boot_core CA57] } {
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
+	setup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
+} elseif { [string equal $_boot_core CA53] } {
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
+	setup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
+} elseif { [string equal $_boot_core CR52] } {
+	setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1
+	setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 0
+} else {
+	setup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  1
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
+}
+
+source [find target/renesas_rcar_reset_common.cfg]
+
+eval "target smp $smp_targets"
+targets $_targets
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rcar_reset_common.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rcar_reset_common.cfg
new file mode 100644
index 0000000..987f0c8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rcar_reset_common.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car Gen2 Evaluation Board common settings
+
+reset_config trst_and_srst srst_nogate
+
+proc init_reset {mode} {
+    # Assert both resets: equivalent to a power-on reset
+    adapter assert trst assert srst
+
+    # Deassert TRST to begin TAP communication
+    adapter deassert trst assert srst
+
+    # TAP should now be responsive, validate the scan-chain
+    jtag arp_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rz.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rz.cfg
new file mode 100644
index 0000000..a0489de
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rz.cfg
@@ -0,0 +1,239 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ SOCs
+# - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7
+# and Cortex-M33 for each SOC
+# - Each SOC can boot through the Cortex-A5x cores or the Cortex-M33
+
+# Supported RZ SOCs and their cores:
+# RZ/G2H:   Cortex-A57 x4, Cortex-A53 x4, Cortex-R7
+# RZ/G2M:   Cortex-A57 x2, Cortex-A53 x4, Cortex-R7
+# RZ/G2N:   Cortex-A57 x2,                Cortex-R7
+# RZ/G2E:                  Cortex-A53 x2, Cortex-R7
+# RZ/G2L:                  Cortex-A55 x2, Cortex-M33
+# RZ/V2L:                  Cortex-A55 x2, Cortex-M33
+# RZ/G2LC:                 Cortex-A55 x2, Cortex-M33
+# RZ/G2UL:                 Cortex-A55 x1, Cortex-M33
+# RZ/G3S:                  Cortex-A55 x1, Cortex-M33 x2
+
+# Usage:
+# There are 2 configuration options:
+# SOC:       Selects the supported SOC. (Default 'G2L')
+# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', 'CA55' or CM33
+
+transport select jtag
+reset_config trst_and_srst srst_gates_jtag
+adapter speed 4000
+adapter srst delay 500
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc G2L
+}
+
+set _num_ca57 0
+set _num_ca55 0
+set _num_ca53 0
+set _num_cr7 0
+set _num_cm33 0
+
+# Set configuration for each SOC and the default 'BOOT_CORE'
+switch $_soc {
+	G2H {
+		set _CHIPNAME r8a774ex
+		set _num_ca57 4
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+		set _ap_num 1
+	}
+	G2M {
+		set _CHIPNAME r8a774ax
+		set _num_ca57 2
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+		set _ap_num 1
+	}
+	G2N {
+		set _CHIPNAME r8a774bx
+		set _num_ca57 2
+		set _num_ca53 0
+		set _num_cr7 1
+		set _boot_core CA57
+		set _ap_num 1
+	}
+	G2E {
+		set _CHIPNAME r8a774c0
+		set _num_ca57 0
+		set _num_ca53 2
+		set _num_cr7 1
+		set _boot_core CA53
+		set _ap_num 1
+	}
+	G2L {
+		set _CHIPNAME r9a07g044l
+		set _num_ca55 2
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	V2L {
+		set _CHIPNAME r9a07g054l
+		set _num_ca55 2
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	G2LC {
+		set _CHIPNAME r9a07g044c
+		set _num_ca55 2
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	G2UL {
+		set _CHIPNAME r9a07g043u
+		set _num_ca55 1
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	G3S {
+		set _CHIPNAME r9a08g045s
+		set _num_ca55 1
+		set _num_cm33 2
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	default {
+		error "'$_soc' is invalid!"
+	}
+}
+
+# If configured, override the default 'CHIPNAME'
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+}
+
+# If configured, override the default 'BOOT_CORE'
+if { [info exists BOOT_CORE] } {
+	set _boot_core $BOOT_CORE
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x6ba00477
+}
+
+echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), \
+	$_num_cr7 CR7(s), $_num_cm33 CM33(s)"
+echo "\tBoot Core - $_boot_core\n"
+
+set _DAPNAME $_CHIPNAME.dap
+
+
+# TAP and DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -ignore-version
+dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+echo "$_CHIPNAME.cpu"
+
+set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+set CA55_DBGBASE {0x10E10000 0x10F10000}
+set CA55_CTIBASE {0x10E20000 0x10F20000}
+set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
+set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
+set  CR7_DBGBASE 0x80910000
+set  CR7_CTIBASE 0x80918000
+set CM33_DBGBASE {0xE000E000 0xE010E000}
+set CM33_CTIBASE {0xE0042000 0xE0142000}
+
+set smp_targets ""
+
+proc setup_a5x {core_name dbgbase ctibase num boot} {
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $::_CHIPNAME.$core_name.$_core
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \
+			-baseaddr [lindex $ctibase $_core]
+		target create $_TARGETNAME aarch64 -dap $::_DAPNAME \
+			-ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] \
+			-cti $_CTINAME
+		if { $_core > 0 || $boot == 0 } {
+			$_TARGETNAME configure -defer-examine
+		}
+		set ::smp_targets "$::smp_targets $_TARGETNAME"
+	}
+}
+
+proc setup_cr7 {dbgbase ctibase} {
+	set _TARGETNAME $::_CHIPNAME.r7
+	set _CTINAME $_TARGETNAME.cti
+	cti create $_CTINAME -dap $::_DAPNAME -ap-num 1 -baseaddr $ctibase
+	target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \
+		-ap-num 1 -dbgbase $dbgbase -defer-examine
+}
+proc setup_cm33 {dbgbase ctibase num boot} {
+	if { $::_soc == "G2L" || $::_soc == "V2L" \
+	|| $::_soc == "G2LC" || $::_soc == "G2UL" } {
+		set _ap_num  2
+	} elseif { $::_soc == "G3S" } {
+		set _ap_num  3
+	}
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		if { $num <= 1 } {
+			set _TARGETNAME $::_CHIPNAME.m33
+		} else {
+			set _TARGETNAME $::_CHIPNAME.m33.$_core
+		}
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $::_DAPNAME -ap-num $_ap_num \
+			-baseaddr [lindex $ctibase $_core]
+		target create $_TARGETNAME cortex_m -dap $::_DAPNAME \
+			-ap-num $_ap_num -dbgbase [lindex $dbgbase $_core]
+		if { $boot == 0 } {
+			$_TARGETNAME configure -defer-examine
+		}
+		incr $_ap_num
+	}
+}
+
+# Organize target list based on the boot core
+if { $_boot_core == "CA57" } {
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
+	setup_cr7 $CR7_DBGBASE $CR7_CTIBASE
+} elseif { $_boot_core == "CA53" } {
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
+	setup_cr7 $CR7_DBGBASE $CR7_CTIBASE
+} elseif { $_boot_core == "CA55" } {
+	setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1
+	setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 0
+} elseif { $_boot_core == "CM33" } {
+	setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 0
+	setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 1
+}
+
+echo "SMP targets:$smp_targets"
+eval "target smp $smp_targets"
+
+if { $_soc == "G2L" || $_soc == "V2L" || $_soc == "G2LC" \
+|| $_soc == "G2UL" || $_soc == "G3S"} {
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1
+}
+
+proc init_reset {mode} {
+    # Assert both resets: equivalent to a power-on reset
+    adapter assert trst assert srst
+
+    # Deassert TRST to begin TAP communication
+    adapter deassert trst assert srst
+
+    # TAP should now be responsive, validate the scan-chain
+    jtag arp_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rz_five.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rz_five.cfg
new file mode 100644
index 0000000..5ab94ab
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_rz_five.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ/Five SoC
+#
+# General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz)
+
+transport select jtag
+
+reset_config trst_and_srst srst_gates_jtag
+adapter speed 4000
+adapter srst delay 500
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME r9A07g043u
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_s7g2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_s7g2.cfg
new file mode 100644
index 0000000..fa9c579
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/renesas_s7g2.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Renesas Synergy S7 G2 w/ ARM Cortex-M4 @ 240 MHz
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME s7g2
+}
+
+if { [info exists CPU_JTAG_TAPID] } {
+	set _CPU_JTAG_TAPID $CPU_JTAG_TAPID
+} else {
+	set _CPU_JTAG_TAPID 0x5ba00477
+}
+
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x5ba02477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+	set _CPU_TAPID $_CPU_JTAG_TAPID
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	# 640 KB On-Chip SRAM
+	set _WORKAREASIZE 0xa0000
+}
+
+$_TARGETNAME configure -work-area-phys 0x1ffe0000 \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rk3308.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rk3308.cfg
new file mode 100644
index 0000000..b6086f1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rk3308.cfg
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Rockchip RK3308 Target
+# https://rockchip.fr/RK3308%20datasheet%20V1.5.pdf
+# https://dl.radxa.com/rockpis/docs/hw/datasheets/Rockchip%20RK3308TRM%20V1.1%20Part1-20180810.pdf
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME rk3308
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x2ba01477
+}
+
+adapter speed 12000
+
+transport select swd
+
+# declare the one SWD tap to access the DAP
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# declare the 4 main application cores
+set _TARGETNAME $_CHIPNAME.core
+set _smp_command ""
+
+set $_TARGETNAME.base(0) 0x81010000
+set $_TARGETNAME.base(1) 0x81012000
+set $_TARGETNAME.base(2) 0x81014000
+set $_TARGETNAME.base(3) 0x81016000
+
+set $_TARGETNAME.cti(0) 0x81018000
+set $_TARGETNAME.cti(1) 0x81019000
+set $_TARGETNAME.cti(2) 0x8101a000
+set $_TARGETNAME.cti(3) 0x8101b000
+
+set _cores 4
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
+                         -dbgbase [set $_TARGETNAME.base($_core)]"
+
+    if { $_core != 0 } {
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+        set _command "$_command -defer-examine"
+    } else {
+        # uncomment to use hardware threads pseudo rtos
+        # set _command "$_command -rtos hwthread"
+        set _command "$_command -work-area-size 0x40000 -work-area-phys 0xfff80000 \
+                                -work-area-backup 0"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+targets ${_TARGETNAME}0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rk3399.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rk3399.cfg
new file mode 100644
index 0000000..1e90414
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rk3399.cfg
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Rockchip RK3399 Target
+# https://rockchip.fr/RK3399%20datasheet%20V1.8.pdf
+# https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.4%20Part1.pdf
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME rk3399
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x5ba02477
+}
+
+adapter speed 12000
+
+transport select swd
+
+# declare the one SWD tap to access the DAP
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+set _TARGETNAME $_CHIPNAME.lcore
+# declare the 6 main application cores
+set _smp_command ""
+
+set $_TARGETNAME.base(0) 0x80030000
+set $_TARGETNAME.base(1) 0x80032000
+set $_TARGETNAME.base(2) 0x80034000
+set $_TARGETNAME.base(3) 0x80036000
+set $_TARGETNAME.cti(0) 0x80038000
+set $_TARGETNAME.cti(1) 0x80039000
+set $_TARGETNAME.cti(2) 0x8003a000
+set $_TARGETNAME.cti(3) 0x8003b000
+
+
+set _TARGETNAME $_CHIPNAME.bcore
+set $_TARGETNAME.base(4) 0x80210000
+set $_TARGETNAME.base(5) 0x80310000
+set $_TARGETNAME.cti(4) 0x80220000
+set $_TARGETNAME.cti(5) 0x80320000
+
+set _cores 6
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+    if {$_core < 4} {
+        set _TARGETNAME $_CHIPNAME.lcore
+    } else {
+        set _TARGETNAME $_CHIPNAME.bcore
+    }
+
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 1
+
+    target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
+                         -dbgbase [set $_TARGETNAME.base($_core)]
+
+    if { $_core != 0 } {
+        ${_TARGETNAME}$_core configure -defer-examine
+    } else {
+        # uncomment to use hardware threads pseudo rtos
+        # ${_TARGETNAME}$_core configure -rtos hwthread"
+        ${_TARGETNAME}$_core configure -work-area-size 0x30000 -work-area-phys 0xff8c0000 \
+                                -work-area-backup 0
+    }
+    set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+}
+
+target smp $_smp_command
+
+targets rk3399.lcore0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rp2040.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rp2040.cfg
new file mode 100644
index 0000000..5e78c69
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rp2040.cfg
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# RP2040 is a microcontroller with dual Cortex-M0+ core.
+# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html
+
+# The device requires multidrop SWD for debug.
+transport select swd
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME rp2040
+}
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x01002927
+}
+
+# Set to '1' to start rescue mode
+if { [info exists RESCUE] } {
+	set _RESCUE $RESCUE
+} else {
+	set _RESCUE 0
+}
+
+# Set to '0' or '1' for single core configuration, 'SMP' for -rtos hwthread
+# handling of both cores, anything else for isolated debugging of both cores
+if { [info exists USE_CORE] } {
+	set _USE_CORE $USE_CORE
+} else {
+	set _USE_CORE SMP
+}
+set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }]
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+# The rescue debug port uses the DP CTRL/STAT bit DBGPWRUPREQ to reset the
+# PSM (power on state machine) of the RP2040 with a flag set in the
+# VREG_AND_POR_CHIP_RESET register. Once the reset is released
+# (by clearing the DBGPWRUPREQ flag), the bootrom will run, see this flag,
+# and halt. Allowing the user to load some fresh code, rather than loading
+# the potentially broken code stored in flash
+if { $_RESCUE } {
+	dap create $_CHIPNAME.rescue_dap -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0xf -ignore-syspwrupack
+	init
+
+	# Clear DBGPWRUPREQ
+	$_CHIPNAME.rescue_dap dpreg 0x4 0x00000000
+
+	# Verifying CTRL/STAT is 0
+	set _CTRLSTAT [$_CHIPNAME.rescue_dap dpreg 0x4]
+	if {[expr {$_CTRLSTAT & 0xf0000000}]} {
+		echo "Rescue failed, DP CTRL/STAT readback $_CTRLSTAT"
+	} else {
+		echo "Now restart OpenOCD without RESCUE flag and load code to RP2040"
+	}
+	shutdown
+}
+
+# core 0
+if { $_USE_CORE != 1 } {
+	dap create $_CHIPNAME.dap0 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0
+	set _TARGETNAME_0 $_CHIPNAME.core0
+	target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0
+	# srst does not exist; use SYSRESETREQ to perform a soft reset
+	$_TARGETNAME_0 cortex_m reset_config sysresetreq
+}
+
+# core 1
+if { $_USE_CORE != 0 } {
+	dap create $_CHIPNAME.dap1 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 1
+	set _TARGETNAME_1 $_CHIPNAME.core1
+	target create $_TARGETNAME_1 cortex_m -dap $_CHIPNAME.dap1 -coreid 1
+	$_TARGETNAME_1 cortex_m reset_config sysresetreq
+}
+
+if {[string compare $_USE_CORE SMP] == 0} {
+	$_TARGETNAME_0 configure  -rtos hwthread
+	$_TARGETNAME_1 configure  -rtos hwthread
+	target smp $_TARGETNAME_0 $_TARGETNAME_1
+}
+
+if { $_USE_CORE == 1 } {
+	set _FLASH_TARGET $_TARGETNAME_1
+} else {
+	set _FLASH_TARGET $_TARGETNAME_0
+}
+# Backup the work area. The flash probe runs an algorithm on the target CPU.
+# The flash is probed during gdb connect if gdb memory_map is enabled (by default).
+$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET
+
+if { $_BOTH_CORES } {
+	# Alias to ensure gdb connecting to core 1 gets the correct memory map
+	flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME
+
+	# Select core 0
+	targets $_TARGETNAME_0
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rsl10.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rsl10.cfg
new file mode 100644
index 0000000..f4692cc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rsl10.cfg
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# RSL10: ARM Cortex-M3
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME rsl10
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# TODO: configure reset
+# reset_config srst_only srst_nogate connect_assert_srst
+
+$_TARGETNAME configure -event examine-fail rsl10_lock_warning
+
+proc rsl10_check_connection {} {
+    set target [target current]
+    set dap [$target cget -dap]
+
+	set IDR [$dap apreg 0 0xfc]
+	if {$IDR != 0x24770011} {
+		echo "Error: Cannot access RSL10 AP, maybe connection problem!"
+		return 1
+	}
+    return 0
+}
+
+proc rsl10_lock_warning {} {
+    if {[rsl10_check_connection]} {return}
+
+    poll off
+    echo "****** WARNING ******"
+    echo "RSL10 device probably has lock engaged."
+    echo "Debug access is denied."
+    echo "Use 'rsl10 unlock key1 key2 key3 key4' to erase and unlock the device."
+    echo "****** ....... ******"
+    echo ""
+}
+
+flash bank $_CHIPNAME.main rsl10 0x00100000 0x60000 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvr1 rsl10 0x00080000 0x800 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvr2 rsl10 0x00080800 0x800 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvr3 rsl10 0x00081000 0x800 0 0 $_TARGETNAME
+
+# TODO: implement flashing for nvr4
+# flash bank $_CHIPNAME.nvr4 rsl10 0x00081800 0x400 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rtl872xd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rtl872xd.cfg
new file mode 100644
index 0000000..65730e2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/rtl872xd.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+# Realtek RTL872xD (ARM Cortex-M33 + M23, wifi+bt dualband soc)
+
+# HLA does not support AP other than 0
+if { [using_hla] } {
+        echo "ERROR: HLA transport cannot work with this target."
+        shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+        set _CHIPNAME $CHIPNAME
+} else {
+        set _CHIPNAME rtl872xd
+}
+
+if { [info exists CPUTAPID] } {
+        set _CPUTAPID $CPUTAPID
+} else {
+        set _CPUTAPID 0x6ba02477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME.km0 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+target create $_TARGETNAME.km4 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 2
+
+cortex_m reset_config sysresetreq
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/s32k.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/s32k.cfg
new file mode 100644
index 0000000..3ff3239
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/s32k.cfg
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale S32K devices
+# Similar to Kinetis Kx series devices.
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME s32k
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x0995001d
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.pflash
+flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME -s32k
+kinetis create_banks
+
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {[using_hla]} {
+   echo ""
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions."
+   echo " A high level adapter (like a ST-Link) you are currently using cannot access"
+   echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your"
+   echo " configuration. Also security locked state of the device will not be reported."
+   echo " Expect problems connecting to a blank device without boot ROM."
+   echo ""
+   echo " Be very careful as you can lock the device though there is no way to unlock"
+   echo " it without mass erase. Don't set write protection on the first block."
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo ""
+} else {
+   # Detect secured MCU or boot lock-up in RESET/WDOG loop
+   $_TARGETNAME configure -event examine-fail {
+      kinetis mdm check_security
+   }
+   # During RESET/WDOG loop the target is sometimes falsely examined
+   $_TARGETNAME configure -event examine-end {
+      kinetis mdm check_security
+   }
+
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+# Disable watchdog not to disturb OpenOCD algorithms running on MCU
+# (e.g. armv7m_checksum_memory() in verify_image)
+# Flash driver also disables watchdog before FTFA flash programming.
+$_TARGETNAME configure -event reset-init {
+   kinetis disable_wdog
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c2410.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c2410.cfg
new file mode 100644
index 0000000..5a04871
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c2410.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Found on the 'TinCanTools' Hammer board.
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME s3c2410
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # This config file was defaulting to big endian..
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # Force an error until we get a good number.
+   set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that cannot set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c2440.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c2440.cfg
new file mode 100644
index 0000000..d976a8e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c2440.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Samsung 2440 system on chip
+# Tested on a S3C2440 Evaluation board by keesj
+# Processor       : ARM920Tid(wb) rev 0 (v4l)
+# Info:   JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME s3c2440
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a bigendian
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0032409d
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
+
+#reset configuration
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c2450.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c2450.cfg
new file mode 100644
index 0000000..801e1bc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c2450.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Samsung 2450 system on chip
+# Processor       : ARM926ejs (wb) rev 0 (v4l)
+# Info:   JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F
+
+
+# FIX!!! what to use here?
+#
+# RCLK?
+#
+# adapter speed 0
+#
+# Really low clock during reset?
+#
+# adapter speed 1
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME s3c2450
+}
+
+if { [info exists ENDIAN] } {
+  set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+  set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+  set _CPUTAPID $CPUTAPID
+} else {
+  set _CPUTAPID 0x07926f0f
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# FIX!!!!! should this really use srst_pulls_trst?
+# With srst_pulls_trst "reset halt" will not reset into the
+# halted mode, but rather "reset run" and then halt the target.
+#
+# However, without "srst_pulls_trst", then "reset halt" produces weird
+# errors:
+# WARNING: unknown debug reason: 0x0
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c4510.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c4510.cfg
new file mode 100644
index 0000000..45bed2f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c4510.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME s3c4510
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+
+# This appears to be a "Version 1" arm7tdmi.
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c6410.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c6410.cfg
new file mode 100644
index 0000000..c157458
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/samsung_s3c6410.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# -*- tcl -*-
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a SMDK6410
+# Processor       : ARM1176
+# Info:   JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
+# [and I do not believe it to be accurate, hence the 0xffffffff below]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME s3c6410
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a bigendian
+   set _ENDIAN little
+}
+
+# trace buffer
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x2b900f0f
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07b76f0f
+}
+
+#jtag scan chain
+
+jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETBTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+#reset configuration
+reset_config trst_and_srst
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/sharp_lh79532.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/sharp_lh79532.cfg
new file mode 100644
index 0000000..af6ceab
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/sharp_lh79532.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lh79532
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # sharp changed the number!
+   set _CPUTAPID 0x00002061
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/sim3x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/sim3x.cfg
new file mode 100644
index 0000000..e6bea70
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/sim3x.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Silicon Laboratories SiM3x Cortex-M3
+#
+
+# SiM3x devices support both JTAG and SWD transports.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME SiM3x
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+if { [info exists CPURAMSIZE] } {
+  set _CPURAMSIZE $CPURAMSIZE
+} else {
+# Minimum size of RAM in the Silicon Labs product matrix (8KB)
+	set _CPURAMSIZE 0x2000
+}
+
+if { [info exists CPUROMSIZE] } {
+  set _CPUROMSIZE $CPUROMSIZE
+} else {
+# Minimum size of FLASH in the Silicon Labs product matrix (32KB)
+	set _CPUROMSIZE 0x8000
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE $_CPURAMSIZE
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/smp8634.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/smp8634.cfg
new file mode 100644
index 0000000..0e609d8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/smp8634.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Sigma Designs SMP8634 (eventually even SMP8635)
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME smp8634
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x08630001
+}
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+reset_config trst_and_srst separate
+
+# jtag scan chain
+# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/snps_em_sk_fpga.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/snps_em_sk_fpga.cfg
new file mode 100644
index 0000000..62f4dec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/snps_em_sk_fpga.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2014-2015,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Xilinx Spartan-6 XC6SLX45  FPGA on EM Starter Kit v1.
+# Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2.
+#
+
+source [find cpu/arc/em.tcl]
+
+set _CHIPNAME arc-em
+set _TARGETNAME $_CHIPNAME.cpu
+
+# EM SK IDENTITY is 0x200444b1
+# EM SK v2 IDENTITY is 0x200044b1
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \
+  -expected-id 0x200044b1
+
+set _coreid 0
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
+  -coreid 0 -dbgbase $_dbgbase -endian little
+
+# There is no SRST, so do a software reset
+$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
+
+arc_em_init_regs
+
+# vim:ft=tcl
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/snps_hsdk.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/snps_hsdk.cfg
new file mode 100644
index 0000000..b4f3684
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/snps_hsdk.cfg
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2019,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# HS Development Kit SoC.
+#
+# Contains quad-core ARC HS38.
+#
+
+source [find cpu/arc/hs.tcl]
+
+set _coreid 0
+set _dbgbase [expr {$_coreid << 13}]
+
+# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
+# OpenOCD is concerned EM and HS are identical.
+set _CHIPNAME arc-em
+
+# OpenOCD discovers JTAG TAPs in reverse order.
+
+# ARC HS38 core 4
+set _TARGETNAME $_CHIPNAME.cpu4
+jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+# Flush L2$.
+$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {$_coreid << 13}]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 4.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 3
+set _TARGETNAME $_CHIPNAME.cpu3
+jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {$_coreid << 13}]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 3.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 2
+set _TARGETNAME $_CHIPNAME.cpu2
+jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {$_coreid << 13}]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 2.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 1
+set _TARGETNAME $_CHIPNAME.cpu1
+jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 1.
+$_TARGETNAME arc cache l2 auto 1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/snps_hsdk_4xd.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/snps_hsdk_4xd.cfg
new file mode 100644
index 0000000..1520e3d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/snps_hsdk_4xd.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Copyright (C) 2023 Synopsys, Inc.
+# Artemiy Volkov 
+
+# Adapted from tcl/target/snps_hsdk.cfg.
+
+#
+# HS Development Kit SoC.
+#
+# Contains quad-core ARC HS47D.
+#
+
+source [find cpu/arc/hs.tcl]
+
+set _coreid 0
+set _dbgbase [expr {$_coreid << 13}]
+
+# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
+# OpenOCD is concerned EM and HS are identical.
+set _CHIPNAME arc-em
+
+
+proc setup_cpu {core_index expected_id} {
+	global _coreid
+	global _dbgbase
+	global _CHIPNAME
+
+	set _TARGETNAME $_CHIPNAME.cpu$core_index
+	jtag newtap $_CHIPNAME cpu$core_index -irlen 4 -ircapture 0x1 -expected-id $expected_id
+
+	target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+	$_TARGETNAME configure -coreid $_coreid
+	$_TARGETNAME configure -dbgbase $_dbgbase
+	$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
+
+	arc_hs_init_regs
+
+	$_TARGETNAME arc cache l2 auto 1
+
+	set _coreid [expr {$_coreid + 1}]
+	set _dbgbase [expr {$_coreid << 13}]
+}
+
+# OpenOCD discovers JTAG TAPs in reverse order.
+
+setup_cpu 4 0x100c54b1
+setup_cpu 3 0x100854b1
+setup_cpu 2 0x100454b1
+setup_cpu 1 0x100054b1
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/spacemit-k1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/spacemit-k1.cfg
new file mode 100644
index 0000000..ef5d783
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/spacemit-k1.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# SpacemiT Key Stone K1 target
+#
+# https://www.spacemit.com/key-stone-k1
+#
+
+transport select jtag
+
+adapter speed 2000
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME k1
+}
+
+if { [info exists CORES] } {
+    set _cores $CORES
+} else {
+    set _cores 1
+}
+
+if { [info exists SECJTAG] } {
+    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21
+} else {
+    jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable
+    jtag configure pre.unknown -event tap-enable ""
+
+    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21 -disable
+    jtag configure $_CHIPNAME.cpu -event tap-enable ""
+
+    jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version
+
+    jtag configure post.unknown -event setup {
+        global _CHIPNAME
+
+        irscan post.unknown 0x98
+        drscan post.unknown 16 0xa
+
+        jtag tapenable pre.unknown
+        jtag tapenable $_CHIPNAME.cpu
+    }
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+set DBGBASE {0x0 0x400}
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+    target create $_TARGETNAME.$_core riscv -chain-position $_TARGETNAME \
+        -coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr {$_core / 4}]]
+
+    if { [expr {$_core % 4}] == 0 } {
+        $_TARGETNAME.$_core configure -rtos hwthread
+    }
+
+    set _smp_command "$_smp_command $_TARGETNAME.$_core"
+}
+
+eval $_smp_command
+
+set _SPEED 8000
+
+$_TARGETNAME.0 configure -event examine-start {
+    adapter speed $_SPEED
+    puts [ adapter speed ]
+}
+
+foreach t [target names] {
+    # $t riscv set_mem_access sysbus progbuf
+    $t riscv set_mem_access progbuf
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/spear3xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/spear3xx.cfg
new file mode 100644
index 0000000..1261cd4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/spear3xx.cfg
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the ST SPEAr3xx family of system on chip
+# Supported SPEAr300, SPEAr310, SPEAr320
+# http://www.st.com/spear
+#
+# Processor: ARM926ejs
+# Info:      JTAG tap: spear3xx.cpu tap/device found: 0x07926041
+# Date:      2009-10-31
+# Author:    Antonio Borneo 
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME spear3xx
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x07926041
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x03 \
+	-expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN \
+	-chain-position $_TARGETNAME
+
+# SPEAr3xx has a 8K block of sram @ 0xd280.0000
+# REVISIT: what OS puts virtual address equal to phys?
+$_TARGETNAME configure \
+	-work-area-virt 0xd2800000 \
+	-work-area-phys 0xd2800000 \
+	-work-area-size 0x2000 \
+	-work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stellaris.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stellaris.cfg
new file mode 100644
index 0000000..3cd91eb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stellaris.cfg
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TI/Luminary Stellaris LM3S chip family
+
+# Some devices have errata in returning their device class.
+# DEVICECLASS is provided as a manual override
+# Manual setting of a device class of 0xff is not allowed
+
+global _DEVICECLASS
+
+if { [info exists DEVICECLASS] } {
+   set _DEVICECLASS $DEVICECLASS
+} else {
+   set _DEVICECLASS 0xff
+}
+
+# Luminary chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# For now we ignore the SPI and UART options, which
+# are usable only for ISP style initial flash programming.
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lm3s
+}
+
+# CPU TAP ID 0x1ba00477 for early Sandstorm parts
+# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
+# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
+# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
+# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
+# ... we'll ignore the JTAG version field, rather than list every
+# chip revision that turns up.
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0ba00477
+}
+
+# SWD DAP, and JTAG TAP, take same params for now;
+# ... even though SWD ignores all except TAPID, and
+# JTAG shouldn't need anything more then irlen. (and TAPID).
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
+    -expected-id $_CPUTAPID -ignore-version
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   # default to 2K working area
+   set _WORKAREASIZE 0x800
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# 8K working area at base of ram, not backed up
+#
+# NOTE: you may need or want to reconfigure the work area;
+# some parts have just 6K, and you may want to use other
+# addresses (at end of mem not beginning) or back it up.
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
+
+# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
+# LM3S parts don't support RTCK
+#
+# NOTE: this may be increased by a reset-init handler, after it
+# configures and enables the PLL.  Or you might need to decrease
+# this, if you're using a slower clock.
+adapter speed 500
+
+source [find mem_helper.tcl]
+
+proc reset_peripherals {family} {
+
+	source [find chip/ti/lm3s/lm3s.tcl]
+
+	echo "Resetting Core Peripherals"
+
+	# Disable the PLL and the system clock divider (nop if disabled)
+	mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
+	mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
+
+	# RCC and RCC2 to their reset values
+	mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]
+	mww $SYSCTL_RCC2 0x07806810
+	mww $SYSCTL_RCC 0x078e3ad1
+
+	# Reset the deep sleep clock configuration register
+	mww $SYSCTL_DSLPCLKCFG 0x07800000
+
+	# Reset the clock gating registers
+	mww $SYSCTL_RCGC0 0x00000040
+	mww $SYSCTL_RCGC1 0
+	mww $SYSCTL_RCGC2 0
+	mww $SYSCTL_SCGC0 0x00000040
+	mww $SYSCTL_SCGC1 0
+	mww $SYSCTL_SCGC2 0
+	mww $SYSCTL_DCGC0 0x00000040
+	mww $SYSCTL_DCGC1 0
+	mww $SYSCTL_DCGC2 0
+
+	# Reset the remaining SysCtl registers
+	mww $SYSCTL_PBORCTL 0
+	mww $SYSCTL_IMC 0
+	mww $SYSCTL_GPIOHBCTL 0
+	mww $SYSCTL_MOSCCTL 0
+	mww $SYSCTL_PIOSCCAL 0
+	mww $SYSCTL_I2SMCLKCFG 0
+
+	# Reset the peripherals
+	mww $SYSCTL_SRCR0 0xffffffff
+	mww $SYSCTL_SRCR1 0xffffffff
+	mww $SYSCTL_SRCR2 0xffffffff
+	mww $SYSCTL_SRCR0 0
+	mww $SYSCTL_SRCR1 0
+	mww $SYSCTL_SRCR2 0
+
+	# Clear any pending SysCtl interrupts
+	mww $SYSCTL_MISC 0xffffffff
+
+	# Wait for any pending flash operations to complete
+	while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }
+	while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }
+
+	# Reset the flash controller registers
+	mww $FLASH_FMA 0
+	mww $FLASH_FCIM 0
+	mww $FLASH_FCMISC 0xffffffff
+	mww $FLASH_FWBVAL 0
+}
+
+$_TARGETNAME configure -event reset-start {
+	adapter speed 500
+
+	#
+	# When nRST is asserted on most Stellaris devices, it clears some of
+	# the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
+	# and OpenOCD depends on those TRMs.  So we won't use SRST on those
+	# chips.  (Only power-on reset should affect debug state, beyond a
+	# few specified bits; not the chip's nRST input, wired to SRST.)
+	#
+	# REVISIT current errata specs don't seem to cover this issue.
+	# Do we have more details than this email?
+	#   https://lists.berlios.de/pipermail
+	#	/openocd-development/2008-August/003065.html
+	#
+
+	global _DEVICECLASS
+
+	if {$_DEVICECLASS != 0xff} {
+	   set device_class $_DEVICECLASS
+	} else {
+	   set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]
+	}
+
+	if {$device_class == 0 || $device_class == 1 ||
+		$device_class == 3 || $device_class == 5 || $device_class == 0xa} {
+		if {![using_hla]} {
+		   # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
+		   cortex_m reset_config sysresetreq
+		}
+	} else {
+		if {![using_hla]} {
+		   # Tempest and Firestorm default to using NVIC VECTRESET
+		   # peripherals will need resetting manually, see proc reset_peripherals
+		   cortex_m reset_config vectreset
+		}
+		# reset peripherals, based on code in
+		# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
+		reset_peripherals $device_class
+	}
+}
+
+# flash configuration ... autodetects sizes, autoprobed
+flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32c0x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32c0x.cfg
new file mode 100644
index 0000000..d015120
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32c0x.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32c0x family
+#
+# stm32c0 devices support SWD transports only.
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32c0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 6kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1800
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # SWD IDCODE (single drop, arm)
+   set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable DBGMCU clock
+	# RCC_APB1ENR |= DBGMCUEN
+	mmw 0x4002103C 0x08000000 0
+
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f0x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f0x.cfg
new file mode 100644
index 0000000..5b8954e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f0x.cfg
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f0x family
+
+#
+# stm32 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+	set _FLASH_SIZE $FLASH_SIZE
+} else {
+	# autodetect size
+	set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0091
+  # Section 29.5.3
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32f0x_default_reset_start {} {
+	# Reset clock is HSI (8 MHz)
+	adapter speed 1000
+}
+
+proc stm32f0x_default_examine_end {} {
+	# Enable debug during low power modes (uses more power)
+	mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+
+	# Stop watchdog counters during halt
+	mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f0x_default_reset_init {} {
+	# Configure PLL to boost clock to HSI x 6 (48 MHz)
+	mww 0x40021004 0x00100000   ;# RCC_CFGR = PLLMUL[2]
+	mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
+	mww 0x40022000 0x00000011   ;# FLASH_ACR = PRFTBE | LATENCY[0]
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+	# Boost JTAG frequency
+	adapter speed 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f1x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f1x.cfg
new file mode 100644
index 0000000..53e81a5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f1x.cfg
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f1x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f1x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB (as found on some STM32F100s)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0008 Section 26.6.3
+      set _CPUTAPID 0x3ba00477
+   } {
+      # this is the SW-DP tap id not the jtag tap id
+      set _CPUTAPID 0x1ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000307 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f2x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f2x.cfg
new file mode 100644
index 0000000..f475826
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f2x.cfg
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f2x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f2x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0033
+      # Section 32.6.3 - corresponds to Cortex-M3 r2p0
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f3x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f3x.cfg
new file mode 100644
index 0000000..aa978d9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f3x.cfg
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f3x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f3x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+   set _FLASH_SIZE $FLASH_SIZE
+} else {
+   # autodetect size
+   set _FLASH_SIZE 0
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0316
+      # Section 29.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32f3x_default_reset_start {} {
+	# Reset clock is HSI (8 MHz)
+	adapter speed 1000
+}
+
+proc stm32f3x_default_examine_end {} {
+	# Enable debug during low power modes (uses more power)
+	mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+
+	# Stop watchdog counters during halt
+	mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f3x_default_reset_init {} {
+	# Configure PLL to boost clock to HSI x 8 (64 MHz)
+	mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+	mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
+	mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+	# Boost JTAG frequency
+	adapter speed 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xe0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f4x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f4x.cfg
new file mode 100644
index 0000000..35d8275
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f4x.cfg
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f4x family
+
+#
+# stm32f4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 32kB (Available RAM in smallest device STM32F410)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0090
+      # Section 38.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
+	targets $_chipname.cpu
+
+	if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+		switch [$_chipname.tpiu cget -port-width] {
+			1 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
+				mmw 0xE0042004 0x00000060 0x000000c0
+				mmw 0x40021020 0x00000000 0x0000ff00
+				mmw 0x40021000 0x000000a0 0x000000f0
+				mmw 0x40021008 0x000000f0 0x00000000
+			  }
+			2 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
+				mmw 0xE0042004 0x000000a0 0x000000c0
+				mmw 0x40021020 0x00000000 0x000fff00
+				mmw 0x40021000 0x000002a0 0x000003f0
+				mmw 0x40021008 0x000003f0 0x00000000
+			  }
+			4 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
+				mmw 0xE0042004 0x000000e0 0x000000c0
+				mmw 0x40021020 0x00000000 0x0fffff00
+				mmw 0x40021000 0x00002aa0 0x00003ff0
+				mmw 0x40021008 0x00003ff0 0x00000000
+			  }
+		}
+	} else {
+		# Set TRACE_IOEN; TRACE_MODE to async
+		mmw 0xE0042004 0x00000020 0x000000c0
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
+
+$_TARGETNAME configure -event reset-init {
+	# Configure PLL to boost clock to HSI x 4 (64 MHz)
+	mww 0x40023804 0x08012008   ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
+	mww 0x40023C00 0x00000102   ;# FLASH_ACR = PRFTBE | 2(Latency)
+	mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
+	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
+
+	# Boost JTAG frequency
+	adapter speed 8000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reduce speed since CPU speed will slow down to 16MHz with the reset
+	adapter speed 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f7x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f7x.cfg
new file mode 100644
index 0000000..3782b9a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32f7x.cfg
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f7x family
+
+#
+# stm32f7 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f7x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 128kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x20000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0385
+      # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
+      set _CPUTAPID 0x5ba00477
+   } {
+      set _CPUTAPID 0x5ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
+
+# On the STM32F7, the Flash is mapped at address 0x08000000 via the AXI and
+# also address 0x00200000 via the ITCM. The former mapping is read-write in
+# hardware, while the latter is read-only. By presenting an alias, we
+# accomplish two things:
+# (1) We allow writing at 0x00200000 (because the alias acts identically to the
+#     original bank), which allows code intended to run from that address to
+#     also be linked for loading at that address, simplifying linking.
+# (2) We allow the proper memory map to be delivered to GDB, which will cause
+#     it to use hardware breakpoints at the 0x00200000 mapping (correctly
+#     identifying it as Flash), which it would otherwise not do. Configuring
+#     the Flash via ITCM alias as virtual
+flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+# Use hardware reset.
+#
+# This target is compatible with connect_assert_srst, which may be set in a
+# board file.
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
+
+$_TARGETNAME configure -event reset-init {
+	# If the HSE was previously enabled and the external clock source
+	# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
+	# properly switched back to HSI. This situation persists even over a system
+	# reset, including a pin reset via SRST. However, activating the clock
+	# security system will detect the problem and clear HSERDY to 0, which in
+	# turn allows the PLL to switch back to HSI properly. Since we just came
+	# out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
+	# have happened; in that case, activate the clock security system to clear
+	# HSERDY.
+	if {[mrw 0x40023800] & 0x00020000} {
+		mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
+		sleep 10                    ;# Wait for CSS to fire, if it wants to
+		mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
+		mww 0x4002380C 0x00800000   ;# RCC_CIR = CSSC
+		sleep 1                     ;# Wait for CSSF to clear
+	}
+
+	# If the clock security system fired, it will pend an NMI. A pending NMI
+	# will cause a bad time for any subsequent executing code, such as a
+	# programming algorithm.
+	if {[mrw 0xE000ED04] & 0x80000000} {
+		# ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be
+		# cleared by any normal means (such as ICSR or NVIC). It can only be
+		# cleared by entering the NMI handler or by resetting the processor.
+		echo "[target current]: Clock security system generated NMI. Clearing."
+
+		# Keep the old DEMCR value.
+		set old [mrw 0xE000EDFC]
+
+		# Enable vector catch on reset.
+		mww 0xE000EDFC 0x01000001
+
+		# Issue local reset via AIRCR.
+		mww 0xE000ED0C 0x05FA0001
+
+		# Restore old DEMCR value.
+		mww 0xE000EDFC $old
+	}
+
+	# Configure PLL to boost clock to HSI x 10 (160 MHz)
+	mww 0x40023804 0x08002808   ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
+	mww 0x40023C00 0x00000107   ;# FLASH_ACR = PRFTBE | 7(Latency)
+	mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
+	sleep 10                    ;# Wait for PLL to lock
+	mww 0x40023808 0x00009400   ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
+	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
+
+	# Boost SWD frequency
+	# Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
+	# suffers from DAP WAITs
+	if {[using_jtag]} {
+		[[target current] cget -dap] memaccess 16
+	} {
+		adapter speed 8000
+	}
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reduce speed since CPU speed will slow down to 16MHz with the reset
+	adapter speed 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32g0x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32g0x.cfg
new file mode 100644
index 0000000..b6d9a22
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32g0x.cfg
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32g0x family
+
+#
+# stm32g0 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	# Section 37.5.5 - corresponds to Cortex-M0+
+	set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc stm32g0x_default_reset_start {} {
+	# Reset clock is HSI16 (16 MHz)
+	adapter speed 2000
+}
+
+proc stm32g0x_default_examine_end {} {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
+
+proc stm32g0x_default_reset_init {} {
+	# Increase clock to 64 Mhz
+	mmw 0x40022000 0x00000002 0x00000005	;# FLASH_ACR: Latency = 2
+	mww 0x4002100C 0x30000802				;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
+	mmw 0x40021000 0x01000000 0x00000000	;# RCC_CR |= PLLON
+	mmw 0x40021008 0x00000002 0x00000005	;# RCC_CFGR: SW=PLLRCLK
+
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32g4x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32g4x.cfg
new file mode 100644
index 0000000..39ed1e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32g4x.cfg
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32g4x family
+
+#
+# stm32g4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest current target has 32kB ram, use 16kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		# See STM Document RM0440
+		# Section 46.6.3 - corresponds to Cortex-M4 r0p1
+		set _CPUTAPID 0x4ba00477
+	} {
+		set _CPUTAPID 0x2ba01477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+	set a [llength [flash list]]
+	set _QSPINAME $_CHIPNAME.qspi
+	flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with HSION | HSIRDY.
+	# Use HSI 16 MHz clock, compliant even with VOS == 2.
+	# 1 WS compliant with VOS == 2 and 16 MHz.
+	mmw 0x40022000 0x00000001 0x0000000E	;# FLASH_ACR: Latency = 1
+	mmw 0x40021000 0x00000100 0x00000000	;# RCC_CR |= HSION
+	mmw 0x40021008 0x00000001 0x00000002	;# RCC_CFGR: SW=HSI16
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is HSI (16 MHz)
+	adapter speed 2000
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32h7x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32h7x.cfg
new file mode 100644
index 0000000..5aae938
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32h7x.cfg
@@ -0,0 +1,308 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32h7x family
+
+#
+# stm32h7 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32h7x
+}
+
+if { [info exists DUAL_BANK] } {
+	set $_CHIPNAME.DUAL_BANK $DUAL_BANK
+	unset DUAL_BANK
+} else {
+	set $_CHIPNAME.DUAL_BANK 0
+}
+
+if { [info exists DUAL_CORE] } {
+	set $_CHIPNAME.DUAL_CORE $DUAL_CORE
+	unset DUAL_CORE
+} else {
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
+	echo "Warning : hla does not support multicore debugging"
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+if { [info exists USE_CTI] } {
+	set $_CHIPNAME.USE_CTI $USE_CTI
+	unset USE_CTI
+} else {
+	set $_CHIPNAME.USE_CTI 0
+}
+
+# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
+if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
+	echo "Warning : could not use CTI with a single core device, CTI is disabled"
+	set $_CHIPNAME.USE_CTI 0
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+	  set _CPUTAPID 0x6ba00477
+   } {
+      set _CPUTAPID 0x6ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+if {![using_hla]} {
+	# STM32H7 provides an APB-AP at access port 2, which allows the access to
+	# the debug and trace features on the system APB System Debug Bus (APB-D).
+	target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+	swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
+	tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
+}
+
+target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
+
+$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+
+if {[set $_CHIPNAME.DUAL_BANK]} {
+	flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
+
+	$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+	flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+
+	if {[set $_CHIPNAME.DUAL_BANK]} {
+		flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
+	}
+}
+
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+} else {
+   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+      set a [llength [flash list]]
+      set _OCTOSPINAME1 $_CHIPNAME.octospi1
+      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+   }
+   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+      set b [llength [flash list]]
+      set _OCTOSPINAME2 $_CHIPNAME.octospi2
+      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
+   }
+}
+
+# Clock after reset is HSI at 64 MHz, no need of PLL
+adapter speed 1800
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+# use hardware reset
+#
+# The STM32H7 does not support connect_assert_srst mode because the AXI is
+# unavailable while SRST is asserted, and that is used to access the DBGMCU
+# component at 0x5C001000 in the examine-end event handler.
+#
+# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
+# of the default AP0, and that works with SRST asserted; however, nonzero AP
+# usage does not work with HLA, so is not done by default. That change could be
+# made in a local configuration file if connect_assert_srst mode is needed for
+# a specific application and a non-HLA adapter is in use.
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+	$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
+
+	if {[set $_CHIPNAME.DUAL_CORE]} {
+		$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+	}
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
+}
+
+$_CHIPNAME.cpu0 configure -event examine-end {
+	# Enable D3 and D1 DBG clocks
+	# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
+	stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
+
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
+	stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
+	stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB3FZ1 |= WWDG1
+	stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
+	# DBGMCU_APB1LFZ1 |= WWDG2
+	stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
+	# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
+	stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
+
+	# Enable clock for tracing
+	# DBGMCU_CR |= TRACECLKEN
+	stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
+
+	# RM0399 (id 0x450) M7+M4 with SWO Funnel
+	# RM0433 (id 0x450) M7 with SWO Funnel
+	# RM0455 (id 0x480) M7 without SWO Funnel
+	# RM0468 (id 0x483) M7 without SWO Funnel
+	# Enable CM7 and CM4 slave ports in SWO trace Funnel
+	# Works ok also on devices single core and without SWO funnel
+	# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
+	# SWTF_CTRL |= ENS0 | ENS1
+	stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	# Clock after reset is HSI at 64 MHz, no need of PLL
+	adapter speed 4000
+}
+
+# get _CHIPNAME from current target
+proc stm32h7x_get_chipname {} {
+	set t [target current]
+	set sep [string last "." $t]
+	if {$sep == -1} {
+		return $t
+	}
+	return [string range $t 0 [expr {$sep - 1}]]
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	$_CHIPNAME.cpu1 configure -event examine-end {
+		set _CHIPNAME [stm32h7x_get_chipname]
+		global $_CHIPNAME.USE_CTI
+
+		# Stop watchdog counters during halt
+		# DBGMCU_APB3FZ2 |= WWDG1
+		stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
+		# DBGMCU_APB1LFZ2 |= WWDG2
+		stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
+		# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
+		stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
+
+		if {[set $_CHIPNAME.USE_CTI]} {
+			stm32h7x_cti_start
+		}
+	}
+}
+
+# like mrw, but with target selection
+proc stm32h7x_mrw {used_target reg} {
+	return [$used_target read_memory $reg 32 1]
+}
+
+# like mmw, but with target selection
+proc stm32h7x_mmw {used_target reg setbits clearbits} {
+	set old [stm32h7x_mrw $used_target $reg]
+	set new [expr {($old & ~$clearbits) | $setbits}]
+	$used_target mww $reg $new
+}
+
+# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
+# this procedure will use the mem_ap on AP2 whenever possible
+proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
+	# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
+	if {![using_hla]} {
+		set _CHIPNAME [stm32h7x_get_chipname]
+		set used_target $_CHIPNAME.ap2
+		set reg_addr [expr {0xE00E1000 + $reg_offset}]
+	} {
+		set used_target [target current]
+		set reg_addr [expr {0x5C001000 + $reg_offset}]
+	}
+
+	stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
+}
+
+if {[set $_CHIPNAME.USE_CTI]} {
+	# create CTI instances for both cores
+	cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
+	cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
+
+	$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
+
+	$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+
+	proc stm32h7x_cti_start {} {
+		set _CHIPNAME [stm32h7x_get_chipname]
+
+		# Configure Cores' CTIs to halt each other
+		# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
+		$_CHIPNAME.cti0 write INEN0 0x1
+		$_CHIPNAME.cti0 write OUTEN0 0x1
+		$_CHIPNAME.cti1 write INEN0 0x1
+		$_CHIPNAME.cti1 write OUTEN0 0x1
+
+		# enable CTIs
+		$_CHIPNAME.cti0 enable on
+		$_CHIPNAME.cti1 enable on
+	}
+
+	proc stm32h7x_cti_stop {} {
+		set _CHIPNAME [stm32h7x_get_chipname]
+
+		$_CHIPNAME.cti0 enable off
+		$_CHIPNAME.cti1 enable off
+	}
+
+	proc stm32h7x_cti_prepare_restart_all {} {
+		stm32h7x_cti_prepare_restart cti0
+		stm32h7x_cti_prepare_restart cti1
+	}
+
+	proc stm32h7x_cti_prepare_restart {cti} {
+		set _CHIPNAME [stm32h7x_get_chipname]
+
+		# Acknowlodge EDBGRQ at TRIGOUT0
+		$_CHIPNAME.$cti write INACK 0x01
+		$_CHIPNAME.$cti write INACK 0x00
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32h7x_dual_bank.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32h7x_dual_bank.cfg
new file mode 100644
index 0000000..41a4773
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32h7x_dual_bank.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32h7x family (dual flash bank)
+
+# STM32H7xxxI 2Mo have a dual bank flash.
+set DUAL_BANK 1
+
+source [find target/stm32h7x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l0.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l0.cfg
new file mode 100644
index 0000000..b4bdb18
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l0.cfg
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# M0+ devices only have SW-DP, but swj-dp code works, just don't
+# set any jtag related features
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l0
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB (max ram on smallest part)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+# JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
+adapter speed 300
+
+adapter srst delay 100
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    # Arm, m0+, non-multidrop.
+    # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
+    set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32l0_enable_HSI16 {} {
+	# Enable HSI16 as clock source
+	echo "STM32L0: Enabling HSI16"
+
+	# Set HSI16ON in RCC_CR (leave MSI enabled)
+    mmw 0x40021000 0x00000101 0
+
+	# Set HSI16 as SYSCLK (RCC_CFGR)
+	mmw 0x4002100c 0x00000001 0
+
+	# Wait until System clock switches to HSI16
+	while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
+
+	# Increase speed
+	adapter speed 2500
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32l0_enable_HSI16
+}
+
+$_TARGETNAME configure -event reset-start {
+	adapter speed 300
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0x40015804 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l0_dual_bank.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l0_dual_bank.cfg
new file mode 100644
index 0000000..ff3cb90
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l0_dual_bank.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/stm32l0.cfg]
+
+# Add the second flash bank.
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l1.cfg
new file mode 100644
index 0000000..53d9076
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l1.cfg
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# stm32l1 devices support both JTAG and SWD transports.
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l1
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 10kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x2800
+}
+
+# JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
+adapter speed 300
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0038
+      # Section 30.6.3 - corresponds to Cortex-M3 r2p0
+      set _CPUTAPID 0x4ba00477
+   } else {
+      # SWD IDCODE (single drop, arm)
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32l_enable_HSI {} {
+	# Enable HSI as clock source
+	echo "STM32L: Enabling HSI"
+
+	# Set HSION in RCC_CR
+	mmw 0x40023800 0x00000101 0
+
+	# Set HSI as SYSCLK
+	mmw 0x40023808 0x00000001 0
+
+	# Increase JTAG speed
+	adapter speed 2000
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32l_enable_HSI
+}
+
+$_TARGETNAME configure -event reset-start {
+	adapter speed 300
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l1x_dual_bank.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l1x_dual_bank.cfg
new file mode 100644
index 0000000..deefdb4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l1x_dual_bank.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/stm32l1.cfg]
+
+# The stm32l1x 384kb have a dual bank flash.
+# Let's add a definition for the second bank here.
+
+# Add the second flash bank.
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l4x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l4x.cfg
new file mode 100644
index 0000000..9a69673
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l4x.cfg
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32l4x family
+
+#
+# stm32l4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 40kB (Available RAM in smallest device STM32L412)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0xa000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0351
+      # Section 44.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+} else {
+   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+      set a [llength [flash list]]
+      set _OCTOSPINAME1 $_CHIPNAME.octospi1
+      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+   }
+   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+      set b [llength [flash list]]
+      set _OCTOSPINAME2 $_CHIPNAME.octospi2
+      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400
+   }
+}
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
+	targets $_chipname.cpu
+
+	if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+		switch [$_chipname.tpiu cget -port-width] {
+			1 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
+				mmw 0xE0042004 0x00000060 0x000000c0
+				mmw 0x48001020 0x00000000 0x0000ff00
+				mmw 0x48001000 0x000000a0 0x000000f0
+				mmw 0x48001008 0x000000f0 0x00000000
+			  }
+			2 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
+				mmw 0xE0042004 0x000000a0 0x000000c0
+				mmw 0x48001020 0x00000000 0x000fff00
+				mmw 0x48001000 0x000002a0 0x000003f0
+				mmw 0x48001008 0x000003f0 0x00000000
+			  }
+			4 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
+				mmw 0xE0042004 0x000000e0 0x000000c0
+				mmw 0x48001020 0x00000000 0x0fffff00
+				mmw 0x48001000 0x00002aa0 0x00003ff0
+				mmw 0x48001008 0x00003ff0 0x00000000
+			  }
+		}
+	} else {
+		# Set TRACE_IOEN; TRACE_MODE to async
+		mmw 0xE0042004 0x00000020 0x000000c0
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
+	# Use MSI 24 MHz clock, compliant even with VOS == 2.
+	# 3 WS compliant with VOS == 2 and 24 MHz.
+	mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
+	mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
+
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 500
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l5x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l5x.cfg
new file mode 100644
index 0000000..c43b699
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32l5x.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32l5x family
+# stm32l5x devices support both JTAG and SWD transports.
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32l5x
+}
+
+source [find target/stm32x5x_common.cfg]
+
+proc stm32l5x_clock_config {} {
+	set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
+	# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
+	# RCC_APB1ENR1 = PWREN
+	mww [expr {0x40021058 + $offset}] 0x10000000
+	# delay for register clock enable (read back reg)
+	mrw [expr {0x40021058 + $offset}]
+	# PWR_CR1 : VOS Range 0
+	mww [expr {0x40007000 + $offset}] 0
+	# while (PWR_SR2 & VOSF)
+	while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}
+	# FLASH_ACR : 5 WS for 110 MHz HCLK
+	mww 0x40022000 0x00000005
+	# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
+	# fVCO = 4 x 55 /1 = 220
+	# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
+	mww [expr {0x4002100C + $offset}] 0x01003711
+	# RCC_CR |= PLLON
+	mmw [expr {0x40021000 + $offset}] 0x01000000 0
+	# while !(RCC_CR & PLLRDY)
+	while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}
+	# RCC_CFGR |= SW_PLL
+	mmw [expr {0x40021008 + $offset}] 0x00000003 0
+	# while ((RCC_CFGR & SWS) != PLL)
+	while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32l5x_clock_config
+	# Boost JTAG frequency
+	adapter speed 4000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32mp13x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32mp13x.cfg
new file mode 100644
index 0000000..bcf25c9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32mp13x.cfg
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP13x (Single Cortex-A7)
+# http://www.st.com/stm32mp1
+
+# HLA does not support custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp13x_dk.cfg\"."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp13x
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x06501041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# NOTE: keep ap-num and dbgbase to speed-up examine after reset
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+
+$_CHIPNAME.cpu cortex_a maskisr on
+$_CHIPNAME.cpu cortex_a dacrfixup on
+
+# interface does not work while srst is asserted
+# this is target specific, valid for every board
+# srst resets the debug unit, behavior equivalent to "srst_pulls_trst"
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# bootrom has an internal timeout of 1 second for detecting the boot flash.
+# wait at least 1 second to guarantee we are out of bootrom
+adapter srst delay 1100
+
+add_help_text axi_secure "Set secure mode for following AXI accesses"
+proc axi_secure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x10006000
+}
+
+add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
+proc axi_nsecure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x30006000
+}
+
+axi_secure
+
+proc dbgmcu_enable_debug {} {
+	# keep clock enabled in low-power
+	## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
+	# freeze watchdog 1 and 2 on core halted
+	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
+}
+
+proc toggle_cpu_dbg_claim0 {} {
+	# toggle CPU0 DBG_CLAIM[0]
+	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
+	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+}
+
+# FIXME: most of handlers below will be removed once reset framework get merged
+$_CHIPNAME.ap1 configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+	catch {dap init}
+	catch {$::_CHIPNAME.dap apid 1}
+}
+$_CHIPNAME.cpu configure -event reset-deassert-pre  {$::_CHIPNAME.cpu arp_examine}
+$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
+$_CHIPNAME.ap1 configure -event examine-start       {dap init}
+$_CHIPNAME.ap1 configure -event examine-end         {dbgmcu_enable_debug}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32mp15x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32mp15x.cfg
new file mode 100644
index 0000000..bcdda73
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32mp15x.cfg
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
+# http://www.st.com/stm32mp1
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp15x
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x06500041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
+# so defer-examine it until the reset framework get merged
+# NOTE: keep ap-num and dbgbase to speed-up examine after reset
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+
+targets $_CHIPNAME.cpu0
+
+target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
+$_CHIPNAME.cpu0 cortex_a maskisr on
+$_CHIPNAME.cpu1 cortex_a maskisr on
+$_CHIPNAME.cpu0 cortex_a dacrfixup on
+$_CHIPNAME.cpu1 cortex_a dacrfixup on
+
+cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000
+cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000
+cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
+cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
+
+# interface does not work while srst is asserted
+# this is target specific, valid for every board
+# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
+# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
+# debug unit, behavior equivalent to "srst_pulls_trst"
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# bootrom has an internal timeout of 1 second for detecting the boot flash.
+# wait at least 1 second to guarantee we are out of bootrom
+adapter srst delay 1100
+
+add_help_text axi_secure "Set secure mode for following AXI accesses"
+proc axi_secure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x10006000
+}
+
+add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
+proc axi_nsecure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x30006000
+}
+
+axi_secure
+
+proc dbgmcu_enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
+	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+	# freeze watchdog 1 and 2 on cores halted
+	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
+}
+
+proc toggle_cpu0_dbg_claim0 {} {
+	# toggle CPU0 DBG_CLAIM[0]
+	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
+	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+}
+
+proc detect_cpu1 {} {
+	set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
+	set dual_core [expr {$cpu1_prsr & 1}]
+	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
+}
+
+proc rcc_enable_traceclk {} {
+	$::_CHIPNAME.ap2 mww 0x5000080c 0x301
+}
+
+# FIXME: most of handler below will be removed once reset framework get merged
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
+$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
+$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
+$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
+$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
+$_CHIPNAME.ap1  configure -event examine-start       {dap init}
+$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
+$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
+$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32u5x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32u5x.cfg
new file mode 100644
index 0000000..44b51e2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32u5x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32u5x family
+# stm32u5x devices support both JTAG and SWD transports.
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32u5x
+}
+
+source [find target/stm32x5x_common.cfg]
+
+proc stm32u5x_clock_config {} {
+	set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
+	# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
+
+	# Enable voltage range 1 for frequency above 100 Mhz
+	# RCC_AHB3ENR = PWREN
+	mww [expr {0x46020C94 + $offset}] 0x00000004
+	# delay for register clock enable (read back reg)
+	mrw [expr {0x46020C94 + $offset}]
+	# PWR_VOSR : VOS Range 1
+	mmw [expr {0x4602080C + $offset}] 0x00030000 0
+	# while !(PWR_VOSR & VOSRDY)
+	while {!([mrw [expr {0x4602080C + $offset}]] & 0x00008000)} {}
+	# FLASH_ACR : 4 WS for 160 MHz HCLK
+	mww [expr {0x40022000 + $offset}] 0x00000004
+	# RCC_PLL1CFGR => PLL1MBOOST=0, PLL1M=0=/1, PLL1FRACEN=0, PLL1SRC=MSI 4MHz
+	#                 PLL1REN=1, PLL1RGE => VCOInputRange=PLLInputRange_4_8
+	mww [expr {0x46020C28 + $offset}] 0x00040009
+	# Enable EPOD Booster
+	mmw [expr {0x4602080C + $offset}] 0x00040000 0
+	# while !(PWR_VOSR & BOOSTRDY)
+	while {!([mrw [expr {0x4602080C + $offset}]] & 0x00004000)} {}
+	# RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80
+	# fVCO = 4 x 80 /1 = 320
+	# SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz
+	mww [expr {0x46020C34 + $offset}] 0x0101024F
+	# RCC_CR |= PLL1ON
+	mmw [expr {0x46020C00 + $offset}] 0x01000000 0
+	# while !(RCC_CR & PLL1RDY)
+	while {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {}
+	# RCC_CFGR1 |= SW_PLL
+	mmw [expr {0x46020C1C + $offset}] 0x00000003 0
+	# while ((RCC_CFGR1 & SWS) != PLL)
+	while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32u5x_clock_config
+	# Boost JTAG frequency
+	adapter speed 4000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32w108xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32w108xx.cfg
new file mode 100644
index 0000000..e6a62e8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32w108xx.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Target configuration for the ST STM32W108xx chips
+#
+# Processor: ARM Cortex-M3
+# Date:      2013-06-09
+# Author:    Giuseppe Barba 
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] == 0 } {
+   set _CHIPNAME stm32w108
+} else {
+   set _CHIPNAME $CHIPNAME
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 8kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x2000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x3ba00477
+   } {
+      set _CPUTAPID 0x1ba01477
+   }
+}
+
+set _ENDIAN little
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+ if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID
+ } else {
+   set _BSTAPID_1 0x169a862b
+   set _BSTAPID_2 0x269a862b
+   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
+		-expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2
+ }
+}
+#
+# Set Target
+#
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+
+# Use the flash driver from the EM357
+set _FLASHNAME $_CHIPNAME.flash
+
+# 64k (0x10000) of flash
+flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32wbax.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32wbax.cfg
new file mode 100644
index 0000000..1299407
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32wbax.cfg
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32wbax family
+
+#
+# stm32wba devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME stm32wbax
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+    set _WORKAREASIZE $WORKAREASIZE
+} else {
+    set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    if { [using_jtag] } {
+        set _CPUTAPID 0x6ba00477
+    } else {
+        # SWD IDCODE (single drop, arm)
+        set _CPUTAPID 0x6ba02477
+    }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+    jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+    jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+    # CPU comes out of reset with HSION | HSIRDY.
+    # Use HSI 16 MHz clock, compliant even with VOS == 2.
+    # 1 WS compliant with VOS == 2 and 16 MHz.
+    mmw 0x40022000 0x00000001 0x0000000E	;# FLASH_ACR: Latency = 1
+    mmw 0x56020C00 0x00000100 0x00000000	;# RCC_CR |= HSION
+    mmw 0x56020C1C 0x00000000 0x00000002	;# RCC_CFGR1: SW=HSI16
+    # Boost JTAG frequency
+    adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+    # Reset clock is HSI (16 MHz)
+    adapter speed 2000
+}
+
+$_TARGETNAME configure -event examine-end {
+    # Enable debug during low power modes (uses more power)
+    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+    mmw 0xE0042004 0x00000006 0
+
+    # Stop watchdog counters during halt
+    # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
+    mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+    targets $_targetname
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32wbx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32wbx.cfg
new file mode 100644
index 0000000..737b144
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32wbx.cfg
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32wbx family
+
+#
+# stm32wb devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32wbx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x6ba00477
+   } else {
+      # SWD IDCODE (single drop, arm)
+      set _CPUTAPID 0x6ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+    # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+    # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+    # 2 WS compliant with VOS=Range1 and 24 MHz.
+    mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTBE | 2(Latency)
+    mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+    # Boost JTAG frequency
+    adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+    # Reset clock is MSI (4 MHz)
+    adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+    # Enable debug during low power modes (uses more power)
+    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+    mmw 0xE0042004 0x00000007 0
+
+    # Stop watchdog counters during halt
+    # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+    mmw 0xE004203C 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+    targets $_targetname
+
+    # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+    # change this value accordingly to configure trace pins
+    # assignment
+    mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32wlx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32wlx.cfg
new file mode 100644
index 0000000..39c897f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32wlx.cfg
@@ -0,0 +1,185 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32wlx family
+
+#
+# stm32wl devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32wlx
+}
+
+if { [info exists DUAL_CORE] } {
+	set $_CHIPNAME.DUAL_CORE $DUAL_CORE
+	unset DUAL_CORE
+} else {
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+if { [info exists WKUP_CM0P] } {
+	set $_CHIPNAME.WKUP_CM0P $WKUP_CM0P
+	unset WKUP_CM0P
+} else {
+	set $_CHIPNAME.WKUP_CM0P 0
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
+	echo "Warning : hla does not support multicore debugging"
+	set $_CHIPNAME.DUAL_CORE 0
+	set $_CHIPNAME.WKUP_CM0P 0
+}
+
+# setup the Work-area start address and size
+# Work-area is a space in RAM used for flash programming
+
+# Memory map for known devices:
+# STM32WL   x5JC   x5JB   x5J8
+#   FLASH   256    128    64
+#   SRAM1   32     16     0
+#   SRAM2   32     32     20
+
+# By default use 8kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x2000
+}
+
+# Use SRAM2 as work area (some devices do not have SRAM1):
+set WORKAREASTART_CM4   0x20008000
+set WORKAREASTART_CM0P  [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}]
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+target create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+flash bank $_CHIPNAME.otp.cpu0   stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+	# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+	# 2 WS compliant with VOS=Range1 and 24 MHz.
+	mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTEN | 2(Latency)
+	mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+$_CHIPNAME.cpu0 configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 500
+}
+
+$_CHIPNAME.cpu0 configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE004203C 0x00001800 0
+
+	set _CHIPNAME [stm32wlx_get_chipname]
+	global $_CHIPNAME.WKUP_CM0P
+
+	if {[set $_CHIPNAME.WKUP_CM0P]} {
+		stm32wlx_wkup_cm0p
+	}
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+
+	$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+	flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+	flash bank $_CHIPNAME.otp.cpu1   stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1
+
+	if {![using_hla]} {
+		# if srst is not fitted use SYSRESETREQ to
+		# perform a soft reset
+		$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+	}
+
+	proc stm32wlx_wkup_cm0p {} {
+		set _CHIPNAME [stm32wlx_get_chipname]
+
+		# enable CPU2 boot after reset and after wakeup from Stop or Standby mode
+		# PWR_CR4 |= C2BOOT
+		stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0
+	}
+}
+
+# get _CHIPNAME from current target
+proc stm32wlx_get_chipname {} {
+	set t [target current]
+	set sep [string last "." $t]
+	if {$sep == -1} {
+		return $t
+	}
+	return [string range $t 0 [expr {$sep - 1}]]
+}
+
+# like mrw, but with target selection
+proc stm32wlx_mrw {used_target reg} {
+	return [$used_target read_memory $reg 32 1]
+}
+
+# like mmw, but with target selection
+proc stm32wlx_mmw {used_target reg setbits clearbits} {
+	set old [stm32wlx_mrw $used_target $reg]
+	set new [expr {($old & ~$clearbits) | $setbits}]
+	$used_target mww $reg $new
+}
+
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32x5x_common.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32x5x_common.cfg
new file mode 100644
index 0000000..fb3aeb1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32x5x_common.cfg
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common script for stm32l5x and stm32u5x families
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		# STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
+		# STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
+		# Corresponds to Cortex®-M33 JTAG debug port ID code
+		set _CPUTAPID 0x0ba04477
+	} {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x0be12477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+# use non-secure RAM by default
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# create sec/ns flash and otp memories (sizes will be probed)
+flash bank $_CHIPNAME.flash_ns      stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp           stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
+
+# Common knowledge tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://review.openocd.org/3366
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {[using_hla]} {
+	echo "Warn : The selected adapter does not support debugging this device in secure mode"
+} else {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc stm32x5x_is_secure {} {
+	# read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16)
+	set DSCSR [mrw 0xE000EE08]
+	return [expr {($DSCSR & (1 << 16)) != 0}]
+}
+
+proc stm32x5x_ahb_ap_non_secure_access {} {
+	# in HLA mode, non-secure debugging is possible without changing the AP CSW
+	if {![using_hla]} {
+		# SPROT=1=Non Secure access, Priv=1
+		[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
+	}
+}
+
+proc stm32x5x_ahb_ap_secure_access {} {
+	if {![using_hla]} {
+		# SPROT=0=Secure access, Priv=1
+		[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
+	}
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 480
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0xE0044004 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0044008 0x00001800 0
+}
+
+$_TARGETNAME configure -event halted {
+	set secure [stm32x5x_is_secure]
+
+	if {$secure} {
+		set secure_str "Secure"
+		stm32x5x_ahb_ap_secure_access
+	} else {
+		set secure_str "Non-Secure"
+		stm32x5x_ahb_ap_non_secure_access
+	}
+
+	# print the secure state only when it changes
+	set _TARGETNAME [target current]
+	global $_TARGETNAME.secure
+
+	if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
+		echo "CPU in $secure_str state"
+		# update saved security state
+		set $_TARGETNAME.secure $secure
+	}
+}
+
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	set use_secure_workarea 0
+	# check if FLASH_OPTR.TZEN is enabled
+	set FLASH_OPTR [mrw 0x40022040]
+	if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
+		echo "TZEN option bit disabled"
+		stm32x5x_ahb_ap_non_secure_access
+	} else {
+		stm32x5x_ahb_ap_secure_access
+		echo "TZEN option bit enabled"
+
+		# check if FLASH_OPTR.RDP is not Level 0.5
+		if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
+			set use_secure_workarea 1
+		}
+	}
+
+	set _TARGETNAME [target current]
+	set workarea_addr [$_TARGETNAME cget -work-area-phys]
+	echo "workarea_addr $workarea_addr"
+
+	if {$use_secure_workarea} {
+		set workarea_addr [expr {$workarea_addr | 0x10000000}]
+	} else {
+		set workarea_addr [expr {$workarea_addr & ~0x10000000}]
+	}
+
+	$_TARGETNAME configure -work-area-phys $workarea_addr
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_EN and TRACE_IOEN in DBGMCU_CR
+	# Leave TRACE_MODE untouched (defaults to async).
+	# When using sync change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0044004 0x00000030 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32xl.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32xl.cfg
new file mode 100644
index 0000000..ad68f3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm32xl.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32xl family (dual flash bank)
+source [find target/stm32f1x.cfg]
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l.cfg
new file mode 100644
index 0000000..583a2a4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l.cfg
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm8l family
+
+#
+# stm8 devices support SWIM transports only.
+#
+
+transport select swim
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm8l
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists FLASHSTART] } {
+   set _FLASHSTART $FLASHSTART
+} else {
+   set _FLASHSTART 0x8000
+}
+
+if { [info exists FLASHEND] } {
+   set _FLASHEND $FLASHEND
+} else {
+   set _FLASHEND 0xffff
+}
+
+if { [info exists EEPROMSTART] } {
+   set _EEPROMSTART $EEPROMSTART
+} else {
+   set _EEPROMSTART 0x4000
+}
+
+if { [info exists EEPROMEND] } {
+   set _EEPROMEND $EEPROMEND
+} else {
+   set _EEPROMEND 0x43ff
+}
+
+if { [info exists OPTIONSTART] } {
+   set _OPTIONSTART $OPTIONSTART
+} else {
+   set _OPTIONSTART 0x4800
+}
+
+if { [info exists OPTIONEND] } {
+   set _OPTIONEND $OPTIONEND
+} else {
+   set _OPTIONEND 0x487f
+}
+
+if { [info exists BLOCKSIZE] } {
+   set _BLOCKSIZE $BLOCKSIZE
+} else {
+   set _BLOCKSIZE 0x80
+}
+
+swim newtap $_CHIPNAME cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu
+
+$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
+$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND
+$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE
+
+# Uncomment this line to enable interrupts while instruction step
+#$_TARGETNAME configure -enable_step_irq
+
+# Set stm8l type
+$_TARGETNAME configure -enable_stm8l
+
+# Set high speed
+adapter speed 800
+# Set low speed
+#adapter speed 363
+
+reset_config srst_only
+
+#uncomment this line to connect under reset
+#reset_config srst_nogate connect_assert_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l151x2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l151x2.cfg
new file mode 100644
index 0000000..db88c71
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l151x2.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x2
+# Supported Devices:
+# STM8L151C2
+# STM8L151F2
+# STM8L151G2
+# STM8L151K2
+
+# 1kB RAM
+# Start 0x0000
+# End   0x03ff
+set WORKAREASIZE 1024
+
+# 4kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0x8fff
+
+# 256B EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x10ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x487f
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l151x3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l151x3.cfg
new file mode 100644
index 0000000..fe904b4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l151x3.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x3
+# Supported Devices:
+# STM8L151C3
+# STM8L151F3
+# STM8L151G3
+# STM8L151K3
+
+# 1kB RAM
+# Start 0x0000
+# End   0x03ff
+set WORKAREASIZE 1024
+
+# 8kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0x9fff
+
+# 256B EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x10ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x487f
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l152.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l152.cfg
new file mode 100644
index 0000000..033b826
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l152.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo 'DEPRECATED: choose between stm8l15xx4.cfg, stm8l15xx6.cfg and stm8l15xx8.cfg instead of stm8l152.cfg'
+echo '            using stm8l152.cfg for backwards compatability'
+
+set EEPROMSTART 0x1000
+set EEPROMEND 0x13ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l15xx4.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l15xx4.cfg
new file mode 100644
index 0000000..4438193
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l15xx4.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x4/STM8L152x4
+# Supported Devices:
+# STM8L151C4
+# STM8L151G4
+# STM8L151K4
+# STM8L152C4
+# STM8L152K4
+
+# 2kB RAM
+# Start 0x0000
+# End   0x07ff
+set WORKAREASIZE 2048
+
+# 16kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0xbfff
+
+# 1kB EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x13ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x48ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l15xx6.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l15xx6.cfg
new file mode 100644
index 0000000..5243295
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l15xx6.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x6/STM8L152x6
+# Supported Devices:
+# STM8L151C6
+# STM8L151G6
+# STM8L151K6
+# STM8L151R6
+# STM8L152C6
+# STM8L152K6
+# STM8L152R6
+
+# 2kB RAM
+# Start 0x0000
+# End   0x07ff
+set WORKAREASIZE 2048
+
+# 32kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0xffff
+
+# 1kB EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x13ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x48ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l15xx8.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l15xx8.cfg
new file mode 100644
index 0000000..e354827
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8l15xx8.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x8/STM8L152x8
+# Supported Devices:
+# STM8L151C8
+# STM8L151M8
+# STM8L151R8
+# STM8L152C8
+# STM8L152K8
+# STM8L152M8
+# STM8L152R8
+
+# 4kB RAM
+# Start 0x0000
+# End   0x0fff
+set WORKAREASIZE 4096
+
+# 64kB Flash
+set FLASHSTART  0x08000
+set FLASHEND    0x17fff
+
+# 2kB EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x17ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x48ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s.cfg
new file mode 100644
index 0000000..01e50d0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s.cfg
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm8s family
+
+#
+# stm8 devices support SWIM transports only.
+#
+
+transport select swim
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm8s
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists FLASHSTART] } {
+   set _FLASHSTART $FLASHSTART
+} else {
+   set _FLASHSTART 0x8000
+}
+
+if { [info exists FLASHEND] } {
+   set _FLASHEND $FLASHEND
+} else {
+   set _FLASHEND 0xffff
+}
+
+if { [info exists EEPROMSTART] } {
+   set _EEPROMSTART $EEPROMSTART
+} else {
+   set _EEPROMSTART 0x4000
+}
+
+if { [info exists EEPROMEND] } {
+   set _EEPROMEND $EEPROMEND
+} else {
+   set _EEPROMEND 0x43ff
+}
+
+if { [info exists OPTIONSTART] } {
+   set _OPTIONSTART $OPTIONSTART
+} else {
+   set _OPTIONSTART 0x4800
+}
+
+if { [info exists OPTIONEND] } {
+   set _OPTIONEND $OPTIONEND
+} else {
+   set _OPTIONEND 0x487f
+}
+
+if { [info exists BLOCKSIZE] } {
+   set _BLOCKSIZE $BLOCKSIZE
+} else {
+   set _BLOCKSIZE 0x80
+}
+
+swim newtap $_CHIPNAME cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu
+
+$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
+$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND
+$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE
+
+# Uncomment this line to enable interrupts while instruction step
+#$_TARGETNAME configure -enable_step_irq
+
+# Set high speed
+adapter speed 800
+# Set low speed
+#adapter speed 363
+
+reset_config srst_only
+
+# uncomment this line to connect under reset
+#reset_config srst_nogate connect_assert_srst
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s003.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s003.cfg
new file mode 100644
index 0000000..60f5c3c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s003.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#config script for STM8S003
+
+set FLASHEND 0x9FFF
+set BLOCKSIZE 0x40
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0x00
+   reset halt
+}
+
+source [find target/stm8s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s103.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s103.cfg
new file mode 100644
index 0000000..41350cb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s103.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#config script for STM8S103
+
+set FLASHEND 0x9FFF
+set EEPROMEND 0x427F
+set OPTIONEND 0x480A
+set BLOCKSIZE 0x40
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0x00
+   reset halt
+}
+
+source [find target/stm8s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s105.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s105.cfg
new file mode 100644
index 0000000..6af491e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/stm8s105.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#config script for STM8S105
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0x00
+   reset halt
+}
+
+source [find target/stm8s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str710.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str710.cfg
new file mode 100644
index 0000000..ff89717
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str710.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#start slow, speed up after reset
+adapter speed 10
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME str710
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
+$_TARGETNAME configure -event reset-init {
+	adapter speed 6000
+
+# Because the hardware cannot be interrogated for the protection state
+# of sectors, initialize all the sectors to be unprotected. The initial
+# state is reflected by the driver, too.
+	flash protect 0 0 last off
+	flash protect 1 0 last off
+}
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	flash protect 0 0 7 off
+	flash protect 1 0 1 off
+}
+
+$_TARGETNAME configure -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank str7x   0 0  
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 $_TARGETNAME STR71x
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str730.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str730.cfg
new file mode 100644
index 0000000..57681f9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str730.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#STR730 CPU
+
+adapter speed 3000
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME str730
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+#jtag nTRST and nSRST delay
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
+
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
+$_TARGETNAME configure -event reset-init {
+	adapter speed 3000
+
+# Because the hardware cannot be interrogated for the protection state
+# of sectors, initialize all the sectors to be unprotected. The initial
+# state is reflected by the driver, too.
+	flash protect 0 0 last off
+}
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR73x
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str750.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str750.cfg
new file mode 100644
index 0000000..5af7b74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str750.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#STR750 CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME str750
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4f1f0041
+}
+
+# jtag speed
+adapter speed 10
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+#jtag nTRST and nSRST delay
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
+
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
+$_TARGETNAME configure -event reset-init {
+	adapter speed 3000
+
+	init_smi
+# Because the hardware cannot be interrogated for the protection state
+# of sectors, initialize all the sectors to be unprotected. The initial
+# state is reflected by the driver, too.
+	flash protect 0 0 last off
+	flash protect 1 0 last off
+}
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	flash protect 0 0 7 off
+	flash protect 1 0 1 off
+}
+
+$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank     
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x
+
+# Serial NOR on SMI CS0.
+set _FLASHNAME $_CHIPNAME.snor
+flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME
+
+source [find mem_helper.tcl]
+
+proc init_smi {} {
+	mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs
+	mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit
+	mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str912.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str912.cfg
new file mode 100644
index 0000000..3167b40
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/str912.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for str9
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+adapter speed 16
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+if { [info exists FLASHTAPID] } {
+   set _FLASHTAPID $FLASHTAPID
+} else {
+   set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+   # possible values: 0x1457f041, 0x2457f041
+   # we ignore version in check below
+   set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID -ignore-version
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
+
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	#adapter speed 3000
+
+	# -- Enable 96K RAM
+	# PFQBC enabled / DTCM & AHB wait-states disabled
+	mww 0x5C002034 0x0191
+
+	str9x flash_config 0 4 2 0 0x80000
+	flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+
+#flash bank str9x   0 0  
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/swj-dp.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/swj-dp.tcl
new file mode 100644
index 0000000..f2b233f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/swj-dp.tcl
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ARM Debug Interface V5 (ADI_V5) utility
+# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
+# SW-DP and JTAG-DP targets don't need to switch based
+# on which transport is active.
+#
+# declare a JTAG or SWD Debug Access Point (DAP)
+# based on the transport in use with this session.
+# You can't access JTAG ops when SWD is active, etc.
+
+# params are currently what "jtag newtap" uses
+# because OpenOCD internals are still strongly biased
+# to JTAG ....  but for SWD, "irlen" etc are ignored,
+# and the internals work differently
+
+# for now, ignore non-JTAG and non-SWD transports
+# (e.g. initial flash programming via SPI or UART)
+
+# split out "chip" and "tag" so we can someday handle
+# them more uniformly irlen too...)
+
+if [catch {transport select}] {
+  echo "Error: unable to select a session transport. Can't continue."
+  shutdown
+}
+
+proc swj_newdap {chip tag args} {
+ if [using_jtag] {
+     eval jtag newtap $chip $tag $args
+ } elseif [using_swd] {
+     eval swd newdap $chip $tag $args
+ } else {
+     echo "Error: transport '[ transport select ]' not supported by swj_newdap"
+     shutdown
+ }
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/swm050.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/swm050.cfg
new file mode 100644
index 0000000..6cc5f6d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/swm050.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Synwit SWM050
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME swm050
+}
+set _CHIPSERIES swm050
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+$_TARGETNAME configure -event reset-init {
+	# Stop the watchdog, just to be safe
+	mww 0x40019000 0x00
+	# Set clock divider value to 1
+	mww 0x400F0000 0x01
+	# Set system clock to 18Mhz
+	mww 0x400F0008 0x00
+}
+
+# SWM050 (Cortex-M0 core) supports SYSRESETREQ
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/test_reset_syntax_error.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/test_reset_syntax_error.cfg
new file mode 100644
index 0000000..7ef5914
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/test_reset_syntax_error.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Test script to check that syntax error in reset
+# script is reported properly.
+
+# at91eb40a target
+
+#jtag scan chain
+set _CHIPNAME syntaxtest
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+
+	syntax error
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/test_syntax_error.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/test_syntax_error.cfg
new file mode 100644
index 0000000..2d5da7f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/test_syntax_error.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This script tests a syntax error in the startup
+# config script
+
+syntax error here
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti-ar7.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti-ar7.cfg
new file mode 100644
index 0000000..28b6cf7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti-ar7.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments AR7 SOC - used in many adsl modems.
+# http://www.linux-mips.org/wiki/AR7
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME ti-ar7
+}
+
+if { [info exists ENDIAN] } {
+    set _ENDIAN $ENDIAN
+} else {
+    set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x0000100f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_CHIPNAME.cpu
+
+# use onboard 4k sram as working area
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti-cjtag.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti-cjtag.cfg
new file mode 100644
index 0000000..97111f1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti-cjtag.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# A start sequence to change from cJTAG to 4-pin JTAG
+# This is needed for CC2538 and CC26xx to be able to communicate through JTAG
+# Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information.
+proc ti_cjtag_to_4pin_jtag {jrc} {
+	# Bypass
+	runtest 20
+	irscan $jrc 0x3f -endstate RUN/IDLE
+	# Two zero bit scans and a one bit drshift
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+
+	# A two bit drhift and a 9 bit drshift
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+
+	# Bypass
+	irscan $jrc 0x3f -endstate RUN/IDLE
+
+	# Set ICEPick IDCODE in data register
+	irscan $jrc 0x04 -endstate RUN/IDLE
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_calypso.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_calypso.cfg
new file mode 100644
index 0000000..9083336
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_calypso.cfg
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Calypso (lite) G2 C035 Digital Base Band chip
+#
+# ARM7TDMIE + DSP subchip (S28C128)
+#
+# 512K SRAM Calypso
+# 256K SRAM Calypso lite
+#
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME calypso
+}
+
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x3100e02f
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+adapter speed 1000
+
+reset_config trst_and_srst
+
+jtag newtap $_CHIPNAME dsp -expected-id 0x00000000 -irlen 8
+jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# target
+
+set _TARGETNAME $_CHIPNAME.arm
+target create $_TARGETNAME arm7tdmi -endian little -chain-position $_TARGETNAME
+
+# workarea
+
+$_TARGETNAME configure -work-area-phys 0x00800000 -work-area-size $_WORKAREASIZE -work-area-backup 1
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+$_TARGETNAME configure -event examine-start {
+	irscan calypso.arm 0x0b -endstate DRPAUSE
+	drscan calypso.arm 2 2 -endstate RUN/IDLE
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc13x0.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc13x0.cfg
new file mode 100644
index 0000000..f1c43a6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc13x0.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC13x0 - ARM Cortex-M3
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc13x0
+set JRC_TAPID 0x0B9BE02F
+set WORKAREASIZE 0x4000
+
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc13x2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc13x2.cfg
new file mode 100644
index 0000000..c850816
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc13x2.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC13x2 - ARM Cortex-M4
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc13x2
+set JRC_TAPID 0x0BB4102F
+set WORKAREASIZE 0x7000
+
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc26x0.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc26x0.cfg
new file mode 100644
index 0000000..b9ccf31
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc26x0.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC26x0 - ARM Cortex-M3
+#
+# http://www.ti.com
+#
+
+source [find target/icepick.cfg]
+source [find target/ti-cjtag.cfg]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cc26x0
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4BA00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+#
+# ICEpick-C (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID 0x0B99A02F
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
+# A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG
+jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
+
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x4000
+}
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
+
+cortex_m reset_config vectreset
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc26x2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc26x2.cfg
new file mode 100644
index 0000000..62c91c3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc26x2.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC26x2 - ARM Cortex-M4
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc26x2
+set JRC_TAPID 0x0BB4102F
+set WORKAREASIZE 0x7000
+
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc26x2x7.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc26x2x7.cfg
new file mode 100644
index 0000000..91c1a80
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc26x2x7.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC26x2 - ARM Cortex-M4
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc26x2x7
+set JRC_TAPID 0x1BB7702F
+set WORKAREASIZE 0x7000
+
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc3220sf.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc3220sf.cfg
new file mode 100644
index 0000000..cf43363
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc3220sf.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC3220SF - ARM Cortex-M4
+#
+# http://www.ti.com/CC3220SF
+#
+
+source [find target/swj-dp.tcl]
+source [find target/icepick.cfg]
+source [find target/ti_cc32xx.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
+
+#
+# On CC32xx family of devices, sysreqreset is disabled, and vectreset is
+# blocked by the boot loader (stops in a while(1) statement). srst reset can
+# leave the target in a state that prevents debug. The following uses the
+# soft_reset_halt command to reset and halt the target. Then the PC and stack
+# are initialized from internal flash. This allows for a more reliable reset,
+# but with two caveats: it only works for the SF variant that has internal
+# flash, and it only resets the CPU and not any peripherals.
+#
+
+proc ocd_process_reset_inner { MODE } {
+
+	soft_reset_halt
+
+	# Initialize MSP, PSP, and PC from vector table at flash 0x01000800
+	set boot [read_memory 0x01000800 32 2]
+
+	reg msp [lindex $boot 0]
+	reg psp [lindex $boot 0]
+	reg pc [lindex $boot 1]
+
+	if { 0 == [string compare $MODE run ] } {
+		resume
+	}
+
+	cc32xx.cpu invoke-event reset-end
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc32xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc32xx.cfg
new file mode 100644
index 0000000..9eb03eb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_cc32xx.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC32xx - ARM Cortex-M4
+#
+# http://www.ti.com/product/CC3200
+# http://www.ti.com/product/CC3220
+#
+
+source [find target/swj-dp.tcl]
+source [find target/icepick.cfg]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cc32xx
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	if {[using_jtag]} {
+		set _DAP_TAPID 0x4BA00477
+	} else {
+		set _DAP_TAPID 0x2BA01477
+	}
+}
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+	jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+} else {
+	swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
+}
+
+#
+# ICEpick-C (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID 0x0B97C02F
+}
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+	jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x2000
+}
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_dm355.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_dm355.cfg
new file mode 100644
index 0000000..4292373
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_dm355.cfg
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments DaVinci family: TMS320DM355
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dm355
+}
+
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
+#
+# Also note: when running without RTCK before the PLLs are set up, you
+# may need to slow the JTAG clock down quite a lot (under 2 MHz).
+#
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 1"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07926001
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b73b02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
+
+# various symbol definitions, to avoid hard-wiring addresses
+# and enable some sharing of DaVinci-family utility code
+global dm355
+set dm355 [ dict create ]
+
+# Physical addresses for controllers and memory
+# (Some of these are valid for many DaVinci family chips)
+dict set dm355 sram0		0x00010000
+dict set dm355 sram1		0x00014000
+dict set dm355 sysbase		0x01c40000
+dict set dm355 pllc1		0x01c40800
+dict set dm355 pllc2		0x01c40c00
+dict set dm355 psc		0x01c41000
+dict set dm355 gpio		0x01c67000
+dict set dm355 a_emif		0x01e10000
+dict set dm355 a_emif_cs0	0x02000000
+dict set dm355 a_emif_cs1	0x04000000
+dict set dm355 ddr_emif		0x20000000
+dict set dm355 ddr		0x80000000
+dict set dm355 uart0		0x01c20000
+dict set dm355 uart1		0x01c20400
+dict set dm355 uart2		0x01e06000
+
+source [find target/davinci.cfg]
+
+################
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
+# and the ETB memory (4K) are other options, while trace is unused.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+
+# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
+# and that the work area is used only with a kernel mmu context ...
+$_TARGETNAME configure \
+	-work-area-virt [expr {0xfffe0000 + 0x4000}] \
+	-work-area-phys [dict get $dm355 sram1] \
+	-work-area-size 0x4000 \
+	-work-area-backup 0
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_dm365.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_dm365.cfg
new file mode 100644
index 0000000..e19efd7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_dm365.cfg
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments DaVinci family: TMS320DM365
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dm365
+}
+
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 1"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x0792602f
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b83e02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
+
+# various symbol definitions, to avoid hard-wiring addresses
+# and enable some sharing of DaVinci-family utility code
+global dm365
+set dm365 [ dict create ]
+
+# Physical addresses for controllers and memory
+# (Some of these are valid for many DaVinci family chips)
+dict set dm365 sram0		0x00010000
+dict set dm365 sram1		0x00014000
+dict set dm365 sysbase		0x01c40000
+dict set dm365 pllc1		0x01c40800
+dict set dm365 pllc2		0x01c40c00
+dict set dm365 psc		0x01c41000
+dict set dm365 gpio		0x01c67000
+dict set dm365 a_emif		0x01d10000
+dict set dm365 a_emif_cs0	0x02000000
+dict set dm365 a_emif_cs1	0x04000000
+dict set dm365 ddr_emif		0x20000000
+dict set dm365 ddr		0x80000000
+
+source [find target/davinci.cfg]
+
+################
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
+# and the ETB memory (4K) are other options, while trace is unused.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+
+# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
+# and that the work area is used only with a kernel mmu context ...
+$_TARGETNAME configure \
+	-work-area-virt [expr {0xfffe0000 + 0x4000}] \
+	-work-area-phys [dict get $dm365 sram1] \
+	-work-area-size 0x4000 \
+	-work-area-backup 0
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_dm6446.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_dm6446.cfg
new file mode 100644
index 0000000..8938234
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_dm6446.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments DaVinci family: TMS320DM6446
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dm6446
+}
+
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: unknown ... must enable via ICEpick
+jtag newtap $_CHIPNAME unknown -irlen 8 -disable
+jtag configure $_CHIPNAME.unknown -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 3"
+
+# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
+jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
+jtag configure $_CHIPNAME.dsp -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 2"
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 1"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07926001
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b70002f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
+# and the ETB memory (4K) are other options, while trace is unused.
+# Little-endian; use the OpenOCD default.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_k3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_k3.cfg
new file mode 100644
index 0000000..2ae0f75
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_k3.cfg
@@ -0,0 +1,501 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments K3 devices:
+# * AM243: https://www.ti.com/lit/pdf/spruim2
+#  Has 4 R5 Cores, M4F and an M3
+# * AM263: https://www.ti.com/lit/pdf/spruj17
+#  Has 4 R5 Cores and an M3
+# * AM273: https://www.ti.com/lit/pdf/spruiu0
+#  Has 2 R5 Cores and an M3
+# * AM625: https://www.ti.com/lit/pdf/spruiv7a
+#  Has 4 ARMV8 Cores and 1 R5 Core and an M4F
+# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
+#  Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM62P: https://www.ti.com/lit/pdf/spruj83
+#  Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM642: https://www.ti.com/lit/pdf/spruim2
+#  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
+# * AM654x: https://www.ti.com/lit/pdf/spruid7
+#  Has 4 ARMV8 Cores and 2 R5 Cores and an M3
+# * J7200: https://www.ti.com/lit/pdf/spruiu1
+#  Has 2 ARMV8 Cores and 4 R5 Cores and an M3
+# * J721E: https://www.ti.com/lit/pdf/spruil1
+#  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
+# * J721S2: https://www.ti.com/lit/pdf/spruj28
+#  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
+# * J722S: https://www.ti.com/lit/zip/sprujb3
+#  Has 4 ARMV8 Cores and 3 R5 Cores
+# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
+#  Has 8 ARMV8 Cores and 8 R5 Cores
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc am654
+}
+
+# set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
+if { [info exists V8_SMP_DEBUG] } {
+	set _v8_smp_debug $V8_SMP_DEBUG
+} else {
+	set _v8_smp_debug 0
+}
+
+# Common Definitions
+
+# System Controller is the very first processor - all current SoCs have it.
+set CM3_CTIBASE		{0x3C016000}
+
+# sysctrl power-ap unlock offsets
+set _sysctrl_ap_unlock_offsets {0xf0 0x44}
+set _sysctrl_ap_num 7
+
+# All the ARMV8s are the next processors.
+#		   CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1
+set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
+set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
+
+# And we add up the R5s
+#		(0)MCU 0   (1)MCU 1   (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
+set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
+set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+set _r5_ap_num 1
+
+# Finally an General Purpose(GP) MCU
+set CM4_CTIBASE		{0x20001000}
+
+# General Purpose MCU (M4) may be present on some very few SoCs
+set _gp_mcu_cores 0
+# General Purpose MCU power-ap unlock offsets
+set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
+
+# Generic mem-ap port number
+set _mem_ap_num 2
+
+# Set configuration overrides for each SOC
+switch $_soc {
+	am263 {
+		set _K3_DAP_TAPID 0x2bb7d02f
+
+		# Mem-ap port
+		set _mem_ap_num 6
+
+		# AM263 has 0 ARMV8 CPUs
+		set _armv8_cores 0
+
+		# AM263 has 2 cluster of 2 R5s cores.
+		set _r5_cores 4
+		set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+		set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
+		set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
+		set _r5_ap_num 5
+	}
+	am273 {
+		set _K3_DAP_TAPID 0x1bb6a02f
+
+		# Mem-ap port
+		set _mem_ap_num 6
+
+		# system controller is on AP0
+		set _sysctrl_ap_num 0
+
+		# AM273 has 0 ARMV8 CPUs
+		set _armv8_cores 0
+
+		# AM273 has 1 cluster of 2 R5s cores.
+		set _r5_cores 2
+		set R5_NAMES {main0_r5.0 main0_r5.1}
+		set R5_DBGBASE {0x90030000 0x90032000}
+		set R5_CTIBASE {0x90038000 0x90039000}
+		set _r5_ap_num 5
+	}
+	am654 {
+		set _K3_DAP_TAPID 0x0bb5a02f
+
+		# AM654 has 2 clusters of 2 A53 cores each.
+		set _armv8_cpu_name a53
+		set _armv8_cores 4
+
+		# AM654 has 1 cluster of 2 R5s cores.
+		set _r5_cores 2
+		set R5_NAMES {mcu_r5.0 mcu_r5.1}
+
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x50}
+	}
+	am243 -
+	am642 {
+		set _K3_DAP_TAPID 0x0bb3802f
+
+		# AM642 has 1 clusters of 2 A53 cores each.
+		set _armv8_cpu_name a53
+		set _armv8_cores 2
+		set ARMV8_DBGBASE {0x90010000 0x90110000}
+		set ARMV8_CTIBASE {0x90020000 0x90120000}
+
+		# AM642 has 2 cluster of 2 R5s cores.
+		set _r5_cores 4
+		set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+		set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
+		set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+
+		# M4 processor
+		set _gp_mcu_cores 1
+
+		# Overrides for am243
+		if { "$_soc" == "am243" } {
+			# Uses the same JTAG ID
+			set _armv8_cores 0
+		}
+	}
+	am625 {
+		set _K3_DAP_TAPID 0x0bb7e02f
+
+		# AM625 has 1 clusters of 4 A53 cores.
+		set _armv8_cpu_name a53
+		set _armv8_cores 4
+		set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+		set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+		# AM625 has 1 cluster of 1 R5s core.
+		set _r5_cores 1
+		set R5_NAMES {main0_r5.0}
+		set R5_DBGBASE {0x9d410000}
+		set R5_CTIBASE {0x9d418000}
+
+		# sysctrl CTI base
+		set CM3_CTIBASE {0x20001000}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+		# M4 processor
+		set _gp_mcu_cores 1
+		set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+
+		# Setup DMEM access descriptions
+		# DAPBUS (Debugger) description
+		set _dmem_base_address 0x740002000
+		set _dmem_ap_address_offset 0x100
+		set _dmem_max_aps 10
+		# Emulated AP description
+		set _dmem_emu_base_address 0x760000000
+		set _dmem_emu_base_address_map_to 0x1d500000
+		set _dmem_emu_ap_list 1
+	}
+	j722s -
+	am62p -
+	am62a7 {
+		set _K3_DAP_TAPID 0x0bb8d02f
+
+		# AM62a7/AM62P has 1 cluster of 4 A53 cores.
+		set _armv8_cpu_name a53
+		set _armv8_cores 4
+		set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+		set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+		# AM62a7/AM62P has 2 cluster of 1 R5 core.
+		set _r5_cores 2
+		set R5_NAMES {main0_r5.0 mcu0_r5.0}
+		set R5_DBGBASE {0x9d410000 0x9d810000}
+		set R5_CTIBASE {0x9d418000 0x9d818000}
+
+		# sysctrl CTI base
+		set CM3_CTIBASE {0x20001000}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+		# Setup DMEM access descriptions
+		# DAPBUS (Debugger) description
+		set _dmem_base_address 0x740002000
+		set _dmem_ap_address_offset 0x100
+		set _dmem_max_aps 10
+		# Emulated AP description
+		set _dmem_emu_base_address 0x760000000
+		set _dmem_emu_base_address_map_to 0x1d500000
+		set _dmem_emu_ap_list 1
+
+		# Overrides for am62p
+		if { "$_soc" == "am62p" } {
+			set _K3_DAP_TAPID 0x0bb9d02f
+			set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
+		}
+		# Overrides for j722s
+		if { "$_soc" == "j722s" } {
+			set _K3_DAP_TAPID 0x0bba002f
+			set _r5_cores 3
+			set R5_NAMES {wkup0_r5.0 main0_r5.0 mcu0_r5.0}
+			set R5_DBGBASE {0x9d410000 0x9d510000 0x9d810000}
+			set R5_CTIBASE {0x9d418000 0x9d518000 0x9d818000}
+		}
+	}
+	j721e {
+		set _K3_DAP_TAPID 0x0bb6402f
+		# J721E has 1 cluster of 2 A72 cores.
+		set _armv8_cpu_name a72
+		set _armv8_cores 2
+
+		# J721E has 3 clusters of 2 R5 cores each.
+		set _r5_cores 6
+
+		# Setup DMEM access descriptions
+		# DAPBUS (Debugger) description
+		set _dmem_base_address 0x4c40002000
+		set _dmem_ap_address_offset 0x100
+		set _dmem_max_aps 8
+		# Emulated AP description
+		set _dmem_emu_base_address 0x4c60000000
+		set _dmem_emu_base_address_map_to 0x1d600000
+		set _dmem_emu_ap_list 1
+	}
+	j7200 {
+		set _K3_DAP_TAPID 0x0bb6d02f
+
+		# J7200 has 1 cluster of 2 A72 cores.
+		set _armv8_cpu_name a72
+		set _armv8_cores 2
+
+		# J7200 has 2 clusters of 2 R5 cores each.
+		set _r5_cores 4
+		set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
+		set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
+
+		# M3 CTI base
+		set CM3_CTIBASE {0x20001000}
+	}
+	j721s2 {
+		set _K3_DAP_TAPID 0x0bb7502f
+
+		# J721s2 has 1 cluster of 2 A72 cores.
+		set _armv8_cpu_name a72
+		set _armv8_cores 2
+
+		# J721s2 has 3 clusters of 2 R5 cores each.
+		set _r5_cores 6
+
+		# sysctrl CTI base
+		set CM3_CTIBASE {0x20001000}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+		# M4 processor
+		set _gp_mcu_cores 1
+		set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+	}
+	j784s4 {
+		set _K3_DAP_TAPID 0x0bb8002f
+
+		# j784s4 has 2 cluster of 4 A72 cores each.
+		set _armv8_cpu_name a72
+		set _armv8_cores 8
+		set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
+                           0x90810000 0x90910000 0x90a10000 0x90b10000}
+		set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
+                           0x90820000 0x90920000 0x90a20000 0x90b20000}
+
+		# J721s2 has 4 clusters of 2 R5 cores each.
+		set _r5_cores 8
+		set R5_DBGBASE {0x9d010000 0x9d012000
+                        0x9d410000 0x9d412000
+                        0x9d510000 0x9d512000
+                        0x9d610000 0x9d612000}
+		set R5_CTIBASE {0x9d018000 0x9d019000
+                        0x9d418000 0x9d419000
+                        0x9d518000 0x9d519000
+                        0x9d618000 0x9d619000}
+		set R5_NAMES {mcu_r5.0 mcu_r5.1
+                      main0_r5.0 main0_r5.1
+                      main1_r5.0 main1_r5.1
+                      main2_r5.0 main2_r5.1}
+
+		# sysctrl CTI base
+		set CM3_CTIBASE {0x20001000}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+	}
+	default {
+		echo "'$_soc' is invalid!"
+	}
+}
+
+proc _get_rtos_type_for_cpu { target_name } {
+	if { [info exists ::RTOS($target_name)] } {
+		return $::RTOS($target_name)
+	}
+	return none
+}
+
+set _CHIPNAME $_soc
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+set _CTINAME $_CHIPNAME.cti
+
+# sysctrl is always present
+cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
+	-ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
+
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
+	-ap-num $_sysctrl_ap_num -defer-examine \
+	-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
+
+$_TARGETNAME.sysctrl configure -event reset-assert { }
+
+proc sysctrl_up {} {
+	# To access sysctrl, we need to enable the JTAG access for the same.
+	# Ensure Power-AP unlocked
+	$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
+	$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
+
+	$::_TARGETNAME.sysctrl arp_examine
+}
+
+$_TARGETNAME.sysctrl configure -event gdb-attach {
+	sysctrl_up
+	# gdb-attach default rule
+	halt 1000
+}
+
+proc _cpu_no_smp_up {} {
+	set _current_target [target current]
+	set _current_type [$_current_target cget -type]
+
+	$_current_target arp_examine
+	$_current_target $_current_type dbginit
+}
+
+proc _armv8_smp_up {} {
+	for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
+		$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
+		$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+		$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
+	}
+	# Set Default target as core 0
+	targets $::_TARGETNAME.$::_armv8_cpu_name.0
+}
+
+set _v8_smp_targets ""
+
+for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
+
+	cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+		-baseaddr [lindex $ARMV8_CTIBASE $_core]
+
+	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
+		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
+
+	set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
+
+	if { $_v8_smp_debug == 0 } {
+		$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+			_cpu_no_smp_up
+			# gdb-attach default rule
+			halt 1000
+		}
+	} else {
+		$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+			_armv8_smp_up
+			# gdb-attach default rule
+			halt 1000
+		}
+	}
+}
+
+if { $_armv8_cores > 0 } {
+	# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
+	set _armv8_up_cmd "$_armv8_cpu_name"_up
+	# Available if V8_SMP_DEBUG is set to non-zero value
+	set _armv8_smp_cmd "$_armv8_cpu_name"_smp
+
+	if { $_v8_smp_debug == 0 } {
+		proc $_armv8_up_cmd { args } {
+			foreach _core $args {
+				targets $_core
+				_cpu_no_smp_up
+			}
+		}
+	} else {
+		proc $_armv8_smp_cmd { args } {
+			_armv8_smp_up
+		}
+		# Declare SMP
+		target smp {*}$_v8_smp_targets
+	}
+}
+
+for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
+	set _r5_name [lindex $R5_NAMES $_core]
+	cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
+		-baseaddr [lindex $R5_CTIBASE $_core]
+
+	# inactive core examination will fail - wait till startup of additional core
+	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
+		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
+
+	$_TARGETNAME.$_r5_name configure -event gdb-attach {
+		_cpu_no_smp_up
+		# gdb-attach default rule
+		halt 1000
+	}
+}
+
+proc r5_up { args } {
+	foreach  _core $args {
+		targets $_core
+		_cpu_no_smp_up
+	}
+}
+
+if { $_gp_mcu_cores != 0 } {
+	cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
+	target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
+	$_TARGETNAME.gp_mcu configure -event reset-assert { }
+
+	proc gp_mcu_up {} {
+		# To access GP MCU, we need to enable the JTAG access for the same.
+		# Ensure Power-AP unlocked
+		$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
+		$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
+
+		$::_TARGETNAME.gp_mcu arp_examine
+	}
+
+	$_TARGETNAME.gp_mcu configure -event gdb-attach {
+		gp_mcu_up
+		# gdb-attach default rule
+		halt 1000
+	}
+}
+
+# In case of DMEM access, configure the dmem adapter with offsets from above.
+if { 0 == [string compare [adapter name] dmem ] } {
+	if { [info exists _dmem_base_address] } {
+		# DAPBUS (Debugger) description
+		dmem base_address $_dmem_base_address
+		dmem ap_address_offset $_dmem_ap_address_offset
+		dmem max_aps $_dmem_max_aps
+
+		# The following are the details of APs to be emulated for direct address access.
+		# Debug Config (Debugger) description
+		dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
+		dmem emu_ap_list $_dmem_emu_ap_list
+		# We are going local bus, so speed is really dummy here.
+		adapter speed 2500
+	} else {
+		puts "ERROR: ${SOC} data is missing to support dmem access!"
+	}
+} else {
+	# AXI AP access port for SoC address map
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_msp432.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_msp432.cfg
new file mode 100644
index 0000000..8a90b98
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_msp432.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments MSP432 - ARM Cortex-M4F @ up to 48 MHz
+#
+# http://www.ti.com/MSP432
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME msp432
+}
+
+if { [info exists CPUTAPID] } {
+	set _DAP_TAPID $CPUTAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+if { [info exists DAP_SWD_ID] } {
+	set _DAP_SWD_ID $DAP_SWD_ID
+} else {
+	set _DAP_SWD_ID 0x2ba01477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+	set _DAP_ID $_DAP_TAPID
+} else {
+	set _DAP_ID $_DAP_SWD_ID
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x4000
+}
+
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
+
+cortex_m reset_config sysresetreq
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_rm4x.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_rm4x.cfg
new file mode 100644
index 0000000..715aa5b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_rm4x.cfg
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/ti_tms570.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570.cfg
new file mode 100644
index 0000000..18e0d82
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed 1500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME tms570
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN big
+}
+
+# TMS570 has an ICEpick-C on which we need the router commands.
+source [find target/icepick.cfg]
+
+# Main DAP
+# DAP_TAPID should be set before source-ing this file
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# ICEpick-C (JTAG route controller)
+# JRC_TAPID should be set before source-ing this file
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+}
+
+set _JRC_TAPID2 0x0B7B302F
+set _JRC_TAPID3 0x0B95502F
+set _JRC_TAPID4 0x0B97102F
+set _JRC_TAPID5 0x0D8A002F
+set _JRC_TAPID6 0x0B8A002F
+
+
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID \
+	-expected-id $_JRC_TAPID2 \
+	-expected-id $_JRC_TAPID3 \
+	-expected-id $_JRC_TAPID4 \
+	-expected-id $_JRC_TAPID5 \
+	-expected-id $_JRC_TAPID6 \
+	-ignore-version
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Cortex-R4 target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
+	-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000
+
+# TMS570 uses quirky BE-32 mode
+$_CHIPNAME.dap ti_be_32_quirks 1
+
+$_TARGETNAME configure -event "reset-assert" {
+	global _CHIPNAME
+
+	# assert warm system reset through ICEPick
+	icepick_c_wreset $_CHIPNAME.jrc
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570lc43xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570lc43xx.cfg
new file mode 100644
index 0000000..ffda989
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570lc43xx.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set DAP_TAPID 0x0B95A02F
+set JRC_TAPID 0x0B95A02F
+
+source [find target/ti_tms570.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570ls20xxx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570ls20xxx.cfg
new file mode 100644
index 0000000..cc2bbd6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570ls20xxx.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TMS570LS20216, TMS570LS20206, TMS570LS10216
+# TMS570LS10206, TMS570LS10116, TMS570LS10106
+set DAP_TAPID 0x0B7B302F
+set JRC_TAPID 0x0B7B302F
+
+source [find target/ti_tms570.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570ls3137.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570ls3137.cfg
new file mode 100644
index 0000000..ebe2cfc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/ti_tms570ls3137.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TMS570LS3137
+set DAP_TAPID 0x0B8A002F
+set JRC_TAPID 0x0B8A002F
+
+source [find target/ti_tms570.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/tmpa900.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/tmpa900.cfg
new file mode 100644
index 0000000..b7ec689
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/tmpa900.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Toshiba TMPA900
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME tmpa900
+}
+
+# Toshiba TMPA900 series MCUs are always little endian as per datasheet.
+set _ENDIAN little
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926031
+}
+
+#TMPA900 has following IDs:
+# CP15.0 register 0x41069265
+# CP15.1 register 0x1d152152
+# ARM core 0x07926031
+
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+adapter srst delay 20
+jtag_ntrst_delay 20
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Internal RAM-0 (16kB): 0xf8004000
+# Internal RAM-1 (8kB): 0xf8008000
+
+# Use internal RAM-0 and RAM-1 as working area (24kB total).
+$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0x6000 \
+-work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/tmpa910.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/tmpa910.cfg
new file mode 100644
index 0000000..276d1ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/tmpa910.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Toshiba TMPA910
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME tmpa910
+}
+
+# Toshiba TMPA910 series MCUs are always little endian as per datasheet.
+set _ENDIAN little
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926031
+}
+
+#TMPA910 has following IDs:
+# CP15.0 register 0x41069265
+# CP15.1 register 0x1d152152
+# ARM core 0x07926031
+
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+adapter srst delay 20
+jtag_ntrst_delay 20
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Internal RAM-0 (16kB): 0xf8004000
+# Internal RAM-1 (16kB): 0xf8008000
+# Internal RAM-2 (16kB): 0xf800c000
+
+# Use internal RAM-0, RAM-1, and RAM-2 as working area (48kB total).
+$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0xc000 \
+-work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/tnetc4401.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/tnetc4401.cfg
new file mode 100644
index 0000000..6a24980
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/tnetc4401.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Texas Instruments (TI) TNETC4401, MIPS32 DOCSIS-tailored SoC (4Kc-based)
+# Used in Knovative KC-100 and Motorola Surfboard SB5120 cable modems.
+# Datasheet: https://brezn.muc.ccc.de/~mazzoo/DOCSIS/tnetc4401.pdf
+transport select jtag
+set _TARGETNAME tnetc4401
+set _CPUTAPID 0x0000100f
+jtag newtap $_TARGETNAME tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
+target create $_TARGETNAME mips_m4k -chain-position $_TARGETNAME.tap -endian big
+
+# May need to halt manually before calling reset init
+$_TARGETNAME configure -event reset-init {
+	halt
+	echo "Attempting to disable watchdog..."
+	mwb phys 0xa8610b00 0 256
+	halt
+	wait_halt
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/u8500.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/u8500.cfg
new file mode 100644
index 0000000..1fdc11f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/u8500.cfg
@@ -0,0 +1,326 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) ST-Ericsson SA 2011
+#  Author : michel.jaouen@stericsson.com
+#  U8500 target
+
+proc mmu_off {} {
+	set cp [arm mrc 15 0 1 0 0]
+	set cp [expr {$cp & ~1}]
+	arm mcr 15 0 1 0 0 $cp
+}
+
+proc mmu_on {} {
+	set cp [arm mrc 15 0 1 0 0]
+	set cp [expr {$cp | 1}]
+	arm mcr 15 0 1 0 0 $cp
+}
+
+proc ocd_gdb_restart {target_id} {
+    global _TARGETNAME_1
+	global _SMP
+    targets $_TARGETNAME_1
+	if { $_SMP == 1 } {
+	cortex_a smp off
+	}
+	rst_run
+	halt
+	if { $_SMP == 1 } {
+	cortex_a smp on
+	}
+}
+
+proc smp_reg {} {
+	global _TARGETNAME_1
+    global _TARGETNAME_2
+    targets $_TARGETNAME_1
+	echo "$_TARGETNAME_1"
+	set pc1 [reg pc]
+	set stck1 [reg sp_svc]
+	targets $_TARGETNAME_2
+	echo "$_TARGETNAME_1"
+	set pc2 [reg pc]
+	set stck2 [reg sp_svc]
+}
+
+
+proc u8500_tapenable {chip val} {
+	echo "JTAG tap enable $chip"
+}
+
+
+proc pwrsts { } {
+	global _CHIPNAME
+	irscan $_CHIPNAME.jrc 0x3a
+	drscan $_CHIPNAME.jrc 4 0
+	set pwrsts [drscan $_CHIPNAME.jrc 16 0]
+	echo "pwrsts ="$pwrsts
+	set a9 [expr "0x$pwrsts & 0xc"]
+	set ape [expr "0x$pwrsts & 0x3"]
+	if {[string equal "0" $ape]} {
+		echo "ape off"
+	} else {
+		echo "ape on"
+	}
+	echo "$a9"
+	switch $a9 {
+		4 {
+			echo "A9 in retention"
+		  }
+		8 {
+			echo "A9 100% DVFS"
+		  }
+		c {
+			echo "A9 50% DVFS"
+		}
+	}
+}
+
+proc poll_pwrsts { } {
+	global _CHIPNAME
+	set result 1
+	set i 0
+	irscan $_CHIPNAME.jrc 0x3a
+	drscan $_CHIPNAME.jrc 4 0
+	set pwrsts [drscan $_CHIPNAME.jrc 16 0]
+	set pwrsts [expr "0x$pwrsts & 0xc"]
+	while {[string equal "4" $pwrsts] && $i<20} {
+		irscan $_CHIPNAME.jrc 0x3a
+		drscan $_CHIPNAME.jrc 4 0;
+		set pwrsts [drscan $_CHIPNAME.jrc 16 0]
+		set pwrsts [expr "0x$pwrsts & 0xc"]
+		if {![string equal "4" $pwrsts]} {
+			set result 1
+		} else {
+			set result 0
+			sleep 200
+			echo "loop $i"
+		}
+		incr i
+	}
+	return $result
+}
+
+proc halt_ { } {
+	if {[poll_pwrsts]==1} {
+		halt
+	} else {
+		echo "halt failed : target in retention"
+	}
+}
+
+
+proc u8500_dapenable {chip} {
+}
+
+proc u8500_tapdisable {chip val} {
+	echo "JTAG tap disable $chip"
+}
+
+
+proc enable_apetap {} {
+	global _CHIPNAME
+	global _TARGETNAME_2
+    global _TARGETNAME_1
+	poll off
+	irscan $_CHIPNAME.jrc 0x3e
+	drscan $_CHIPNAME.jrc 8 0xcf
+	jtag tapenable $_CHIPNAME.dap
+	irscan $_CHIPNAME.jrc 0x6
+	drscan $_CHIPNAME.jrc 32 0
+	irscan $_CHIPNAME.jrc 0x6
+	drscan $_CHIPNAME.jrc 32 0
+	set status [$_TARGETNAME_1 curstate]
+    if {[string equal "unknown" $status]} {
+	$_TARGETNAME_1 arp_examine
+	cache_config l2x 0xa0412000 8
+	}
+
+	set status [$_TARGETNAME_2 curstate]
+    if {[string equal "unknown" $status]} {
+	$_TARGETNAME_2 arp_examine
+	}
+	}
+
+tcl port 5555
+telnet port 4444
+gdb port 3333
+
+if { [info exists CHIPNAME] } {
+global _CHIPNAME
+    set _CHIPNAME $CHIPNAME
+} else {
+global _CHIPNAME
+	set _CHIPNAME u8500
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+	set _ENDIAN little
+}
+
+
+
+# Subsidiary TAP: APE with scan chains for ARM Debug, EmbeddedICE-RT,
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+	"u8500_dapenable $_CHIPNAME.cpu"
+jtag configure $_CHIPNAME.cpu -event tap-disable \
+	"u8500_tapdisable $_CHIPNAME.cpu 0xc0"
+
+
+#CLTAPC TAP JRC equivalent
+if { [info exists CLTAPC_ID] } {
+   set _CLTAPC_ID $CLTAPC_ID
+} else {
+   set _CLTAPC_ID 0x22286041
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x6 -irmask 0xf -expected-id $_CLTAPC_ID -ignore-version
+
+
+if { ![info exists TARGETNAME_1] } {
+global _TARGETNAME_1
+set _TARGETNAME_1 $_CHIPNAME.cpu1
+} else {
+global _TARGETNAME_1
+set _TARGETNAME_1 $TARGETNAME_1
+}
+
+if { [info exists DAP_DBG1] } {
+	set _DAP_DBG1 $DAP_DBG1
+} else {
+	set _DAP_DBG1 0x801A8000
+}
+if { [info exists DAP_DBG2] } {
+	set _DAP_DBG2 $DAP_DBG2
+} else {
+	set _DAP_DBG2 0x801AA000
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME_1 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
+
+
+if { ![info exists TARGETNAME_2] } {
+global _TARGETNAME_2
+set _TARGETNAME_2 $_CHIPNAME.cpu2
+} else {
+global _TARGETNAME_2
+set _TARGETNAME_2 $TARGETNAME_2
+}
+
+target create $_TARGETNAME_2 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
+
+
+if {![info exists SMP]} {
+global _SMP
+set _SMP 1
+} else {
+global _SMP
+set _SMP $SMP
+}
+global SMP
+if { $_SMP == 1} {
+target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
+}
+
+
+
+
+proc secsts1 { } {
+	global _CHIPNAME
+        irscan $_CHIPNAME.jrc 0x3a
+		drscan $_CHIPNAME.jrc 4 4
+	set secsts1 [drscan $_CHIPNAME.jrc 16 0]
+	echo "secsts1 ="$secsts1
+	set secsts1 [expr "0x$secsts1 & 0x4"]
+	if {![string equal "4" $secsts1]} {
+	echo "APE target secured"
+        } else {
+        echo "APE target not secured"
+        }
+}
+
+proc att { } {
+	global _CHIPNAME
+	jtag arp_init
+	irscan $_CHIPNAME.jrc 0x3a
+	drscan $_CHIPNAME.jrc 4 4
+	set secsts1 [drscan $_CHIPNAME.jrc 16 0]
+	echo "secsts1 ="$secsts1
+	set secsts1 [expr "0x$secsts1 & 0x4"]
+	if {[string equal "4" $secsts1]} {
+		if {[poll_pwrsts]==1} {
+		enable_apetap
+                } else {
+		echo "target in retention"
+		}
+	} else {
+		echo "target secured"
+	}
+
+}
+
+
+
+proc rst_run { } {
+	global _CHIPNAME
+	global _TARGETNAME_2
+	global _TARGETNAME_1
+	set status [$_TARGETNAME_1 curstate]
+	if {[string equal "halted" $status]} {
+	resume
+	targets $_TARGETNAME_1
+	}
+    set status [$_TARGETNAME_2 curstate]
+	if {[string equal "halted" $status]} {
+	resume
+	targets $_TARGETNAME_2
+	}
+   	poll off
+	jtag arp_init
+	reset
+	sleep 20
+	irscan $_CHIPNAME.jrc 0x3a
+	drscan $_CHIPNAME.jrc 4 4
+	set secsts1 [drscan $_CHIPNAME.jrc 16 0]
+	echo "secsts1 ="$secsts1
+	set secsts1 [expr "0x$secsts1 & 0x4"]
+	while {![string equal "4" $secsts1]} {
+		irscan u8500.jrc 0x3a
+		drscan u8500.jrc 4 4
+		set secsts1 [drscan $_CHIPNAME.jrc 16 0]
+		echo "secsts1 ="$secsts1
+		set secsts1 [expr "0x$secsts1 & 0x4"]
+	}
+	echo "ape debugable"
+	enable_apetap
+	poll on
+	targets $_TARGETNAME_1
+	dap apsel 1
+}
+
+if {![info exists MAXSPEED]} {
+global _MAXSPEED
+set _MAXSPEED 15000
+} else {
+global _MAXSPEED
+set _MAXSPEED $MAXSPEED
+}
+global _MAXSPEED
+adapter speed $_MAXSPEED
+
+
+gdb breakpoint_override hard
+set mem inaccessible-by-default-off
+
+jtag_ntrst_delay 100
+reset_config trst_and_srst combined
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vd_aarch64.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vd_aarch64.cfg
new file mode 100644
index 0000000..177416b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vd_aarch64.cfg
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm v8 64b Cortex A
+
+if {![info exists CORES]} {
+	set CORES 1
+}
+if {![info exists CHIPNAME]} {
+	set CHIPNAME aarch64
+}
+if {[info exists ACCESSPORT]} {
+	set _APNUM "-ap-num $ACCESSPORT"
+	if { $ACCESSPORT > 0xff } {
+		set _DAP6 "-adiv6"
+	} else {
+		set _DAP6 "-adiv5"
+	}
+} else {
+	set _APNUM ""
+}
+
+set _TARGETNAME $CHIPNAME.cpu
+set _CTINAME $CHIPNAME.cti
+set _DAPNAME $CHIPNAME.dap
+
+dap create $_DAPNAME $_DAP6 -chain-position $_TARGETNAME
+
+for { set _core 0 } { $_core < $CORES } { incr _core } \
+{
+	set _cmd "cti create $_CTINAME.$_core -dap $_DAPNAME $_APNUM -baseaddr [lindex $CTIBASE $_core]"
+	eval $_cmd
+	set _cmd "target create $_TARGETNAME.$_core aarch64 -dap $_DAPNAME $_APNUM -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
+	if { $_core != 0 } {
+		# non-boot core examination may fail
+		set _cmd "$_cmd -defer-examine"
+		set _smp_cmd "$_smp_cmd $_TARGETNAME.$_core"
+	} else {
+		set _smp_cmd "target smp $_TARGETNAME.$_core"
+	}
+	eval $_cmd
+}
+eval $_smp_cmd
+
+set _TARGETCUR $_TARGETNAME.0
+targets $_TARGETCUR
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vd_cortex_m.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vd_cortex_m.cfg
new file mode 100644
index 0000000..7db9d3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vd_cortex_m.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# ARM Cortex M
+
+if {![info exists CHIPNAME]} {
+	set CHIPNAME cortex_m
+}
+set _TARGETNAME $CHIPNAME.cpu
+set _DAPNAME $CHIPNAME.dap
+
+dap create $_DAPNAME -chain-position $_TARGETNAME
+
+target create $_TARGETNAME cortex_m -dap $_DAPNAME
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vd_riscv.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vd_riscv.cfg
new file mode 100644
index 0000000..f08cb1a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vd_riscv.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV core
+
+if {![info exists _HARTID]} {
+	set _HARTID 0x00
+}
+if {![info exists _CHIPNAME]} {
+	set _CHIPNAME riscv
+}
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+riscv set_mem_access sysbus progbuf
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vybrid_vf6xx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vybrid_vf6xx.cfg
new file mode 100644
index 0000000..776c16b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/vybrid_vf6xx.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Vybrid VF610
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME vf610
+}
+
+if { [info exists A5_JTAG_TAPID] } {
+	set _A5_JTAG_TAPID $A5_JTAG_TAPID
+} else {
+	set _A5_JTAG_TAPID 0x4BA00477
+}
+
+if { [info exists A5_SWD_TAPID] } {
+	set _A5_SWD_TAPID $A5_SWD_TAPID
+} else {
+	set _A5_SWD_TAPID 0x3BA02477
+}
+
+if { [using_jtag] } {
+	set _A5_TAPID $_A5_JTAG_TAPID
+} else {
+	set _A5_TAPID $_A5_SWD_TAPID
+}
+
+source [find target/swj-dp.tcl]
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000
+target create ${_TARGETNAME}1 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xilinx_zynqmp.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xilinx_zynqmp.cfg
new file mode 100644
index 0000000..e8224be
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xilinx_zynqmp.cfg
@@ -0,0 +1,240 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# target configuration for
+# Xilinx ZynqMP (UltraScale+ / A53)
+#
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME uscale
+}
+
+#
+# DAP tap (Quard core A53)
+#
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x5ba00477
+}
+
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+#
+# PS tap (UltraScale+)
+#
+if { [info exists PS_TAPID] } {
+    set _PS_TAPID $PS_TAPID
+    jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
+} else {
+    # FPGA Programmable logic. Values take from Table 39-1 in UG1085:
+    jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -ignore-version \
+        -expected-id 0x04711093 \
+        -expected-id 0x04710093 \
+        -expected-id 0x04721093 \
+        -expected-id 0x04720093 \
+        -expected-id 0x04739093 \
+        -expected-id 0x04730093 \
+        -expected-id 0x04738093 \
+        -expected-id 0x04740093 \
+        -expected-id 0x04750093 \
+        -expected-id 0x04759093 \
+        -expected-id 0x04758093
+}
+
+set jtag_configured 0
+
+jtag configure $_CHIPNAME.ps -event setup {
+    global _CHIPNAME
+    global jtag_configured
+
+    if { $jtag_configured == 0 } {
+        # add the DAP tap to the chain
+        # See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924
+        irscan $_CHIPNAME.ps 0x824
+        drscan $_CHIPNAME.ps 32 0x00000003
+        runtest 100
+
+        # setup event will be re-entered through jtag arp_init
+        # break the recursion
+        set jtag_configured 1
+        # re-initialized the jtag chain
+        jtag arp_init
+    }
+}
+
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+set _smp_command ""
+
+set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+set _cores 4
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -baseaddr [lindex $CTIBASE $_core]
+
+    set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command $_TARGETNAME.$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp $_TARGETNAME.$_core"
+    }
+
+    eval $_command
+}
+
+target create uscale.axi mem_ap -dap uscale.dap -ap-num 0
+
+eval $_smp_command
+targets $_TARGETNAME.0
+
+proc core_up { args } {
+    global _TARGETNAME
+    foreach core $args {
+        $_TARGETNAME.$core arp_examine
+    }
+}
+
+proc BIT {n} {
+	return [expr {1 << $n}]
+}
+
+set IPI_BASE			0xff300000
+set IPI_PMU_0_TRIG		[expr {$IPI_BASE + 0x30000}]
+set IPI_PMU_0_IER		[expr {$IPI_BASE + 0x30018}]
+set IPI_PMU_0					[BIT 16]
+
+set CRF_APB_BASE		0xfd1a0000
+set CRF_APB_RST_FPD_APU		[expr {$CRF_APB_BASE + 0x104}]
+set CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET	[BIT 10]
+set CRF_APB_RST_FPD_APU_L2_RESET		[BIT  8]
+set CRF_APB_RST_FPD_APU_ACPU0_RESET		[BIT  0]
+
+set APU_BASE			0xfd5c0000
+set APU_RVBARADDR_BASE		[expr {$APU_BASE + 0x40}]
+
+set PMU_BASE			0xffd80000
+set PMU_GLOBAL			$PMU_BASE
+set PMU_GLOBAL_MB_SLEEP				[BIT 16]
+set PMU_GLOBAL_FW_IS_PRESENT			[BIT  4]
+set PMU_GLOBAL_DONT_SLEEP			[BIT  0]
+
+set PMU_RAM_BASE		0xffdc0000
+
+set OCM_RAM_BASE		0xfffc0000
+
+rename BIT {}
+
+add_help_text halt_pmu "Halt the PMU in preparation for loading new firmware.\
+	This should be matched with a call to resume_pmu."
+proc halt_pmu {} {
+	set axi $::_CHIPNAME.axi
+	set val [$axi read_memory $::IPI_PMU_0_IER 32 1]
+	$axi write_memory $::IPI_PMU_0_IER 32 [expr {$val | $::IPI_PMU_0}]
+
+	set val [$axi read_memory $::IPI_PMU_0_TRIG 32 1]
+	$axi write_memory $::IPI_PMU_0_TRIG 32 [expr {$val | $::IPI_PMU_0}]
+
+	set start [ms]
+	while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_MB_SLEEP)} {
+		if {[ms] - $start > 1000} {
+			error "Timed out waiting for PMU to halt"
+		}
+	}
+}
+
+add_help_text resume_pmu "Resume the PMU after loading new firmware. This\
+	should be matched with a call to halt_pmu."
+proc resume_pmu {} {
+	set axi $::_CHIPNAME.axi
+	set val [$axi read_memory $::PMU_GLOBAL 32 1]
+	$axi write_memory $::PMU_GLOBAL 32 [expr {$val | $::PMU_GLOBAL_DONT_SLEEP}]
+
+	set start [ms]
+	while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_FW_IS_PRESENT)} {
+		if {[ms] - $start > 5000} {
+			error "Timed out waiting for PMU firmware"
+		}
+	}
+}
+
+add_usage_text release_apu {apu}
+add_help_text release_apu "Release an APU from reset. It will start executing\
+	at RVBARADDR. You probably want resume_apu or start_apu instead."
+proc release_apu {apu} {
+	set axi $::_CHIPNAME.axi
+	set val [$axi read_memory $::CRF_APB_RST_FPD_APU 32 1]
+	set mask [expr {
+		(($::CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET | \
+		  $::CRF_APB_RST_FPD_APU_ACPU0_RESET) << $apu) | \
+		$::CRF_APB_RST_FPD_APU_L2_RESET
+	}]
+	$axi write_memory $::CRF_APB_RST_FPD_APU 32 [expr {$val & ~$mask}]
+
+	core_up $apu
+	$::_TARGETNAME.$apu aarch64 dbginit
+}
+
+proc _rvbaraddr {apu} {
+	return [expr {$::APU_RVBARADDR_BASE + 8 * $apu}]
+}
+
+add_usage_text resume_apu {apu addr}
+add_help_text resume_apu "Resume an APU at a given address."
+proc resume_apu {apu addr} {
+	set addrl [expr {$addr & 0xffffffff}]
+	set addrh [expr {$addr >> 32}]
+	$::_CHIPNAME.axi write_memory [_rvbaraddr $apu] 32 [list $addrl $addrh]
+
+	release_apu $apu
+}
+
+add_usage_text start_apu {apu}
+add_help_text start_apu "Start an APU and put it into an infinite loop at\
+	RVBARADDR. This can be convenient if you just want to halt the APU\
+	(since it won't execute anything unusual)."
+proc start_apu {apu} {
+	set axi $::_CHIPNAME.axi
+	foreach {addrl addrh} [$axi read_memory [_rvbaraddr $apu] 32 2] {
+		set addr [expr {($addrh << 32) | $addrl}]
+	}
+	# write the infinite loop instruction
+	$axi write_memory $addr 32 0x14000000
+
+	release_apu $apu
+}
+
+add_usage_text boot_pmu {image}
+add_help_text boot_pmu "Boot the PMU with a given firmware image, loading it\
+	to the beginning of PMU RAM. The PMU ROM will jump to this location\
+	after we resume it."
+proc boot_pmu {image} {
+	halt_pmu
+	echo "Info : Loading PMU firmware $image to $::PMU_RAM_BASE"
+	load_image $image $::PMU_RAM_BASE
+	resume_pmu
+}
+
+add_usage_text boot_apu "image \[apu=0 \[addr=$OCM_RAM_BASE\]\]"
+add_help_text boot_apu "Boot an APU with a given firmware image. The default\
+	address is the beginning of OCM RAM. Upon success, the default target\
+	will be changed to the (running) apu."
+proc boot_apu [list image {apu 0} [list addr $OCM_RAM_BASE]] {
+	start_apu $apu
+	targets $::_TARGETNAME.$apu
+	halt
+
+	echo "Info : Loading APU$apu firmware $image to $addr"
+	load_image $image $addr
+	resume $addr
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xmc1xxx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xmc1xxx.cfg
new file mode 100644
index 0000000..cafd032
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xmc1xxx.cfg
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC1100/XMC1200/XMC1300 family (ARM Cortex-M0 @ 32 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xmc1000
+}
+
+#
+# Only SWD and SPD supported
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CPUTAPID] } {
+	set _CPU_SWD_TAPID $CPUTAPID
+} else {
+	set _CPU_SWD_TAPID 0x0BB11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+$_TARGETNAME configure -work-area-phys 0x20000000 \
+                       -work-area-size $_WORKAREASIZE \
+                       -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xmc4xxx.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xmc4xxx.cfg
new file mode 100644
index 0000000..0e28494
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xmc4xxx.cfg
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4100/XMC4200/XMC4400/XMC4500 family (ARM Cortex-M4 @ 80-120 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xmc4000
+}
+
+source [find target/swj-dp.tcl]
+
+#
+# SWJ-DP
+#
+if { [info exists CPU_JTAG_TAPID] } {
+	set _CPU_JTAG_TAPID $CPU_JTAG_TAPID
+} else {
+	set _CPU_JTAG_TAPID 0x4BA00477
+}
+
+#
+# SW_DP
+#
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x2BA01477
+}
+
+if { [using_jtag] } {
+	set _CPU_TAPID $_CPU_JTAG_TAPID
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16 kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME xmc4xxx 0x0C000000 0 0 0 $_TARGETNAME
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xmos_xs1-xau8a-10_arm.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xmos_xs1-xau8a-10_arm.cfg
new file mode 100644
index 0000000..60fe9ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xmos_xs1-xau8a-10_arm.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# XMOS xCORE-XA XS1-XAU8A-10: ARM Cortex-M3 @ 48 MHz
+#
+# http://www.xmos.com/products/silicon/xcore-xa/xa-series
+#
+
+if { ![info exists CHIPNAME] } {
+	set CHIPNAME xcorexa
+}
+
+if { ![info exists WORKAREASIZE] } {
+	# XS1-XAU8A-10-FB265: 128 KB SRAM
+	set WORKAREASIZE 0x20000
+}
+
+source [find target/efm32.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-esp32.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-esp32.cfg
new file mode 100644
index 0000000..9a70072
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-esp32.cfg
@@ -0,0 +1,224 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa ESP32 target
+
+#  Core definition and ABI
+xtensa xtdef	LX
+xtensa xtopt	arnum				64
+xtensa xtopt	windowed			1
+
+#  Exception/Interrupt Options
+xtensa xtopt	exceptions			1
+xtensa xtopt	hipriints			1
+xtensa xtopt	intlevels			6
+xtensa xtopt	excmlevel			3
+
+#  Cache Options
+xtensa xtmem	icache				4 0 1
+xtensa xtmem	dcache				4 0 1 0
+
+#  Memory Options
+xtensa xtmem	irom				0x400D0000	0x330000
+xtensa xtmem	irom				0x40000000	0x64F00
+xtensa xtmem	iram				0x40070000	0x30000
+xtensa xtmem	iram				0x400C0000	0x2000
+xtensa xtmem	drom				0x3F400000	0x800000
+xtensa xtmem	drom				0x3FF90000	0x10000
+xtensa xtmem	dram				0x3FFAE000	0x52000
+xtensa xtmem	dram				0x3FF80000	0x2000
+xtensa xtmem	dram				0x3F800000	0x400000
+xtensa xtmem	dram				0x50000000	0x2000
+xtensa xtmem	dram				0x3FF00000	0x71000
+xtensa xtmem	dram				0x60000000	0x20000000
+
+#  Memory Protection/Translation Options
+
+#  Debug Options
+xtensa xtopt	debuglevel			6
+xtensa xtopt	ibreaknum			2
+xtensa xtopt	dbreaknum			2
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			1
+xtensa xtopt	perfcount			2
+
+#  Core Registers
+#  xtregfmt:	Optionally specify "contiguous" vs. "sparse" GDB register map.
+#				Default setting is "sparse" and is used with xt-gdb.
+#				If contiguous, optional parameter specifies number of registers
+#				in "Read General Registers" (g-packet) requests.
+#				NOTE: For contiguous format, registers listed in GDB order.
+#  xtregs:		Total number of Xtensa registers in the system
+xtensa xtregs	173
+xtensa xtregfmt	contiguous			105
+xtensa xtreg	pc					0x0020
+xtensa xtreg	ar0					0x0100
+xtensa xtreg	ar1					0x0101
+xtensa xtreg	ar2					0x0102
+xtensa xtreg	ar3					0x0103
+xtensa xtreg	ar4					0x0104
+xtensa xtreg	ar5					0x0105
+xtensa xtreg	ar6					0x0106
+xtensa xtreg	ar7					0x0107
+xtensa xtreg	ar8					0x0108
+xtensa xtreg	ar9					0x0109
+xtensa xtreg	ar10				0x010a
+xtensa xtreg	ar11				0x010b
+xtensa xtreg	ar12				0x010c
+xtensa xtreg	ar13				0x010d
+xtensa xtreg	ar14				0x010e
+xtensa xtreg	ar15				0x010f
+xtensa xtreg	ar16				0x0110
+xtensa xtreg	ar17				0x0111
+xtensa xtreg	ar18				0x0112
+xtensa xtreg	ar19				0x0113
+xtensa xtreg	ar20				0x0114
+xtensa xtreg	ar21				0x0115
+xtensa xtreg	ar22				0x0116
+xtensa xtreg	ar23				0x0117
+xtensa xtreg	ar24				0x0118
+xtensa xtreg	ar25				0x0119
+xtensa xtreg	ar26				0x011a
+xtensa xtreg	ar27				0x011b
+xtensa xtreg	ar28				0x011c
+xtensa xtreg	ar29				0x011d
+xtensa xtreg	ar30				0x011e
+xtensa xtreg	ar31				0x011f
+xtensa xtreg	ar32				0x0120
+xtensa xtreg	ar33				0x0121
+xtensa xtreg	ar34				0x0122
+xtensa xtreg	ar35				0x0123
+xtensa xtreg	ar36				0x0124
+xtensa xtreg	ar37				0x0125
+xtensa xtreg	ar38				0x0126
+xtensa xtreg	ar39				0x0127
+xtensa xtreg	ar40				0x0128
+xtensa xtreg	ar41				0x0129
+xtensa xtreg	ar42				0x012a
+xtensa xtreg	ar43				0x012b
+xtensa xtreg	ar44				0x012c
+xtensa xtreg	ar45				0x012d
+xtensa xtreg	ar46				0x012e
+xtensa xtreg	ar47				0x012f
+xtensa xtreg	ar48				0x0130
+xtensa xtreg	ar49				0x0131
+xtensa xtreg	ar50				0x0132
+xtensa xtreg	ar51				0x0133
+xtensa xtreg	ar52				0x0134
+xtensa xtreg	ar53				0x0135
+xtensa xtreg	ar54				0x0136
+xtensa xtreg	ar55				0x0137
+xtensa xtreg	ar56				0x0138
+xtensa xtreg	ar57				0x0139
+xtensa xtreg	ar58				0x013a
+xtensa xtreg	ar59				0x013b
+xtensa xtreg	ar60				0x013c
+xtensa xtreg	ar61				0x013d
+xtensa xtreg	ar62				0x013e
+xtensa xtreg	ar63				0x013f
+xtensa xtreg	lbeg				0x0200
+xtensa xtreg	lend				0x0201
+xtensa xtreg	lcount				0x0202
+xtensa xtreg	sar					0x0203
+xtensa xtreg	windowbase			0x0248
+xtensa xtreg	windowstart			0x0249
+xtensa xtreg	configid0			0x02b0
+xtensa xtreg	configid1			0x02d0
+xtensa xtreg	ps					0x02e6
+xtensa xtreg	threadptr			0x03e7
+xtensa xtreg	br					0x0204
+xtensa xtreg	scompare1			0x020c
+xtensa xtreg	acclo				0x0210
+xtensa xtreg	acchi				0x0211
+xtensa xtreg	m0					0x0220
+xtensa xtreg	m1					0x0221
+xtensa xtreg	m2					0x0222
+xtensa xtreg	m3					0x0223
+xtensa xtreg	expstate			0x03e6
+xtensa xtreg	f64r_lo				0x03ea
+xtensa xtreg	f64r_hi				0x03eb
+xtensa xtreg	f64s				0x03ec
+xtensa xtreg	f0					0x0030
+xtensa xtreg	f1					0x0031
+xtensa xtreg	f2					0x0032
+xtensa xtreg	f3					0x0033
+xtensa xtreg	f4					0x0034
+xtensa xtreg	f5					0x0035
+xtensa xtreg	f6					0x0036
+xtensa xtreg	f7					0x0037
+xtensa xtreg	f8					0x0038
+xtensa xtreg	f9					0x0039
+xtensa xtreg	f10					0x003a
+xtensa xtreg	f11					0x003b
+xtensa xtreg	f12					0x003c
+xtensa xtreg	f13					0x003d
+xtensa xtreg	f14					0x003e
+xtensa xtreg	f15					0x003f
+xtensa xtreg	fcr					0x03e8
+xtensa xtreg	fsr					0x03e9
+xtensa xtreg	mmid				0x0259
+xtensa xtreg	ibreakenable		0x0260
+xtensa xtreg	memctl				0x0261
+xtensa xtreg	atomctl				0x0263
+xtensa xtreg	ddr					0x0268
+xtensa xtreg	ibreaka0			0x0280
+xtensa xtreg	ibreaka1			0x0281
+xtensa xtreg	dbreaka0			0x0290
+xtensa xtreg	dbreaka1			0x0291
+xtensa xtreg	dbreakc0			0x02a0
+xtensa xtreg	dbreakc1			0x02a1
+xtensa xtreg	epc1				0x02b1
+xtensa xtreg	epc2				0x02b2
+xtensa xtreg	epc3				0x02b3
+xtensa xtreg	epc4				0x02b4
+xtensa xtreg	epc5				0x02b5
+xtensa xtreg	epc6				0x02b6
+xtensa xtreg	epc7				0x02b7
+xtensa xtreg	depc				0x02c0
+xtensa xtreg	eps2				0x02c2
+xtensa xtreg	eps3				0x02c3
+xtensa xtreg	eps4				0x02c4
+xtensa xtreg	eps5				0x02c5
+xtensa xtreg	eps6				0x02c6
+xtensa xtreg	eps7				0x02c7
+xtensa xtreg	excsave1			0x02d1
+xtensa xtreg	excsave2			0x02d2
+xtensa xtreg	excsave3			0x02d3
+xtensa xtreg	excsave4			0x02d4
+xtensa xtreg	excsave5			0x02d5
+xtensa xtreg	excsave6			0x02d6
+xtensa xtreg	excsave7			0x02d7
+xtensa xtreg	cpenable			0x02e0
+xtensa xtreg	interrupt			0x02e2
+xtensa xtreg	intset				0x02e2
+xtensa xtreg	intclear			0x02e3
+xtensa xtreg	intenable			0x02e4
+xtensa xtreg	vecbase				0x02e7
+xtensa xtreg	exccause			0x02e8
+xtensa xtreg	debugcause			0x02e9
+xtensa xtreg	ccount				0x02ea
+xtensa xtreg	prid				0x02eb
+xtensa xtreg	icount				0x02ec
+xtensa xtreg	icountlevel			0x02ed
+xtensa xtreg	excvaddr			0x02ee
+xtensa xtreg	ccompare0			0x02f0
+xtensa xtreg	ccompare1			0x02f1
+xtensa xtreg	ccompare2			0x02f2
+xtensa xtreg	misc0				0x02f4
+xtensa xtreg	misc1				0x02f5
+xtensa xtreg	misc2				0x02f6
+xtensa xtreg	misc3				0x02f7
+xtensa xtreg	a0					0x0000
+xtensa xtreg	a1					0x0001
+xtensa xtreg	a2					0x0002
+xtensa xtreg	a3					0x0003
+xtensa xtreg	a4					0x0004
+xtensa xtreg	a5					0x0005
+xtensa xtreg	a6					0x0006
+xtensa xtreg	a7					0x0007
+xtensa xtreg	a8					0x0008
+xtensa xtreg	a9					0x0009
+xtensa xtreg	a10					0x000a
+xtensa xtreg	a11					0x000b
+xtensa xtreg	a12					0x000c
+xtensa xtreg	a13					0x000d
+xtensa xtreg	a14					0x000e
+xtensa xtreg	a15					0x000f
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-esp32s2.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-esp32s2.cfg
new file mode 100644
index 0000000..b38cb1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-esp32s2.cfg
@@ -0,0 +1,223 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa ESP32S2 target
+
+#  Core definition and ABI
+xtensa xtdef	LX
+xtensa xtopt	arnum				64
+xtensa xtopt	windowed			1
+
+#  Exception/Interrupt Options
+xtensa xtopt	exceptions			1
+xtensa xtopt	hipriints			1
+xtensa xtopt	intlevels			6
+xtensa xtopt	excmlevel			3
+
+#  Cache Options
+xtensa xtmem	icache				4 0 1
+xtensa xtmem	dcache				4 0 1 0
+
+#  Memory Options
+xtensa xtmem	irom				0x40080000	0x780000
+xtensa xtmem	irom				0x40000000	0x20000
+xtensa xtmem	iram				0x40020000	0x50000
+xtensa xtmem	iram				0x40070000	0x2000
+xtensa xtmem	drom				0x3F000000	0x400000
+xtensa xtmem	drom				0x3F4D3FFC	0xAAC004
+xtensa xtmem	drom				0x3FFA0000	0x10000
+xtensa xtmem	dram				0x3FFB0000	0x50000
+xtensa xtmem	dram				0x3FF9E000	0x2000
+xtensa xtmem	dram				0x50000000	0x2000
+xtensa xtmem	dram				0x3F500000	0xA80000
+xtensa xtmem	dram				0x3F400000	0xD3FFC
+xtensa xtmem	dram				0x60000000	0x20000000
+
+#  Memory Protection/Translation Options
+
+#  Debug Options
+xtensa xtopt	debuglevel			6
+xtensa xtopt	ibreaknum			2
+xtensa xtopt	dbreaknum			2
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			0
+xtensa xtopt	perfcount			2
+
+#  Core Registers
+#  xtregfmt:	Optionally specify "contiguous" vs. "sparse" GDB register map.
+#				Default setting is "sparse" and is used with xt-gdb.
+#				If contiguous, optional parameter specifies number of registers
+#				in "Read General Registers" (g-packet) requests.
+#				NOTE: For contiguous format, registers listed in GDB order.
+#  xtregs:		Total number of Xtensa registers in the system
+xtensa xtregs	171
+xtensa xtregfmt	contiguous			73
+xtensa xtreg	pc					0x0020
+xtensa xtreg	ar0					0x0100
+xtensa xtreg	ar1					0x0101
+xtensa xtreg	ar2					0x0102
+xtensa xtreg	ar3					0x0103
+xtensa xtreg	ar4					0x0104
+xtensa xtreg	ar5					0x0105
+xtensa xtreg	ar6					0x0106
+xtensa xtreg	ar7					0x0107
+xtensa xtreg	ar8					0x0108
+xtensa xtreg	ar9					0x0109
+xtensa xtreg	ar10				0x010a
+xtensa xtreg	ar11				0x010b
+xtensa xtreg	ar12				0x010c
+xtensa xtreg	ar13				0x010d
+xtensa xtreg	ar14				0x010e
+xtensa xtreg	ar15				0x010f
+xtensa xtreg	ar16				0x0110
+xtensa xtreg	ar17				0x0111
+xtensa xtreg	ar18				0x0112
+xtensa xtreg	ar19				0x0113
+xtensa xtreg	ar20				0x0114
+xtensa xtreg	ar21				0x0115
+xtensa xtreg	ar22				0x0116
+xtensa xtreg	ar23				0x0117
+xtensa xtreg	ar24				0x0118
+xtensa xtreg	ar25				0x0119
+xtensa xtreg	ar26				0x011a
+xtensa xtreg	ar27				0x011b
+xtensa xtreg	ar28				0x011c
+xtensa xtreg	ar29				0x011d
+xtensa xtreg	ar30				0x011e
+xtensa xtreg	ar31				0x011f
+xtensa xtreg	ar32				0x0120
+xtensa xtreg	ar33				0x0121
+xtensa xtreg	ar34				0x0122
+xtensa xtreg	ar35				0x0123
+xtensa xtreg	ar36				0x0124
+xtensa xtreg	ar37				0x0125
+xtensa xtreg	ar38				0x0126
+xtensa xtreg	ar39				0x0127
+xtensa xtreg	ar40				0x0128
+xtensa xtreg	ar41				0x0129
+xtensa xtreg	ar42				0x012a
+xtensa xtreg	ar43				0x012b
+xtensa xtreg	ar44				0x012c
+xtensa xtreg	ar45				0x012d
+xtensa xtreg	ar46				0x012e
+xtensa xtreg	ar47				0x012f
+xtensa xtreg	ar48				0x0130
+xtensa xtreg	ar49				0x0131
+xtensa xtreg	ar50				0x0132
+xtensa xtreg	ar51				0x0133
+xtensa xtreg	ar52				0x0134
+xtensa xtreg	ar53				0x0135
+xtensa xtreg	ar54				0x0136
+xtensa xtreg	ar55				0x0137
+xtensa xtreg	ar56				0x0138
+xtensa xtreg	ar57				0x0139
+xtensa xtreg	ar58				0x013a
+xtensa xtreg	ar59				0x013b
+xtensa xtreg	ar60				0x013c
+xtensa xtreg	ar61				0x013d
+xtensa xtreg	ar62				0x013e
+xtensa xtreg	ar63				0x013f
+xtensa xtreg	sar					0x0203
+xtensa xtreg	windowbase			0x0248
+xtensa xtreg	windowstart			0x0249
+xtensa xtreg	configid0			0x02b0
+xtensa xtreg	configid1			0x02d0
+xtensa xtreg	ps					0x02e6
+xtensa xtreg	threadptr			0x03e7
+xtensa xtreg	gpio_out			0x0300
+xtensa xtreg	mmid				0x0259
+xtensa xtreg	ibreakenable		0x0260
+xtensa xtreg	ddr					0x0268
+xtensa xtreg	ibreaka0			0x0280
+xtensa xtreg	ibreaka1			0x0281
+xtensa xtreg	dbreaka0			0x0290
+xtensa xtreg	dbreaka1			0x0291
+xtensa xtreg	dbreakc0			0x02a0
+xtensa xtreg	dbreakc1			0x02a1
+xtensa xtreg	epc1				0x02b1
+xtensa xtreg	epc2				0x02b2
+xtensa xtreg	epc3				0x02b3
+xtensa xtreg	epc4				0x02b4
+xtensa xtreg	epc5				0x02b5
+xtensa xtreg	epc6				0x02b6
+xtensa xtreg	epc7				0x02b7
+xtensa xtreg	depc				0x02c0
+xtensa xtreg	eps2				0x02c2
+xtensa xtreg	eps3				0x02c3
+xtensa xtreg	eps4				0x02c4
+xtensa xtreg	eps5				0x02c5
+xtensa xtreg	eps6				0x02c6
+xtensa xtreg	eps7				0x02c7
+xtensa xtreg	excsave1			0x02d1
+xtensa xtreg	excsave2			0x02d2
+xtensa xtreg	excsave3			0x02d3
+xtensa xtreg	excsave4			0x02d4
+xtensa xtreg	excsave5			0x02d5
+xtensa xtreg	excsave6			0x02d6
+xtensa xtreg	excsave7			0x02d7
+xtensa xtreg	cpenable			0x02e0
+xtensa xtreg	interrupt			0x02e2
+xtensa xtreg	intset				0x02e2
+xtensa xtreg	intclear			0x02e3
+xtensa xtreg	intenable			0x02e4
+xtensa xtreg	vecbase				0x02e7
+xtensa xtreg	exccause			0x02e8
+xtensa xtreg	debugcause			0x02e9
+xtensa xtreg	ccount				0x02ea
+xtensa xtreg	prid				0x02eb
+xtensa xtreg	icount				0x02ec
+xtensa xtreg	icountlevel			0x02ed
+xtensa xtreg	excvaddr			0x02ee
+xtensa xtreg	ccompare0			0x02f0
+xtensa xtreg	ccompare1			0x02f1
+xtensa xtreg	ccompare2			0x02f2
+xtensa xtreg	misc0				0x02f4
+xtensa xtreg	misc1				0x02f5
+xtensa xtreg	misc2				0x02f6
+xtensa xtreg	misc3				0x02f7
+xtensa xtreg	pwrctl				0x2014
+xtensa xtreg	pwrstat				0x2015
+xtensa xtreg	eristat				0x2016
+xtensa xtreg	cs_itctrl			0x2017
+xtensa xtreg	cs_claimset			0x2018
+xtensa xtreg	cs_claimclr			0x2019
+xtensa xtreg	cs_lockaccess		0x201a
+xtensa xtreg	cs_lockstatus		0x201b
+xtensa xtreg	cs_authstatus		0x201c
+xtensa xtreg	fault_info			0x202b
+xtensa xtreg	trax_id				0x202c
+xtensa xtreg	trax_control		0x202d
+xtensa xtreg	trax_status			0x202e
+xtensa xtreg	trax_data			0x202f
+xtensa xtreg	trax_address		0x2030
+xtensa xtreg	trax_pctrigger		0x2031
+xtensa xtreg	trax_pcmatch		0x2032
+xtensa xtreg	trax_delay			0x2033
+xtensa xtreg	trax_memstart		0x2034
+xtensa xtreg	trax_memend			0x2035
+xtensa xtreg	pmg					0x2043
+xtensa xtreg	pmpc				0x2044
+xtensa xtreg	pm0					0x2045
+xtensa xtreg	pm1					0x2046
+xtensa xtreg	pmctrl0				0x2047
+xtensa xtreg	pmctrl1				0x2048
+xtensa xtreg	pmstat0				0x2049
+xtensa xtreg	pmstat1				0x204a
+xtensa xtreg	ocdid				0x204b
+xtensa xtreg	ocd_dcrclr			0x204c
+xtensa xtreg	ocd_dcrset			0x204d
+xtensa xtreg	ocd_dsr				0x204e
+xtensa xtreg	a0					0x0000
+xtensa xtreg	a1					0x0001
+xtensa xtreg	a2					0x0002
+xtensa xtreg	a3					0x0003
+xtensa xtreg	a4					0x0004
+xtensa xtreg	a5					0x0005
+xtensa xtreg	a6					0x0006
+xtensa xtreg	a7					0x0007
+xtensa xtreg	a8					0x0008
+xtensa xtreg	a9					0x0009
+xtensa xtreg	a10					0x000a
+xtensa xtreg	a11					0x000b
+xtensa xtreg	a12					0x000c
+xtensa xtreg	a13					0x000d
+xtensa xtreg	a14					0x000e
+xtensa xtreg	a15					0x000f
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-esp32s3.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-esp32s3.cfg
new file mode 100644
index 0000000..b3f20e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-esp32s3.cfg
@@ -0,0 +1,276 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa ESP32S3 target
+
+#  Core definition and ABI
+xtensa xtdef	LX
+xtensa xtopt	arnum				64
+xtensa xtopt	windowed			1
+
+#  Exception/Interrupt Options
+xtensa xtopt	exceptions			1
+xtensa xtopt	hipriints			1
+xtensa xtopt	intlevels			6
+xtensa xtopt	excmlevel			3
+
+#  Cache Options
+
+#  Memory Options
+xtensa xtmem	irom				0x42000000	0x2000000
+xtensa xtmem	irom				0x40000000	0x60000
+xtensa xtmem	iram				0x40370000	0x70000
+xtensa xtmem	iram				0x600FE000	0x2000
+xtensa xtmem	drom				0x3C000000	0x1000000
+xtensa xtmem	drom				0x3FF00000	0x20000
+xtensa xtmem	dram				0x3FC88000	0x78000
+xtensa xtmem	dram				0x600FE000	0x2000
+xtensa xtmem	dram				0x50000000	0x2000
+xtensa xtmem	dram				0x60000000	0x10000000
+
+#  Memory Protection/Translation Options
+
+#  Debug Options
+xtensa xtopt	debuglevel			6
+xtensa xtopt	ibreaknum			2
+xtensa xtopt	dbreaknum			2
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			0
+xtensa xtopt	perfcount			2
+
+
+#  Core Registers
+#  xtregfmt:	Optionally specify "contiguous" vs. "sparse" GDB register map.
+#				Default setting is "sparse" and is used with xt-gdb.
+#				If contiguous, optional parameter specifies number of registers
+#				in "Read General Registers" (g-packet) requests.
+#				NOTE: For contiguous format, registers listed in GDB order.
+#  xtregs:		Total number of Xtensa registers in the system
+xtensa xtregs	228
+xtensa xtregfmt	contiguous			128
+xtensa xtreg	pc					0x0020
+xtensa xtreg	ar0					0x0100
+xtensa xtreg	ar1					0x0101
+xtensa xtreg	ar2					0x0102
+xtensa xtreg	ar3					0x0103
+xtensa xtreg	ar4					0x0104
+xtensa xtreg	ar5					0x0105
+xtensa xtreg	ar6					0x0106
+xtensa xtreg	ar7					0x0107
+xtensa xtreg	ar8					0x0108
+xtensa xtreg	ar9					0x0109
+xtensa xtreg	ar10				0x010a
+xtensa xtreg	ar11				0x010b
+xtensa xtreg	ar12				0x010c
+xtensa xtreg	ar13				0x010d
+xtensa xtreg	ar14				0x010e
+xtensa xtreg	ar15				0x010f
+xtensa xtreg	ar16				0x0110
+xtensa xtreg	ar17				0x0111
+xtensa xtreg	ar18				0x0112
+xtensa xtreg	ar19				0x0113
+xtensa xtreg	ar20				0x0114
+xtensa xtreg	ar21				0x0115
+xtensa xtreg	ar22				0x0116
+xtensa xtreg	ar23				0x0117
+xtensa xtreg	ar24				0x0118
+xtensa xtreg	ar25				0x0119
+xtensa xtreg	ar26				0x011a
+xtensa xtreg	ar27				0x011b
+xtensa xtreg	ar28				0x011c
+xtensa xtreg	ar29				0x011d
+xtensa xtreg	ar30				0x011e
+xtensa xtreg	ar31				0x011f
+xtensa xtreg	ar32				0x0120
+xtensa xtreg	ar33				0x0121
+xtensa xtreg	ar34				0x0122
+xtensa xtreg	ar35				0x0123
+xtensa xtreg	ar36				0x0124
+xtensa xtreg	ar37				0x0125
+xtensa xtreg	ar38				0x0126
+xtensa xtreg	ar39				0x0127
+xtensa xtreg	ar40				0x0128
+xtensa xtreg	ar41				0x0129
+xtensa xtreg	ar42				0x012a
+xtensa xtreg	ar43				0x012b
+xtensa xtreg	ar44				0x012c
+xtensa xtreg	ar45				0x012d
+xtensa xtreg	ar46				0x012e
+xtensa xtreg	ar47				0x012f
+xtensa xtreg	ar48				0x0130
+xtensa xtreg	ar49				0x0131
+xtensa xtreg	ar50				0x0132
+xtensa xtreg	ar51				0x0133
+xtensa xtreg	ar52				0x0134
+xtensa xtreg	ar53				0x0135
+xtensa xtreg	ar54				0x0136
+xtensa xtreg	ar55				0x0137
+xtensa xtreg	ar56				0x0138
+xtensa xtreg	ar57				0x0139
+xtensa xtreg	ar58				0x013a
+xtensa xtreg	ar59				0x013b
+xtensa xtreg	ar60				0x013c
+xtensa xtreg	ar61				0x013d
+xtensa xtreg	ar62				0x013e
+xtensa xtreg	ar63				0x013f
+xtensa xtreg	lbeg				0x0200
+xtensa xtreg	lend				0x0201
+xtensa xtreg	lcount				0x0202
+xtensa xtreg	sar					0x0203
+xtensa xtreg	windowbase			0x0248
+xtensa xtreg	windowstart			0x0249
+xtensa xtreg	configid0			0x02b0
+xtensa xtreg	configid1			0x02d0
+xtensa xtreg	ps					0x02e6
+xtensa xtreg	threadptr			0x03e7
+xtensa xtreg	br					0x0204
+xtensa xtreg	scompare1			0x020c
+xtensa xtreg	acclo				0x0210
+xtensa xtreg	acchi				0x0211
+xtensa xtreg	m0					0x0220
+xtensa xtreg	m1					0x0221
+xtensa xtreg	m2					0x0222
+xtensa xtreg	m3					0x0223
+xtensa xtreg	gpio_out			0x030c
+xtensa xtreg	f0					0x0030
+xtensa xtreg	f1					0x0031
+xtensa xtreg	f2					0x0032
+xtensa xtreg	f3					0x0033
+xtensa xtreg	f4					0x0034
+xtensa xtreg	f5					0x0035
+xtensa xtreg	f6					0x0036
+xtensa xtreg	f7					0x0037
+xtensa xtreg	f8					0x0038
+xtensa xtreg	f9					0x0039
+xtensa xtreg	f10					0x003a
+xtensa xtreg	f11					0x003b
+xtensa xtreg	f12					0x003c
+xtensa xtreg	f13					0x003d
+xtensa xtreg	f14					0x003e
+xtensa xtreg	f15					0x003f
+xtensa xtreg	fcr					0x03e8
+xtensa xtreg	fsr					0x03e9
+xtensa xtreg	accx_0				0x0300
+xtensa xtreg	accx_1				0x0301
+xtensa xtreg	qacc_h_0			0x0302
+xtensa xtreg	qacc_h_1			0x0303
+xtensa xtreg	qacc_h_2			0x0304
+xtensa xtreg	qacc_h_3			0x0305
+xtensa xtreg	qacc_h_4			0x0306
+xtensa xtreg	qacc_l_0			0x0307
+xtensa xtreg	qacc_l_1			0x0308
+xtensa xtreg	qacc_l_2			0x0309
+xtensa xtreg	qacc_l_3			0x030a
+xtensa xtreg	qacc_l_4			0x030b
+xtensa xtreg	sar_byte			0x030d
+xtensa xtreg	fft_bit_width		0x030e
+xtensa xtreg	ua_state_0			0x030f
+xtensa xtreg	ua_state_1			0x0310
+xtensa xtreg	ua_state_2			0x0311
+xtensa xtreg	ua_state_3			0x0312
+xtensa xtreg	q0					0x1008
+xtensa xtreg	q1					0x1009
+xtensa xtreg	q2					0x100a
+xtensa xtreg	q3					0x100b
+xtensa xtreg	q4					0x100c
+xtensa xtreg	q5					0x100d
+xtensa xtreg	q6					0x100e
+xtensa xtreg	q7					0x100f
+xtensa xtreg	mmid				0x0259
+xtensa xtreg	ibreakenable		0x0260
+xtensa xtreg	memctl				0x0261
+xtensa xtreg	atomctl				0x0263
+xtensa xtreg	ddr					0x0268
+xtensa xtreg	ibreaka0			0x0280
+xtensa xtreg	ibreaka1			0x0281
+xtensa xtreg	dbreaka0			0x0290
+xtensa xtreg	dbreaka1			0x0291
+xtensa xtreg	dbreakc0			0x02a0
+xtensa xtreg	dbreakc1			0x02a1
+xtensa xtreg	epc1				0x02b1
+xtensa xtreg	epc2				0x02b2
+xtensa xtreg	epc3				0x02b3
+xtensa xtreg	epc4				0x02b4
+xtensa xtreg	epc5				0x02b5
+xtensa xtreg	epc6				0x02b6
+xtensa xtreg	epc7				0x02b7
+xtensa xtreg	depc				0x02c0
+xtensa xtreg	eps2				0x02c2
+xtensa xtreg	eps3				0x02c3
+xtensa xtreg	eps4				0x02c4
+xtensa xtreg	eps5				0x02c5
+xtensa xtreg	eps6				0x02c6
+xtensa xtreg	eps7				0x02c7
+xtensa xtreg	excsave1			0x02d1
+xtensa xtreg	excsave2			0x02d2
+xtensa xtreg	excsave3			0x02d3
+xtensa xtreg	excsave4			0x02d4
+xtensa xtreg	excsave5			0x02d5
+xtensa xtreg	excsave6			0x02d6
+xtensa xtreg	excsave7			0x02d7
+xtensa xtreg	cpenable			0x02e0
+xtensa xtreg	interrupt			0x02e2
+xtensa xtreg	intset				0x02e2
+xtensa xtreg	intclear			0x02e3
+xtensa xtreg	intenable			0x02e4
+xtensa xtreg	vecbase				0x02e7
+xtensa xtreg	exccause			0x02e8
+xtensa xtreg	debugcause			0x02e9
+xtensa xtreg	ccount				0x02ea
+xtensa xtreg	prid				0x02eb
+xtensa xtreg	icount				0x02ec
+xtensa xtreg	icountlevel			0x02ed
+xtensa xtreg	excvaddr			0x02ee
+xtensa xtreg	ccompare0			0x02f0
+xtensa xtreg	ccompare1			0x02f1
+xtensa xtreg	ccompare2			0x02f2
+xtensa xtreg	misc0				0x02f4
+xtensa xtreg	misc1				0x02f5
+xtensa xtreg	misc2				0x02f6
+xtensa xtreg	misc3				0x02f7
+xtensa xtreg	pwrctl				0x2028
+xtensa xtreg	pwrstat				0x2029
+xtensa xtreg	eristat				0x202a
+xtensa xtreg	cs_itctrl			0x202b
+xtensa xtreg	cs_claimset			0x202c
+xtensa xtreg	cs_claimclr			0x202d
+xtensa xtreg	cs_lockaccess		0x202e
+xtensa xtreg	cs_lockstatus		0x202f
+xtensa xtreg	cs_authstatus		0x2030
+xtensa xtreg	fault_info			0x203f
+xtensa xtreg	trax_id				0x2040
+xtensa xtreg	trax_control		0x2041
+xtensa xtreg	trax_status			0x2042
+xtensa xtreg	trax_data			0x2043
+xtensa xtreg	trax_address		0x2044
+xtensa xtreg	trax_pctrigger		0x2045
+xtensa xtreg	trax_pcmatch		0x2046
+xtensa xtreg	trax_delay			0x2047
+xtensa xtreg	trax_memstart		0x2048
+xtensa xtreg	trax_memend			0x2049
+xtensa xtreg	pmg					0x2057
+xtensa xtreg	pmpc				0x2058
+xtensa xtreg	pm0					0x2059
+xtensa xtreg	pm1					0x205a
+xtensa xtreg	pmctrl0				0x205b
+xtensa xtreg	pmctrl1				0x205c
+xtensa xtreg	pmstat0				0x205d
+xtensa xtreg	pmstat1				0x205e
+xtensa xtreg	ocdid				0x205f
+xtensa xtreg	ocd_dcrclr			0x2060
+xtensa xtreg	ocd_dcrset			0x2061
+xtensa xtreg	ocd_dsr				0x2062
+xtensa xtreg	a0					0x0000
+xtensa xtreg	a1					0x0001
+xtensa xtreg	a2					0x0002
+xtensa xtreg	a3					0x0003
+xtensa xtreg	a4					0x0004
+xtensa xtreg	a5					0x0005
+xtensa xtreg	a6					0x0006
+xtensa xtreg	a7					0x0007
+xtensa xtreg	a8					0x0008
+xtensa xtreg	a9					0x0009
+xtensa xtreg	a10					0x000a
+xtensa xtreg	a11					0x000b
+xtensa xtreg	a12					0x000c
+xtensa xtreg	a13					0x000d
+xtensa xtreg	a14					0x000e
+xtensa xtreg	a15					0x000f
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-nxp_rt600.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-nxp_rt600.cfg
new file mode 100644
index 0000000..ca7fd68
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-nxp_rt600.cfg
@@ -0,0 +1,255 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa HiFi DSP in NXP RT600 target
+
+
+#  Core instance default definition
+if { [info exists XTNAME] } {
+    set _XTNAME $XTNAME
+} else {
+    set _XTNAME xtensa.cpu
+}
+
+
+#  Core definition and ABI
+$_XTNAME xtensa xtdef	LX
+$_XTNAME xtensa xtopt	arnum           	32
+$_XTNAME xtensa xtopt	windowed        	1
+
+
+#  Exception/Interrupt Options
+$_XTNAME xtensa xtopt	exceptions      	1
+$_XTNAME xtensa xtopt	hipriints       	1
+$_XTNAME xtensa xtopt	intlevels       	4
+$_XTNAME xtensa xtopt	excmlevel       	2
+
+
+#  Cache Options
+$_XTNAME xtensa xtmem	icache          	256	32768	4
+$_XTNAME xtensa xtmem	dcache          	256	65536	4	1
+
+
+#  Memory Options
+$_XTNAME xtensa xtmem	iram            	0x24020000	65536
+$_XTNAME xtensa xtmem	dram            	0x24000000	65536
+$_XTNAME xtensa xtmem	sram            	0x00000000	603979776
+
+
+#  Memory Protection/Translation Options
+
+
+#  Debug Options
+$_XTNAME xtensa xtopt	debuglevel      	4
+$_XTNAME xtensa xtopt	ibreaknum       	2
+$_XTNAME xtensa xtopt	dbreaknum       	2
+
+
+#  Core Registers
+$_XTNAME xtensa xtregs	208
+$_XTNAME xtensa xtreg	pc              	0x0020
+$_XTNAME xtensa xtreg	ar0             	0x0100
+$_XTNAME xtensa xtreg	ar1             	0x0101
+$_XTNAME xtensa xtreg	ar2             	0x0102
+$_XTNAME xtensa xtreg	ar3             	0x0103
+$_XTNAME xtensa xtreg	ar4             	0x0104
+$_XTNAME xtensa xtreg	ar5             	0x0105
+$_XTNAME xtensa xtreg	ar6             	0x0106
+$_XTNAME xtensa xtreg	ar7             	0x0107
+$_XTNAME xtensa xtreg	ar8             	0x0108
+$_XTNAME xtensa xtreg	ar9             	0x0109
+$_XTNAME xtensa xtreg	ar10            	0x010a
+$_XTNAME xtensa xtreg	ar11            	0x010b
+$_XTNAME xtensa xtreg	ar12            	0x010c
+$_XTNAME xtensa xtreg	ar13            	0x010d
+$_XTNAME xtensa xtreg	ar14            	0x010e
+$_XTNAME xtensa xtreg	ar15            	0x010f
+$_XTNAME xtensa xtreg	ar16            	0x0110
+$_XTNAME xtensa xtreg	ar17            	0x0111
+$_XTNAME xtensa xtreg	ar18            	0x0112
+$_XTNAME xtensa xtreg	ar19            	0x0113
+$_XTNAME xtensa xtreg	ar20            	0x0114
+$_XTNAME xtensa xtreg	ar21            	0x0115
+$_XTNAME xtensa xtreg	ar22            	0x0116
+$_XTNAME xtensa xtreg	ar23            	0x0117
+$_XTNAME xtensa xtreg	ar24            	0x0118
+$_XTNAME xtensa xtreg	ar25            	0x0119
+$_XTNAME xtensa xtreg	ar26            	0x011a
+$_XTNAME xtensa xtreg	ar27            	0x011b
+$_XTNAME xtensa xtreg	ar28            	0x011c
+$_XTNAME xtensa xtreg	ar29            	0x011d
+$_XTNAME xtensa xtreg	ar30            	0x011e
+$_XTNAME xtensa xtreg	ar31            	0x011f
+$_XTNAME xtensa xtreg	lbeg            	0x0200
+$_XTNAME xtensa xtreg	lend            	0x0201
+$_XTNAME xtensa xtreg	lcount          	0x0202
+$_XTNAME xtensa xtreg	sar             	0x0203
+$_XTNAME xtensa xtreg	prefctl         	0x0228
+$_XTNAME xtensa xtreg	windowbase      	0x0248
+$_XTNAME xtensa xtreg	windowstart     	0x0249
+$_XTNAME xtensa xtreg	configid0       	0x02b0
+$_XTNAME xtensa xtreg	configid1       	0x02d0
+$_XTNAME xtensa xtreg	ps              	0x02e6
+$_XTNAME xtensa xtreg	threadptr       	0x03e7
+$_XTNAME xtensa xtreg	br              	0x0204
+$_XTNAME xtensa xtreg	scompare1       	0x020c
+$_XTNAME xtensa xtreg	acclo           	0x0210
+$_XTNAME xtensa xtreg	acchi           	0x0211
+$_XTNAME xtensa xtreg	m0              	0x0220
+$_XTNAME xtensa xtreg	m1              	0x0221
+$_XTNAME xtensa xtreg	m2              	0x0222
+$_XTNAME xtensa xtreg	m3              	0x0223
+$_XTNAME xtensa xtreg	expstate        	0x03e6
+$_XTNAME xtensa xtreg	f64r_lo         	0x03ea
+$_XTNAME xtensa xtreg	f64r_hi         	0x03eb
+$_XTNAME xtensa xtreg	f64s            	0x03ec
+$_XTNAME xtensa xtreg	ae_ovf_sar      	0x03f0
+$_XTNAME xtensa xtreg	ae_bithead      	0x03f1
+$_XTNAME xtensa xtreg	ae_ts_fts_bu_bp 	0x03f2
+$_XTNAME xtensa xtreg	ae_cw_sd_no     	0x03f3
+$_XTNAME xtensa xtreg	ae_cbegin0      	0x03f6
+$_XTNAME xtensa xtreg	ae_cend0        	0x03f7
+$_XTNAME xtensa xtreg	ae_cbegin1      	0x03f8
+$_XTNAME xtensa xtreg	ae_cend1        	0x03f9
+$_XTNAME xtensa xtreg	aed0            	0x1010
+$_XTNAME xtensa xtreg	aed1            	0x1011
+$_XTNAME xtensa xtreg	aed2            	0x1012
+$_XTNAME xtensa xtreg	aed3            	0x1013
+$_XTNAME xtensa xtreg	aed4            	0x1014
+$_XTNAME xtensa xtreg	aed5            	0x1015
+$_XTNAME xtensa xtreg	aed6            	0x1016
+$_XTNAME xtensa xtreg	aed7            	0x1017
+$_XTNAME xtensa xtreg	aed8            	0x1018
+$_XTNAME xtensa xtreg	aed9            	0x1019
+$_XTNAME xtensa xtreg	aed10           	0x101a
+$_XTNAME xtensa xtreg	aed11           	0x101b
+$_XTNAME xtensa xtreg	aed12           	0x101c
+$_XTNAME xtensa xtreg	aed13           	0x101d
+$_XTNAME xtensa xtreg	aed14           	0x101e
+$_XTNAME xtensa xtreg	aed15           	0x101f
+$_XTNAME xtensa xtreg	u0              	0x1020
+$_XTNAME xtensa xtreg	u1              	0x1021
+$_XTNAME xtensa xtreg	u2              	0x1022
+$_XTNAME xtensa xtreg	u3              	0x1023
+$_XTNAME xtensa xtreg	aep0            	0x1024
+$_XTNAME xtensa xtreg	aep1            	0x1025
+$_XTNAME xtensa xtreg	aep2            	0x1026
+$_XTNAME xtensa xtreg	aep3            	0x1027
+$_XTNAME xtensa xtreg	fcr_fsr         	0x1029
+$_XTNAME xtensa xtreg	mmid            	0x0259
+$_XTNAME xtensa xtreg	ibreakenable    	0x0260
+$_XTNAME xtensa xtreg	memctl          	0x0261
+$_XTNAME xtensa xtreg	atomctl         	0x0263
+$_XTNAME xtensa xtreg	ddr             	0x0268
+$_XTNAME xtensa xtreg	ibreaka0        	0x0280
+$_XTNAME xtensa xtreg	ibreaka1        	0x0281
+$_XTNAME xtensa xtreg	dbreaka0        	0x0290
+$_XTNAME xtensa xtreg	dbreaka1        	0x0291
+$_XTNAME xtensa xtreg	dbreakc0        	0x02a0
+$_XTNAME xtensa xtreg	dbreakc1        	0x02a1
+$_XTNAME xtensa xtreg	epc1            	0x02b1
+$_XTNAME xtensa xtreg	epc2            	0x02b2
+$_XTNAME xtensa xtreg	epc3            	0x02b3
+$_XTNAME xtensa xtreg	epc4            	0x02b4
+$_XTNAME xtensa xtreg	epc5            	0x02b5
+$_XTNAME xtensa xtreg	depc            	0x02c0
+$_XTNAME xtensa xtreg	eps2            	0x02c2
+$_XTNAME xtensa xtreg	eps3            	0x02c3
+$_XTNAME xtensa xtreg	eps4            	0x02c4
+$_XTNAME xtensa xtreg	eps5            	0x02c5
+$_XTNAME xtensa xtreg	excsave1        	0x02d1
+$_XTNAME xtensa xtreg	excsave2        	0x02d2
+$_XTNAME xtensa xtreg	excsave3        	0x02d3
+$_XTNAME xtensa xtreg	excsave4        	0x02d4
+$_XTNAME xtensa xtreg	excsave5        	0x02d5
+$_XTNAME xtensa xtreg	cpenable        	0x02e0
+$_XTNAME xtensa xtreg	interrupt       	0x02e2
+$_XTNAME xtensa xtreg	intset          	0x02e2
+$_XTNAME xtensa xtreg	intclear        	0x02e3
+$_XTNAME xtensa xtreg	intenable       	0x02e4
+$_XTNAME xtensa xtreg	vecbase         	0x02e7
+$_XTNAME xtensa xtreg	exccause        	0x02e8
+$_XTNAME xtensa xtreg	debugcause      	0x02e9
+$_XTNAME xtensa xtreg	ccount          	0x02ea
+$_XTNAME xtensa xtreg	prid            	0x02eb
+$_XTNAME xtensa xtreg	icount          	0x02ec
+$_XTNAME xtensa xtreg	icountlevel     	0x02ed
+$_XTNAME xtensa xtreg	excvaddr        	0x02ee
+$_XTNAME xtensa xtreg	ccompare0       	0x02f0
+$_XTNAME xtensa xtreg	ccompare1       	0x02f1
+$_XTNAME xtensa xtreg	misc0           	0x02f4
+$_XTNAME xtensa xtreg	misc1           	0x02f5
+$_XTNAME xtensa xtreg	pwrctl          	0x2024
+$_XTNAME xtensa xtreg	pwrstat         	0x2025
+$_XTNAME xtensa xtreg	eristat         	0x2026
+$_XTNAME xtensa xtreg	cs_itctrl       	0x2027
+$_XTNAME xtensa xtreg	cs_claimset     	0x2028
+$_XTNAME xtensa xtreg	cs_claimclr     	0x2029
+$_XTNAME xtensa xtreg	cs_lockaccess   	0x202a
+$_XTNAME xtensa xtreg	cs_lockstatus   	0x202b
+$_XTNAME xtensa xtreg	cs_authstatus   	0x202c
+$_XTNAME xtensa xtreg	pmg             	0x203b
+$_XTNAME xtensa xtreg	pmpc            	0x203c
+$_XTNAME xtensa xtreg	pm0             	0x203d
+$_XTNAME xtensa xtreg	pm1             	0x203e
+$_XTNAME xtensa xtreg	pmctrl0         	0x203f
+$_XTNAME xtensa xtreg	pmctrl1         	0x2040
+$_XTNAME xtensa xtreg	pmstat0         	0x2041
+$_XTNAME xtensa xtreg	pmstat1         	0x2042
+$_XTNAME xtensa xtreg	ocdid           	0x2043
+$_XTNAME xtensa xtreg	ocd_dcrclr      	0x2044
+$_XTNAME xtensa xtreg	ocd_dcrset      	0x2045
+$_XTNAME xtensa xtreg	ocd_dsr         	0x2046
+$_XTNAME xtensa xtreg	a0              	0x0000
+$_XTNAME xtensa xtreg	a1              	0x0001
+$_XTNAME xtensa xtreg	a2              	0x0002
+$_XTNAME xtensa xtreg	a3              	0x0003
+$_XTNAME xtensa xtreg	a4              	0x0004
+$_XTNAME xtensa xtreg	a5              	0x0005
+$_XTNAME xtensa xtreg	a6              	0x0006
+$_XTNAME xtensa xtreg	a7              	0x0007
+$_XTNAME xtensa xtreg	a8              	0x0008
+$_XTNAME xtensa xtreg	a9              	0x0009
+$_XTNAME xtensa xtreg	a10             	0x000a
+$_XTNAME xtensa xtreg	a11             	0x000b
+$_XTNAME xtensa xtreg	a12             	0x000c
+$_XTNAME xtensa xtreg	a13             	0x000d
+$_XTNAME xtensa xtreg	a14             	0x000e
+$_XTNAME xtensa xtreg	a15             	0x000f
+$_XTNAME xtensa xtreg	b0              	0x0010
+$_XTNAME xtensa xtreg	b1              	0x0011
+$_XTNAME xtensa xtreg	b2              	0x0012
+$_XTNAME xtensa xtreg	b3              	0x0013
+$_XTNAME xtensa xtreg	b4              	0x0014
+$_XTNAME xtensa xtreg	b5              	0x0015
+$_XTNAME xtensa xtreg	b6              	0x0016
+$_XTNAME xtensa xtreg	b7              	0x0017
+$_XTNAME xtensa xtreg	b8              	0x0018
+$_XTNAME xtensa xtreg	b9              	0x0019
+$_XTNAME xtensa xtreg	b10             	0x001a
+$_XTNAME xtensa xtreg	b11             	0x001b
+$_XTNAME xtensa xtreg	b12             	0x001c
+$_XTNAME xtensa xtreg	b13             	0x001d
+$_XTNAME xtensa xtreg	b14             	0x001e
+$_XTNAME xtensa xtreg	b15             	0x001f
+$_XTNAME xtensa xtreg	psintlevel      	0x2006
+$_XTNAME xtensa xtreg	psum            	0x2007
+$_XTNAME xtensa xtreg	pswoe           	0x2008
+$_XTNAME xtensa xtreg	psexcm          	0x2009
+$_XTNAME xtensa xtreg	pscallinc       	0x200a
+$_XTNAME xtensa xtreg	psowb           	0x200b
+$_XTNAME xtensa xtreg	acc             	0x200c
+$_XTNAME xtensa xtreg	dbnum           	0x2011
+$_XTNAME xtensa xtreg	ae_overflow     	0x2014
+$_XTNAME xtensa xtreg	ae_sar          	0x2015
+$_XTNAME xtensa xtreg	ae_cwrap        	0x2016
+$_XTNAME xtensa xtreg	ae_bitptr       	0x2017
+$_XTNAME xtensa xtreg	ae_bitsused     	0x2018
+$_XTNAME xtensa xtreg	ae_tablesize    	0x2019
+$_XTNAME xtensa xtreg	ae_first_ts     	0x201a
+$_XTNAME xtensa xtreg	ae_nextoffset   	0x201b
+$_XTNAME xtensa xtreg	ae_searchdone   	0x201c
+$_XTNAME xtensa xtreg	roundmode       	0x201d
+$_XTNAME xtensa xtreg	invalidflag     	0x201e
+$_XTNAME xtensa xtreg	divzeroflag     	0x201f
+$_XTNAME xtensa xtreg	overflowflag    	0x2020
+$_XTNAME xtensa xtreg	underflowflag   	0x2021
+$_XTNAME xtensa xtreg	inexactflag     	0x2022
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-xt8.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-xt8.cfg
new file mode 100644
index 0000000..523dc74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa-core-xt8.cfg
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa xt8 target
+
+
+#  Core instance default definition
+if { [info exists XTNAME] } {
+    set _XTNAME $XTNAME
+} else {
+    set _XTNAME xtensa
+}
+
+
+#  Core definition and ABI
+$_XTNAME xtensa xtdef	LX
+$_XTNAME xtensa xtopt	arnum           	32
+$_XTNAME xtensa xtopt	windowed        	1
+
+
+#  Exception/Interrupt Options
+$_XTNAME xtensa xtopt	exceptions      	1
+$_XTNAME xtensa xtopt	hipriints       	1
+$_XTNAME xtensa xtopt	intlevels       	3
+$_XTNAME xtensa xtopt	excmlevel       	1
+
+
+#  Cache Options
+$_XTNAME xtensa xtmem	icache          	16	1024	1
+$_XTNAME xtensa xtmem	dcache          	16	1024	1	1
+
+
+#  Memory Options
+$_XTNAME xtensa xtmem	iram            	0x40000000	1048576
+$_XTNAME xtensa xtmem	dram            	0x3ff00000	262144
+$_XTNAME xtensa xtmem	srom            	0x50000000	131072
+$_XTNAME xtensa xtmem	sram            	0x60000000	4194304
+
+
+#  Memory Protection/Translation Options
+
+
+#  Debug Options
+$_XTNAME xtensa xtopt	debuglevel      	3
+$_XTNAME xtensa xtopt	ibreaknum       	2
+$_XTNAME xtensa xtopt	dbreaknum       	2
+
+
+#  Core Registers
+$_XTNAME xtensa xtregs	127
+$_XTNAME xtensa xtreg	a0              	0x0000
+$_XTNAME xtensa xtreg	a1              	0x0001
+$_XTNAME xtensa xtreg	a2              	0x0002
+$_XTNAME xtensa xtreg	a3              	0x0003
+$_XTNAME xtensa xtreg	a4              	0x0004
+$_XTNAME xtensa xtreg	a5              	0x0005
+$_XTNAME xtensa xtreg	a6              	0x0006
+$_XTNAME xtensa xtreg	a7              	0x0007
+$_XTNAME xtensa xtreg	a8              	0x0008
+$_XTNAME xtensa xtreg	a9              	0x0009
+$_XTNAME xtensa xtreg	a10             	0x000a
+$_XTNAME xtensa xtreg	a11             	0x000b
+$_XTNAME xtensa xtreg	a12             	0x000c
+$_XTNAME xtensa xtreg	a13             	0x000d
+$_XTNAME xtensa xtreg	a14             	0x000e
+$_XTNAME xtensa xtreg	a15             	0x000f
+$_XTNAME xtensa xtreg	pc              	0x0020
+$_XTNAME xtensa xtreg	ar0             	0x0100
+$_XTNAME xtensa xtreg	ar1             	0x0101
+$_XTNAME xtensa xtreg	ar2             	0x0102
+$_XTNAME xtensa xtreg	ar3             	0x0103
+$_XTNAME xtensa xtreg	ar4             	0x0104
+$_XTNAME xtensa xtreg	ar5             	0x0105
+$_XTNAME xtensa xtreg	ar6             	0x0106
+$_XTNAME xtensa xtreg	ar7             	0x0107
+$_XTNAME xtensa xtreg	ar8             	0x0108
+$_XTNAME xtensa xtreg	ar9             	0x0109
+$_XTNAME xtensa xtreg	ar10            	0x010a
+$_XTNAME xtensa xtreg	ar11            	0x010b
+$_XTNAME xtensa xtreg	ar12            	0x010c
+$_XTNAME xtensa xtreg	ar13            	0x010d
+$_XTNAME xtensa xtreg	ar14            	0x010e
+$_XTNAME xtensa xtreg	ar15            	0x010f
+$_XTNAME xtensa xtreg	ar16            	0x0110
+$_XTNAME xtensa xtreg	ar17            	0x0111
+$_XTNAME xtensa xtreg	ar18            	0x0112
+$_XTNAME xtensa xtreg	ar19            	0x0113
+$_XTNAME xtensa xtreg	ar20            	0x0114
+$_XTNAME xtensa xtreg	ar21            	0x0115
+$_XTNAME xtensa xtreg	ar22            	0x0116
+$_XTNAME xtensa xtreg	ar23            	0x0117
+$_XTNAME xtensa xtreg	ar24            	0x0118
+$_XTNAME xtensa xtreg	ar25            	0x0119
+$_XTNAME xtensa xtreg	ar26            	0x011a
+$_XTNAME xtensa xtreg	ar27            	0x011b
+$_XTNAME xtensa xtreg	ar28            	0x011c
+$_XTNAME xtensa xtreg	ar29            	0x011d
+$_XTNAME xtensa xtreg	ar30            	0x011e
+$_XTNAME xtensa xtreg	ar31            	0x011f
+$_XTNAME xtensa xtreg	lbeg            	0x0200
+$_XTNAME xtensa xtreg	lend            	0x0201
+$_XTNAME xtensa xtreg	lcount          	0x0202
+$_XTNAME xtensa xtreg	sar             	0x0203
+$_XTNAME xtensa xtreg	windowbase      	0x0248
+$_XTNAME xtensa xtreg	windowstart     	0x0249
+$_XTNAME xtensa xtreg	configid0       	0x02b0
+$_XTNAME xtensa xtreg	configid1       	0x02d0
+$_XTNAME xtensa xtreg	ps              	0x02e6
+$_XTNAME xtensa xtreg	expstate        	0x03e6
+$_XTNAME xtensa xtreg	mmid            	0x0259
+$_XTNAME xtensa xtreg	ibreakenable    	0x0260
+$_XTNAME xtensa xtreg	ddr             	0x0268
+$_XTNAME xtensa xtreg	ibreaka0        	0x0280
+$_XTNAME xtensa xtreg	ibreaka1        	0x0281
+$_XTNAME xtensa xtreg	dbreaka0        	0x0290
+$_XTNAME xtensa xtreg	dbreaka1        	0x0291
+$_XTNAME xtensa xtreg	dbreakc0        	0x02a0
+$_XTNAME xtensa xtreg	dbreakc1        	0x02a1
+$_XTNAME xtensa xtreg	epc1            	0x02b1
+$_XTNAME xtensa xtreg	epc2            	0x02b2
+$_XTNAME xtensa xtreg	epc3            	0x02b3
+$_XTNAME xtensa xtreg	depc            	0x02c0
+$_XTNAME xtensa xtreg	eps2            	0x02c2
+$_XTNAME xtensa xtreg	eps3            	0x02c3
+$_XTNAME xtensa xtreg	excsave1        	0x02d1
+$_XTNAME xtensa xtreg	excsave2        	0x02d2
+$_XTNAME xtensa xtreg	excsave3        	0x02d3
+$_XTNAME xtensa xtreg	interrupt       	0x02e2
+$_XTNAME xtensa xtreg	intset          	0x02e2
+$_XTNAME xtensa xtreg	intclear        	0x02e3
+$_XTNAME xtensa xtreg	intenable       	0x02e4
+$_XTNAME xtensa xtreg	exccause        	0x02e8
+$_XTNAME xtensa xtreg	debugcause      	0x02e9
+$_XTNAME xtensa xtreg	ccount          	0x02ea
+$_XTNAME xtensa xtreg	icount          	0x02ec
+$_XTNAME xtensa xtreg	icountlevel     	0x02ed
+$_XTNAME xtensa xtreg	excvaddr        	0x02ee
+$_XTNAME xtensa xtreg	ccompare0       	0x02f0
+$_XTNAME xtensa xtreg	ccompare1       	0x02f1
+$_XTNAME xtensa xtreg	pwrctl          	0x200f
+$_XTNAME xtensa xtreg	pwrstat         	0x2010
+$_XTNAME xtensa xtreg	eristat         	0x2011
+$_XTNAME xtensa xtreg	cs_itctrl       	0x2012
+$_XTNAME xtensa xtreg	cs_claimset     	0x2013
+$_XTNAME xtensa xtreg	cs_claimclr     	0x2014
+$_XTNAME xtensa xtreg	cs_lockaccess   	0x2015
+$_XTNAME xtensa xtreg	cs_lockstatus   	0x2016
+$_XTNAME xtensa xtreg	cs_authstatus   	0x2017
+$_XTNAME xtensa xtreg	fault_info      	0x2026
+$_XTNAME xtensa xtreg	trax_id         	0x2027
+$_XTNAME xtensa xtreg	trax_control    	0x2028
+$_XTNAME xtensa xtreg	trax_status     	0x2029
+$_XTNAME xtensa xtreg	trax_data       	0x202a
+$_XTNAME xtensa xtreg	trax_address    	0x202b
+$_XTNAME xtensa xtreg	trax_pctrigger  	0x202c
+$_XTNAME xtensa xtreg	trax_pcmatch    	0x202d
+$_XTNAME xtensa xtreg	trax_delay      	0x202e
+$_XTNAME xtensa xtreg	trax_memstart   	0x202f
+$_XTNAME xtensa xtreg	trax_memend     	0x2030
+$_XTNAME xtensa xtreg	pmg             	0x203e
+$_XTNAME xtensa xtreg	pmpc            	0x203f
+$_XTNAME xtensa xtreg	pm0             	0x2040
+$_XTNAME xtensa xtreg	pm1             	0x2041
+$_XTNAME xtensa xtreg	pmctrl0         	0x2042
+$_XTNAME xtensa xtreg	pmctrl1         	0x2043
+$_XTNAME xtensa xtreg	pmstat0         	0x2044
+$_XTNAME xtensa xtreg	pmstat1         	0x2045
+$_XTNAME xtensa xtreg	ocdid           	0x2046
+$_XTNAME xtensa xtreg	ocd_dcrclr      	0x2047
+$_XTNAME xtensa xtreg	ocd_dcrset      	0x2048
+$_XTNAME xtensa xtreg	ocd_dsr         	0x2049
+$_XTNAME xtensa xtreg	psintlevel      	0x2003
+$_XTNAME xtensa xtreg	psum            	0x2004
+$_XTNAME xtensa xtreg	pswoe           	0x2005
+$_XTNAME xtensa xtreg	psexcm          	0x2006
+$_XTNAME xtensa xtreg	pscallinc       	0x2007
+$_XTNAME xtensa xtreg	psowb           	0x2008
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa.cfg
new file mode 100644
index 0000000..c277673
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/xtensa.cfg
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Target Support for Xtensa Processors
+#
+
+set xtensa_ids { 0x120034e5 0x120134e5
+				 0x209034e5 0x209134e5 0x209234e5 0x209334e5 0x209434e5 0x209534e5 0x209634e5 0x209734e5
+				 0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5 0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5
+				 0x20b034e5 0x20b33ac5 0x20b33ac7 }
+set expected_xtensa_ids {}
+foreach i $xtensa_ids {
+	lappend expected_xtensa_ids -expected-id $i
+}
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xtensa
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPARGLIST "-expected-id $CPUTAPID"
+} else {
+	set _CPUTAPARGLIST [join $expected_xtensa_ids]
+}
+
+if { [info exists XTENSA_NUM_CORES] } {
+	set _XTENSA_NUM_CORES $XTENSA_NUM_CORES
+} else {
+	set _XTENSA_NUM_CORES 1
+}
+
+set _TARGETNAME $_CHIPNAME
+set _CPU0NAME cpu
+set _TAPNAME $_CHIPNAME.$_CPU0NAME
+
+if { [info exists XTENSA_DAP] } {
+	source [find target/swj-dp.tcl]
+	# SWD mode ignores the -irlen parameter
+	eval swj_newdap $_CHIPNAME cpu -irlen 4 $_CPUTAPARGLIST
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+	set _TARGETNAME $_CHIPNAME.cpu
+	if { [info exists XTENSA_DAP_BASE] } {
+		# Specify fixed offset for accessing XDM via APB behind a DAP interface
+		target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap -dbgbase $XTENSA_DAP_BASE
+	} else {
+		target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap
+	}
+} elseif { $_XTENSA_NUM_CORES > 1 } {
+	# JTAG direct (without DAP)
+	for {set i 0} {$i < $_XTENSA_NUM_CORES} {incr i} {
+		set _LCPUNAME $_CPU0NAME$i
+		set _LTAPNAME $_CHIPNAME.$_LCPUNAME
+		eval jtag newtap $_CHIPNAME $_LCPUNAME -irlen 5 $_CPUTAPARGLIST
+		target create $_LTAPNAME xtensa -chain-position $_LTAPNAME -coreid $i
+
+		$_LTAPNAME configure -event reset-assert-post { soft_reset_halt }
+	}
+} else {
+	# JTAG direct (without DAP) - for legacy xtensa-config-XXX.cfg format
+	eval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST
+	target create $_TARGETNAME xtensa -chain-position $_TAPNAME
+}
+
+if { $_XTENSA_NUM_CORES == 1 } {
+	# DAP and single-core legacy JTAG
+	$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
+}
+
+gdb report_register_access_error enable
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/zynq_7000.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/zynq_7000.cfg
new file mode 100644
index 0000000..5a88b6e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/target/zynq_7000.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx Zynq-7000 All Programmable SoC
+#
+# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
+# https://www.xilinx.com/member/forms/download/sim-model-eval-license-xef.html?filename=bsdl_zynq_2.zip
+#
+# 0x03736093  XQ7Z100 XC7Z100I XC7Z100
+# 0x03731093  XQ7Z045 XC7Z045I XC7Z045
+# 0x0372c093  XQ7Z030 XC7Z030I XC7Z030 XA7Z030
+# 0x03727093  XQ7Z020 XC7Z020I XC7Z020 XA7Z020
+# 0x03732093  XC7Z035I XC7Z035
+# 0x0373b093  XC7Z015I XC7Z015
+# 0x03728093  XC7Z014S
+# 0x0373c093  XC7Z012S
+# 0x03722093  XC7Z010I XC7Z010 XA7Z010
+# 0x03723093  XC7Z007S
+
+set _CHIPNAME zynq
+set _TARGETNAME $_CHIPNAME.cpu
+
+jtag newtap zynq_pl bs -irlen 6 -ignore-version -ircapture 0x1 -irmask 0x03 \
+    -expected-id 0x03723093 \
+    -expected-id 0x03722093 \
+    -expected-id 0x0373c093 \
+    -expected-id 0x03728093 \
+    -expected-id 0x0373B093 \
+    -expected-id 0x03732093 \
+    -expected-id 0x03727093 \
+    -expected-id 0x0372C093 \
+    -expected-id 0x03731093 \
+    -expected-id 0x03736093
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
+    -coreid 0 -dbgbase 0x80090000
+target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
+    -coreid 1 -dbgbase 0x80092000
+target smp ${_TARGETNAME}0 ${_TARGETNAME}1
+
+adapter speed 1000
+
+${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
+${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
+
+pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
+virtex2 set_user_codes zynq_pl.pld 0x02 0x03 0x22 0x23
+
+set XC7_JSHUTDOWN 0x0d
+set XC7_JPROGRAM 0x0b
+set XC7_JSTART 0x0c
+set XC7_BYPASS 0x3f
+
+proc zynqpl_program {tap} {
+	echo "DEPRECATED! use 'virtex2 program ...' not 'zynqpl_program'"
+	global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
+	irscan $tap $XC7_JSHUTDOWN
+	irscan $tap $XC7_JPROGRAM
+	runtest 60000
+	#JSTART prevents this from working...
+	#irscan $tap $XC7_JSTART
+	runtest 2000
+	irscan $tap $XC7_BYPASS
+	runtest 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/test/selftest.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/test/selftest.cfg
new file mode 100644
index 0000000..10efb0c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/test/selftest.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+add_help_text selftest "run selftest using working ram  
     "
+
+proc selftest {tmpfile address size} {
+
+   for {set i 0} {$i < $size } {set i [expr {$i+4}]} {
+       mww [expr {$address+$i}] $i
+   }
+
+   for {set i 0} {$i < 10 } {set i [expr {$i+1}]} {
+    echo "Test iteration $i"
+    dump_image $tmpfile $address $size
+	verify_image $tmpfile $address bin
+	load_image $tmpfile $address bin
+   }
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/test/syntax1.cfg b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/test/syntax1.cfg
new file mode 100644
index 0000000..7735ee9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/test/syntax1.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough
+adapter assert trst assert srst
+adapter deassert trst deassert srst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f
+
+#target configuration
+#daemon_startup reset
+
+set _TARGETNAME [format "%s.cpu" lpc2148]
+target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+soft_reset_halt
+mvb 0xE01FC040 0x01
+}
+
+
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/tools/firmware-recovery.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/tools/firmware-recovery.tcl
new file mode 100644
index 0000000..6a328cd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/tools/firmware-recovery.tcl
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "\n\nFirmware recovery helpers"
+echo "Use -c firmware_help to get help\n"
+
+set known_boards {
+    "asus-rt-n16		ASUS RT-N16"
+    "asus-rt-n66u		ASUS RT-N66U"
+    "linksys-wag200g		Linksys WAG200G"
+    "linksys-wrt54gl		Linksys WRT54GL v1.1"
+    "netgear-dg834v3		Netgear DG834G v3"
+    "tp-link_tl-mr3020		TP-LINK TL-MR3020"
+    "bt-homehubv1		BT HomeHub v1"
+}
+
+proc firmware_help { } {
+    echo "
+Your OpenOCD command should look like this:
+openocd -f interface/.cfg -f tools/firmware-recovery.tcl -c \"*; shutdown\"
+
+Where:
+ is one of the supported devices, e.g. ftdi/jtagkey2
+ are firmware-recovery commands separated by semicolon
+
+Supported commands:
+firmware_help			get this help
+list_boards			list known boards and exit
+board 			select board you work with
+list_partitions			list partitions of the currently selected board
+dump_part  	save partition's contents to a file
+erase_part 		erase the given partition
+flash_part  	erase, flash and verify the given partition
+ram_boot 		load binary file to RAM and run it
+adapter speed 		set JTAG clock frequency in kHz
+
+For example, to clear nvram and reflash CFE on an RT-N16 using TUMPA, run:
+openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\
+	-c \"board asus-rt-n16; erase_part nvram; flash_part CFE cfe-n16.bin; shutdown\"
+\n\n"
+    shutdown
+}
+
+# set default, can be overridden later
+adapter speed 1000
+
+proc get_partition { name } {
+    global partition_list
+    dict get $partition_list $name
+}
+
+proc partition_desc { name } { lindex [get_partition $name] 0 }
+proc partition_start { name } { lindex [get_partition $name] 1 }
+proc partition_size { name } { lindex [get_partition $name] 2 }
+
+proc list_boards { } {
+    global known_boards
+    echo "List of the supported boards:\n"
+    echo "Board name\t\tDescription"
+    echo "-----------------------------------"
+    foreach i $known_boards {
+	echo $i
+    }
+    echo "\n\n"
+}
+
+proc board { name } {
+    script [find board/$name.cfg]
+}
+
+proc list_partitions { } {
+    global partition_list
+    set fstr "%-16s%-14s%-14s%s"
+    echo "\nThe currently selected board is known to have these partitions:\n"
+    echo [format $fstr Name Start Size Description]
+    echo "-------------------------------------------------------"
+    for {set i 0} {$i < [llength $partition_list]} {incr i 2} {
+	set key [lindex $partition_list $i]
+	echo [format $fstr $key [partition_start $key] [partition_size $key] [partition_desc $key]]
+    }
+    echo "\n\n"
+}
+
+# Magic to work with any targets, including semi-functional
+proc prepare_target { } {
+    init
+    catch {halt}
+    catch {reset init}
+    catch {halt}
+}
+
+proc dump_part { name filename } {
+    prepare_target
+    dump_image $filename [partition_start $name] [partition_size $name]
+}
+
+proc erase_part { name } {
+    prepare_target
+    flash erase_address [partition_start $name] [partition_size $name]
+}
+
+proc flash_part { name filename } {
+    prepare_target
+    flash write_image erase $filename [partition_start $name] bin
+    echo "Verifying:"
+    verify_image $filename [partition_start $name]
+}
+
+proc ram_boot { filename } {
+    global ram_boot_address
+    prepare_target
+    load_image $filename $ram_boot_address bin
+    resume $ram_boot_address
+}
+
+echo ""
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/tools/memtest.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/tools/memtest.tcl
new file mode 100644
index 0000000..f70f950
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/tools/memtest.tcl
@@ -0,0 +1,191 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Algorithms by Michael Barr, released into public domain
+# Ported to OpenOCD by Shane Volpe, additional fixes by Paul Fertser
+
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+source [find bitsbytes.tcl]
+source [find memory.tcl]
+
+proc runAllMemTests { baseAddress nBytes } {
+    memTestDataBus $baseAddress
+    memTestAddressBus $baseAddress $nBytes
+    memTestDevice $baseAddress $nBytes
+}
+
+#***********************************************************************************
+# *
+# * Function:    memTestDataBus()
+# *
+# * Description: Test the data bus wiring in a memory region by
+# *              performing a walking 1's test at a fixed address
+# *              within that region.  The address (and hence the
+# *              memory region) is selected by the caller.
+# *		 Ported from:
+# *		 http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C
+# * Notes:
+# *
+# * Returns:     Empty string if the test succeeds.
+# *              A non-zero result is the first pattern that failed.
+# *
+#***********************************************************************************
+proc memTestDataBus { address } {
+    echo "Running memTestDataBus"
+
+    for {set i 0} {$i < 32} {incr i} {
+	# Shift bit
+	set pattern [expr {1 << $i}]
+
+	# Write pattern to memory
+	memwrite32 $address $pattern
+
+	# Read pattern from memory
+	set data [memread32 $address]
+
+	if {$data != $pattern} {
+	    echo "FAILED DATABUS: Address: $address, Pattern: $pattern, Returned: $data"
+	    return $pattern
+	}
+    }
+}
+
+#***********************************************************************************
+# *
+# * Function:    memTestAddressBus()
+# *
+# * Description: Perform a walking 1's test on the relevant bits
+# *              of the address and check for aliasing.  This test
+# *              will find single-bit address failures such as stuck
+# *              -high, stuck-low, and shorted pins.  The base address
+# *              and size of the region are selected by the caller.
+# *		 Ported from:
+# *		 http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C
+# *
+# * Notes:       For best results, the selected base address should
+# *              have enough LSB 0's to guarantee single address bit
+# *              changes.  For example, to test a 64-Kbyte region,
+# *              select a base address on a 64-Kbyte boundary.  Also,
+# *              select the region size as a power-of-two--if at all
+# *              possible.
+# *
+# * Returns:     Empty string if the test succeeds.
+# *              A non-zero result is the first address at which an
+# *              aliasing problem was uncovered.  By examining the
+# *              contents of memory, it may be possible to gather
+# *              additional information about the problem.
+# *
+#***********************************************************************************
+proc memTestAddressBus { baseAddress nBytes } {
+    set addressMask [expr {$nBytes - 1}]
+    set pattern 0xAAAAAAAA
+    set antipattern 0x55555555
+
+    echo "Running memTestAddressBus"
+
+    echo "addressMask: [convertToHex $addressMask]"
+
+    echo "memTestAddressBus: Writing the default pattern at each of the power-of-two offsets..."
+    for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}] } {
+	set addr [expr {$baseAddress + $offset}]
+	memwrite32 $addr $pattern
+    }
+
+    echo "memTestAddressBus: Checking for address bits stuck high..."
+    memwrite32 $baseAddress $antipattern
+
+    for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} {
+	set addr [expr {$baseAddress + $offset}]
+	set data [memread32 $addr]
+
+	if {$data != $pattern} {
+	    echo "FAILED DATA_ADDR_BUS_SHIGH: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]"
+	    return $pattern
+	}
+    }
+
+    echo "memTestAddressBus: Checking for address bits stuck low or shorted..."
+    memwrite32 $baseAddress $pattern
+    for {set testOffset 32} {[expr {$testOffset & $addressMask}] != 0} {set testOffset [expr {$testOffset << 1}] } {
+	set addr [expr {$baseAddress + $testOffset}]
+	memwrite32 $addr $antipattern
+
+	set data [memread32 $baseAddress]
+	if {$data != $pattern} {
+	    echo "FAILED DATA_ADDR_BUS_SLOW: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]"
+	    return $pattern
+	}
+
+	for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} {
+	    set addr [expr {$baseAddress + $offset}]
+	    set data [memread32 $baseAddress]
+
+            if {(($data != $pattern) && ($offset != $testOffset))} {
+		echo "FAILED DATA_ADDR_BUS_SLOW2: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset], testOffset [convertToHex $testOffset]"
+		return $pattern
+	    }
+        }
+	set addr [expr {$baseAddress + $testOffset}]
+	memwrite32 $addr $pattern
+    }
+}
+
+#***********************************************************************************
+# *
+# * Function:    memTestDevice()
+# *
+# * Description: Test the integrity of a physical memory device by
+# *              performing an increment/decrement test over the
+# *              entire region.  In the process every storage bit
+# *              in the device is tested as zero and as one.  The
+# *              base address and the size of the region are
+# *              selected by the caller.
+# *		 Ported from:
+# *		 http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C
+# * Notes:
+# *
+# * Returns:     Empty string if the test succeeds.
+# *              A non-zero result is the first address at which an
+# *              incorrect value was read back.  By examining the
+# *              contents of memory, it may be possible to gather
+# *              additional information about the problem.
+# *
+#***********************************************************************************
+proc memTestDevice { baseAddress nBytes } {
+    echo "Running memTestDevice"
+
+    echo "memTestDevice: Filling memory with a known pattern..."
+    for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {
+	memwrite32 [expr {$baseAddress + $offset}] $pattern
+    }
+
+    echo "memTestDevice: Checking each location and inverting it for the second pass..."
+    for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {
+	set addr [expr {$baseAddress + $offset}]
+	set data [memread32 $addr]
+
+	if {$data != $pattern} {
+	    echo "FAILED memTestDevice_pattern: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset]"
+	    return $pattern
+	}
+
+	set antiPattern [expr {~$pattern}]
+	memwrite32 [expr {$baseAddress + $offset}] $antiPattern
+    }
+
+    echo "memTestDevice: Checking each location for the inverted pattern and zeroing it..."
+    for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {
+	set antiPattern [expr {~$pattern & ((1<<32) - 1)}]
+	set addr [expr {$baseAddress + $offset}]
+	set data [memread32 $addr]
+	set dataHex [convertToHex $data]
+	set antiPatternHex [convertToHex $antiPattern]
+	if {$dataHex != $antiPatternHex} {
+	    echo "FAILED memTestDevice_antipattern: Address: [convertToHex $addr], antiPattern: $antiPatternHex, Returned: $dataHex, offset: $offset"
+	    return $pattern
+	}
+    }
+}
+
+proc convertToHex { value } {
+    format 0x%08x $value
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/tools/test_cpu_speed.tcl b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/tools/test_cpu_speed.tcl
new file mode 100644
index 0000000..f1a3fb3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/scripts/tools/test_cpu_speed.tcl
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Description:
+#  Measure the CPU clock frequency of an ARM Cortex-M based device.
+#
+# Return:
+#  The CPU clock frequency in Hz. A negative value indicates that the loop
+#  counter was saturated.
+#
+# Note:
+#  You may need to adapt the number of cycles for your device.
+#
+add_help_text cortex_m_test_cpu_speed "Measure the CPU clock frequency of an ARM Cortex-M based device"
+add_usage_text cortex_m_test_cpu_speed {address [timeout [cycles_per_loop]]}
+proc cortex_m_test_cpu_speed { address { timeout 200 } { cycles_per_loop 4 } } {
+	set loop_counter_start 0xffffffff
+
+	halt
+
+	# Backup registers and memory.
+	set backup_regs [get_reg -force {pc r0 xpsr}]
+	set backup_mem [read_memory $address 16 3]
+
+	# We place the following code at the given address to measure the
+	# CPU clock frequency:
+	#
+	# 3801: subs r0, #1
+	# d1fd: bne #-2
+	# e7fe: b #-4
+	write_memory $address 16 {0x3801 0xd1fd 0xe7fe}
+
+	set_reg "pc $address r0 $loop_counter_start"
+	resume
+	sleep $timeout
+	halt
+
+	# Get the loop counter value from register r0.
+	set loop_counter_end [dict values [get_reg r0]]
+	set loop_counter_diff [expr {$loop_counter_start - $loop_counter_end}]
+
+	# Restore registers and memory.
+	set_reg $backup_regs
+	write_memory $address 16 $backup_mem
+
+	if { [expr {$loop_counter_end == 0}] } {
+		return -1
+	}
+
+	return [expr {double($loop_counter_diff) * $cycles_per_loop / $timeout * 1000}]
+}
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/dir b/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/dir
new file mode 100644
index 0000000..637a63b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/dir
@@ -0,0 +1,18 @@
+This is the file .../info/dir, which contains the
+topmost node of the Info hierarchy, called (dir)Top.
+The first time you invoke Info you start off looking at this node.
+
+File: dir,	Node: Top	This is the top of the INFO tree
+
+  This (the Directory node) gives a menu of major topics.
+  Typing "q" exits, "H" lists all Info commands, "d" returns here,
+  "h" gives a primer for first-timers,
+  "mEmacs" visits the Emacs manual, etc.
+
+  In Emacs, you can click mouse button 2 on a menu item or cross reference
+  to select it.
+
+* Menu:
+
+Development
+* OpenOCD: (openocd).           OpenOCD User's Guide
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/openocd.info b/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/openocd.info
new file mode 100644
index 0000000..bbf7d7e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/openocd.info
@@ -0,0 +1,124 @@
+This is openocd.info, produced by makeinfo version 6.6 from
+openocd.texi.
+
+This User's Guide documents release 0.12.0+dev, dated 2 November 2025,
+of the Open On-Chip Debugger (OpenOCD).
+
+   * Copyright (C) 2008-2022 The OpenOCD Project
+   * Copyright (C) 2007-2008 Spencer Oliver 
+   * Copyright (C) 2008-2010 Oyvind Harboe 
+   * Copyright (C) 2008 Duane Ellis 
+   * Copyright (C) 2009-2010 David Brownell
+
+     Permission is granted to copy, distribute and/or modify this
+     document under the terms of the GNU Free Documentation License,
+     Version 1.2 or any later version published by the Free Software
+     Foundation; with no Invariant Sections, no Front-Cover Texts, and
+     no Back-Cover Texts.  A copy of the license is included in the
+     section entitled "GNU Free Documentation License".
+INFO-DIR-SECTION Development
+START-INFO-DIR-ENTRY
+* OpenOCD: (openocd).      OpenOCD User's Guide
+END-INFO-DIR-ENTRY
+
+
+Indirect:
+openocd.info-1: 995
+openocd.info-2: 353031
+openocd.info-3: 603246
+
+Tag Table:
+(Indirect)
+Node: Top995
+Node: About3514
+Node: Developers7846
+Node: Debug Adapter Hardware11186
+Node: About Jim-Tcl23626
+Node: Running25771
+Node: OpenOCD Project Setup31167
+Ref: OpenOCD Project Setup-Footnote-151119
+Ref: OpenOCD Project Setup-Footnote-251459
+Ref: OpenOCD Project Setup-Footnote-351727
+Node: Config File Guidelines52055
+Ref: theinitboardprocedure63234
+Ref: theinittargetsprocedure74574
+Ref: translatingconfigurationfiles78246
+Ref: Config File Guidelines-Footnote-179497
+Node: Server Configuration79572
+Ref: configurationstage79894
+Ref: enteringtherunstage81369
+Ref: tcpipports84822
+Ref: gdb port85357
+Ref: gdbconfiguration87764
+Ref: gdbbreakpointoverride88079
+Ref: gdbflashprogram88454
+Ref: eventpolling89964
+Node: Debug Adapter Configuration92400
+Ref: adapter gpio94626
+Ref: hla_interface129020
+Ref: st_link_dap_interface130117
+Ref: swimtransport151012
+Ref: jtagspeed151779
+Node: Reset Configuration154741
+Ref: srstandtrstissues157669
+Ref: reset_config161851
+Node: TAP Declaration169763
+Ref: enablinganddisablingtaps181964
+Ref: autoprobing184611
+Ref: dapdeclaration187266
+Ref: dap_create187780
+Ref: DAP subcommand apreg190606
+Ref: TAP Declaration-Footnote-1193995
+Node: CPU Configuration194195
+Ref: targettypes197089
+Ref: targetconfiguration201296
+Ref: rtostype207090
+Ref: gdbportoverride210070
+Ref: targetcurstate215108
+Ref: targetevents217351
+Node: Flash Commands224397
+Ref: norconfiguration225930
+Ref: flashprogrammingcommands229167
+Ref: flashprotect236947
+Ref: program237773
+Ref: flashdriverlist238053
+Ref: jtagspi240803
+Ref: at91sam3262932
+Ref: atsame5266288
+Ref: nandconfiguration336921
+Ref: nanddriverlist347307
+Node: Flash Programming353031
+Node: PLD/FPGA Commands354644
+Node: General Commands362256
+Ref: debuglevel365228
+Ref: targetstatehandling366556
+Ref: resetcommand372891
+Ref: memoryaccess375310
+Ref: imageaccess377178
+Node: Architecture and Core Commands385812
+Ref: armhardwaretracing386282
+Ref: traceportdrivers394196
+Ref: armcrosstrigger395927
+Ref: arm9vectorcatch405545
+Ref: xscalevectorcatch413450
+Ref: add-reg-type-struct468724
+Ref: softwaredebugmessagesandtracing485845
+Node: JTAG Commands489314
+Node: Boundary Scan Commands496804
+Node: Utility Commands505986
+Node: Nuclei Commands507831
+Node: GDB and OpenOCD513294
+Ref: programmingusinggdb518405
+Ref: gdbmeminspect520051
+Ref: gdbrtossupport521988
+Ref: usingopenocdsmpwithgdb524863
+Node: Tcl Scripting API525537
+Node: FAQ529053
+Ref: faqrtck529163
+Ref: faqtaporder541054
+Node: Tcl Crash Course542820
+Node: License554828
+Node: OpenOCD Concept Index577240
+Node: Command and Driver Index603246
+
+End Tag Table
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/openocd.info-1 b/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/openocd.info-1
new file mode 100644
index 0000000..e8873d7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/openocd.info-1
@@ -0,0 +1,7697 @@
+This is openocd.info, produced by makeinfo version 6.6 from
+openocd.texi.
+
+This User's Guide documents release 0.12.0+dev, dated 2 November 2025,
+of the Open On-Chip Debugger (OpenOCD).
+
+   * Copyright (C) 2008-2022 The OpenOCD Project
+   * Copyright (C) 2007-2008 Spencer Oliver 
+   * Copyright (C) 2008-2010 Oyvind Harboe 
+   * Copyright (C) 2008 Duane Ellis 
+   * Copyright (C) 2009-2010 David Brownell
+
+     Permission is granted to copy, distribute and/or modify this
+     document under the terms of the GNU Free Documentation License,
+     Version 1.2 or any later version published by the Free Software
+     Foundation; with no Invariant Sections, no Front-Cover Texts, and
+     no Back-Cover Texts.  A copy of the license is included in the
+     section entitled "GNU Free Documentation License".
+INFO-DIR-SECTION Development
+START-INFO-DIR-ENTRY
+* OpenOCD: (openocd).      OpenOCD User's Guide
+END-INFO-DIR-ENTRY
+
+
+File: openocd.info,  Node: Top,  Next: About,  Up: (dir)
+
+OpenOCD User's Guide
+********************
+
+This User's Guide documents release 0.12.0+dev, dated 2 November 2025,
+of the Open On-Chip Debugger (OpenOCD).
+
+   * Copyright (C) 2008-2022 The OpenOCD Project
+   * Copyright (C) 2007-2008 Spencer Oliver 
+   * Copyright (C) 2008-2010 Oyvind Harboe 
+   * Copyright (C) 2008 Duane Ellis 
+   * Copyright (C) 2009-2010 David Brownell
+
+     Permission is granted to copy, distribute and/or modify this
+     document under the terms of the GNU Free Documentation License,
+     Version 1.2 or any later version published by the Free Software
+     Foundation; with no Invariant Sections, no Front-Cover Texts, and
+     no Back-Cover Texts.  A copy of the license is included in the
+     section entitled "GNU Free Documentation License".
+
+* Menu:
+
+* About::                            About OpenOCD
+* Developers::                       OpenOCD Developer Resources
+* Debug Adapter Hardware::           Debug Adapter Hardware
+* About Jim-Tcl::                    About Jim-Tcl
+* Running::                          Running OpenOCD
+* OpenOCD Project Setup::            OpenOCD Project Setup
+* Config File Guidelines::           Config File Guidelines
+* Server Configuration::             Server Configuration
+* Debug Adapter Configuration::      Debug Adapter Configuration
+* Reset Configuration::              Reset Configuration
+* TAP Declaration::                  TAP Declaration
+* CPU Configuration::                CPU Configuration
+* Flash Commands::                   Flash Commands
+* Flash Programming::                Flash Programming
+* PLD/FPGA Commands::                PLD/FPGA Commands
+* General Commands::                 General Commands
+* Architecture and Core Commands::   Architecture and Core Commands
+* JTAG Commands::                    JTAG Commands
+* Boundary Scan Commands::           Boundary Scan Commands
+* Utility Commands::                 Utility Commands
+* Nuclei Commands::                  Nuclei Commands
+* GDB and OpenOCD::                  Using GDB and OpenOCD
+* Tcl Scripting API::                Tcl Scripting API
+* FAQ::                              Frequently Asked Questions
+* Tcl Crash Course::                 Tcl Crash Course
+* License::                          GNU Free Documentation License
+
+* OpenOCD Concept Index::            Concept Index
+* Command and Driver Index::         Command and Driver Index
+
+
+File: openocd.info,  Node: About,  Next: Developers,  Prev: Top,  Up: Top
+
+About
+*****
+
+OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis
+written at the University of Applied Sciences Augsburg
+().  Since that time, the project has grown
+into an active open-source project, supported by a diverse community of
+software and hardware developers from around the world.
+
+What is OpenOCD?
+================
+
+The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system
+programming and boundary-scan testing for embedded target devices.
+
+It does so with the assistance of a "debug adapter", which is a small
+hardware module which helps provide the right kind of electrical
+signaling to the target being debugged.  These are required since the
+debug host (on which OpenOCD runs) won't usually have native support for
+such signaling, or the connector needed to hook up to the target.
+
+Such debug adapters support one or more "transport" protocols, each of
+which involves different electrical signaling (and uses different
+messaging protocols on top of that signaling).  There are many types of
+debug adapter, and little uniformity in what they are called.  (There
+are also product naming differences.)
+
+These adapters are sometimes packaged as discrete dongles, which may
+generically be called "hardware interface dongles".  Some development
+boards also integrate them directly, which may let the development board
+connect directly to the debug host over USB (and sometimes also to power
+it over USB).
+
+For example, a "JTAG Adapter" supports JTAG signaling, and is used to
+communicate with JTAG (IEEE 1149.1) compliant TAPs on your target board.
+A "TAP" is a "Test Access Port", a module which processes special
+instructions and data.  TAPs are daisy-chained within and between chips
+and boards.  JTAG supports debugging and boundary scan operations.
+
+There are also "SWD Adapters" that support Serial Wire Debug (SWD)
+signaling to communicate with some newer ARM cores, as well as debug
+adapters which support both JTAG and SWD transports.  SWD supports only
+debugging, whereas JTAG also supports boundary scan operations.
+
+For some chips, there are also "Programming Adapters" supporting special
+transports used only to write code to flash memory, without support for
+on-chip debugging or boundary scan.  (At this writing, OpenOCD does not
+support such non-debug adapters.)
+
+Dongles: OpenOCD currently supports many types of hardware dongles:
+USB-based, parallel port-based, and other standalone boxes that run
+OpenOCD internally.  *Note Debug Adapter Hardware::.
+
+GDB Debug: It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
+ARM922T, ARM926EJ-S, ARM966E-S), XScale (PXA25x, IXP42x), Cortex-M3
+(Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
+Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
+
+Flash Programming: Flash writing is supported for external
+CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and
+several internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7,
+AT91SAM3U, STR7x, STR9x, LM3, STM32x and EFM32).  Preliminary support
+for various NAND flash controllers (LPC3180, Orion, S3C24xx, more) is
+included.
+
+OpenOCD Web Site
+================
+
+The OpenOCD web site provides the latest public news from the community:
+
+
+
+Latest User's Guide:
+====================
+
+The user's guide you are now reading may not be the latest one
+available.  A version for more recent code may be available.  Its HTML
+form is published regularly at:
+
+
+
+PDF form is likewise published at:
+
+
+
+OpenOCD User's Forum
+====================
+
+There is an OpenOCD forum (phpBB) hosted by SparkFun, which might be
+helpful to you.  Note that if you want anything to come to the attention
+of developers, you should post it to the OpenOCD Developer Mailing List
+instead of this forum.
+
+
+
+OpenOCD User's Mailing List
+===========================
+
+The OpenOCD User Mailing List provides the primary means of
+communication between users:
+
+
+
+OpenOCD IRC
+===========
+
+Support can also be found on irc: 
+
+
+File: openocd.info,  Node: Developers,  Next: Debug Adapter Hardware,  Prev: About,  Up: Top
+
+1 OpenOCD Developer Resources
+*****************************
+
+If you are interested in improving the state of OpenOCD's debugging and
+testing support, new contributions will be welcome.  Motivated
+developers can produce new target, flash or interface drivers, improve
+the documentation, as well as more conventional bug fixes and
+enhancements.
+
+The resources in this chapter are available for developers wishing to
+explore or expand the OpenOCD source code.
+
+1.1 OpenOCD Git Repository
+==========================
+
+During the 0.3.x release cycle, OpenOCD switched from Subversion to a
+Git repository hosted at SourceForge.  The repository URL is:
+
+
+
+or via http
+
+
+
+You may prefer to use a mirror and the HTTP protocol:
+
+
+
+With standard Git tools, use 'git clone' to initialize a local
+repository, and 'git pull' to update it.  There are also gitweb pages
+letting you browse the repository with a web browser, or download
+arbitrary snapshots without needing a Git client:
+
+
+
+The 'README' file contains the instructions for building the project
+from the repository or a snapshot.
+
+Developers that want to contribute patches to the OpenOCD system are
+strongly encouraged to work against mainline.  Patches created against
+older versions may require additional work from their submitter in order
+to be updated for newer releases.
+
+1.2 Doxygen Developer Manual
+============================
+
+During the 0.2.x release cycle, the OpenOCD project began providing a
+Doxygen reference manual.  This document contains more technical
+information about the software internals, development processes, and
+similar documentation:
+
+
+
+This document is a work-in-progress, but contributions would be welcome
+to fill in the gaps.  All of the source files are provided in-tree,
+listed in the Doxyfile configuration at the top of the source tree.
+
+1.3 Gerrit Review System
+========================
+
+All changes in the OpenOCD Git repository go through the web-based
+Gerrit Code Review System:
+
+
+
+After a one-time registration and repository setup, anyone can push
+commits from their local Git repository directly into Gerrit.  All users
+and developers are encouraged to review, test, discuss and vote for
+changes in Gerrit.  The feedback provides the basis for a maintainer to
+eventually submit the change to the main Git repository.
+
+The 'HACKING' file, also available as the Patch Guide in the Doxygen
+Developer Manual, contains basic information about how to connect a
+repository to Gerrit, prepare and push patches.  Patch authors are
+expected to maintain their changes while they're in Gerrit, respond to
+feedback and if necessary rework and push improved versions of the
+change.
+
+1.4 OpenOCD Developer Mailing List
+==================================
+
+The OpenOCD Developer Mailing List provides the primary means of
+communication between developers:
+
+
+
+1.5 OpenOCD Bug Tracker
+=======================
+
+The OpenOCD Bug Tracker is hosted on SourceForge:
+
+
+
+
+File: openocd.info,  Node: Debug Adapter Hardware,  Next: About Jim-Tcl,  Prev: Developers,  Up: Top
+
+2 Debug Adapter Hardware
+************************
+
+Defined: dongle: A small device that plugs into a computer and serves as
+an adapter ....  [snip]
+
+In the OpenOCD case, this generally refers to a small adapter that
+attaches to your computer via USB or the parallel port.
+
+2.1 Choosing a Dongle
+=====================
+
+There are several things you should keep in mind when choosing a dongle.
+
+  1. Transport Does it support the kind of communication that you need?
+     OpenOCD focuses mostly on JTAG. Your version may also support other
+     ways to communicate with target devices.
+  2. Voltage What voltage is your target - 1.8, 2.8, 3.3, or 5V? Does
+     your dongle support it?  You might need a level converter.
+  3. Pinout What pinout does your target board use?  Does your dongle
+     support it?  You may be able to use jumper wires, or an "octopus"
+     connector, to convert pinouts.
+  4. Connection Does your computer have the USB, parallel, or Ethernet
+     port needed?
+  5. RTCK Do you expect to use it with ARM chips and boards with RTCK
+     support (also known as "adaptive clocking")?
+
+2.2 USB FT2232 Based
+====================
+
+There are many USB JTAG dongles on the market, many of them based on a
+chip from "Future Technology Devices International" (FTDI) known as the
+FTDI FT2232; this is a USB full speed (12 Mbps) chip.  See:
+ for more information.  In summer 2009, USB
+high speed (480 Mbps) versions of these FTDI chips started to become
+available in JTAG adapters.  Around 2012, a new variant appeared -
+FT232H - this is a single-channel version of FT2232H. (Adapters using
+those high speed FT2232H or FT232H chips may support adaptive clocking.)
+
+The FT2232 chips are flexible enough to support some other transport
+options, such as SWD or the SPI variants used to program some chips.
+They have two communications channels, and one can be used for a UART
+adapter at the same time the other one is used to provide a debug
+adapter.
+
+Also, some development boards integrate an FT2232 chip to serve as a
+built-in low-cost debug adapter and USB-to-serial solution.
+
+   * usbjtag
+     Link
+     
+   * jtagkey
+     See: 
+   * jtagkey2
+     See: 
+   * oocdlink
+     See:  By Joern Kaipf
+   * signalyzer
+     See: 
+   * Stellaris Eval Boards
+     See:  - The Stellaris eval boards bundle
+     FT2232-based JTAG and SWD support, which can be used to debug the
+     Stellaris chips.  Using separate JTAG adapters is optional.  These
+     boards can also be used in a "pass through" mode as JTAG adapters
+     to other target boards, disabling the Stellaris chip.
+   * TI/Luminary ICDI
+     See:  - TI/Luminary In-Circuit Debug Interface
+     (ICDI) Boards are included in Stellaris LM3S9B9x Evaluation Kits.
+     Like the non-detachable FT2232 support on the other Stellaris eval
+     boards, they can be used to debug other target boards.
+   * olimex-jtag
+     See: 
+   * Flyswatter/Flyswatter2
+     See: 
+   * turtelizer2
+     See: Turtelizer 2
+     (http://www.ethernut.de/en/hardware/turtelizer/index.html), or
+     
+   * comstick
+     Link: 
+   * stm32stick
+     Link 
+   * axm0432_jtag
+     Axiom AXM-0432 Link  - NOTE: This JTAG does
+     not appear to be available anymore as of April 2012.
+   * cortino
+     Link 
+   * dlp-usb1232h
+     Link 
+   * digilent-hs1
+     Link 
+   * opendous
+     Link  FT2232H-based
+     (OpenHardware).
+   * JTAG-lock-pick Tiny 2
+     Link  FT232H-based
+
+   * GW16042
+     Link:  FT2232H-based
+
+2.3 USB-JTAG / Altera USB-Blaster compatibles
+=============================================
+
+These devices also show up as FTDI devices, but are not
+protocol-compatible with the FT2232 devices.  They are, however,
+protocol-compatible among themselves.  USB-JTAG devices typically
+consist of a FT245 followed by a CPLD that understands a particular
+protocol, or emulates this protocol using some other hardware.
+
+They may appear under different USB VID/PID depending on the particular
+product.  The driver can be configured to search for any VID/PID pair
+(see the section on driver commands).
+
+   * USB-JTAG Kolja Waschk's USB Blaster-compatible adapter
+     Link: 
+   * Altera USB-Blaster
+     Link: 
+
+2.4 USB J-Link based
+====================
+
+There are several OEM versions of the SEGGER J-Link adapter.  It is an
+example of a microcontroller based JTAG adapter, it uses an AT91SAM764
+internally.
+
+   * SEGGER J-Link
+     Link: 
+   * Atmel SAM-ICE (Only works with Atmel chips!)
+     Link: 
+   * IAR J-Link
+
+2.5 USB RLINK based
+===================
+
+Raisonance has an adapter called RLink.  It exists in a stripped-down
+form on the STM32 Primer, permanently attached to the JTAG lines.  It
+also exists on the STM32 Primer2, but that is wired for SWD and not
+JTAG, thus not supported.
+
+   * Raisonance RLink
+     Link: 
+   * STM32 Primer
+     Link: 
+   * STM32 Primer2
+     Link: 
+
+2.6 USB ST-LINK based
+=====================
+
+STMicroelectronics has an adapter called ST-LINK. They only work with
+STMicroelectronics chips, notably STM32 and STM8.
+
+   * ST-LINK
+     This is available standalone and as part of some kits, eg.
+     STM32VLDISCOVERY.
+     Link: 
+   * ST-LINK/V2
+     This is available standalone and as part of some kits, eg.
+     STM32F4DISCOVERY.
+     Link: 
+   * STLINK-V3
+     This is available standalone and as part of some kits.
+     Link: 
+   * STLINK-V3PWR
+     This is available standalone.  Beside the debugger functionality,
+     the probe includes a SMU (source measurement unit) aimed at
+     analyzing power consumption during code execution.  The SMU is not
+     supported by OpenOCD.
+     Link: 
+
+For info the original ST-LINK enumerates using the mass storage usb
+class; however, its implementation is completely broken.  The result is
+this causes issues under Linux.  The simplest solution is to get Linux
+to ignore the ST-LINK using one of the following methods:
+   * modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
+   * add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
+
+2.7 USB TI/Stellaris ICDI based
+===============================
+
+Texas Instruments has an adapter called ICDI. It is not to be confused
+with the FTDI based adapters that were originally fitted to their
+evaluation boards.  This is the adapter fitted to the Stellaris
+LaunchPad.
+
+2.8 USB Nuvoton Nu-Link
+=======================
+
+Nuvoton has an adapter called Nu-Link.  It is available either as
+stand-alone dongle and embedded on development boards.  It supports SWD,
+serial port bridge and mass storage for firmware update.  Both Nu-Link
+v1 and v2 are supported.
+
+2.9 USB CMSIS-DAP based
+=======================
+
+ARM has released a interface standard called CMSIS-DAP that simplifies
+connecting debuggers to ARM Cortex based targets
+.
+
+2.10 USB Other
+==============
+
+   * USBprog
+     Link:  - which uses an Atmel
+     MEGA32 and a UBN9604
+
+   * USB - Presto
+     Link: 
+
+   * Versaloon-Link
+     Link: 
+
+   * ARM-JTAG-EW
+     Link: 
+
+   * angie
+     Link: 
+
+   * Buspirate
+     Link: 
+
+   * opendous
+     Link:  - which uses an
+     AT90USB162
+
+   * estick
+     Link: 
+
+   * Keil ULINK v1
+     Link: 
+
+   * TI XDS110 Debug Probe
+     Link:
+     
+
+     Link:
+     
+
+2.11 IBM PC Parallel Printer Port Based
+=======================================
+
+The two well-known "JTAG Parallel Ports" cables are the Xilinx DLC5 and
+the Macraigor Wiggler.  There are many clones and variations of these on
+the market.
+
+Note that parallel ports are becoming much less common, so if you have
+the choice you should probably avoid these adapters in favor of
+USB-based ones.
+
+   * Wiggler - There are many clones of this.
+     Link: 
+
+   * DLC5 - From XILINX - There are many clones of this
+     Link: Search the web for: "XILINX DLC5" - it is no longer produced,
+     PDF schematics are easily found and it is easy to make.
+
+   * Amontec - JTAG Accelerator
+     Link: 
+
+   * Wiggler2
+     Link:
+     
+
+   * Wiggler_ntrst_inverted
+     Yet another variation - See the source code, src/jtag/parport.c
+
+   * old_amt_wiggler
+     Unknown - probably not on the market today
+
+   * arm-jtag
+     Link: Most likely 
+     [another wiggler clone]
+
+   * chameleon
+     Link: 
+
+   * Triton
+     Unknown.
+
+   * Lattice
+     ispDownload from Lattice Semiconductor
+     
+
+   * flashlink
+     From STMicroelectronics;
+     Link:
+     
+
+2.12 Other...
+=============
+
+   * ep93xx
+     An EP93xx based Linux machine using the GPIO pins directly.
+
+   * at91rm9200
+     Like the EP93xx - but an ATMEL AT91RM9200 based solution using the
+     GPIO pins on the chip.
+
+   * bcm2835gpio
+     A BCM2835-based board (e.g.  Raspberry Pi) using the GPIO pins of
+     the expansion header.
+
+   * imx_gpio
+     A NXP i.MX-based board (e.g.  Wandboard) using the GPIO pins
+     (should work on any i.MX processor).
+
+   * am335xgpio
+     A Texas Instruments AM335x-based board (e.g.  BeagleBone Black)
+     using the GPIO pins of the expansion headers.
+
+   * jtag_vpi
+     A JTAG driver acting as a client for the JTAG VPI server interface.
+
+     Link: 
+
+   * vdebug
+     A driver for Cadence virtual Debug Interface to emulated or
+     simulated targets.  It implements a client connecting to the vdebug
+     server, which in turn communicates with the emulated or simulated
+     RTL model through a transactor.  The driver supports JTAG and
+     DAP-level transports.
+
+   * jtag_dpi
+     A JTAG driver acting as a client for the SystemVerilog Direct
+     Programming Interface (DPI) for JTAG devices.  DPI allows OpenOCD
+     to connect to the JTAG interface of a hardware model written in
+     SystemVerilog, for example, on an emulation model of target
+     hardware.
+
+   * xlnx_pcie_xvc
+     A JTAG driver exposing Xilinx Virtual Cable over PCI Express to
+     OpenOCD as JTAG/SWD interface.
+
+   * linuxgpiod
+     A bitbang JTAG driver using Linux GPIO through library libgpiod.
+
+   * sysfsgpio
+     A bitbang JTAG driver using Linux legacy sysfs GPIO. This is
+     deprecated from Linux v5.3; prefer using linuxgpiod.
+
+   * esp_usb_jtag
+     A JTAG driver to communicate with builtin debug modules of
+     Espressif ESP32-C3 and ESP32-S3 chips using OpenOCD.
+
+
+File: openocd.info,  Node: About Jim-Tcl,  Next: Running,  Prev: Debug Adapter Hardware,  Up: Top
+
+3 About Jim-Tcl
+***************
+
+OpenOCD uses a small "Tcl Interpreter" known as Jim-Tcl.  This
+programming language provides a simple and extensible command
+interpreter.
+
+All commands presented in this Guide are extensions to Jim-Tcl.  You can
+use them as simple commands, without needing to learn much of anything
+about Tcl.  Alternatively, you can write Tcl programs with them.
+
+You can learn more about Jim at its website, .  There
+is an active and responsive community, get on the mailing list if you
+have any questions.  Jim-Tcl maintainers also lurk on the OpenOCD
+mailing list.
+
+   * Jim vs.  Tcl
+     Jim-Tcl is a stripped down version of the well known Tcl language,
+     which can be found here: .  Jim-Tcl has far
+     fewer features.  Jim-Tcl is several dozens of .C files and .H files
+     and implements the basic Tcl command set.  In contrast: Tcl 8.6 is
+     a 4.2 MB .zip file containing 1540 files.
+
+   * Missing Features
+     Our practice has been: Add/clone the real Tcl feature if/when
+     needed.  We welcome Jim-Tcl improvements, not bloat.  Also there
+     are a large number of optional Jim-Tcl features that are not
+     enabled in OpenOCD.
+
+   * Scripts
+     OpenOCD configuration scripts are Jim-Tcl Scripts.  OpenOCD's
+     command interpreter today is a mixture of (newer) Jim-Tcl commands,
+     and the (older) original command interpreter.
+
+   * Commands
+     At the OpenOCD telnet command line (or via the GDB monitor command)
+     one can type a Tcl for() loop, set variables, etc.  Some of the
+     commands documented in this guide are implemented as Tcl scripts,
+     from a 'startup.tcl' file internal to the server.
+
+   * Historical Note
+     Jim-Tcl was introduced to OpenOCD in spring 2008.  Fall 2010,
+     before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl as a
+     Git submodule, which greatly simplified upgrading Jim-Tcl to
+     benefit from new features and bugfixes in Jim-Tcl.
+
+   * Need a crash course in Tcl?
+     *Note Tcl Crash Course::.
+
+
+File: openocd.info,  Node: Running,  Next: OpenOCD Project Setup,  Prev: About Jim-Tcl,  Up: Top
+
+4 Running
+*********
+
+Properly installing OpenOCD sets up your operating system to grant it
+access to the debug adapters.  On Linux, this usually involves
+installing a file in '/etc/udev/rules.d,' so OpenOCD has permissions.
+An example rules file that works for many common adapters is shipped
+with OpenOCD in the 'contrib' directory.  MS-Windows needs complex and
+confusing driver configuration for every peripheral.  Such issues are
+unique to each operating system, and are not detailed in this User's
+Guide.
+
+Then later you will invoke the OpenOCD server, with various options to
+tell it how each debug session should work.  The '--help' option shows:
+bash$ openocd --help
+
+--help       | -h       display this help
+--version    | -v       display OpenOCD version
+--file       | -f       use configuration file 
+--search     | -s       dir to search for config files and scripts
+--debug      | -d       set debug level to 3
+             | -d    set debug level to 
+--log_output | -l       redirect log output to file 
+--command    | -c       run 
+
+If you don't give any '-f' or '-c' options, OpenOCD tries to read the
+configuration file 'openocd.cfg'.  To specify one or more different
+configuration files, use '-f' options.  For example:
+
+     openocd -f config1.cfg -f config2.cfg -f config3.cfg
+
+Configuration files and scripts are searched for in
+  1. the current directory,
+  2. any search dir specified on the command line using the '-s' option,
+  3. any search dir specified using the 'add_script_search_dir' command,
+  4. a directory in the 'OPENOCD_SCRIPTS' environment variable (if set),
+  5. '%APPDATA%/OpenOCD' (only on Windows),
+  6. '$HOME/Library/Preferences/org.openocd' (only on Darwin),
+  7. '$XDG_CONFIG_HOME/openocd' ('$XDG_CONFIG_HOME' defaults to
+     '$HOME/.config'),
+  8. '$HOME/.openocd',
+  9. the site wide script library '$pkgdatadir/site' and
+  10. the OpenOCD-supplied script library '$pkgdatadir/scripts'.
+The first found file with a matching file name will be used.
+
+     Note: Don't try to use configuration script names or paths which
+     include the "#" character.  That character begins Tcl comments.
+
+4.1 Simple setup, no customization
+==================================
+
+In the best case, you can use two scripts from one of the script
+libraries, hook up your JTAG adapter, and start the server ...  and your
+JTAG setup will just work "out of the box".  Always try to start by
+reusing those scripts, but assume you'll need more customization even if
+this works.  *Note OpenOCD Project Setup::.
+
+If you find a script for your JTAG adapter, and for your board or
+target, you may be able to hook up your JTAG adapter then start the
+server with some variation of one of the following:
+
+     openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
+     openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
+
+You might also need to configure which reset signals are present, using
+'-c 'reset_config trst_and_srst'' or something similar.  If all goes
+well you'll see output something like
+
+     Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
+     For bug reports, read
+             http://openocd.org/doc/doxygen/bugs.html
+     Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
+            (mfg: 0x23b, part: 0xba00, ver: 0x3)
+
+Seeing that "tap/device found" message, and no warnings, means the JTAG
+communication is working.  That's a key milestone, but you'll probably
+need more project-specific setup.
+
+4.2 What OpenOCD does as it starts
+==================================
+
+OpenOCD starts by processing the configuration commands provided on the
+command line or, if there were no '-c command' or '-f file.cfg' options
+given, in 'openocd.cfg'.  *Note Configuration Stage: configurationstage.
+At the end of the configuration stage it verifies the JTAG scan chain
+defined using those commands; your configuration should ensure that this
+always succeeds.  Normally, OpenOCD then starts running as a server.
+Alternatively, commands may be used to terminate the configuration stage
+early, perform work (such as updating some flash memory), and then shut
+down without acting as a server.
+
+Once OpenOCD starts running as a server, it waits for connections from
+clients (Telnet, GDB, RPC) and processes the commands issued through
+those channels.
+
+If you are having problems, you can enable internal debug messages via
+the '-d' option.
+
+Also it is possible to interleave Jim-Tcl commands w/config scripts
+using the '-c' command line switch.
+
+To enable debug output (when reporting problems or working on OpenOCD
+itself), use the '-d' command line switch.  This sets the 'debug_level'
+to "3", outputting the most information, including debug messages.  The
+default setting is "2", outputting only informational messages, warnings
+and errors.  You can also change this setting from within a telnet or
+gdb session using 'debug_level' (*note debug_level: debuglevel.).
+
+You can redirect all output from the server to a file using the '-l
+' switch.
+
+Note!  OpenOCD will launch the GDB & telnet server even if it can not
+establish a connection with the target.  In general, it is possible for
+the JTAG controller to be unresponsive until the target is set up
+correctly via e.g.  GDB monitor commands in a GDB init script.
+
+
+File: openocd.info,  Node: OpenOCD Project Setup,  Next: Config File Guidelines,  Prev: Running,  Up: Top
+
+5 OpenOCD Project Setup
+***********************
+
+To use OpenOCD with your development projects, you need to do more than
+just connect the JTAG adapter hardware (dongle) to your development
+board and start the OpenOCD server.  You also need to configure your
+OpenOCD server so that it knows about your adapter and board, and helps
+your work.  You may also want to connect OpenOCD to GDB, possibly using
+Eclipse or some other GUI.
+
+5.1 Hooking up the JTAG Adapter
+===============================
+
+Today's most common case is a dongle with a JTAG cable on one side (such
+as a ribbon cable with a 10-pin or 20-pin IDC connector) and a USB cable
+on the other.  Instead of USB, some dongles use Ethernet; older ones may
+use a PC parallel port, or even a serial port.
+
+  1. _Start with power to your target board turned off_, and nothing
+     connected to your JTAG adapter.  If you're particularly paranoid,
+     unplug power to the board.  It's important to have the ground
+     signal properly set up, unless you are using a JTAG adapter which
+     provides galvanic isolation between the target board and the
+     debugging host.
+
+  2. _Be sure it's the right kind of JTAG connector._  If your dongle
+     has a 20-pin ARM connector, you need some kind of adapter (or
+     octopus, see below) to hook it up to boards using 14-pin or 10-pin
+     connectors ...  or to 20-pin connectors which don't use ARM's
+     pinout.
+
+     In the same vein, make sure the voltage levels are compatible.  Not
+     all JTAG adapters have the level shifters needed to work with 1.2
+     Volt boards.
+
+  3. _Be certain the cable is properly oriented_ or you might damage
+     your board.  In most cases there are only two possible ways to
+     connect the cable.  Connect the JTAG cable from your adapter to the
+     board.  Be sure it's firmly connected.
+
+     In the best case, the connector is keyed to physically prevent you
+     from inserting it wrong.  This is most often done using a slot on
+     the board's male connector housing, which must match a key on the
+     JTAG cable's female connector.  If there's no housing, then you
+     must look carefully and make sure pin 1 on the cable hooks up to
+     pin 1 on the board.  Ribbon cables are frequently all grey except
+     for a wire on one edge, which is red.  The red wire is pin 1.
+
+     Sometimes dongles provide cables where one end is an "octopus" of
+     color coded single-wire connectors, instead of a connector block.
+     These are great when converting from one JTAG pinout to another,
+     but are tedious to set up.  Use these with connector pinout
+     diagrams to help you match up the adapter signals to the right
+     board pins.
+
+  4. _Connect the adapter's other end_ once the JTAG cable is connected.
+     A USB, parallel, or serial port connector will go to the host which
+     you are using to run OpenOCD. For Ethernet, consult the
+     documentation and your network administrator.
+
+     For USB-based JTAG adapters you have an easy sanity check at this
+     point: does the host operating system see the JTAG adapter?  If
+     you're running Linux, try the 'lsusb' command.  If that host is an
+     MS-Windows host, you'll need to install a driver before OpenOCD
+     works.
+
+  5. _Connect the adapter's power supply, if needed._  This step is
+     primarily for non-USB adapters, but sometimes USB adapters need
+     extra power.
+
+  6. _Power up the target board._  Unless you just let the magic smoke
+     escape, you're now ready to set up the OpenOCD server so you can
+     use JTAG to work with that board.
+
+Talk with the OpenOCD server using telnet ('telnet localhost 4444' on
+many systems) or GDB. *Note GDB and OpenOCD::.
+
+5.2 Project Directory
+=====================
+
+There are many ways you can configure OpenOCD and start it up.
+
+A simple way to organize them all involves keeping a single directory
+for your work with a given board.  When you start OpenOCD from that
+directory, it searches there first for configuration files, scripts,
+files accessed through semihosting, and for code you upload to the
+target board.  It is also the natural place to write files, such as log
+files and data you download from the board.
+
+5.3 Configuration Basics
+========================
+
+There are two basic ways of configuring OpenOCD, and a variety of ways
+you can mix them.  Think of the difference as just being how you start
+the server:
+
+   * Many '-f file' or '-c command' options on the command line
+   * No options, but a "user config file" in the current directory named
+     'openocd.cfg'
+
+Here is an example 'openocd.cfg' file for a setup using a Signalyzer
+FT2232-based JTAG adapter to talk to a board with an Atmel AT91SAM7X256
+microcontroller:
+
+     source [find interface/ftdi/signalyzer.cfg]
+
+     # GDB can also flash my flash!
+     gdb memory_map enable
+     gdb flash_program enable
+
+     source [find target/sam7x256.cfg]
+
+Here is the command line equivalent of that configuration:
+
+     openocd -f interface/ftdi/signalyzer.cfg \
+             -c "gdb memory_map enable" \
+             -c "gdb flash_program enable" \
+             -f target/sam7x256.cfg
+
+You could wrap such long command lines in shell scripts, each supporting
+a different development task.  One might re-flash the board with a
+specific firmware version.  Another might set up a particular debugging
+or run-time environment.
+
+     Important: At this writing (October 2009) the command line method
+     has problems with how it treats variables.  For example, after '-c
+     "set VAR value"', or doing the same in a script, the variable VAR
+     will have no value that can be tested in a later script.
+
+Here we will focus on the simpler solution: one user config file,
+including basic configuration plus any TCL procedures to simplify your
+work.
+
+5.4 User Config Files
+=====================
+
+A user configuration file ties together all the parts of a project in
+one place.  One of the following will match your situation best:
+
+   * Ideally almost everything comes from configuration files provided
+     by someone else.  For example, OpenOCD distributes a 'scripts'
+     directory (probably in '/usr/share/openocd/scripts' on Linux).
+     Board and tool vendors can provide these too, as can individual
+     user sites; the '-s' command line option lets you say where to find
+     these files.  (*Note Running::.)  The AT91SAM7X256 example above
+     works this way.
+
+     Three main types of non-user configuration file each have their own
+     subdirectory in the 'scripts' directory:
+
+       1. interface - one for each different debug adapter;
+       2. board - one for each different board
+       3. target - the chips which integrate CPUs and other JTAG TAPs
+
+     Best case: include just two files, and they handle everything else.
+     The first is an interface config file.  The second is
+     board-specific, and it sets up the JTAG TAPs and their GDB targets
+     (by deferring to some 'target.cfg' file), declares all flash
+     memory, and leaves you nothing to do except meet your deadline:
+
+          source [find interface/olimex-jtag-tiny.cfg]
+          source [find board/csb337.cfg]
+
+     Boards with a single microcontroller often won't need more than the
+     target config file, as in the AT91SAM7X256 example.  That's because
+     there is no external memory (flash, DDR RAM), and the board
+     differences are encapsulated by application code.
+
+   * Maybe you don't know yet what your board looks like to JTAG. Once
+     you know the 'interface.cfg' file to use, you may need help from
+     OpenOCD to discover what's on the board.  Once you find the JTAG
+     TAPs, you can just search for appropriate target and board
+     configuration files ...  or write your own, from the bottom up.
+     *Note Autoprobing: autoprobing.
+
+   * You can often reuse some standard config files but need to write a
+     few new ones, probably a 'board.cfg' file.  You will be using
+     commands described later in this User's Guide, and working with the
+     guidelines in the next chapter.
+
+     For example, there may be configuration files for your JTAG adapter
+     and target chip, but you need a new board-specific config file
+     giving access to your particular flash chips.  Or you might need to
+     write another target chip configuration file for a new chip built
+     around the Cortex-M3 core.
+
+          Note: When you write new configuration files, please submit
+          them for inclusion in the next OpenOCD release.  For example,
+          a 'board/newboard.cfg' file will help the next users of that
+          board, and a 'target/newcpu.cfg' will help support users of
+          any board using that chip.
+
+   * You may need to write some C code.  It may be as simple as
+     supporting a new FT2232 or parport based adapter; a bit more
+     involved, like a NAND or NOR flash controller driver; or a big
+     piece of work like supporting a new chip architecture.
+
+Reuse the existing config files when you can.  Look first in the
+'scripts/boards' area, then 'scripts/targets'.  You may find a board
+configuration that's a good example to follow.
+
+When you write config files, separate the reusable parts (things every
+user of that interface, chip, or board needs) from ones specific to your
+environment and debugging approach.
+
+   * For example, a 'gdb-attach' event handler that invokes the 'reset
+     init' command will interfere with debugging early boot code, which
+     performs some of the same actions that the 'reset-init' event
+     handler does.
+
+   * Likewise, the 'arm9 vector_catch' command (or its siblings 'xscale
+     vector_catch' and 'cortex_m vector_catch') can be a time-saver
+     during some debug sessions, but don't make everyone use that
+     either.  Keep those kinds of debugging aids in your user config
+     file, along with messaging and tracing setup.  (*Note Software
+     Debug Messages and Tracing: softwaredebugmessagesandtracing.)
+
+   * You might need to override some defaults.  For example, you might
+     need to move, shrink, or back up the target's work area if your
+     application needs much SRAM.
+
+   * TCP/IP port configuration is another example of something which is
+     environment-specific, and should only appear in a user config file.
+     *Note TCP/IP Ports: tcpipports.
+
+5.5 Project-Specific Utilities
+==============================
+
+A few project-specific utility routines may well speed up your work.
+Write them, and keep them in your project's user config file.
+
+For example, if you are making a boot loader work on a board, it's nice
+to be able to debug the "after it's loaded to RAM" parts separately from
+the finicky early code which sets up the DDR RAM controller and clocks.
+A script like this one, or a more GDB-aware sibling, may help:
+
+     proc ramboot { } {
+         # Reset, running the target's "reset-init" scripts
+         # to initialize clocks and the DDR RAM controller.
+         # Leave the CPU halted.
+         reset init
+
+         # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
+         load_image u-boot.bin 0x20000000
+
+         # Start running.
+         resume 0x20000000
+     }
+
+Then once that code is working you will need to make it boot from NOR
+flash; a different utility would help.  Alternatively, some developers
+write to flash using GDB. (You might use a similar script if you're
+working with a flash based microcontroller application instead of a boot
+loader.)
+
+     proc newboot { } {
+         # Reset, leaving the CPU halted. The "reset-init" event
+         # proc gives faster access to the CPU and to NOR flash;
+         # "reset halt" would be slower.
+         reset init
+
+         # Write standard version of U-Boot into the first two
+         # sectors of NOR flash ... the standard version should
+         # do the same lowlevel init as "reset-init".
+         flash protect 0 0 1 off
+         flash erase_sector 0 0 1
+         flash write_bank 0 u-boot.bin 0x0
+         flash protect 0 0 1 on
+
+         # Reboot from scratch using that new boot loader.
+         reset run
+     }
+
+You may need more complicated utility procedures when booting from NAND.
+That often involves an extra bootloader stage, running from on-chip SRAM
+to perform DDR RAM setup so it can load the main bootloader code (which
+won't fit into that SRAM).
+
+Other helper scripts might be used to write production system images,
+involving considerably more than just a three stage bootloader.
+
+5.6 Target Software Changes
+===========================
+
+Sometimes you may want to make some small changes to the software you're
+developing, to help make JTAG debugging work better.  For example, in C
+or assembly language code you might use '#ifdef JTAG_DEBUG' (or its
+converse) around code handling issues like:
+
+   * Watchdog Timers...  Watchdog timers are typically used to
+     automatically reset systems if some application task doesn't
+     periodically reset the timer.  (The assumption is that the system
+     has locked up if the task can't run.)  When a JTAG debugger halts
+     the system, that task won't be able to run and reset the timer ...
+     potentially causing resets in the middle of your debug sessions.
+
+     It's rarely a good idea to disable such watchdogs, since their
+     usage needs to be debugged just like all other parts of your
+     firmware.  That might however be your only option.
+
+     Look instead for chip-specific ways to stop the watchdog from
+     counting while the system is in a debug halt state.  It may be
+     simplest to set that non-counting mode in your debugger startup
+     scripts.  You may however need a different approach when, for
+     example, a motor could be physically damaged by firmware remaining
+     inactive in a debug halt state.  That might involve a type of
+     firmware mode where that "non-counting" mode is disabled at the
+     beginning then re-enabled at the end; a watchdog reset might fire
+     and complicate the debug session, but hardware (or people) would be
+     protected.(1)
+
+   * ARM Semihosting...  When linked with a special runtime library
+     provided with many toolchains(2), your target code can use I/O
+     facilities on the debug host.  That library provides a small set of
+     system calls which are handled by OpenOCD. It can let the debugger
+     provide your system console and a file system, helping with early
+     debugging or providing a more capable environment for
+     sometimes-complex tasks like installing system firmware onto NAND
+     or SPI flash.
+
+   * ARM Wait-For-Interrupt...  Many ARM chips synchronize the JTAG
+     clock using the core clock.  Low power states which stop that core
+     clock thus prevent JTAG access.  Idle loops in tasking environments
+     often enter those low power states via the 'WFI' instruction (or
+     its coprocessor equivalent, before ARMv7).
+
+     You may want to _disable that instruction_ in source code, or
+     otherwise prevent using that state, to ensure you can get JTAG
+     access at any time.(3)  For example, the OpenOCD 'halt' command may
+     not work for an idle processor otherwise.
+
+   * Delay after reset...  Not all chips have good support for debugger
+     access right after reset; many LPC2xxx chips have issues here.
+     Similarly, applications that reconfigure pins used for JTAG access
+     as they start will also block debugger access.
+
+     To work with boards like this, _enable a short delay loop_ the
+     first thing after reset, before "real" startup activities.  For
+     example, one second's delay is usually more than enough time for a
+     JTAG debugger to attach, so that early code execution can be
+     debugged or firmware can be replaced.
+
+   * Debug Communications Channel (DCC)... Some processors include
+     mechanisms to send messages over JTAG. Many ARM cores support
+     these, as do some cores from other vendors.  (OpenOCD may be able
+     to use this DCC internally, speeding up some operations like
+     writing to memory.)
+
+     Your application may want to deliver various debugging messages
+     over JTAG, by _linking with a small library of code_ provided with
+     OpenOCD and using the utilities there to send various kinds of
+     message.  *Note Software Debug Messages and Tracing:
+     softwaredebugmessagesandtracing.
+
+5.7 Target Hardware Setup
+=========================
+
+Chip vendors often provide software development boards which are highly
+configurable, so that they can support all options that product boards
+may require.  _Make sure that any jumpers or switches match the system
+configuration you are working with._
+
+Common issues include:
+
+   * JTAG setup ...  Boards may support more than one JTAG
+     configuration.  Examples include jumpers controlling pullups versus
+     pulldowns on the nTRST and/or nSRST signals, and choice of
+     connectors (e.g.  which of two headers on the base board, or one
+     from a daughtercard).  For some Texas Instruments boards, you may
+     need to jumper the EMU0 and EMU1 signals (which OpenOCD won't
+     currently control).
+
+   * Boot Modes ...  Complex chips often support multiple boot modes,
+     controlled by external jumpers.  Make sure this is set up
+     correctly.  For example many i.MX boards from NXP need to be
+     jumpered to "ATX mode" to start booting using the on-chip ROM, when
+     using second stage bootloader code stored in a NAND flash chip.
+
+     Such explicit configuration is common, and not limited to booting
+     from NAND. You might also need to set jumpers to start booting
+     using code loaded from an MMC/SD card; external SPI flash;
+     Ethernet, UART, or USB links; NOR flash; OneNAND flash; some
+     external host; or various other sources.
+
+   * Memory Addressing ...  Boards which support multiple boot modes may
+     also have jumpers to configure memory addressing.  One board, for
+     example, jumpers external chipselect 0 (used for booting) to
+     address either a large SRAM (which must be pre-loaded via JTAG),
+     NOR flash, or NAND flash.  When it's jumpered to address NAND
+     flash, that board must also be told to start booting from on-chip
+     ROM.
+
+     Your 'board.cfg' file may also need to be told this jumper
+     configuration, so that it can know whether to declare NOR flash
+     using 'flash bank' or instead declare NAND flash with 'nand
+     device'; and likewise which probe to perform in its 'reset-init'
+     handler.
+
+     A closely related issue is bus width.  Jumpers might need to
+     distinguish between 8 bit or 16 bit bus access for the flash used
+     to start booting.
+
+   * Peripheral Access ...  Development boards generally provide access
+     to every peripheral on the chip, sometimes in multiple modes (such
+     as by providing multiple audio codec chips).  This interacts with
+     software configuration of pin multiplexing, where for example a
+     given pin may be routed either to the MMC/SD controller or the GPIO
+     controller.  It also often interacts with configuration jumpers.
+     One jumper may be used to route signals to an MMC/SD card slot or
+     an expansion bus (which might in turn affect booting); others might
+     control which audio or video codecs are used.
+
+Plus you should of course have 'reset-init' event handlers which set up
+the hardware to match that jumper configuration.  That includes in
+particular any oscillator or PLL used to clock the CPU, and any memory
+controllers needed to access external memory and peripherals.  Without
+such handlers, you won't be able to access those resources without
+working target firmware which can do that setup ...  this can be awkward
+when you're trying to debug that target firmware.  Even if there's a ROM
+bootloader which handles a few issues, it rarely provides full access to
+all board-specific capabilities.
+
+   ---------- Footnotes ----------
+
+   (1) Note that many systems support a "monitor mode" debug that is a
+somewhat cleaner way to address such issues.  You can think of it as
+only halting part of the system, maybe just one task, instead of the
+whole thing.  At this writing, January 2010, OpenOCD based debugging
+does not support monitor mode debug, only "halt mode" debug.
+
+   (2) See chapter 8 "Semihosting" in ARM DUI 0203I
+(http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf),
+the "RealView Compilation Tools Developer Guide".  The CodeSourcery EABI
+toolchain also includes a semihosting library.
+
+   (3) As a more polite alternative, some processors have special
+debug-oriented registers which can be used to change various features
+including how the low power states are clocked while debugging.  The
+STM32 DBGMCU_CR register is an example; at the cost of extra power
+consumption, JTAG can be used during low power states.
+
+
+File: openocd.info,  Node: Config File Guidelines,  Next: Server Configuration,  Prev: OpenOCD Project Setup,  Up: Top
+
+6 Config File Guidelines
+************************
+
+This chapter is aimed at any user who needs to write a config file,
+including developers and integrators of OpenOCD and any user who needs
+to get a new board working smoothly.  It provides guidelines for
+creating those files.
+
+You should find the following directories under $(INSTALLDIR)/scripts,
+with config files maintained upstream.  Use them as-is where you can; or
+as models for new files.
+   * 'interface' ...  These are for debug adapters.  Files that specify
+     configuration to use specific JTAG, SWD and other adapters go here.
+   * 'board' ...  Think Circuit Board, PWA, PCB, they go by many names.
+     Board files contain initialization items that are specific to a
+     board.
+
+     They reuse target configuration files, since the same
+     microprocessor chips are used on many boards, but support for
+     external parts varies widely.  For example, the SDRAM
+     initialization sequence for the board, or the type of external
+     flash and what address it uses.  Any initialization sequence to
+     enable that external flash or SDRAM should be found in the board
+     file.  Boards may also contain multiple targets: two CPUs; or a CPU
+     and an FPGA.
+   * 'target' ...  Think chip.  The "target" directory represents the
+     JTAG TAPs on a chip which OpenOCD should control, not a board.  Two
+     common types of targets are ARM chips and FPGA or CPLD chips.  When
+     a chip has multiple TAPs (maybe it has both ARM and DSP cores), the
+     target config file defines all of them.
+   * _more_ ...  browse for other library files which may be useful.
+     For example, there are various generic and CPU-specific utilities.
+
+The 'openocd.cfg' user config file may override features in any of the
+above files by setting variables before sourcing the target file, or by
+adding commands specific to their situation.
+
+6.1 Interface Config Files
+==========================
+
+The user config file should be able to source one of these files with a
+command like this:
+
+     source [find interface/FOOBAR.cfg]
+
+A preconfigured interface file should exist for every debug adapter in
+use today with OpenOCD. That said, perhaps some of these config files
+have only been used by the developer who created it.
+
+A separate chapter gives information about how to set these up.  *Note
+Debug Adapter Configuration::.  Read the OpenOCD source code (and
+Developer's Guide) if you have a new kind of hardware interface and need
+to provide a driver for it.
+
+ -- Command: find 'filename'
+     Prints full path to FILENAME according to OpenOCD search rules.
+
+ -- Command: ocd_find 'filename'
+     Prints full path to FILENAME according to OpenOCD search rules.
+     This is a low level function used by the 'find'.  Usually you want
+     to use 'find', instead.
+
+6.2 Board Config Files
+======================
+
+The user config file should be able to source one of these files with a
+command like this:
+
+     source [find board/FOOBAR.cfg]
+
+The point of a board config file is to package everything about a given
+board that user config files need to know.  In summary the board files
+should contain (if present)
+
+  1. One or more 'source [find target/...cfg]' statements
+  2. NOR flash configuration (*note NOR Configuration:
+     norconfiguration.)
+  3. NAND flash configuration (*note NAND Configuration:
+     nandconfiguration.)
+  4. Target 'reset' handlers for SDRAM and I/O configuration
+  5. JTAG adapter reset configuration (*note Reset Configuration::)
+  6. All things that are not "inside a chip"
+
+Generic things inside target chips belong in target config files, not
+board config files.  So for example a 'reset-init' event handler should
+know board-specific oscillator and PLL parameters, which it passes to
+target-specific utility code.
+
+The most complex task of a board config file is creating such a
+'reset-init' event handler.  Define those handlers last, after you
+verify the rest of the board configuration works.
+
+6.2.1 Communication Between Config files
+----------------------------------------
+
+In addition to target-specific utility code, another way that board and
+target config files communicate is by following a convention on how to
+use certain variables.
+
+The full Tcl/Tk language supports "namespaces", but Jim-Tcl does not.
+Thus the rule we follow in OpenOCD is this: Variables that begin with a
+leading underscore are temporary in nature, and can be modified and used
+at will within a target configuration file.
+
+Complex board config files can do the things like this, for a board with
+three chips:
+
+     # Chip #1: PXA270 for network side, big endian
+     set CHIPNAME network
+     set ENDIAN big
+     source [find target/pxa270.cfg]
+     # on return: _TARGETNAME = network.cpu
+     # other commands can refer to the "network.cpu" target.
+     $_TARGETNAME configure .... events for this CPU..
+
+     # Chip #2: PXA270 for video side, little endian
+     set CHIPNAME video
+     set ENDIAN little
+     source [find target/pxa270.cfg]
+     # on return: _TARGETNAME = video.cpu
+     # other commands can refer to the "video.cpu" target.
+     $_TARGETNAME configure .... events for this CPU..
+
+     # Chip #3: Xilinx FPGA for glue logic
+     set CHIPNAME xilinx
+     unset ENDIAN
+     source [find target/spartan3.cfg]
+
+That example is oversimplified because it doesn't show any flash memory,
+or the 'reset-init' event handlers to initialize external DRAM or
+(assuming it needs it) load a configuration into the FPGA. Such features
+are usually needed for low-level work with many boards, where "low
+level" implies that the board initialization software may not be
+working.  (That's a common reason to need JTAG tools.  Another is to
+enable working with microcontroller-based systems, which often have no
+debugging support except a JTAG connector.)
+
+Target config files may also export utility functions to board and user
+config files.  Such functions should use name prefixes, to help avoid
+naming collisions.
+
+Board files could also accept input variables from user config files.
+For example, there might be a 'J4_JUMPER' setting used to identify what
+kind of flash memory a development board is using, or how to set up
+other clocks and peripherals.
+
+6.2.2 Variable Naming Convention
+--------------------------------
+
+Most boards have only one instance of a chip.  However, it should be
+easy to create a board with more than one such chip (as shown above).
+Accordingly, we encourage these conventions for naming variables
+associated with different 'target.cfg' files, to promote consistency and
+so that board files can override target defaults.
+
+Inputs to target config files include:
+
+   * 'CHIPNAME' ...  This gives a name to the overall chip, and is used
+     as part of tap identifier dotted names.  While the default is
+     normally provided by the chip manufacturer, board files may need to
+     distinguish between instances of a chip.
+   * 'ENDIAN' ...  By default 'little' - although chips may hard-wire
+     'big'.  Chips that can't change endianness don't need to use this
+     variable.
+   * 'CPUTAPID' ...  When OpenOCD examines the JTAG chain, it can be
+     told verify the chips against the JTAG IDCODE register.  The target
+     file will hold one or more defaults, but sometimes the chip in a
+     board will use a different ID (perhaps a newer revision).
+
+Outputs from target config files include:
+
+   * '_TARGETNAME' ...  By convention, this variable is created by the
+     target configuration script.  The board configuration file may make
+     use of this variable to configure things like a "reset init"
+     script, or other things specific to that board and that target.  If
+     the chip has 2 targets, the names are '_TARGETNAME0',
+     '_TARGETNAME1', ...  etc.
+
+6.2.3 The reset-init Event Handler
+----------------------------------
+
+Board config files run in the OpenOCD configuration stage; they can't
+use TAPs or targets, since they haven't been fully set up yet.  This
+means you can't write memory or access chip registers; you can't even
+verify that a flash chip is present.  That's done later in event
+handlers, of which the target 'reset-init' handler is one of the most
+important.
+
+Except on microcontrollers, the basic job of 'reset-init' event handlers
+is setting up flash and DRAM, as normally handled by boot loaders.
+Microcontrollers rarely use boot loaders; they run right out of their
+on-chip flash and SRAM memory.  But they may want to use one of these
+handlers too, if just for developer convenience.
+
+     Note: Because this is so very board-specific, and chip-specific, no
+     examples are included here.  Instead, look at the board config
+     files distributed with OpenOCD. If you have a boot loader, its
+     source code will help; so will configuration files for other JTAG
+     tools (*note Translating Configuration Files:
+     translatingconfigurationfiles.).
+
+Some of this code could probably be shared between different boards.
+For example, setting up a DRAM controller often doesn't differ by much
+except the bus width (16 bits or 32?)  and memory timings, so a reusable
+TCL procedure loaded by the 'target.cfg' file might take those as
+parameters.  Similarly with oscillator, PLL, and clock setup; and
+disabling the watchdog.  Structure the code cleanly, and provide
+comments to help the next developer doing such work.  (_You might be
+that next person_ trying to reuse init code!)
+
+The last thing normally done in a 'reset-init' handler is probing
+whatever flash memory was configured.  For most chips that needs to be
+done while the associated target is halted, either because JTAG memory
+access uses the CPU or to prevent conflicting CPU access.
+
+6.2.4 JTAG Clock Rate
+---------------------
+
+Before your 'reset-init' handler has set up the PLLs and clocking, you
+may need to run with a low JTAG clock rate.  *Note JTAG Speed:
+jtagspeed.  Then you'd increase that rate after your handler has made it
+possible to use the faster JTAG clock.  When the initial low speed is
+board-specific, for example because it depends on a board-specific
+oscillator speed, then you should probably set it up in the board config
+file; if it's target-specific, it belongs in the target config file.
+
+For most ARM-based processors the fastest JTAG clock(1) is one sixth of
+the CPU clock; or one eighth for ARM11 cores.  Consult chip
+documentation to determine the peak JTAG clock rate, which might be less
+than that.
+
+     Warning: On most ARMs, JTAG clock detection is coupled to the core
+     clock, so software using a 'wait for interrupt' operation blocks
+     JTAG access.  Adaptive clocking provides a partial workaround, but
+     a more complete solution just avoids using that instruction with
+     JTAG debuggers.
+
+If both the chip and the board support adaptive clocking, use the
+'jtag_rclk' command, in case your board is used with JTAG adapter which
+also supports it.  Otherwise use 'adapter speed'.  Set the slow rate at
+the beginning of the reset sequence, and the faster rate as soon as the
+clocks are at full speed.
+
+6.2.5 The init_board procedure
+------------------------------
+
+The concept of 'init_board' procedure is very similar to 'init_targets'
+(*Note The init_targets procedure: theinittargetsprocedure.)  - it's a
+replacement of "linear" configuration scripts.  This procedure is meant
+to be executed when OpenOCD enters run stage (*Note Entering the Run
+Stage: enteringtherunstage,) after 'init_targets'.  The idea to have
+separate 'init_targets' and 'init_board' procedures is to allow the
+first one to configure everything target specific (internal flash,
+internal RAM, etc.)  and the second one to configure everything board
+specific (reset signals, chip frequency, reset-init event handler,
+external memory, etc.).  Additionally "linear" board config file will
+most likely fail when target config file uses 'init_targets' scheme
+("linear" script is executed before 'init' and 'init_targets' - after),
+so separating these two configuration stages is very convenient, as the
+easiest way to overcome this problem is to convert board config file to
+use 'init_board' procedure.  Board config scripts don't need to override
+'init_targets' defined in target config files when they only need to add
+some specifics.
+
+Just as 'init_targets', the 'init_board' procedure can be overridden by
+"next level" script (which sources the original), allowing greater code
+reuse.
+
+     ### board_file.cfg ###
+
+     # source target file that does most of the config in init_targets
+     source [find target/target.cfg]
+
+     proc enable_fast_clock {} {
+         # enables fast on-board clock source
+         # configures the chip to use it
+     }
+
+     # initialize only board specifics - reset, clock, adapter frequency
+     proc init_board {} {
+         reset_config trst_and_srst trst_pulls_srst
+
+         $_TARGETNAME configure -event reset-start {
+             adapter speed 100
+         }
+
+         $_TARGETNAME configure -event reset-init {
+             enable_fast_clock
+             adapter speed 10000
+         }
+     }
+
+6.3 Target Config Files
+=======================
+
+Board config files communicate with target config files using naming
+conventions as described above, and may source one or more target config
+files like this:
+
+     source [find target/FOOBAR.cfg]
+
+The point of a target config file is to package everything about a given
+chip that board config files need to know.  In summary the target files
+should contain
+
+  1. Set defaults
+  2. Add TAPs to the scan chain
+  3. Add CPU targets (includes GDB support)
+  4. CPU/Chip/CPU-Core specific features
+  5. On-Chip flash
+
+As a rule of thumb, a target file sets up only one chip.  For a
+microcontroller, that will often include a single TAP, which is a CPU
+needing a GDB target, and its on-chip flash.
+
+More complex chips may include multiple TAPs, and the target config file
+may need to define them all before OpenOCD can talk to the chip.  For
+example, some phone chips have JTAG scan chains that include an ARM core
+for operating system use, a DSP, another ARM core embedded in an image
+processing engine, and other processing engines.
+
+6.3.1 Default Value Boiler Plate Code
+-------------------------------------
+
+All target configuration files should start with code like this, letting
+board config files express environment-specific differences in how
+things should be set up.
+
+     # Boards may override chip names, perhaps based on role,
+     # but the default should match what the vendor uses
+     if { [info exists CHIPNAME] } {
+        set  _CHIPNAME $CHIPNAME
+     } else {
+        set  _CHIPNAME sam7x256
+     }
+
+     # ONLY use ENDIAN with targets that can change it.
+     if { [info exists ENDIAN] } {
+        set  _ENDIAN $ENDIAN
+     } else {
+        set  _ENDIAN little
+     }
+
+     # TAP identifiers may change as chips mature, for example with
+     # new revision fields (the "3" here). Pick a good default; you
+     # can pass several such identifiers to the "jtag newtap" command.
+     if { [info exists CPUTAPID ] } {
+        set _CPUTAPID $CPUTAPID
+     } else {
+        set _CPUTAPID 0x3f0f0f0f
+     }
+
+_Remember:_ Board config files may include multiple target config files,
+or the same target file multiple times (changing at least 'CHIPNAME').
+
+Likewise, the target configuration file should define '_TARGETNAME' (or
+'_TARGETNAME0' etc) and use it later on when defining debug targets:
+
+     set _TARGETNAME $_CHIPNAME.cpu
+     target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
+
+6.3.2 Adding TAPs to the Scan Chain
+-----------------------------------
+
+After the "defaults" are set up, add the TAPs on each chip to the JTAG
+scan chain.  *Note TAP Declaration::, and the naming convention for
+taps.
+
+In the simplest case the chip has only one TAP, probably for a CPU or
+FPGA. The config file for the Atmel AT91SAM7X256 looks (in part) like
+this:
+
+     jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+A board with two such at91sam7 chips would be able to source such a
+config file twice, with different values for 'CHIPNAME', so it adds a
+different TAP each time.
+
+If there are nonzero '-expected-id' values, OpenOCD attempts to verify
+the actual tap id against those values.  It will issue error messages if
+there is mismatch, which can help to pinpoint problems in OpenOCD
+configurations.
+
+     JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
+                     (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+     ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
+     ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
+     ERROR:      got: mfg: 0x787, part: 0xf0f0, ver: 0x3
+
+There are more complex examples too, with chips that have multiple TAPs.
+Ones worth looking at include:
+
+   * 'target/omap3530.cfg' - with disabled ARM and DSP, plus a JRC to
+     enable them
+   * 'target/str912.cfg' - with flash, CPU, and boundary scan
+   * 'target/ti_dm355.cfg' - with ETM, ARM, and JRC (this JRC is not
+     currently used)
+
+6.3.3 Add CPU targets
+---------------------
+
+After adding a TAP for a CPU, you should set it up so that GDB and other
+commands can use it.  *Note CPU Configuration::.  For the at91sam7
+example above, the command can look like this; note that '$_ENDIAN' is
+not needed, since OpenOCD defaults to little endian, and this chip
+doesn't support changing that.
+
+     set _TARGETNAME $_CHIPNAME.cpu
+     target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
+
+Work areas are small RAM areas associated with CPU targets.  They are
+used by OpenOCD to speed up downloads, and to download small snippets of
+code to program flash chips.  If the chip includes a form of
+"on-chip-ram" - and many do - define a work area if you can.  Again
+using the at91sam7 as an example, this can look like:
+
+     $_TARGETNAME configure -work-area-phys 0x00200000 \
+                  -work-area-size 0x4000 -work-area-backup 0
+
+6.3.4 Define CPU targets working in SMP
+---------------------------------------
+
+After setting targets, you can define a list of targets working in SMP.
+
+     set _TARGETNAME_1 $_CHIPNAME.cpu1
+     set _TARGETNAME_2 $_CHIPNAME.cpu2
+     target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
+     -coreid 0 -dbgbase $_DAP_DBG1
+     target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
+     -coreid 1 -dbgbase $_DAP_DBG2
+     #define 2 targets working in smp.
+     target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
+In the above example on cortex_a, 2 cpus are working in SMP. In SMP only
+one GDB instance is created and :
+   * a set of hardware breakpoint sets the same breakpoint on all
+     targets in the list.
+   * halt command triggers the halt of all targets in the list.
+   * resume command triggers the write context and the restart of all
+     targets in the list.
+   * following a breakpoint: the target stopped by the breakpoint is
+     displayed to the GDB session.
+   * dedicated GDB serial protocol packets are implemented for
+     switching/retrieving the target displayed by the GDB session *note
+     Using OpenOCD SMP with GDB: usingopenocdsmpwithgdb.
+
+The SMP behaviour can be disabled/enabled dynamically.  On cortex_a
+following command have been implemented.
+   * cortex_a smp on : enable SMP mode, behaviour is as described above.
+   * cortex_a smp off : disable SMP mode, the current target is the one
+     displayed in the GDB session, only this target is now controlled by
+     GDB session.  This behaviour is useful during system boot up.
+   * cortex_a smp : display current SMP mode.
+   * cortex_a smp_gdb : display/fix the core id displayed in GDB session
+     see following example.
+
+     >cortex_a smp_gdb
+     gdb coreid  0 -> -1
+     #0 : coreid 0 is displayed to GDB ,
+     #-> -1 : next resume triggers a real resume
+     > cortex_a smp_gdb 1
+     gdb coreid  0 -> 1
+     #0 :coreid 0 is displayed to GDB ,
+     #->1  : next resume displays coreid 1 to GDB
+     > resume
+     > cortex_a smp_gdb
+     gdb coreid  1 -> 1
+     #1 :coreid 1 is displayed to GDB ,
+     #->1 : next resume displays coreid 1 to GDB
+     > cortex_a smp_gdb -1
+     gdb coreid  1 -> -1
+     #1 :coreid 1 is displayed to GDB,
+     #->-1 : next resume triggers a real resume
+
+6.3.5 Chip Reset Setup
+----------------------
+
+As a rule, you should put the 'reset_config' command into the board
+file.  Most things you think you know about a chip can be tweaked by the
+board.
+
+Some chips have specific ways the TRST and SRST signals are managed.  In
+the unusual case that these are _chip specific_ and can never be changed
+by board wiring, they could go here.  For example, some chips can't
+support JTAG debugging without both signals.
+
+Provide a 'reset-assert' event handler if you can.  Such a handler uses
+JTAG operations to reset the target, letting this target config be used
+in systems which don't provide the optional SRST signal, or on systems
+where you don't want to reset all targets at once.  Such a handler might
+write to chip registers to force a reset, use a JRC to do that
+(preferable - the target may be wedged!), or force a watchdog timer to
+trigger.  (For Cortex-M targets, this is not necessary.  The target
+driver knows how to use trigger an NVIC reset when SRST is not
+available.)
+
+Some chips need special attention during reset handling if they're going
+to be used with JTAG. An example might be needing to send some commands
+right after the target's TAP has been reset, providing a
+'reset-deassert-post' event handler that writes a chip register to
+report that JTAG debugging is being done.  Another would be
+reconfiguring the watchdog so that it stops counting while the core is
+halted in the debugger.
+
+JTAG clocking constraints often change during reset, and in some cases
+target config files (rather than board config files) are the right
+places to handle some of those issues.  For example, immediately after
+reset most chips run using a slower clock than they will use later.
+That means that after reset (and potentially, as OpenOCD first starts
+up) they must use a slower JTAG clock rate than they will use later.
+*Note JTAG Speed: jtagspeed.
+
+     Important: When you are debugging code that runs right after chip
+     reset, getting these issues right is critical.  In particular, if
+     you see intermittent failures when OpenOCD verifies the scan chain
+     after reset, look at how you are setting up JTAG clocking.
+
+6.3.6 The init_targets procedure
+--------------------------------
+
+Target config files can either be "linear" (script executed line-by-line
+when parsed in configuration stage, *Note Configuration Stage:
+configurationstage,) or they can contain a special procedure called
+'init_targets', which will be executed when entering run stage (after
+parsing all config files or after 'init' command, *Note Entering the Run
+Stage: enteringtherunstage.)  Such procedure can be overridden by "next
+level" script (which sources the original).  This concept facilitates
+code reuse when basic target config files provide generic configuration
+procedures and 'init_targets' procedure, which can then be sourced and
+enhanced or changed in a "more specific" target config file.  This is
+not possible with "linear" config scripts, because sourcing them
+executes every initialization commands they provide.
+
+     ### generic_file.cfg ###
+
+     proc setup_my_chip {chip_name flash_size ram_size} {
+         # basic initialization procedure ...
+     }
+
+     proc init_targets {} {
+         # initializes generic chip with 4kB of flash and 1kB of RAM
+         setup_my_chip MY_GENERIC_CHIP 4096 1024
+     }
+
+     ### specific_file.cfg ###
+
+     source [find target/generic_file.cfg]
+
+     proc init_targets {} {
+         # initializes specific chip with 128kB of flash and 64kB of RAM
+         setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
+     }
+
+The easiest way to convert "linear" config files to 'init_targets'
+version is to enclose every line of "code" (i.e.  not 'source' commands,
+procedures, etc.)  in this procedure.
+
+For an example of this scheme see LPC2000 target config files.
+
+The 'init_boards' procedure is a similar concept concerning board config
+files (*Note The init_board procedure: theinitboardprocedure.)
+
+6.3.7 The init_target_events procedure
+--------------------------------------
+
+A special procedure called 'init_target_events' is run just after
+'init_targets' (*Note The init_targets procedure:
+theinittargetsprocedure.)  and before 'init_board' (*Note The init_board
+procedure: theinitboardprocedure.)  It is used to set up default target
+events for the targets that do not have those events already assigned.
+
+6.3.8 ARM Core Specific Hacks
+-----------------------------
+
+If the chip has a DCC, enable it.  If the chip is an ARM9 with some
+special high speed download features - enable it.
+
+If present, the MMU, the MPU and the CACHE should be disabled.
+
+Some ARM cores are equipped with trace support, which permits
+examination of the instruction and data bus activity.  Trace activity is
+controlled through an "Embedded Trace Module" (ETM) on one of the core's
+scan chains.  The ETM emits voluminous data through a "trace port".
+(*Note ARM Hardware Tracing: armhardwaretracing.)  If you are using an
+external trace port, configure it in your board config file.  If you are
+using an on-chip "Embedded Trace Buffer" (ETB), configure it in your
+target config file.
+
+     etm config $_TARGETNAME 16 normal full etb
+     etb config $_TARGETNAME $_CHIPNAME.etb
+
+6.3.9 Internal Flash Configuration
+----------------------------------
+
+This applies ONLY TO MICROCONTROLLERS that have flash built in.
+
+Never ever in the "target configuration file" define any type of flash
+that is external to the chip.  (For example a BOOT flash on Chip Select
+0.)  Such flash information goes in a board file - not the TARGET (chip)
+file.
+
+Examples:
+   * at91sam7x256 - has 256K flash YES enable it.
+   * str912 - has flash internal YES enable it.
+   * imx27 - uses boot flash on CS0 - it goes in the board file.
+   * pxa270 - again - CS0 flash - it goes in the board file.
+
+6.4 Translating Configuration Files
+===================================
+
+If you have a configuration file for another hardware debugger or
+toolset (Abatron, BDI2000, BDI3000, CCS, Lauterbach, SEGGER, Macraigor,
+etc.), translating it into OpenOCD syntax is often quite
+straightforward.  The most tricky part of creating a configuration
+script is oftentimes the reset init sequence where e.g.  PLLs, DRAM and
+the like is set up.
+
+One trick that you can use when translating is to write small Tcl
+procedures to translate the syntax into OpenOCD syntax.  This can avoid
+manual translation errors and make it easier to convert other scripts
+later on.
+
+Example of transforming quirky arguments to a simple search and replace
+job:
+
+     #   Lauterbach syntax(?)
+     #
+     #       Data.Set c15:0x042f %long 0x40000015
+     #
+     #   OpenOCD syntax when using procedure below.
+     #
+     #       setc15 0x01 0x00050078
+
+     proc setc15 {regs value} {
+         global TARGETNAME
+
+         echo [format "set p15 0x%04x, 0x%08x" $regs $value]
+
+         arm mcr 15 [expr {($regs >> 12) & 0x7}] \
+             [expr {($regs >> 0) & 0xf}] [expr {($regs >> 4) & 0xf}] \
+             [expr {($regs >> 8) & 0x7}] $value
+     }
+
+   ---------- Footnotes ----------
+
+   (1) A FAQ  gives
+details.
+
+
+File: openocd.info,  Node: Server Configuration,  Next: Debug Adapter Configuration,  Prev: Config File Guidelines,  Up: Top
+
+7 Server Configuration
+**********************
+
+The commands here are commonly found in the openocd.cfg file and are
+used to specify what TCP/IP ports are used, and how GDB should be
+supported.
+
+7.1 Configuration Stage
+=======================
+
+When the OpenOCD server process starts up, it enters a _configuration
+stage_ which is the only time that certain commands, _configuration
+commands_, may be issued.  Normally, configuration commands are only
+available inside startup scripts.
+
+In this manual, the definition of a configuration command is presented
+as a _Config Command_, not as a _Command_ which may be issued
+interactively.  The runtime 'help' command also highlights configuration
+commands, and those which may be issued at any time.
+
+Those configuration commands include declaration of TAPs, flash banks,
+the interface used for JTAG communication, and other basic setup.  The
+server must leave the configuration stage before it may access or
+activate TAPs.  After it leaves this stage, configuration commands may
+no longer be issued.
+
+ -- Command: command mode [command_name]
+     Returns the command modes allowed by a command: 'any', 'config', or
+     'exec'.  If no command is specified, returns the current command
+     mode.  Returns 'unknown' if an unknown command is given.  Command
+     can be multiple tokens.  (command valid any time)
+
+     In this document, the modes are described as stages, 'config' and
+     'exec' mode correspond configuration stage and run stage.  'any'
+     means the command can be executed in either stages.  *Note
+     Configuration Stage: configurationstage, and *Note Entering the Run
+     Stage: enteringtherunstage.
+
+7.2 Entering the Run Stage
+==========================
+
+The first thing OpenOCD does after leaving the configuration stage is to
+verify that it can talk to the scan chain (list of TAPs) which has been
+configured.  It will warn if it doesn't find TAPs it expects to find, or
+finds TAPs that aren't supposed to be there.  You should see no errors
+at this point.  If you see errors, resolve them by correcting the
+commands you used to configure the server.  Common errors include using
+an initial JTAG speed that's too fast, and not providing the right
+IDCODE values for the TAPs on the scan chain.
+
+Once OpenOCD has entered the run stage, a number of commands become
+available.  A number of these relate to the debug targets you may have
+declared.  For example, the 'mww' command will not be available until a
+target has been successfully instantiated.  If you want to use those
+commands, you may need to force entry to the run stage.
+
+ -- Config Command: init
+     This command terminates the configuration stage and enters the run
+     stage.  This helps when you need to have the startup scripts manage
+     tasks such as resetting the target, programming flash, etc.  To
+     reset the CPU upon startup, add "init" and "reset" at the end of
+     the config script or at the end of the OpenOCD command line using
+     the '-c' command line switch.
+
+     If this command does not appear in any startup/configuration file
+     OpenOCD executes the command for you after processing all
+     configuration files and/or command line options.
+
+     NOTE: This command normally occurs near the end of your openocd.cfg
+     file to force OpenOCD to "initialize" and make the targets ready.
+     For example: If your openocd.cfg file needs to read/write memory on
+     your target, 'init' must occur before the memory read/write
+     commands.  This includes 'nand probe'.
+
+     'init' calls the following internal OpenOCD commands to initialize
+     corresponding subsystems:
+      -- Config Command: target init
+      -- Command: transport init
+      -- Command: dap init
+      -- Config Command: flash init
+      -- Config Command: nand init
+      -- Config Command: pld init
+      -- Command: tpiu init
+
+     At last, 'init' executes all the commands that are specified in the
+     TCL list POST_INIT_COMMANDS.  The commands are executed in the same
+     order they occupy in the list.  If one of the commands fails, then
+     the error is propagated and OpenOCD fails too.
+          lappend post_init_commands {echo "OpenOCD successfully initialized."}
+          lappend post_init_commands {echo "Have fun with OpenOCD !"}
+
+ -- Config Command: noinit
+     Prevent OpenOCD from implicit 'init' call at the end of startup.
+     Allows issuing configuration commands over telnet or Tcl
+     connection.  When you are done with configuration use 'init' to
+     enter the run stage.
+
+ -- Overridable Procedure: jtag_init
+     This is invoked at server startup to verify that it can talk to the
+     scan chain (list of TAPs) which has been configured.
+
+     The default implementation first tries 'jtag arp_init', which uses
+     only a lightweight JTAG reset before examining the scan chain.  If
+     that fails, it tries again, using a harder reset from the
+     overridable procedure 'init_reset'.
+
+     Implementations must have verified the JTAG scan chain before they
+     return.  This is done by calling 'jtag arp_init' (or 'jtag
+     arp_init-reset').
+
+7.3 TCP/IP Ports
+================
+
+The OpenOCD server accepts remote commands in several syntaxes.  Each
+syntax uses a different TCP/IP port, which you may specify only during
+configuration (before those ports are opened).
+
+For reasons including security, you may wish to prevent remote access
+using one or more of these ports.  In such cases, just specify the
+relevant port number as "disabled".
+
+You can request the operating system to select one of the available
+ports for the server by specifying the relevant port number as "0".
+
+ -- Config Command: gdb port [number]
+     Normally gdb listens to a TCP/IP port, but GDB can also communicate
+     via pipes(stdin/out or named pipes).  The name "gdb port" stuck
+     because it covers probably more than 90% of the normal use cases.
+
+     No arguments reports GDB port.  "pipe" means listen to stdin output
+     to stdout, an integer is base port number, "disabled" disables the
+     gdb server.
+
+     When using "pipe", also use log_output to redirect the log output
+     to a file so as not to flood the stdin/out pipes.
+
+     The -p/-pipe option is deprecated and a warning is printed as it is
+     equivalent to passing in -c "gdb_port pipe; log_output
+     openocd.log".
+
+     Any other string is interpreted as named pipe to listen to.  Output
+     pipe is the same name as input pipe, but with 'o' appended, e.g.
+     /var/gdb, /var/gdbo.
+
+     The GDB port for the first target will be the base port, the second
+     target will listen on port + 1, and so on.  When not specified
+     during the configuration stage, the port NUMBER defaults to 3333.
+     When NUMBER is not a numeric value, incrementing it to compute the
+     next port number does not work.  In this case, specify the proper
+     NUMBER for each target by using the option '-gdb-port' of the
+     commands 'target create' or '$target_name configure'.  *Note option
+     -gdb-port: gdbportoverride.
+
+     Note: when using "gdb port pipe", increasing the default remote
+     timeout in gdb (with 'set remotetimeout') is recommended.  An
+     insufficient timeout may cause initialization to fail with "Unknown
+     remote qXfer reply: OK".
+
+ -- Config Command: tcl port [number]
+     Specify or query the port used for a simplified RPC connection that
+     can be used by clients to issue TCL commands and get the output
+     from the Tcl engine.  Intended as a machine interface.  When not
+     specified during the configuration stage, the port NUMBER defaults
+     to 6666.  When specified as "disabled", this service is not
+     activated.
+
+ -- Config Command: telnet port [number]
+     Specify or query the port on which to listen for incoming telnet
+     connections.  This port is intended for interaction with one human
+     through TCL commands.  When not specified during the configuration
+     stage, the port NUMBER defaults to 4444.  When specified as
+     "disabled", this service is not activated.
+
+7.4 GDB Configuration
+=====================
+
+You can reconfigure some GDB behaviors if needed.  The ones listed here
+are static and global.  *Note Target Configuration: targetconfiguration,
+about configuring individual targets.  *Note Target Events:
+targetevents, about configuring target-specific event handling.
+
+ -- Command: gdb breakpoint_override ['hard'|'soft'|'disable']
+     Force breakpoint type for gdb 'break' commands.  This option
+     supports GDB GUIs which don't distinguish hard versus soft
+     breakpoints, if the default OpenOCD and GDB behaviour is not
+     sufficient.  GDB normally uses hardware breakpoints if the memory
+     map has been set up for flash regions.
+
+ -- Config Command: gdb flash_program ('enable'|'disable')
+     Set to 'enable' to cause OpenOCD to program the flash memory when a
+     vFlash packet is received.  The default behaviour is 'enable'.
+
+ -- Config Command: gdb memory_map ('enable'|'disable')
+     Set to 'enable' to cause OpenOCD to send the memory configuration
+     to GDB when requested.  GDB will then know when to set hardware
+     breakpoints, and program flash using the GDB load command.  'gdb
+     flash_program enable' must also be enabled for flash programming to
+     work.  Default behaviour is 'enable'.  *Note gdb flash_program:
+     gdbflashprogram.
+
+ -- Config Command: gdb report_data_abort ('enable'|'disable')
+     Specifies whether data aborts cause an error to be reported by GDB
+     memory read packets.  The default behaviour is 'disable'; use
+     'enable' see these errors reported.
+
+ -- Config Command: gdb report_register_access_error
+          ('enable'|'disable')
+     Specifies whether register accesses requested by GDB register
+     read/write packets report errors or not.  The default behaviour is
+     'disable'; use 'enable' see these errors reported.
+
+ -- Config Command: gdb target_description ('enable'|'disable')
+     Set to 'enable' to cause OpenOCD to send the target descriptions to
+     gdb via qXfer:features:read packet.  The default behaviour is
+     'enable'.
+
+ -- Command: gdb save_tdesc
+     Saves the target description file to the local file system.
+
+     The file name is target_name.xml.
+
+7.5 Event Polling
+=================
+
+Hardware debuggers are parts of asynchronous systems, where significant
+events can happen at any time.  The OpenOCD server needs to detect some
+of these events, so it can report them to through TCL command line or to
+GDB.
+
+Examples of such events include:
+
+   * One of the targets can stop running ...  maybe it triggers a code
+     breakpoint or data watchpoint, or halts itself.
+   * Messages may be sent over "debug message" channels ...  many
+     targets support such messages sent over JTAG, for receipt by the
+     person debugging or tools.
+   * Loss of power ...  some adapters can detect these events.
+   * Resets not issued through JTAG ...  such reset sources can include
+     button presses or other system hardware, sometimes including the
+     target itself (perhaps through a watchdog).
+   * Debug instrumentation sometimes supports event triggering such as
+     "trace buffer full" (so it can quickly be emptied) or other signals
+     (to correlate with code behavior).
+
+None of those events are signaled through standard JTAG signals.
+However, most conventions for JTAG connectors include voltage level and
+system reset (SRST) signal detection.  Some connectors also include
+instrumentation signals, which can imply events when those signals are
+inputs.
+
+In general, OpenOCD needs to periodically check for those events, either
+by looking at the status of signals on the JTAG connector or by sending
+synchronous "tell me your status" JTAG requests to the various active
+targets.  There is a command to manage and monitor that polling, which
+is normally done in the background.
+
+ -- Command: poll ['on'|'off']
+     Poll the current target for its current state.  (Also, *note target
+     curstate: targetcurstate.)  If that target is in debug mode,
+     architecture specific information about the current state is
+     printed.  An optional parameter allows background polling to be
+     enabled and disabled.
+
+     You could use this from the TCL command shell, or from GDB using
+     'monitor poll' command.  Leave background polling enabled while
+     you're using GDB.
+          > poll
+          background polling: on
+          target state: halted
+          target halted in ARM state due to debug-request, \
+                         current mode: Supervisor
+          cpsr: 0x800000d3 pc: 0x11081bfc
+          MMU: disabled, D-Cache: disabled, I-Cache: enabled
+          >
+
+
+File: openocd.info,  Node: Debug Adapter Configuration,  Next: Reset Configuration,  Prev: Server Configuration,  Up: Top
+
+8 Debug Adapter Configuration
+*****************************
+
+Correctly installing OpenOCD includes making your operating system give
+OpenOCD access to debug adapters.  Once that has been done, Tcl commands
+are used to select which one is used, and to configure how it is used.
+
+     Note: Because OpenOCD started out with a focus purely on JTAG, you
+     may find places where it wrongly presumes JTAG is the only
+     transport protocol in use.  Be aware that recent versions of
+     OpenOCD are removing that limitation.  JTAG remains more functional
+     than most other transports.  Other transports do not support
+     boundary scan operations, or may be specific to a given chip
+     vendor.  Some might be usable only for programming flash memory,
+     instead of also for debugging.
+
+Debug Adapters/Interfaces/Dongles are normally configured through
+commands in an interface configuration file which is sourced by your
+'openocd.cfg' file, or through a command line '-f interface/....cfg'
+option.
+
+     source [find interface/olimex-jtag-tiny.cfg]
+
+These commands tell OpenOCD what type of JTAG adapter you have, and how
+to talk to it.  A few cases are so simple that you only need to say what
+driver to use:
+
+     # jlink interface
+     adapter driver jlink
+
+Most adapters need a bit more configuration than that.
+
+8.1 Adapter Configuration
+=========================
+
+The 'adapter driver' command tells OpenOCD what type of debug adapter
+you are using.  Depending on the type of adapter, you may need to use
+one or more additional commands to further identify or configure the
+adapter.
+
+ -- Config Command: adapter driver name
+     Use the adapter driver NAME to connect to the target.
+
+ -- Command: adapter list
+     List the debug adapter drivers that have been built into the
+     running copy of OpenOCD.
+ -- Config Command: adapter transports transport_name+
+     Specifies the transports supported by this debug adapter.  The
+     adapter driver builds-in similar knowledge; use this only when
+     external configuration (such as jumpering) changes what the
+     hardware can support.
+
+ -- Config Command: adapter gpio [ 'tdo' | 'tdi' | 'tms' | 'tck' |
+          'trst' | 'swdio' | 'swdio_dir' | 'swclk' | 'srst' | 'led' [
+          gpio_number | '-chip' chip_number | '-active-high' |
+          '-active-low' | '-push-pull' | '-open-drain' | '-open-source'
+          | '-pull-none' | '-pull-up' | '-pull-down' | '-init-inactive'
+          | '-init-active' | '-init-input' ] ]
+
+     Define the GPIO mapping that the adapter will use.  The following
+     signals can be defined:
+
+        - 'tdo', 'tdi', 'tms', 'tck', 'trst': JTAG transport signals
+        - 'swdio', 'swclk': SWD transport signals
+        - 'swdio_dir': optional swdio buffer control signal
+        - 'srst': system reset signal
+        - 'led': optional activity led
+
+     Some adapters require that the GPIO chip number is set in addition
+     to the GPIO number.  The configuration options enable signals to be
+     defined as active-high or active-low.  The output drive mode can be
+     set to push-pull, open-drain or open-source.  Most adapters will
+     have to emulate open-drain or open-source drive modes by switching
+     between an input and output.  Input and output signals can be
+     instructed to use a pull-up or pull-down resistor, assuming it is
+     supported by the adaptor driver and hardware.  The initial state of
+     outputs may also be set, "active" state means 1 for active-high
+     outputs and 0 for active-low outputs.  Bidirectional signals may
+     also be initialized as an input.  If the swdio signal is buffered
+     the buffer direction can be controlled with the swdio_dir signal;
+     the active state means that the buffer should be set as an output
+     with respect to the adapter.  The command options are cumulative
+     with later commands able to override settings defined by earlier
+     ones.  The two commands 'gpio led 7 -active-high' and 'gpio led
+     -chip 1 -active-low' sent sequentially are equivalent to issuing
+     the single command 'gpio led 7 -chip 1 -active-low'.  It is not
+     permissible to set the drive mode or initial state for signals
+     which are inputs.  The drive mode for the srst and trst signals
+     must be set with the 'adapter reset_config' command.  It is not
+     permissible to set the initial state of swdio_dir as it is derived
+     from the initial state of swdio.  The command 'adapter gpio' prints
+     the current configuration for all GPIOs while the command 'adapter
+     gpio gpio_name' prints the current configuration for gpio_name.
+     Not all adapters support this generic GPIO mapping, some require
+     their own commands to define the GPIOs used.  Adapters that support
+     the generic mapping may not support all of the listed options.
+
+ -- Command: adapter name
+     Returns the name of the debug adapter driver being used.
+
+ -- Config Command: adapter usb location [-[.]...]
+     Displays or specifies the physical USB port of the adapter to use.
+     The path roots at BUS and walks down the physical ports, with each
+     PORT option specifying a deeper level in the bus topology, the last
+     PORT denoting where the target adapter is actually plugged.  The
+     USB bus topology can be queried with the command _lsusb -t_ or
+     _dmesg_.
+
+     This command is only available if your libusb1 is at least version
+     1.0.16.
+
+ -- Config Command: adapter serial serial_string
+     Specifies the SERIAL_STRING of the adapter to use.  If this command
+     is not specified, serial strings are not checked.  Only the
+     following adapter drivers use the serial string from this command:
+     arm-jtag-ew, cmsis_dap, esp_usb_jtag, ft232r, ftdi, hla (ti-icdi),
+     jlink, kitprog, opendus, openjtag, osbdm, presto, rlink, st-link,
+     usb_blaster (ublast2), usbprog, vsllink, xds110.
+
+8.2 Interface Drivers
+=====================
+
+Each of the interface drivers listed here must be explicitly enabled
+when OpenOCD is configured, in order to be made available at run time.
+
+ -- Interface Driver: amt_jtagaccel
+     Amontec Chameleon in its JTAG Accelerator configuration, connected
+     to a PC's EPP mode parallel port.  This defines some
+     driver-specific commands:
+
+      -- Config Command: parport port number
+          Specifies either the address of the I/O port (default: 0x378
+          for LPT1) or the number of the '/dev/parport' device.
+
+      -- Config Command: rtck ['enable'|'disable']
+          Displays status of RTCK option.  Optionally sets that option
+          first.
+
+ -- Interface Driver: angie
+     This is the NanoXplore's ANGIE USB-JTAG Adapter.
+
+ -- Interface Driver: arm-jtag-ew
+     Olimex ARM-JTAG-EW USB adapter This has one driver-specific
+     command:
+
+      -- Command: armjtagew_info
+          Logs some status
+
+ -- Interface Driver: at91rm9200
+     Supports bitbanged JTAG from the local system, presuming that
+     system is an Atmel AT91rm9200 and a specific set of GPIOs is used.
+
+ -- Interface Driver: cmsis-dap
+     ARM CMSIS-DAP compliant based adapter v1 (USB HID based) or v2 (USB
+     bulk).
+
+      -- Config Command: cmsis-dap vid_pid [vid pid]+
+          The vendor ID and product ID of the CMSIS-DAP device.  If not
+          specified the driver will attempt to auto detect the CMSIS-DAP
+          device.  Currently, up to eight [VID, PID] pairs may be given,
+          e.g.
+               cmsis-dap vid_pid 0xc251 0xf001 0x0d28 0x0204
+
+      -- Config Command: cmsis-dap backend ['auto'|'usb_bulk'|'hid']
+          Specifies how to communicate with the adapter:
+
+             - 'hid' Use HID generic reports - CMSIS-DAP v1
+             - 'usb_bulk' Use USB bulk - CMSIS-DAP v2
+             - 'auto' First try USB bulk CMSIS-DAP v2, if not found try
+               HID CMSIS-DAP v1.  This is the default if 'cmsis-dap
+               backend' is not specified.
+
+      -- Config Command: cmsis-dap usb interface [number]
+          Specifies the NUMBER of the USB interface to use in v2 mode
+          (USB bulk).  In most cases need not to be specified and
+          interfaces are searched by interface string or for user class
+          interface.
+
+      -- Command: cmsis-dap quirk ['enable'|'disable']
+          Enables or disables the following workarounds of known
+          CMSIS-DAP adapter quirks:
+             - disconnect and re-connect before sending a switch
+               sequence
+             - packets pipelining is suppressed, only one packet at a
+               time is submitted to the adapter
+          The quirk workarounds are disabled by default.  The command
+          without a parameter displays current setting.
+
+      -- Command: cmsis-dap info
+          Display various device information, like hardware version,
+          firmware version, current bus status.
+
+      -- Command: cmsis-dap cmd number number ...
+          Execute an arbitrary CMSIS-DAP command.  Use for adapter
+          testing or for handling of an adapter vendor specific command
+          from a Tcl script.
+
+          Take given numbers as bytes, assemble a CMSIS-DAP protocol
+          command packet from them and send it to the adapter.  The
+          first 4 bytes of the adapter response are logged.  See
+          
+
+ -- Interface Driver: dummy
+     A dummy software-only driver for debugging.
+
+ -- Interface Driver: ep93xx
+     Cirrus Logic EP93xx based single-board computer bit-banging (in
+     development)
+
+ -- Interface Driver: ftdi
+     This driver is for adapters using the MPSSE (Multi-Protocol
+     Synchronous Serial Engine) mode built into many FTDI chips, such as
+     the FT2232, FT4232 and FT232H.
+
+     The driver is using libusb-1.0 in asynchronous mode to talk to the
+     FTDI device, bypassing intermediate libraries like libftdi.
+
+     Support for new FTDI based adapters can be added completely through
+     configuration files, without the need to patch and rebuild OpenOCD.
+
+     The driver uses a signal abstraction to enable Tcl configuration
+     files to define outputs for one or several FTDI GPIO. These outputs
+     can then be controlled using the 'ftdi set_signal' command.
+     Special signal names are reserved for nTRST, nSRST and LED (for
+     blink) so that they, if defined, will be used for their customary
+     purpose.  Inputs can be read using the 'ftdi get_signal' command.
+
+     To support SWD, a signal named SWD_EN must be defined.  It is set
+     to 1 when the SWD protocol is selected.  When set, the adapter
+     should route the SWDIO pin to the data input.  An SWDIO_OE signal,
+     if defined, will be set to 1 or 0 as required by the protocol, to
+     tell the adapter to drive the data output onto the SWDIO pin or
+     keep the SWDIO pin Hi-Z, respectively.
+
+     Depending on the type of buffer attached to the FTDI GPIO, the
+     outputs have to be controlled differently.  In order to support
+     tristateable signals such as nSRST, both a data GPIO and an
+     output-enable GPIO can be specified for each signal.  The following
+     output buffer configurations are supported:
+
+        - Push-pull with one FTDI output as (non-)inverted data line
+        - Open drain with one FTDI output as (non-)inverted
+          output-enable
+        - Tristate with one FTDI output as (non-)inverted data line and
+          another FTDI output as (non-)inverted output-enable
+        - Unbuffered, using the FTDI GPIO as a tristate output directly
+          by switching data and direction as necessary
+
+     These interfaces have several commands, used to configure the
+     driver before initializing the JTAG scan chain:
+
+      -- Config Command: ftdi vid_pid [vid pid]+
+          The vendor ID and product ID of the adapter.  Up to eight
+          [VID, PID] pairs may be given, e.g.
+               ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
+
+      -- Config Command: ftdi device_desc description
+          Provides the USB device description (the _iProduct string_) of
+          the adapter.  If not specified, the device description is
+          ignored during device selection.
+
+      -- Config Command: ftdi channel channel
+          Selects the channel of the FTDI device to use for MPSSE
+          operations.  Most adapters use the default, channel 0, but
+          there are exceptions.
+
+      -- Config Command: ftdi layout_init data direction
+          Specifies the initial values of the FTDI GPIO data and
+          direction registers.  Each value is a 16-bit number
+          corresponding to the concatenation of the high and low FTDI
+          GPIO registers.  The values should be selected based on the
+          schematics of the adapter, such that all signals are set to
+          safe levels with minimal impact on the target system.  Avoid
+          floating inputs, conflicting outputs and initially asserted
+          reset signals.
+
+      -- Command: ftdi oscan1_mode on|off
+          Enable or disable OScan1 mode.  This mode is intended for use
+          with an adapter, such as the ARM-JTAG-SWD by Olimex, that sits
+          in between the FTDI chip and the target.  The cJTAG prococol
+          is composed of two wires: TCKC (clock) and TMSC (data).  TMSC
+          is a bidirectional signal which is time-multiplexed
+          alternating TDI, TMS and TDO. The multiplexing is achieved by
+          a tri-state buffer which puts TMSC in Hi-Z when the device is
+          supposed to take the control of the line (TDO phase).
+
+          The ARM-JTAG-SWD adapter uses standard TRST and TMS signals to
+          control TMSC direction.  TRST is used by the adapter as
+          selector for the multiplexers which set the JTAG probe in
+          2-wire mode.  Whatever signal is used for this purpose, it
+          must be defined with the name JTAG_SEL using 'ftdi
+          layout_signal'.  JTAG_SEL is set to 0 during OScan1
+          initialization.
+
+          Some JTAG probes like the Digilent JTAG-HS2, support cJTAG by
+          using a separate pin to control when TMS is driven onto TMSC.
+          You can use such probes by defining the signal TMSC_EN using
+          'ftdi layout_signal TMSC_EN -data '.
+
+      -- Command: ftdi jscan3_mode on|off
+          Enable or disable JScan3 mode.  This mode uses the classic
+          4-wire JTAG protocol in chips whose JTAG port is only
+          compliant with the cJTAG standard (IEEE 1149.7).
+
+          Since cJTAG needs a 2-wire escape sequence to select the
+          operating mode, a cJTAG adapter like ARM-JTAG-SWD by Olimex is
+          still required.  This means that a cJTAG probe configuration
+          script must be used too.
+
+      -- Command: ftdi layout_signal name ['-data'|'-ndata' data_mask]
+               ['-input'|'-ninput' input_mask] ['-oe'|'-noe' oe_mask]
+               ['-alias'|'-nalias' name]
+          Creates a signal with the specified NAME, controlled by one or
+          more FTDI GPIO pins via a range of possible buffer
+          connections.  The masks are FTDI GPIO register bitmasks to
+          tell the driver the connection and type of the output buffer
+          driving the respective signal.  DATA_MASK is the bitmask for
+          the pin(s) connected to the data input of the output buffer.
+          '-ndata' is used with inverting data inputs and '-data' with
+          non-inverting inputs.  The '-oe' (or '-noe') option tells
+          where the output-enable (or not-output-enable) input to the
+          output buffer is connected.  The options '-input' and
+          '-ninput' specify the bitmask for pins to be read with the
+          method 'ftdi get_signal'.
+
+          Both DATA_MASK and OE_MASK need not be specified.  For
+          example, a simple open-collector transistor driver would be
+          specified with '-oe' only.  In that case the signal can only
+          be set to drive low or to Hi-Z and the driver will complain if
+          the signal is set to drive high.  Which means that if it's a
+          reset signal, 'reset_config' must be specified as
+          'srst_open_drain', not 'srst_push_pull'.
+
+          A special case is provided when '-data' and '-oe' is set to
+          the same bitmask.  Then the FTDI pin is considered being
+          connected straight to the target without any buffer.  The FTDI
+          pin is then switched between output and input as necessary to
+          provide the full set of low, high and Hi-Z characteristics.
+          In all other cases, the pins specified in a signal definition
+          are always driven by the FTDI.
+
+          If '-alias' or '-nalias' is used, the signal is created
+          identical (or with data inverted) to an already specified
+          signal NAME.
+
+      -- Command: ftdi set_signal name '0'|'1'|'z'
+          Set a previously defined signal to the specified level.
+             - '0', drive low
+             - '1', drive high
+             - 'z', set to high-impedance
+
+      -- Command: ftdi get_signal name
+          Get the value of a previously defined signal.
+
+      -- Command: ftdi tdo_sample_edge 'rising'|'falling'
+          Configure TCK edge at which the adapter samples the value of
+          the TDO signal
+
+          Due to signal propagation delays, sampling TDO on rising TCK
+          can become quite peculiar at high JTAG clock speeds.  However,
+          FTDI chips offer a possibility to sample TDO on falling edge
+          of TCK. With some board/adapter configurations, this may
+          increase stability at higher JTAG clocks.
+             - 'rising', sample TDO on rising edge of TCK - this is the
+               default
+             - 'falling', sample TDO on falling edge of TCK
+
+     For example adapter definitions, see the configuration files
+     shipped in the 'interface/ftdi' directory.
+
+ -- Interface Driver: ft232r
+     This driver is implementing synchronous bitbang mode of an FTDI
+     FT232R, FT230X, FT231X and similar USB UART bridge ICs by reusing
+     RS232 signals as GPIO. It currently doesn't support using CBUS pins
+     as GPIO.
+
+     List of connections (default physical pin numbers for FT232R in
+     28-pin SSOP package):
+        - RXD(5) - TDI
+        - TXD(1) - TCK
+        - RTS(3) - TDO
+        - CTS(11) - TMS
+        - DTR(2) - TRST
+        - DCD(10) - SRST
+
+     User can change default pinout by supplying configuration commands
+     with GPIO numbers or RS232 signal names.  GPIO numbers correspond
+     to bit numbers in FTDI GPIO register.  They differ from physical
+     pin numbers.  For details see actual FTDI chip datasheets.  Every
+     JTAG line must be configured to unique GPIO number different than
+     any other JTAG line, even those lines that are sometimes not used
+     like TRST or SRST.
+
+     FT232R
+        - bit 7 - RI
+        - bit 6 - DCD
+        - bit 5 - DSR
+        - bit 4 - DTR
+        - bit 3 - CTS
+        - bit 2 - RTS
+        - bit 1 - RXD
+        - bit 0 - TXD
+
+     These interfaces have several commands, used to configure the
+     driver before initializing the JTAG scan chain:
+
+      -- Config Command: ft232r vid_pid VID PID
+          The vendor ID and product ID of the adapter.  If not
+          specified, default 0x0403:0x6001 is used.
+
+      -- Config Command: ft232r jtag_nums TCK TMS TDI TDO
+          Set four JTAG GPIO numbers at once.  If not specified, default
+          0 3 1 2 or TXD CTS RXD RTS is used.
+
+      -- Config Command: ft232r tck_num TCK
+          Set TCK GPIO number.  If not specified, default 0 or TXD is
+          used.
+
+      -- Config Command: ft232r tms_num TMS
+          Set TMS GPIO number.  If not specified, default 3 or CTS is
+          used.
+
+      -- Config Command: ft232r tdi_num TDI
+          Set TDI GPIO number.  If not specified, default 1 or RXD is
+          used.
+
+      -- Config Command: ft232r tdo_num TDO
+          Set TDO GPIO number.  If not specified, default 2 or RTS is
+          used.
+
+      -- Config Command: ft232r trst_num TRST
+          Set TRST GPIO number.  If not specified, default 4 or DTR is
+          used.
+
+      -- Config Command: ft232r srst_num SRST
+          Set SRST GPIO number.  If not specified, default 6 or DCD is
+          used.
+
+      -- Config Command: ft232r restore_serial WORD
+          Restore serial port after JTAG. This USB bitmode control word
+          (16-bit) will be sent before quit.  Lower byte should set GPIO
+          direction register to a "sane" state: 0x15 for TXD RTS DTR as
+          outputs (1), others as inputs (0).  Higher byte is usually 0
+          to disable bitbang mode.  When kernel driver reattaches,
+          serial port should continue to work.  Value 0xFFFF disables
+          sending control word and serial port, then kernel driver will
+          not reattach.  If not specified, default 0xFFFF is used.
+
+ -- Interface Driver: remote_bitbang
+     Drive JTAG and SWD from a remote process.  This sets up a UNIX or
+     TCP socket connection with a remote process and sends ASCII encoded
+     bitbang requests to that process instead of directly driving JTAG
+     and SWD.
+
+     The remote_bitbang driver is useful for debugging software running
+     on processors which are being simulated.
+
+      -- Config Command: remote_bitbang port number
+          Specifies the TCP port of the remote process to connect to or
+          0 to use UNIX sockets instead of TCP.
+
+      -- Config Command: remote_bitbang host hostname
+          Specifies the hostname of the remote process to connect to
+          using TCP, or the name of the UNIX socket to use if
+          remote_bitbang port is 0.
+
+      -- Config Command: remote_bitbang use_remote_sleep (on|off)
+          If this option is enabled, delays will not be executed locally
+          but instead forwarded to the remote host.  This is useful if
+          the remote host performs its own request queuing rather than
+          executing requests immediately.
+
+          This is disabled by default.  This option must only be enabled
+          if the given remote_bitbang host supports receiving the delay
+          information.
+
+     For example, to connect remotely via TCP to the host foobar you
+     might have something like:
+
+          adapter driver remote_bitbang
+          remote_bitbang port 3335
+          remote_bitbang host foobar
+
+     And if you also wished to enable remote sleeping:
+
+          adapter driver remote_bitbang
+          remote_bitbang port 3335
+          remote_bitbang host foobar
+          remote_bitbang use_remote_sleep on
+
+     To connect to another process running locally via UNIX sockets with
+     socket named mysocket:
+
+          adapter driver remote_bitbang
+          remote_bitbang port 0
+          remote_bitbang host mysocket
+
+ -- Interface Driver: usb_blaster
+     USB JTAG/USB-Blaster compatibles over one of the userspace
+     libraries for FTDI chips.  These interfaces have several commands,
+     used to configure the driver before initializing the JTAG scan
+     chain:
+
+      -- Config Command: usb_blaster vid_pid vid pid
+          The vendor ID and product ID of the FTDI FT245 device.  If not
+          specified, default values are used.  Currently, only one VID,
+          PID pair may be given, e.g.  for Altera USB-Blaster (default):
+               usb_blaster vid_pid 0x09FB 0x6001
+          The following VID/PID is for Kolja Waschk's USB JTAG:
+               usb_blaster vid_pid 0x16C0 0x06AD
+
+      -- Command: usb_blaster pin ('pin6'|'pin8') ('0'|'1'|'s'|'t')
+          Sets the state or function of the unused GPIO pins on
+          USB-Blasters (pins 6 and 8 on the female JTAG header).  These
+          pins can be used as SRST and/or TRST provided the appropriate
+          connections are made on the target board.
+
+          For example, to use pin 6 as SRST:
+               usb_blaster pin pin6 s
+               reset_config srst_only
+
+      -- Config Command: usb_blaster lowlevel_driver ('ftdi'|'ublast2')
+          Chooses the low level access method for the adapter.  If not
+          specified, 'ftdi' is selected unless it wasn't enabled during
+          the configure stage.  USB-Blaster II needs 'ublast2'.
+
+      -- Config Command: usb_blaster firmware PATH
+          This command specifies PATH to access USB-Blaster II firmware
+          image.  To be used with USB-Blaster II only.
+
+ -- Interface Driver: gw16012
+     Gateworks GW16012 JTAG programmer.  This has one driver-specific
+     command:
+
+      -- Config Command: parport port [port_number]
+          Display either the address of the I/O port (default: 0x378 for
+          LPT1) or the number of the '/dev/parport' device.  If a
+          parameter is provided, first switch to use that port.  This is
+          a write-once setting.
+
+ -- Interface Driver: jlink
+     SEGGER J-Link family of USB adapters.  It currently supports JTAG
+     and SWD transports.
+
+          Compatibility Note: SEGGER released many firmware versions for
+          the many hardware versions they produced.  OpenOCD was
+          extensively tested and intended to run on all of them, but
+          some combinations were reported as incompatible.  As a general
+          recommendation, it is advisable to use the latest firmware
+          version available for each hardware version.  However the
+          current V8 is a moving target, and SEGGER firmware versions
+          released after the OpenOCD was released may not be compatible.
+          In such cases it is recommended to revert to the last known
+          functional version.  For 0.5.0, this is from "Feb 8 2012
+          14:30:39", packed with 4.42c.  For 0.6.0, the last known
+          version is from "May 3 2012 18:36:22", packed with 4.46f.
+
+      -- Command: jlink hwstatus
+          Display various hardware related information, for example
+          target voltage and pin states.
+      -- Command: jlink freemem
+          Display free device internal memory.
+      -- Command: jlink jtag ['2'|'3']
+          Set the JTAG command version to be used.  Without argument,
+          show the actual JTAG command version.
+      -- Command: jlink targetpower ['0'|'1'|'on'|'off']
+          Switch the 5 V target power supply on or off.  Without
+          argument, show the state of the target power supply.  The
+          target power supply is usually connected to pin 19 of the
+          20-pin connector.
+      -- Command: jlink config
+          Display the device configuration.
+      -- Command: jlink config targetpower ['on'|'off']
+          Set the target power state on JTAG-pin 19.  Without argument,
+          show the target power state.
+      -- Command: jlink config mac ['ff:ff:ff:ff:ff:ff']
+          Set the MAC address of the device.  Without argument, show the
+          MAC address.
+      -- Command: jlink config ip ['A.B.C.D'('/E'|'F.G.H.I')]
+          Set the IP configuration of the device, where A.B.C.D is the
+          IP address, E the bit of the subnet mask and F.G.H.I the
+          subnet mask.  Without arguments, show the IP configuration.
+      -- Command: jlink config usb ['0' to '3']
+          Set the USB address of the device.  This will also change the
+          USB Product ID (PID) of the device.  Without argument, show
+          the USB address.
+      -- Command: jlink config reset
+          Reset the current configuration.
+      -- Command: jlink config write
+          Write the current configuration to the internal persistent
+          storage.
+      -- Command: jlink emucom write  
+          Write data to an EMUCOM channel.  The data needs to be encoded
+          as hexadecimal pairs.
+
+          The following example shows how to write the three bytes 0xaa,
+          0x0b and 0x23 to the EMUCOM channel 0x10:
+               > jlink emucom write 0x10 aa0b23
+      -- Command: jlink emucom read  
+          Read data from an EMUCOM channel.  The read data is encoded as
+          hexadecimal pairs.
+
+          The following example shows how to read 4 bytes from the
+          EMUCOM channel 0x0:
+               > jlink emucom read 0x0 4
+               77a90000
+      -- Config Command: jlink usb <'0' to '3'>
+          Set the USB address of the interface, in case more than one
+          adapter is connected to the host.  If not specified, USB
+          addresses are not considered.  Device selection via USB
+          address is not always unambiguous.  It is recommended to use
+          the serial number instead, if possible.
+
+          As a configuration command, it can be used only before 'init'.
+
+ -- Interface Driver: kitprog
+     This driver is for Cypress Semiconductor's KitProg adapters.  The
+     KitProg is an SWD-only adapter that is designed to be used with
+     Cypress's PSoC and PRoC device families, but it is possible to use
+     it with some other devices.  If you are using this adapter with a
+     PSoC or a PRoC, you may need to add 'kitprog init_acquire_psoc' or
+     'kitprog acquire_psoc' to your configuration script.
+
+     Note that this driver is for the proprietary KitProg protocol, not
+     the CMSIS-DAP mode introduced in firmware 2.14.  If the KitProg is
+     in CMSIS-DAP mode, it cannot be used with this driver, and must
+     either be used with the cmsis-dap driver or switched back to
+     KitProg mode.  See the Cypress KitProg User Guide for instructions
+     on how to switch KitProg modes.
+
+     Known limitations:
+        * The frequency of SWCLK cannot be configured, and varies
+          between 1.6 MHz and 2.7 MHz.
+        * For firmware versions below 2.14, "JTAG to SWD" sequences are
+          replaced by "SWD line reset" in the driver.  This is for two
+          reasons.  First, the KitProg does not support sending
+          arbitrary SWD sequences, and only firmware 2.14 and later
+          implement both "JTAG to SWD" and "SWD line reset" in firmware.
+          Earlier firmware versions only implement "SWD line reset".
+          Second, due to a firmware quirk, an SWD sequence must be sent
+          after every target reset in order to re-establish
+          communications with the target.
+        * Due in part to the limitation above, KitProg devices with
+          firmware below version 2.14 will need to use 'kitprog
+          init_acquire_psoc' in order to communicate with PSoC 5LP
+          devices.  This is because, assuming debug is not disabled on
+          the PSoC, the PSoC 5LP needs its JTAG interface switched to
+          SWD mode before communication can begin, but prior to firmware
+          2.14, "JTAG to SWD" could only be sent with an acquisition
+          sequence.
+
+      -- Config Command: kitprog init_acquire_psoc
+          Indicate that a PSoC acquisition sequence needs to be run
+          during adapter init.  Please be aware that the acquisition
+          sequence hard-resets the target.
+
+      -- Command: kitprog acquire_psoc
+          Run a PSoC acquisition sequence immediately.  Typically, this
+          should not be used outside of the target-specific
+          configuration scripts since it hard-resets the target as a
+          side-effect.  This is necessary for "reset halt" on some PSoC
+          4 series devices.
+
+      -- Command: kitprog info
+          Display various adapter information, such as the hardware
+          version, firmware version, and target voltage.
+
+ -- Interface Driver: parport
+     Supports PC parallel port bit-banging cables: Wigglers, PLD
+     download cable, and more.  These interfaces have several commands,
+     used to configure the driver before initializing the JTAG scan
+     chain:
+
+      -- Config Command: parport cable name
+          Set the layout of the parallel port cable used to connect to
+          the target.  This is a write-once setting.  Currently valid
+          cable NAME values include:
+
+             - altium Altium Universal JTAG cable.
+             - arm-jtag Same as original wiggler except SRST and TRST
+               connections reversed and TRST is also inverted.
+             - chameleon The Amontec Chameleon's CPLD when operated in
+               configuration mode.  This is only used to program the
+               Chameleon itself, not a connected target.
+             - dlc5 The Xilinx Parallel cable III.
+             - flashlink The ST Parallel cable.
+             - lattice Lattice ispDOWNLOAD Cable
+             - old_amt_wiggler The Wiggler configuration that comes with
+               some versions of Amontec's Chameleon Programmer.  The new
+               version available from the website uses the original
+               Wiggler layout ('WIGGLER')
+             - triton The parallel port adapter found on the "Karo
+               Triton 1 Development Board".  This is also the layout
+               used by the HollyGates design (see
+               ).
+             - wiggler The original Wiggler layout, also supported by
+               several clones, such as the Olimex ARM-JTAG
+             - wiggler2 Same as original wiggler except an led is fitted
+               on D5.
+             - wiggler_ntrst_inverted Same as original wiggler except
+               TRST is inverted.
+
+      -- Config Command: parport port [port_number]
+          Display either the address of the I/O port (default: 0x378 for
+          LPT1) or the number of the '/dev/parport' device.  If a
+          parameter is provided, first switch to use that port.  This is
+          a write-once setting.
+
+          When using PPDEV to access the parallel port, use the number
+          of the parallel port: 'parport port 0' (the default).  If
+          'parport port 0x378' is specified you may encounter a problem.
+
+      -- Config Command: parport toggling_time [nanoseconds]
+          Displays how many nanoseconds the hardware needs to toggle
+          TCK; the parport driver uses this value to obey the 'adapter
+          speed' configuration.  When the optional NANOSECONDS parameter
+          is given, that setting is changed before displaying the
+          current value.
+
+          The default setting should work reasonably well on commodity
+          PC hardware.  However, you may want to calibrate for your
+          specific hardware.
+               Tip: To measure the toggling time with a logic analyzer
+               or a digital storage oscilloscope, follow the procedure
+               below:
+                    > parport toggling_time 1000
+                    > adapter speed 500
+               This sets the maximum JTAG clock speed of the hardware,
+               but the actual speed probably deviates from the requested
+               500 kHz.  Now, measure the time between the two closest
+               spaced TCK transitions.  You can use 'runtest 1000' or
+               something similar to generate a large set of samples.
+               Update the setting to match your measurement:
+                    > parport toggling_time 
+               Now the clock speed will be a better match for 'adapter
+               speed' command given in OpenOCD scripts and event
+               handlers.
+
+               You can do something similar with many digital
+               multimeters, but note that you'll probably need to run
+               the clock continuously for several seconds before it
+               decides what clock rate to show.  Adjust the toggling
+               time up or down until the measured clock rate is a good
+               match with the rate you specified in the 'adapter speed'
+               command; be conservative.
+
+      -- Config Command: parport write_on_exit ('on'|'off')
+          This will configure the parallel driver to write a known
+          cable-specific value to the parallel interface on exiting
+          OpenOCD.
+
+     For example, the interface configuration file for a classic
+     "Wiggler" cable on LPT2 might look something like this:
+
+          adapter driver parport
+          parport port 0x278
+          parport cable wiggler
+
+ -- Interface Driver: presto
+     ASIX PRESTO USB JTAG programmer.
+
+ -- Interface Driver: rlink
+     Raisonance RLink USB adapter
+
+ -- Interface Driver: usbprog
+     usbprog is a freely programmable USB adapter.
+
+ -- Interface Driver: vsllink
+     vsllink is part of Versaloon which is a versatile USB programmer.
+
+          Note: This defines quite a few driver-specific commands, which
+          are not currently documented here.
+
+ -- Interface Driver: hla
+     This is a driver that supports multiple High Level Adapters.  This
+     type of adapter does not expose some of the lower level api's that
+     OpenOCD would normally use to access the target.
+
+     Currently supported adapters include the STMicroelectronics
+     ST-LINK, TI ICDI and Nuvoton Nu-Link.  ST-LINK firmware version >=
+     V2.J21.S4 recommended due to issues with earlier versions of
+     firmware where serial number is reset after first use.  Suggest
+     using ST firmware update utility to upgrade ST-LINK firmware even
+     if current version reported is V2.J21.S4.
+
+      -- Config Command: hla device_desc description
+          Currently Not Supported.
+
+      -- Config Command: hla layout ('icdi'|'nulink')
+          Specifies the adapter layout to use.
+
+      -- Config Command: hla vid_pid [vid pid]+
+          Pairs of vendor IDs and product IDs of the device.
+
+      -- Command: hla command command
+          Execute a custom adapter-specific command.  The COMMAND string
+          is passed as is to the underlying adapter layout handler.
+
+ -- Interface Driver: st-link
+     This is a driver that supports STMicroelectronics adapters
+     ST-LINK/V2 (from 2015 firmware V2J24), STLINK-V3 and STLINK-V3PWR,
+     thanks to a new API that provides directly access the arm ADIv5
+     DAP.
+
+     The older API that requires HLA transport is deprecated and will be
+     dropped from OpenOCD. In mean time it's still available by using
+     'interface/stlink-hla.cfg'.
+
+     The new API provide access to multiple AP on the same DAP, but the
+     maximum number of the AP port is limited by the specific firmware
+     version (e.g.  firmware V2J29 has 3 as maximum AP number, while
+     V2J32 has 8).  An error is returned for any AP number above the
+     maximum allowed value.
+
+     _Note:_ Either these same adapters and their older versions are
+     also supported by *note the hla interface driver: hla_interface.
+
+      -- Config Command: st-link backend (usb | tcp [port])
+          Choose between 'exclusive' USB communication (the default
+          backend) or 'shared' mode using ST-Link TCP server (the
+          default port is 7184).
+
+          _Note:_ ST-Link TCP server is a binary application provided by
+          ST available from ST-LINK server software module
+          (https://www.st.com/en/development-tools/st-link-server.html).
+
+          _Note:_ ST-Link TCP server does not support the SWIM
+          transport.
+
+      -- Config Command: st-link vid_pid [vid pid]+
+          Pairs of vendor IDs and product IDs of the device.
+
+      -- Command: st-link cmd rx_n (tx_byte)+
+          Sends an arbitrary command composed by the sequence of bytes
+          TX_BYTE and receives RX_N bytes.
+
+          For example, the command to read the target's supply voltage
+          is one byte 0xf7 followed by 15 bytes zero.  It returns 8
+          bytes, where the first 4 bytes represent the ADC sampling of
+          the reference voltage 1.2V and the last 4 bytes represent the
+          ADC sampling of half the target's supply voltage.
+               > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+               0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
+          The result can be converted to Volts (ignoring the most
+          significant bytes, always zero)
+               > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
+               > set n [expr {[lindex $a 4] + 256 * [lindex $a 5]}]
+               > set d [expr {[lindex $a 0] + 256 * [lindex $a 1]}]
+               > echo [expr {2 * 1.2 * $n / $d}]
+               3.24891518738
+
+ -- Interface Driver: opendous
+     opendous-jtag is a freely programmable USB adapter.
+
+ -- Interface Driver: ulink
+     This is the Keil ULINK v1 JTAG debugger.
+
+ -- Interface Driver: xds110
+     The XDS110 is included as the embedded debug probe on many Texas
+     Instruments LaunchPad evaluation boards.  The XDS110 is also
+     available as a stand-alone USB debug probe with the added
+     capability to supply power to the target board.  The following
+     commands are supported by the XDS110 driver:
+
+      -- Config Command: xds110 supply voltage_in_millivolts
+          Available only on the XDS110 stand-alone probe.  Sets the
+          voltage level of the XDS110 power supply.  A value of 0 leaves
+          the supply off.  Otherwise, the supply can be set to any value
+          in the range 1800 to 3600 millivolts.
+
+      -- Command: xds110 info
+          Displays information about the connected XDS110 debug probe
+          (e.g.  firmware version).
+
+ -- Interface Driver: xlnx_pcie_xvc
+     This driver supports the Xilinx Virtual Cable (XVC) over PCI
+     Express.  It is commonly found in Xilinx based PCI Express designs.
+     It allows debugging fabric based JTAG/SWD devices such as
+     Cortex-M1/M3 microcontrollers.  Access to this is exposed via
+     extended capability registers in the PCI Express configuration
+     space.
+
+     For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG
+     mode).
+
+      -- Config Command: xlnx_pcie_xvc config device
+          Specifies the PCI Express device via parameter DEVICE to use.
+
+          The correct value for DEVICE can be obtained by looking at the
+          output of lscpi -D (first column) for the corresponding
+          device.
+
+          The string will be of the format "DDDD:BB:SS.F" such as
+          "0000:65:00.1".
+
+ -- Interface Driver: bcm2835gpio
+     This SoC is present in Raspberry Pi which is a cheap single-board
+     computer exposing some GPIOs on its expansion header.
+
+     The driver accesses memory-mapped GPIO peripheral registers
+     directly for maximum performance, but the only possible race
+     condition is for the pins' modes/muxing (which is highly unlikely),
+     so it should be able to coexist nicely with both sysfs bitbanging
+     and various peripherals' kernel drivers.  The driver restores the
+     previous configuration on exit.
+
+     GPIO numbers >= 32 can't be used for performance reasons.  GPIO
+     configuration is handled by the generic command *note 'adapter
+     gpio': adapter gpio.
+
+     See 'interface/raspberrypi-native.cfg' for a sample config and
+     'interface/raspberrypi-gpio-connector.cfg' for pinout.
+
+      -- Config Command: bcm2835gpio speed_coeffs SPEED_COEFF
+               SPEED_OFFSET
+          Set SPEED_COEFF and SPEED_OFFSET for delay calculations.  If
+          unspecified, speed_coeff defaults to 113714, and speed_offset
+          defaults to 28.
+
+      -- Config Command: bcm2835gpio peripheral_mem_dev DEVICE
+          Set the device path for access to the memory mapped GPIO
+          control registers.  Uses '/dev/gpiomem' by default, this is
+          also the preferred option with respect to system security.  If
+          overridden to '/dev/mem':
+             - OpenOCD needs 'cap_sys_rawio' or run as root to open
+               '/dev/mem'.  Please be aware of security issues imposed
+               by running OpenOCD with elevated user rights and by
+               '/dev/mem' itself.
+             - correct 'peripheral_base' must be configured.
+             - GPIO 0-27 pads are set to the limited slew rate and drive
+               strength is reduced to 4 mA (2 mA on RPi 4).
+
+      -- Config Command: bcm2835gpio peripheral_base BASE
+          Set the peripheral base register address to access GPIOs.
+          Ignored if '/dev/gpiomem' is used.  For the RPi1, use
+          0x20000000.  For RPi2 and RPi3, use 0x3F000000.  For RPi4, use
+          0xFE000000.  A full list can be found in the official guide
+          (https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md).
+
+ -- Interface Driver: imx_gpio
+     i.MX SoC is present in many community boards.  Wandboard is an
+     example of the one which is most popular.
+
+     This driver is mostly the same as bcm2835gpio.
+
+     See 'interface/imx-native.cfg' for a sample config and pinout.
+
+ -- Interface Driver: am335xgpio The AM335x SoC is present in BeagleBone
+     Black and BeagleBone Green single-board computers which expose some
+     of the GPIOs on the two expansion headers.
+
+     For maximum performance the driver accesses memory-mapped GPIO
+     peripheral registers directly.  The memory mapping requires read
+     and write permission to kernel memory; if /dev/gpiomem exists it
+     will be used, otherwise /dev/mem will be used.  The driver restores
+     the GPIO state on exit.
+
+     All four GPIO ports are available.  GPIO configuration is handled
+     by the generic command *note 'adapter gpio': adapter gpio.
+
+      -- Config Command: am335xgpio speed_coeffs SPEED_COEFF
+               SPEED_OFFSET
+          Set SPEED_COEFF and SPEED_OFFSET for delay calculations.  If
+          unspecified speed_coeff defaults to 600000 and speed_offset
+          defaults to 575.
+
+     See 'interface/beaglebone-swd-native.cfg' for a sample
+     configuration file.
+
+ -- Interface Driver: linuxgpiod
+     Linux provides userspace access to GPIO through libgpiod since
+     Linux kernel version v4.6.  The driver emulates either JTAG or SWD
+     transport through bitbanging.  There are no driver-specific
+     commands, all GPIO configuration is handled by the generic command
+     *note 'adapter gpio': adapter gpio.  This driver supports the
+     resistor pull options provided by the 'adapter gpio' command but
+     the underlying hardware may not be able to support them.
+
+     See 'interface/dln-2-gpiod.cfg' for a sample configuration file.
+
+ -- Interface Driver: sysfsgpio
+     Linux legacy userspace access to GPIO through sysfs is deprecated
+     from Linux kernel version v5.3.  Prefer using linuxgpiod, instead.
+
+     See 'interface/sysfsgpio-raspberrypi.cfg' for a sample config.
+
+ -- Interface Driver: openjtag
+     OpenJTAG compatible USB adapter.  This defines some driver-specific
+     commands:
+
+      -- Config Command: openjtag variant variant
+          Specifies the variant of the OpenJTAG adapter (see
+          ).  Currently valid VARIANT values
+          include:
+
+             - standard Standard variant (default).
+             - cy7c65215 Cypress CY7C65215 Dual Channel USB-Serial
+               Bridge Controller (see
+               ).
+
+      -- Config Command: openjtag device_desc string
+          The USB device description string of the adapter.  This value
+          is only used with the standard variant.
+
+      -- Config Command: openjtag vid_pid vid pid
+          The USB vendor ID and product ID of the adapter.  If not
+          specified, default 0x0403:0x6001 is used.  This value is only
+          used with the standard variant.
+               openjtag vid_pid 0x403 0x6014
+
+ -- Interface Driver: vdebug
+     Cadence Virtual Debug Interface driver.
+
+      -- Config Command: vdebug server host:port
+          Specifies the host and TCP port number where the vdebug server
+          runs.
+
+      -- Config Command: vdebug batching value
+          Specifies the batching method for the vdebug request.
+          Possible values are 0 for no batching 1 or wr to batch write
+          transactions together (default) 2 or rw to batch both read and
+          write transactions
+
+      -- Config Command: vdebug polling min max
+          Takes two values, representing the polling interval in ms.
+          Lower values mean faster debugger responsiveness, but lower
+          emulation performance.  The minimum should be around 10,
+          maximum should not exceed 1000, which is the default gdb and
+          keepalive timeout value.
+
+      -- Config Command: vdebug bfm_path path clk_period
+          Specifies the hierarchical path and input clk period of the
+          vdebug BFM in the design.  The hierarchical path uses Verilog
+          notation top.inst.inst The clock period must include the unit,
+          for instance 40ns.
+
+      -- Config Command: vdebug mem_path path base size
+          Specifies the hierarchical path to the design memory instance
+          for backdoor access.  Up to 4 memories can be specified.  The
+          hierarchical path uses Verilog notation.  The base specifies
+          start address in the design address space, size its size in
+          bytes.  Both values can use hexadecimal notation with prefix
+          0x.
+
+ -- Interface Driver: jtag_dpi
+     SystemVerilog Direct Programming Interface (DPI) compatible driver
+     for JTAG devices in emulation.  The driver acts as a client for the
+     SystemVerilog DPI server interface.
+
+      -- Config Command: jtag_dpi set_port port
+          Specifies the TCP/IP port number of the SystemVerilog DPI
+          server interface.
+
+      -- Config Command: jtag_dpi set_address address
+          Specifies the TCP/IP address of the SystemVerilog DPI server
+          interface.
+
+ -- Interface Driver: buspirate
+
+     This driver is for the Bus Pirate (see
+     ) and compatible
+     devices.  It uses a simple data protocol over a serial port
+     connection.
+
+     Most hardware development boards have a UART, a real serial port,
+     or a virtual USB serial device, so this driver allows you to start
+     building your own JTAG adapter without the complexity of a custom
+     USB connection.
+
+      -- Config Command: buspirate port serial_port
+          Specify the serial port's filename.  For example:
+               buspirate port /dev/ttyUSB0
+
+      -- Config Command: buspirate speed (normal|fast)
+          Set the communication speed to 115k (normal) or 1M (fast).
+          For example:
+               buspirate speed normal
+
+      -- Config Command: buspirate mode (normal|open-drain)
+          Set the Bus Pirate output mode.
+             - In normal mode (push/pull), do not enable the pull-ups,
+               and do not connect I/O header pin VPU to JTAG VREF.
+             - In open drain mode, you will then need to enable the
+               pull-ups.
+          For example:
+               buspirate mode normal
+
+      -- Config Command: buspirate pullup (0|1)
+          Whether to connect (1) or not (0) the I/O header pin VPU (JTAG
+          VREF) to the pull-up/pull-down resistors on MOSI (JTAG TDI),
+          CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS). For
+          example:
+               buspirate pullup 0
+
+      -- Config Command: buspirate vreg (0|1)
+          Whether to enable (1) or disable (0) the built-in voltage
+          regulator, which can be used to supply power to a test circuit
+          through I/O header pins +3V3 and +5V. For example:
+               buspirate vreg 0
+
+      -- Command: buspirate led (0|1)
+          Turns the Bus Pirate's LED on (1) or off (0).  For example:
+          buspirate led 1
+
+ -- Interface Driver: esp_usb_jtag
+     Espressif JTAG driver to communicate with ESP32-C3, ESP32-S3 chips
+     and ESP USB Bridge board using OpenOCD. These chips have built-in
+     JTAG circuitry and can be debugged without any additional hardware.
+     Only an USB cable connected to the D+/D- pins is necessary.
+
+      -- Command: espusbjtag tdo
+          Returns the current state of the TDO line
+
+      -- Command: espusbjtag setio setio
+          Manually set the status of the output lines with the order of
+          (tdi tms tck trst srst)
+               espusbjtag setio 0 1 0 1 0
+
+      -- Config Command: espusbjtag vid_pid vid_pid
+          Set vendor ID and product ID for the ESP usb jtag driver
+               espusbjtag vid_pid 0x303a 0x1001
+
+      -- Config Command: espusbjtag caps_descriptor caps_descriptor
+          Set the jtag descriptor to read capabilities of ESP usb jtag
+          driver
+               espusbjtag caps_descriptor 0x2000
+
+      -- Config Command: espusbjtag chip_id chip_id
+          Set chip id to transfer to the ESP USB bridge board
+               espusbjtag chip_id 1
+
+ -- Interface Driver: dmem Direct Memory access debug interface
+
+     The Texas Instruments K3 SoC family provides memory access to DAP
+     and coresight control registers.  This allows control over the
+     microcontrollers directly from one of the processors on the SOC
+     itself.
+
+     For maximum performance, the driver accesses the debug registers
+     directly over the SoC memory map.  The memory mapping requires read
+     and write permission to kernel memory via "/dev/mem" and assumes
+     that the system firewall configurations permit direct access to the
+     debug memory space.
+
+     +-----------+
+     |  OpenOCD  |   SoC mem map (/dev/mem)
+     |    on     +--------------+
+     | Cortex-A53|              |
+     +-----------+              |
+                                |
+     +-----------+        +-----v-----+
+     |Cortex-M4F <--------+           |
+     +-----------+        |           |
+                          |  DebugSS  |
+     +-----------+        |           |
+     |Cortex-M4F <--------+           |
+     +-----------+        +-----------+
+
+     NOTE: Firewalls are configurable in K3 SoC and depending on various
+     types of device configuration, this function may be blocked out.
+     Typical behavior observed in such cases is a firewall exception
+     report on the security controller and armv8 processor reporting a
+     system error.
+
+     See 'tcl/interface/ti_k3_am625-swd-native.cfg' for a sample
+     configuration file.
+
+      -- Command: dmem info
+          Print the DAPBUS dmem configuration.
+
+      -- Config Command: dmem device device_path
+          Set the DAPBUS memory access device (default: /dev/mem).
+
+      -- Config Command: dmem base_address base_address
+          Set the DAPBUS base address which is used to access CoreSight
+          compliant Access Ports (APs) directly.
+
+      -- Config Command: dmem ap_address_offset offset_address
+          Set the address offset between Access Ports (APs).
+
+      -- Config Command: dmem max_aps n
+          Set the maximum number of valid access ports on the SoC.
+
+      -- Config Command: dmem emu_ap_list n
+          Set the list of Access Ports (APs) that need to be emulated.
+          This emulation mode supports software translation of an AP
+          request into an address mapped transaction that does not rely
+          on physical AP hardware.  This maybe needed if the AP is
+          either denied access via memory map or protected using other
+          SoC mechanisms.
+
+      -- Config Command: dmem emu_base_address_range base_address
+               address_window_size
+          Set the emulated address and address window size.  Both of
+          these parameters must be aligned to page size.
+
+8.3 Transport Configuration
+===========================
+
+As noted earlier, depending on the version of OpenOCD you use, and the
+debug adapter you are using, several transports may be available to
+communicate with debug targets (or perhaps to program flash memory).
+ -- Command: transport list
+     displays the names of the transports supported by this version of
+     OpenOCD.
+
+ -- Command: transport select [transport_name]
+     Select which of the supported transports to use in this OpenOCD
+     session.
+
+     When invoked with 'transport_name', attempts to select the named
+     transport.  The transport must be supported by the debug adapter
+     hardware and by the version of OpenOCD you are using (including the
+     adapter's driver).  When invoked with no transport name:
+        - if no transport has been selected yet, it auto-selects the
+          first transport supported by the debug adapter
+        - it returns the name of the session's selected transport
+
+8.3.1 JTAG Transport
+--------------------
+
+JTAG is the original transport supported by OpenOCD, and most of the
+OpenOCD commands support it.  JTAG transports expose a chain of one or
+more Test Access Points (TAPs), each of which must be explicitly
+declared.  JTAG supports both debugging and boundary scan testing.
+Flash programming support is built on top of debug support.
+
+JTAG transport is selected with the command 'transport select jtag'.
+Unless your adapter uses either *note the hla interface driver:
+hla_interface. (in which case the command is 'transport select
+hla_jtag') or *note the st-link interface driver: st_link_dap_interface.
+(in which case the command is 'transport select dapdirect_jtag').
+
+8.3.2 SWD Transport
+-------------------
+
+SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
+Debug Access Point (DAP, which must be explicitly declared.  (SWD uses
+fewer signal wires than JTAG.) SWD is debug-oriented, and does not
+support boundary scan testing.  Flash programming support is built on
+top of debug support.  (Some processors support both JTAG and SWD.)
+
+SWD transport is selected with the command 'transport select swd'.
+Unless your adapter uses either *note the hla interface driver:
+hla_interface. (in which case the command is 'transport select hla_swd')
+or *note the st-link interface driver: st_link_dap_interface. (in which
+case the command is 'transport select dapdirect_swd').
+
+ -- Config Command: swd newdap ...
+     Declares a single DAP which uses SWD transport.  Parameters are
+     currently the same as "jtag newtap" but this is expected to change.
+
+The newer SWD devices (SW-DP v2 or SWJ-DP v2) support the multi-drop
+extension of SWD protocol: two or more devices can be connected to one
+SWD adapter.  SWD transport works in multi-drop mode if *note DAP:
+dap_create. is configured with both '-dp-id' and '-instance-id'
+parameters regardless how many DAPs are created.
+
+Not all adapters and adapter drivers support SWD multi-drop.  Only the
+following adapter drivers are SWD multi-drop capable: cmsis_dap (use an
+adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based.
+
+8.3.3 SPI Transport
+-------------------
+
+The Serial Peripheral Interface (SPI) is a general purpose transport
+which uses four wire signaling.  Some processors use it as part of a
+solution for flash programming.
+
+8.3.4 SWIM Transport
+--------------------
+
+The Single Wire Interface Module (SWIM) is a low-pin-count debug
+protocol used by the STMicroelectronics MCU family STM8 and documented
+in the User Manual UM470
+(https://www.st.com/resource/en/user_manual/cd00173911.pdf).
+
+SWIM does not support boundary scan testing nor multiple cores.
+
+The SWIM transport is selected with the command 'transport select swim'.
+
+The concept of TAPs does not fit in the protocol since SWIM does not
+implement a scan chain.  Nevertheless, the current SW model of OpenOCD
+requires defining a virtual SWIM TAP through the command 'swim newtap
+basename tap_type'.  The TAP definition must precede the target
+definition command 'target create target_name stm8 -chain-position
+basename.tap_type'.
+
+8.4 JTAG Speed
+==============
+
+JTAG clock setup is part of system setup.  It _does not belong with
+interface setup_ since any interface only knows a few of the constraints
+for the JTAG clock speed.  Sometimes the JTAG speed is changed during
+the target initialization process: (1) slow at reset, (2) program the
+CPU clocks, (3) run fast.  Both the "slow" and "fast" clock rates are
+functions of the oscillators used, the chip, the board design, and
+sometimes power management software that may be active.
+
+The speed used during reset, and the scan chain verification which
+follows reset, can be adjusted using a 'reset-start' target event
+handler.  It can then be reconfigured to a faster speed by a
+'reset-init' target event handler after it reprograms those CPU clocks,
+or manually (if something else, such as a boot loader, sets up those
+clocks).  *Note Target Events: targetevents.  When the initial low JTAG
+speed is a chip characteristic, perhaps because of a required oscillator
+speed, provide such a handler in the target config file.  When that
+speed is a function of a board-specific characteristic such as which
+speed oscillator is used, it belongs in the board config file instead.
+In both cases it's safest to also set the initial JTAG clock rate to
+that same slow speed, so that OpenOCD never starts up using a clock
+speed that's faster than the scan chain can support.
+
+     jtag_rclk 3000
+     $_TARGET.cpu configure -event reset-start { jtag_rclk 3000 }
+
+If your system supports adaptive clocking (RTCK), configuring JTAG to
+use that is probably the most robust approach.  However, it introduces
+delays to synchronize clocks; so it may not be the fastest solution.
+
+NOTE: Script writers should consider using 'jtag_rclk' instead of
+'adapter speed', but only for (ARM) cores and boards which support
+adaptive clocking.
+
+ -- Command: adapter speed max_speed_kHz
+     A non-zero speed is in KHZ. Hence: 3000 is 3mhz.  JTAG interfaces
+     usually support a limited number of speeds.  The speed actually
+     used won't be faster than the speed specified.
+
+     Chip data sheets generally include a top JTAG clock rate.  The
+     actual rate is often a function of a CPU core clock, and is
+     normally less than that peak rate.  For example, most ARM cores
+     accept at most one sixth of the CPU clock.
+
+     Speed 0 (khz) selects RTCK method.  *Note FAQ RTCK: faqrtck.  If
+     your system uses RTCK, you won't need to change the JTAG clocking
+     after setup.  Not all interfaces, boards, or targets support
+     "rtck".  If the interface device can not support it, an error is
+     returned when you try to use RTCK.
+
+ -- Function: jtag_rclk fallback_speed_kHz
+     This Tcl proc (defined in 'startup.tcl') attempts to enable
+     RTCK/RCLK. If that fails (maybe the interface, board, or target
+     doesn't support it), falls back to the specified frequency.
+          # Fall back to 3mhz if RTCK is not supported
+          jtag_rclk 3000
+
+
+File: openocd.info,  Node: Reset Configuration,  Next: TAP Declaration,  Prev: Debug Adapter Configuration,  Up: Top
+
+9 Reset Configuration
+*********************
+
+Every system configuration may require a different reset configuration.
+This can also be quite confusing.  Resets also interact with RESET-INIT
+event handlers, which do things like setting up clocks and DRAM, and
+JTAG clock rates.  (*Note JTAG Speed: jtagspeed.)  They can also
+interact with JTAG routers.  Please see the various board files for
+examples.
+
+     Note: To maintainers and integrators: Reset configuration touches
+     several things at once.  Normally the board configuration file
+     should define it and assume that the JTAG adapter supports
+     everything that's wired up to the board's JTAG connector.
+
+     However, the target configuration file could also make note of
+     something the silicon vendor has done inside the chip, which will
+     be true for most (or all) boards using that chip.  And when the
+     JTAG adapter doesn't support everything, the user configuration
+     file will need to override parts of the reset configuration
+     provided by other files.
+
+9.1 Types of Reset
+==================
+
+There are many kinds of reset possible through JTAG, but they may not
+all work with a given board and adapter.  That's part of why reset
+configuration can be error prone.
+
+   * _System Reset_ ...  the _SRST_ hardware signal resets all chips
+     connected to the JTAG adapter, such as processors, power management
+     chips, and I/O controllers.  Normally resets triggered with this
+     signal behave exactly like pressing a RESET button.
+   * _JTAG TAP Reset_ ...  the _TRST_ hardware signal resets just the
+     TAP controllers connected to the JTAG adapter.  Such resets should
+     not be visible to the rest of the system; resetting a device's TAP
+     controller just puts that controller into a known state.
+   * _Emulation Reset_ ...  many devices can be reset through JTAG
+     commands.  These resets are often distinguishable from system
+     resets, either explicitly (a "reset reason" register says so) or
+     implicitly (not all parts of the chip get reset).
+   * _Other Resets_ ...  system-on-chip devices often support several
+     other types of reset.  You may need to arrange that a watchdog
+     timer stops while debugging, preventing a watchdog reset.  There
+     may be individual module resets.
+
+In the best case, OpenOCD can hold SRST, then reset the TAPs via TRST
+and send commands through JTAG to halt the CPU at the reset vector
+before the 1st instruction is executed.  Then when it finally releases
+the SRST signal, the system is halted under debugger control before any
+code has executed.  This is the behavior required to support the 'reset
+halt' and 'reset init' commands; after 'reset init' a board-specific
+script might do things like setting up DRAM. (*Note Reset Command:
+resetcommand.)
+
+9.2 SRST and TRST Issues
+========================
+
+Because SRST and TRST are hardware signals, they can have a variety of
+system-specific constraints.  Some of the most common issues are:
+
+   * _Signal not available_ ...  Some boards don't wire SRST or TRST to
+     the JTAG connector.  Some JTAG adapters don't support such signals
+     even if they are wired up.  Use the 'reset_config' SIGNALS options
+     to say when either of those signals is not connected.  When SRST is
+     not available, your code might not be able to rely on controllers
+     having been fully reset during code startup.  Missing TRST is not a
+     problem, since JTAG-level resets can be triggered using with TMS
+     signaling.
+
+   * _Signals shorted_ ...  Sometimes a chip, board, or adapter will
+     connect SRST to TRST, instead of keeping them separate.  Use the
+     'reset_config' COMBINATION options to say when those signals aren't
+     properly independent.
+
+   * _Timing_ ...  Reset circuitry like a resistor/capacitor delay
+     circuit, reset supervisor, or on-chip features can extend the
+     effect of a JTAG adapter's reset for some time after the adapter
+     stops issuing the reset.  For example, there may be chip or board
+     requirements that all reset pulses last for at least a certain
+     amount of time; and reset buttons commonly have hardware
+     debouncing.  Use the 'adapter srst delay' and 'jtag_ntrst_delay'
+     commands to say when extra delays are needed.
+
+   * _Drive type_ ...  Reset lines often have a pullup resistor, letting
+     the JTAG interface treat them as open-drain signals.  But that's
+     not a requirement, so the adapter may need to use push/pull output
+     drivers.  Also, with weak pullups it may be advisable to drive
+     signals to both levels (push/pull) to minimize rise times.  Use the
+     'reset_config' TRST_TYPE and SRST_TYPE parameters to say how to
+     drive reset signals.
+
+   * _Special initialization_ ...  Targets sometimes need special JTAG
+     initialization sequences to handle chip-specific issues (not
+     limited to errata).  For example, certain JTAG commands might need
+     to be issued while the system as a whole is in a reset state (SRST
+     active) but the JTAG scan chain is usable (TRST inactive).  Many
+     systems treat combined assertion of SRST and TRST as a trigger for
+     a harder reset than SRST alone.  Such custom reset handling is
+     discussed later in this chapter.
+
+There can also be other issues.  Some devices don't fully conform to the
+JTAG specifications.  Trivial system-specific differences are common,
+such as SRST and TRST using slightly different names.  There are also
+vendors who distribute key JTAG documentation for their chips only to
+developers who have signed a Non-Disclosure Agreement (NDA).
+
+Sometimes there are chip-specific extensions like a requirement to use
+the normally-optional TRST signal (precluding use of JTAG adapters which
+don't pass TRST through), or needing extra steps to complete a TAP
+reset.
+
+In short, SRST and especially TRST handling may be very finicky, needing
+to cope with both architecture and board specific constraints.
+
+9.3 Commands for Handling Resets
+================================
+
+ -- Command: adapter srst pulse_width milliseconds
+     Minimum amount of time (in milliseconds) OpenOCD should wait after
+     asserting nSRST (active-low system reset) before allowing it to be
+     deasserted.
+
+ -- Command: adapter srst delay milliseconds
+     How long (in milliseconds) OpenOCD should wait after deasserting
+     nSRST (active-low system reset) before starting new JTAG
+     operations.  When a board has a reset button connected to SRST line
+     it will probably have hardware debouncing, implying you should use
+     this.
+
+ -- Command: jtag_ntrst_assert_width milliseconds
+     Minimum amount of time (in milliseconds) OpenOCD should wait after
+     asserting nTRST (active-low JTAG TAP reset) before allowing it to
+     be deasserted.
+
+ -- Command: jtag_ntrst_delay milliseconds
+     How long (in milliseconds) OpenOCD should wait after deasserting
+     nTRST (active-low JTAG TAP reset) before starting new JTAG
+     operations.
+
+ -- Command: reset_config mode_flag ...
+     This command displays or modifies the reset configuration of your
+     combination of JTAG board and target in target configuration
+     scripts.
+
+     Information earlier in this section describes the kind of problems
+     the command is intended to address (*note SRST and TRST Issues:
+     srstandtrstissues.).  As a rule this command belongs only in board
+     config files, describing issues like _board doesn't connect TRST_;
+     or in user config files, addressing limitations derived from a
+     particular combination of interface and board.  (An unlikely
+     example would be using a TRST-only adapter with a board that only
+     wires up SRST.)
+
+     The MODE_FLAG options can be specified in any order, but only one
+     of each type - SIGNALS, COMBINATION, GATES, TRST_TYPE, SRST_TYPE
+     and CONNECT_TYPE - may be specified at a time.  If you don't
+     provide a new value for a given type, its previous value (perhaps
+     the default) is unchanged.  For example, this means that you don't
+     need to say anything at all about TRST just to declare that if the
+     JTAG adapter should want to drive SRST, it must explicitly be
+     driven high ('srst_push_pull').
+
+        * SIGNALS can specify which of the reset signals are connected.
+          For example, If the JTAG interface provides SRST, but the
+          board doesn't connect that signal properly, then OpenOCD can't
+          use it.  Possible values are 'none' (the default),
+          'trst_only', 'srst_only' and 'trst_and_srst'.
+
+               Tip: If your board provides SRST and/or TRST through the
+               JTAG connector, you must declare that so those signals
+               can be used.
+
+        * The COMBINATION is an optional value specifying broken reset
+          signal implementations.  The default behaviour if no option
+          given is 'separate', indicating everything behaves normally.
+          'srst_pulls_trst' states that the test logic is reset together
+          with the reset of the system (e.g.  NXP LPC2000, "broken"
+          board layout), 'trst_pulls_srst' says that the system is reset
+          together with the test logic (only hypothetical, I haven't
+          seen hardware with such a bug, and can be worked around).
+          'combined' implies both 'srst_pulls_trst' and
+          'trst_pulls_srst'.
+
+        * The GATES tokens control flags that describe some cases where
+          JTAG may be unavailable during reset.  'srst_gates_jtag'
+          (default) indicates that asserting SRST gates the JTAG clock.
+          This means that no communication can happen on JTAG while SRST
+          is asserted.  Its converse is 'srst_nogate', indicating that
+          JTAG commands can safely be issued while SRST is active.
+
+        * The CONNECT_TYPE tokens control flags that describe some cases
+          where SRST is asserted while connecting to the target.
+          'srst_nogate' is required to use this option.
+          'connect_deassert_srst' (default) indicates that SRST will not
+          be asserted while connecting to the target.  Its converse is
+          'connect_assert_srst', indicating that SRST will be asserted
+          before any target connection.  Only some targets support this
+          feature, STM32 and STR9 are examples.  This feature is useful
+          if you are unable to connect to your target due to incorrect
+          options byte config or illegal program execution.
+
+     The optional TRST_TYPE and SRST_TYPE parameters allow the driver
+     mode of each reset line to be specified.  These values only affect
+     JTAG interfaces with support for different driver modes, like the
+     Amontec JTAGkey and JTAG Accelerator.  Also, they are necessarily
+     ignored if the relevant signal (TRST or SRST) is not connected.
+
+        * Possible TRST_TYPE driver modes for the test reset signal
+          (TRST) are the default 'trst_push_pull', and
+          'trst_open_drain'.  Most boards connect this signal to a
+          pulldown, so the JTAG TAPs never leave reset unless they are
+          hooked up to a JTAG adapter.
+
+        * Possible SRST_TYPE driver modes for the system reset signal
+          (SRST) are the default 'srst_open_drain', and
+          'srst_push_pull'.  Most boards connect this signal to a
+          pullup, and allow the signal to be pulled low by various
+          events including system power-up and pressing a reset button.
+
+9.4 Custom Reset Handling
+=========================
+
+OpenOCD has several ways to help support the various reset mechanisms
+provided by chip and board vendors.  The commands shown in the previous
+section give standard parameters.  There are also _event handlers_
+associated with TAPs or Targets.  Those handlers are Tcl procedures you
+can provide, which are invoked at particular points in the reset
+sequence.
+
+_When SRST is not an option_ you must set up a 'reset-assert' event
+handler for your target.  For example, some JTAG adapters don't include
+the SRST signal; and some boards have multiple targets, and you won't
+always want to reset everything at once.
+
+After configuring those mechanisms, you might still find your board
+doesn't start up or reset correctly.  For example, maybe it needs a
+slightly different sequence of SRST and/or TRST manipulations, because
+of quirks that the 'reset_config' mechanism doesn't address; or
+asserting both might trigger a stronger reset, which needs special
+attention.
+
+Experiment with lower level operations, such as 'adapter assert',
+'adapter deassert' and the 'jtag arp_*' operations shown here, to find a
+sequence of operations that works.  *Note JTAG Commands::.  When you
+find a working sequence, it can be used to override 'jtag_init', which
+fires during OpenOCD startup (*note Configuration Stage:
+configurationstage.); or 'init_reset', which fires during reset
+processing.
+
+You might also want to provide some project-specific reset schemes.  For
+example, on a multi-target board the standard 'reset' command would
+reset all targets, but you may need the ability to reset only one target
+at time and thus want to avoid using the board-wide SRST signal.
+
+ -- Overridable Procedure: init_reset mode
+     This is invoked near the beginning of the 'reset' command, usually
+     to provide as much of a cold (power-up) reset as practical.  By
+     default it is also invoked from 'jtag_init' if the scan chain does
+     not respond to pure JTAG operations.  The MODE parameter is the
+     parameter given to the low level reset command ('halt', 'init', or
+     'run'), 'setup', or potentially some other value.
+
+     The default implementation just invokes 'jtag arp_init-reset'.
+     Replacements will normally build on low level JTAG operations such
+     as 'adapter assert' and 'adapter deassert'.  Operations here must
+     not address individual TAPs (or their associated targets) until the
+     JTAG scan chain has first been verified to work.
+
+     Implementations must have verified the JTAG scan chain before they
+     return.  This is done by calling 'jtag arp_init' (or 'jtag
+     arp_init-reset').
+
+ -- Command: jtag arp_init
+     This validates the scan chain using just the four standard JTAG
+     signals (TMS, TCK, TDI, TDO). It starts by issuing a JTAG-only
+     reset.  Then it performs checks to verify that the scan chain
+     configuration matches the TAPs it can observe.  Those checks
+     include checking IDCODE values for each active TAP, and verifying
+     the length of their instruction registers using TAP '-ircapture'
+     and '-irmask' values.  If these tests all pass, TAP 'setup' events
+     are issued to all TAPs with handlers for that event.
+
+ -- Command: jtag arp_init-reset
+     This uses TRST and SRST to try resetting everything on the JTAG
+     scan chain (and anything else connected to SRST). It then invokes
+     the logic of 'jtag arp_init'.
+
+
+File: openocd.info,  Node: TAP Declaration,  Next: CPU Configuration,  Prev: Reset Configuration,  Up: Top
+
+10 TAP Declaration
+******************
+
+_Test Access Ports_ (TAPs) are the core of JTAG. TAPs serve many roles,
+including:
+
+   * Debug Target A CPU TAP can be used as a GDB debug target.
+   * Flash Programming Some chips program the flash directly via JTAG.
+     Others do it indirectly, making a CPU do it.
+   * Program Download Using the same CPU support GDB uses, you can
+     initialize a DRAM controller, download code to DRAM, and then start
+     running that code.
+   * Boundary Scan Most chips support boundary scan, which helps test
+     for board assembly problems like solder bridges and missing
+     connections.
+
+OpenOCD must know about the active TAPs on your board(s).  Setting up
+the TAPs is the core task of your configuration files.  Once those TAPs
+are set up, you can pass their names to code which sets up CPUs and
+exports them as GDB targets, probes flash memory, performs low-level
+JTAG operations, and more.
+
+10.1 Scan Chains
+================
+
+TAPs are part of a hardware "scan chain", which is a daisy chain of
+TAPs.  They also need to be added to OpenOCD's software mirror of that
+hardware list, giving each member a name and associating other data with
+it.  Simple scan chains, with a single TAP, are common in systems with a
+single microcontroller or microprocessor.  More complex chips may have
+several TAPs internally.  Very complex scan chains might have a dozen or
+more TAPs: several in one chip, more in the next, and connecting to
+other boards with their own chips and TAPs.
+
+You can display the list with the 'scan_chain' command.  (Don't confuse
+this with the list displayed by the 'targets' command, presented in the
+next chapter.  That only displays TAPs for CPUs which are configured as
+debugging targets.)  Here's what the scan chain might look like for a
+chip more than one TAP:
+
+   TapName            Enabled IdCode     Expected   IrLen IrCap IrMask
+-- ------------------ ------- ---------- ---------- ----- ----- ------
+ 0 omap5912.dsp          Y    0x03df1d81 0x03df1d81    38 0x01  0x03
+ 1 omap5912.arm          Y    0x0692602f 0x0692602f     4 0x01  0x0f
+ 2 omap5912.unknown      Y    0x00000000 0x00000000     8 0x01  0x03
+
+OpenOCD can detect some of that information, but not all of it.  *Note
+Autoprobing: autoprobing.  Unfortunately, those TAPs can't always be
+autoconfigured, because not all devices provide good support for that.
+JTAG doesn't require supporting IDCODE instructions, and chips with JTAG
+routers may not link TAPs into the chain until they are told to do so.
+
+The configuration mechanism currently supported by OpenOCD requires
+explicit configuration of all TAP devices using 'jtag newtap' commands,
+as detailed later in this chapter.  A command like this would declare
+one tap and name it 'chip1.cpu':
+
+     jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
+
+Each target configuration file lists the TAPs provided by a given chip.
+Board configuration files combine all the targets on a board, and so
+forth.  Note that _the order in which TAPs are declared is very
+important._  That declaration order must match the order in the JTAG
+scan chain, both inside a single chip and between them.  *Note FAQ TAP
+Order: faqtaporder.
+
+For example, the STMicroelectronics STR912 chip has three separate
+TAPs(1).  To configure those taps, 'target/str912.cfg' includes commands
+something like this:
+
+     jtag newtap str912 flash ... params ...
+     jtag newtap str912 cpu ... params ...
+     jtag newtap str912 bs ... params ...
+
+Actual config files typically use a variable such as '$_CHIPNAME'
+instead of literals like 'str912', to support more than one chip of each
+type.  *Note Config File Guidelines::.
+
+ -- Command: jtag names
+     Returns the names of all current TAPs in the scan chain.  Use 'jtag
+     cget' or 'jtag tapisenabled' to examine attributes and state of
+     each TAP.
+          foreach t [jtag names] {
+              puts [format "TAP: %s\n" $t]
+          }
+
+ -- Command: scan_chain
+     Displays the TAPs in the scan chain configuration, and their
+     status.  The set of TAPs listed by this command is fixed by exiting
+     the OpenOCD configuration stage, but systems with a JTAG router can
+     enable or disable TAPs dynamically.
+
+10.2 TAP Names
+==============
+
+When TAP objects are declared with 'jtag newtap', a "dotted.name" is
+created for the TAP, combining the name of a module (usually a chip) and
+a label for the TAP. For example: 'xilinx.tap', 'str912.flash',
+'omap3530.jrc', 'dm6446.dsp', or 'stm32.cpu'.  Many other commands use
+that dotted.name to manipulate or refer to the TAP. For example, CPU
+configuration uses the name, as does declaration of NAND or NOR flash
+banks.
+
+The components of a dotted name should follow "C" symbol name rules:
+start with an alphabetic character, then numbers and underscores are OK;
+while others (including dots!)  are not.
+
+10.3 TAP Declaration Commands
+=============================
+
+ -- Config Command: jtag newtap chipname tapname configparams...
+     Declares a new TAP with the dotted name CHIPNAME.TAPNAME, and
+     configured according to the various CONFIGPARAMS.
+
+     The CHIPNAME is a symbolic name for the chip.  Conventionally
+     target config files use '$_CHIPNAME', defaulting to the model name
+     given by the chip vendor but overridable.
+
+     The TAPNAME reflects the role of that TAP, and should follow this
+     convention:
+
+        * 'bs' - For boundary scan if this is a separate TAP;
+        * 'cpu' - The main CPU of the chip, alternatively 'arm' and
+          'dsp' on chips with both ARM and DSP CPUs, 'arm1' and 'arm2'
+          on chips with two ARMs, and so forth;
+        * 'etb' - For an embedded trace buffer (example: an ARM ETB11);
+        * 'flash' - If the chip has a flash TAP, like the str912;
+        * 'jrc' - For JTAG route controller (example: the ICEPick
+          modules on many Texas Instruments chips, like the OMAP3530 on
+          Beagleboards);
+        * 'tap' - Should be used only for FPGA- or CPLD-like devices
+          with a single TAP;
+        * 'unknownN' - If you have no idea what the TAP is for (N is a
+          number);
+        * _when in doubt_ - Use the chip maker's name in their data
+          sheet.  For example, the Freescale i.MX31 has a SDMA (Smart
+          DMA) with a JTAG TAP; that TAP should be named 'sdma'.
+
+     Every TAP requires at least the following CONFIGPARAMS:
+
+        * '-irlen' NUMBER
+          The length in bits of the instruction register, such as 4 or 5
+          bits.
+
+     A TAP may also provide optional CONFIGPARAMS:
+
+        * '-disable' (or '-enable')
+          Use the '-disable' parameter to flag a TAP which is not linked
+          into the scan chain after a reset using either TRST or the
+          JTAG state machine's RESET state.  You may use '-enable' to
+          highlight the default state (the TAP is linked in).  *Note
+          Enabling and Disabling TAPs: enablinganddisablingtaps.
+        * '-expected-id' NUMBER
+          A non-zero NUMBER represents a 32-bit IDCODE which you expect
+          to find when the scan chain is examined.  These codes are not
+          required by all JTAG devices.  _Repeat the option_ as many
+          times as required if more than one ID code could appear (for
+          example, multiple versions).  Specify NUMBER as zero to
+          suppress warnings about IDCODE values that were found but not
+          included in the list.
+
+          Provide this value if at all possible, since it lets OpenOCD
+          tell when the scan chain it sees isn't right.  These values
+          are provided in vendors' chip documentation, usually a
+          technical reference manual.  Sometimes you may need to probe
+          the JTAG hardware to find these values.  *Note Autoprobing:
+          autoprobing.
+        * '-ignore-version'
+          Specify this to ignore the JTAG version field in the
+          '-expected-id' option.  When vendors put out multiple versions
+          of a chip, or use the same JTAG-level ID for several
+          largely-compatible chips, it may be more practical to ignore
+          the version field than to update config files to handle all of
+          the various chip IDs.  The version field is defined as bit
+          28-31 of the IDCODE.
+        * '-ignore-bypass'
+          Specify this to ignore the 'bypass' bit of the idcode.  Some
+          vendor put an invalid idcode regarding this bit.  Specify this
+          to ignore this bit and to not consider this tap in bypass
+          mode.
+        * '-ircapture' NUMBER
+          The bit pattern loaded by the TAP into the JTAG shift register
+          on entry to the IRCAPTURE state, such as 0x01.  JTAG requires
+          the two LSBs of this value to be 01.  By default, '-ircapture'
+          and '-irmask' are set up to verify that two-bit value.  You
+          may provide additional bits if you know them, or indicate that
+          a TAP doesn't conform to the JTAG specification.
+        * '-irmask' NUMBER
+          A mask used with '-ircapture' to verify that instruction scans
+          work correctly.  Such scans are not used by OpenOCD except to
+          verify that there seems to be no problems with JTAG scan chain
+          operations.
+        * '-ignore-syspwrupack'
+          Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP
+          CTRL/STAT register during initial examination and when
+          checking the sticky error bit.  This bit is normally checked
+          after setting the CSYSPWRUPREQ bit, but some devices do not
+          set the ack bit until sometime later.
+        * '-ir-bypass' NUMBER
+          Vendor specific bypass instruction, required by some
+          hierarchical JTAG routers where the normal BYPASS instruction
+          bypasses the whole router and a vendor specific bypass
+          instruction is required to access child nodes.
+
+10.4 Other TAP commands
+=======================
+
+ -- Command: jtag cget dotted.name '-idcode'
+     Get the value of the IDCODE found in hardware.
+
+ -- Command: jtag cget dotted.name '-event' event_name
+ -- Command: jtag configure dotted.name '-event' event_name handler
+     At this writing this TAP attribute mechanism is limited and used
+     mostly for event handling.  (It is not a direct analogue of the
+     'cget'/'configure' mechanism for debugger targets.)  See the next
+     section for information about the available events.
+
+     The 'configure' subcommand assigns an event handler, a TCL string
+     which is evaluated when the event is triggered.  The 'cget'
+     subcommand returns that handler.
+
+10.5 TAP Events
+===============
+
+OpenOCD includes two event mechanisms.  The one presented here applies
+to all JTAG TAPs.  The other applies to debugger targets, which are
+associated with certain TAPs.
+
+The TAP events currently defined are:
+
+   * post-reset
+     The TAP has just completed a JTAG reset.  The tap may still be in
+     the JTAG RESET state.  Handlers for these events might perform
+     initialization sequences such as issuing TCK cycles, TMS sequences
+     to ensure exit from the ARM SWD mode, and more.
+
+     Because the scan chain has not yet been verified, handlers for
+     these events _should not issue commands which scan the JTAG IR or
+     DR registers_ of any particular target.  NOTE: As this is written
+     (September 2009), nothing prevents such access.
+   * setup
+     The scan chain has been reset and verified.  This handler may
+     enable TAPs as needed.
+   * tap-disable
+     The TAP needs to be disabled.  This handler should implement 'jtag
+     tapdisable' by issuing the relevant JTAG commands.
+   * tap-enable
+     The TAP needs to be enabled.  This handler should implement 'jtag
+     tapenable' by issuing the relevant JTAG commands.
+
+If you need some action after each JTAG reset which isn't actually
+specific to any TAP (since you can't yet trust the scan chain's contents
+to be accurate), you might:
+
+     jtag configure CHIP.jrc -event post-reset {
+       echo "JTAG Reset done"
+       ... non-scan jtag operations to be done after reset
+     }
+
+10.6 Enabling and Disabling TAPs
+================================
+
+In some systems, a "JTAG Route Controller" (JRC) is used to enable
+and/or disable specific JTAG TAPs.  Many ARM-based chips from Texas
+Instruments include an "ICEPick" module, which is a JRC. Such chips
+include DaVinci and OMAP3 processors.
+
+A given TAP may not be visible until the JRC has been told to link it
+into the scan chain; and if the JRC has been told to unlink that TAP, it
+will no longer be visible.  Such routers address problems that JTAG
+"bypass mode" ignores, such as:
+
+   * The scan chain can only go as fast as its slowest TAP.
+   * Having many TAPs slows instruction scans, since all TAPs receive
+     new instructions.
+   * TAPs in the scan chain must be powered up, which wastes power and
+     prevents debugging some power management mechanisms.
+
+The IEEE 1149.1 JTAG standard has no concept of a "disabled" tap, as
+implied by the existence of JTAG routers.  However, the upcoming IEEE
+1149.7 framework (layered on top of JTAG) does include a kind of JTAG
+router functionality.
+
+In OpenOCD, tap enabling/disabling is invoked by the Tcl commands shown
+below, and is implemented using TAP event handlers.  So for example,
+when defining a TAP for a CPU connected to a JTAG router, your
+'target.cfg' file should define TAP event handlers using code that looks
+something like this:
+
+     jtag configure CHIP.cpu -event tap-enable {
+       ... jtag operations using CHIP.jrc
+     }
+     jtag configure CHIP.cpu -event tap-disable {
+       ... jtag operations using CHIP.jrc
+     }
+
+Then you might want that CPU's TAP enabled almost all the time:
+
+     jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
+
+Note how that particular setup event handler declaration uses quotes to
+evaluate '$CHIP' when the event is configured.  Using brackets { } would
+cause it to be evaluated later, at runtime, when it might have a
+different value.
+
+ -- Command: jtag tapdisable dotted.name
+     If necessary, disables the tap by sending it a 'tap-disable' event.
+     Returns the string "1" if the tap specified by DOTTED.NAME is
+     enabled, and "0" if it is disabled.
+
+ -- Command: jtag tapenable dotted.name
+     If necessary, enables the tap by sending it a 'tap-enable' event.
+     Returns the string "1" if the tap specified by DOTTED.NAME is
+     enabled, and "0" if it is disabled.
+
+ -- Command: jtag tapisenabled dotted.name
+     Returns the string "1" if the tap specified by DOTTED.NAME is
+     enabled, and "0" if it is disabled.
+
+          Note: Humans will find the 'scan_chain' command more helpful
+          for querying the state of the JTAG taps.
+
+10.7 Autoprobing
+================
+
+TAP configuration is the first thing that needs to be done after
+interface and reset configuration.  Sometimes it's hard finding out what
+TAPs exist, or how they are identified.  Vendor documentation is not
+always easy to find and use.
+
+To help you get past such problems, OpenOCD has a limited _autoprobing_
+ability to look at the scan chain, doing a "blind interrogation" and
+then reporting the TAPs it finds.  To use this mechanism, start the
+OpenOCD server with only data that configures your JTAG interface, and
+arranges to come up with a slow clock (many devices don't support fast
+JTAG clocks right when they come out of reset).
+
+For example, your 'openocd.cfg' file might have:
+
+     source [find interface/olimex-arm-usb-tiny-h.cfg]
+     reset_config trst_and_srst
+     jtag_rclk 8
+
+When you start the server without any TAPs configured, it will attempt
+to autoconfigure the TAPs.  There are two parts to this:
+
+  1. _TAP discovery_ ...  After a JTAG reset (sometimes a system reset
+     may be needed too), each TAP's data registers will hold the
+     contents of either the IDCODE or BYPASS register.  If JTAG
+     communication is working, OpenOCD will see each TAP, and report
+     what '-expected-id' to use with it.
+  2. _IR Length discovery_ ...  Unfortunately JTAG does not provide a
+     reliable way to find out the value of the '-irlen' parameter to use
+     with a TAP that is discovered.  If OpenOCD can discover the length
+     of a TAP's instruction register, it will report it.  Otherwise you
+     may need to consult vendor documentation, such as chip data sheets
+     or BSDL files.
+
+In many cases your board will have a simple scan chain with just a
+single device.  Here's what OpenOCD reported with one board that's a bit
+more complex:
+
+     clock speed 8 kHz
+     There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
+     AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
+     AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
+     AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
+     AUTO auto0.tap - use "... -irlen 4"
+     AUTO auto1.tap - use "... -irlen 4"
+     AUTO auto2.tap - use "... -irlen 6"
+     no gdb ports allocated as no target has been specified
+
+Given that information, you should be able to either find some existing
+config files to use, or create your own.  If you create your own, you
+would configure from the bottom up: first a 'target.cfg' file with these
+TAPs, any targets associated with them, and any on-chip resources; then
+a 'board.cfg' with off-chip resources, clocking, and so forth.
+
+10.8 DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
+=======================================================
+
+Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is no longer
+implicitly created together with the target.  It must be explicitly
+declared using the 'dap create' command.  For all ARMv6-M, ARMv7 and
+ARMv8 targets, the option "'-dap' DAP_NAME" has to be used instead of
+"'-chain-position' DOTTED.NAME" when the target is created.
+
+The 'dap' command group supports the following sub-commands:
+
+ -- Command: dap create dap_name '-chain-position' dotted.name
+          configparams...
+     Declare a DAP instance named DAP_NAME linked to the JTAG tap
+     DOTTED.NAME.  This also creates a new command ('dap_name') which is
+     used for various purposes including additional configuration.
+     There can only be one DAP for each JTAG tap in the system.
+
+     A DAP may also provide optional CONFIGPARAMS:
+
+        * '-adiv5' Specify that it's an ADIv5 DAP. This is the default
+          if not specified.
+        * '-adiv6' Specify that it's an ADIv6 DAP.
+        * '-ignore-syspwrupack' Specify this to ignore the CSYSPWRUPACK
+          bit in the ARM DAP DP CTRL/STAT register during initial
+          examination and when checking the sticky error bit.  This bit
+          is normally checked after setting the CSYSPWRUPREQ bit, but
+          some devices do not set the ack bit until sometime later.
+
+        * '-dp-id' NUMBER
+          Debug port identification number for SWD DPv2 multidrop.  The
+          NUMBER is written to bits 0..27 of DP TARGETSEL during DP
+          selection.  To find the id number of a single connected device
+          read DP TARGETID: 'device.dap dpreg 0x24' Use bits 0..27 of
+          TARGETID.
+
+        * '-instance-id' NUMBER
+          Instance identification number for SWD DPv2 multidrop.  The
+          NUMBER is written to bits 28..31 of DP TARGETSEL during DP
+          selection.  To find the instance number of a single connected
+          device read DP DLPIDR: 'device.dap dpreg 0x34' The instance
+          number is in bits 28..31 of DLPIDR value.
+
+ -- Command: dap names
+     This command returns a list of all registered DAP objects.  It it
+     useful mainly for TCL scripting.
+
+ -- Command: dap info [NUM|'root']
+     Displays the ROM table for MEM-AP NUM, defaulting to the currently
+     selected AP of the currently selected target.  On ADIv5 DAP NUM is
+     the numeric index of the AP. On ADIv6 DAP NUM is the base address
+     of the AP. With ADIv6 only, 'root' specifies the root ROM table.
+
+ -- Command: dap init
+     Initialize all registered DAPs.  This command is used internally
+     during initialization.  It can be issued at any time after the
+     initialization, too.
+
+The following commands exist as subcommands of DAP instances:
+
+ -- Command: $dap_name info [NUM|'root']
+     Displays the ROM table for MEM-AP NUM, defaulting to the currently
+     selected AP. On ADIv5 DAP NUM is the numeric index of the AP. On
+     ADIv6 DAP NUM is the base address of the AP. With ADIv6 only,
+     'root' specifies the root ROM table.
+
+ -- Command: $dap_name apid [num]
+     Displays ID register from AP NUM, defaulting to the currently
+     selected AP. On ADIv5 DAP NUM is the numeric index of the AP. On
+     ADIv6 DAP NUM is the base address of the AP.
+
+ -- Command: $dap_name apreg ap_num reg [value]
+     Displays content of a register REG from AP AP_NUM or set a new
+     value VALUE.  On ADIv5 DAP AP_NUM is the numeric index of the AP.
+     On ADIv6 DAP AP_NUM is the base address of the AP. REG is byte
+     address of a word register, 0, 4, 8 ...  0xfc.
+
+ -- Command: $dap_name apsel [num]
+     Select AP NUM, defaulting to 0.  On ADIv5 DAP NUM is the numeric
+     index of the AP. On ADIv6 DAP NUM is the base address of the AP.
+
+ -- Command: $dap_name dpreg reg [value]
+     Displays the content of DP register at address REG, or set it to a
+     new value VALUE.
+
+     In case of SWD, REG is a value in packed format dpbanksel << 4 |
+     addr and assumes values 0, 4, 8 ...  0xfc.  In case of JTAG it only
+     assumes values 0, 4, 8 and 0xc.
+
+     _Note:_ Consider using 'poll off' to avoid any disturbing
+     background activity by OpenOCD while you are operating at such
+     low-level.
+
+ -- Command: $dap_name baseaddr [num]
+     Displays debug base address from MEM-AP NUM, defaulting to the
+     currently selected AP. On ADIv5 DAP NUM is the numeric index of the
+     AP. On ADIv6 DAP NUM is the base address of the AP.
+
+ -- Command: $dap_name memaccess [value]
+     Displays the number of extra tck cycles in the JTAG idle to use for
+     MEM-AP memory bus access [0-255], giving additional time to respond
+     to reads.  If VALUE is defined, first assigns that.
+
+ -- Command: $dap_name apcsw [value [mask]]
+     Displays or changes CSW bit pattern for MEM-AP transfers.
+
+     At the begin of each memory access the CSW pattern is extended
+     (bitwise or-ed) by "Size" and "AddrInc" bit-fields according to
+     transfer requirements and the result is written to the real CSW
+     register.  All bits except dynamically updated fields "Size" and
+     "AddrInc" can be changed by changing the CSW pattern.  Refer to ARM
+     ADI v5 manual chapter 7.6.4 and appendix A for details.
+
+     Use VALUE only syntax if you want to set the new CSW pattern as a
+     whole.  The example sets HPROT1 bit (required by Cortex-M) and
+     clears the rest of the pattern:
+          kx.dap apcsw 0x2000000
+
+     If MASK is also used, the CSW pattern is changed only on bit
+     positions where the mask bit is 1.  The following example sets
+     HPROT3 (cacheable) and leaves the rest of the pattern intact.  It
+     configures memory access through DCache on Cortex-M7.
+          set CSW_HPROT3_CACHEABLE [expr {1 << 27}]
+          samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
+
+     Another example clears SPROT bit and leaves the rest of pattern
+     intact:
+          set CSW_SPROT [expr {1 << 30}]
+          samv.dap apcsw 0 $CSW_SPROT
+
+     _Note:_ If you want to check the real value of CSW, not CSW
+     pattern, use 'xxx.dap apreg 0'.  *Note DAP subcommand apreg::.
+
+     _Warning:_ Some of the CSW bits are vital for working memory
+     transfer.  If you set a wrong CSW pattern and MEM-AP stopped
+     working, use the following example with a proper dap name:
+          xxx.dap apcsw default
+
+ -- Config Command: $dap_name ti_be_32_quirks ['enable']
+     Set/get quirks mode for TI TMS450/TMS570 processors Disabled by
+     default
+
+ -- Config Command: $dap_name nu_npcx_quirks ['enable']
+     Set/get quirks mode for Nuvoton NPCX/NPCD MCU families Disabled by
+     default
+
+   ---------- Footnotes ----------
+
+   (1) See the ST document titled: _STR91xFAxxx, Section 3.15 Jtag
+Interface, Page: 28/102, Figure 3: JTAG chaining inside the STR91xFA_.
+
+
+
+File: openocd.info,  Node: CPU Configuration,  Next: Flash Commands,  Prev: TAP Declaration,  Up: Top
+
+11 CPU Configuration
+********************
+
+This chapter discusses how to set up GDB debug targets for CPUs.  You
+can also access these targets without GDB (*note Architecture and Core
+Commands::, and *note Target State handling: targetstatehandling.) and
+through various kinds of NAND and NOR flash commands.  If you have
+multiple CPUs you can have multiple such targets.
+
+We'll start by looking at how to examine the targets you have, then look
+at how to add one more target and how to configure it.
+
+11.1 Target List
+================
+
+All targets that have been set up are part of a list, where each member
+has a name.  That name should normally be the same as the TAP name.  You
+can display the list with the 'targets' (plural!)  command.  This
+display often has only one CPU; here's what it might look like with more
+than one:
+    TargetName         Type       Endian TapName            State
+--  ------------------ ---------- ------ ------------------ ------------
+ 0* at91rm9200.cpu     arm920t    little at91rm9200.cpu     running
+ 1  MyTarget           cortex_m   little mychip.foo         tap-disabled
+
+One member of that list is the "current target", which is implicitly
+referenced by many commands.  It's the one marked with a '*' near the
+target name.  In particular, memory addresses often refer to the address
+space seen by that current target.  Commands like 'mdw' (memory display
+words) and 'flash erase_address' (erase NOR flash blocks) are examples;
+and there are many more.
+
+Several commands let you examine the list of targets:
+
+ -- Command: target current
+     Returns the name of the current target.
+
+ -- Command: target names
+     Lists the names of all current targets in the list.
+          foreach t [target names] {
+              puts [format "Target: %s\n" $t]
+          }
+
+ -- Command: targets [name]
+     _Note: the name of this command is plural.  Other target command
+     names are singular._
+
+     With no parameter, this command displays a table of all known
+     targets in a user friendly form.
+
+     With a parameter, this command sets the current target to the given
+     target with the given NAME; this is only relevant on boards which
+     have more than one target.
+
+11.2 Target CPU Types
+=====================
+
+Each target has a "CPU type", as shown in the output of the 'targets'
+command.  You need to specify that type when calling 'target create'.
+The CPU type indicates more than just the instruction set.  It also
+indicates how that instruction set is implemented, what kind of debug
+support it integrates, whether it has an MMU (and if so, what kind),
+what core-specific commands may be available (*note Architecture and
+Core Commands::), and more.
+
+It's easy to see what target types are supported, since there's a
+command to list them.
+
+ -- Command: target types
+     Lists all supported target types.  At this writing, the supported
+     CPU types are:
+
+        * 'aarch64' - this is an ARMv8-A core with an MMU.
+        * 'arm11' - this is a generation of ARMv6 cores.
+        * 'arm720t' - this is an ARMv4 core with an MMU.
+        * 'arm7tdmi' - this is an ARMv4 core.
+        * 'arm920t' - this is an ARMv4 core with an MMU.
+        * 'arm926ejs' - this is an ARMv5 core with an MMU.
+        * 'arm946e' - this is an ARMv5 core with an MMU.
+        * 'arm966e' - this is an ARMv5 core.
+        * 'arm9tdmi' - this is an ARMv4 core.
+        * 'avr' - implements Atmel's 8-bit AVR instruction set.
+          (Support for this is preliminary and incomplete.)
+        * 'avr32_ap7k' - this an AVR32 core.
+        * 'cortex_a' - this is an ARMv7-A core with an MMU.
+        * 'cortex_m' - this is an ARMv7-M core, supporting only the
+          compact Thumb2 instruction set.  Supports also ARMv6-M and
+          ARMv8-M cores
+        * 'cortex_r4' - this is an ARMv7-R core.
+        * 'dragonite' - resembles arm966e.
+        * 'dsp563xx' - implements Freescale's 24-bit DSP. (Support for
+          this is still incomplete.)
+        * 'dsp5680xx' - implements Freescale's 5680x DSP.
+        * 'esirisc' - this is an EnSilica eSi-RISC core.  The current
+          implementation supports eSi-32xx cores.
+        * 'esp32' - this is an Espressif SoC with dual Xtensa cores.
+        * 'esp32s2' - this is an Espressif SoC with single Xtensa core.
+        * 'esp32s3' - this is an Espressif SoC with dual Xtensa cores.
+        * 'fa526' - resembles arm920 (w/o Thumb).
+        * 'feroceon' - resembles arm926.
+        * 'hla_target' - a Cortex-M alternative to work with HL adapters
+          like ST-Link.
+        * 'ls1_sap' - this is the SAP on NXP LS102x CPUs, allowing
+          access to physical memory addresses independently of CPU
+          cores.
+        * 'mem_ap' - this is an ARM debug infrastructure Access Port
+          without a CPU, through which bus read and write cycles can be
+          generated; it may be useful for working with non-CPU hardware
+          behind an AP or during development of support for new CPUs.
+          It's possible to connect a GDB client to this target (the GDB
+          port has to be specified, *Note option -gdb-port:
+          gdbportoverride.), and a fake ARM core will be emulated to
+          comply to GDB remote protocol.
+        * 'mips_m4k' - a MIPS core.
+        * 'mips_mips64' - a MIPS64 core.
+        * 'or1k' - this is an OpenRISC 1000 core.  The current
+          implementation supports three JTAG TAP cores:
+             - 'OpenCores TAP' (See:
+               )
+             - 'Altera Virtual JTAG TAP' (See:
+               )
+             - 'Xilinx BSCAN_* virtual JTAG interface' (See:
+               )
+          And two debug interfaces cores:
+             - 'Advanced debug interface'
+               (See: )
+             - 'SoC Debug Interface'
+               (See: )
+        * 'quark_d20xx' - an Intel Quark D20xx core.
+        * 'quark_x10xx' - an Intel Quark X10xx core.
+        * 'riscv' - a RISC-V core.
+        * 'stm8' - implements an STM8 core.
+        * 'testee' - a dummy target for cases without a real CPU, e.g.
+          CPLD.
+        * 'xscale' - this is actually an architecture, not a CPU type.
+          It is based on the ARMv5 architecture.
+        * 'xtensa' - this is a generic Cadence/Tensilica Xtensa core.
+
+To avoid being confused by the variety of ARM based cores, remember this
+key point: _ARM is a technology licencing company_.  (See:
+.)  The CPU name used by OpenOCD will reflect the
+CPU design that was licensed, not a vendor brand which incorporates that
+design.  Name prefixes like arm7, arm9, arm11, and cortex reflect design
+generations; while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
+reflect an architecture version implemented by a CPU design.
+
+11.3 Target Configuration
+=========================
+
+Before creating a "target", you must have added its TAP to the scan
+chain.  When you've added that TAP, you will have a 'dotted.name' which
+is used to set up the CPU support.  The chip-specific configuration file
+will normally configure its CPU(s) right after it adds all of the chip's
+TAPs to the scan chain.
+
+Although you can set up a target in one step, it's often clearer if you
+use shorter commands and do it in two steps: create it, then configure
+optional parts.  All operations on the target after it's created will
+use a new command, created as part of target creation.
+
+The two main things to configure after target creation are a work area,
+which usually has target-specific defaults even if the board setup code
+overrides them later; and event handlers (*note Target Events:
+targetevents.), which tend to be much more board-specific.  The key
+steps you use might look something like this
+
+     dap create mychip.dap -chain-position mychip.cpu
+     target create MyTarget cortex_m -dap mychip.dap
+     MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
+     MyTarget configure -event reset-deassert-pre { jtag_rclk 5 }
+     MyTarget configure -event reset-init { myboard_reinit }
+
+You should specify a working area if you can; typically it uses some
+on-chip SRAM. Such a working area can speed up many things, including
+bulk writes to target memory; flash operations like checking to see if
+memory needs to be erased; GDB memory checksumming; and more.
+
+     Warning: On more complex chips, the work area can become
+     inaccessible when application code (such as an operating system)
+     enables or disables the MMU. For example, the particular MMU
+     context used to access the virtual address will probably matter ...
+     and that context might not have easy access to other addresses
+     needed.  At this writing, OpenOCD doesn't have much MMU
+     intelligence.
+
+It's often very useful to define a 'reset-init' event handler.  For
+systems that are normally used with a boot loader, common tasks include
+updating clocks and initializing memory controllers.  That may be needed
+to let you write the boot loader into flash, in order to "de-brick" your
+board; or to load programs into external DDR memory without having run
+the boot loader.
+
+ -- Config Command: target create target_name type configparams...
+     This command creates a GDB debug target that refers to a specific
+     JTAG tap.  It enters that target into a list, and creates a new
+     command ('TARGET_NAME') which is used for various purposes
+     including additional configuration.
+
+        * TARGET_NAME ...  is the name of the debug target.  By
+          convention this should be the same as the _dotted.name_ of the
+          TAP associated with this target, which must be specified here
+          using the '-chain-position DOTTED.NAME' configparam.
+
+          This name is also used to create the target object command,
+          referred to here as '$target_name', and in other places the
+          target needs to be identified.
+        * TYPE ...  specifies the target type.  *Note target types:
+          targettypes.
+        * CONFIGPARAMS ...  all parameters accepted by '$target_name
+          configure' are permitted.  If the target is big-endian, set it
+          here with '-endian big'.
+
+          You _must_ set the '-chain-position DOTTED.NAME' or '-dap
+          DAP_NAME' here.
+
+ -- Command: $target_name configure configparams...
+     The options accepted by this command may also be specified as
+     parameters to 'target create'.  Their values can later be queried
+     one at a time by using the '$target_name cget' command.
+
+     _Warning:_ changing some of these after setup is dangerous.  For
+     example, moving a target from one TAP to another; and changing its
+     endianness.
+
+        * '-chain-position' DOTTED.NAME - names the TAP used to access
+          this target.
+
+        * '-dap' DAP_NAME - names the DAP used to access this target.
+          *Note DAP declaration: dapdeclaration, on how to create and
+          manage DAP instances.
+
+        * '-endian' ('big'|'little') - specifies whether the CPU uses
+          big or little endian conventions
+
+        * '-event' EVENT_NAME EVENT_BODY - *Note Target Events:
+          targetevents.  Note that this updates a list of named event
+          handlers.  Calling this twice with two different event names
+          assigns two different handlers, but calling it twice with the
+          same event name assigns only one handler.
+
+          Current target is temporarily overridden to the event issuing
+          target before handler code starts and switched back after
+          handler is done.
+
+        * '-work-area-backup' ('0'|'1') - says whether the work area
+          gets backed up; by default, _it is not backed up._  When
+          possible, use a working_area that doesn't need to be backed
+          up, since performing a backup slows down operations.  For
+          example, the beginning of an SRAM block is likely to be used
+          by most build systems, but the end is often unused.
+
+        * '-work-area-size' SIZE - specify work are size, in bytes.  The
+          same size applies regardless of whether its physical or
+          virtual address is being used.
+
+        * '-work-area-phys' ADDRESS - set the work area base ADDRESS to
+          be used when no MMU is active.
+
+        * '-work-area-virt' ADDRESS - set the work area base ADDRESS to
+          be used when an MMU is active.  _Do not specify a value for
+          this except on targets with an MMU._ The value should normally
+          correspond to a static mapping for the '-work-area-phys'
+          address, set up by the current operating system.
+
+        * '-rtos' RTOS_TYPE - enable rtos support for target, RTOS_TYPE
+          can be one of 'auto', 'none', 'eCos', 'ThreadX', 'FreeRTOS',
+          'linux', 'ChibiOS', 'embKernel', 'mqx', 'uCOS-III', 'nuttx',
+          'RIOT', 'Zephyr', 'rtkernel' *Note RTOS Support:
+          gdbrtossupport.
+
+        * '-defer-examine' - skip target examination at initial JTAG
+          chain scan and after a reset.  A manual call to arp_examine is
+          required to access the target for debugging.
+
+        * '-ap-num' AP_NUMBER - set DAP access port for target.  On
+          ADIv5 DAP AP_NUMBER is the numeric index of the DAP AP the
+          target is connected to.  On ADIv6 DAP AP_NUMBER is the base
+          address of the DAP AP the target is connected to.  Use this
+          option with systems where multiple, independent cores are
+          connected to separate access ports of the same DAP.
+
+        * '-dbgbase' DBG_BASE_ADDRESS - set the base address of the
+          debug controller.  This is ignored and not required for target
+          types that have the debug controller at fixed addresses, like
+          'cortex_m'.  On DAP based SoC, OpenOCD can parse the ROM table
+          in the DAP access port to identify the base address of the
+          debug controller, but the parsing can be slow on devices with
+          big ROM tables.  While using '-dbgbase' is suggested to speed
+          up the target examination, it is often the only viable
+          solution for devices with incorrect ROM table content or with
+          ROM table partially not accessible due to clock gating or
+          power management.
+
+        * '-coreid' COREID - set an index to identify the CPU or its
+          debug controller.
+
+             - When '-dbgbase' option is not provided on devices with
+               multiple CPUs on the same DAP access port (e.g.
+               'cortex_a', 'cortex_r4', 'aarch64' and 'armv8r'), this
+               option specifies that the ROM table parsing should select
+               the CPU in position COREID.
+
+             - On target type 'riscv', COREID specifies the hart
+               (HARdware Threads) on the DM (Debug Module).  It is used
+               on multi-hart devices to index a specific hart ID. When
+               not present, it's default value is zero.
+
+             - This value COREID is currently also used in other
+               contexts as a general CPU index, e.g.  in SMP nodes or to
+               select a specific CPU in a chip.  To avoid confusion,
+               these additional use cases are going to be dropped.
+
+        * '-cti' CTI_NAME - set Cross-Trigger Interface (CTI) connected
+          to the target.  Currently, only the 'aarch64' target makes use
+          of this option, where it is a mandatory configuration for the
+          target run control.  *Note ARM Cross-Trigger Interface:
+          armcrosstrigger, for instruction on how to declare and control
+          a CTI instance.
+
+        * '-gdb-port' NUMBER - *Note command gdb port: gdb port, for the
+          possible values of the parameter NUMBER, which are not only
+          numeric values.  Use this option to override, for this target
+          only, the global parameter set with command 'gdb port'.  *Note
+          command gdb port: gdb port.
+
+        * '-gdb-max-connections' NUMBER - EXPERIMENTAL: set the maximum
+          number of GDB connections that are allowed for the target.
+          Default is 1.  A negative value for NUMBER means unlimited
+          connections.  See *Note Using GDB as a non-intrusive memory
+          inspector: gdbmeminspect.
+
+11.4 Other $target_name Commands
+================================
+
+The Tcl/Tk language has the concept of object commands, and OpenOCD
+adopts that same model for targets.
+
+A good Tk example is a on screen button.  Once a button is created a
+button has a name (a path in Tk terms) and that name is useable as a
+first class command.  For example in Tk, one can create a button and
+later configure it like this:
+
+     # Create
+     button .foobar -background red -command { foo }
+     # Modify
+     .foobar configure -foreground blue
+     # Query
+     set x [.foobar cget -background]
+     # Report
+     puts [format "The button is %s" $x]
+
+In OpenOCD's terms, the "target" is an object just like a Tcl/Tk button,
+and its object commands are invoked the same way.
+
+     str912.cpu    mww 0x1234 0x42
+     omap3530.cpu  mww 0x5555 123
+
+The commands supported by OpenOCD target objects are:
+
+ -- Command: $target_name arp_examine 'allow-defer'
+ -- Command: $target_name arp_halt
+ -- Command: $target_name arp_poll
+ -- Command: $target_name arp_reset
+ -- Command: $target_name arp_waitstate
+     Internal OpenOCD scripts (most notably 'startup.tcl') use these to
+     deal with specific reset cases.  They are not otherwise documented
+     here.
+
+ -- Command: $target_name set_reg dict
+     Set register values of the target.
+
+        * DICT ...  Tcl dictionary with pairs of register names and
+          values.
+
+     For example, the following command sets the value 0 to the program
+     counter (pc) register and 0x1000 to the stack pointer (sp)
+     register:
+
+          set_reg {pc 0 sp 0x1000}
+
+ -- Command: $target_name get_reg [-force] list
+     Get register values from the target and return them as Tcl
+     dictionary with pairs of register names and values.  If option
+     "-force" is set, the register values are read directly from the
+     target, bypassing any caching.
+
+        * LIST ...  List of register names
+
+     For example, the following command retrieves the values from the
+     program counter (pc) and stack pointer (sp) register:
+
+          get_reg {pc sp}
+
+ -- Command: $target_name write_memory address width data ['phys']
+     This function provides an efficient way to write to the target
+     memory from a Tcl script.
+
+        * ADDRESS ...  target memory address
+        * WIDTH ...  memory access bit size, can be 8, 16, 32 or 64
+        * DATA ...  Tcl list with the elements to write
+        * ['phys'] ...  treat the memory address as physical instead of
+          virtual address
+
+     For example, the following command writes two 32 bit words into the
+     target memory at address 0x20000000:
+
+          write_memory 0x20000000 32 {0xdeadbeef 0x00230500}
+
+ -- Command: $target_name read_memory address width count ['phys']
+     This function provides an efficient way to read the target memory
+     from a Tcl script.  A Tcl list containing the requested memory
+     elements is returned by this function.
+
+        * ADDRESS ...  target memory address
+        * WIDTH ...  memory access bit size, can be 8, 16, 32 or 64
+        * COUNT ...  number of elements to read
+        * ['phys'] ...  treat the memory address as physical instead of
+          virtual address
+
+     For example, the following command reads two 32 bit words from the
+     target memory at address 0x20000000:
+
+          read_memory 0x20000000 32 2
+
+ -- Command: $target_name cget queryparm
+     Each configuration parameter accepted by '$target_name configure'
+     can be individually queried, to return its current value.  The
+     QUERYPARM is a parameter name accepted by that command, such as
+     '-work-area-phys'.  There are a few special cases:
+
+        * '-event' EVENT_NAME - returns the handler for the event named
+          EVENT_NAME.  This is a special case because setting a handler
+          requires two parameters.
+        * '-type' - returns the target type.  This is a special case
+          because this is set using 'target create' and can't be changed
+          using '$target_name configure'.
+
+     For example, if you wanted to summarize information about all the
+     targets you might use something like this:
+
+          foreach name [target names] {
+              set y [$name cget -endian]
+              set z [$name cget -type]
+              puts [format "Chip %d is %s, Endian: %s, type: %s" \
+                           $x $name $y $z]
+          }
+
+ -- Command: $target_name curstate
+     Displays the current target state: 'debug-running', 'halted',
+     'reset', 'running', or 'unknown'.  (Also, *note Event Polling:
+     eventpolling.)
+
+ -- Command: $target_name debug_reason
+     Displays the current debug reason: 'debug-request', 'breakpoint',
+     'watchpoint', 'watchpoint-and-breakpoint', 'single-step',
+     'target-not-halted', 'program-exit', 'exception-catch' or
+     'undefined'.
+
+ -- Command: $target_name eventlist
+     Displays a table listing all event handlers currently associated
+     with this target.  *Note Target Events: targetevents.
+
+ -- Command: $target_name invoke-event event_name
+     Invokes the handler for the event named EVENT_NAME.  (This is
+     primarily intended for use by OpenOCD framework code, for example
+     by the reset code in 'startup.tcl'.)
+
+ -- Command: $target_name mdd [phys] addr [count]
+ -- Command: $target_name mdw [phys] addr [count]
+ -- Command: $target_name mdh [phys] addr [count]
+ -- Command: $target_name mdb [phys] addr [count]
+     Display contents of address ADDR, as 64-bit doublewords ('mdd'),
+     32-bit words ('mdw'), 16-bit halfwords ('mdh'), or 8-bit bytes
+     ('mdb').  When the current target has an MMU which is present and
+     active, ADDR is interpreted as a virtual address.  Otherwise, or if
+     the optional PHYS flag is specified, ADDR is interpreted as a
+     physical address.  If COUNT is specified, displays that many units.
+     (If you want to process the data instead of displaying it, see the
+     'read_memory' primitives.)
+
+ -- Command: $target_name mwd [phys] addr doubleword [count]
+ -- Command: $target_name mww [phys] addr word [count]
+ -- Command: $target_name mwh [phys] addr halfword [count]
+ -- Command: $target_name mwb [phys] addr byte [count]
+     Writes the specified DOUBLEWORD (64 bits), WORD (32 bits), HALFWORD
+     (16 bits), or BYTE (8-bit) value, at the specified address ADDR.
+     When the current target has an MMU which is present and active,
+     ADDR is interpreted as a virtual address.  Otherwise, or if the
+     optional PHYS flag is specified, ADDR is interpreted as a physical
+     address.  If COUNT is specified, fills that many units of
+     consecutive address.
+
+11.5 Target Events
+==================
+
+At various times, certain things can happen, or you want them to happen.
+For example:
+   * What should happen when GDB connects?  Should your target reset?
+   * When GDB tries to flash the target, do you need to enable the flash
+     via a special command?
+   * Is using SRST appropriate (and possible) on your system?  Or
+     instead of that, do you need to issue JTAG commands to trigger
+     reset?  SRST usually resets everything on the scan chain, which can
+     be inappropriate.
+   * During reset, do you need to write to certain memory locations to
+     set up system clocks or to reconfigure the SDRAM? How about
+     configuring the watchdog timer, or other peripherals, to stop
+     running while you hold the core stopped for debugging?
+
+All of the above items can be addressed by target event handlers.  These
+are set up by '$target_name configure -event' or 'target create ...
+-event'.
+
+The programmer's model matches the '-command' option used in Tcl/Tk
+buttons and events.  The two examples below act the same, but one
+creates and invokes a small procedure while the other inlines it.
+
+     proc my_init_proc { } {
+         echo "Disabling watchdog..."
+         mww 0xfffffd44 0x00008000
+     }
+     mychip.cpu configure -event reset-init my_init_proc
+     mychip.cpu configure -event reset-init {
+         echo "Disabling watchdog..."
+         mww 0xfffffd44 0x00008000
+     }
+
+The following target events are defined:
+
+   * debug-halted
+     The target has halted for debug reasons (i.e.: breakpoint)
+   * debug-resumed
+     The target has resumed (i.e.: GDB said run)
+   * early-halted
+     Occurs early in the halt process
+   * examine-start
+     Before target examine is called.
+   * examine-end
+     After target examine is called with no errors.
+   * examine-fail
+     After target examine fails.
+   * gdb-attach
+     When GDB connects.  Issued before any GDB communication with the
+     target starts.  GDB expects the target is halted during attachment.
+     *Note GDB as a non-intrusive memory inspector: gdbmeminspect, how
+     to connect GDB to running target.  The event can be also used to
+     set up the target so it is possible to probe flash.  Probing flash
+     is necessary during GDB connect if you want to use *note
+     programming using GDB: programmingusinggdb.  Another use of the
+     flash memory map is for GDB to automatically choose hardware or
+     software breakpoints depending on whether the breakpoint is in RAM
+     or read only memory.  Default is 'halt'
+   * gdb-detach
+     When GDB disconnects
+   * gdb-end
+     When the target has halted and GDB is not doing anything (see early
+     halt)
+   * gdb-flash-erase-start
+     Before the GDB flash process tries to erase the flash (default is
+     'reset init')
+   * gdb-flash-erase-end
+     After the GDB flash process has finished erasing the flash
+   * gdb-flash-write-start
+     Before GDB writes to the flash
+   * gdb-flash-write-end
+     After GDB writes to the flash (default is 'reset halt')
+   * gdb-start
+     Before the target steps, GDB is trying to start/resume the target
+   * halted
+     The target has halted
+   * reset-assert-pre
+     Issued as part of 'reset' processing after 'reset-start' was
+     triggered but before either SRST alone is asserted on the scan
+     chain, or 'reset-assert' is triggered.
+   * reset-assert
+     Issued as part of 'reset' processing after 'reset-assert-pre' was
+     triggered.  When such a handler is present, cores which support
+     this event will use it instead of asserting SRST. This support is
+     essential for debugging with JTAG interfaces which don't include an
+     SRST line (JTAG doesn't require SRST), and for selective reset on
+     scan chains that have multiple targets.
+   * reset-assert-post
+     Issued as part of 'reset' processing after 'reset-assert' has been
+     triggered.  or the target asserted SRST on the entire scan chain.
+   * reset-deassert-pre
+     Issued as part of 'reset' processing after 'reset-assert-post' has
+     been triggered.
+   * reset-deassert-post
+     Issued as part of 'reset' processing after 'reset-deassert-pre' has
+     been triggered and (if the target is using it) after SRST has been
+     released on the scan chain.
+   * reset-end
+     Issued as the final step in 'reset' processing.
+   * reset-init
+     Used by reset init command for board-specific initialization.  This
+     event fires after _reset-deassert-post_.
+
+     This is where you would configure PLLs and clocking, set up DRAM so
+     you can download programs that don't fit in on-chip SRAM, set up
+     pin multiplexing, and so on.  (You may be able to switch to a fast
+     JTAG clock rate here, after the target clocks are fully set up.)
+   * reset-start
+     Issued as the first step in 'reset' processing before
+     'reset-assert-pre' is called.
+
+     This is the most robust place to use 'jtag_rclk' or 'adapter speed'
+     to switch to a low JTAG clock rate, when reset disables PLLs needed
+     to use a fast clock.
+   * resume-start
+     Before any target is resumed
+   * resume-end
+     After all targets have resumed
+   * resumed
+     Target has resumed
+   * step-start
+     Before a target is single-stepped
+   * step-end
+     After single-step has completed
+   * trace-config
+     After target hardware trace configuration was changed
+   * semihosting-user-cmd-0x100
+     The target made a semihosting call with user-defined operation
+     number 0x100
+   * semihosting-user-cmd-0x101
+     The target made a semihosting call with user-defined operation
+     number 0x101
+   * semihosting-user-cmd-0x102
+     The target made a semihosting call with user-defined operation
+     number 0x102
+   * semihosting-user-cmd-0x103
+     The target made a semihosting call with user-defined operation
+     number 0x103
+   * semihosting-user-cmd-0x104
+     The target made a semihosting call with user-defined operation
+     number 0x104
+   * semihosting-user-cmd-0x105
+     The target made a semihosting call with user-defined operation
+     number 0x105
+   * semihosting-user-cmd-0x106
+     The target made a semihosting call with user-defined operation
+     number 0x106
+   * semihosting-user-cmd-0x107
+     The target made a semihosting call with user-defined operation
+     number 0x107
+
+     Note: OpenOCD events are not supposed to be preempt by another
+     event, but this is not enforced in current code.  Only the target
+     event resumed is executed with polling disabled; this avoids
+     polling to trigger the event halted, reversing the logical order of
+     execution of their handlers.  Future versions of OpenOCD will
+     prevent the event preemption and will disable the schedule of
+     polling during the event execution.  Do not rely on polling in any
+     event handler; this means, don't expect the status of a core to
+     change during the execution of the handler.  The event handler will
+     have to enable polling or use '$target_name arp_poll' to check if
+     the core has changed status.
+
+
+File: openocd.info,  Node: Flash Commands,  Next: Flash Programming,  Prev: CPU Configuration,  Up: Top
+
+12 Flash Commands
+*****************
+
+OpenOCD has different commands for NOR and NAND flash; the "flash"
+command works with NOR flash, while the "nand" command works with NAND
+flash.  This partially reflects different hardware technologies: NOR
+flash usually supports direct CPU instruction and data bus access, while
+data from a NAND flash must be copied to memory before it can be used.
+(SPI flash must also be copied to memory before use.)  However, the
+documentation also uses "flash" as a generic term; for example, "Put
+flash configuration in board-specific files".
+
+Flash Steps:
+  1. Configure via the command 'flash bank'
+     Do this in a board-specific configuration file, passing parameters
+     as needed by the driver.
+  2. Operate on the flash via 'flash subcommand'
+     Often commands to manipulate the flash are typed by a human, or run
+     via a script in some automated way.  Common tasks include writing a
+     boot loader, operating system, or other data.
+  3. GDB Flashing
+     Flashing via GDB requires the flash be configured via "flash bank",
+     and the GDB flash features be enabled.  *Note GDB Configuration:
+     gdbconfiguration.
+
+Many CPUs have the ability to "boot" from the first flash bank.  This
+means that misprogramming that bank can "brick" a system, so that it
+can't boot.  JTAG tools, like OpenOCD, are often then used to "de-brick"
+the board by (re)installing working boot firmware.
+
+12.1 Flash Configuration Commands
+=================================
+
+ -- Config Command: flash bank name driver base size chip_width
+          bus_width target [driver_options]
+     Configures a flash bank which provides persistent storage for
+     addresses from base to base + size - 1.  These banks will often be
+     visible to GDB through the target's memory map.  In some cases,
+     configuring a flash bank will activate extra commands; see the
+     driver-specific documentation.
+
+        * NAME ...  may be used to reference the flash bank in other
+          flash commands.  A number is also available.
+        * DRIVER ...  identifies the controller driver associated with
+          the flash bank being declared.  This is usually 'cfi' for
+          external flash, or else the name of a microcontroller with
+          embedded flash memory.  *Note Flash Driver List:
+          flashdriverlist.
+        * BASE ...  Base address of the flash chip.
+        * SIZE ...  Size of the chip, in bytes.  For some drivers, this
+          value is detected from the hardware.
+        * CHIP_WIDTH ...  Width of the flash chip, in bytes; ignored for
+          most microcontroller drivers.
+        * BUS_WIDTH ...  Width of the data bus used to access the chip,
+          in bytes; ignored for most microcontroller drivers.
+        * TARGET ...  Names the target used to issue commands to the
+          flash controller.
+        * DRIVER_OPTIONS ...  drivers may support, or require,
+          additional parameters.  See the driver-specific documentation
+          for more information.
+          Note: This command is not available after OpenOCD
+          initialization has completed.  Use it in board specific
+          configuration files, not interactively.
+
+ -- Command: flash banks
+     Prints a one-line summary of each device that was declared using
+     'flash bank', numbered from zero.  Note that this is the _plural_
+     form; the _singular_ form is a very different command.
+
+ -- Command: flash list
+     Retrieves a list of associative arrays for each device that was
+     declared using 'flash bank', numbered from zero.  This returned
+     list can be manipulated easily from within scripts.
+
+ -- Command: flash probe num
+     Identify the flash, or validate the parameters of the configured
+     flash.  Operation depends on the flash type.  The NUM parameter is
+     a value shown by 'flash banks'.  Most flash commands will
+     implicitly _autoprobe_ the bank; flash drivers can distinguish
+     between probing and autoprobing, but most don't bother.
+
+12.2 Preparing a Target before Flash Programming
+================================================
+
+The target device should be in well defined state before the flash
+programming begins.
+
+_Always issue_ 'reset init' before *note Flash Programming Commands:
+flashprogrammingcommands.  Do not issue another 'reset' or 'reset halt'
+or 'resume' until the programming session is finished.
+
+If you use *note Programming using GDB: programmingusinggdb, the target
+is prepared automatically in the event gdb-flash-erase-start
+
+The jimtcl script 'program' calls 'reset init' explicitly.
+
+12.3 Erasing, Reading, Writing to Flash
+=======================================
+
+One feature distinguishing NOR flash from NAND or serial flash
+technologies is that for read access, it acts exactly like any other
+addressable memory.  This means you can use normal memory read commands
+like 'mdw' or 'dump_image' with it, with no special 'flash' subcommands.
+*Note Memory access: memoryaccess, and *note Image access: imageaccess.
+
+Write access works differently.  Flash memory normally needs to be
+erased before it's written.  Erasing a sector turns all of its bits to
+ones, and writing can turn ones into zeroes.  This is why there are
+special commands for interactive erasing and writing, and why GDB needs
+to know which parts of the address space hold NOR flash memory.
+
+     Note: Most of these erase and write commands leverage the fact that
+     NOR flash chips consume target address space.  They implicitly
+     refer to the current JTAG target, and map from an address in that
+     target's address space back to a flash bank.  A few commands use
+     abstract addressing based on bank and sector numbers, and don't
+     depend on searching the current target and its address space.
+     Avoid confusing the two command models.
+
+Some flash chips implement software protection against accidental
+writes, since such buggy writes could in some cases "brick" a system.
+For such systems, erasing and writing may require sector protection to
+be disabled first.  Examples include CFI flash such as "Intel Advanced
+Bootblock flash", and AT91SAM7 on-chip flash.  *Note flash protect:
+flashprotect.
+
+ -- Command: flash erase_sector num first last
+     Erase sectors in bank NUM, starting at sector FIRST up to and
+     including LAST.  Sector numbering starts at 0.  Providing a LAST
+     sector of 'last' specifies "to the end of the flash bank".  The NUM
+     parameter is a value shown by 'flash banks'.
+
+ -- Command: flash erase_address ['pad'] ['unlock'] address length
+     Erase sectors starting at ADDRESS for LENGTH bytes.  Unless 'pad'
+     is specified, address must begin a flash sector, and address +
+     length - 1 must end a sector.  Specifying 'pad' erases extra data
+     at the beginning and/or end of the specified region, as needed to
+     erase only full sectors.  The flash bank to use is inferred from
+     the ADDRESS, and the specified length must stay within that bank.
+     As a special case, when LENGTH is zero and ADDRESS is the start of
+     the bank, the whole flash is erased.  If 'unlock' is specified,
+     then the flash is unprotected before erase starts.
+
+ -- Command: flash filld address double-word length
+ -- Command: flash fillw address word length
+ -- Command: flash fillh address halfword length
+ -- Command: flash fillb address byte length
+     Fills flash memory with the specified DOUBLE-WORD (64 bits), WORD
+     (32 bits), HALFWORD (16 bits), or BYTE (8-bit) pattern, starting at
+     ADDRESS and continuing for LENGTH units (word/halfword/byte).  No
+     erasure is done before writing; when needed, that must be done
+     before issuing this command.  Writes are done in blocks of up to
+     1024 bytes, and each write is verified by reading back the data and
+     comparing it to what was written.  The flash bank to use is
+     inferred from the ADDRESS of each block, and the specified length
+     must stay within that bank.
+
+ -- Command: flash mdw addr [count]
+ -- Command: flash mdh addr [count]
+ -- Command: flash mdb addr [count]
+     Display contents of address ADDR, as 32-bit words ('mdw'), 16-bit
+     halfwords ('mdh'), or 8-bit bytes ('mdb').  If COUNT is specified,
+     displays that many units.  Reads from flash using the flash driver,
+     therefore it enables reading from a bank not mapped in target
+     address space.  The flash bank to use is inferred from the ADDRESS
+     of each block, and the specified length must stay within that bank.
+
+ -- Command: flash write_bank num filename [offset]
+     Write the binary 'filename' to flash bank NUM, starting at OFFSET
+     bytes from the beginning of the bank.  If OFFSET is omitted, start
+     at the beginning of the flash bank.  The NUM parameter is a value
+     shown by 'flash banks'.
+
+ -- Command: flash read_bank num filename [offset [length]]
+     Read LENGTH bytes from the flash bank NUM starting at OFFSET and
+     write the contents to the binary 'filename'.  If OFFSET is omitted,
+     start at the beginning of the flash bank.  If LENGTH is omitted,
+     read the remaining bytes from the flash bank.  The NUM parameter is
+     a value shown by 'flash banks'.
+
+ -- Command: flash verify_bank num filename [offset]
+     Compare the contents of the binary file FILENAME with the contents
+     of the flash bank NUM starting at OFFSET.  If OFFSET is omitted,
+     start at the beginning of the flash bank.  Fail if the contents do
+     not match.  The NUM parameter is a value shown by 'flash banks'.
+
+ -- Command: flash write_image [erase] [unlock] filename [offset] [type]
+     Write the image 'filename' to the current target's flash bank(s).
+     Only loadable sections from the image are written.  A relocation
+     OFFSET may be specified, in which case it is added to the base
+     address for each section in the image.  The file [TYPE] can be
+     specified explicitly as 'bin' (binary), 'ihex' (Intel hex), 'elf'
+     (ELF file), 's19' (Motorola s19).  'mem', or 'builder'.  The
+     relevant flash sectors will be erased prior to programming if the
+     'erase' parameter is given.  If 'unlock' is provided, then the
+     flash banks are unlocked before erase and program.  The flash bank
+     to use is inferred from the address of each image section.
+
+          Warning: Be careful using the 'erase' flag when the flash is
+          holding data you want to preserve.  Portions of the flash
+          outside those described in the image's sections might be
+          erased with no notice.
+             * When a section of the image being written does not fill
+               out all the sectors it uses, the unwritten parts of those
+               sectors are necessarily also erased, because sectors
+               can't be partially erased.
+             * Data stored in sector "holes" between image sections are
+               also affected.  For example, "'flash write_image erase
+               ...'" of an image with one byte at the beginning of a
+               flash bank and one byte at the end erases the entire bank
+               - not just the two sectors being written.
+          Also, when flash protection is important, you must re-apply it
+          after it has been removed by the 'unlock' flag.
+
+ -- Command: flash verify_image filename [offset] [type]
+     Verify the image 'filename' to the current target's flash bank(s).
+     Parameters follow the description of 'flash write_image'.  In
+     contrast to the 'verify_image' command, for banks with specific
+     verify method, that one is used instead of the usual target's read
+     memory methods.  This is necessary for flash banks not readable by
+     ordinary memory reads.  This command gives only an overall good/bad
+     result for each bank, not addresses of individual failed bytes as
+     it's intended only as quick check for successful programming.
+
+12.4 Other Flash commands
+=========================
+
+ -- Command: flash erase_check num
+     Check erase state of sectors in flash bank NUM, and display that
+     status.  The NUM parameter is a value shown by 'flash banks'.
+
+ -- Command: flash info num [sectors]
+     Print info about flash bank NUM, a list of protection blocks and
+     their status.  Use 'sectors' to show a list of sectors instead.
+
+     The NUM parameter is a value shown by 'flash banks'.  This command
+     will first query the hardware, it does not print cached and
+     possibly stale information.
+
+ -- Command: flash protect num first last ('on'|'off')
+     Enable ('on') or disable ('off') protection of flash blocks in
+     flash bank NUM, starting at protection block FIRST and continuing
+     up to and including LAST.  Providing a LAST block of 'last'
+     specifies "to the end of the flash bank".  The NUM parameter is a
+     value shown by 'flash banks'.  The protection block is usually
+     identical to a flash sector.  Some devices may utilize a protection
+     block distinct from flash sector.  See 'flash info' for a list of
+     protection blocks.
+
+ -- Command: flash padded_value num value
+     Sets the default value used for padding any image sections, This
+     should normally match the flash bank erased value.  If not
+     specified by this command or the flash driver then it defaults to
+     0xff.
+
+ -- Command: program filename [preverify] [verify] [reset] [exit]
+          [offset]
+     This is a helper script that simplifies using OpenOCD as a
+     standalone programmer.  The only required parameter is 'filename',
+     the others are optional.  *Note Flash Programming::.
+
+12.5 Flash Driver List
+======================
+
+As noted above, the 'flash bank' command requires a driver name, and
+allows driver-specific options and behaviors.  Some drivers also
+activate driver-specific commands.
+
+ -- Flash Driver: virtual
+     This is a special driver that maps a previously defined bank to
+     another address.  All bank settings will be copied from the master
+     physical bank.
+
+     The VIRTUAL driver defines one mandatory parameters,
+
+        * MASTER_BANK The bank that this virtual address refers to.
+
+     So in the following example addresses 0xbfc00000 and 0x9fc00000
+     refer to the flash bank defined at address 0x1fc00000.  Any command
+     executed on the virtual banks is actually performed on the physical
+     banks.
+          flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
+          flash bank vbank0 virtual 0xbfc00000 0 0 0 \
+                     $_TARGETNAME $_FLASHNAME
+          flash bank vbank1 virtual 0x9fc00000 0 0 0 \
+                     $_TARGETNAME $_FLASHNAME
+
+12.5.1 External Flash
+---------------------
+
+ -- Flash Driver: cfi
+     The "Common Flash Interface" (CFI) is the main standard for
+     external NOR flash chips, each of which connects to a specific
+     external chip select on the CPU. Frequently the first such chip is
+     used to boot the system.  Your board's 'reset-init' handler might
+     need to configure additional chip selects using other commands
+     (like: 'mww' to configure a bus and its timings), or perhaps
+     configure a GPIO pin that controls the "write protect" pin on the
+     flash chip.  The CFI driver can use a target-specific working area
+     to significantly speed up operation.
+
+     The CFI driver can accept the following optional parameters, in any
+     order:
+
+        * JEDEC_PROBE ...  is used to detect certain non-CFI flash ROMs,
+          like AM29LV010 and similar types.
+        * X16_AS_X8 ...  when a 16-bit flash is hooked up to an 8-bit
+          bus.
+        * BUS_SWAP ...  when data bytes in a 16-bit flash needs to be
+          swapped.
+        * DATA_SWAP ...  when data bytes in a 16-bit flash needs to be
+          swapped when writing data values (i.e.  not CFI commands).
+
+     To configure two adjacent banks of 16 MBytes each, both sixteen
+     bits (two bytes) wide on a sixteen bit bus:
+
+          flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
+          flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
+
+     To configure one bank of 32 MBytes built from two sixteen bit (two
+     byte) wide parts wired in parallel to create a thirty-two bit (four
+     byte) bus with doubled throughput:
+
+          flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
+
+ -- Flash Driver: jtagspi
+     Several FPGAs and CPLDs can retrieve their configuration
+     (bitstream) from a SPI flash connected to them.  To access this
+     flash from the host, some FPGA device provides dedicated JTAG
+     instructions, while other FPGA devices should be programmed with a
+     special proxy bitstream that exposes the SPI flash on the device's
+     JTAG interface.  The flash can then be accessed through JTAG.
+
+     Since signalling between JTAG and SPI is compatible, all that is
+     required for a proxy bitstream is to connect TDI-MOSI, TDO-MISO,
+     TCK-CLK and activate the flash chip select when the JTAG state
+     machine is in SHIFT-DR.
+
+     Such a bitstream for several Xilinx FPGAs can be found in
+     'contrib/loaders/flash/fpga/xilinx_bscan_spi.py'.  It requires
+     migen (https://github.com/m-labs/migen) and a Xilinx toolchain to
+     build.
+
+     This mechanism with a proxy bitstream can also be used for FPGAs
+     from Intel and Efinix.  FPGAs from Lattice and Cologne Chip have
+     dedicated JTAG instructions and procedure to connect the JTAG to
+     the SPI signals and don't need a proxy bitstream.  Support for
+     these devices with dedicated procedure is provided by the pld
+     drivers.  For convenience the PLD drivers will provide the USERx
+     code for FPGAs with a proxy bitstream.  Currently the following PLD
+     drivers are able to support jtagspi:
+        * Efinix: proxy-bitstream
+        * Gatemate: dedicated procedure
+        * Intel/Altera: proxy-bitstream
+        * Lattice: dedicated procedure supporting ECP2, ECP3, ECP5,
+          Certus and Certus Pro devices
+        * AMD/Xilinx: proxy-bitstream
+
+     This flash bank driver requires a target on a JTAG tap and will
+     access that tap directly.  Since no support from the target is
+     needed, the target can be a "testee" dummy.  Since the target does
+     not expose the flash memory mapping, target commands that would
+     otherwise be expected to access the flash will not work.  These
+     include all '*_image' and '$target_name m*' commands as well as
+     'program'.  Equivalent functionality is available through the
+     'flash write_bank', 'flash read_bank', and 'flash verify_bank'
+     commands.
+
+     According to device size, 1- to 4-byte addresses are sent.
+     However, some flash chips additionally have to be switched to
+     4-byte addresses by an extra command, see below.
+
+        * IR ...  is loaded into the JTAG IR to map the flash as the
+          JTAG DR. For the bitstreams generated from
+          'xilinx_bscan_spi.py' this is the USER1 instruction.
+               target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
+               set _USER1_INSTR_CODE 0x02
+               flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \
+                          $_TARGETNAME $_USER1_INSTR_CODE
+
+        * The option '-pld' NAME is used to have support from the PLD
+          driver of pld device NAME.  The name is the name of the pld
+          device given during creation of the pld device.  Pld device
+          names are shown by the 'pld devices' command.
+
+               target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
+               set _JTAGSPI_CHAIN_ID $_CHIPNAME.pld
+               flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \
+                          $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID
+
+      -- Command: jtagspi set bank_id name total_size page_size read_cmd
+               unused pprg_cmd mass_erase_cmd sector_size
+               sector_erase_cmd
+          Sets flash parameters: NAME human readable string, TOTAL_SIZE
+          size in bytes, PAGE_SIZE is write page size.  READ_CMD and
+          PPRG_CMD are commands for read and page program, respectively.
+          MASS_ERASE_CMD, SECTOR_SIZE and SECTOR_ERASE_CMD are optional.
+               jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
+
+      -- Command: jtagspi cmd bank_id resp_num cmd_byte ...
+          Sends command CMD_BYTE and at most 20 following bytes and
+          reads RESP_NUM bytes afterwards.  E.g.  for 'Enter 4-byte
+          address mode'
+               jtagspi cmd 0 0 0xB7
+
+      -- Command: jtagspi always_4byte bank_id [ on | off ]
+          Some devices use 4-byte addresses for all commands except the
+          legacy 0x03 read regardless of device size.  This command
+          controls the corresponding hack.
+
+ -- Flash Driver: xcf
+     Xilinx FPGAs can be configured from specialized flash ICs named
+     Platform Flash.  It is (almost) regular NOR flash with erase
+     sectors, program pages, etc.  The only difference is special
+     registers controlling its FPGA specific behavior.  They must be
+     properly configured for successful FPGA loading using additional
+     XCF driver command:
+
+      -- Command: xcf ccb 
+          command accepts additional parameters:
+             * EXTERNAL|INTERNAL ...  selects clock source.
+             * SERIAL|PARALLEL ...  selects serial or parallel data bus
+               mode.
+             * SLAVE|MASTER ...  selects slave of master mode for flash
+               device.
+             * 40|20 ...  selects clock frequency in MHz for internal
+               clock in master mode.
+               xcf ccb 0 external parallel slave 40
+          All of them must be specified even if clock frequency is
+          pointless in slave mode.  If only bank id specified than
+          command prints current CCB register value.  Note: there is no
+          need to write this register every time you erase/program data
+          sectors because it stores in dedicated sector.
+
+      -- Command: xcf configure 
+          Initiates FPGA loading procedure.  Useful if your board has no
+          "configure" button.
+               xcf configure 0
+
+     Additional driver notes:
+        * Only single revision supported.
+        * Driver automatically detects need of bit reverse, but only
+          "bin" (raw binary, do not confuse it with "bit") and "mcs"
+          (Intel hex) file types supported.
+        * For additional info check xapp972.pdf and ug380.pdf.
+
+ -- Flash Driver: lpcspifi
+     NXP's LPC43xx and LPC18xx families include a proprietary SPI Flash
+     Interface (SPIFI) peripheral that can drive and provide memory
+     mapped access to external SPI flash devices.
+
+     The lpcspifi driver initializes this interface and provides program
+     and erase functionality for these serial flash devices.  Use of
+     this driver requires a working area of at least 1kB to be
+     configured on the target device; more than this will significantly
+     reduce flash programming times.
+
+     The setup command only requires the BASE parameter.  All other
+     parameters are ignored, and the flash size and layout are
+     configured by the driver.
+
+          flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
+
+ -- Flash Driver: stmsmi
+     Some devices from STMicroelectronics (e.g.  STR75x MCU family,
+     SPEAr MPU family) include a proprietary "Serial Memory Interface"
+     (SMI) controller able to drive external SPI flash devices.
+     Depending on specific device and board configuration, up to 4
+     external flash devices can be connected.
+
+     SMI makes the flash content directly accessible in the CPU address
+     space; each external device is mapped in a memory bank.  CPU can
+     directly read data, execute code and boot from SMI banks.  Normal
+     OpenOCD commands like 'mdw' can be used to display the flash
+     content.
+
+     The setup command only requires the BASE parameter in order to
+     identify the memory bank.  All other parameters are ignored.
+     Additional information, like flash size, are detected
+     automatically.
+
+          flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
+
+ -- Flash Driver: stmqspi
+     Some devices from STMicroelectronics include a proprietary "QuadSPI
+     Interface" (e.g.  STM32F4, STM32F7, STM32L4) or "OctoSPI Interface"
+     (e.g.  STM32L4+) controller able to drive one or even two (dual
+     mode) external SPI flash devices.  The OctoSPI is a superset of
+     QuadSPI, its presence is detected automatically.  Currently only
+     the regular command mode is supported, whereas the HyperFlash mode
+     is not.
+
+     QuadSPI/OctoSPI makes the flash contents directly accessible in the
+     CPU address space; in case of dual mode both devices must be of the
+     same type and are mapped in the same memory bank (even and odd
+     addresses interleaved).  CPU can directly read data, execute code
+     (but not boot) from QuadSPI bank.
+
+     The 'flash bank' command only requires the BASE parameter and the
+     extra parameter IO_BASE in order to identify the memory bank.  Both
+     are fixed by hardware, see datasheet or RM. All other parameters
+     are ignored.
+
+     The controller must be initialized after each reset and properly
+     configured for memory-mapped read operation for the particular
+     flash chip(s), for the full list of available register settings cf.
+     the controller's RM. This setup is quite board specific (that's why
+     booting from this memory is not possible).  The flash driver infers
+     all parameters from current controller register values when 'flash
+     probe BANK_ID' is executed.
+
+     Normal OpenOCD commands like 'mdw' can be used to display the flash
+     content, but only after proper controller initialization as
+     described above.  However, due to a silicon bug in some devices,
+     attempting to access the very last word should be avoided.
+
+     It is possible to use two (even different) flash chips
+     alternatingly, if individual bank chip selects are available.  For
+     some package variants, this is not the case due to limited pin
+     count.  To switch from one to another, adjust FSEL bit accordingly
+     and re-issue 'flash probe bank_id'.  Note that the bank base
+     address will _not_ change, so the address spaces of both devices
+     will overlap.  In dual flash mode both chips must be identical
+     regarding size and most other properties.
+
+     Block or sector protection internal to the flash chip is not
+     handled by this driver at all, but can be dealt with manually by
+     the 'cmd' command, see below.  The sector protection via 'flash
+     protect' command etc.  is completely internal to openocd, intended
+     only to prevent accidental erase or overwrite and it does not
+     persist across openocd invocations.
+
+     OpenOCD contains a hardcoded list of flash devices with their
+     properties, these are auto-detected.  If a device is not included
+     in this list, SFDP discovery is attempted.  If this fails or gives
+     inappropriate results, manual setting is required (see 'set'
+     command).
+
+          flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
+                     $_TARGETNAME 0xA0001000
+          flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
+                     $_TARGETNAME 0xA0001400
+
+     There are three specific commands
+      -- Command: stmqspi mass_erase bank_id
+          Clears sector protections and performs a mass erase.  Works
+          only if there is no chip specific write protection engaged.
+
+      -- Command: stmqspi set bank_id name total_size page_size read_cmd
+               fread_cmd pprg_cmd mass_erase_cmd sector_size
+               sector_erase_cmd
+          Set flash parameters: NAME human readable string, TOTAL_SIZE
+          size in bytes, PAGE_SIZE is write page size.  READ_CMD,
+          FREAD_CMD and PPRG_CMD are commands for reading and page
+          programming.  FREAD_CMD is used in DPI and QPI modes, READ_CMD
+          in normal SPI (single line) mode.  MASS_ERASE_CMD, SECTOR_SIZE
+          and SECTOR_ERASE_CMD are optional.
+
+          This command is required if chip id is not hardcoded yet and
+          e.g.  for EEPROMs or FRAMs which don't support an id command.
+
+          In dual mode parameters of both chips are set identically.
+          The parameters refer to a single chip, so the whole bank gets
+          twice the specified capacity etc.
+
+      -- Command: stmqspi cmd bank_id resp_num cmd_byte ...
+          If RESP_NUM is zero, sends command CMD_BYTE and following data
+          bytes.  In dual mode command byte is sent to _both_ chips but
+          data bytes are sent _alternatingly_ to chip 1 and 2, first to
+          flash 1, second to flash 2, etc., i.e.  the total number of
+          bytes (including cmd_byte) must be odd.
+
+          If RESP_NUM is not zero, cmd and at most four following data
+          bytes are sent, in dual mode _simultaneously_ to both chips.
+          Then RESP_NUM bytes are read interleaved from both chips
+          starting with chip 1.  In this case RESP_NUM must be even.
+
+          Note the hardware dictated subtle difference of those two
+          cases in dual-flash mode.
+
+          To check basic communication settings, issue
+               stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
+               stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
+          for single flash mode or
+               stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
+               stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
+          for dual flash mode.  This should return the status register
+          contents.
+
+          In 8-line mode, CMD_BYTE is sent twice - first time as given,
+          second time complemented.  Additionally, in 8-line mode only,
+          some commands (e.g.  Read Status) need a dummy address, e.g.
+               stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
+          should return the status register contents.
+
+ -- Flash Driver: mrvlqspi
+     This driver supports QSPI flash controller of Marvell's Wireless
+     Microcontroller platform.
+
+     The flash size is autodetected based on the table of known JEDEC
+     IDs hardcoded in the OpenOCD sources.
+
+          flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
+
+ -- Flash Driver: ath79
+     Members of ATH79 SoC family from Atheros include a SPI interface
+     with 3 chip selects.  On reset a SPI flash connected to the first
+     chip select (CS0) is made directly read-accessible in the CPU
+     address space (up to 16MBytes) and is usually used to store the
+     bootloader and operating system.  Normal OpenOCD commands like
+     'mdw' can be used to display the flash content while it is in
+     memory-mapped mode (only the first 4MBytes are accessible without
+     additional configuration on reset).
+
+     The setup command only requires the BASE parameter in order to
+     identify the memory bank.  The actual value for the base address is
+     not otherwise used by the driver.  However the mapping is passed to
+     gdb.  Thus for the memory mapped flash (chipselect CS0) the base
+     address should be the actual memory mapped base address.  For
+     unmapped chipselects (CS1 and CS2) care should be taken to use a
+     base address that does not overlap with real memory regions.
+     Additional information, like flash size, are detected
+     automatically.  An optional additional parameter sets the
+     chipselect for the bank, with the default CS0.  CS1 and CS2 require
+     additional GPIO setup before they can be used since the alternate
+     function must be enabled on the GPIO pin CS1/CS2 is routed to on
+     the given SoC.
+
+          flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
+
+          # When using multiple chipselects the base should be different
+          # for each, otherwise the write_image command is not able to
+          # distinguish the banks.
+          flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
+          flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
+          flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
+
+ -- Flash Driver: fespi
+
+     SiFive's Freedom E SPI controller, used in HiFive and other boards.
+
+          flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
+
+ -- Flash Driver: nuspi
+
+     Nuclei's SPI controller, used in Nuclei RISC-V fpga evaluation
+     board and other boards.
+
+          flash bank $_FLASHNAME nuspi 0x20000000 0 0 0 $_TARGETNAME
+
+12.5.2 Internal Flash (Microcontrollers)
+----------------------------------------
+
+ -- Flash Driver: aduc702x
+     The ADUC702x analog microcontrollers from Analog Devices include
+     internal flash and use ARM7TDMI cores.  The aduc702x flash driver
+     works with models ADUC7019 through ADUC7028.  The setup command
+     only requires the TARGET argument since all devices in this family
+     have the same memory layout.
+
+          flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
+
+ -- Flash Driver: ambiqmicro
+     All members of the Apollo microcontroller family from Ambiq Micro
+     include internal flash and use ARM's Cortex-M4 core.  The host
+     connects over USB to an FTDI interface that communicates with the
+     target using SWD.
+
+     The AMBIQMICRO driver reads the Chip Information Register detect
+     the device class of the MCU. The Flash and SRAM sizes directly
+     follow device class, and are used to set up the flash banks.  If
+     this fails, the driver will use default values set to the minimum
+     sizes of an Apollo chip.
+
+     All Apollo chips have two flash banks of the same size.  In all
+     cases the first flash bank starts at location 0, and the second
+     bank starts after the first.
+
+          # Flash bank 0
+          flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
+          # Flash bank 1 - same size as bank0, starts after bank 0.
+          flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
+                     $_TARGETNAME
+
+     Flash is programmed using custom entry points into the bootloader.
+     This is the only way to program the flash as no flash control
+     registers are available to the user.
+
+     The AMBIQMICRO driver adds some additional commands:
+
+      -- Command: ambiqmicro mass_erase 
+          Erase entire bank.
+      -- Command: ambiqmicro page_erase   
+          Erase device pages.
+      -- Command: ambiqmicro program_otp   
+          Program OTP is a one time operation to create write protected
+          flash.  The user writes sectors to SRAM starting at
+          0x10000010.  Program OTP will write these sectors from SRAM to
+          flash, and write protect the flash.
+
+ -- Flash Driver: at91samd
+     All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC
+     microcontroller families from Atmel include internal flash and use
+     ARM's Cortex-M0+ core.
+
+     Do not use for ATSAM D51 and E5x: use *Note atsame5::.
+
+     The devices have one flash bank:
+
+          flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
+
+      -- Command: at91samd chip-erase
+          Issues a complete Flash erase via the Device Service Unit
+          (DSU). This can be used to erase a chip back to its factory
+          state and does not require the processor to be halted.
+
+      -- Command: at91samd set-security
+          Secures the Flash via the Set Security Bit (SSB) command.
+          This prevents access to the Flash and can only be undone by
+          using the chip-erase command which erases the Flash contents
+          and turns off the security bit.  Warning: at this time,
+          openocd will not be able to communicate with a secured chip
+          and it is therefore not possible to chip-erase it without
+          using another tool.
+
+               at91samd set-security enable
+
+      -- Command: at91samd eeprom
+          Shows or sets the EEPROM emulation size configuration, stored
+          in the User Row of the Flash.  When setting, the EEPROM size
+          must be specified in bytes and it must be one of the permitted
+          sizes according to the datasheet.  Settings are written
+          immediately but only take effect on MCU reset.  EEPROM
+          emulation requires additional firmware support and the minimum
+          EEPROM size may not be the same as the minimum that the
+          hardware supports.  Set the EEPROM size to 0 in order to
+          disable this feature.
+
+               at91samd eeprom
+               at91samd eeprom 1024
+
+      -- Command: at91samd bootloader
+          Shows or sets the bootloader size configuration, stored in the
+          User Row of the Flash.  This is called the BOOTPROT region.
+          When setting, the bootloader size must be specified in bytes
+          and it must be one of the permitted sizes according to the
+          datasheet.  Settings are written immediately but only take
+          effect on MCU reset.  Setting the bootloader size to 0
+          disables bootloader protection.
+
+               at91samd bootloader
+               at91samd bootloader 16384
+
+      -- Command: at91samd dsu_reset_deassert
+          This command releases internal reset held by DSU and prepares
+          reset vector catch in case of reset halt.  Command is used
+          internally in event reset-deassert-post.
+
+      -- Command: at91samd nvmuserrow
+          Writes or reads the entire 64 bit wide NVM user row register
+          which is located at 0x804000.  This register includes various
+          fuses lock-bits and factory calibration data.  Reading the
+          register is done by invoking this command without any
+          arguments.  Writing is possible by giving 1 or 2 hex values.
+          The first argument is the register value to be written and the
+          second one is an optional changemask.  Every bit which value
+          in changemask is 0 will stay unchanged.  The lock- and
+          reserved-bits are masked out and cannot be changed.
+
+               # Read user row
+               >at91samd nvmuserrow
+               NVMUSERROW: 0xFFFFFC5DD8E0C788
+               # Write 0xFFFFFC5DD8E0C788 to user row
+               >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
+               # Write 0x12300 to user row but leave other bits and low
+               # byte unchanged
+               >at91samd nvmuserrow 0x12345 0xFFF00
+
+ -- Flash Driver: at91sam3
+     All members of the AT91SAM3 microcontroller family from Atmel
+     include internal flash and use ARM's Cortex-M3 core.  The driver
+     currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips.
+     Note that the driver was orginaly developed and tested using the
+     AT91SAM3U4E, using a SAM3U-EK eval board.  Support for other chips
+     in the family was cribbed from the data sheet.  _Note to future
+     readers/updaters: Please remove this worrisome comment after other
+     chips are confirmed._
+
+     The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other
+     chips have one flash bank.  In all cases the flash banks are at the
+     following fixed locations:
+
+          # Flash bank 0 - all chips
+          flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
+          # Flash bank 1 - only 256K chips
+          flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
+
+     Internally, the AT91SAM3 flash memory is organized as follows.
+     Unlike the AT91SAM7 chips, these are not used as parameters to the
+     'flash bank' command:
+
+        * _N-Banks:_ 256K chips have 2 banks, others have 1 bank.
+        * _Bank Size:_ 128K/64K Per flash bank
+        * _Sectors:_ 16 or 8 per bank
+        * _SectorSize:_ 8K Per Sector
+        * _PageSize:_ 256 bytes per page.  Note that OpenOCD operates on
+          'sector' sizes, not page sizes.
+
+     The AT91SAM3 driver adds some additional commands:
+
+      -- Command: at91sam3 gpnvm
+      -- Command: at91sam3 gpnvm clear number
+      -- Command: at91sam3 gpnvm set number
+      -- Command: at91sam3 gpnvm show ['all'|number]
+          With no parameters, 'show' or 'show all', shows the status of
+          all GPNVM bits.  With 'show' NUMBER, displays that bit.
+
+          With 'set' NUMBER or 'clear' NUMBER, modifies that GPNVM bit.
+
+      -- Command: at91sam3 info
+          This command attempts to display information about the
+          AT91SAM3 chip.  _First_ it read the 'CHIPID_CIDR' [address
+          0x400e0740, see Section 28.2.1, page 505 of the AT91SAM3U
+          29/may/2009 datasheet, document id: doc6430A] and decodes the
+          values.  _Second_ it reads the various clock configuration
+          registers and attempts to display how it believes the chip is
+          configured.  By default, the SLOWCLK is assumed to be 32768
+          Hz, see the command 'at91sam3 slowclk'.
+
+      -- Command: at91sam3 slowclk [value]
+          This command shows/sets the slow clock frequency used in the
+          'at91sam3 info' command calculations above.
+
+ -- Flash Driver: at91sam4
+     All members of the AT91SAM4 microcontroller family from Atmel
+     include internal flash and use ARM's Cortex-M4 core.  This driver
+     uses the same command names/syntax as *Note at91sam3::.
+
+ -- Flash Driver: at91sam4l
+     All members of the AT91SAM4L microcontroller family from Atmel
+     include internal flash and use ARM's Cortex-M4 core.  This driver
+     uses the same command names/syntax as *Note at91sam3::.
+
+     The AT91SAM4L driver adds some additional commands:
+      -- Command: at91sam4l smap_reset_deassert
+          This command releases internal reset held by SMAP and prepares
+          reset vector catch in case of reset halt.  Command is used
+          internally in event reset-deassert-post.
+
+ -- Flash Driver: atsame5
+     All members of the SAM E54, E53, E51 and D51 microcontroller
+     families from Microchip (former Atmel) include internal flash and
+     use ARM's Cortex-M4 core.
+
+     The devices have two ECC flash banks with a swapping feature.  This
+     driver handles both banks together as it were one.  Bank swapping
+     is not supported yet.
+
+          flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
+
+      -- Command: atsame5 bootloader
+          Shows or sets the bootloader size configuration, stored in the
+          User Page of the Flash.  This is called the BOOTPROT region.
+          When setting, the bootloader size must be specified in bytes.
+          The nearest bigger protection size is used.  Settings are
+          written immediately but only take effect on MCU reset.
+          Setting the bootloader size to 0 disables bootloader
+          protection.
+
+               atsame5 bootloader
+               atsame5 bootloader 16384
+
+      -- Command: atsame5 chip-erase
+          Issues a complete Flash erase via the Device Service Unit
+          (DSU). This can be used to erase a chip back to its factory
+          state and does not require the processor to be halted.
+
+      -- Command: atsame5 dsu_reset_deassert
+          This command releases internal reset held by DSU and prepares
+          reset vector catch in case of reset halt.  Command is used
+          internally in event reset-deassert-post.
+
+      -- Command: atsame5 userpage
+          Writes or reads the first 64 bits of NVM User Page which is
+          located at 0x804000.  This field includes various fuses.
+          Reading is done by invoking this command without any
+          arguments.  Writing is possible by giving 1 or 2 hex values.
+          The first argument is the value to be written and the second
+          one is an optional bit mask (a zero bit in the mask means the
+          bit stays unchanged).  The reserved fields are always masked
+          out and cannot be changed.
+
+               # Read
+               >atsame5 userpage
+               USER PAGE: 0xAEECFF80FE9A9239
+               # Write
+               >atsame5 userpage 0xAEECFF80FE9A9239
+               # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other
+               # bits unchanged (setup SmartEEPROM of virtual size 8192
+               # bytes)
+               >atsame5 userpage 0x4200000000 0x7f00000000
+
+ -- Flash Driver: atsamv
+     All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
+     Atmel include internal flash and use ARM's Cortex-M7 core.  This
+     driver uses the same command names/syntax as *Note at91sam3::.
+
+          flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
+
+      -- Command: atsamv gpnvm ['show' ['all'|number]]
+      -- Command: atsamv gpnvm ('clr'|'set') number
+          With no parameters, 'show' or 'show all', shows the status of
+          all GPNVM bits.  With 'show' NUMBER, displays that bit.
+
+          With 'set' NUMBER or 'clear' NUMBER, modifies that GPNVM bit.
+
+ -- Flash Driver: at91sam7
+     All members of the AT91SAM7 microcontroller family from Atmel
+     include internal flash and use ARM7TDMI cores.  The driver
+     automatically recognizes a number of these chips using the chip
+     identification register, and autoconfigures itself.
+
+          flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
+
+     For chips which are not recognized by the controller driver, you
+     must provide additional parameters in the following order:
+
+        * CHIP_MODEL ...  label used with 'flash info'
+        * BANKS
+        * SECTORS_PER_BANK
+        * PAGES_PER_SECTOR
+        * PAGES_SIZE
+        * NUM_NVM_BITS
+        * FREQ_KHZ ...  required if an external clock is provided,
+          optional (but recommended) when the oscillator frequency is
+          known
+
+     It is recommended that you provide zeroes for all of those values
+     except the clock frequency, so that everything except that
+     frequency will be autoconfigured.  Knowing the frequency helps
+     ensure correct timings for flash access.
+
+     The flash controller handles erases automatically on a page
+     (128/256 byte) basis, so explicit erase commands are not necessary
+     for flash programming.  However, there is an "EraseAll" command
+     that can erase an entire flash plane (of up to 256KB), and it will
+     be used automatically when you issue 'flash erase_sector' or 'flash
+     erase_address' commands.
+
+      -- Command: at91sam7 gpnvm bitnum ('set'|'clear')
+          Set or clear a "General Purpose Non-Volatile Memory" (GPNVM)
+          bit for the processor.  Each processor has a number of such
+          bits, used for controlling features such as brownout detection
+          (so they are not truly general purpose).
+               Note: This assumes that the first flash bank (number 0)
+               is associated with the appropriate at91sam7 target.
+
+ -- Flash Driver: avr
+     The AVR 8-bit microcontrollers from Atmel integrate flash memory.
+     _The current implementation is incomplete._
+
+ -- Flash Driver: bluenrg-x
+     STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP/LPS
+     Bluetooth low energy wireless system-on-chip.  They include ARM
+     Cortex-M0/M0+ core and internal flash memory.  The driver
+     automatically recognizes these chips using the chip identification
+     registers, and autoconfigures itself.
+
+          flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
+
+     Note that when users ask to erase all the sectors of the flash, a
+     mass erase command is used which is faster than erasing each single
+     sector one by one.
+
+          flash erase_sector 0 0 last # It will perform a mass erase
+
+     Triggering a mass erase is also useful when users want to disable
+     readout protection.
+
+ -- Flash Driver: cc26xx
+     All versions of the SimpleLink CC13xx and CC26xx microcontrollers
+     from Texas Instruments include internal flash.  The cc26xx flash
+     driver supports both the CC13xx and CC26xx family of devices.  The
+     driver automatically recognizes the specific version's flash
+     parameters and autoconfigures itself.  The flash bank starts at
+     address 0.
+
+          flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
+
+ -- Flash Driver: cc3220sf
+     The CC3220SF version of the SimpleLink CC32xx microcontrollers from
+     Texas Instruments includes 1MB of internal flash.  The cc3220sf
+     flash driver only supports the internal flash.  The serial flash on
+     SimpleLink boards is programmed via the bootloader over a UART
+     connection.  Security features of the CC3220SF may erase the
+     internal flash during power on reset.  Refer to documentation at
+      for details on security features and
+     programming the serial flash.
+
+          flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
+
+ -- Flash Driver: efm32
+     All members of the EFM32/EFR32 microcontroller family from Energy
+     Micro (now Silicon Labs) include internal flash and use Arm
+     Cortex-M3 or Cortex-M4 cores.  The driver automatically recognizes
+     a number of these chips using the chip identification register, and
+     autoconfigures itself.
+          flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
+     It supports writing to the user data page, as well as the portion
+     of the lockbits page past 512 bytes on chips with larger page
+     sizes.  The latter is used by the SiLabs bootloader/AppLoader
+     system for encryption keys.  Setting protection on these pages is
+     currently not supported.
+          flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
+          flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
+
+     A special feature of efm32 controllers is that it is possible to
+     completely disable the debug interface by writing the correct
+     values to the 'Debug Lock Word'.  OpenOCD supports this via the
+     following command:
+          efm32 debuglock num
+     The NUM parameter is a value shown by 'flash banks'.  Note that in
+     order for this command to take effect, the target needs to be
+     reset.  _The current implementation is incomplete.  Unprotecting
+     flash pages is not supported._
+
+ -- Flash Driver: eneispif
+     All versions of the KB1200 microcontrollers from ENE include
+     internal flash.  The eneispif flash driver supports the KB1200
+     family of devices.  The driver automatically recognizes the
+     specific version's flash parameters and autoconfigures itself.  The
+     flash bank starts at address 0x60000000.  An optional additional
+     parameter sets the address of eneispif controller, with the default
+     address is 0x50101000.
+
+
+          flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME \
+                     0x50101000
+
+          # Address defaults to 0x50101000
+          flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME
+
+
+ -- Flash Driver: esirisc
+     Members of the eSi-RISC family may optionally include internal
+     flash programmed via the eSi-TSMC Flash interface.  Additional
+     parameters are required to configure the driver: 'cfg_address' is
+     the base address of the configuration register interface,
+     'clock_hz' is the expected clock frequency, and 'wait_states' is
+     the number of configured read wait states.
+
+          flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
+                     $_TARGETNAME cfg_address clock_hz wait_states
+
+      -- Command: esirisc flash mass_erase bank_id
+          Erase all pages in data memory for the bank identified by
+          'bank_id'.
+
+      -- Command: esirisc flash ref_erase bank_id
+          Erase the reference cell for the bank identified by 'bank_id'.
+          _This is an uncommon operation._
+
+ -- Flash Driver: fm3
+     All members of the FM3 microcontroller family from Fujitsu include
+     internal flash and use ARM Cortex-M3 cores.  The FM3 driver uses
+     the TARGET parameter to select the correct bank config, it can
+     currently be one of the following: 'mb9bfxx1.cpu', 'mb9bfxx2.cpu',
+     'mb9bfxx3.cpu', 'mb9bfxx4.cpu', 'mb9bfxx5.cpu' or 'mb9bfxx6.cpu'.
+
+          flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
+
+ -- Flash Driver: fm4
+     All members of the FM4 microcontroller family from Spansion
+     (formerly Fujitsu) include internal flash and use ARM Cortex-M4
+     cores.  The FM4 driver uses a FAMILY parameter to select the
+     correct bank config, it can currently be one of the following:
+     'MB9BFx64', 'MB9BFx65', 'MB9BFx66', 'MB9BFx67', 'MB9BFx68',
+     'S6E2Cx8', 'S6E2Cx9', 'S6E2CxA' or 'S6E2Dx', with 'x' treated as
+     wildcard and otherwise case (and any trailing characters) ignored.
+
+          flash bank ${_FLASHNAME}0 fm4 0x00000000 0 0 0 \
+                     $_TARGETNAME S6E2CCAJ0A
+          flash bank ${_FLASHNAME}1 fm4 0x00100000 0 0 0 \
+                     $_TARGETNAME S6E2CCAJ0A
+     _The current implementation is incomplete.  Protection is not
+     supported, nor is Chip Erase (only Sector Erase is implemented)._
+
+ -- Flash Driver: kinetis
+     Several microcontrollers from NXP (former Freescale), including Kx,
+     KLx, KVx and KE1x members of the Kinetis family, and
+     S32K11x/S32K14x microcontrollers, include internal flash and use
+     ARM Cortex-M0+ or M4 cores.  Kinetis and S32K1 families use
+     incompatible identification registers, so the driver assumes
+     Kinetis and requires a driver option to indicate S32K1 is to be
+     used.  Within the familiy, the driver automatically recognizes
+     flash size and a number of flash banks (1-4) using the chip
+     identification register, and autoconfigures itself.  Use kinetis_ke
+     driver for KE0x and KEAx devices.
+
+     The KINETIS driver defines option:
+        * -s32k select S32K11x/S32K14x microcontroller flash support.
+
+        * -sim-base ADDR ...  base of System Integration Module where
+          chip identification resides.  Driver tries known locations if
+          option is omitted.
+
+          flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
+
+      -- Config Command: kinetis create_banks
+          Configuration command enables automatic creation of additional
+          flash banks based on real flash layout of device.  Banks are
+          created during device probe.  Use 'flash probe 0' to force
+          probe.
+
+      -- Command: kinetis fcf_source [protection|write]
+          Select what source is used when writing to a Flash
+          Configuration Field.  'protection' mode builds FCF content
+          from protection bits previously set by 'flash protect'
+          command.  This mode is default.  MCU is protected from
+          unwanted locking by immediate writing FCF after erase of
+          relevant sector.  'write' mode enables direct write to FCF.
+          Protection cannot be set by 'flash protect' command.  FCF is
+          written along with the rest of a flash image.  _BEWARE:
+          Incorrect flash configuration may permanently lock the
+          device!_
+
+      -- Command: kinetis fopt [num]
+          Set value to write to FOPT byte of Flash Configuration Field.
+          Used in kinetis 'fcf_source protection' mode only.
+
+      -- Command: kinetis mdm check_security
+          Checks status of device security lock.  Used internally in
+          examine-end and examine-fail event.
+
+      -- Command: kinetis mdm halt
+          Issues a halt via the MDM-AP. This command can be used to
+          break a watchdog reset loop when connecting to an unsecured
+          target.
+
+      -- Command: kinetis mdm mass_erase
+          Issues a complete flash erase via the MDM-AP. This can be used
+          to erase a chip back to its factory state, removing security.
+          It does not require the processor to be halted, however the
+          target will remain in a halted state after this command
+          completes.
+
+      -- Command: kinetis nvm_partition
+          For FlexNVM devices only (KxxDX and KxxFX). Not supported
+          (yet) on S32K1 devices.  Command shows or sets data flash or
+          EEPROM backup size in kilobytes, sets two EEPROM blocks sizes
+          in bytes and enables/disables loading of EEPROM contents to
+          FlexRAM during reset.
+
+          For details see device reference manual, Flash Memory Module,
+          Program Partition command.
+
+          Setting is possible only once after mass_erase.  Reset the
+          device after partition setting.
+
+          Show partition size:
+               kinetis nvm_partition info
+
+          Set 32 KB data flash, rest of FlexNVM is EEPROM backup.
+          EEPROM has two blocks of 512 and 1536 bytes and its contents
+          is loaded to FlexRAM during reset:
+               kinetis nvm_partition dataflash 32 512 1536 on
+
+          Set 16 KB EEPROM backup, rest of FlexNVM is a data flash.
+          EEPROM has two blocks of 1024 bytes and its contents is not
+          loaded to FlexRAM during reset:
+               kinetis nvm_partition eebkp 16 1024 1024 off
+
+      -- Command: kinetis mdm reset
+          Issues a reset via the MDM-AP. This causes the MCU to output a
+          low pulse on the RESET pin, which can be used to reset other
+          hardware on board.
+
+      -- Command: kinetis disable_wdog
+          For Kx devices only (KLx has different COP watchdog, it is not
+          supported).  Command disables watchdog timer.
+
+ -- Flash Driver: kinetis_ke
+     KE0x and KEAx members of the Kinetis microcontroller family from
+     NXP include internal flash and use ARM Cortex-M0+.  The driver
+     automatically recognizes the KE0x sub-family using the chip
+     identification register, and autoconfigures itself.  Use kinetis
+     (not kinetis_ke) driver for KE1x devices.
+
+          flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
+
+      -- Command: kinetis_ke mdm check_security
+          Checks status of device security lock.  Used internally in
+          examine-end event.
+
+      -- Command: kinetis_ke mdm mass_erase
+          Issues a complete Flash erase via the MDM-AP. This can be used
+          to erase a chip back to its factory state.  Command removes
+          security lock from a device (use of SRST highly recommended).
+          It does not require the processor to be halted.
+
+      -- Command: kinetis_ke disable_wdog
+          Command disables watchdog timer.
+
+ -- Flash Driver: lpc2000
+     This is the driver to support internal flash of all members of the
+     LPC11(x)00 and LPC1300 microcontroller families and most members of
+     the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
+     LPC8Nxx and NHS31xx microcontroller families from NXP.
+
+          Note: There are LPC2000 devices which are not supported by the
+          LPC2000 driver: The LPC2888 is supported by the LPC288X
+          driver.  The LPC29xx family is supported by the LPC2900
+          driver.
+
+     The LPC2000 driver defines two mandatory and two optional
+     parameters, which must appear in the following order:
+
+        * VARIANT ...  required, may be 'lpc2000_v1' (older LPC21xx and
+          LPC22xx) 'lpc2000_v2' (LPC213x, LPC214x, LPC210[123], LPC23xx
+          and LPC24xx) 'lpc1700' (LPC175x and LPC176x and LPC177x/8x)
+          'lpc4300' - available also as 'lpc1800' alias (LPC18x[2357]
+          and LPC43x[2357]) 'lpc800' (LPC8xx) 'lpc1100' (LPC11(x)xx and
+          LPC13xx) 'lpc1500' (LPC15xx) 'lpc54100' (LPC541xx) 'lpc4000'
+          (LPC40xx) or 'auto' - automatically detects flash variant and
+          size for LPC11(x)00, LPC8xx, LPC13xx, LPC17xx, LPC40xx,
+          LPC8Nxx and NHS31xx
+        * CLOCK_KHZ ...  the frequency, in kiloHertz, at which the core
+          is running
+        * 'calc_checksum' ...  optional (but you probably want to
+          provide this!), telling the driver to calculate a valid
+          checksum for the exception vector table.
+               Note: If you don't provide 'calc_checksum' when you're
+               writing the vector table, the boot ROM will almost
+               certainly ignore your flash image.  However, if you do
+               provide it, with most tool chains 'verify_image' will
+               fail.
+        * 'iap_entry' ...  optional telling the driver to use a
+          different ROM IAP entry point.
+
+     LPC flashes don't require the chip and bus width to be specified.
+
+          flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
+                lpc2000_v2 14765 calc_checksum
+
+      -- Command: lpc2000 part_id bank
+          Displays the four byte part identifier associated with the
+          specified flash BANK.
+
+ -- Flash Driver: lpc288x
+     The LPC2888 microcontroller from NXP needs slightly different flash
+     support from its lpc2000 siblings.  The LPC288X driver defines one
+     mandatory parameter, the programming clock rate in Hz.  LPC flashes
+     don't require the chip and bus width to be specified.
+
+          flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
+
+ -- Flash Driver: lpc2900
+     This driver supports the LPC29xx ARM968E based microcontroller
+     family from NXP.
+
+     The predefined parameters BASE, SIZE, CHIP_WIDTH and BUS_WIDTH of
+     the 'flash bank' command are ignored.  Flash size and sector layout
+     are auto-configured by the driver.  The driver has one additional
+     mandatory parameter: The CPU clock rate (in kHz) at the time the
+     flash operations will take place.  Most of the time this will not
+     be the crystal frequency, but a higher PLL frequency.  The
+     'reset-init' event handler in the board script is usually the place
+     where you start the PLL.
+
+     The driver rejects flashless devices (currently the LPC2930).
+
+     The EEPROM in LPC2900 devices is not mapped directly into the
+     address space.  It must be handled much more like NAND flash
+     memory, and will therefore be handled by a separate
+     'lpc2900_eeprom' driver (not yet available).
+
+     Sector protection in terms of the LPC2900 is handled transparently.
+     Every time a sector needs to be erased or programmed, it is
+     automatically unprotected.  What is shown as protection status in
+     the 'flash info' command, is actually the LPC2900 _sector
+     security_.  This is a mechanism to prevent a sector from ever being
+     erased or programmed again.  As this is an irreversible mechanism,
+     it is handled by a special command ('lpc2900 secure_sector'), and
+     not by the standard 'flash protect' command.
+
+     Example for a 125 MHz clock frequency:
+          flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
+
+     Some 'lpc2900'-specific commands are defined.  In the following
+     command list, the BANK parameter is the bank number as obtained by
+     the 'flash banks' command.
+
+      -- Command: lpc2900 signature bank
+          Calculates a 128-bit hash value, the _signature_, from the
+          whole flash content.  This is a hardware feature of the flash
+          block, hence the calculation is very fast.  You may use this
+          to verify the content of a programmed device against a known
+          signature.  Example:
+               lpc2900 signature 0
+                 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
+
+      -- Command: lpc2900 read_custom bank filename
+          Reads the 912 bytes of customer information from the flash
+          index sector, and saves it to a file in binary format.
+          Example:
+               lpc2900 read_custom 0 /path_to/customer_info.bin
+
+     The index sector of the flash is a _write-only_ sector.  It cannot
+     be erased!  In order to guard against unintentional write access,
+     all following commands need to be preceded by a successful call to
+     the 'password' command:
+
+      -- Command: lpc2900 password bank password
+          You need to use this command right before each of the
+          following commands: 'lpc2900 write_custom', 'lpc2900
+          secure_sector', 'lpc2900 secure_jtag'.
+
+          The password string is fixed to "I_know_what_I_am_doing".
+          Example:
+               lpc2900 password 0 I_know_what_I_am_doing
+                 Potentially dangerous operation allowed in next command!
+
+      -- Command: lpc2900 write_custom bank filename type
+          Writes the content of the file into the customer info space of
+          the flash index sector.  The filetype can be specified with
+          the TYPE field.  Possible values for TYPE are: BIN (binary),
+          IHEX (Intel hex format), ELF (ELF binary) or S19 (Motorola
+          S-records).  The file must contain a single section, and the
+          contained data length must be exactly 912 bytes.
+               Attention: This cannot be reverted!  Be careful!
+          Example:
+               lpc2900 write_custom 0 /path_to/customer_info.bin bin
+
+      -- Command: lpc2900 secure_sector bank first last
+          Secures the sector range from FIRST to LAST (including)
+          against further program and erase operations.  The sector
+          security will be effective after the next power cycle.
+               Attention: This cannot be reverted!  Be careful!
+          Secured sectors appear as _protected_ in the 'flash info'
+          command.  Example:
+               lpc2900 secure_sector 0 1 1
+               flash info 0
+                 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
+                         #  0: 0x00000000 (0x2000 8kB) not protected
+                         #  1: 0x00002000 (0x2000 8kB) protected
+                         #  2: 0x00004000 (0x2000 8kB) not protected
+
+      -- Command: lpc2900 secure_jtag bank
+          Irreversibly disable the JTAG port.  The new JTAG security
+          setting will be effective after the next power cycle.
+               Attention: This cannot be reverted!  Be careful!
+          Examples:
+               lpc2900 secure_jtag 0
+
+ -- Flash Driver: mdr
+     This drivers handles the integrated NOR flash on Milandr Cortex-M
+     based controllers.  A known limitation is that the Info memory
+     can't be read or verified as it's not memory mapped.
+
+          flash bank  mdr   \
+                0 0  TYPE PAGE_COUNT SEC_COUNT
+
+        * TYPE - 0 for main memory, 1 for info memory
+        * PAGE_COUNT - total number of pages
+        * SEC_COUNT - number of sector per page count
+
+     Example usage:
+          if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
+             flash bank ${_CHIPNAME}_info.flash mdr 0x00000000 0x01000 \
+                   0 0 $_TARGETNAME 1 1 4
+          } else {
+             flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
+                   0 0 $_TARGETNAME 0 32 4
+          }
+
+ -- Flash Driver: msp432
+     All versions of the SimpleLink MSP432 microcontrollers from Texas
+     Instruments include internal flash.  The msp432 flash driver
+     automatically recognizes the specific version's flash parameters
+     and autoconfigures itself.  Main program flash starts at address 0.
+     The information flash region on MSP432P4 versions starts at address
+     0x200000.
+
+          flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
+
+      -- Command: msp432 mass_erase bank_id [main|all]
+          Performs a complete erase of flash.  By default, 'mass_erase'
+          will erase only the main program flash.
+
+          On MSP432P4 versions, using 'mass_erase all' will erase both
+          the main program and information flash regions.  To also erase
+          the BSL in information flash, the user must first use the
+          'bsl' command.
+
+      -- Command: msp432 bsl bank_id [unlock|lock]
+          On MSP432P4 versions, 'bsl' unlocks and locks the bootstrap
+          loader (BSL) region in information flash so that flash
+          commands can erase or write the BSL. Leave the BSL locked to
+          prevent accidentally corrupting the bootstrap loader.
+
+          To erase and program the BSL:
+               msp432 bsl unlock
+               flash erase_address 0x202000 0x2000
+               flash write_image bsl.bin 0x202000
+               msp432 bsl lock
+
+ -- Flash Driver: niietcm4
+     This drivers handles the integrated NOR flash on NIIET Cortex-M4
+     based controllers.  Flash size and sector layout are
+     auto-configured by the driver.  Main flash memory is called
+     "Bootflash" and has main region and info region.  Info region is
+     NOT memory mapped by default, but it can replace first part of main
+     region if needed.  Full erase, single and block writes are
+     supported for both main and info regions.  There is additional not
+     memory mapped flash called "Userflash", which also have division
+     into regions: main and info.  Purpose of userflash - to store
+     system and user settings.  Driver has special commands to perform
+     operations with this memory.
+
+          flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
+
+     Some niietcm4-specific commands are defined:
+
+      -- Command: niietcm4 uflash_read_byte bank ('main'|'info') address
+          Read byte from main or info userflash region.
+
+      -- Command: niietcm4 uflash_write_byte bank ('main'|'info')
+               address value
+          Write byte to main or info userflash region.
+
+      -- Command: niietcm4 uflash_full_erase bank
+          Erase all userflash including info region.
+
+      -- Command: niietcm4 uflash_erase bank ('main'|'info')
+               first_sector last_sector
+          Erase sectors of main or info userflash region, starting at
+          sector first up to and including last.
+
+      -- Command: niietcm4 uflash_protect_check bank ('main'|'info')
+          Check sectors protect.
+
+      -- Command: niietcm4 uflash_protect bank ('main'|'info')
+               first_sector last_sector ('on'|'off')
+          Protect sectors of main or info userflash region, starting at
+          sector first up to and including last.
+
+      -- Command: niietcm4 bflash_info_remap bank ('on'|'off')
+          Enable remapping bootflash info region to 0x00000000 (or
+          0x40000000 if external memory boot used).
+
+      -- Command: niietcm4 extmem_cfg bank
+               ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh')
+               pin_num ('func1'|'func3')
+          Configure external memory interface for boot.
+
+      -- Command: niietcm4 service_mode_erase bank
+          Perform emergency erase of all flash (bootflash and
+          userflash).
+
+      -- Command: niietcm4 driver_info bank
+          Show information about flash driver.
+
+ -- Flash Driver: npcx
+     All versions of the NPCX microcontroller families from Nuvoton
+     include internal flash.  The NPCX flash driver supports the NPCX
+     family of devices.  The driver automatically recognizes the
+     specific version's flash parameters and autoconfigures itself.  The
+     flash bank starts at address 0x64000000.  An optional additional
+     parameter sets the FIU version for the bank, with the default FIU
+     is NPCX.FIU.
+
+
+          flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME npcx_v2.fiu
+
+          # FIU defaults to npcx.fiu
+          flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
+
+
+ -- Flash Driver: nrf5
+     Supports all members of the nRF51, nRF52 and nRF53 microcontroller
+     families from Nordic Semiconductor.  nRF91 family is supported too.
+     One driver handles both the main flash and the UICR area.
+
+     Flash protection is handled on nRF51 family and nRF52805, nRF52810,
+     nRF52811, nRF52832 devices.  Flash access control list (ACL)
+     protection scheme of the newer devices is not supported.
+
+          flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
+
+     Some nrf5-specific commands are defined:
+
+      -- Command: nrf5 mass_erase
+          Erases the contents of the code memory and user information
+          configuration registers as well.  It must be noted that this
+          command works only for chips that do not have factory
+          pre-programmed region 0 code.
+
+ -- Flash Driver: ocl
+     This driver is an implementation of the "on chip flash loader"
+     protocol proposed by Pavel Chromy.
+
+     It is a minimalistic command-response protocol intended to be used
+     over a DCC when communicating with an internal or external flash
+     loader running from RAM. An example implementation for AT91SAM7x is
+     available in 'contrib/loaders/flash/at91sam7x/'.
+
+          flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
+
+ -- Flash Driver: pic32mx
+     The PIC32MX microcontrollers are based on the MIPS 4K cores, and
+     integrate flash memory.
+
+          flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
+          flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
+
+     Some pic32mx-specific commands are defined:
+      -- Command: pic32mx pgm_word address value bank
+          Programs the specified 32-bit VALUE at the given ADDRESS in
+          the specified chip BANK.
+      -- Command: pic32mx unlock bank
+          Unlock and erase specified chip BANK.  This will remove any
+          Code Protection.
+
+ -- Flash Driver: psoc4
+     All members of the PSoC 41xx/42xx microcontroller family from
+     Cypress include internal flash and use ARM Cortex-M0 cores.  The
+     driver automatically recognizes a number of these chips using the
+     chip identification register, and autoconfigures itself.
+
+     Note: Erased internal flash reads as 00.  System ROM of PSoC 4 does
+     not implement erase of a flash sector.
+
+          flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
+
+     psoc4-specific commands
+      -- Command: psoc4 flash_autoerase num (on|off)
+          Enables or disables autoerase mode for a flash bank.
+
+          If flash_autoerase is off, use mass_erase before flash
+          programming.  Flash erase command fails if region to erase is
+          not whole flash memory.
+
+          If flash_autoerase is on, a sector is both erased and
+          programmed in one system ROM call.  Flash erase command is
+          ignored.  This mode is suitable for gdb load.
+
+          The NUM parameter is a value shown by 'flash banks'.
+
+      -- Command: psoc4 mass_erase num
+          Erases the contents of the flash memory, protection and
+          security lock.
+
+          The NUM parameter is a value shown by 'flash banks'.
+
+ -- Flash Driver: psoc5lp
+     All members of the PSoC 5LP microcontroller family from Cypress
+     include internal program flash and use ARM Cortex-M3 cores.  The
+     driver probes for a number of these chips and autoconfigures
+     itself, apart from the base address.
+
+          flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
+
+     Note: PSoC 5LP chips can be configured to have ECC enabled or
+     disabled.
+          Attention: If flash operations are performed in ECC-disabled
+          mode, they will also affect the ECC flash region.  Erasing a
+          16k flash sector in the 0x00000000 area will then also erase
+          the corresponding 2k data bytes in the 0x48000000 area.
+          Writing to the ECC data bytes in ECC-disabled mode is not
+          implemented.
+
+     Commands defined in the PSOC5LP driver:
+
+      -- Command: psoc5lp mass_erase
+          Erases all flash data and ECC/configuration bytes, all flash
+          protection rows, and all row latches in all flash arrays on
+          the device.
+
+ -- Flash Driver: psoc5lp_eeprom
+     All members of the PSoC 5LP microcontroller family from Cypress
+     include internal EEPROM and use ARM Cortex-M3 cores.  The driver
+     probes for a number of these chips and autoconfigures itself, apart
+     from the base address.
+
+          flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
+                     $_TARGETNAME
+
+ -- Flash Driver: psoc5lp_nvl
+     All members of the PSoC 5LP microcontroller family from Cypress
+     include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
+     The driver probes for a number of these chips and autoconfigures
+     itself.
+
+          flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
+
+     PSoC 5LP chips have multiple NV Latches:
+
+        * Device Configuration NV Latch - 4 bytes
+        * Write Once (WO) NV Latch - 4 bytes
+
+     Note: This driver only implements the Device Configuration NVL.
+
+     The PSOC5LP driver reads the ECC mode from Device Configuration
+     NVL.
+          Attention: Switching ECC mode via write to Device
+          Configuration NVL will require a reset after successful write.
+
+ -- Flash Driver: psoc6
+     Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
+     PSoC6 is a dual-core device with CM0+ and CM4 cores.  Both cores
+     share the same Flash/RAM/MMIO address space.
+
+     Flash in PSoC6 is split into three regions:
+        * Main Flash - this is the main storage for user application.
+          Total size varies among devices, sector size: 256 kBytes, row
+          size: 512 bytes.  Supports erase operation on individual rows.
+        * Work Flash - intended to be used as storage for user data
+          (e.g.  EEPROM emulation).  Total size: 32 KBytes, sector size:
+          32 KBytes, row size: 512 bytes.
+        * Supervisory Flash - special region which contains
+          device-specific service data.  This region does not support
+          erase operation.  Only few rows can be programmed by the user,
+          most of the rows are read only.  Programming operation will
+          erase row automatically.
+
+     All three flash regions are supported by the driver.  Flash
+     geometry is detected automatically by parsing data in
+     SPCIF_GEOMETRY register.
+
+     PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
+
+          flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
+                     ${TARGET}.cm0
+          flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
+                     ${TARGET}.cm0
+          flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
+                     ${TARGET}.cm0
+          flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
+                     ${TARGET}.cm0
+          flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
+                     ${TARGET}.cm0
+          flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
+                     ${TARGET}.cm0
+
+          flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
+                     ${TARGET}.cm4
+          flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
+                     ${TARGET}.cm4
+          flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
+                     ${TARGET}.cm4
+          flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
+                     ${TARGET}.cm4
+          flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
+                     ${TARGET}.cm4
+          flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
+                     ${TARGET}.cm4
+
+     psoc6-specific commands
+      -- Command: psoc6 reset_halt
+          Command can be used to simulate broken Vector Catch from
+          gdbinit or tcl scripts.  When invoked for CM0+ target, it will
+          set break point at application entry point and issue
+          SYSRESETREQ. This will reset both cores and all peripherals.
+          CM0+ will reset CM4 during boot anyway so this is safe.  On
+          CM4 target, VECTRESET is used instead of SYSRESETREQ to avoid
+          unwanted reset of CM0+;
+
+      -- Command: psoc6 mass_erase num
+          Erases the contents given flash bank.  The NUM parameter is a
+          value shown by 'flash banks'.  Note: only Main and Work flash
+          regions support Erase operation.
+
+ -- Flash Driver: qn908x
+     The NXP QN908x microcontrollers feature a Cortex-M4F with
+     integrated Bluetooth LE 5 support and an internal flash of up to
+     512 KiB. These chips only support the SWD interface.
+
+     The QN908X driver uses the internal "Flash Memory Controller" block
+     via SWD to erase, program and read the internal flash.  This driver
+     does not support the ISP (In-System Programming) mode which is an
+     alternate way to program the flash via UART, SPI or USB.
+
+     The internal flash is 512 KiB in size in all released chips and it
+     starts at the address 0x01000000, although it can be mapped to
+     address 0 and it is aliased to other addresses.  This driver only
+     recognizes the bank starting at address 0x01000000.
+
+     The internal bootloader stored in ROM is in charge of loading and
+     verifying the image from flash, or enter ISP mode.  The programmed
+     image must start at the beginning of the flash and contain a valid
+     header and a matching CRC32 checksum.  Additionally, the image
+     header contains a "Code Read Protection" (CRP) word which indicates
+     whether SWD access is enabled, as well as whether ISP mode is
+     enabled.  Therefore, it is possible to program an image that
+     disables SWD and ISP making it impossible to program another image
+     in the future through these interfaces, or even debug the current
+     image.  While this is a valid use case for production deployments
+     where the chips are locked down, by default this driver doesn't
+     allow such images that disable the SWD interface.  To program such
+     images see the 'qn908x allow_brick' command.
+
+     Apart from the CRP field which is located in the image header, the
+     last page of the flash memory contains a "Flash lock and protect"
+     descriptor which allows to individually protect each 2 KiB page, as
+     well as disabling SWD access to the flash and RAM. If this access
+     is disabled it is not possible to read, erase or program individual
+     pages from the SWD interface or even access the read-only "Flash
+     information page" with information about the bootloader version and
+     flash size.  However when this protection is in place, it is still
+     possible to mass erase the whole chip and then program a new image,
+     for which you can use the 'qn908x mass_erase'.
+
+     Example:
+          flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
+
+     Parameters:
+        * 'calc_checksum' optional parameter to compute the required
+          checksum of the first bytes in the vector table.
+               Note: If the checksum in the header of your image is
+               invalid and you don't provide the 'calc_checksum' option
+               the boot ROM will not boot your image and it may render
+               the flash inaccessible.  On the other hand, if you use
+               this option to compute the checksum keep in mind that
+               'verify_image' will fail on those four bytes of the
+               checksum since those bytes in the flash will have the
+               updated checksum.
+
+      -- Command: qn908x allow_brick
+          Allow the qn908x driver to program images with a "Code Read
+          Protection" byte that disables the SWD access.  Programming
+          such image will cause OpenOCD to not be able to reach the
+          target over SWD anymore after the new image is programmed and
+          its configuration takes effect, e.g.  after a reboot.  After
+          executing 'qn908x allow_brick' these images will be allowed to
+          be programmed when writing to the flash.
+
+      -- Command: qn908x disable_wdog
+          Disable the watchdog timer (WDT) by resetting its CTRL field.
+          The WDT starts enabled after a 'reset halt' and it doesn't run
+          while the target is halted.  However, the verification process
+          in this driver uses the generic Cortex-M verification process
+          which executes a payload in RAM and thus requires the watchdog
+          to be disabled before running 'verify_image' after a reset
+          halt or any other condition where the watchdog is running.
+          Note that this is not done automatically and you must run this
+          command in those scenarios.
+
+      -- Command: qn908x mass_erase
+          Erases the complete flash using the mass_erase method.  Mass
+          erase is only allowed if enabled in the Lock Status Register 8
+          (LOCK_STAT_8) which is read from the last sector of the flash
+          on boot.  However, this mass_erase lock protection can be
+          bypassed and this command does so automatically.
+
+          In the same LOCK_STAT_8 the flash and RAM access from SWD can
+          be disabled by setting two bits in this register.  After a
+          mass_erase, all the bits of the flash would be set, making it
+          the default to restrict SWD access to the flash and RAM
+          regions.  This new after erase LOCK_STAT_8 value only takes
+          effect after being read from flash on the next reboot for
+          example.  After a mass_erase the LOCK_STAT_8 register is
+          changed by the hardware to allow access to flash and RAM
+          regardless of the value on flash, but only right after a
+          mass_erase and until the next boot.  Therefore it is possible
+          to perform a mass_erase, program a new image, verify it and
+          then reboot to a valid image that's locked from the SWD
+          access.
+
+          The 'qn908x mass_erase' command clears the bits that would be
+          loaded from the flash into LOCK_STAT_8 after erasing the whole
+          chip to allow SWD access for debugging or re-flashing an image
+          without a mass_erase by default.  If the image being
+          programmed also programs the last page of the flash with its
+          own settings, this mass_erase behavior will interfere with
+          that write since a new erase of at least the last page would
+          need to be performed before writing to it again.  For this
+          reason the optional 'keep_lock' argument can be used to leave
+          the flash and RAM lock set.  For development environments, the
+          default behavior is desired.
+
+          The mass erase locking mechanism is independent from the
+          individual page locking bits, so it is possible that you can't
+          erase a given page that is locked and you can't unprotect that
+          page because the locking bits are also locked, but can still
+          mass erase the whole flash.
+
+ -- Flash Driver: rp2040
+     Supports RP2040 "Raspberry Pi Pico" microcontroller.  RP2040 is a
+     dual-core device with two CM0+ cores.  Both cores share the same
+     Flash/RAM/MMIO address space.  Non-volatile storage is achieved
+     with an external QSPI flash; a Boot ROM provides helper functions.
+
+          flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
+
+ -- Flash Driver: rsl10
+     Supports Onsemi RSL10 microcontroller flash memory.  Uses functions
+     stored in ROM to control flash memory interface.
+
+          flash bank $_FLASHNAME rsl10 $_FLASHBASE $_FLASHSIZE 0 0 $_TARGETNAME
+
+      -- Command: rsl10 lock key1 key2 key3 key4
+          Writes KEY1 KEY2 KEY3 KEY4 words to 0X81044 0X81048 0X8104C
+          0X8050.  Locks debug port by writing 0X4C6F634B to 0X81040.
+
+          To unlock use the 'rsl10 unlock key1 key2 key3 key4' command.
+
+      -- Command: rsl10 unlock key1 key2 key3 key4
+          Unlocks debug port, by writing KEY1 KEY2 KEY3 KEY4 words to
+          registers through DAP, and clears 0X81040 address in flash to
+          0x1.
+
+      -- Command: rsl10 mass_erase
+          Erases all unprotected flash sectors.
+
+ -- Flash Driver: sim3x
+     All members of the SiM3 microcontroller family from Silicon
+     Laboratories include internal flash and use ARM Cortex-M3 cores.
+     It supports both JTAG and SWD interface.  The SIM3X driver tries to
+     probe the device to auto detect the MCU. If this fails, it will use
+     the SIZE parameter as the size of flash bank.
+
+          flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
+
+     There are 2 commands defined in the SIM3X driver:
+
+      -- Command: sim3x mass_erase
+          Erases the complete flash.  This is used to unlock the flash.
+          And this command is only possible when using the SWD
+          interface.
+
+      -- Command: sim3x lock
+          Lock the flash.  To unlock use the 'sim3x mass_erase' command.
+
+ -- Flash Driver: stellaris
+     All members of the Stellaris LM3Sxxx, LM4x and Tiva C
+     microcontroller families from Texas Instruments include internal
+     flash.  The driver automatically recognizes a number of these chips
+     using the chip identification register, and autoconfigures itself.
+
+          flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
+
+      -- Command: stellaris recover
+          Performs the _Recovering a "Locked" Device_ procedure to
+          restore the flash and its associated nonvolatile registers to
+          their factory default values (erased).  This is the only way
+          to remove flash protection or re-enable debugging if that
+          capability has been disabled.
+
+          Note that the final "power cycle the chip" step in this
+          procedure must be performed by hand, since OpenOCD can't do
+          it.
+               Warning: if more than one Stellaris chip is connected,
+               the procedure is applied to all of them.
+
+ -- Flash Driver: stm32f1x
+     This driver supports the STM32F0, STM32F1 and STM32F3
+     microcontroller series from STMicroelectronics.  The driver is also
+     compatible with the GD32F1, GD32VF103 (RISC-V core), GD32F3 and
+     GD32E23 microcontroller series from GigaDevice.  The driver also
+     supports the APM32F0 and APM32F1 series from Geehy Semiconductor.
+     The driver automatically recognizes a number of these chips using
+     the chip identification register, and autoconfigures itself.
+
+          flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
+
+     Note that some devices have been found that have a flash size
+     register that contains an invalid value, to workaround this issue
+     you can override the probed value used by the flash driver.
+
+          flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
+
+     If you have a target with dual flash banks then define the second
+     bank as per the following example.
+          flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
+
+     Some stm32f1x-specific commands are defined:
+
+      -- Command: stm32f1x lock num
+          Locks the entire stm32 device against reading.  The NUM
+          parameter is a value shown by 'flash banks'.
+
+      -- Command: stm32f1x unlock num
+          Unlocks the entire stm32 device for reading.  This command
+          will cause a mass erase of the entire stm32 device if
+          previously locked.  The NUM parameter is a value shown by
+          'flash banks'.
+
+      -- Command: stm32f1x mass_erase num
+          Mass erases the entire stm32 device.  The NUM parameter is a
+          value shown by 'flash banks'.
+
+      -- Command: stm32f1x options_read num
+          Reads and displays active stm32 option bytes loaded during POR
+          or upon executing the 'stm32f1x options_load' command.  The
+          NUM parameter is a value shown by 'flash banks'.
+
+      -- Command: stm32f1x options_write num ('SWWDG'|'HWWDG')
+               ('RSTSTNDBY'|'NORSTSTNDBY') ('RSTSTOP'|'NORSTSTOP')
+               ('USEROPT' user_data)
+          Writes the stm32 option byte with the specified values.  The
+          NUM parameter is a value shown by 'flash banks'.  The
+          USER_DATA parameter is content of higher 16 bits of the option
+          byte register (Data0 and Data1 as one 16bit number).
+
+      -- Command: stm32f1x options_load num
+          Generates a special kind of reset to re-load the stm32 option
+          bytes written by the 'stm32f1x options_write' or 'flash
+          protect' commands without having to power cycle the target.
+          Not applicable to stm32f1x devices.  The NUM parameter is a
+          value shown by 'flash banks'.
+
+ -- Flash Driver: stm32f2x
+     All members of the STM32F2, STM32F4 and STM32F7 microcontroller
+     families from STMicroelectronics include internal flash and use ARM
+     Cortex-M3/M4/M7 cores.  The driver also works for the APM32F4
+     series from Geehy Semiconductor.  The driver automatically
+     recognizes a number of these chips using the chip identification
+     register, and autoconfigures itself.
+
+          flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+     If you use OTP (One-Time Programmable) memory define it as a second
+     bank as per the following example.
+          flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
+
+      -- Command: stm32f2x otp num ('enable'|'disable'|'show')
+          Enables or disables OTP write commands for bank NUM.  The NUM
+          parameter is a value shown by 'flash banks'.
+
+     Note that some devices have been found that have a flash size
+     register that contains an invalid value, to workaround this issue
+     you can override the probed value used by the flash driver.
+
+          flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
+
+     Some stm32f2x-specific commands are defined:
+
+      -- Command: stm32f2x lock num
+          Locks the entire stm32 device.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+      -- Command: stm32f2x unlock num
+          Unlocks the entire stm32 device.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+      -- Command: stm32f2x mass_erase num
+          Mass erases the entire stm32f2x device.  The NUM parameter is
+          a value shown by 'flash banks'.
+
+      -- Command: stm32f2x options_read num
+          Reads and displays user options and (where implemented)
+          boot_addr0, boot_addr1, optcr2.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+      -- Command: stm32f2x options_write num user_options boot_addr0
+               boot_addr1
+          Writes user options and (where implemented) boot_addr0 and
+          boot_addr1 in raw format.  Warning: The meaning of the various
+          bits depends on the device, always check datasheet!  The NUM
+          parameter is a value shown by 'flash banks', USER_OPTIONS a 12
+          bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR,
+          BOOT_ADDR0 and BOOT_ADDR1 two halfwords (of FLASH_OPTCR1).
+
+      -- Command: stm32f2x optcr2_write num optcr2
+          Writes FLASH_OPTCR2 options.  Warning: Clearing PCROPi bits
+          requires a full mass erase!  The NUM parameter is a value
+          shown by 'flash banks', OPTCR2 a 32-bit word.
+
+ -- Flash Driver: stm32h7x
+     All members of the STM32H7 microcontroller families from
+     STMicroelectronics include internal flash and use ARM Cortex-M7
+     core.  The driver automatically recognizes a number of these chips
+     using the chip identification register, and autoconfigures itself.
+
+          flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
+
+     Note that some devices have been found that have a flash size
+     register that contains an invalid value, to workaround this issue
+     you can override the probed value used by the flash driver.
+
+          flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
+
+     Some stm32h7x-specific commands are defined:
+
+      -- Command: stm32h7x lock num
+          Locks the entire stm32 device.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+      -- Command: stm32h7x unlock num
+          Unlocks the entire stm32 device.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+      -- Command: stm32h7x mass_erase num
+          Mass erases the entire stm32h7x device.  The NUM parameter is
+          a value shown by 'flash banks'.
+
+      -- Command: stm32h7x option_read num reg_offset
+          Reads an option byte register from the stm32h7x device.  The
+          NUM parameter is a value shown by 'flash banks', REG_OFFSET is
+          the register offset of the option byte to read from the used
+          bank registers' base.  For example: in STM32H74x/H75x the bank
+          1 registers' base is 0x52002000 and 0x52002100 for bank 2.
+
+          Example usage:
+               # read OPTSR_CUR
+               stm32h7x option_read 0 0x1c
+               # read WPSN_CUR1R
+               stm32h7x option_read 0 0x38
+               # read WPSN_CUR2R
+               stm32h7x option_read 1 0x38
+
+      -- Command: stm32h7x option_write num reg_offset value [reg_mask]
+          Writes an option byte register of the stm32h7x device.  The
+          NUM parameter is a value shown by 'flash banks', REG_OFFSET is
+          the register offset of the option byte to write from the used
+          bank register base, and REG_MASK is the mask to apply when
+          writing the register (only bits with a '1' will be touched).
+
+          Example usage:
+               # swap bank 1 and bank 2 in dual bank devices
+               # by setting SWAP_BANK_OPT bit in OPTSR_PRG
+               stm32h7x option_write 0 0x20 0x8000000 0x8000000
+
+ -- Flash Driver: stm32lx
+     All members of the STM32L0 and STM32L1 microcontroller families
+     from STMicroelectronics include internal flash and use ARM
+     Cortex-M3 and Cortex-M0+ cores.  The driver automatically
+     recognizes a number of these chips using the chip identification
+     register, and autoconfigures itself.
+
+          flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
+
+     Note that some devices have been found that have a flash size
+     register that contains an invalid value, to workaround this issue
+     you can override the probed value used by the flash driver.  If you
+     use 0 as the bank base address, it tells the driver to autodetect
+     the bank location assuming you're configuring the second bank.
+
+          flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
+
+     Some stm32lx-specific commands are defined:
+
+      -- Command: stm32lx lock num
+          Locks the entire stm32 device.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+      -- Command: stm32lx unlock num
+          Unlocks the entire stm32 device.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+      -- Command: stm32lx mass_erase num
+          Mass erases the entire stm32lx device (all flash banks and
+          EEPROM data).  This is the only way to unlock a protected
+          flash (unless RDP Level is 2 which can't be unlocked at all).
+          The NUM parameter is a value shown by 'flash banks'.
+
+ -- Flash Driver: stm32l4x
+     All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
+     microcontroller families from STMicroelectronics include internal
+     flash and use ARM Cortex-M0+, M4 and M33 cores.  The driver
+     automatically recognizes a number of these chips using the chip
+     identification register, and autoconfigures itself.
+
+          flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+     If you use OTP (One-Time Programmable) memory define it as a second
+     bank as per the following example.
+          flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
+
+      -- Command: stm32l4x otp num ('enable'|'disable'|'show')
+          Enables or disables OTP write commands for bank NUM.  The NUM
+          parameter is a value shown by 'flash banks'.
+
+     Note that some devices have been found that have a flash size
+     register that contains an invalid value, to workaround this issue
+     you can override the probed value used by the flash driver.
+     However, specifying a wrong value might lead to a completely wrong
+     flash layout, so this feature must be used carefully.
+
+          flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
+
+     Some stm32l4x-specific commands are defined:
+
+      -- Command: stm32l4x lock num
+          Locks the entire stm32 device.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+          _Note:_ To apply the protection change immediately, use
+          'stm32l4x option_load'.
+
+      -- Command: stm32l4x unlock num
+          Unlocks the entire stm32 device.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+          _Note:_ To apply the protection change immediately, use
+          'stm32l4x option_load'.
+
+      -- Command: stm32l4x mass_erase num
+          Mass erases the entire stm32l4x device.  The NUM parameter is
+          a value shown by 'flash banks'.
+
+      -- Command: stm32l4x option_read num reg_offset
+          Reads an option byte register from the stm32l4x device.  The
+          NUM parameter is a value shown by 'flash banks', REG_OFFSET is
+          the register offset of the Option byte to read.
+
+          For example to read the FLASH_OPTR register:
+               stm32l4x option_read 0 0x20
+               # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
+               # Option Register (for STM32WBx): <0x58004020> = ...
+               # The correct flash base address will be used automatically
+
+          The above example will read out the FLASH_OPTR register which
+          contains the RDP option byte, Watchdog configuration, BOR
+          level etc.
+
+      -- Command: stm32l4x option_write num reg_offset value [reg_mask]
+          Write an option byte register of the stm32l4x device.  The NUM
+          parameter is a value shown by 'flash banks', REG_OFFSET is the
+          register offset of the Option byte to write, and REG_MASK is
+          the mask to apply when writing the register (only bits with a
+          '1' will be touched).
+
+          _Note:_ To apply the option bytes change immediately, use
+          'stm32l4x option_load'.
+
+          For example to write the WRP1AR option bytes:
+               stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
+
+          The above example will write the WRP1AR option register
+          configuring the Write protection Area A for bank 1.  The above
+          example set WRP1AR_END=255, WRP1AR_START=0.  This will
+          effectively write protect all sectors in flash bank 1.
+
+      -- Command: stm32l4x wrp_info num [device_bank]
+          List the protected areas using WRP. The NUM parameter is a
+          value shown by 'flash banks'.  DEVICE_BANK parameter is
+          optional, possible values 'bank1' or 'bank2', if not
+          specified, the command will display the whole flash protected
+          areas.
+
+          Note: DEVICE_BANK is different from banks created using 'flash
+          bank'.  Devices supported in this flash driver, can have main
+          flash memory organized in single or dual-banks mode.  Thus the
+          usage of DEVICE_BANK is meaningful only in dual-bank mode, to
+          get write protected areas in a specific DEVICE_BANK
+
+      -- Command: stm32l4x option_load num
+          Forces a re-load of the option byte registers.  Will cause a
+          system reset of the device.  The NUM parameter is a value
+          shown by 'flash banks'.
+
+      -- Command: stm32l4x trustzone num ['enable' | 'disable']
+          Enables or disables Global TrustZone Security, using the TZEN
+          option bit.  If neither 'enabled' nor 'disable' are specified,
+          the command will display the TrustZone status.  _Note:_ This
+          command works only with devices with TrustZone, eg.  STM32L5.
+          _Note:_ This command will perform an OBL_Launch after
+          modifying the TZEN.
+
+ -- Flash Driver: str7x
+     All members of the STR7 microcontroller family from
+     STMicroelectronics include internal flash and use ARM7TDMI cores.
+     The STR7X driver defines one mandatory parameter, VARIANT, which is
+     either 'STR71x', 'STR73x' or 'STR75x'.
+
+          flash bank $_FLASHNAME str7x \
+                0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
+
+      -- Command: str7x disable_jtag bank
+          Activate the Debug/Readout protection mechanism for the
+          specified flash bank.
+
+ -- Flash Driver: str9x
+     Most members of the STR9 microcontroller family from
+     STMicroelectronics include internal flash and use ARM966E cores.
+     The str9 needs the flash controller to be configured using the
+     'str9x flash_config' command prior to Flash programming.
+
+          flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
+          str9x flash_config 0 4 2 0 0x80000
+
+      -- Command: str9x flash_config num bbsr nbbsr bbadr nbbadr
+          Configures the str9 flash controller.  The NUM parameter is a
+          value shown by 'flash banks'.
+
+             * BBSR - Boot Bank Size register
+             * NBBSR - Non Boot Bank Size register
+             * BBADR - Boot Bank Start Address register
+             * NBBADR - Boot Bank Start Address register
+
+ -- Flash Driver: str9xpec
+
+     Only use this driver for locking/unlocking the device or
+     configuring the option bytes.  Use the standard str9 driver for
+     programming.  Before using the flash commands the turbo mode must
+     be enabled using the 'str9xpec enable_turbo' command.
+
+     Here is some background info to help you better understand how this
+     driver works.  OpenOCD has two flash drivers for the str9:
+       1. Standard driver 'str9x' programmed via the str9 core.
+          Normally used for flash programming as it is faster than the
+          'str9xpec' driver.
+       2. Direct programming 'str9xpec' using the flash controller.
+          This is an ISC compliant (IEEE 1532) tap connected in series
+          with the str9 core.  The str9 core does not need to be running
+          to program using this flash driver.  Typical use for this
+          driver is locking/unlocking the target and programming the
+          option bytes.
+
+     Before we run any commands using the 'str9xpec' driver we must
+     first disable the str9 core.  This example assumes the 'str9xpec'
+     driver has been configured for flash bank 0.
+          # assert srst, we do not want core running
+          # while accessing str9xpec flash driver
+          adapter assert srst
+          # turn off target polling
+          poll off
+          # disable str9 core
+          str9xpec enable_turbo 0
+          # read option bytes
+          str9xpec options_read 0
+          # re-enable str9 core
+          str9xpec disable_turbo 0
+          poll on
+          reset halt
+     The above example will read the str9 option bytes.  When performing
+     a unlock remember that you will not be able to halt the str9 - it
+     has been locked.  Halting the core is not required for the
+     'str9xpec' driver as mentioned above, just issue the commands above
+     manually or from a telnet prompt.
+
+     Several str9xpec-specific commands are defined:
+
+      -- Command: str9xpec disable_turbo num
+          Restore the str9 into JTAG chain.
+
+      -- Command: str9xpec enable_turbo num
+          Enable turbo mode, will simply remove the str9 from the chain
+          and talk directly to the embedded flash controller.
+
+      -- Command: str9xpec lock num
+          Lock str9 device.  The str9 will only respond to an unlock
+          command that will erase the device.
+
+      -- Command: str9xpec part_id num
+          Prints the part identifier for bank NUM.
+
+      -- Command: str9xpec options_cmap num ('bank0'|'bank1')
+          Configure str9 boot bank.
+
+      -- Command: str9xpec options_lvdsel num ('vdd'|'vdd_vddq')
+          Configure str9 lvd source.
+
+      -- Command: str9xpec options_lvdthd num ('2.4v'|'2.7v')
+          Configure str9 lvd threshold.
+
+      -- Command: str9xpec options_lvdwarn bank ('vdd'|'vdd_vddq')
+          Configure str9 lvd reset warning source.
+
+      -- Command: str9xpec options_read num
+          Read str9 option bytes.
+
+      -- Command: str9xpec options_write num
+          Write str9 option bytes.
+
+      -- Command: str9xpec unlock num
+          unlock str9 device.
+
+ -- Flash Driver: swm050
+     All members of the swm050 microcontroller family from Foshan Synwit
+     Tech.
+
+          flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
+
+     One swm050-specific command is defined:
+
+      -- Command: swm050 mass_erase bank_id
+          Erases the entire flash bank.
+
+ -- Flash Driver: tms470
+     Most members of the TMS470 microcontroller family from Texas
+     Instruments include internal flash and use ARM7TDMI cores.  This
+     driver doesn't require the chip and bus width to be specified.
+
+     Some tms470-specific commands are defined:
+
+      -- Command: tms470 flash_keyset key0 key1 key2 key3
+          Saves programming keys in a register, to enable flash erase
+          and write commands.
+
+      -- Command: tms470 osc_megahertz clock_mhz
+          Reports the clock speed, which is used to calculate timings.
+
+      -- Command: tms470 plldis (0|1)
+          Disables (1) or enables (0) use of the PLL to speed up the
+          flash clock.
+
+ -- Flash Driver: w600
+     W60x series Wi-Fi SoC from WinnerMicro are designed with ARM
+     Cortex-M3 and have 1M Byte QFLASH inside.  The W600 driver uses the
+     TARGET parameter to select the correct bank config.
+
+          flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
+
+ -- Flash Driver: xmc1xxx
+     All members of the XMC1xxx microcontroller family from Infineon.
+     This driver does not require the chip and bus width to be
+     specified.
+
+ -- Flash Driver: xmc4xxx
+     All members of the XMC4xxx microcontroller family from Infineon.
+     This driver does not require the chip and bus width to be
+     specified.
+
+     Some xmc4xxx-specific commands are defined:
+
+      -- Command: xmc4xxx flash_password bank_id passwd1 passwd2
+          Saves flash protection passwords which are used to lock the
+          user flash
+
+      -- Command: xmc4xxx flash_unprotect bank_id user_level[0-1]
+          Removes Flash write protection from the selected user bank
+
+12.6 NAND Flash Commands
+========================
+
+Compared to NOR or SPI flash, NAND devices are inexpensive and high
+density.  Today's NAND chips, and multi-chip modules, commonly hold
+multiple GigaBytes of data.
+
+NAND chips consist of a number of "erase blocks" of a given size (such
+as 128 KBytes), each of which is divided into a number of pages (of
+perhaps 512 or 2048 bytes each).  Each page of a NAND flash has an "out
+of band" (OOB) area to hold Error Correcting Code (ECC) and other
+metadata, usually 16 bytes of OOB for every 512 bytes of page data.
+
+One key characteristic of NAND flash is that its error rate is higher
+than that of NOR flash.  In normal operation, that ECC is used to
+correct and detect errors.  However, NAND blocks can also wear out and
+become unusable; those blocks are then marked "bad".  NAND chips are
+even shipped from the manufacturer with a few bad blocks.  The highest
+density chips use a technology (MLC) that wears out more quickly, so ECC
+support is increasingly important as a way to detect blocks that have
+begun to fail, and help to preserve data integrity with techniques such
+as wear leveling.
+
+Software is used to manage the ECC. Some controllers don't support ECC
+directly; in those cases, software ECC is used.  Other controllers speed
+up the ECC calculations with hardware.  Single-bit error correction
+hardware is routine.  Controllers geared for newer MLC chips may correct
+4 or more errors for every 512 bytes of data.
+
+You will need to make sure that any data you write using OpenOCD
+includes the appropriate kind of ECC. For example, that may mean passing
+the 'oob_softecc' flag when writing NAND data, or ensuring that the
+correct hardware ECC mode is used.
+
+The basic steps for using NAND devices include:
+  1. Declare via the command 'nand device'
+     Do this in a board-specific configuration file, passing parameters
+     as needed by the controller.
+  2. Configure each device using 'nand probe'.
+     Do this only after the associated target is set up, such as in its
+     reset-init script or in procures defined to access that device.
+  3. Operate on the flash via 'nand subcommand'
+     Often commands to manipulate the flash are typed by a human, or run
+     via a script in some automated way.  Common task include writing a
+     boot loader, operating system, or other data needed to initialize
+     or de-brick a board.
+
+NOTE: At the time this text was written, the largest NAND flash fully
+supported by OpenOCD is 2 GiBytes (16 GiBits).  This is because the
+variables used to hold offsets and lengths are only 32 bits wide.
+(Larger chips may work in some cases, unless an offset or length is
+larger than 0xffffffff, the largest 32-bit unsigned integer.)  Some
+larger devices will work, since they are actually multi-chip modules
+with two smaller chips and individual chipselect lines.
+
+12.6.1 NAND Configuration Commands
+----------------------------------
+
+NAND chips must be declared in configuration scripts, plus some
+additional configuration that's done after OpenOCD has initialized.
+
+ -- Config Command: nand device name driver target [configparams...]
+     Declares a NAND device, which can be read and written to after it
+     has been configured through 'nand probe'.  In OpenOCD, devices are
+     single chips; this is unlike some operating systems, which may
+     manage multiple chips as if they were a single (larger) device.  In
+     some cases, configuring a device will activate extra commands; see
+     the controller-specific documentation.
+
+     NOTE: This command is not available after OpenOCD initialization
+     has completed.  Use it in board specific configuration files, not
+     interactively.
+
+        * NAME ...  may be used to reference the NAND bank in most other
+          NAND commands.  A number is also available.
+        * DRIVER ...  identifies the NAND controller driver associated
+          with the NAND device being declared.  *Note NAND Driver List:
+          nanddriverlist.
+        * TARGET ...  names the target used when issuing commands to the
+          NAND controller.
+        * CONFIGPARAMS ...  controllers may support, or require,
+          additional parameters.  See the controller-specific
+          documentation for more information.
+
+ -- Command: nand list
+     Prints a summary of each device declared using 'nand device',
+     numbered from zero.  Note that un-probed devices show no details.
+          > nand list
+          #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
+                  blocksize: 131072, blocks: 8192
+          #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
+                  blocksize: 131072, blocks: 8192
+          >
+
+ -- Command: nand probe num
+     Probes the specified device to determine key characteristics like
+     its page and block sizes, and how many blocks it has.  The NUM
+     parameter is the value shown by 'nand list'.  You must
+     (successfully) probe a device before you can use it with most other
+     NAND commands.
+
+12.6.2 Erasing, Reading, Writing to NAND Flash
+----------------------------------------------
+
+ -- Command: nand dump num filename offset length [oob_option]
+     Reads binary data from the NAND device and writes it to the file,
+     starting at the specified offset.  The NUM parameter is the value
+     shown by 'nand list'.
+
+     Use a complete path name for FILENAME, so you don't depend on the
+     directory used to start the OpenOCD server.
+
+     The OFFSET and LENGTH must be exact multiples of the device's page
+     size.  They describe a data region; the OOB data associated with
+     each such page may also be accessed.
+
+     NOTE: At the time this text was written, no error correction was
+     done on the data that's read, unless raw access was disabled and
+     the underlying NAND controller driver had a 'read_page' method
+     which handled that error correction.
+
+     By default, only page data is saved to the specified file.  Use an
+     OOB_OPTION parameter to save OOB data:
+        * no oob_* parameter
+          Output file holds only page data; OOB is discarded.
+        * 'oob_raw'
+          Output file interleaves page data and OOB data; the file will
+          be longer than "length" by the size of the spare areas
+          associated with each data page.  Note that this kind of "raw"
+          access is different from what's implied by 'nand raw_access',
+          which just controls whether a hardware-aware access method is
+          used.
+        * 'oob_only'
+          Output file has only raw OOB data, and will be smaller than
+          "length" since it will contain only the spare areas associated
+          with each data page.
+
+ -- Command: nand erase num [offset length]
+     Erases blocks on the specified NAND device, starting at the
+     specified OFFSET and continuing for LENGTH bytes.  Both of those
+     values must be exact multiples of the device's block size, and the
+     region they specify must fit entirely in the chip.  If those
+     parameters are not specified, the whole NAND chip will be erased.
+     The NUM parameter is the value shown by 'nand list'.
+
+     NOTE: This command will try to erase bad blocks, when told to do
+     so, which will probably invalidate the manufacturer's bad block
+     marker.  For the remainder of the current server session, 'nand
+     info' will still report that the block "is" bad.
+
+ -- Command: nand write num filename offset [option...]
+     Writes binary data from the file into the specified NAND device,
+     starting at the specified offset.  Those pages should already have
+     been erased; you can't change zero bits to one bits.  The NUM
+     parameter is the value shown by 'nand list'.
+
+     Use a complete path name for FILENAME, so you don't depend on the
+     directory used to start the OpenOCD server.
+
+     The OFFSET must be an exact multiple of the device's page size.
+     All data in the file will be written, assuming it doesn't run past
+     the end of the device.  Only full pages are written, and any extra
+     space in the last page will be filled with 0xff bytes.  (That
+     includes OOB data, if that's being written.)
+
+     NOTE: At the time this text was written, bad blocks are ignored.
+     That is, this routine will not skip bad blocks, but will instead
+     try to write them.  This can cause problems.
+
+     Provide at most one OPTION parameter.  With some NAND drivers, the
+     meanings of these parameters may change if 'nand raw_access' was
+     used to disable hardware ECC.
+        * no oob_* parameter
+          File has only page data, which is written.  If raw access is
+          in use, the OOB area will not be written.  Otherwise, if the
+          underlying NAND controller driver has a 'write_page' routine,
+          that routine may write the OOB with hardware-computed ECC
+          data.
+        * 'oob_only'
+          File has only raw OOB data, which is written to the OOB area.
+          Each page's data area stays untouched.  This can be a
+          dangerous option, since it can invalidate the ECC data.  You
+          may need to force raw access to use this mode.
+        * 'oob_raw'
+          File interleaves data and OOB data, both of which are written
+          If raw access is enabled, the data is written first, then the
+          un-altered OOB. Otherwise, if the underlying NAND controller
+          driver has a 'write_page' routine, that routine may modify the
+          OOB before it's written, to include hardware-computed ECC
+          data.
+        * 'oob_softecc'
+          File has only page data, which is written.  The OOB area is
+          filled with 0xff, except for a standard 1-bit software ECC
+          code stored in conventional locations.  You might need to
+          force raw access to use this mode, to prevent the underlying
+          driver from applying hardware ECC.
+        * 'oob_softecc_kw'
+          File has only page data, which is written.  The OOB area is
+          filled with 0xff, except for a 4-bit software ECC specific to
+          the boot ROM in Marvell Kirkwood SoCs.  You might need to
+          force raw access to use this mode, to prevent the underlying
+          driver from applying hardware ECC.
+
+ -- Command: nand verify num filename offset [option...]
+     Verify the binary data in the file has been programmed to the
+     specified NAND device, starting at the specified offset.  The NUM
+     parameter is the value shown by 'nand list'.
+
+     Use a complete path name for FILENAME, so you don't depend on the
+     directory used to start the OpenOCD server.
+
+     The OFFSET must be an exact multiple of the device's page size.
+     All data in the file will be read and compared to the contents of
+     the flash, assuming it doesn't run past the end of the device.  As
+     with 'nand write', only full pages are verified, so any extra space
+     in the last page will be filled with 0xff bytes.
+
+     The same OPTIONS accepted by 'nand write', and the file will be
+     processed similarly to produce the buffers that can be compared
+     against the contents produced from 'nand dump'.
+
+     NOTE: This will not work when the underlying NAND controller
+     driver's 'write_page' routine must update the OOB with a
+     hardware-computed ECC before the data is written.  This limitation
+     may be removed in a future release.
+
+12.6.3 Other NAND commands
+--------------------------
+
+ -- Command: nand check_bad_blocks num [offset length]
+     Checks for manufacturer bad block markers on the specified NAND
+     device.  If no parameters are provided, checks the whole device;
+     otherwise, starts at the specified OFFSET and continues for LENGTH
+     bytes.  Both of those values must be exact multiples of the
+     device's block size, and the region they specify must fit entirely
+     in the chip.  The NUM parameter is the value shown by 'nand list'.
+
+     NOTE: Before using this command you should force raw access with
+     'nand raw_access enable' to ensure that the underlying driver will
+     not try to apply hardware ECC.
+
+ -- Command: nand info num
+     The NUM parameter is the value shown by 'nand list'.  This prints
+     the one-line summary from "nand list", plus for devices which have
+     been probed this also prints any known status for each block.
+
+ -- Command: nand raw_access num ('enable'|'disable')
+     Sets or clears an flag affecting how page I/O is done.  The NUM
+     parameter is the value shown by 'nand list'.
+
+     This flag is cleared (disabled) by default, but changing that value
+     won't affect all NAND devices.  The key factor is whether the
+     underlying driver provides 'read_page' or 'write_page' methods.  If
+     it doesn't provide those methods, the setting of this flag is
+     irrelevant; all access is effectively "raw".
+
+     When those methods exist, they are normally used when reading data
+     ('nand dump' or reading bad block markers) or writing it ('nand
+     write').  However, enabling raw access (setting the flag) prevents
+     use of those methods, bypassing hardware ECC logic.  This can be a
+     dangerous option, since writing blocks with the wrong ECC data can
+     cause them to be marked as bad.
+
+12.6.4 NAND Driver List
+-----------------------
+
+As noted above, the 'nand device' command allows driver-specific options
+and behaviors.  Some controllers also activate controller-specific
+commands.
+
+ -- NAND Driver: at91sam9
+     This driver handles the NAND controllers found on AT91SAM9 family
+     chips from Atmel.  It takes two extra parameters: address of the
+     NAND chip; address of the ECC controller.
+          nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
+     AT91SAM9 chips support single-bit ECC hardware.  The 'write_page'
+     and 'read_page' methods are used to utilize the ECC hardware unless
+     they are disabled by using the 'nand raw_access' command.  There
+     are four additional commands that are needed to fully configure the
+     AT91SAM9 NAND controller.  Two are optional; most boards use the
+     same wiring for ALE/CLE:
+      -- Config Command: at91sam9 cle num addr_line
+          Configure the address line used for latching commands.  The
+          NUM parameter is the value shown by 'nand list'.
+      -- Config Command: at91sam9 ale num addr_line
+          Configure the address line used for latching addresses.  The
+          NUM parameter is the value shown by 'nand list'.
+
+     For the next two commands, it is assumed that the pins have already
+     been properly configured for input or output.
+      -- Config Command: at91sam9 rdy_busy num pio_base_addr pin
+          Configure the RDY/nBUSY input from the NAND device.  The NUM
+          parameter is the value shown by 'nand list'.  PIO_BASE_ADDR is
+          the base address of the PIO controller and PIN is the pin
+          number.
+      -- Config Command: at91sam9 ce num pio_base_addr pin
+          Configure the chip enable input to the NAND device.  The NUM
+          parameter is the value shown by 'nand list'.  PIO_BASE_ADDR is
+          the base address of the PIO controller and PIN is the pin
+          number.
+
+ -- NAND Driver: davinci
+     This driver handles the NAND controllers found on DaVinci family
+     chips from Texas Instruments.  It takes three extra parameters:
+     address of the NAND chip; hardware ECC mode to use ('hwecc1',
+     'hwecc4', 'hwecc4_infix'); address of the AEMIF controller on this
+     processor.
+          nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
+     All DaVinci processors support the single-bit ECC hardware, and
+     newer ones also support the four-bit ECC hardware.  The
+     'write_page' and 'read_page' methods are used to implement those
+     ECC modes, unless they are disabled using the 'nand raw_access'
+     command.
+
+ -- NAND Driver: lpc3180
+     These controllers require an extra 'nand device' parameter: the
+     clock rate used by the controller.
+      -- Command: lpc3180 select num [mlc|slc]
+          Configures use of the MLC or SLC controller mode.  MLC implies
+          use of hardware ECC. The NUM parameter is the value shown by
+          'nand list'.
+
+     At this writing, this driver includes 'write_page' and 'read_page'
+     methods.  Using 'nand raw_access' to disable those methods will
+     prevent use of hardware ECC in the MLC controller mode, but won't
+     change SLC behavior.
+
+ -- NAND Driver: mx3
+     This driver handles the NAND controller in i.MX31.  The mxc driver
+     should work for this chip as well.
+
+ -- NAND Driver: mxc
+     This driver handles the NAND controller found in Freescale i.MX
+     chips.  It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
+     The driver takes 3 extra arguments, chip ('mx27', 'mx31', 'mx35'),
+     ecc ('noecc', 'hwecc') and optionally if bad block information
+     should be swapped between main area and spare area ('biswap'),
+     defaults to off.
+          nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
+      -- Command: mxc biswap bank_num [enable|disable]
+          Turns on/off bad block information swapping from main area,
+          without parameter query status.
+
+ -- NAND Driver: orion
+     These controllers require an extra 'nand device' parameter: the
+     address of the controller.
+          nand device orion 0xd8000000
+     These controllers don't define any specialized commands.  At this
+     writing, their drivers don't include 'write_page' or 'read_page'
+     methods, so 'nand raw_access' won't change any behavior.
+
+ -- NAND Driver: s3c2410
+ -- NAND Driver: s3c2412
+ -- NAND Driver: s3c2440
+ -- NAND Driver: s3c2443
+ -- NAND Driver: s3c6400
+     These S3C family controllers don't have any special 'nand device'
+     options, and don't define any specialized commands.  At this
+     writing, their drivers don't include 'write_page' or 'read_page'
+     methods, so 'nand raw_access' won't change any behavior.
+
diff --git a/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/openocd.info-2 b/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/openocd.info-2
new file mode 100644
index 0000000..be93f77
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/linux/2025.10/share/doc/info/openocd.info-2
@@ -0,0 +1,5462 @@
+This is openocd.info, produced by makeinfo version 6.6 from
+openocd.texi.
+
+This User's Guide documents release 0.12.0+dev, dated 2 November 2025,
+of the Open On-Chip Debugger (OpenOCD).
+
+   * Copyright (C) 2008-2022 The OpenOCD Project
+   * Copyright (C) 2007-2008 Spencer Oliver 
+   * Copyright (C) 2008-2010 Oyvind Harboe 
+   * Copyright (C) 2008 Duane Ellis 
+   * Copyright (C) 2009-2010 David Brownell
+
+     Permission is granted to copy, distribute and/or modify this
+     document under the terms of the GNU Free Documentation License,
+     Version 1.2 or any later version published by the Free Software
+     Foundation; with no Invariant Sections, no Front-Cover Texts, and
+     no Back-Cover Texts.  A copy of the license is included in the
+     section entitled "GNU Free Documentation License".
+INFO-DIR-SECTION Development
+START-INFO-DIR-ENTRY
+* OpenOCD: (openocd).      OpenOCD User's Guide
+END-INFO-DIR-ENTRY
+
+
+File: openocd.info,  Node: Flash Programming,  Next: PLD/FPGA Commands,  Prev: Flash Commands,  Up: Top
+
+13 Flash Programming
+********************
+
+OpenOCD implements numerous ways to program the target flash, whether
+internal or external.  Programming can be achieved by either using *note
+Programming using GDB: programmingusinggdb, or using the commands given
+in *note Flash Programming Commands: flashprogrammingcommands.
+
+
+To simplify using the flash commands directly a jimtcl script is
+available that handles the programming and verify stage.  OpenOCD will
+program/verify/reset the target and optionally shutdown.
+
+The script is executed as follows and by default the following actions
+will be performed.
+  1. 'init' is executed.
+  2. 'reset init' is called to reset and halt the target, any 'reset
+     init' scripts are executed.
+  3. 'flash write_image' is called to erase and write any flash using
+     the filename given.
+  4. If the 'preverify' parameter is given, the target is "verified"
+     first and only flashed if this fails.
+  5. 'verify_image' is called if 'verify' parameter is given.
+  6. 'reset run' is called if 'reset' parameter is given.
+  7. OpenOCD is shutdown if 'exit' parameter is given.
+
+An example of usage is given below.  *Note program::.
+
+     # program and verify using elf/hex/s19. verify and reset
+     # are optional parameters
+     openocd -f board/stm32f3discovery.cfg \
+     	-c "program filename.elf verify reset exit"
+
+     # binary files need the flash address passing
+     openocd -f board/stm32f3discovery.cfg \
+     	-c "program filename.bin exit 0x08000000"
+
+
+File: openocd.info,  Node: PLD/FPGA Commands,  Next: General Commands,  Prev: Flash Programming,  Up: Top
+
+14 PLD/FPGA Commands
+********************
+
+Programmable Logic Devices (PLDs) and the more flexible Field
+Programmable Gate Arrays (FPGAs) are both types of programmable
+hardware.  OpenOCD can support programming them.  Although PLDs are
+generally restrictive (cells are less functional, and there are no
+special purpose cells for memory or computational tasks), they share the
+same OpenOCD infrastructure.  Accordingly, both are called PLDs here.
+
+14.1 PLD/FPGA Configuration and Commands
+========================================
+
+As it does for JTAG TAPs, debug targets, and flash chips (both NOR and
+NAND), OpenOCD maintains a list of PLDs available for use in various
+commands.  Also, each such PLD requires a driver.  PLD drivers may also
+be needed to program SPI flash connected to the FPGA to store the
+bitstream (*Note jtagspi:: for details).
+
+They are referenced by the name which was given when the pld was created
+or the number shown by the 'pld devices' command.  New PLDs are defined
+by 'pld create pld_name driver_name -chain-position tap_name
+[driver_options]'.
+
+ -- Config Command: pld create pld_name driver_name -chain-position
+          tap_name [driver_options]
+     Creates a new PLD device, supported by driver DRIVER_NAME,
+     assigning PLD_NAME for further reference.  '-chain-position'
+     TAP_NAME names the TAP used to access this target.  The driver may
+     make use of any DRIVER_OPTIONS to configure its behavior.
+
+ -- Command: pld devices
+     List the known PLDs with their name.
+
+ -- Command: pld load pld_name filename
+     Loads the file 'filename' into the PLD identified by PLD_NAME.  The
+     file format must be inferred by the driver.
+
+14.2 PLD/FPGA Drivers, Options, and Commands
+============================================
+
+Drivers may support PLD-specific options to the 'pld create' command,
+and may also define commands usable only with that particular type of
+PLD.
+
+ -- FPGA Driver: virtex2 ['-no_jstart']
+     Virtex-II is a family of FPGAs sold by Xilinx.  This driver can
+     also be used to load Series3, Series6, Series7 and Zynq 7000
+     devices.  It supports the IEEE 1532 standard for In-System
+     Configuration (ISC).
+
+     If -NO_JSTART is given, the JSTART instruction is not used after
+     loading the bitstream.  While required for Series2, Series3, and
+     Series6, it breaks bitstream loading on Series7.
+
+          openocd -f board/digilent_zedboard.cfg -c "init" \
+          	-c "pld load 0 zedboard_bitstream.bit"
+
+      -- Command: virtex2 read_stat pld_name
+          Reads and displays the Virtex-II status register (STAT) for
+          FPGA PLD_NAME.
+
+      -- Command: virtex2 set_instr_codes pld_name cfg_out cfg_in jprogb
+               jstart jshutdown [user1 [user2 [user3 [user4]]]]
+          Change values for boundary scan instructions.  Default are
+          values for Virtex 2, devices Virtex 4/5/6 and SSI devices are
+          using different values.  PLD_NAME is the name of the pld
+          device.  CFG_OUT is the value used to select CFG_OUT
+          instruction.  CFG_IN is the value used to select CFG_IN
+          instruction.  JPROGB is the value used to select JPROGRAM
+          instruction.  JSTART is the value used to select JSTART
+          instruction.  JSHUTDOWN is the value used to select JSHUTDOWN
+          instruction.  USER1 to USER4 are the intruction used to select
+          the user registers USER1 to USER4.
+
+      -- Command: virtex2 set_user_codes pld_name user1 [user2 [user3
+               [user4]]]
+          Change values for boundary scan instructions selecting the
+          registers USER1 to USER4.  Description of the arguments can be
+          found at command 'virtex2 set_instr_codes'.
+
+      -- Command: virtex2 refresh pld_name
+          Load the bitstream from external memory for FPGA PLD_NAME.
+          A.k.a.  program.
+
+ -- FPGA Driver: lattice ['-family' ]
+     The FGPA families ECP2, ECP3, ECP5, Certus and CertusPro by Lattice
+     are supported.  This driver can be used to load the bitstream into
+     the FPGA or read the status register and read/write the usercode
+     register.
+
+     For the option '-family' NAME is one of ECP2 ECP3 ECP5 CERTUS.
+     This is needed when the JTAG ID of the device is not known by
+     openocd (newer NX devices).
+
+      -- Command: lattice read_status pld_name
+          Reads and displays the status register for FPGA PLD_NAME.
+
+      -- Command: lattice read_user pld_name
+          Reads and displays the user register for FPGA PLD_NAME.
+
+      -- Command: lattice write_user pld_name val
+          Writes the user register.  for FPGA PLD_NAME with value VAL.
+
+      -- Command: lattice set_preload pld_name length
+          Set the length of the register for the preload.  This is
+          needed when the JTAG ID of the device is not known by openocd
+          (newer NX devices).  The load command for the FPGA PLD_NAME
+          will use a length for the preload of LENGTH.
+
+      -- Command: lattice refresh pld_name
+          Load the bitstream from external memory for FPGA PLD_NAME.
+          A.k.a program.
+
+ -- FPGA Driver: efinix ['-family' ]
+     Both families (Trion and Titanium) sold by Efinix are supported as
+     both use the same protocol for In-System Configuration.  This
+     driver can be used to load the bitstream into the FPGA. For the
+     option '-family' NAME is one of TRION|TITANIUM.
+
+ -- FPGA Driver: intel '-family' 
+     This driver can be used to load the bitstream into Intel (former
+     Altera) FPGAs.  The families Cyclone III, Cyclone IV, Cyclone V,
+     Cyclone 10 and Arria II are supported.
+
+     The option '-family' NAME is one of CYCLONEIII CYCLONEIV CYCLONEV
+     CYCLONE10 ARRIAII.
+
+     As input file format the driver supports a '.rbf' (raw bitstream
+     file) file.  The '.rbf' file can be generated from a '.sof' file
+     with quartus_cpf -c blinker.sof blinker.rbf
+
+     Creates a new PLD device, an FPGA of the Cyclone III family, using
+     the TAP named cycloneiii.tap:
+          pld create cycloneiii.pld intel -chain-position cycloneiii.tap -family cycloneiii
+
+      -- Command: intel set_bscan pld_name len
+          Set boundary scan register length of FPGA PLD_NAME to LEN.
+          This is needed because the length can vary between chips with
+          the same JTAG ID.
+
+      -- Command: intel set_check_pos pld_name pos
+          Selects the position POS in the boundary-scan register.  The
+          bit at this position is checked after loading the bitstream
+          and must be '1', which is the case when no error occurred.
+          With a value of -1 for POS the check will be omitted.
+
+ -- FPGA Driver: gowin
+     This driver can be used to load the bitstream into FPGAs from
+     Gowin.  It is possible to program the SRAM. Programming the flash
+     is not supported.  The files .fs and .bin generated by Gowin FPGA
+     Designer are supported.
+
+      -- Command: gowin read_status pld_name
+          Reads and displays the status register for FPGA PLD_NAME.
+
+      -- Command: gowin read_user pld_name
+          Reads and displays the user register for FPGA PLD_NAME.
+
+      -- Command: gowin refresh pld_name
+          Load the bitstream from external memory for FPGA PLD_NAME.
+          A.k.a.  reload.
+
+ -- FPGA Driver: gatemate
+     This driver can be used to load the bitstream into GateMate FPGAs
+     form CologneChip.  The files .bit and .cfg both generated by p_r
+     tool from CologneChip are supported.
+
+
+File: openocd.info,  Node: General Commands,  Next: Architecture and Core Commands,  Prev: PLD/FPGA Commands,  Up: Top
+
+15 General Commands
+*******************
+
+The commands documented in this chapter here are common commands that
+you, as a human, may want to type and see the output of.  Configuration
+type commands are documented elsewhere.
+
+Intent:
+   * Source Of Commands
+     OpenOCD commands can occur in a configuration script (discussed
+     elsewhere) or typed manually by a human or supplied
+     programmatically, or via one of several TCP/IP Ports.
+
+   * From the human
+     A human should interact with the telnet interface (default port:
+     4444) or via GDB (default port 3333).
+
+     To issue commands from within a GDB session, use the 'monitor'
+     command, e.g.  use 'monitor poll' to issue the 'poll' command.  All
+     output is relayed through the GDB session.
+
+   * Machine Interface The Tcl interface's intent is to be a machine
+     interface.  The default Tcl port is 6666.
+
+15.1 Server Commands
+====================
+
+ -- Command: exit
+     Exits the current telnet session.
+
+ -- Command: help [string]
+     With no parameters, prints help text for all commands.  Otherwise,
+     prints each helptext containing STRING.  Not every command provides
+     helptext.
+
+     Configuration commands, and commands valid at any time, are
+     explicitly noted in parenthesis.  In most cases, no such
+     restriction is listed; this indicates commands which are only
+     available after the configuration stage has completed.
+
+ -- Command: usage [string]
+     With no parameters, prints usage text for all commands.  Otherwise,
+     prints all usage text of which command, help text, and usage text
+     containing STRING.  Not every command provides helptext.
+
+ -- Command: sleep msec ['busy']
+     Wait for at least MSEC milliseconds before resuming.  If 'busy' is
+     passed, busy-wait instead of sleeping.  (This option is strongly
+     discouraged.)  Useful in connection with script files ('script'
+     command and 'target_name' configuration).
+
+ -- Command: shutdown ['error']
+     Close the OpenOCD server, disconnecting all clients (GDB, telnet,
+     other).  If option 'error' is used, OpenOCD will return a non-zero
+     exit code to the parent process.
+
+     If user types CTRL-C or kills OpenOCD, the command 'shutdown' will
+     be automatically executed to cause OpenOCD to exit.
+
+     It is possible to specify, in the TCL list PRE_SHUTDOWN_COMMANDS ,
+     a set of commands to be automatically executed before 'shutdown' ,
+     e.g.:
+          lappend pre_shutdown_commands {echo "Goodbye, my friend ..."}
+          lappend pre_shutdown_commands {echo "see you soon !"}
+     The commands in the list will be executed (in the same order they
+     occupy in the list) before OpenOCD exits.  If one of the commands
+     in the list fails, then the remaining commands are not executed
+     anymore while OpenOCD will proceed to quit.
+
+ -- Command: debug_level [n]
+     Display debug level.  If N (from 0..4) is provided, then set it to
+     that level.  This affects the kind of messages sent to the server
+     log.  Level 0 is error messages only; level 1 adds warnings; level
+     2 adds informational messages; level 3 adds debugging messages; and
+     level 4 adds verbose low-level debug messages.  The default is
+     level 2, but that can be overridden on the command line along with
+     the location of that log file (which is normally the server's
+     standard output).  *Note Running::.
+
+ -- Command: echo [-n] message
+     Logs a message at "user" priority.  Option "-n" suppresses trailing
+     newline.
+          echo "Downloading kernel -- please wait"
+
+ -- Command: log_output [filename | 'default']
+     Redirect logging to FILENAME.  If used without an argument or
+     FILENAME is set to 'default' log output channel is set to stderr.
+
+ -- Command: add_script_search_dir [directory]
+     Add DIRECTORY to the file/script search path.
+
+ -- Config Command: bindto [NAME]
+     Specify hostname or IPv4 address on which to listen for incoming
+     TCP/IP connections.  By default, OpenOCD will listen on the
+     loopback interface only.  If your network environment is safe,
+     'bindto 0.0.0.0' can be used to cover all available interfaces.
+
+15.2 Target State handling
+==========================
+
+In this section "target" refers to a CPU configured as shown earlier
+(*note CPU Configuration::).  These commands, like many, implicitly
+refer to a current target which is used to perform the various
+operations.  The current target may be changed by using 'targets'
+command with the name of the target which should become current.
+
+ -- Command: reg [(number|name) [(value|'force')]]
+     Access a single register by NUMBER or by its NAME.  The target must
+     generally be halted before access to CPU core registers is allowed.
+     Depending on the hardware, some other registers may be accessible
+     while the target is running.
+
+     _With no arguments_: list all available registers for the current
+     target, showing number, name, size, value, and cache status.  For
+     valid entries, a value is shown; valid entries which are also dirty
+     (and will be written back later) are flagged as such.
+
+     _With number/name_: display that register's value.  Use FORCE
+     argument to read directly from the target, bypassing any internal
+     cache.
+
+     _With both number/name and value_: set register's value.  Writes
+     may be held in a writeback cache internal to OpenOCD, so that
+     setting the value marks the register as dirty instead of
+     immediately flushing that value.  Resuming CPU execution (including
+     by single stepping) or otherwise activating the relevant module
+     will flush such values.
+
+     Cores may have surprisingly many registers in their Debug and trace
+     infrastructure:
+
+          > reg
+          ===== ARM registers
+          (0) r0 (/32): 0x0000D3C2 (dirty)
+          (1) r1 (/32): 0xFD61F31C
+          (2) r2 (/32)
+          ...
+          (164) ETM_contextid_comparator_mask (/32)
+          >
+
+ -- Command: set_reg dict
+     Set register values of the target.
+
+        * DICT ...  Tcl dictionary with pairs of register names and
+          values.
+
+     For example, the following command sets the value 0 to the program
+     counter (pc) register and 0x1000 to the stack pointer (sp)
+     register:
+
+          set_reg {pc 0 sp 0x1000}
+
+ -- Command: get_reg [-force] list
+     Get register values from the target and return them as Tcl
+     dictionary with pairs of register names and values.  If option
+     "-force" is set, the register values are read directly from the
+     target, bypassing any caching.
+
+        * LIST ...  List of register names
+
+     For example, the following command retrieves the values from the
+     program counter (pc) and stack pointer (sp) register:
+
+          get_reg {pc sp}
+
+ -- Command: write_memory address width data ['phys']
+     This function provides an efficient way to write to the target
+     memory from a Tcl script.
+
+        * ADDRESS ...  target memory address
+        * WIDTH ...  memory access bit size, can be 8, 16, 32 or 64
+        * DATA ...  Tcl list with the elements to write
+        * ['phys'] ...  treat the memory address as physical instead of
+          virtual address
+
+     For example, the following command writes two 32 bit words into the
+     target memory at address 0x20000000:
+
+          write_memory 0x20000000 32 {0xdeadbeef 0x00230500}
+
+ -- Command: read_memory address width count ['phys']
+     This function provides an efficient way to read the target memory
+     from a Tcl script.  A Tcl list containing the requested memory
+     elements is returned by this function.
+
+        * ADDRESS ...  target memory address
+        * WIDTH ...  memory access bit size, can be 8, 16, 32 or 64
+        * COUNT ...  number of elements to read
+        * ['phys'] ...  treat the memory address as physical instead of
+          virtual address
+
+     For example, the following command reads two 32 bit words from the
+     target memory at address 0x20000000:
+
+          read_memory 0x20000000 32 2
+
+ -- Command: debug_reason
+     Displays the current debug reason: 'debug-request', 'breakpoint',
+     'watchpoint', 'watchpoint-and-breakpoint', 'single-step',
+     'target-not-halted', 'program-exit', 'exception-catch' or
+     'undefined'.
+
+ -- Command: halt [ms]
+ -- Command: wait_halt [ms]
+     The 'halt' command first sends a halt request to the target, which
+     'wait_halt' doesn't.  Otherwise these behave the same: wait up to
+     MS milliseconds, or 5 seconds if there is no parameter, for the
+     target to halt (and enter debug mode).  Using 0 as the MS parameter
+     prevents OpenOCD from waiting.
+
+          Warning: On ARM cores, software using the _wait for interrupt_
+          operation often blocks the JTAG access needed by a 'halt'
+          command.  This is because that operation also puts the core
+          into a low power mode by gating the core clock; but the core
+          clock is needed to detect JTAG clock transitions.
+
+          One partial workaround uses adaptive clocking: when the core
+          is interrupted the operation completes, then JTAG clocks are
+          accepted at least until the interrupt handler completes.
+          However, this workaround is often unusable since the
+          processor, board, and JTAG adapter must all support adaptive
+          JTAG clocking.  Also, it can't work until an interrupt is
+          issued.
+
+          A more complete workaround is to not use that operation while
+          you work with a JTAG debugger.  Tasking environments generally
+          have idle loops where the body is the _wait for interrupt_
+          operation.  (On older cores, it is a coprocessor action; newer
+          cores have a 'wfi' instruction.)  Such loops can just remove
+          that operation, at the cost of higher power consumption
+          (because the CPU is needlessly clocked).
+
+ -- Command: resume [address]
+     Resume the target at its current code position, or the optional
+     ADDRESS if it is provided.
+
+     NOTE: targets are expected to temporary disable breakpoints if they
+     match the address of the current code position or the ADDRESS
+     provided by user.
+
+ -- Command: step [address]
+     Single-step the target at its current code position, or the
+     optional ADDRESS if it is provided.
+
+     NOTE: targets are expected to temporary disable breakpoints if they
+     match the address of the current code position or the ADDRESS
+     provided by user.
+
+ -- Command: reset
+ -- Command: reset run
+ -- Command: reset halt
+ -- Command: reset init
+     Perform as hard a reset as possible, using SRST if possible.  _All
+     defined targets will be reset, and target events will fire during
+     the reset sequence._
+
+     The optional parameter specifies what should happen after the
+     reset.  If there is no parameter, a 'reset run' is executed.  The
+     other options will not work on all systems.  *Note Reset
+     Configuration::.
+
+        - run Let the target run
+        - halt Immediately halt the target
+        - init Immediately halt the target, and execute the reset-init
+          script
+
+ -- Command: soft_reset_halt
+     Requesting target halt and executing a soft reset.  This is often
+     used when a target cannot be reset and halted.  The target, after
+     reset is released begins to execute code.  OpenOCD attempts to stop
+     the CPU and then sets the program counter back to the reset vector.
+     Unfortunately the code that was executed may have left the hardware
+     in an unknown state.
+
+ -- Command: adapter assert [signal [assert|deassert signal]]
+ -- Command: adapter deassert [signal [assert|deassert signal]]
+     Set values of reset signals.  Without parameters returns current
+     status of the signals.  The SIGNAL parameter values may be 'srst',
+     indicating that srst signal is to be asserted or deasserted,
+     'trst', indicating that trst signal is to be asserted or
+     deasserted.
+
+     The 'reset_config' command should already have been used to
+     configure how the board and the adapter treat these two signals,
+     and to say if either signal is even present.  *Note Reset
+     Configuration::.  Trying to assert a signal that is not present
+     triggers an error.  If a signal is present on the adapter and not
+     specified in the command, the signal will not be modified.
+
+          Note: TRST is specially handled.  It actually signifies JTAG's
+          RESET state.  So if the board doesn't support the optional
+          TRST signal, or it doesn't support it along with the specified
+          SRST value, JTAG reset is triggered with TMS and TCK signals
+          instead of the TRST signal.  And no matter how that JTAG reset
+          is triggered, once the scan chain enters RESET with TRST
+          inactive, TAP 'post-reset' events are delivered to all TAPs
+          with handlers for that event.
+
+15.3 Memory access commands
+===========================
+
+These commands allow accesses of a specific size to the memory system.
+Often these are used to configure the current target in some special
+way.  For example - one may need to write certain values to the SDRAM
+controller to enable SDRAM.
+
+  1. Use the 'targets' (plural) command to change the current target.
+  2. In system level scripts these commands are deprecated.  Please use
+     their TARGET object siblings to avoid making assumptions about what
+     TAP is the current target, or about MMU configuration.
+
+ -- Command: mdd [phys] addr [count]
+ -- Command: mdw [phys] addr [count]
+ -- Command: mdh [phys] addr [count]
+ -- Command: mdb [phys] addr [count]
+     Display contents of address ADDR, as 64-bit doublewords ('mdd'),
+     32-bit words ('mdw'), 16-bit halfwords ('mdh'), or 8-bit bytes
+     ('mdb').  When the current target has an MMU which is present and
+     active, ADDR is interpreted as a virtual address.  Otherwise, or if
+     the optional PHYS flag is specified, ADDR is interpreted as a
+     physical address.  If COUNT is specified, displays that many units.
+     (If you want to process the data instead of displaying it, see the
+     'read_memory' primitives.)
+
+ -- Command: mwd [phys] addr doubleword [count]
+ -- Command: mww [phys] addr word [count]
+ -- Command: mwh [phys] addr halfword [count]
+ -- Command: mwb [phys] addr byte [count]
+     Writes the specified DOUBLEWORD (64 bits), WORD (32 bits), HALFWORD
+     (16 bits), or BYTE (8-bit) value, at the specified address ADDR.
+     When the current target has an MMU which is present and active,
+     ADDR is interpreted as a virtual address.  Otherwise, or if the
+     optional PHYS flag is specified, ADDR is interpreted as a physical
+     address.  If COUNT is specified, fills that many units of
+     consecutive address.
+
+15.4 Image loading commands
+===========================
+
+ -- Command: dump_image filename address size
+     Dump SIZE bytes of target memory starting at ADDRESS to the binary
+     file named FILENAME.
+
+ -- Command: fast_load
+     Loads an image stored in memory by 'fast_load_image' to the current
+     target.  Must be preceded by fast_load_image.
+
+ -- Command: fast_load_image filename [address ['bin'|'ihex'|'elf'|'s19'
+          ['min_addr' ['max_length']]]]
+     Normally you should be using 'load_image' or GDB load.  However,
+     for testing purposes or when I/O overhead is significant(OpenOCD
+     running on an embedded host), storing the image in memory and
+     uploading the image to the target can be a way to upload e.g.
+     multiple debug sessions when the binary does not change.  Arguments
+     are the same as 'load_image', but the image is stored in OpenOCD
+     host memory, i.e.  does not affect target.  This approach is also
+     useful when profiling target programming performance as I/O and
+     target programming can easily be profiled separately.
+
+ -- Command: load_image filename [address ['bin'|'ihex'|'elf'|'s19'
+          ['min_addr' ['max_length']]]]
+     Load image from file FILENAME to target memory.  If an ADDRESS is
+     specified, it is used as an offset to the file format defined
+     addressing (e.g.  'bin' file is loaded at that address).  The file
+     format may optionally be specified ('bin', 'ihex', 'elf', or
+     's19').  In addition the following arguments may be specified:
+     MIN_ADDR - ignore data below MIN_ADDR (this is w.r.t.  to the
+     target's load address + ADDRESS) MAX_LENGTH - maximum number of
+     bytes to load.
+          proc load_image_bin {fname foffset address length } {
+              # Load data from fname filename at foffset offset to
+              # target at address. Load at most length bytes.
+              load_image $fname [expr {$address - $foffset}] bin \
+                         $address $length
+          }
+
+ -- Command: test_image filename [address ['bin'|'ihex'|'elf']]
+     Displays image section sizes and addresses as if FILENAME were
+     loaded into target memory starting at ADDRESS (defaults to zero).
+     The file format may optionally be specified ('bin', 'ihex', or
+     'elf')
+
+ -- Command: verify_image filename [address ['bin'|'ihex'|'elf']]
+     Verify FILENAME against target memory.  If an ADDRESS is specified,
+     it is used as an offset to the file format defined addressing (e.g.
+     'bin' file is compared against memory starting at that address).
+     The file format may optionally be specified ('bin', 'ihex', or
+     'elf') This will first attempt a comparison using a CRC checksum,
+     if this fails it will try a binary compare.
+
+ -- Command: verify_image_checksum filename [address
+          ['bin'|'ihex'|'elf']]
+     Verify FILENAME against target memory.  If an ADDRESS is specified,
+     it is used as an offset to the file format defined addressing (e.g.
+     'bin' file is compared against memory starting at that address).
+     The file format may optionally be specified ('bin', 'ihex', or
+     'elf') This perform a comparison using a CRC checksum only
+
+15.5 Breakpoint and Watchpoint commands
+=======================================
+
+CPUs often make debug modules accessible through JTAG, with hardware
+support for a handful of code breakpoints and data watchpoints.  In
+addition, CPUs almost always support software breakpoints.
+
+ -- Command: bp [address len ['hw']]
+     With no parameters, lists all active breakpoints.  Else sets a
+     breakpoint on code execution starting at ADDRESS for LENGTH bytes.
+     This is a software breakpoint, unless 'hw' is specified in which
+     case it will be a hardware breakpoint.
+
+     (*Note arm9 vector_catch: arm9vectorcatch, or *note xscale
+     vector_catch: xscalevectorcatch, for similar mechanisms that do not
+     consume hardware breakpoints.)
+
+ -- Command: rbp 'all' | address
+     Remove the breakpoint at ADDRESS or all breakpoints.
+
+ -- Command: rwp 'all' | address
+     Remove data watchpoint on ADDRESS or all watchpoints.
+
+ -- Command: wp [address length [('r'|'w'|'a') [value [mask]]]]
+     With no parameters, lists all active watchpoints.  Else sets a data
+     watchpoint on data from ADDRESS for LENGTH bytes.  The watch point
+     is an "access" watchpoint unless the 'r' or 'w' parameter is
+     provided, defining it as respectively a read or write watchpoint.
+     If a VALUE is provided, that value is used when determining if the
+     watchpoint should trigger.  The value may be first be masked using
+     MASK to mark "don't care" fields.
+
+15.6 Real Time Transfer (RTT)
+=============================
+
+Real Time Transfer (RTT) is an interface specified by SEGGER based on
+basic memory reads and writes to transfer data bidirectionally between
+target and host.  The specification is independent of the target
+architecture.  Every target that supports so called "background memory
+access", which means that the target memory can be accessed by the
+debugger while the target is running, can be used.  This interface is
+especially of interest for targets without Serial Wire Output (SWO),
+such as ARM Cortex-M0, or where semihosting is not applicable because of
+real-time constraints.
+
+     Note: The current implementation supports only single target
+     devices.
+
+The data transfer between host and target device is organized through
+unidirectional up/down-channels for target-to-host and host-to-target
+communication, respectively.
+
+     Note: The current implementation does not respect channel buffer
+     flags.  They are used to determine what happens when writing to a
+     full buffer, for example.
+
+Channels are exposed via raw TCP/IP connections.  One or more RTT
+servers can be assigned to each channel to make them accessible to an
+unlimited number of TCP/IP connections.
+
+ -- Command: rtt setup address size [ID]
+     Configure RTT for the currently selected target.  Once RTT is
+     started, OpenOCD searches for a control block with the identifier
+     ID starting at the memory address ADDRESS within the next SIZE
+     bytes.  ID defaults to the string "SEGGER RTT"
+
+ -- Command: rtt start
+     Start RTT. If the control block location is not known, OpenOCD
+     starts searching for it.
+
+ -- Command: rtt stop
+     Stop RTT.
+
+ -- Command: rtt polling_interval [interval]
+     Display the polling interval.  If INTERVAL is provided, set the
+     polling interval.  The polling interval determines (in
+     milliseconds) how often the up-channels are checked for new data.
+
+ -- Command: rtt channels
+     Display a list of all channels and their properties.
+
+ -- Command: rtt channellist
+     Return a list of all channels and their properties as Tcl list.
+     The list can be manipulated easily from within scripts.
+
+ -- Command: rtt server start port channel [message]
+     Start a TCP server on PORT for the channel CHANNEL.  When MESSAGE
+     is not empty, it will be sent to a client when it connects.
+
+ -- Command: rtt server stop port
+     Stop the TCP sever with port PORT.
+
+The following example shows how to setup RTT using the SEGGER RTT
+implementation on the target device.
+
+     resume
+
+     rtt setup 0x20000000 2048
+     rtt start
+
+     rtt server start 9090 0
+
+In this example, OpenOCD searches the control block with the ID "SEGGER
+RTT" starting at 0x20000000 for 2048 bytes.  The RTT channel 0 is
+exposed through the TCP/IP port 9090.
+
+15.7 Misc Commands
+==================
+
+ -- Command: profile seconds filename [start end]
+     Profiling samples the CPU's program counter as quickly as possible,
+     which is useful for non-intrusive stochastic profiling.  Saves up
+     to 1000000 samples in 'filename' using "gmon.out" format.  Optional
+     'start' and 'end' parameters allow to limit the address range.
+
+ -- Command: version [git]
+     Returns a string identifying the version of this OpenOCD server.
+     With option 'git', it returns the git version obtained at compile
+     time through "git describe".
+
+ -- Command: virt2phys virtual_address
+     Requests the current target to map the specified VIRTUAL_ADDRESS to
+     its corresponding physical address, and displays the result.
+
+ -- Command: add_help_text 'command_name' 'help-string'
+     Add or replace help text on the given COMMAND_NAME.
+
+ -- Command: add_usage_text 'command_name' 'help-string'
+     Add or replace usage text on the given COMMAND_NAME.
+
+ -- Command: ms
+     Returns current time since the Epoch in ms (See:
+     ).  Useful to
+     compute delays in TCL.
+
+
+File: openocd.info,  Node: Architecture and Core Commands,  Next: JTAG Commands,  Prev: General Commands,  Up: Top
+
+16 Architecture and Core Commands
+*********************************
+
+Most CPUs have specialized JTAG operations to support debugging.
+OpenOCD packages most such operations in its standard command framework.
+Some of those operations don't fit well in that framework, so they are
+exposed here as architecture or implementation (core) specific commands.
+
+16.1 ARM Hardware Tracing
+=========================
+
+CPUs based on ARM cores may include standard tracing interfaces, based
+on an "Embedded Trace Module" (ETM) which sends voluminous address and
+data bus trace records to a "Trace Port".
+
+   * Development-oriented boards will sometimes provide a high speed
+     trace connector for collecting that data, when the particular CPU
+     supports such an interface.  (The standard connector is a 38-pin
+     Mictor, with both JTAG and trace port support.)  Those trace
+     connectors are supported by higher end JTAG adapters and some logic
+     analyzer modules; frequently those modules can buffer several
+     megabytes of trace data.  Configuring an ETM coupled to such an
+     external trace port belongs in the board-specific configuration
+     file.
+   * If the CPU doesn't provide an external interface, it probably has
+     an "Embedded Trace Buffer" (ETB) on the chip, which is a dedicated
+     SRAM. 4KBytes is one common ETB size.  Configuring an ETM coupled
+     only to an ETB belongs in the CPU-specific (target) configuration
+     file, since it works the same on all boards.
+
+ETM support in OpenOCD doesn't seem to be widely used yet.
+
+     Issues: ETM support may be buggy, and at least some 'etm config'
+     parameters should be detected by asking the ETM for them.
+
+     ETM trigger events could also implement a kind of complex hardware
+     breakpoint, much more powerful than the simple watchpoint hardware
+     exported by EmbeddedICE modules.  _Such breakpoints can be
+     triggered even when using the dummy trace port driver_.
+
+     It seems like a GDB hookup should be possible, as well as tracing
+     only during specific states (perhaps _handling IRQ 23_ or _calls
+     foo()_).
+
+     There should be GUI tools to manipulate saved trace data and help
+     analyse it in conjunction with the source code.  It's unclear how
+     much of a common interface is shared with the current XScale trace
+     support, or should be shared with eventual Nexus-style trace module
+     support.
+
+     At this writing (November 2009) only ARM7, ARM9, and ARM11 support
+     for ETM modules is available.  The code should be able to work with
+     some newer cores; but not all of them support this original style
+     of JTAG access.
+
+16.1.1 ETM Configuration
+------------------------
+
+ETM setup is coupled with the trace port driver configuration.
+
+ -- Config Command: etm config target width mode clocking driver
+     Declares the ETM associated with TARGET, and associates it with a
+     given trace port DRIVER.  *Note Trace Port Drivers:
+     traceportdrivers.
+
+     Several of the parameters must reflect the trace port capabilities,
+     which are a function of silicon capabilities (exposed later using
+     'etm info') and of what hardware is connected to that port (such as
+     an external pod, or ETB). The WIDTH must be either 4, 8, or 16,
+     except with ETMv3.0 and newer modules which may also support 1, 2,
+     24, 32, 48, and 64 bit widths.  (With those versions, 'etm info'
+     also shows whether the selected port width and mode are supported.)
+
+     The MODE must be 'normal', 'multiplexed', or 'demultiplexed'.  The
+     CLOCKING must be 'half' or 'full'.
+
+          Warning: With ETMv3.0 and newer, the bits set with the MODE
+          and CLOCKING parameters both control the mode.  This modified
+          mode does not map to the values supported by previous ETM
+          modules, so this syntax is subject to change.
+
+          Note: You can see the ETM registers using the 'reg' command.
+          Not all possible registers are present in every ETM. Most of
+          the registers are write-only, and are used to configure what
+          CPU activities are traced.
+
+ -- Command: etm info
+     Displays information about the current target's ETM. This includes
+     resource counts from the 'ETM_CONFIG' register, as well as silicon
+     capabilities (except on rather old modules).  from the
+     'ETM_SYS_CONFIG' register.
+
+ -- Command: etm status
+     Displays status of the current target's ETM and trace port driver:
+     is the ETM idle, or is it collecting data?  Did trace data
+     overflow?  Was it triggered?
+
+ -- Command: etm tracemode [type context_id_bits cycle_accurate
+          branch_output]
+     Displays what data that ETM will collect.  If arguments are
+     provided, first configures that data.  When the configuration
+     changes, tracing is stopped and any buffered trace data is
+     invalidated.
+
+        * TYPE ...  describing how data accesses are traced, when they
+          pass any ViewData filtering that was set up.  The value is one
+          of 'none' (save nothing), 'data' (save data), 'address' (save
+          addresses), 'all' (save data and addresses)
+        * CONTEXT_ID_BITS ...  0, 8, 16, or 32
+        * CYCLE_ACCURATE ...  'enable' or 'disable' cycle-accurate
+          instruction tracing.  Before ETMv3, enabling this causes much
+          extra data to be recorded.
+        * BRANCH_OUTPUT ...  'enable' or 'disable'.  Disable this unless
+          you need to try reconstructing the instruction trace stream
+          without an image of the code.
+
+ -- Command: etm trigger_debug ('enable'|'disable')
+     Displays whether ETM triggering debug entry (like a breakpoint) is
+     enabled or disabled, after optionally modifying that configuration.
+     The default behaviour is 'disable'.  Any change takes effect after
+     the next 'etm start'.
+
+     By using script commands to configure ETM registers, you can make
+     the processor enter debug state automatically when certain
+     conditions, more complex than supported by the breakpoint hardware,
+     happen.
+
+16.1.2 ETM Trace Operation
+--------------------------
+
+After setting up the ETM, you can use it to collect data.  That data can
+be exported to files for later analysis.  It can also be parsed with
+OpenOCD, for basic sanity checking.
+
+To configure what is being traced, you will need to write various trace
+registers using 'reg ETM_*' commands.  For the definitions of these
+registers, read ARM publication _IHI 0014, "Embedded Trace Macrocell,
+Architecture Specification"_.  Be aware that most of the relevant
+registers are write-only, and that ETM resources are limited.  There are
+only a handful of address comparators, data comparators, counters, and
+so on.
+
+Examples of scenarios you might arrange to trace include:
+
+   * Code flow within a function, _excluding_ subroutines it calls.  Use
+     address range comparators to enable tracing for instruction access
+     within that function's body.
+   * Code flow within a function, _including_ subroutines it calls.  Use
+     the sequencer and address comparators to activate tracing on an
+     "entered function" state, then deactivate it by exiting that state
+     when the function's exit code is invoked.
+   * Code flow starting at the fifth invocation of a function, combining
+     one of the above models with a counter.
+   * CPU data accesses to the registers for a particular device, using
+     address range comparators and the ViewData logic.
+   * Such data accesses only during IRQ handling, combining the above
+     model with sequencer triggers which on entry and exit to the IRQ
+     handler.
+   * _...  more_
+
+At this writing, September 2009, there are no Tcl utility procedures to
+help set up any common tracing scenarios.
+
+ -- Command: etm analyze
+     Reads trace data into memory, if it wasn't already present.
+     Decodes and prints the data that was collected.
+
+ -- Command: etm dump filename
+     Stores the captured trace data in 'filename'.
+
+ -- Command: etm image filename [base_address] [type]
+     Opens an image file.
+
+ -- Command: etm load filename
+     Loads captured trace data from 'filename'.
+
+ -- Command: etm start
+     Starts trace data collection.
+
+ -- Command: etm stop
+     Stops trace data collection.
+
+16.1.3 Trace Port Drivers
+-------------------------
+
+To use an ETM trace port it must be associated with a driver.
+
+ -- Trace Port Driver: dummy
+     Use the 'dummy' driver if you are configuring an ETM that's not
+     connected to anything (on-chip ETB or off-chip trace connector).
+     _This driver lets OpenOCD talk to the ETM, but it does not expose
+     any trace data collection._
+      -- Config Command: etm_dummy config target
+          Associates the ETM for TARGET with a dummy driver.
+
+ -- Trace Port Driver: etb
+     Use the 'etb' driver if you are configuring an ETM to use on-chip
+     ETB memory.
+      -- Config Command: etb config target etb_tap
+          Associates the ETM for TARGET with the ETB at ETB_TAP.  You
+          can see the ETB registers using the 'reg' command.
+      -- Command: etb trigger_percent [percent]
+          This displays, or optionally changes, ETB behavior after the
+          ETM's configured _trigger_ event fires.  It controls how much
+          more trace data is saved after the (single) trace trigger
+          becomes active.
+
+             * The default corresponds to _trace around_ usage,
+               recording 50 percent data before the event and the rest
+               afterwards.
+             * The minimum value of PERCENT is 2 percent, recording
+               almost exclusively data before the trigger.  Such extreme
+               _trace before_ usage can help figure out what caused that
+               event to happen.
+             * The maximum value of PERCENT is 100 percent, recording
+               data almost exclusively after the event.  This extreme
+               _trace after_ usage might help sort out how the event
+               caused trouble.
+
+16.2 ARM Cross-Trigger Interface
+================================
+
+The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
+that connects event sources like tracing components or CPU cores with
+each other through a common trigger matrix (CTM). For ARMv8
+architecture, a CTI is mandatory for core run control and each core has
+an individual CTI instance attached to it.  OpenOCD has limited support
+for CTI using the _cti_ group of commands.
+
+ -- Command: cti create cti_name '-dap' dap_name '-ap-num' apn
+          '-baseaddr' base_address
+     Creates a CTI instance CTI_NAME on the DAP instance DAP_NAME on
+     MEM-AP APN.  On ADIv5 DAP APN is the numeric index of the DAP AP
+     the CTI is connected to.  On ADIv6 DAP APN is the base address of
+     the DAP AP the CTI is connected to.  The BASE_ADDRESS must match
+     the base address of the CTI on the respective MEM-AP. All arguments
+     are mandatory.  This creates a new command '$cti_name' which is
+     used for various purposes including additional configuration.
+
+ -- Command: $cti_name enable 'on|off'
+     Enable ('on') or disable ('off') the CTI.
+
+ -- Command: $cti_name dump
+     Displays a register dump of the CTI.
+
+ -- Command: $cti_name write REG_NAME VALUE
+     Write VALUE to the CTI register with the symbolic name REG_NAME.
+
+ -- Command: $cti_name read REG_NAME
+     Print the value read from the CTI register with the symbolic name
+     REG_NAME.
+
+ -- Command: $cti_name ack EVENT
+     Acknowledge a CTI EVENT.
+
+ -- Command: $cti_name channel CHANNEL_NUMBER OPERATION
+     Perform a specific channel operation, the possible operations are:
+     gate, ungate, set, clear and pulse
+
+ -- Command: $cti_name testmode 'on|off'
+     Enable ('on') or disable ('off') the integration test mode of the
+     CTI.
+
+ -- Command: cti names
+     Prints a list of names of all CTI objects created.  This command is
+     mainly useful in TCL scripting.
+
+16.3 Generic ARM
+================
+
+These commands should be available on all ARM processors.  They are
+available in addition to other core-specific commands that may be
+available.
+
+ -- Command: arm core_state ['arm'|'thumb']
+     Displays the core_state, optionally changing it to process either
+     'arm' or 'thumb' instructions.  The target may later be resumed in
+     the currently set core_state.  (Processors may also support the
+     Jazelle state, but that is not currently supported in OpenOCD.)
+
+ -- Command: arm disassemble address [count ['thumb']]
+     Disassembles COUNT instructions starting at ADDRESS.  If COUNT is
+     not specified, a single instruction is disassembled.  If 'thumb' is
+     specified, or the low bit of the address is set, Thumb2 (mixed
+     16/32-bit) instructions are used; else ARM (32-bit) instructions
+     are used.  (Processors may also support the Jazelle state, but
+     those instructions are not currently understood by OpenOCD.)
+
+     Note that all Thumb instructions are Thumb2 instructions, so older
+     processors (without Thumb2 support) will still see correct
+     disassembly of Thumb code.  Also, ThumbEE opcodes are the same as
+     Thumb2, with a handful of exceptions.  ThumbEE disassembly
+     currently has no explicit support.
+
+ -- Command: arm mcr pX op1 CRn CRm op2 value
+     Write VALUE to a coprocessor PX register passing parameters CRN,
+     CRM, opcodes OPC1 and OPC2, and using the MCR instruction.
+     (Parameter sequence matches the ARM instruction, but omits an ARM
+     register.)
+
+ -- Command: arm mrc pX coproc op1 CRn CRm op2
+     Read a coprocessor PX register passing parameters CRN, CRM, opcodes
+     OPC1 and OPC2, and the MRC instruction.  Returns the result so it
+     can be manipulated by Jim scripts.  (Parameter sequence matches the
+     ARM instruction, but omits an ARM register.)
+
+ -- Command: arm reg
+     Display a table of all banked core registers, fetching the current
+     value from every core mode if necessary.
+
+ -- Command: arm semihosting ['enable'|'disable']
+     Display status of semihosting, after optionally changing that
+     status.
+
+     Semihosting allows for code executing on an ARM target to use the
+     I/O facilities on the host computer i.e.  the system where OpenOCD
+     is running.  The target application must be linked against a
+     library implementing the ARM semihosting convention that forwards
+     operation requests by using a special SVC instruction that is
+     trapped at the Supervisor Call vector by OpenOCD.
+
+ -- Command: arm semihosting_redirect ('disable' | 'tcp' 
+          ['debug'|'stdio'|'all'])
+     Redirect semihosting messages to a specified TCP port.
+
+     This command redirects debug (READC, WRITEC and WRITE0) and stdio
+     (READ, WRITE) semihosting operations to the specified TCP port.
+     The command allows to select which type of operations to redirect
+     (debug, stdio, all (default)).
+
+     Note: for stdio operations, only I/O from/to ':tt' file descriptors
+     are redirected.
+
+ -- Command: arm semihosting_cmdline ['enable'|'disable']
+     Set the command line to be passed to the debugger.
+
+          arm semihosting_cmdline argv0 argv1 argv2 ...
+
+     This option lets one set the command line arguments to be passed to
+     the program.  The first argument (argv0) is the program name in a
+     standard C environment (argv[0]).  Depending on the program (not
+     much programs look at argv[0]), argv0 is ignored and can be any
+     string.
+
+ -- Command: arm semihosting_fileio ['enable'|'disable']
+     Display status of semihosting fileio, after optionally changing
+     that status.
+
+     Enabling this option forwards semihosting I/O to GDB process using
+     the File-I/O remote protocol extension.  This is especially useful
+     for interacting with remote files or displaying console messages in
+     the debugger.
+
+ -- Command: arm semihosting_resexit ['enable'|'disable']
+     Enable resumable SEMIHOSTING_SYS_EXIT.
+
+     When SEMIHOSTING_SYS_EXIT is called outside a debug session, things
+     are simple, the openocd process calls exit() and passes the value
+     returned by the target.
+
+     When SEMIHOSTING_SYS_EXIT is called during a debug session, by
+     default execution returns to the debugger, leaving the debugger in
+     a HALT state, similar to the state entered when encountering a
+     break.
+
+     In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT return
+     normally, as any semihosting call, and do not break to the
+     debugger.  The standard allows this to happen, but the condition to
+     trigger it is a bit obscure ("by performing an RDI_Execute request
+     or equivalent").
+
+     To make the SEMIHOSTING_SYS_EXIT call return normally, enable this
+     option (default: disabled).
+
+ -- Command: arm semihosting_read_user_param
+     Read parameter of the semihosting call from the target.  Usable in
+     semihosting-user-cmd-0x10* event handlers, returning a string.
+
+     When the target makes semihosting call with operation number from
+     range 0x100- 0x107, an optional string parameter can be passed to
+     the server.  This parameter is valid during the run of the event
+     handlers and is accessible with this command.
+
+ -- Command: arm semihosting_basedir [dir]
+     Set the base directory for semihosting I/O, either an absolute path
+     or a path relative to OpenOCD working directory.  Use "."  for the
+     current directory.
+
+16.4 ARMv4 and ARMv5 Architecture
+=================================
+
+The ARMv4 and ARMv5 architectures are widely used in embedded systems,
+and introduced core parts of the instruction set in use today.  That
+includes the Thumb instruction set, introduced in the ARMv4T variant.
+
+16.4.1 ARM7 and ARM9 specific commands
+--------------------------------------
+
+These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI,
+ARM720T, ARM9TDMI, ARM920T or ARM926EJ-S. They are available in addition
+to the ARM commands, and any other core-specific commands that may be
+available.
+
+ -- Command: arm7_9 dbgrq ['enable'|'disable']
+     Displays the value of the flag controlling use of the EmbeddedIce
+     DBGRQ signal to force entry into debug mode, instead of
+     breakpoints.  If a boolean parameter is provided, first assigns
+     that flag.
+
+     This should be safe for all but ARM7TDMI-S cores (like NXP LPC).
+     This feature is enabled by default on most ARM9 cores, including
+     ARM9TDMI, ARM920T, and ARM926EJ-S.
+
+ -- Command: arm7_9 dcc_downloads ['enable'|'disable']
+     Displays the value of the flag controlling use of the debug
+     communications channel (DCC) to write larger (>128 byte) amounts of
+     memory.  If a boolean parameter is provided, first assigns that
+     flag.
+
+     DCC downloads offer a huge speed increase, but might be unsafe,
+     especially with targets running at very low speeds.  This command
+     was introduced with OpenOCD rev.  60, and requires a few bytes of
+     working area.
+
+ -- Command: arm7_9 fast_memory_access ['enable'|'disable']
+     Displays the value of the flag controlling use of memory writes and
+     reads that don't check completion of the operation.  If a boolean
+     parameter is provided, first assigns that flag.
+
+     This provides a huge speed increase, especially with USB JTAG
+     cables (FT2232), but might be unsafe if used with targets running
+     at very low speeds, like the 32kHz startup clock of an AT91RM9200.
+
+16.4.2 ARM9 specific commands
+-----------------------------
+
+ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
+integer processors.  Such cores include the ARM920T, ARM926EJ-S, and
+ARM966.
+
+ -- Command: arm9 vector_catch ['all'|'none'|list]
+     Vector Catch hardware provides a sort of dedicated breakpoint for
+     hardware events such as reset, interrupt, and abort.  You can use
+     this to conserve normal breakpoint resources, so long as you're not
+     concerned with code that branches directly to those hardware
+     vectors.
+
+     This always finishes by listing the current configuration.  If
+     parameters are provided, it first reconfigures the vector catch
+     hardware to intercept 'all' of the hardware vectors, 'none' of
+     them, or a list with one or more of the following: 'reset' 'undef'
+     'swi' 'pabt' 'dabt' 'irq' 'fiq'.
+
+16.4.3 ARM920T specific commands
+--------------------------------
+
+These commands are available to ARM920T based CPUs, which are
+implementations of the ARMv4T architecture built using the ARM9TDMI
+integer core.  They are available in addition to the ARM, ARM7/ARM9, and
+ARM9 commands.
+
+ -- Command: arm920t cache_info
+     Print information about the caches found.  This allows to see
+     whether your target is an ARM920T (2x16kByte cache) or ARM922T
+     (2x8kByte cache).
+
+ -- Command: arm920t cp15 regnum [value]
+     Display cp15 register REGNUM; else if a VALUE is provided, that
+     value is written to that register.  This uses "physical access" and
+     the register number is as shown in bits 38..33 of table 9-9 in the
+     ARM920T TRM. (Not all registers can be written.)
+
+ -- Command: arm920t read_cache filename
+     Dump the content of ICache and DCache to a file named 'filename'.
+
+ -- Command: arm920t read_mmu filename
+     Dump the content of the ITLB and DTLB to a file named 'filename'.
+
+16.4.4 ARM926ej-s specific commands
+-----------------------------------
+
+These commands are available to ARM926ej-s based CPUs, which are
+implementations of the ARMv5TEJ architecture based on the ARM9EJ-S
+integer core.  They are available in addition to the ARM, ARM7/ARM9, and
+ARM9 commands.
+
+The Feroceon cores also support these commands, although they are not
+built from ARM926ej-s designs.
+
+ -- Command: arm926ejs cache_info
+     Print information about the caches found.
+
+16.4.5 ARM966E specific commands
+--------------------------------
+
+These commands are available to ARM966 based CPUs, which are
+implementations of the ARMv5TE architecture.  They are available in
+addition to the ARM, ARM7/ARM9, and ARM9 commands.
+
+ -- Command: arm966e cp15 regnum [value]
+     Display cp15 register REGNUM; else if a VALUE is provided, that
+     value is written to that register.  The six bit REGNUM values are
+     bits 37..32 from table 7-2 of the ARM966E-S TRM. There is no
+     current control over bits 31..30 from that table, as required for
+     BIST support.
+
+16.4.6 XScale specific commands
+-------------------------------
+
+Some notes about the debug implementation on the XScale CPUs:
+
+The XScale CPU provides a special debug-only mini-instruction cache
+(mini-IC) in which exception vectors and target-resident debug handler
+code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
+must point vector 0 (the reset vector) to the entry of the debug
+handler.  However, this means that the complete first cacheline in the
+mini-IC is marked valid, which makes the CPU fetch all exception
+handlers from the mini-IC, ignoring the code in RAM.
+
+To address this situation, OpenOCD provides the 'xscale vector_table'
+command, which allows the user to explicitly write individual entries to
+either the high or low vector table stored in the mini-IC.
+
+It is recommended to place a pc-relative indirect branch in the vector
+table, and put the branch destination somewhere in memory.  Doing so
+makes sure the code in the vector table stays constant regardless of
+code layout in memory:
+     _vectors:
+             ldr     pc,[pc,#0x100-8]
+             ldr     pc,[pc,#0x100-8]
+             ldr     pc,[pc,#0x100-8]
+             ldr     pc,[pc,#0x100-8]
+             ldr     pc,[pc,#0x100-8]
+             ldr     pc,[pc,#0x100-8]
+             ldr     pc,[pc,#0x100-8]
+             ldr     pc,[pc,#0x100-8]
+             .org 0x100
+             .long real_reset_vector
+             .long real_ui_handler
+             .long real_swi_handler
+             .long real_pf_abort
+             .long real_data_abort
+             .long 0 /* unused */
+             .long real_irq_handler
+             .long real_fiq_handler
+
+Alternatively, you may choose to keep some or all of the mini-IC vector
+table entries synced with those written to memory by your system
+software.  The mini-IC can not be modified while the processor is
+executing, but for each vector table entry not previously defined using
+the 'xscale vector_table' command, OpenOCD will copy the value from
+memory to the mini-IC every time execution resumes from a halt.  This is
+done for both high and low vector tables (although the table not in use
+may not be mapped to valid memory, and in this case that copy operation
+will silently fail).  This means that you will need to briefly halt
+execution at some strategic point during system start-up; e.g., after
+the software has initialized the vector table, but before exceptions are
+enabled.  A breakpoint can be used to accomplish this once the
+appropriate location in the start-up code has been identified.  A
+watchpoint over the vector table region is helpful in finding the
+location if you're not sure.  Note that the same situation exists any
+time the vector table is modified by the system software.
+
+The debug handler must be placed somewhere in the address space using
+the 'xscale debug_handler' command.  The allowed locations for the debug
+handler are either (0x800 - 0x1fef800) or (0xfe000800 - 0xfffff800).
+The default value is 0xfe000800.
+
+XScale has resources to support two hardware breakpoints and two
+watchpoints.  However, the following restrictions on watchpoint
+functionality apply: (1) the value and mask arguments to the 'wp'
+command are not supported, (2) the watchpoint length must be a power of
+two and not less than four, and can not be greater than the watchpoint
+address, and (3) a watchpoint with a length greater than four consumes
+all the watchpoint hardware resources.  This means that at any one time,
+you can have enabled either two watchpoints with a length of four, or
+one watchpoint with a length greater than four.
+
+These commands are available to XScale based CPUs, which are
+implementations of the ARMv5TE architecture.
+
+ -- Command: xscale analyze_trace
+     Displays the contents of the trace buffer.
+
+ -- Command: xscale cache_clean_address address
+     Changes the address used when cleaning the data cache.
+
+ -- Command: xscale cache_info
+     Displays information about the CPU caches.
+
+ -- Command: xscale cp15 regnum [value]
+     Display cp15 register REGNUM; else if a VALUE is provided, that
+     value is written to that register.
+
+ -- Command: xscale debug_handler target address
+     Changes the address used for the specified target's debug handler.
+
+ -- Command: xscale dcache ['enable'|'disable']
+     Enables or disable the CPU's data cache.
+
+ -- Command: xscale dump_trace filename
+     Dumps the raw contents of the trace buffer to 'filename'.
+
+ -- Command: xscale icache ['enable'|'disable']
+     Enables or disable the CPU's instruction cache.
+
+ -- Command: xscale mmu ['enable'|'disable']
+     Enables or disable the CPU's memory management unit.
+
+ -- Command: xscale trace_buffer ['enable'|'disable' ['fill' [n] |
+          'wrap']]
+     Displays the trace buffer status, after optionally enabling or
+     disabling the trace buffer and modifying how it is emptied.
+
+ -- Command: xscale trace_image filename [offset [type]]
+     Opens a trace image from 'filename', optionally rebasing its
+     segment addresses by OFFSET.  The image TYPE may be one of 'bin'
+     (binary), 'ihex' (Intel hex), 'elf' (ELF file), 's19' (Motorola
+     s19), 'mem', or 'builder'.
+
+ -- Command: xscale vector_catch [mask]
+     Display a bitmask showing the hardware vectors to catch.  If the
+     optional parameter is provided, first set the bitmask to that
+     value.
+
+     The mask bits correspond with bit 16..23 in the DCSR:
+          0x01    Trap Reset
+          0x02    Trap Undefined Instructions
+          0x04    Trap Software Interrupt
+          0x08    Trap Prefetch Abort
+          0x10    Trap Data Abort
+          0x20    reserved
+          0x40    Trap IRQ
+          0x80    Trap FIQ
+
+ -- Command: xscale vector_table [('low'|'high') index value]
+
+     Set an entry in the mini-IC vector table.  There are two tables:
+     one for low vectors (at 0x00000000), and one for high vectors
+     (0xFFFF0000), each holding the 8 exception vectors.  INDEX can be
+     1-7, because vector 0 points to the debug handler entry and can not
+     be overwritten.  VALUE holds the 32-bit opcode that is placed in
+     the mini-IC.
+
+     Without arguments, the current settings are displayed.
+
+16.5 ARMv6 Architecture
+=======================
+
+16.5.1 ARM11 specific commands
+------------------------------
+
+ -- Command: arm11 memwrite burst ['enable'|'disable']
+     Displays the value of the memwrite burst-enable flag, which is
+     enabled by default.  If a boolean parameter is provided, first
+     assigns that flag.  Burst writes are only used for memory writes
+     larger than 1 word.  They improve performance by assuming that the
+     CPU has read each data word over JTAG and completed its write
+     before the next word arrives, instead of polling for a status flag
+     to verify that completion.  This is usually safe, because JTAG runs
+     much slower than the CPU.
+
+ -- Command: arm11 memwrite error_fatal ['enable'|'disable']
+     Displays the value of the memwrite error_fatal flag, which is
+     enabled by default.  If a boolean parameter is provided, first
+     assigns that flag.  When set, certain memory write errors cause
+     earlier transfer termination.
+
+ -- Command: arm11 step_irq_enable ['enable'|'disable']
+     Displays the value of the flag controlling whether IRQs are enabled
+     during single stepping; they are disabled by default.  If a boolean
+     parameter is provided, first assigns that.
+
+ -- Command: arm11 vcr [value]
+     Displays the value of the _Vector Catch Register (VCR)_,
+     coprocessor 14 register 7.  If VALUE is defined, first assigns
+     that.
+
+     Vector Catch hardware provides dedicated breakpoints for certain
+     hardware events.  The specific bit values are core-specific (as in
+     fact is using coprocessor 14 register 7 itself) but all current
+     ARM11 cores _except the ARM1176_ use the same six bits.
+
+16.6 ARMv7 and ARMv8 Architecture
+=================================
+
+16.6.1 ARMv7-A specific commands
+--------------------------------
+
+ -- Command: cortex_a cache_info
+     display information about target caches
+
+ -- Command: cortex_a dacrfixup ['on'|'off']
+     Work around issues with software breakpoints when the program text
+     is mapped read-only by the operating system.  This option sets the
+     CP15 DACR to "all-manager" to bypass MMU permission checks on
+     memory access.  Defaults to 'off'.
+
+ -- Command: cortex_a dbginit
+     Initialize core debug Enables debug by unlocking the Software Lock
+     and clearing sticky powerdown indications
+
+ -- Command: cortex_a smp [on|off]
+     Display/set the current SMP mode
+
+ -- Command: cortex_a smp_gdb [core_id]
+     Display/set the current core displayed in GDB
+
+ -- Command: cortex_a maskisr ['on'|'off']
+     Selects whether interrupts will be processed when single stepping
+
+ -- Command: cache_config l2x [base way]
+     configure l2x cache
+
+ -- Command: cortex_a mmu dump ['0'|'1'|'addr' address ['num_entries']]
+     Dump the MMU translation table from TTB0 or TTB1 register, or from
+     physical memory location ADDRESS.  When dumping the table from
+     ADDRESS, print at most NUM_ENTRIES page table entries.  NUM_ENTRIES
+     is optional, if omitted, the maximum possible (4096) entries are
+     printed.
+
+16.6.2 ARMv7-R specific commands
+--------------------------------
+
+ -- Command: cortex_r4 dbginit
+     Initialize core debug Enables debug by unlocking the Software Lock
+     and clearing sticky powerdown indications
+
+ -- Command: cortex_r4 maskisr ['on'|'off']
+     Selects whether interrupts will be processed when single stepping
+
+16.6.3 ARM CoreSight TPIU and SWO specific commands
+---------------------------------------------------
+
+ARM CoreSight provides several modules to generate debugging information
+internally (ITM, DWT and ETM). Their output is directed through TPIU or
+SWO modules to be captured externally either on an SWO pin (this
+configuration is called SWV) or on a synchronous parallel trace port.
+
+ARM CoreSight provides independent HW blocks named TPIU and SWO each
+with its own functionality.  Embedded in Cortex-M3 and M4, ARM provides
+an optional HW block that includes both TPIU and SWO functionalities and
+is again named TPIU, which causes quite some confusion.  The registers
+map of all the TPIU and SWO implementations allows using a single driver
+that detects at runtime the features available.
+
+The 'tpiu' is used for either TPIU or SWO. A convenient alias 'swo' is
+available to help distinguish, in scripts, the commands for SWO from the
+commands for TPIU.
+
+ -- Command: swo ...
+     Alias of 'tpiu ...'.  Can be used in scripts to distinguish the
+     commands for SWO from the commands for TPIU.
+
+ -- Command: tpiu create tpiu_name configparams...
+     Creates a TPIU or a SWO object.  The two commands are equivalent.
+     Add the object in a list and add new commands ('TPIU_NAME') which
+     are used for various purposes including additional configuration.
+
+        * TPIU_NAME - the name of the TPIU or SWO object.  This name is
+          also used to create the object's command, referred to here as
+          '$tpiu_name', and in other places where the TPIU or SWO needs
+          to be identified.
+        * CONFIGPARAMS - all parameters accepted by '$tpiu_name
+          configure' are permitted.
+
+          You _must_ set here the AP and MEM_AP base_address through
+          '-dap DAP_NAME', '-ap-num AP_NUMBER' and '-baseaddr
+          BASE_ADDRESS'.
+
+ -- Command: tpiu names
+     Lists all the TPIU or SWO objects created so far.  The two commands
+     are equivalent.
+
+ -- Command: tpiu init
+     Initialize all registered TPIU and SWO. The two commands are
+     equivalent.  These commands are used internally during
+     initialization.  They can be issued at any time after the
+     initialization, too.
+
+ -- Command: $tpiu_name cget queryparm
+     Each configuration parameter accepted by '$tpiu_name configure' can
+     be individually queried, to return its current value.  The
+     QUERYPARM is a parameter name accepted by that command, such as
+     '-dap'.
+
+ -- Command: $tpiu_name configure configparams...
+     The options accepted by this command may also be specified as
+     parameters to 'tpiu create'.  Their values can later be queried one
+     at a time by using the '$tpiu_name cget' command.
+
+        * '-dap' DAP_NAME - names the DAP used to access this TPIU.
+          *Note DAP declaration: dapdeclaration, on how to create and
+          manage DAP instances.
+
+        * '-ap-num' AP_NUMBER - sets DAP access port for TPIU. On ADIv5
+          DAP AP_NUMBER is the numeric index of the DAP AP the TPIU is
+          connected to.  On ADIv6 DAP AP_NUMBER is the base address of
+          the DAP AP the TPIU is connected to.
+
+        * '-baseaddr' BASE_ADDRESS - sets the TPIU BASE_ADDRESS where to
+          access the TPIU in the DAP AP memory space.
+
+        * '-protocol' ('sync'|'uart'|'manchester') - sets the protocol
+          used for trace data:
+             - 'sync' - synchronous parallel trace output mode, using
+               PORT_WIDTH data bits (default);
+             - 'uart' - use asynchronous SWO mode with NRZ (same as
+               regular UART 8N1) coding;
+             - 'manchester' - use asynchronous SWO mode with Manchester
+               coding.
+
+        * '-event' EVENT_NAME EVENT_BODY - assigns an event handler, a
+          TCL string which is evaluated when the event is triggered.
+          The events 'pre-enable', 'post-enable', 'pre-disable' and
+          'post-disable' are defined for TPIU/SWO. A typical use case
+          for the event 'pre-enable' is to enable the trace clock of the
+          TPIU.
+
+        * '-output' ('external'|':'PORT|FILENAME|'-') - specifies the
+          destination of the trace data:
+             - 'external' - configure TPIU/SWO to let user capture trace
+               output externally, either with an additional UART or with
+               a logic analyzer (default);
+             - '-' - configure TPIU/SWO and debug adapter to gather
+               trace data and forward it to 'tcl trace' command;
+             - ':'PORT - configure TPIU/SWO and debug adapter to gather
+               trace data, open a TCP server at port PORT and send the
+               trace data to each connected client;
+             - FILENAME - configure TPIU/SWO and debug adapter to gather
+               trace data and append it to FILENAME, which can be either
+               a regular file or a named pipe.
+
+        * '-traceclk' TRACECLKIN_FREQ - mandatory parameter.  Specifies
+          the frequency in Hz of the trace clock.  For the TPIU embedded
+          in Cortex-M3 or M4, this is usually the same frequency as
+          HCLK. For protocol 'sync' this is twice the frequency of the
+          pin data rate.
+
+        * '-pin-freq' TRACE_FREQ - specifies the expected data rate in
+          Hz of the SWO pin.  Parameter used only on protocols 'uart'
+          and 'manchester'.  Can be omitted to let the adapter driver
+          select the maximum supported rate automatically.
+
+        * '-port-width' PORT_WIDTH - sets to PORT_WIDTH the width of the
+          synchronous parallel port used for trace output.  Parameter
+          used only on protocol 'sync'.  If not specified, default value
+          is 1.
+
+        * '-formatter' ('0'|'1') - specifies if the formatter should be
+          enabled.  Parameter used only on protocol 'sync'.  If not
+          specified, default value is 0.
+
+ -- Command: $tpiu_name enable
+     Uses the parameters specified by the previous '$tpiu_name
+     configure' to configure and enable the TPIU or the SWO. If
+     required, the adapter is also configured and enabled to receive the
+     trace data.  This command can be used before 'init', but it will
+     take effect only after the 'init'.
+
+ -- Command: $tpiu_name disable
+     Disable the TPIU or the SWO, terminating the receiving of the trace
+     data.
+
+Example usage:
+  1. STM32L152 board is programmed with an application that configures
+     PLL to provide core clock with 24MHz frequency; to use ITM output
+     it's enough to:
+          #include 
+              ...
+              	ITM_STIM8(0) = c;
+              ...
+     (the most obvious way is to use the first stimulus port for printf,
+     for that this ITM_STIM8 assignment can be used inside _write(); to
+     make it blocking to avoid data loss, add 'while (!(ITM_STIM8(0) &
+     ITM_STIM_FIFOREADY));');
+  2. An FT2232H UART is connected to the SWO pin of the board;
+  3. Commands to configure UART for 12MHz baud rate:
+          $ setserial /dev/ttyUSB1 spd_cust divisor 5
+          $ stty -F /dev/ttyUSB1 38400
+     (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
+     baud with our custom divisor to get 12MHz)
+  4. 'itmdump -f /dev/ttyUSB1 -d1'
+  5. OpenOCD invocation line:
+          openocd -f interface/stlink.cfg \
+          -c "transport select dapdirect_swd" \
+          -f target/stm32l1.cfg \
+          -c "stm32l1.tpiu configure -protocol uart" \
+          -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \
+          -c "stm32l1.tpiu enable"
+
+16.6.4 ARMv7-M specific commands
+--------------------------------
+
+ -- Command: itm port PORT ('0'|'1'|'on'|'off')
+     Enable or disable trace output for ITM stimulus PORT (counting from
+     0).  Port 0 is enabled on target creation automatically.
+
+ -- Command: itm ports ('0'|'1'|'on'|'off')
+     Enable or disable trace output for all ITM stimulus ports.
+
+16.6.5 Cortex-M specific commands
+---------------------------------
+
+ -- Command: cortex_m maskisr ('auto'|'on'|'off'|'steponly')
+     Control masking (disabling) interrupts during target step/resume.
+
+     The 'auto' option handles interrupts during stepping in a way that
+     they get served but don't disturb the program flow.  The step
+     command first allows pending interrupt handlers to execute, then
+     disables interrupts and steps over the next instruction where the
+     core was halted.  After the step interrupts are enabled again.  If
+     the interrupt handlers don't complete within 500ms, the step
+     command leaves with the core running.
+
+     The 'steponly' option disables interrupts during single-stepping
+     but enables them during normal execution.  This can be used as a
+     partial workaround for 702596 erratum in Cortex-M7 r0p1.  See
+     "Cortex-M7 (AT610) and Cortex-M7 with FPU (AT611) Software
+     Developer Errata Notice" from ARM for further details.
+
+     Note that a free hardware (FPB) breakpoint is required for the
+     'auto' option.  If no breakpoint is available at the time of the
+     step, then the step is taken with interrupts enabled, i.e.  the
+     same way the 'off' option does.
+
+     Default is 'auto'.
+
+ -- Command: cortex_m vector_catch ['all'|'none'|list]
+     Vector Catch hardware provides dedicated breakpoints for certain
+     hardware events.
+
+     Parameters request interception of 'all' of these hardware event
+     vectors, 'none' of them, or one or more of the following:
+     'hard_err' for a HardFault exception; 'mm_err' for a MemManage
+     exception; 'bus_err' for a BusFault exception; 'irq_err',
+     'state_err', 'chk_err', or 'nocp_err' for various UsageFault
+     exceptions; or 'reset'.  If NVIC setup code does not enable them,
+     MemManage, BusFault, and UsageFault exceptions are mapped to
+     HardFault.  UsageFault checks for divide-by-zero and unaligned
+     access must also be explicitly enabled.
+
+     This finishes by listing the current vector catch configuration.
+
+ -- Command: cortex_m reset_config ('sysresetreq'|'vectreset')
+     Control reset handling if hardware srst is not fitted *Note
+     reset_config: reset_config.
+
+        - 'sysresetreq' use AIRCR SYSRESETREQ to reset system.
+        - 'vectreset' use AIRCR VECTRESET to reset system (default).
+
+     Using 'vectreset' is a safe option for Cortex-M3, M4 and M7 cores.
+     This however has the disadvantage of only resetting the core, all
+     peripherals are unaffected.  A solution would be to use a
+     'reset-init' event handler to manually reset the peripherals.
+     *Note Target Events: targetevents.
+
+     Cortex-M0, M0+ and M1 do not support 'vectreset', use 'sysresetreq'
+     instead.
+
+16.6.6 ARMv8-A specific commands
+--------------------------------
+
+ -- Command: aarch64 cache_info
+     Display information about target caches
+
+ -- Command: aarch64 dbginit
+     This command enables debugging by clearing the OS Lock and sticky
+     power-down and reset indications.  It also establishes the
+     expected, basic cross-trigger configuration the aarch64 target code
+     relies on.  In a configuration file, the command would typically be
+     called from a 'reset-end' or 'reset-deassert-post' handler, to
+     re-enable debugging after a system reset.  However, normally it is
+     not necessary to use the command at all.
+
+ -- Command: aarch64 disassemble address [count]
+     Disassembles COUNT instructions starting at ADDRESS.  If COUNT is
+     not specified, a single instruction is disassembled.
+
+ -- Command: aarch64 smp [on|off]
+     Display, enable or disable SMP handling mode.  The state of SMP
+     handling influences the way targets in an SMP group are handled by
+     the run control.  With SMP handling enabled, issuing halt or resume
+     to one core will trigger halting or resuming of all cores in the
+     group.  The command 'target smp' defines which targets are in the
+     SMP group.  With SMP handling disabled, all targets need to be
+     treated individually.
+
+ -- Command: aarch64 maskisr ['on'|'off']
+     Selects whether interrupts will be processed when single stepping.
+     The default configuration is 'on'.
+
+ -- Command: $target_name catch_exc
+          ['off'|'sec_el1'|'sec_el3'|'nsec_el1'|'nsec_el2']+
+     Cause '$target_name' to halt when an exception is taken.  Any
+     combination of Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is
+     valid.  The target '$target_name' will halt before taking the
+     exception.  In order to resume the target, the exception catch must
+     be disabled again with '$target_name catch_exc off'.  Issuing the
+     command without options prints the current configuration.
+
+ -- Command: $target_name pauth ['off'|'on']
+     Enable or disable pointer authentication features.  When pointer
+     authentication is used on ARM cores, GDB asks GDB servers for an
+     8-bytes mask to remove signature bits added by pointer
+     authentication.  If this feature is enabled, OpenOCD provides GDB
+     with an 8-bytes mask.  Pointer authentication feature is broken
+     until gdb 12.1, going to be fixed.  Consider using a newer version
+     of gdb if you want to enable pauth feature.  The default
+     configuration is 'off'.
+
+16.7 EnSilica eSi-RISC Architecture
+===================================
+
+eSi-RISC is a highly configurable microprocessor architecture for
+embedded systems provided by EnSilica.  (See:
+.)
+
+16.7.1 eSi-RISC Configuration
+-----------------------------
+
+ -- Command: esirisc cache_arch ('harvard'|'von_neumann')
+     Configure the caching architecture.  Targets with the
+     'UNIFIED_ADDRESS_SPACE' option disabled employ a Harvard
+     architecture.  By default, 'von_neumann' is assumed.
+
+ -- Command: esirisc hwdc ('all'|'none'|mask ...)
+     Configure hardware debug control.  The HWDC register controls which
+     exceptions return control back to the debugger.  Possible masks are
+     'all', 'none', 'reset', 'interrupt', 'syscall', 'error', and
+     'debug'.  By default, 'reset', 'error', and 'debug' are enabled.
+
+16.7.2 eSi-RISC Operation
+-------------------------
+
+ -- Command: esirisc flush_caches
+     Flush instruction and data caches.  This command requires that the
+     target is halted when the command is issued and configured with an
+     instruction or data cache.
+
+16.7.3 eSi-Trace Configuration
+------------------------------
+
+eSi-RISC targets may be configured with support for instruction tracing.
+Trace data may be written to an in-memory buffer or FIFO. If a FIFO is
+configured, DMA is typically employed to move trace data off-device
+using a high-speed peripheral (eg.  SPI). Collected trace data is
+encoded in one of three different formats.  At a minimum, 'esirisc trace
+buffer' or 'esirisc trace fifo' must be issued along with 'esirisc trace
+format' before trace data can be collected.
+
+OpenOCD provides rudimentary analysis of collected trace data.  If more
+detail is needed, collected trace data can be dumped to a file and
+processed by external tooling.
+
+     Issues: OpenOCD is unable to process trace data sent to a FIFO. A
+     potential workaround for this issue is to configure DMA to copy
+     trace data to an in-memory buffer, which can then be passed to the
+     'esirisc trace analyze' and 'esirisc trace dump' commands.
+
+     It is possible to corrupt trace data when using a FIFO if the
+     peripheral responsible for draining data from the FIFO is not fast
+     enough.  This can be managed by enabling flow control, however this
+     can impact timing-sensitive software operation on the CPU.
+
+ -- Command: esirisc trace buffer address size ['wrap']
+     Configure trace buffer using the provided address and size.  If the
+     'wrap' option is specified, trace collection will continue once the
+     end of the buffer is reached.  By default, wrap is disabled.
+
+ -- Command: esirisc trace fifo address
+     Configure trace FIFO using the provided address.
+
+ -- Command: esirisc trace flow_control ('enable'|'disable')
+     Enable or disable stalling the CPU to collect trace data.  By
+     default, flow control is disabled.
+
+ -- Command: esirisc trace format ('full'|'branch'|'icache') pc_bits
+     Configure trace format and number of PC bits to be captured.
+     'pc_bits' must be within 1 and 31 as the LSB is not collected.  If
+     external tooling is used to analyze collected trace data, these
+     values must match.
+
+     Supported trace formats:
+        * 'full' capture full trace data, allowing execution history and
+          timing to be determined.
+        * 'branch' capture taken branch instructions and branch target
+          addresses.
+        * 'icache' capture instruction cache misses.
+
+ -- Command: esirisc trace trigger start ('condition') [start_data
+          start_mask]
+     Configure trigger start condition using the provided start data and
+     mask.  A brief description of each condition is provided below; for
+     more detail on how these values are used, see the eSi-RISC
+     Architecture Manual.
+
+     Supported conditions:
+        * 'none' manual tracing (see 'esirisc trace start').
+        * 'pc' start tracing if the PC matches start data and mask.
+        * 'load' start tracing if the effective address of a load
+          instruction matches start data and mask.
+        * 'store' start tracing if the effective address of a store
+          instruction matches start data and mask.
+        * 'exception' start tracing if the EID of an exception matches
+          start data and mask.
+        * 'eret' start tracing when an 'ERET' instruction is executed.
+        * 'wait' start tracing when a 'WAIT' instruction is executed.
+        * 'stop' start tracing when a 'STOP' instruction is executed.
+        * 'high' start tracing when an external signal is a logical
+          high.
+        * 'low' start tracing when an external signal is a logical low.
+
+ -- Command: esirisc trace trigger stop ('condition') [stop_data
+          stop_mask]
+     Configure trigger stop condition using the provided stop data and
+     mask.  A brief description of each condition is provided below; for
+     more detail on how these values are used, see the eSi-RISC
+     Architecture Manual.
+
+     Supported conditions:
+        * 'none' manual tracing (see 'esirisc trace stop').
+        * 'pc' stop tracing if the PC matches stop data and mask.
+        * 'load' stop tracing if the effective address of a load
+          instruction matches stop data and mask.
+        * 'store' stop tracing if the effective address of a store
+          instruction matches stop data and mask.
+        * 'exception' stop tracing if the EID of an exception matches
+          stop data and mask.
+        * 'eret' stop tracing when an 'ERET' instruction is executed.
+        * 'wait' stop tracing when a 'WAIT' instruction is executed.
+        * 'stop' stop tracing when a 'STOP' instruction is executed.
+
+ -- Command: esirisc trace trigger delay ('trigger') [cycles]
+     Configure trigger start/stop delay in clock cycles.
+
+     Supported triggers:
+        * 'none' no delay to start or stop collection.
+        * 'start' delay 'cycles' after trigger to start collection.
+        * 'stop' delay 'cycles' after trigger to stop collection.
+        * 'both' delay 'cycles' after both triggers to start or stop
+          collection.
+
+16.7.4 eSi-Trace Operation
+--------------------------
+
+ -- Command: esirisc trace init
+     Initialize trace collection.  This command must be called any time
+     the configuration changes.  If a trace buffer has been configured,
+     the contents will be overwritten when trace collection starts.
+
+ -- Command: esirisc trace info
+     Display trace configuration.
+
+ -- Command: esirisc trace status
+     Display trace collection status.
+
+ -- Command: esirisc trace start
+     Start manual trace collection.
+
+ -- Command: esirisc trace stop
+     Stop manual trace collection.
+
+ -- Command: esirisc trace analyze [address size]
+     Analyze collected trace data.  This command may only be used if a
+     trace buffer has been configured.  If a trace FIFO has been
+     configured, trace data must be copied to an in-memory buffer
+     identified by the 'address' and 'size' options using DMA.
+
+ -- Command: esirisc trace dump [address size] 'filename'
+     Dump collected trace data to file.  This command may only be used
+     if a trace buffer has been configured.  If a trace FIFO has been
+     configured, trace data must be copied to an in-memory buffer
+     identified by the 'address' and 'size' options using DMA.
+
+16.8 Intel Architecture
+=======================
+
+Intel Quark X10xx is the first product in the Quark family of SoCs.  It
+is an IA-32 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx
+is codenamed Lakemont.  Lakemont version 1 (LMT1) is used in X10xx.  The
+CPU TAP (Lakemont TAP) is used for software debug and the CLTAP is used
+for SoC level operations.  Useful docs are here:
+https://communities.intel.com/community/makers/documentation
+   * Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for
+     doc num 330015)
+   * Intel Quark SoC X1000 Debug Operations User Guide (web search for
+     doc num 329866)
+   * Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
+
+16.8.1 x86 32-bit specific commands
+-----------------------------------
+
+The three main address spaces for x86 are memory, I/O and configuration
+space.  These commands allow a user to read and write to the 64Kbyte I/O
+address space.
+
+ -- Command: x86_32 idw address
+     Display the contents of a 32-bit I/O port from address range 0x0000
+     - 0xffff.
+
+ -- Command: x86_32 idh address
+     Display the contents of a 16-bit I/O port from address range 0x0000
+     - 0xffff.
+
+ -- Command: x86_32 idb address
+     Display the contents of a 8-bit I/O port from address range 0x0000
+     - 0xffff.
+
+ -- Command: x86_32 iww address
+     Write the contents of a 32-bit I/O port to address range 0x0000 -
+     0xffff.
+
+ -- Command: x86_32 iwh address
+     Write the contents of a 16-bit I/O port to address range 0x0000 -
+     0xffff.
+
+ -- Command: x86_32 iwb address
+     Write the contents of a 8-bit I/O port to address range 0x0000 -
+     0xffff.
+
+16.9 OpenRISC Architecture
+==========================
+
+The OpenRISC CPU is a soft core.  It is used in a programmable SoC which
+can be configured with any of the TAP / Debug Unit available.
+
+16.9.1 TAP and Debug Unit selection commands
+--------------------------------------------
+
+ -- Command: tap_select ('vjtag'|'mohor'|'xilinx_bscan')
+     Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and
+     Mohor TAP.
+ -- Command: du_select ('adv'|'mohor') [option]
+     Select between the Advanced Debug Interface and the classic one.
+
+     An option can be passed as a second argument to the debug unit.
+
+     When using the Advanced Debug Interface, option = 1 means the RTL
+     core is configured with ADBG_USE_HISPEED = 1.  This configuration
+     skips status checking between bytes while doing read or write
+     bursts.
+
+16.9.2 Registers commands
+-------------------------
+
+ -- Command: addreg [name] [address] [feature] [reg_group]
+     Add a new register in the cpu register list.  This register will be
+     included in the generated target descriptor file.
+
+     *[feature]* must be "org.gnu.gdb.or1k.group[0..10]".
+
+     *[reg_group]* can be anything.  The default register list defines
+     "system", "dmmu", "immu", "dcache", "icache", "mac", "debug",
+     "perf", "power", "pic" and "timer" groups.
+
+     _example:_
+          addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
+
+16.10 MIPS Architecture
+=======================
+
+MIPS (http://mips.com/) is a simple, streamlined, highly scalable RISC
+architecture.  The architecture is evolving over time, from MIPS I~V to
+MIPS release 1~6 iterations, the architecture is now able to handle
+various tasks with different ASEs, including SIMD(MSA), DSP, VZ, MT and
+more.  MIPS32 supports 32-bit programs while MIPS64 can support both
+32-bit and 64-bit programs.
+
+16.10.1 MIPS Terminology
+------------------------
+
+The term ASE means Application-Specific Extension, ASEs provide features
+that improve the efficiency and performance of certain workloads, such
+as digital signal processing(DSP), Virtualization(VZ),
+Multi-Threading(MT), SIMD(MSA) and more.
+
+MIPS Cores use Coprocessors(CPx) to configure their behaviour or to let
+software know the capabilities of current CPU, the main Coprocessor is
+CP0, containing 32 registers with a maximum select number of 7.
+
+16.10.2 MIPS FPU & Vector Registers
+-----------------------------------
+
+MIPS processors does not all comes with FPU co-processor, and when it
+does, the FPU appears as Coprocessor 1 whereas the Coprocessor 0 is for
+the main processor.
+
+Most of MIPS FPUs are 64 bits, IEEE 754 standard, and they provides both
+32-bit single precision and 64-bit double precision calculations.  Fixed
+point format calculations are also provided with both 32 and 64-bit
+modes.
+
+The MIPS SIMD Architecture(MSA) operates on 32 128-bit wide vector
+registers.  If both MSA and the scalar floating-point unit (FPU) are
+present, the 128-bit MSA vector registers extend and share the 64-bit
+FPU registers.  MSA and FPU can not be both present, unless the FPU has
+64-bit floating-point register.
+
+16.10.3 MIPS Configuration Commands
+-----------------------------------
+
+ -- Command: mips32 cpuinfo
+     Displays detailed information about current CPU core.  This
+     includes core type, vendor, instruction set, cache size, and other
+     relevant details.
+
+ -- Config Command: mips32 scan_delay [nanoseconds]
+     Display or set scan delay in nano seconds.  A value below 2_000_000
+     will set the scan delay into legacy mode.
+
+ -- Config Command: mips32 cp0 [[reg_name|regnum select] [value]]
+     Displays or sets coprocessor 0 register by register number and
+     select or their name.  This command shows all available cp0
+     register if no arguments are provided.
+
+     For common MIPS Coprocessor 0 registers, you can find the
+     definitions of them on MIPS Privileged Resource Architecture
+     Documents(MIPS Document MD00090).
+
+     For core specific cp0 registers, you can find the definitions of
+     them on Core Specific Software User's Manual(SUM), for example,
+     MIPS M5150 Software User Manual (MD00980).
+
+ -- Command: mips32 ejtag_reg
+     Reads EJTAG Registers for inspection.
+
+     EJTAG Register Specification could be found in MIPS Document
+     MD00047F, for core specific EJTAG Register definition, please check
+     Core Specific SUM manual.
+
+ -- Command: mips32 dsp [[register_name] [value]]
+     Displays all DSP registers' contents or get/set value by register
+     name.  Will display an error if current CPU does not support DSP.
+
+16.11 RISC-V Architecture
+=========================
+
+RISC-V (http://riscv.org/) is a free and open ISA. OpenOCD supports JTAG
+debug of RV32 and RV64 cores in heterogeneous multicore systems of up to
+2^20 harts.  OpenOCD primarily supports 0.13 of the RISC-V Debug
+Specification, but there is also support for legacy targets that
+implement version 0.11.
+
+16.11.1 RISC-V Terminology
+--------------------------
+
+A _hart_ is a hardware thread.  A hart may share resources (eg.  FPU)
+with another hart, or may be a separate core.  RISC-V treats those the
+same, and OpenOCD exposes each hart as a separate core.
+
+16.11.2 Vector Registers
+------------------------
+
+For harts that implement the vector extension, OpenOCD provides access
+to the relevant CSRs, as well as the vector registers (v0-v31).  The
+size of each vector register is dependent on the value of vlenb.  RISC-V
+allows each vector register to be divided into selected-width elements,
+and this division can be changed at run-time.  Because OpenOCD cannot
+update register definitions at run-time, it exposes each vector register
+to gdb as a union of fields of vectors so that users can easily access
+individual bytes, shorts, words, longs, and quads inside each vector
+register.  It is left to gdb or higher-level debuggers to present this
+data in a more intuitive format.
+
+In the XML register description, the vector registers (when vlenb=16)
+look as follows:
+
+     
+     
+     
+     
+     
+     
+     
+     
+     
+     
+     
+     
+     
+     
+     ...
+     
+     
+
+16.11.3 RISC-V Debug Configuration Commands
+-------------------------------------------
+
+ -- Command: riscv dump_sample_buf [base64]
+     Dump and clear the contents of the sample buffer.  Which samples
+     are collected is configured with 'riscv memory_sample'.  If the
+     optional base64 argument is passed, the raw buffer is dumped in
+     base64 format, so that external tools can gather the data
+     efficiently.
+
+ -- Config Command: riscv expose_csrs n[-m|=name] [...]
+     Configure which CSRs to expose in addition to the standard ones.
+     The CSRs to expose can be specified as individual register numbers
+     or register ranges (inclusive).  For the individually listed CSRs,
+     a human-readable name can optionally be set using the 'n=name'
+     syntax, which will get 'csr_' prepended to it.  If no name is
+     provided, the register will be named 'csr'.
+
+     By default OpenOCD attempts to expose only CSRs that are mentioned
+     in a spec, and then only if the corresponding extension appears to
+     be implemented.  This command can be used if OpenOCD gets this
+     wrong, or if the target implements custom CSRs.
+
+          # Expose a single RISC-V CSR number 128 under the name "csr128":
+          riscv expose_csrs 128
+
+          # Expose multiple RISC-V CSRs 128..132 under names "csr128" through "csr132":
+          riscv expose_csrs 128-132
+
+          # Expose a single RISC-V CSR number 1996 under custom name "csr_myregister":
+          riscv expose_csrs 1996=myregister
+
+ -- Config Command: riscv expose_custom n[-m|=name] [...]
+     The RISC-V Debug Specification allows targets to expose custom
+     registers through abstract commands.  (See Section 3.5.1.1 in that
+     document.)  This command configures individual registers or
+     register ranges (inclusive) that shall be exposed.  Number 0
+     indicates the first custom register, whose abstract command number
+     is 0xc000.  For individually listed registers, a human-readable
+     name can be optionally provided using the 'n=name' syntax, which
+     will get 'custom_' prepended to it.  If no name is provided, the
+     register will be named 'custom'.
+
+          # Expose one RISC-V custom register with number 0xc010 (0xc000 + 16)
+          # under the name "custom16":
+          $_TARGETNAME expose_custom 16
+
+          # Expose a range of RISC-V custom registers with numbers 0xc010 .. 0xc018
+          # (0xc000+16 .. 0xc000+24) under the names "custom16" through "custom24":
+          $_TARGETNAME expose_custom 16-24
+
+          # Expose one RISC-V custom register with number 0xc020 (0xc000 + 32) under
+          # user-defined name "custom_myregister":
+          $_TARGETNAME expose_custom 32=myregister
+
+ -- Config Command: riscv hide_csrs n[-m] [,n1[-m1]] [...]
+     The RISC-V Specification defines many CSRs, and we may want to
+     avoid showing each CSR to the user, as they may not be relevant to
+     the task at hand.  For example, we may choose not to show trigger
+     or PMU registers for simple debugging scenarios.  This command
+     allows to mark individual registers or register ranges (inclusive)
+     as "hidden".  Such hidden registers won't be displayed in GDB or
+     'reg' command output.
+
+
+          # Hide range of RISC-V CSRs
+          # CSR_TSELECT - 1952 and CSR_TDATA1 - 1953
+          $_TARGETNAME riscv hide_csrs 1952-1953
+
+
+ -- Command: riscv memory_sample bucket address|clear [size=4]
+     Configure OpenOCD to frequently read size bytes at the given
+     addresses.  Execute the command with no arguments to see the
+     current configuration.  Use clear to stop using a given bucket.
+
+     OpenOCD will allocate a 1MB sample buffer, and when it fills up no
+     more samples will be collected until it is emptied with 'riscv
+     dump_sample_buf'.
+
+ -- Command: riscv repeat_read count address [size=4]
+     Quickly read count words of the given size from address.  This can
+     be useful to read out a buffer that's memory-mapped to be accessed
+     through a single address, or to sample a changing value in a
+     memory-mapped device.
+
+ -- Command: riscv info
+     Displays some information OpenOCD detected about the target.
+     Output's format allows to use it directly with TCL's 'array set'
+     function.  In case obtaining an info point failed, the
+     corresponding value is displayed as "unavailable".
+
+ -- Command: riscv reset_delays [wait]
+     OpenOCD learns how many Run-Test/Idle cycles are required between
+     scans to avoid encountering the target being busy.  This command
+     resets those learned values after 'wait' scans.  It's only useful
+     for testing OpenOCD itself.
+
+ -- Command: riscv set_command_timeout_sec [seconds]
+     Set the wall-clock timeout (in seconds) for individual commands.
+     The default should work fine for all but the slowest targets (eg.
+     simulators).
+
+ -- Command: riscv set_mem_access method1 [method2] [method3]
+     Specify which RISC-V memory access method(s) shall be used, and in
+     which order of priority.  At least one method must be specified.
+
+     Available methods are:
+        * 'progbuf' - Use RISC-V Debug Program Buffer to access memory.
+        * 'sysbus' - Access memory via RISC-V Debug System Bus
+          interface.
+        * 'abstract' - Access memory via RISC-V Debug abstract commands.
+
+     By default, all memory access methods are enabled in the following
+     order: 'progbuf sysbus abstract'.
+
+     This command can be used to change the memory access methods if the
+     default behavior is not suitable for a particular target.
+
+ -- Command: riscv virt2phys_mode ['hw'|'sw'|'off']
+     Configure how OpenOCD translates virtual addresses to physical:
+        * 'sw' - OpenOCD translates virtual addresses explicitly by
+          traversing the page table entries (by performing physical
+          memory accesses to read the respective entries).  This is the
+          default mode.
+        * 'hw' - Virtual addresses are translated implicitly by
+          hardware.  (Virtual memory access will fail with an error if
+          the hardware doesn't support the necessary functionality.)
+        * 'off' - Virtual addresses are not translated (identity mapping
+          is assumed).
+     Returns current translation mode if called without arguments.
+
+ -- Command: riscv resume_order normal|reversed
+     Some software assumes all harts are executing nearly continuously.
+     Such software may be sensitive to the order that harts are resumed
+     in.  On harts that don't support hasel, this option allows the user
+     to choose the order the harts are resumed in.  If you are using
+     this option, it's probably masking a race condition problem in your
+     code.
+
+     Normal order is from lowest hart index to highest.  This is the
+     default behavior.  Reversed order is from highest hart index to
+     lowest.
+
+ -- Command: riscv set_ir ('idcode'|'dtmcs'|'dmi') [value]
+     Set the IR value for the specified JTAG register.  This is useful,
+     for example, when using the existing JTAG interface on a Xilinx
+     FPGA by way of BSCANE2 primitives that only permit a limited
+     selection of IR values.
+
+     When utilizing version 0.11 of the RISC-V Debug Specification,
+     'dtmcs' and 'dmi' set the IR values for the DTMCONTROL and DBUS
+     registers, respectively.
+
+ -- Command: riscv smp [on|off]
+     Display, enable or disable SMP handling mode.  This command is
+     needed only if user wants to temporary disable SMP handling for an
+     existing SMP group (see 'aarch64 smp' for additional information).
+     To define an SMP group the command 'target smp' should be used.
+
+ -- Command: riscv smp_gdb [core_id]
+     Display/set the current core displayed in GDB. This is needed only
+     if 'riscv smp' was used.
+
+ -- Command: riscv use_bscan_tunnel width [type]
+     Enable or disable use of a BSCAN tunnel to reach the Debug Module.
+     Supply the WIDTH of the DM transport TAP's instruction register to
+     enable.  The WIDTH should fit into 7 bits.  Supply a value of 0 to
+     disable.  Pass a second argument (optional) to indicate Bscan
+     Tunnel Type:
+       1. 0:(default) NESTED_TAP
+       2. 1: DATA_REGISTER
+
+     This BSCAN tunnel interface is specific to SiFive IP. Anybody may
+     implement it, but currently there is no good documentation on it.
+     In a nutshell, this feature scans USER4 into a Xilinx TAP to select
+     the tunnel device (assuming hardware is present and it is hooked up
+     to the Xilinx USER4 IR) and encapsulates a tunneled scan directive
+     into a DR scan into the Xilinx TAP. A tunneled DR scan consists of:
+       1. 1 bit that selects IR when 0, or DR when 1
+       2. 7 bits that encode the width of the desired tunneled scan
+       3. A width+1 stream of bits for the tunneled TDI. The plus one is
+          because there is a one-clock skew between TDI of Xilinx chain
+          and TDO from tunneled chain.
+       4. 3 bits of zero that the tunnel uses to go back to idle state.
+
+ -- Command: riscv set_bscan_tunnel_ir value
+     Allows the use_bscan_tunnel feature to target non Xilinx device by
+     specifying the JTAG TAP IR used to access the bscan tunnel.
+
+ -- Command: riscv set_maskisr ['off'|'steponly']
+     Selects whether interrupts will be disabled when single stepping.
+     The default configuration is 'off'.  This feature is only useful on
+     hardware that always steps into interrupts and doesn't support
+     dcsr.stepie=0.  Keep in mind, disabling the option does not
+     guarantee that single stepping will go into interrupt handlers.  To
+     make that happen, dcsr.stepie would have to be written to 1 as
+     well.
+
+ -- Command: riscv set_ebreakm [on|off]
+     Control dcsr.ebreakm.  When on (default), M-mode ebreak
+     instructions trap to OpenOCD. When off, they generate a breakpoint
+     exception handled internally.
+
+ -- Command: riscv set_ebreaks [on|off]
+     Control dcsr.ebreaks.  When on (default), S-mode ebreak
+     instructions trap to OpenOCD. When off, they generate a breakpoint
+     exception handled internally.
+
+ -- Command: riscv set_ebreaku [on|off]
+     Control dcsr.ebreaku.  When on (default), U-mode ebreak
+     instructions trap to OpenOCD. When off, they generate a breakpoint
+     exception handled internally.
+
+The commands below can be used to prevent OpenOCD from using certain
+RISC-V trigger features.  For example in cases when there are known
+issues in the target hardware.
+
+ -- Command: riscv set_enable_trigger_feature
+          [('eq'|'napot'|'ge_lt'|'all') ('wp'|'none')]
+     Control which RISC-V trigger features can be used by OpenOCD
+     placing watchpoints.  All trigger features are allowed by default.
+     Only new watchpoints, inserted after this command, are affected
+     (watchpoints that were already placed before are not changed).
+
+     The first argument selects one of the configurable RISC-V trigger
+     features:
+
+        - 'eq': Equality match trigger
+        - 'napot': NAPOT trigger
+        - 'ge_lt': Chained pair of 'greater-equal' and 'less-than'
+          triggers
+        - 'all': All trigger features which were described above
+
+     The second argument configures how OpenOCD should use the selected
+     trigger feature:
+
+        - 'wp': Enable this trigger feature for watchpoints - allow
+          OpenOCD to use it.  (Default.)
+        - 'none': Disable the use of this trigger feature.  OpenOCD will
+          not attempt to use it.
+
+     With no parameters, prints current trigger features configuration.
+
+16.11.4 RISC-V Authentication Commands
+--------------------------------------
+
+The following commands can be used to authenticate to a RISC-V system.
+Eg.  a trivial challenge-response protocol could be implemented as
+follows in a configuration file, immediately following 'init':
+     set challenge [riscv authdata_read]
+     riscv authdata_write [expr {$challenge + 1}]
+
+ -- Command: riscv authdata_read [index=0]
+     Return the 32-bit value read from authdata or authdata0 (index=0),
+     or authdata1 (index=1).
+
+ -- Command: riscv authdata_write [index=0] value
+     Write the 32-bit value to authdata or authdata0 (index=0), or
+     authdata1 (index=1).
+
+16.11.5 RISC-V DMI Commands
+---------------------------
+
+The following commands allow for direct low-level access to the
+registers of the Debug Module (DM). They can be useful to access custom
+features in the DM.
+
+ -- Command: riscv dm_read reg_address
+     Perform a 32-bit read from the register indicated by reg_address
+     from the DM of the current target.
+
+ -- Command: riscv dm_write reg_address value
+     Write the 32-bit value to the register indicated by reg_address
+     from the DM of the current target.
+
+The following commands allow for direct low-level access to the Debug
+Module Interface (DMI). They can be useful to access any device that
+resides on the DMI.
+
+ -- Command: riscv dmi_read address
+     Perform a 32-bit read from the given DMI address, returning the
+     value.
+
+ -- Command: riscv dmi_write address value
+     Perform a 32-bit write to the given DMI address.
+
+16.11.6 RISC-V Trigger Commands
+-------------------------------
+
+The RISC-V Debug Specification defines several optional trigger types
+that don't map cleanly onto OpenOCD's notion of hardware breakpoints.
+For the types that the target supports, these commands let you set those
+triggers directly.  (It's also possible to do so by writing the
+appropriate CSRs.)
+
+ -- Command: riscv etrigger set ['m'] ['s'] ['u'] ['vs'] ['vu']
+          exception_codes
+     Set an exception trigger (type 5) on the current target, which
+     halts the target when it fires.  'm', 's', 'u', 'vs', and 'vu'
+     control which execution modes the trigger fires in.
+     EXCEPTION_CODES is a bit field, where each bit corresponds to an
+     exception code in mcause (defined in the RISC-V Privileged Spec).
+     The etrigger will fire on the exceptions whose bits are set in
+     EXCEPTION_CODES.
+
+     For details on this trigger type, see the RISC-V Debug
+     Specification.
+
+ -- Command: riscv etrigger clear
+     Clear the type 5 trigger that was set using 'riscv etrigger set'.
+
+ -- Command: riscv icount set ['m'] ['s'] ['u'] ['vs'] ['vu']
+          ['pending'] count
+     Set an instruction count trigger (type 3) on the current target,
+     which halts the target when it fires.  'm', 's', 'u', 'vs', and
+     'vu' control which execution modes the trigger fires in.  If
+     ['pending'] is passed then the pending bit is set, which is
+     unlikely to be useful unless you're debugging the hardware
+     implementation of this trigger.  COUNT sets the number of
+     instructions to execute before the trigger is taken.
+
+     For details on this trigger type, see the RISC-V Debug
+     Specification.
+
+ -- Command: riscv icount clear
+     Clear the type 3 trigger that was set using 'riscv icount set'.
+
+ -- Command: riscv itrigger set ['m'] ['s'] ['u'] ['vs'] ['vu'] ['nmi']
+          mie_bits
+     Set an interrupt trigger (type 4) on the current target, which
+     halts the target when it fires.  'm', 's', 'u', 'vs', and 'vu'
+     control which execution modes the trigger fires in.  If ['nmi'] is
+     passed then the trigger will fire on non-maskable interrupts in
+     those modes.  MIE_BITS controls which interrupts the trigger fires
+     on, using the same bit assignments as in the mie CSR (defined in
+     the RISC-V Privileged Spec).
+
+     For details on this trigger type, see the RISC-V Debug
+     Specification.
+
+ -- Command: riscv reserve_trigger [index 'on|off']
+     Manages the set of reserved triggers.  Reserving a trigger results
+     in OpenOCD not using it internally (e.g.  skipping it when setting
+     a watchpoint or a hardware breakpoint), so that the user or the
+     application has unfettered control over the trigger.  By default
+     there are no reserved triggers.
+
+       1. INDEX specifies the index of a trigger to reserve or free up.
+       2. The second argument specifies whether the trigger should be
+          reserved (ON) or a prior reservation cancelled (OFF).
+       3. If called without parameters, returns indices of reserved
+          triggers.
+
+ -- Command: riscv itrigger clear
+     Clear the type 4 trigger that was set using 'riscv itrigger set'.
+
+16.11.7 RISC-V Program Buffer Commands
+--------------------------------------
+
+Program Buffer is an optional feature of RISC-V targets - it is a
+mechanism that debuggers can use to execute sequences of arbitrary
+instructions (small programs) on the target.  For details on the Program
+Buffer, please refer to the RISC-V Debug Specification.
+
+ -- Command: riscv exec_progbuf inst1 [inst2 [... inst16]]
+     Execute the given sequence of instructions on the target using the
+     Program Buffer.  The command can only be used on halted targets.
+
+     The instructions INST1 ..  INST16 shall be specified in their
+     binary form (as 32-bit integers).  In case a pair of compressed
+     (16-bit) instructions is used, the first instruction should be
+     placed to the lower 16-bits of the 32-bit value.  The terminating
+     EBREAK instruction needs not be specified - it is added
+     automatically if needed.
+
+Examples:
+
+     # Execute 32-bit instructions "fence rw,rw" (0x0330000f)
+     # and "fence.i" (0x0000100f) using the Program Buffer,
+     # in this order:
+
+     riscv exec_progbuf 0x0330000f 0x0000100f
+
+     # Execute 16-bit instructions "c.addi s0,s0,1" (0x0405)
+     # and "c.add s1,s1,s0" (0x94a2) using the Program Buffer,
+     # in this order:
+
+     riscv exec_progbuf 0x94a20405
+
+ -- Command: riscv autofence [on|off]
+     When on (default), OpenOCD will automatically execute RISC-V fence
+     instructions (FENCE.I and FENCE RW, RW) in these cases:
+        * before step or resume,
+        * before memory read via the Program Buffer,
+        * after memory write via the Program Buffer.
+     When off, users need to take care of memory coherency themselves,
+     for example using the RISCV EXEC_PROGBUF command to execute fences
+     or CMO instructions (RISC-V Cache Management Operations).
+
+16.12 ARC Architecture
+======================
+
+Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
+designers can optimize for a wide range of uses, from deeply embedded to
+high-performance host applications in a variety of market segments.  See
+more at:
+.
+OpenOCD currently supports ARC EM processors.  There is a set
+ARC-specific OpenOCD commands that allow low-level access to the core
+and provide necessary support for ARC extensibility and configurability
+capabilities.  ARC processors has much more configuration capabilities
+than most of the other processors and in addition there is an extension
+interface that allows SoC designers to add custom registers and
+instructions.  For the OpenOCD that mostly means that set of core and
+AUX registers in target will vary and is not fixed for a particular
+processor model.  To enable extensibility several TCL commands are
+provided that allow to describe those optional registers in OpenOCD
+configuration files.  Moreover those commands allow for a dynamic target
+features discovery.
+
+16.12.1 General ARC commands
+----------------------------
+
+ -- Config Command: arc add-reg configparams
+
+     Add a new register to processor target.  By default newly created
+     register is marked as not existing.  CONFIGPARAMS must have
+     following required arguments:
+
+        * '-name' name
+          Name of a register.
+
+        * '-num' number
+          Architectural register number: core register number or AUX
+          register number.
+
+        * '-feature' XML_feature
+          Name of GDB XML target description feature.
+
+     CONFIGPARAMS may have following optional arguments:
+
+        * '-gdbnum' number
+          GDB register number.  It is recommended to not assign GDB
+          register number manually, because there would be a risk that
+          two register will have same number.  When register GDB number
+          is not set with this option, then register will get a previous
+          register number + 1.  This option is required only for those
+          registers that must be at particular address expected by GDB.
+
+        * '-core'
+          This option specifies that register is a core registers.  If
+          not - this is an AUX register.  AUX registers and core
+          registers reside in different address spaces.
+
+        * '-bcr'
+          This options specifies that register is a BCR register.  BCR
+          means Build Configuration Registers - this is a special type
+          of AUX registers that are read only and non-volatile, that is
+          - they never change their value.  Therefore OpenOCD never
+          invalidates values of those registers in internal caches.
+          Because BCR is a type of AUX registers, this option cannot be
+          used with '-core'.
+
+        * '-type' type_name
+          Name of type of this register.  This can be either one of the
+          basic GDB types, or a custom types described with 'arc
+          add-reg-type-[flags|struct]'.
+
+        * '-g'
+          If specified then this is a "general" register.  General
+          registers are always read by OpenOCD on context save (when
+          core has just been halted) and is always transferred to GDB
+          client in a response to g-packet.  Contrary to this,
+          non-general registers are read and sent to GDB client
+          on-demand.  In general it is not recommended to apply this
+          option to custom registers.
+
+ -- Config Command: arc add-reg-type-flags -name name flags...
+     Adds new register type of "flags" class.  "Flags" types can contain
+     only one-bit fields.  Each flag definition looks like '-flag name
+     bit-position'.
+
+ -- Config Command: arc add-reg-type-struct -name name structs...
+     Adds new register type of "struct" class.  "Struct" types can
+     contain either bit-fields or fields of other types, however at the
+     moment only bit fields are supported.  Structure bit field
+     definition looks like '-bitfield name startbit endbit'.
+
+ -- Command: arc get-reg-field reg-name field-name
+     Returns value of bit-field in a register.  Register must be
+     "struct" register type, *Note add-reg-type-struct::.  command
+     definition.
+
+ -- Command: arc set-reg-exists reg-names...
+     Specify that some register exists.  Any amount of names can be
+     passed as an argument for a single command invocation.
+
+16.12.2 ARC JTAG commands
+-------------------------
+
+ -- Command: arc jtag set-aux-reg regnum value
+     This command writes value to AUX register via its number.  This
+     command access register in target directly via JTAG, bypassing any
+     OpenOCD internal caches, therefore it is unsafe to use if that
+     register can be operated by other means.
+
+ -- Command: arc jtag set-core-reg regnum value
+     This command is similar to 'arc jtag set-aux-reg' but is for core
+     registers.
+
+ -- Command: arc jtag get-aux-reg regnum
+     This command returns the value storded in AUX register via its
+     number.  This commands access register in target directly via JTAG,
+     bypassing any OpenOCD internal caches, therefore it is unsafe to
+     use if that register can be operated by other means.
+
+ -- Command: arc jtag get-core-reg regnum
+     This command is similar to 'arc jtag get-aux-reg' but is for core
+     registers.
+
+16.13 STM8 Architecture
+=======================
+
+STM8 (http://st.com/stm8/) is a 8-bit microcontroller platform from
+STMicroelectronics, based on a proprietary 8-bit core architecture.
+
+OpenOCD supports debugging STM8 through the STMicroelectronics debug
+protocol SWIM, *note SWIM: swimtransport.
+
+16.14 Xtensa Architecture
+=========================
+
+Xtensa is a highly-customizable, user-extensible microprocessor and DSP
+architecture for complex embedded systems provided by Cadence Design
+Systems, Inc.  See the Tensilica IP
+(https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html) website
+for additional information and documentation.
+
+OpenOCD supports generic Xtensa processor implementations which can be
+customized by providing a core-specific configuration file which
+describes every enabled Xtensa architecture option, e.g.  number of
+address registers, exceptions, reduced size instructions support, memory
+banks configuration etc.  OpenOCD also supports SMP configurations for
+Xtensa processors with any number of cores and allows configuring their
+debug interconnect (termed "break/stall networks"), which control how
+debug signals are distributed among cores.  Xtensa "break networks" are
+compatible with ARM's Cross Trigger Interface (CTI). OpenOCD implements
+both generic Xtensa targets as well as several Espressif Xtensa-based
+chips from the ESP32 family
+(https://www.espressif.com/en/products/socs).
+
+OCD sessions for Xtensa processor and DSP targets are accessed via the
+Xtensa Debug Module (XDM), which provides external connectivity either
+through a traditional JTAG interface or an ARM DAP interface.  If used,
+the DAP interface can control Xtensa targets through JTAG or SWD probes.
+
+16.14.1 Xtensa Core Configuration
+---------------------------------
+
+Due to the high level of configurability in Xtensa cores, the Xtensa
+target configuration comprises two categories:
+
+  1. Base Xtensa support common to all core configurations, and
+  2. Core-specific support as configured for individual cores.
+
+All common Xtensa support is built into the OpenOCD Xtensa target layer
+and is enabled through a combination of TCL scripts: the target-specific
+'target/xtensa.cfg' and a board-specific 'board/xtensa-*.cfg', similar
+to other target architectures.
+
+Importantly, core-specific configuration information must be provided by
+the user, and takes the form of an 'xtensa-core-XXX.cfg' TCL script that
+defines the core's configurable features through a series of Xtensa
+configuration commands (detailed below).
+
+This core-specific 'xtensa-core-XXX.cfg' file is typically either:
+
+   * Located within the Xtensa core configuration build as
+     'src/config/xtensa-core-openocd.cfg', or
+   * Generated by running the command 'xt-gdb --dump-oocd-config' from
+     the Xtensa processor tool-chain's command-line tools.
+
+NOTE: 'xtensa-core-XXX.cfg' must match the target Xtensa hardware
+connected to OpenOCD.
+
+Some example Xtensa configurations are bundled with OpenOCD for
+reference:
+  1. Cadence Palladium VDebug emulation target.  The user can combine
+     their 'xtensa-core-XXX.cfg' with the provided
+     'board/xtensa-palladium-vdebug.cfg' to debug an emulated Xtensa RTL
+     design.
+  2. NXP MIMXRT685-EVK evaluation kit.  The relevant configuration files
+     are:
+        * 'board/xtensa-rt685-ext.cfg'
+        * 'target/xtensa-core-nxp_rt600.cfg'
+     Additional information is available by searching for "i.MX RT600
+     Evaluation Kit" on .
+
+16.14.2 Xtensa Configuration Commands
+-------------------------------------
+
+ -- Config Command: xtensa xtdef ('LX'|'NX')
+     Configure the Xtensa target architecture to LX or NX. Currently,
+     Xtensa LX support is limited to LX6 and newer cores.
+
+ -- Config Command: xtensa xtopt option value
+     Configure Xtensa target options that are relevant to the debug
+     subsystem.  OPTION is one of: 'arnum', 'windowed', 'cpenable',
+     'exceptions', 'intnum', 'hipriints', 'excmlevel', 'intlevels',
+     'debuglevel', 'ibreaknum', or 'dbreaknum'.  VALUE is an integer
+     with the exact range determined by each particular option.
+
+     NOTE: Some options are specific to Xtensa LX or Xtensa NX
+     architecture, while others may be common to both but have different
+     valid ranges.
+
+ -- Config Command: xtensa xtmem
+          ('iram'|'dram'|'sram'|'irom'|'drom'|'srom') baseaddr bytes
+     Configure Xtensa target memory.  Memory type determines access
+     rights, where RAMs are read/write while ROMs are read-only.
+     BASEADDR and BYTES are both integers, typically hexadecimal and
+     decimal, respectively.
+
+     NOTE: Some Xtensa memory types, such as system RAM/ROM or
+     MMIO/device regions, can be added or modified after the Xtensa core
+     has been generated.  Additional 'xtensa xtmem' definitions should
+     be manually added to xtensa-core-XXX.cfg to keep OpenOCD's target
+     address map consistent with the Xtensa configuration.
+
+ -- Config Command: xtensa xtmem ('icache'|'dcache') linebytes
+          cachebytes ways [writeback]
+     Configure Xtensa processor cache.  All parameters are required
+     except for the optional 'writeback' parameter; all are integers.
+
+ -- Config Command: xtensa xtmpu numfgseg minsegsz lockable execonly
+     Configure an Xtensa Memory Protection Unit (MPU). MPUs can restrict
+     access and/or control cacheability of specific address ranges, but
+     are lighter-weight than a full traditional MMU. All parameters are
+     required; all are integers.
+
+ -- Config Command: xtensa xtmmu numirefillentries numdrefillentries
+     (Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU).
+     Both parameters are required; both are integers.
+
+ -- Config Command: xtensa xtregs numregs
+     Configure the total number of registers for the Xtensa core.
+     Configuration logic expects to subsequently process this number of
+     'xtensa xtreg' definitions.  NUMREGS is an integer.
+
+ -- Config Command: xtensa xtregfmt ('sparse'|'contiguous') [general]
+     Configure the type of register map used by GDB to access the Xtensa
+     core.  Generic Xtensa tools (e.g.  xt-gdb) require 'sparse' mapping
+     (default) while Espressif tools expect 'contiguous' mapping.
+     Contiguous mapping takes an additional, optional integer parameter
+     'numgregs', which specifies the number of general registers used in
+     handling g/G packets.
+
+ -- Config Command: xtensa xtreg name offset
+     Configure an Xtensa core register.  All core registers are 32 bits
+     wide, while TIE and user registers may have variable widths.  NAME
+     is a character string identifier while OFFSET is a hexadecimal
+     integer.
+
+16.14.3 Xtensa Operation Commands
+---------------------------------
+
+ -- Command: xtensa maskisr ('on'|'off')
+     (Xtensa-LX only) Mask or unmask Xtensa interrupts during
+     instruction step.  When masked, an interrupt that occurs during a
+     step operation is handled and its ISR is executed, with the user's
+     debug session returning after potentially executing many
+     instructions.  When unmasked, a triggered interrupt will result in
+     execution progressing the requested number of instructions into the
+     relevant vector/ISR code.
+
+ -- Command: xtensa set_permissive (0|1)
+     By default accessing memory beyond defined regions is forbidden.
+     This commnd controls memory access address check.  When set to (1),
+     skips access controls and address range check before read/write
+     memory.
+
+ -- Command: xtensa smpbreak [none|breakinout|runstall] | [BreakIn]
+          [BreakOut] [RunStallIn] [DebugModeOut]
+     Configures debug signals connection ("break network") for currently
+     selected core.
+        * 'none' - Core's "break/stall network" is disconnected.  Core
+          is not affected by any debug signal from other cores.
+        * 'breakinout' - Core's "break network" is fully connected
+          (break inputs and outputs are enabled).  Core will receive
+          debug break signals from other cores and send such signals to
+          them.  For example when another core is stopped due to
+          breakpoint hit this core will be stopped too and vice versa.
+        * 'runstall' - Core's "stall network" is fully connected (stall
+          inputs and outputs are enabled).  This feature is not well
+          implemented and tested yet.
+        * 'BreakIn' - Core's "break-in" signal is enabled.  Core will
+          receive debug break signals from other cores.  For example
+          when another core is stopped due to breakpoint hit this core
+          will be stopped too.
+        * 'BreakOut' - Core's "break-out" signal is enabled.  Core will
+          send debug break signal to other cores.  For example when this
+          core is stopped due to breakpoint hit other cores with enabled
+          break-in signals will be stopped too.
+        * 'RunStallIn' - Core's "runstall-in" signal is enabled.  This
+          feature is not well implemented and tested yet.
+        * 'DebugModeOut' - Core's "debugmode-out" signal is enabled.
+          This feature is not well implemented and tested yet.
+
+ -- Command: xtensa exe 
+     Execute one arbitrary instruction provided as an ascii string.  The
+     string represents an integer number of instruction bytes, thus its
+     length must be even.  The instruction can be of any width that is
+     valid for the Xtensa core configuration.
+
+ -- Command: xtensa dm (address) [value]
+     Read or write Xtensa Debug Module (DM) registers.  ADDRESS is
+     required for both reads and writes and is a 4-byte-aligned value
+     typically between 0 and 0x3ffc.  VALUE is specified only for write
+     accesses.
+
+16.14.4 Xtensa Performance Monitor Configuration
+------------------------------------------------
+
+ -- Command: xtensa perfmon_enable   [mask]
+          [kernelcnt] [tracelevel]
+     Enable and start performance counter.
+        * 'counter_id' - Counter ID (0-1).
+        * 'select' - Selects performance metric to be counted by the
+          counter, e.g.  0 - CPU cycles, 2 - retired instructions.
+        * 'mask' - Selects input subsets to be counted (counter will
+          increment only once even if more than one condition
+          corresponding to a mask bit occurs).
+        * 'kernelcnt' - 0 - count events with "CINTLEVEL <= tracelevel",
+          1 - count events with "CINTLEVEL > tracelevel".
+        * 'tracelevel' - Compares this value to "CINTLEVEL" when
+          deciding whether to count.
+
+ -- Command: xtensa perfmon_dump (counter_id)
+     Dump performance counter value.  If no argument specified, dumps
+     all counters.
+
+16.14.5 Xtensa Trace Configuration
+----------------------------------
+
+ -- Command: xtensa tracestart [pc /[]] [after 
+          [ins|words]]
+     Set up and start a HW trace.  Optionally set PC address range to
+     trigger tracing stop when reached during program execution.  This
+     command also allows to specify the amount of data to capture after
+     stop trigger activation.
+        * 'pcval' - PC value which will trigger trace data collection
+          stop.
+        * 'maskbitcount' - PC value mask.
+        * 'n' - Maximum number of instructions/words to capture after
+          trace stop trigger.
+
+ -- Command: xtensa tracestop
+     Stop current trace as started by the tracestart command.
+
+ -- Command: xtensa tracedump 
+     Dump trace memory to a file.
+
+16.15 Espressif Specific Commands
+=================================
+
+ -- Command: esp apptrace (start  [
+          [ [ [ []]]]])
+     Starts application level tracing
+     (https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library).
+     Data will be stored to specified destination.  Available
+     destinations are:
+        * 'file://' - Save trace logs into file.
+        * 'tcp://:' - Send trace logs to tcp port on
+          specified host.  OpenOCD will act as a tcp client.
+        * 'con:' - Print trace logs to the stdout.
+     Other parameters will be same for each destination.
+        * 'poll_period' - trace data polling period in ms.
+        * 'trace_size' - maximum trace data size.  Tracing will be
+          stopped automatically when that amount is reached.  Use "-1"
+          to disable the limitation.
+        * 'stop_tmo' - Data reception timeout in ms.  Tracing will be
+          stopped automatically when no data is received within that
+          period.
+        * 'wait4halt' - if non-zero then wait for target to be halted
+          before tracing start.
+        * 'skip_size' - amount of tracing data to be skipped before
+          writing it to destination.
+
+ -- Command: esp apptrace (stop)
+     Stops tracing started with above command.
+
+ -- Command: esp apptrace (status)
+     Requests ongoing tracing status.
+
+ -- Command: esp apptrace (dump file://)
+     Dumps tracing data from target buffer.  It can be useful to dump
+     the latest data buffered on target for post-mortem analysis.  For
+     example when target starts tracing automatically w/o OpenOCD
+     command and keeps only the latest data window which fit into the
+     buffer.  application level tracing
+     (https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library).
+     Data will be stored to specified destination.
+
+ -- Command: esp sysview (start file:// [file://]
+          [ [ [ [
+          []]]]])
+     Starts SEGGER SystemView
+     (https://www.segger.com/products/development-tools/systemview/)
+     compatible tracing.  Data will be stored to specified destination.
+     For dual-core chips traces from every core will be saved to
+     separate files.  Resulting files can be open in "SEGGER SystemView"
+     application.
+     
+     The meaning of the arguments is identical to 'esp apptrace start'.
+
+ -- Command: esp sysview (stop)
+     Stops SystremView compatible tracing started with above command.
+     
+
+ -- Command: esp sysview (status)
+     Requests ongoing SystremView compatible tracing status.
+     
+
+ -- Command: esp sysview_mcore (start file:// [
+          [ [ [ []]]]])
+     This command is identical to 'esp sysview start', but uses
+     Espressif multi-core extension to SEGGER SystemView
+     (https://www.segger.com/products/development-tools/systemview/)
+     data format.  Data will be stored to specified destination.
+     Tracing data from all cores are saved in the same file.  The
+     meaning of the arguments is identical to 'esp sysview start'.
+
+ -- Command: esp sysview_mcore (stop)
+     Stops Espressif multi-core SystremView tracing started with above
+     command.
+
+ -- Command: esp sysview_mcore (status)
+     Requests ongoing Espressif multi-core SystremView tracing status.
+
+16.16 Software Debug Messages and Tracing
+=========================================
+
+OpenOCD can process certain requests from target software, when the
+target uses appropriate libraries.  The most powerful mechanism is
+semihosting, but there is also a lighter weight mechanism using only the
+DCC channel.
+
+Currently 'target_request debugmsgs' is supported only for 'arm7_9' and
+'cortex_m' cores.  These messages are received as part of target
+polling, so you need to have 'poll on' active to receive them.  They are
+intrusive in that they will affect program execution times.  If that is
+a problem, *note ARM Hardware Tracing: armhardwaretracing.
+
+See 'libdcc' in the contrib dir for more details.  In addition to
+sending strings, characters, and arrays of various size integers from
+the target, 'libdcc' also exports a software trace point mechanism.  The
+target being debugged may issue trace messages which include a 24-bit
+"trace point" number.  Trace point support includes two distinct
+mechanisms, each supported by a command:
+
+   * _History_ ...  A circular buffer of trace points can be set up, and
+     then displayed at any time.  This tracks where code has been, which
+     can be invaluable in finding out how some fault was triggered.
+
+     The buffer may overflow, since it collects records continuously.
+     It may be useful to use some of the 24 bits to represent a
+     particular event, and other bits to hold data.
+
+   * _Counting_ ...  An array of counters can be set up, and then
+     displayed at any time.  This can help establish code coverage and
+     identify hot spots.
+
+     The array of counters is directly indexed by the trace point
+     number, so trace points with higher numbers are not counted.
+
+Linux-ARM kernels have a "Kernel low-level debugging via EmbeddedICE DCC
+channel" option (CONFIG_DEBUG_ICEDCC, depends on CONFIG_DEBUG_LL) which
+uses this mechanism to deliver messages before a serial console can be
+activated.  This is not the same format used by 'libdcc'.  Other
+software, such as the U-Boot boot loader, sometimes does the same thing.
+
+ -- Command: target_request debugmsgs ['enable'|'disable'|'charmsg']
+     Displays current handling of target DCC message requests.  These
+     messages may be sent to the debugger while the target is running.
+     The optional 'enable' and 'charmsg' parameters both enable the
+     messages, while 'disable' disables them.
+
+     With 'charmsg' the DCC words each contain one character, as used by
+     Linux with CONFIG_DEBUG_ICEDCC; otherwise the libdcc format is
+     used.
+
+ -- Command: trace history ['clear'|count]
+     With no parameter, displays all the trace points that have
+     triggered in the order they triggered.  With the parameter 'clear',
+     erases all current trace history records.  With a COUNT parameter,
+     allocates space for that many history records.
+
+ -- Command: trace point ['clear'|identifier]
+     With no parameter, displays all trace point identifiers and how
+     many times they have been triggered.  With the parameter 'clear',
+     erases all current trace point counters.  With a numeric IDENTIFIER
+     parameter, creates a new a trace point counter and associates it
+     with that identifier.
+
+     _Important:_ The identifier and the trace point number are not
+     related except by this command.  These trace point numbers always
+     start at zero (from server startup, or after 'trace point clear')
+     and count up from there.
+
+
+File: openocd.info,  Node: JTAG Commands,  Next: Boundary Scan Commands,  Prev: Architecture and Core Commands,  Up: Top
+
+17 JTAG Commands
+****************
+
+Most general purpose JTAG commands have been presented earlier.  (*Note
+JTAG Speed: jtagspeed, *note Reset Configuration::, and *note TAP
+Declaration::.)  Lower level JTAG commands, as presented here, may be
+needed to work with targets which require special attention during
+operations such as reset or initialization.
+
+To use these commands you will need to understand some of the basics of
+JTAG, including:
+
+   * A JTAG scan chain consists of a sequence of individual TAP devices
+     such as a CPUs.
+   * Control operations involve moving each TAP through the same
+     standard state machine (in parallel) using their shared TMS and
+     clock signals.
+   * Data transfer involves shifting data through the chain of
+     instruction or data registers of each TAP, writing new register
+     values while the reading previous ones.
+   * Data register sizes are a function of the instruction active in a
+     given TAP, while instruction register sizes are fixed for each TAP.
+     All TAPs support a BYPASS instruction with a single bit data
+     register.
+   * The way OpenOCD differentiates between TAP devices is by shifting
+     different instructions into (and out of) their instruction
+     registers.
+
+17.1 Low Level JTAG Commands
+============================
+
+These commands are used by developers who need to access JTAG
+instruction or data registers, possibly controlling the order of TAP
+state transitions.  If you're not debugging OpenOCD internals, or
+bringing up a new JTAG adapter or a new type of TAP device (like a CPU
+or JTAG router), you probably won't need to use these commands.  In a
+debug session that doesn't use JTAG for its transport protocol, these
+commands are not available.
+
+ -- Command: drscan tap [numbits value]+ ['-endstate' tap_state]
+     Loads the data register of TAP with a series of bit fields that
+     specify the entire register.  Each field is NUMBITS bits long with
+     a numeric VALUE (hexadecimal encouraged).  The return value holds
+     the original value of each of those fields.
+
+     For example, a 38 bit number might be specified as one field of 32
+     bits then one of 6 bits.  _For portability, never pass fields which
+     are more than 32 bits long.  Many OpenOCD implementations do not
+     support 64-bit (or larger) integer values._
+
+     All TAPs other than TAP must be in BYPASS mode.  The single bit in
+     their data registers does not matter.
+
+     When TAP_STATE is specified, the JTAG state machine is left in that
+     state.  For example DRPAUSE might be specified, so that more
+     instructions can be issued before re-entering the RUN/IDLE state.
+     If the end state is not specified, the RUN/IDLE state is entered.
+
+          Warning: OpenOCD does not record information about data
+          register lengths, so _it is important that you get the bit
+          field lengths right_.  Remember that different JTAG
+          instructions refer to different data registers, which may have
+          different lengths.  Moreover, those lengths may not be fixed;
+          the SCAN_N instruction can change the length of the register
+          accessed by the INTEST instruction (by connecting a different
+          scan chain).
+
+ -- Command: flush_count
+     Returns the number of times the JTAG queue has been flushed.  This
+     may be used for performance tuning.
+
+     For example, flushing a queue over USB involves a minimum latency,
+     often several milliseconds, which does not change with the amount
+     of data which is written.  You may be able to identify performance
+     problems by finding tasks which waste bandwidth by flushing small
+     transfers too often, instead of batching them into larger
+     operations.
+
+ -- Command: irscan [tap instruction]+ ['-endstate' tap_state]
+     For each TAP listed, loads the instruction register with its
+     associated numeric INSTRUCTION.  (The number of bits in that
+     instruction may be displayed using the 'scan_chain' command.)  For
+     other TAPs, a BYPASS instruction is loaded.
+
+     When TAP_STATE is specified, the JTAG state machine is left in that
+     state.  For example IRPAUSE might be specified, so the data
+     register can be loaded before re-entering the RUN/IDLE state.  If
+     the end state is not specified, the RUN/IDLE state is entered.
+
+          Note: OpenOCD currently supports only a single field for
+          instruction register values, unlike data register values.  For
+          TAPs where the instruction register length is more than 32
+          bits, portable scripts currently must issue only BYPASS
+          instructions.
+
+ -- Command: pathmove start_state [next_state ...]
+     Start by moving to START_STATE, which must be one of the _stable_
+     states.  Unless it is the only state given, this will often be the
+     current state, so that no TCK transitions are needed.  Then, in a
+     series of single state transitions (conforming to the JTAG state
+     machine) shift to each NEXT_STATE in sequence, one per TCK cycle.
+     The final state must also be stable.
+
+ -- Command: runtest NUM_CYCLES
+     Move to the RUN/IDLE state, and execute at least NUM_CYCLES of the
+     JTAG clock (TCK). Instructions often need some time to execute
+     before they take effect.
+
+ -- Command: verify_ircapture ('enable'|'disable')
+     Verify values captured during IRCAPTURE and returned during IR
+     scans.  Default is enabled, but this can be overridden by
+     'verify_jtag'.  This flag is ignored when validating JTAG chain
+     configuration.
+
+ -- Command: verify_jtag ('enable'|'disable')
+     Enables verification of DR and IR scans, to help detect programming
+     errors.  For IR scans, 'verify_ircapture' must also be enabled.
+     Default is enabled.
+
+17.2 TAP state names
+====================
+
+The TAP_STATE names used by OpenOCD in the 'drscan', 'irscan', and
+'pathmove' commands are the same as those used in SVF boundary scan
+documents, except that SVF uses IDLE instead of RUN/IDLE.
+
+   * RESET ...  _stable_ (with TMS high); acts as if TRST were pulsed
+   * RUN/IDLE ...  _stable_; don't assume this always means IDLE
+   * DRSELECT
+   * DRCAPTURE
+   * DRSHIFT ...  _stable_; TDI/TDO shifting through the data register
+   * DREXIT1
+   * DRPAUSE ...  _stable_; data register ready for update or more
+     shifting
+   * DREXIT2
+   * DRUPDATE
+   * IRSELECT
+   * IRCAPTURE
+   * IRSHIFT ...  _stable_; TDI/TDO shifting through the instruction
+     register
+   * IREXIT1
+   * IRPAUSE ...  _stable_; instruction register ready for update or
+     more shifting
+   * IREXIT2
+   * IRUPDATE
+
+Note that only six of those states are fully "stable" in the face of TMS
+fixed (low except for RESET) and a free-running JTAG clock.  For all the
+others, the next TCK transition changes to a new state.
+
+   * From DRSHIFT and IRSHIFT, clock transitions will produce side
+     effects by changing register contents.  The values to be latched in
+     upcoming DRUPDATE or IRUPDATE states may not be as expected.
+   * RUN/IDLE, DRPAUSE, and IRPAUSE are reasonable choices after
+     'drscan' or 'irscan' commands, since they are free of JTAG side
+     effects.
+   * RUN/IDLE may have side effects that appear at non-JTAG levels, such
+     as advancing the ARM9E-S instruction pipeline.  Consult the
+     documentation for the TAP(s) you are working with.
+
+
+File: openocd.info,  Node: Boundary Scan Commands,  Next: Utility Commands,  Prev: JTAG Commands,  Up: Top
+
+18 Boundary Scan Commands
+*************************
+
+One of the original purposes of JTAG was to support boundary scan based
+hardware testing.  Although its primary focus is to support On-Chip
+Debugging, OpenOCD also includes some boundary scan commands.
+
+18.1 SVF: Serial Vector Format
+==============================
+
+The Serial Vector Format, better known as "SVF", is a way to represent
+JTAG test patterns in text files.  In a debug session using JTAG for its
+transport protocol, OpenOCD supports running such test files.
+
+ -- Command: svf 'filename' ['-tap TAPNAME'] ['-quiet'] ['-nil']
+          ['-progress'] ['-ignore_error'] ['-noreset'] ['-addcycles
+          CYCLECOUNT']
+     This issues a JTAG reset (Test-Logic-Reset) and then runs the SVF
+     script from 'filename'.
+
+     Arguments can be specified in any order; the optional dash doesn't
+     affect their semantics.
+
+     Command options:
+        - '-tap TAPNAME' ignore IR and DR headers and footers specified
+          by the SVF file with HIR, TIR, HDR and TDR commands; instead,
+          calculate them automatically according to the current JTAG
+          chain configuration, targeting TAPNAME;
+        - '-quiet' do not log every command before execution;
+        - '-nil' "dry run", i.e., do not perform any operations on the
+          real interface;
+        - '-progress' enable progress indication;
+        - '-ignore_error' continue execution despite TDO check errors.
+        - '-noreset' omit JTAG reset (Test-Logic-Reset) before executing
+          content of the SVF file;
+        - '-addcycles CYCLECOUNT' inject CYCLECOUNT number of additional
+          TCLK cycles after each SDR scan instruction;
+
+18.2 XSVF: Xilinx Serial Vector Format
+======================================
+
+The Xilinx Serial Vector Format, better known as "XSVF", is a binary
+representation of SVF which is optimized for use with Xilinx devices.
+In a debug session using JTAG for its transport protocol, OpenOCD
+supports running such test files.
+
+     Important: Not all XSVF commands are supported.
+
+ -- Command: xsvf (tapname|'plain') filename ['virt2'] ['quiet']
+     This issues a JTAG reset (Test-Logic-Reset) and then runs the XSVF
+     script from 'filename'.  When a TAPNAME is specified, the commands
+     are directed at that TAP. When 'virt2' is specified, the XRUNTEST
+     command counts are interpreted as TCK cycles instead of
+     microseconds.  Unless the 'quiet' option is specified, messages are
+     logged for comments and some retries.
+
+The OpenOCD sources also include two utility scripts for working with
+XSVF; they are not currently installed after building the software.  You
+may find them useful:
+
+   * _svf2xsvf_ ...  converts SVF files into the extended XSVF syntax
+     understood by the 'xsvf' command; see notes below.
+   * _xsvfdump_ ...  converts XSVF files into a text output format;
+     understands the OpenOCD extensions.
+
+The input format accepts a handful of non-standard extensions.  These
+include three opcodes corresponding to SVF extensions from Lattice
+Semiconductor (LCOUNT, LDELAY, LDSR), and two opcodes supporting a more
+accurate translation of SVF (XTRST, XWAITSTATE). If _xsvfdump_ shows a
+file is using those opcodes, it probably will not be usable with other
+XSVF tools.
+
+18.3 IPDBG: JTAG-Host server
+============================
+
+IPDBG is a set of tools to debug IP-Cores.  It comprises, among others,
+a logic analyzer and an arbitrary waveform generator.  These are
+synthesize-able hardware descriptions of logic circuits in addition to
+software for control, visualization and further analysis.  In a session
+using JTAG for its transport protocol, OpenOCD supports the function of
+a JTAG-Host.  The JTAG-Host is needed to connect the circuit over JTAG
+to the control-software.  The JTAG-Hub is the circuit which transfers
+the data from JTAG to the different tools connected to the Hub.  Hub
+implementations for most major FPGA vendors/families are provided.  For
+more details see .
+
+ -- Command: ipdbg create-hub HUB_NAME '-tap TAPNAME' '-ir IR_VALUE
+          [DR_LENGTH]' ['-vir [VIR_VALUE [LENGTH [INSTR_CODE]]]']
+ -- Command: ipdbg create-hub HUB_NAME '-pld PLD_NAME [USER]' ['-vir
+          [VIR_VALUE [LENGTH [INSTR_CODE]]]']
+     Creates a IPDBG JTAG Hub.  The created hub is later used to start,
+     stop and configure IPDBG JTAG Host servers.  The first argument
+     HUB_NAME is the name of the created hub.  It can be used later as a
+     reference.
+
+     The pld drivers are able to provide the tap and ir_value for the
+     IPDBG JTAG-Host server.  This will be used with the second variant
+     with option '-pld'.
+
+     Command options:
+        * HUB_NAME the name of the IPDBG hub.  This name is also used to
+          create the object's command, referred to here as '$hub_name',
+          and in other places where the Hub needs to be identified.
+
+        * '-tap TAPNAME' targeting the TAP TAPNAME.
+
+        * '-ir IR_VALUE' states that the JTAG hub is reachable with
+          dr-scans while the JTAG instruction register has the value
+          IR_VALUE.  Also known as USERx instructions.  The optional
+          DR_LENGTH is the length of the dr.  Current JTAG-Hub
+          implementation only supports dr_length=13, which is also the
+          default value.
+
+        * '-vir [VIR_VALUE [LENGTH [INSTR_CODE]]]' To support more Hubs
+          than USER registers in a single FPGA it is possible to use a
+          mechanism known as virtual-ir where the user data-register is
+          reachable if there is a specific value in a second dr.  This
+          second dr is called vir (virtual ir).  With this parameter
+          given, the IPDBG satisfies this condition prior an access to
+          the IPDBG-Hub.  The value shifted into the vir is given by the
+          first parameter VIR_VALUE (default: 0x11).  The second
+          parameter LENGTH is the length of the vir data register
+          (default: 5).  With the INSTR_CODE (default: 0x00e) parameter
+          the ir value to shift data through vir can be configured.
+
+        * '-pld PLD_NAME [USER]' The defined driver for the pld PLD_NAME
+          is used to get the tap and user instruction.  The pld devices
+          names can be shown by the command 'pld devices'.  With [USER]
+          one can select a different USERx-Instruction.  If the IPDBG
+          JTAG-Hub is used without modification the default value of 1
+          which selects the first USERx instruction is adequate.  The
+          USERx instructions are vendor specific and don't change
+          between families of the same vendor.  So if there's a pld
+          driver for your vendor it should work with your FPGA even when
+          the driver is not compatible with your device for the
+          remaining features.  If your device/vendor is not supported
+          you have to use the first variant.
+
+ -- Command: $hub_name ipdbg start '-tool NUMBER' '-port NUMBER'
+     Starts a IPDBG JTAG-Host server.  The remaining arguments can be
+     specified in any order.
+
+     Command options:
+        * '-port NUMBER' tcp port number where the JTAG-Host will
+          listen.  The default is 4242 which is used when the option is
+          not given.
+        * '-tool NUMBER' number of the tool/feature.  These corresponds
+          to the ports "data_(up/down)_(0..6)" at the JtagHub.  The
+          default is 1 which is used when the option is not given.
+
+ -- Command: $hub_name ipdbg stop '-tool NUMBER'
+     Stops a IPDBG JTAG-Host server.  Command options:
+        * '-tool NUMBER' number of the tool/feature.  These corresponds
+          to the ports "data_(up/down)_(0..6)" at the JtagHub.  The
+          default is 1 which is used when the option is not given.
+
+Examples:
+     ipdbg create-hub xc6s.ipdbghub -tap xc6s.tap -hub 0x02
+     xc6s.ipdbghub ipdbg start -port 4242 -tool 4
+Creates a IPDBG Hub and starts a server listening on tcp-port 4242 which
+connects to tool 4.  The connection is through the TAP of a Xilinx
+Spartan 6 on USER1 instruction (tested with a papillion pro board).
+
+     ipdbg create-hub max10m50.ipdbghub -tap max10m50.tap -hub 0x00C -vir
+     max10m50.ipdbghub ipdbg start -tool 1 -port 60000
+Starts a server listening on tcp-port 60000 which connects to tool 1
+(data_up_1/data_down_1).  The connection is through the TAP of a Intel
+MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is
+smaller than 5).
+
+     ipdbg create-hub xc7.ipdbghub -pld xc7.pld
+     xc7.ipdbghub ipdbg start -port 5555 -tool 0
+Starts a server listening on tcp-port 5555 which connects to tool 0
+(data_up_0/data_down_0).  The TAP and ir value used to reach the JTAG
+Hub is given by the pld driver.
+
+ -- Command: $hub_name queuing '-size SIZE'
+     Configure the queuing between IPDBG JTAG-Host and Hub.  The maximum
+     possible queue size is 1024 which is also the default.
+
+        * '-size SIZE' max number of transfers in the queue.
+
+     bitbang.ibdbghub queuing -size 32
+Send a maximum of 32 transfers to the queue before executing them.
+
+
+File: openocd.info,  Node: Utility Commands,  Next: Nuclei Commands,  Prev: Boundary Scan Commands,  Up: Top
+
+19 Utility Commands
+*******************
+
+19.1 RAM testing
+================
+
+There is often a need to stress-test random access memory (RAM) for
+errors.  OpenOCD comes with a Tcl implementation of well-known memory
+testing procedures allowing the detection of all sorts of issues with
+electrical wiring, defective chips, PCB layout and other common hardware
+problems.
+
+To use them, you usually need to initialise your RAM controller first;
+consult your SoC's documentation to get the recommended list of register
+operations and translate them to the corresponding 'mww'/'mwb' commands.
+
+Load the memory testing functions with
+
+     source [find tools/memtest.tcl]
+
+to get access to the following facilities:
+
+ -- Command: memTestDataBus address
+     Test the data bus wiring in a memory region by performing a walking
+     1's test at a fixed address within that region.
+
+ -- Command: memTestAddressBus baseaddress size
+     Perform a walking 1's test on the relevant bits of the address and
+     check for aliasing.  This test will find single-bit address
+     failures such as stuck-high, stuck-low, and shorted pins.
+
+ -- Command: memTestDevice baseaddress size
+     Test the integrity of a physical memory device by performing an
+     increment/decrement test over the entire region.  In the process
+     every storage bit in the device is tested as zero and as one.
+
+ -- Command: runAllMemTests baseaddress size
+     Run all of the above tests over a specified memory region.
+
+19.2 Firmware recovery helpers
+==============================
+
+OpenOCD includes an easy-to-use script to facilitate mass-market devices
+recovery with JTAG.
+
+For quickstart instructions run:
+     openocd -f tools/firmware-recovery.tcl -c firmware_help
+
+
+File: openocd.info,  Node: Nuclei Commands,  Next: GDB and OpenOCD,  Prev: Utility Commands,  Up: Top
+
+20 Nuclei Commands
+******************
+
+The commands here apply only to Nuclei series CPUs.
+
+20.1 Show CPU Info
+==================
+
+Usually we don't know what instruction sets a CPU supports, what
+functional components it contains, and the various configurations of the
+components.  The only way to get the desired information is to read the
+corresponding CSR registers and then do the math.  It would be a pain in
+the ass to do this for every function point that needs to be known.
+This command is designed to solve this problem by automatically reading
+the CSRs and doing the math, and then formatting the output.
+
+This command should be executed after the 'init' command.
+
+ -- Command: nuclei cpuinfo
+     Displays some information about the currently used CPU.
+
+20.2 Etrace Commands
+====================
+
+Some Nuclei cpus are equipped with trace support, which permits
+examination of the instruction activity.  Trace activity is controlled
+through an "Embedded Trace"(Etrace) Module on the core's scan chains.
+The following commands are for etrace.
+
+This command should be executed after the 'init' command.
+
+ -- Command: nuclei etrace config atb2axi-config-addr buffer-addr
+          buffer-size wrap
+     Configure each parameter needed for etrace.  Command options:
+        * 'atb2axi-config-addr' The address of the atb2axi controller.
+        * 'buffer-addr' The base address of etrace buffer.
+        * 'buffer-size' The bytes size of the etrace buffer.
+        * 'wrap' [0|1] Whether trace data is automatically looped back
+          for overwriting.
+
+ -- Command: nuclei etrace enable
+     Enable the etrace switch within the CPU.
+
+ -- Command: nuclei etrace disable
+     Disable the etrace switch within the CPU.
+
+ -- Command: nuclei etrace start
+     Start etrace data collection.
+
+ -- Command: nuclei etrace stop
+     Stop etrace data collection.
+
+ -- Command: nuclei etrace dump filename
+     dump etrace data to the specified file.
+
+ -- Command: nuclei etrace clear
+     clear etrace register status and flags.
+
+ -- Command: nuclei etrace info
+     display etrace some info.
+
+20.3 Extended Commands
+======================
+
+Nuclei extends the functionality of some existing commands, as described
+below.
+
+ -- Command: ftdi nscan1_mode on|off
+     Enable or disable Nuclei CJTAG mode.  Usage is the same as 'ftdi
+     oscan1_mode'.
+
+ -- Command: flash bank name driver base size chip_width bus_width
+          target [driver_options]
+     Nuclei extends this command with two drivers, nuspi and custom.
+     Use can refer to the 'flash bank' command.
+
+   * 'driver_options' ...
+
+     For nuspi, [driver_options] has two options, the final command
+     format looks like this:
+          flash bank name nuspi base size chip_width bus_width target \
+          [spi_base] [simulation]
+
+     For custom, [driver_options] has three options, the final command
+     format looks like this:
+          flash bank name custom base size chip_width bus_width target \
+          spi_base loader_path [simulation] [sectorsize=]
+
+Here are some examples for nuspi:
+     # if spi_base is not specified then spi_base is 0x10014000.
+     flash bank $FLASHNAME nuspi 0x20000000 0 0 0 $TARGETNAME
+
+     # Without the simulation parameter, the flash operation will have
+     # a timeout, the value of which is automatically calculated according
+     # to the size of the operation data volume.
+     flash bank $FLASHNAME nuspi 0x20000000 0 0 0 $TARGETNAME 0x10180000
+
+     # If the simulation parameter is present, the flash operation will
+     # no longer time out.
+     flash bank $FLASHNAME nuspi 0x20000000 0 0 0 $TARGETNAME 0x10180000 \
+     simulation
+
+Here are some examples for custom:
+     # Without the simulation parameter, the flash operation will have a
+     # timeout, the value of which is automatically calculated according
+     # to the size of the operation data volume.
+     flash bank $FLASHNAME custom 0x20000000 0 0 0 $TARGETNAME 0x10180000 \
+     /home/admin/flashloader.bin
+
+     # If the simulation parameter is present, the flash operation will no
+     # longer time out. if the sectorsize parameter is not specified,
+     # then sectorsize is 0x10000.
+     flash bank $FLASHNAME custom 0x20000000 0 0 0 $TARGETNAME 0x10180000 \
+     /home/admin/flashloader.bin simulation
+
+     flash bank $FLASHNAME custom 0x20000000 0 0 0 $TARGETNAME 0x10180000 \
+     /home/admin/flashloader.bin sectorsize=0x1000
+
+     flash bank $FLASHNAME custom 0x20000000 0 0 0 $TARGETNAME 0x10180000 \
+     /home/admin/flashloader.bin simulation sectorsize=0x1000
+
+     flash bank $FLASHNAME nuspi 0x20000000 0 0 0 $TARGETNAME 0x10180000 \
+     /home/admin/flashloader.bin sectorsize=0x1000 simulation
+
+This flashloader.bin is compiled and generated through the
+openocd-flashloader project, the open source address is
+https://github.com/riscv-mcu/openflashloader.
+
+ -- Command: init resethalt
+     Nuclei extends the init command with the resethalt parameter.
+     Usage is the same as 'init'.
+
+In practice, usually encountered due to software problems caused by the
+CPU stuck, then the debugger will not be connected to the development
+board, only to the development board power off.  If your code is running
+in flash, powering down the board will not solve the problem.  resethalt
+is designed to solve this problem.
+
+Here are some examples:
+     init resethalt
+
+
+File: openocd.info,  Node: GDB and OpenOCD,  Next: Tcl Scripting API,  Prev: Nuclei Commands,  Up: Top
+
+21 GDB and OpenOCD
+******************
+
+OpenOCD complies with the remote gdbserver protocol and, as such, can be
+used to debug remote targets.  Setting up GDB to work with OpenOCD can
+involve several components:
+
+   * The OpenOCD server support for GDB may need to be configured.
+     *Note GDB Configuration: gdbconfiguration.
+   * GDB's support for OpenOCD may need configuration, as shown in this
+     chapter.
+   * If you have a GUI environment like Eclipse, that also will probably
+     need to be configured.
+
+Of course, the version of GDB you use will need to be one which has been
+built to know about the target CPU you're using.  It's probably part of
+the tool chain you're using.  For example, if you are doing
+cross-development for ARM on an x86 PC, instead of using the native x86
+'gdb' command you might use 'arm-none-eabi-gdb' if that's the tool chain
+used to compile your code.
+
+21.1 Connecting to GDB
+======================
+
+Use GDB 6.7 or newer with OpenOCD if you run into trouble.  For instance
+GDB 6.3 has a known bug that produces bogus memory access errors, which
+has since been fixed; see
+
+
+OpenOCD can communicate with GDB in two ways:
+
+  1. A socket (TCP/IP) connection is typically started as follows:
+          target extended-remote localhost:3333
+     This would cause GDB to connect to the gdbserver on the local pc
+     using port 3333.
+
+     The extended remote protocol is a super-set of the remote protocol
+     and should be the preferred choice.  More details are available in
+     GDB documentation
+     
+
+     To speed-up typing, any GDB command can be abbreviated, including
+     the extended remote command above that becomes:
+          tar ext :3333
+
+     Note: If any backward compatibility issue requires using the old
+     remote protocol in place of the extended remote one, the former
+     protocol is still available through the command:
+          target remote localhost:3333
+
+  2. A pipe connection is typically started as follows:
+          target extended-remote | \
+                 openocd -c "gdb port pipe; log_output openocd.log"
+     This would cause GDB to run OpenOCD and communicate using pipes
+     (stdin/stdout).  Using this method has the advantage of GDB
+     starting/stopping OpenOCD for the debug session.  log_output sends
+     the log output to a file to ensure that the pipe is not saturated
+     when using higher debug level outputs.
+
+To list the available OpenOCD commands type 'monitor help' on the GDB
+command line.
+
+21.2 Sample GDB session startup
+===============================
+
+With the remote protocol, GDB sessions start a little differently than
+they do when you're debugging locally.  Here's an example showing how to
+start a debug session with a small ARM program.  In this case the
+program was linked to be loaded into SRAM on a Cortex-M3.  Most programs
+would be written into flash (address 0) and run from there.
+
+     $ arm-none-eabi-gdb example.elf
+     (gdb) target extended-remote localhost:3333
+     Remote debugging using localhost:3333
+     ...
+     (gdb) monitor reset halt
+     ...
+     (gdb) load
+     Loading section .vectors, size 0x100 lma 0x20000000
+     Loading section .text, size 0x5a0 lma 0x20000100
+     Loading section .data, size 0x18 lma 0x200006a0
+     Start address 0x2000061c, load size 1720
+     Transfer rate: 22 KB/sec, 573 bytes/write.
+     (gdb) continue
+     Continuing.
+     ...
+
+You could then interrupt the GDB session to make the program break, type
+'where' to show the stack, 'list' to show the code around the program
+counter, 'step' through code, set breakpoints or watchpoints, and so on.
+
+21.3 Configuring GDB for OpenOCD
+================================
+
+OpenOCD supports the gdb 'qSupported' packet, this enables information
+to be sent by the GDB remote server (i.e.  OpenOCD) to GDB. Typical
+information includes packet size and the device's memory map.  You do
+not need to configure the packet size by hand, and the relevant parts of
+the memory map should be automatically set up when you declare (NOR)
+flash banks.
+
+However, there are other things which GDB can't currently query.  You
+may need to set those up by hand.  As OpenOCD starts up, you will often
+see a line reporting something like:
+
+     Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
+
+You can pass that information to GDB with these commands:
+
+     set remote hardware-breakpoint-limit 6
+     set remote hardware-watchpoint-limit 4
+
+With that particular hardware (Cortex-M3) the hardware breakpoints only
+work for code running from flash memory.  Most other ARM systems do not
+have such restrictions.
+
+Rather than typing such commands interactively, you may prefer to save
+them in a file and have GDB execute them as it starts, perhaps using a
+'.gdbinit' in your project directory or starting GDB using 'gdb -x
+filename'.
+
+21.4 Programming using GDB
+==========================
+
+By default the target memory map is sent to GDB. This can be disabled by
+the following OpenOCD configuration option:
+     gdb memory_map disable
+For this to function correctly a valid flash configuration must also be
+set in OpenOCD. For faster performance you should also configure a valid
+working area.
+
+Informing GDB of the memory map of the target will enable GDB to protect
+any flash areas of the target and use hardware breakpoints by default.
+This means that the OpenOCD option 'gdb breakpoint_override' is not
+required when using a memory map.  *Note gdb breakpoint_override:
+gdbbreakpointoverride.
+
+To view the configured memory map in GDB, use the GDB command 'info
+mem'.  All other unassigned addresses within GDB are treated as RAM.
+
+GDB 6.8 and higher set any memory area not in the memory map as
+inaccessible.  This can be changed to the old behaviour by using the
+following GDB command
+     set mem inaccessible-by-default off
+
+If 'gdb flash_program enable' is also used, GDB will be able to program
+any flash memory using the vFlash interface.
+
+GDB will look at the target memory map when a load command is given, if
+any areas to be programmed lie within the target flash area the vFlash
+packets will be used.
+
+If the target needs configuring before GDB programming, set target event
+gdb-flash-erase-start:
+     $_TARGETNAME configure -event gdb-flash-erase-start BODY
+*Note Target Events: targetevents, for other GDB programming related
+events.
+
+To verify any flash programming the GDB command 'compare-sections' can
+be used.
+
+21.5 Using GDB as a non-intrusive memory inspector
+==================================================
+
+If your project controls more than a blinking LED, let's say a heavy
+industrial robot or an experimental nuclear reactor, stopping the
+controlling process just because you want to attach GDB is not a good
+option.
+
+OpenOCD does not support GDB non-stop mode (might be implemented in the
+future).  Though there is a possible setup where the target does not get
+stopped and GDB treats it as it were running.  If the target supports
+background access to memory while it is running, you can use GDB in this
+mode to inspect memory (mainly global variables) without any intrusion
+of the target process.
+
+Remove default setting of gdb-attach event.  *Note Target Events:
+targetevents.  Place following command after target configuration:
+     $_TARGETNAME configure -event gdb-attach {}
+
+If any of installed flash banks does not support probe on running
+target, switch off gdb memory_map:
+     gdb memory_map disable
+
+Ensure GDB is configured without interrupt-on-connect.  Some GDB
+versions set it by default, some does not.
+     set remote interrupt-on-connect off
+
+If you switched gdb memory_map off, you may want to setup GDB memory map
+manually or issue 'set mem inaccessible-by-default off'
+
+Now you can issue GDB command 'target extended-remote ...' and inspect
+memory of a running target.  Do not use GDB commands 'continue', 'step'
+or 'next' as they synchronize GDB with your target and GDB would require
+stopping the target to get the prompt back.
+
+Do not use this mode under an IDE like Eclipse as it caches values of
+previously shown variables.
+
+It's also possible to connect more than one GDB to the same target by
+the target's configuration option '-gdb-max-connections'.  This allows,
+for example, one GDB to run a script that continuously polls a set of
+variables while other GDB can be used interactively.  Be extremely
+careful in this case, because the two GDB can easily get out-of-sync.
+
+21.6 RTOS Support
+=================
+
+OpenOCD includes RTOS support, this will however need enabling as it
+defaults to disabled.  It can be enabled by passing '-rtos' arg to the
+target.  *Note RTOS Type: rtostype.
+
+*Note Debugging Programs with Multiple Threads: (gdb)Threads, for
+details about relevant GDB commands.
+
+
+An example setup is below:
+
+     $_TARGETNAME configure -rtos auto
+
+This will attempt to auto detect the RTOS within your application.
+
+Currently supported rtos's include:
+   * 'eCos'
+   * 'ThreadX'
+   * 'FreeRTOS'
+   * 'linux'
+   * 'ChibiOS'
+   * 'embKernel'
+   * 'mqx'
+   * 'uCOS-III'
+   * 'nuttx'
+   * 'RIOT'
+   * 'hwthread' (This is not an actual RTOS. *Note Using OpenOCD SMP
+     with GDB: usingopenocdsmpwithgdb.)
+   * 'Zephyr'
+   * 'rtkernel'
+
+At any time, it's possible to drop the selected RTOS using:
+     $_TARGETNAME configure -rtos none
+
+Before an RTOS can be detected, it must export certain symbols;
+otherwise, it cannot be used by OpenOCD. Below is a list of the required
+symbols for each supported RTOS.
+
+'eCos symbols'
+     Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
+'ThreadX symbols'
+     _tx_thread_current_ptr, _tx_thread_created_ptr,
+     _tx_thread_created_count.
+'FreeRTOS symbols'
+     pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1,
+     xDelayedTaskList2, pxDelayedTaskList, pxOverflowDelayedTaskList,
+     xPendingReadyList, uxCurrentNumberOfTasks, uxTopUsedPriority,
+     xSchedulerRunning.
+'linux symbols'
+     init_task.
+'ChibiOS symbols'
+     rlist, ch_debug, chSysInit.
+'embKernel symbols'
+     Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
+     Rtos::sListSuspended, Rtos::sMaxPriorities,
+     Rtos::sCurrentTaskCount.
+'mqx symbols'
+     _mqx_kernel_data, MQX_init_struct.
+'uC/OS-III symbols'
+     OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty.
+'nuttx symbols'
+     g_readytorun, g_tasklisttable.
+'RIOT symbols'
+     sched_threads, sched_num_threads, sched_active_pid, max_threads,
+     _tcb_name_offset.
+'Zephyr symbols'
+     _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size
+'rtkernel symbols'
+     Multiple struct offsets.
+
+For most RTOS supported the above symbols will be exported by default.
+However for some, eg.  FreeRTOS, uC/OS-III and Zephyr, extra steps must
+be taken.
+
+Zephyr must be compiled with the DEBUG_THREAD_INFO option.  This will
+generate some symbols with information needed in order to build the list
+of threads.
+
+FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific
+file to be linked along with the project:
+
+'FreeRTOS'
+     contrib/rtos-helpers/FreeRTOS-openocd.c
+'uC/OS-III'
+     contrib/rtos-helpers/uCOS-III-openocd.c
+
+21.7 RTOS Commands
+==================
+
+ -- Config Command: freertos_ticktype_size (2|4|8)
+     Pass the size (in bytes) of FreeRTOS TickType_t to OpenOCD. To make
+     sure the calculation of offsets and sizes is correct.  Defaults to
+     4.
+
+21.8 Using OpenOCD SMP with GDB
+===============================
+
+OpenOCD includes a pseudo RTOS called _hwthread_ that presents CPU cores
+("hardware threads") in an SMP system as threads to GDB. With this
+extension, GDB can be used to inspect the state of an SMP system in a
+natural way.  After halting the system, using the GDB command 'info
+threads' will list the context of each active CPU core in the system.
+GDB's 'thread' command can be used to switch the view to a different CPU
+core.  The 'step' and 'stepi' commands can be used to step a specific
+core while other cores are free-running or remain halted, depending on
+the scheduler-locking mode configured in GDB.
+
+
+File: openocd.info,  Node: Tcl Scripting API,  Next: FAQ,  Prev: GDB and OpenOCD,  Up: Top
+
+22 Tcl Scripting API
+********************
+
+22.1 API rules
+==============
+
+Tcl commands are stateless; e.g.  the 'telnet' command has a concept of
+currently active target, the Tcl API proc's take this sort of state
+information as an argument to each proc.
+
+There are three main types of return values: single value, name value
+pair list and lists.
+
+Name value pair.  The proc 'foo' below returns a name/value pair list.
+
+     >  set foo(me)  Duane
+     >  set foo(you) Oyvind
+     >  set foo(mouse) Micky
+     >  set foo(duck) Donald
+
+If one does this:
+
+     >  set foo
+
+The result is:
+
+     me Duane you Oyvind mouse Micky duck Donald
+
+Thus, to get the names of the associative array is easy:
+
+foreach { name value } [set foo] {
+        puts "Name: $name, Value: $value"
+}
+
+Lists returned should be relatively small.  Otherwise, a range should be
+passed in to the proc in question.
+
+22.2 Internal low-level Commands
+================================
+
+By "low-level", we mean commands that a human would typically not invoke
+directly.
+
+   * flash banks     
+      ['driver options' ...]
+
+     Return information about the flash banks
+
+   * capture 
+
+     Run  and return full log output that was produced during
+     its execution together with the command output.  Example:
+
+          > capture "reset init"
+
+OpenOCD commands can consist of two words, e.g.  "flash banks".  The
+'startup.tcl' "unknown" proc will translate this into a Tcl proc called
+"flash_banks".
+
+22.3 Tcl RPC server
+===================
+
+OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
+commands and receive the results.
+
+To access it, your application needs to connect to a configured TCP port
+(see 'tcl port').  Then it can pass any string to the interpreter
+terminating it with '0x1a' and wait for the return value (it will be
+terminated with '0x1a' as well).  This can be repeated as many times as
+desired without reopening the connection.
+
+It is not needed anymore to prefix the OpenOCD commands with 'ocd_' to
+get the results back.  But sometimes you might need the 'capture'
+command.
+
+See 'contrib/rpc_examples/' for specific client implementations.
+
+22.4 Tcl RPC server notifications
+=================================
+
+Notifications are sent asynchronously to other commands being executed
+over the RPC server, so the port must be polled continuously.
+
+Target event, state and reset notifications are emitted as Tcl
+associative arrays in the following format.
+
+type target_event event [event-name]
+type target_state state [state-name]
+type target_reset mode [reset-mode]
+
+ -- Command: tcl notifications [on/off]
+     Toggle output of target notifications to the current Tcl RPC
+     server.  Only available from the Tcl RPC server.  Defaults to off.
+
+22.5 Tcl RPC server trace output
+================================
+
+Trace data is sent asynchronously to other commands being executed over
+the RPC server, so the port must be polled continuously.
+
+Target trace data is emitted as a Tcl associative array in the following
+format.
+
+type target_trace data [trace-data-hex-encoded]
+
+ -- Command: tcl trace [on/off]
+     Toggle output of target trace data to the current Tcl RPC server.
+     Only available from the Tcl RPC server.  Defaults to off.
+
+     See an example application here:
+      [OpenOcdTraceUtil]
+
+
+File: openocd.info,  Node: FAQ,  Next: Tcl Crash Course,  Prev: Tcl Scripting API,  Up: Top
+
+23 FAQ
+******
+
+  1. RTCK, also known as: Adaptive Clocking - What is it?
+
+     In digital circuit design it is often referred to as "clock
+     synchronisation" the JTAG interface uses one clock (TCK or TCLK)
+     operating at some speed, your CPU target is operating at another.
+     The two clocks are not synchronised, they are "asynchronous"
+
+     In order for the two to work together they must be synchronised
+     well enough to work; JTAG can't go ten times faster than the CPU,
+     for example.  There are 2 basic options:
+       1. Use a special "adaptive clocking" circuit to change the JTAG
+          clock rate to match what the CPU currently supports.
+       2. The JTAG clock must be fixed at some speed that's enough
+          slower than the CPU clock that all TMS and TDI transitions can
+          be detected.
+
+     Does this really matter?  For some chips and some situations, this
+     is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link; the
+     CPU has no difficulty keeping up with JTAG. Startup sequences are
+     often problematic though, as are other situations where the CPU
+     clock rate changes (perhaps to save power).
+
+     For example, Atmel AT91SAM chips start operation from reset with a
+     32kHz system clock.  Boot firmware may activate the main oscillator
+     and PLL before switching to a faster clock (perhaps that 500 MHz
+     ARM926 scenario).  If you're using JTAG to debug that startup
+     sequence, you must slow the JTAG clock to sometimes 1 to 4kHz.
+     After startup completes, JTAG can use a faster clock.
+
+     Consider also debugging a 500MHz ARM926 hand held battery powered
+     device that enters a low power "deep sleep" mode, at 32kHz CPU
+     clock, between keystrokes unless it has work to do.  When would
+     that 5 MHz JTAG clock be usable?
+
+     Solution #1 - A special circuit
+
+     In order to make use of this, your CPU, board, and JTAG adapter
+     must all support the RTCK feature.  Not all of them support this;
+     keep reading!
+
+     The RTCK ("Return TCK") signal in some ARM chips is used to help
+     with this problem.  ARM has a good description of the problem
+     described at this link:
+      [checked
+     28/nov/2008].  Link title: "How does the JTAG synchronisation logic
+     work?  / how does adaptive clocking work?".
+
+     The nice thing about adaptive clocking is that "battery powered
+     hand held device example" - the adaptiveness works perfectly all
+     the time.  One can set a break point or halt the system in the deep
+     power down code, slow step out until the system speeds up.
+
+     Note that adaptive clocking may also need to work at the board
+     level, when a board-level scan chain has multiple chips.  Parallel
+     clock voting schemes are good way to implement this, both within
+     and between chips, and can easily be implemented with a CPLD. It's
+     not difficult to have logic fan a module's input TCK signal out to
+     each TAP in the scan chain, and then wait until each TAP's RTCK
+     comes back with the right polarity before changing the output RTCK
+     signal.  Texas Instruments makes some clock voting logic available
+     for free (with no support) in VHDL form; see
+     
+
+     Solution #2 - Always works - but may be slower
+
+     Often this is a perfectly acceptable solution.
+
+     In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
+     the target clock speed.  But what that "magic division" is varies
+     depending on the chips on your board.  ARM rule of thumb Most ARM
+     based systems require an 6:1 division; ARM11 cores use an 8:1
+     division.  Xilinx rule of thumb is 1/12 the clock speed.
+
+     Note: most full speed FT2232 based JTAG adapters are limited to a
+     maximum of 6MHz.  The ones using USB high speed chips (FT2232H)
+     often support faster clock rates (and adaptive clocking).
+
+     You can still debug the 'low power' situations - you just need to
+     either use a fixed and very slow JTAG clock rate ...  or else
+     manually adjust the clock speed at every step.  (Adjusting is
+     painful and tedious, and is not always practical.)
+
+     It is however easy to "code your way around it" - i.e.: Cheat a
+     little, have a special debug mode in your application that does a
+     "high power sleep".  If you are careful - 98% of your problems can
+     be debugged this way.
+
+     Note that on ARM you may need to avoid using the _wait for
+     interrupt_ operation in your idle loops even if you don't otherwise
+     change the CPU clock rate.  That operation gates the CPU clock, and
+     thus the JTAG clock; which prevents JTAG access.  One consequence
+     is not being able to 'halt' cores which are executing that _wait
+     for interrupt_ operation.
+
+     To set the JTAG frequency use the command:
+
+          # Example: 1.234MHz
+          adapter speed 1234
+
+  2. Win32 Pathnames Why don't backslashes work in Windows paths?
+
+     OpenOCD uses Tcl and a backslash is an escape char.  Use { and }
+     around Windows filenames.
+
+          > echo \a
+
+          > echo {\a}
+          \a
+          > echo "\a"
+
+          >
+
+  3. Missing: cygwin1.dll OpenOCD complains about a missing cygwin1.dll.
+
+     Make sure you have Cygwin installed, or at least a version of
+     OpenOCD that claims to come with all the necessary DLLs.  When
+     using Cygwin, try launching OpenOCD from the Cygwin shell.
+
+  4. Breakpoint Issue I'm trying to set a breakpoint using GDB (or a
+     front-end like Insight or Eclipse), but OpenOCD complains that
+     "Info: arm7_9_common.c:213 arm7_9_add_breakpoint(): sw breakpoint
+     requested, but software breakpoints not enabled".
+
+     GDB issues software breakpoints when a normal breakpoint is
+     requested, or to implement source-line single-stepping.  On ARMv4T
+     systems, like ARM7TDMI, ARM720T or ARM920T, software breakpoints
+     consume one of the two available hardware breakpoints.
+
+  5. LPC2000 Flash When erasing or writing LPC2000 on-chip flash, the
+     operation fails at random.
+
+     Make sure the core frequency specified in the 'flash lpc2000' line
+     matches the clock at the time you're programming the flash.  If
+     you've specified the crystal's frequency, make sure the PLL is
+     disabled.  If you've specified the full core speed (e.g.  60MHz),
+     make sure the PLL is enabled.
+
+  6. Amontec Chameleon When debugging using an Amontec Chameleon in its
+     JTAG Accelerator configuration, I keep getting "Error:
+     amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed out
+     while waiting for end of scan, rtck was disabled".
+
+     Make sure your PC's parallel port operates in EPP mode.  You might
+     have to try several settings in your PC BIOS (ECP, EPP, and
+     different versions of those).
+
+  7. Data Aborts When debugging with OpenOCD and GDB (plain GDB,
+     Insight, or Eclipse), I get lots of "Error: arm7_9_common.c:1771
+     arm7_9_read_memory(): memory read caused data abort".
+
+     The errors are non-fatal, and are the result of GDB trying to trace
+     stack frames beyond the last valid frame.  It might be possible to
+     prevent this by setting up a proper "initial" stack frame, if you
+     happen to know what exactly has to be done, feel free to add this
+     here.
+
+     Simple: In your startup code - push 8 registers of zeros onto the
+     stack before calling main().  What GDB is doing is "climbing" the
+     run time stack by reading various values on the stack using the
+     standard call frame for the target.  GDB keeps going - until one of
+     2 things happen #1 an invalid frame is found, or #2 some huge
+     number of stackframes have been processed.  By pushing zeros on the
+     stack, GDB gracefully stops.
+
+     Debugging Interrupt Service Routines - In your ISR before you call
+     your C code, do the same - artificially push some zeros onto the
+     stack, remember to pop them off when the ISR is done.
+
+     Also note: If you have a multi-threaded operating system, they
+     often do not in the interest of saving memory waste these few
+     bytes.  Painful...
+
+  8. JTAG Reset Config I get the following message in the OpenOCD
+     console (or log file): "Warning: arm7_9_common.c:679
+     arm7_9_assert_reset(): srst resets test logic, too".
+
+     This warning doesn't indicate any serious problem, as long as you
+     don't want to debug your core right out of reset.  Your .cfg file
+     specified 'reset_config trst_and_srst srst_pulls_trst' to tell
+     OpenOCD that either your board, your debugger or your target uC
+     (e.g.  LPC2000) can't assert the two reset signals independently.
+     With this setup, it's not possible to halt the core right out of
+     reset, everything else should work fine.
+
+  9. USB Power When using OpenOCD in conjunction with Amontec JTAGkey
+     and the Yagarto toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the
+     debugging seems to be unstable.  When single-stepping over large
+     blocks of code, GDB and OpenOCD quit with an error message.  Is
+     there a stability issue with OpenOCD?
+
+     No, this is not a stability issue concerning OpenOCD. Most users
+     have solved this issue by simply using a self-powered USB hub,
+     which they connect their Amontec JTAGkey to.  Apparently, some
+     computers do not provide a USB power supply stable enough for the
+     Amontec JTAGkey to be operated.
+
+     Laptops running on battery have this problem too...
+
+  10. GDB Disconnects When using the Amontec JTAGkey, sometimes OpenOCD
+     crashes with the following error message: "Error: gdb_server.c:101
+     gdb_get_char(): read: 10054".  What does that mean and what might
+     be the reason for this?
+
+     Error code 10054 corresponds to WSAECONNRESET, which means that the
+     debugger (GDB) has closed the connection to OpenOCD. This might be
+     a GDB issue.
+
+  11. LPC2000 Flash In the configuration file in the section where flash
+     device configurations are described, there is a parameter for
+     specifying the clock frequency for LPC2000 internal flash devices
+     (e.g.  'flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME
+     lpc2000_v1 14746 calc_checksum'), which must be specified in
+     kilohertz.  However, I do have a quartz crystal of a frequency that
+     contains fractions of kilohertz (e.g.  14,745,600 Hz, i.e.
+     14,745.600 kHz).  Is it possible to specify real numbers for the
+     clock frequency?
+
+     No.  The clock frequency specified here must be given as an
+     integral number.  However, this clock frequency is used by the
+     In-Application-Programming (IAP) routines of the LPC2000 family
+     only, which seems to be very tolerant concerning the given clock
+     frequency, so a slight difference between the specified clock
+     frequency and the actual clock frequency will not cause any
+     trouble.
+
+  12. Command Order Do I have to keep a specific order for the commands
+     in the configuration file?
+
+     Well, yes and no.  Commands can be given in arbitrary order, yet
+     the devices listed for the JTAG scan chain must be given in the
+     right order (jtag newdevice), with the device closest to the
+     TDO-Pin being listed first.  In general, whenever objects of the
+     same type exist which require an index number, then these objects
+     must be given in the right order (jtag newtap, targets and flash
+     banks - a target references a jtag newtap and a flash bank
+     references a target).
+
+     You can use the "scan_chain" command to verify and display the tap
+     order.
+
+     Also, some commands can't execute until after 'init' has been
+     processed.  Such commands include 'nand probe' and everything else
+     that needs to write to controller registers, perhaps for setting up
+     DRAM and loading it with code.
+
+  13. JTAG TAP Order Do I have to declare the TAPS in some particular
+     order?
+
+     Yes; whenever you have more than one, you must declare them in the
+     same order used by the hardware.
+
+     Many newer devices have multiple JTAG TAPs.  For example:
+     STMicroelectronics STM32 chips have two TAPs, a "boundary scan TAP"
+     and "Cortex-M3" TAP. Example: The STM32 reference manual, Document
+     ID: RM0008, Section 26.5, Figure 259, page 651/681, the "TDI" pin
+     is connected to the boundary scan TAP, which then connects to the
+     Cortex-M3 TAP, which then connects to the TDO pin.
+
+     Thus, the proper order for the STM32 chip is: (1) The Cortex-M3,
+     then (2) The boundary scan TAP. If your board includes an
+     additional JTAG chip in the scan chain (for example a Xilinx CPLD
+     or FPGA) you could place it before or after the STM32 chip in the
+     chain.  For example:
+
+        * OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
+        * STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
+        * STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
+        * STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
+        * Xilinx TDO Pin -> OpenOCD TDO (input)
+
+     The "jtag device" commands would thus be in the order shown below.
+     Note:
+
+        * jtag newtap Xilinx tap -irlen ...
+        * jtag newtap stm32 cpu -irlen ...
+        * jtag newtap stm32 bs -irlen ...
+        * # Create the debug target and say where it is
+        * target create stm32.cpu -chain-position stm32.cpu ...
+
+  14. SYSCOMP Sometimes my debugging session terminates with an error.
+     When I look into the log file, I can see these error messages:
+     Error: arm7_9_common.c:561 arm7_9_execute_sys_speed(): timeout
+     waiting for SYSCOMP
+
+     TODO.
+
+
+File: openocd.info,  Node: Tcl Crash Course,  Next: License,  Prev: FAQ,  Up: Top
+
+24 Tcl Crash Course
+*******************
+
+Not everyone knows Tcl - this is not intended to be a replacement for
+learning Tcl, the intent of this chapter is to give you some idea of how
+the Tcl scripts work.
+
+This chapter is written with two audiences in mind.  (1) OpenOCD users
+who need to understand a bit more of how Jim-Tcl works so they can do
+something useful, and (2) those that want to add a new command to
+OpenOCD.
+
+24.1 Tcl Rule #1
+================
+
+There is a famous joke, it goes like this:
+  1. Rule #1: The wife is always correct
+  2. Rule #2: If you think otherwise, See Rule #1
+
+The Tcl equal is this:
+
+  1. Rule #1: Everything is a string
+  2. Rule #2: If you think otherwise, See Rule #1
+
+As in the famous joke, the consequences of Rule #1 are profound.  Once
+you understand Rule #1, you will understand Tcl.
+
+24.2 Tcl Rule #1b
+=================
+
+There is a second pair of rules.
+  1. Rule #1: Control flow does not exist.  Only commands
+     For example: the classic FOR loop or IF statement is not a control
+     flow item, they are commands, there is no such thing as control
+     flow in Tcl.
+  2. Rule #2: If you think otherwise, See Rule #1
+     Actually what happens is this: There are commands that by
+     convention, act like control flow key words in other languages.
+     One of those commands is the word "for", another command is "if".
+
+24.3 Per Rule #1 - All Results are strings
+==========================================
+
+Every Tcl command results in a string.  The word "result" is used
+deliberately.  No result is just an empty string.  Remember: Rule #1 -
+Everything is a string
+
+24.4 Tcl Quoting Operators
+==========================
+
+In life of a Tcl script, there are two important periods of time, the
+difference is subtle.
+  1. Parse Time
+  2. Evaluation Time
+
+The two key items here are how "quoted things" work in Tcl.  Tcl has
+three primary quoting constructs, the [square-brackets] the
+{curly-braces} and "double-quotes"
+
+By now you should know $VARIABLES always start with a $DOLLAR sign.
+BTW: To set a variable, you actually use the command "set", as in "set
+VARNAME VALUE" much like the ancient BASIC language "let x = 1"
+statement, but without the equal sign.
+
+   * [square-brackets]
+     [square-brackets] are command substitutions.  It operates much like
+     Unix Shell 'back-ticks'.  The result of a [square-bracket]
+     operation is exactly 1 string.  Remember Rule #1 - Everything is a
+     string.  These two statements are roughly identical:
+              # bash example
+              X=`date`
+              echo "The Date is: $X"
+              # Tcl example
+              set X [date]
+              puts "The Date is: $X"
+   * "double-quoted-things"
+     "double-quoted-things" are just simply quoted text.  $VARIABLES and
+     [square-brackets] are expanded in place - the result however is
+     exactly 1 string.  Remember Rule #1 - Everything is a string
+              set x "Dinner"
+              puts "It is now \"[date]\", $x is in 1 hour"
+   * {Curly-Braces}
+     {Curly-Braces} are magic: $VARIABLES and [square-brackets] are
+     parsed, but are NOT expanded or executed.  {Curly-Braces} are like
+     'single-quote' operators in BASH shell scripts, with the added
+     feature: {curly-braces} can be nested, single quotes can not.
+     {{{this is nested 3 times}}} NOTE: [date] is a bad example; at this
+     writing, Jim/OpenOCD does not have a date command.
+
+24.5 Consequences of Rule 1/2/3/4
+=================================
+
+The consequences of Rule 1 are profound.
+
+24.5.1 Tokenisation & Execution.
+--------------------------------
+
+Of course, whitespace, blank lines and #comment lines are handled in the
+normal way.
+
+As a script is parsed, each (multi) line in the script file is tokenised
+and according to the quoting rules.  After tokenisation, that line is
+immediately executed.
+
+Multi line statements end with one or more "still-open" {curly-braces}
+which - eventually - closes a few lines later.
+
+24.5.2 Command Execution
+------------------------
+
+Remember earlier: There are no "control flow" statements in Tcl.
+Instead there are COMMANDS that simply act like control flow operators.
+
+Commands are executed like this:
+
+  1. Parse the next line into (argc) and (argv[]).
+  2. Look up (argv[0]) in a table and call its function.
+  3. Repeat until End Of File.
+
+It sort of works like this:
+         for(;;){
+             ReadAndParse( &argc, &argv );
+
+             cmdPtr = LookupCommand( argv[0] );
+
+             (*cmdPtr->Execute)( argc, argv );
+         }
+
+When the command "proc" is parsed (which creates a procedure function)
+it gets 3 parameters on the command line.  1 the name of the proc
+(function), 2 the list of parameters, and 3 the body of the function.
+Note the choice of words: LIST and BODY. The PROC command stores these
+items in a table somewhere so it can be found by "LookupCommand()"
+
+24.5.3 The FOR command
+----------------------
+
+The most interesting command to look at is the FOR command.  In Tcl, the
+FOR command is normally implemented in C. Remember, FOR is a command
+just like any other command.
+
+When the ascii text containing the FOR command is parsed, the parser
+produces 5 parameter strings, (If in doubt: Refer to Rule #1) they are:
+
+  0. The ascii text 'for'
+  1. The start text
+  2. The test expression
+  3. The next text
+  4. The body text
+
+Sort of reminds you of "main( int argc, char **argv )" does it not?
+Remember Rule #1 - Everything is a string.  The key point is this: Often
+many of those parameters are in {curly-braces} - thus the variables
+inside are not expanded or replaced until later.
+
+Remember that every Tcl command looks like the classic "main( argc, argv
+)" function in C. In JimTCL - they actually look like this:
+
+     int
+     MyCommand( Jim_Interp *interp,
+                int *argc,
+                Jim_Obj * const *argvs );
+
+Real Tcl is nearly identical.  Although the newer versions have
+introduced a byte-code parser and interpreter, but at the core, it still
+operates in the same basic way.
+
+24.5.4 FOR command implementation
+---------------------------------
+
+To understand Tcl it is perhaps most helpful to see the FOR command.
+Remember, it is a COMMAND not a control flow structure.
+
+In Tcl there are two underlying C helper functions.
+
+Remember Rule #1 - You are a string.
+
+The first helper parses and executes commands found in an ascii string.
+Commands can be separated by semicolons, or newlines.  While parsing,
+variables are expanded via the quoting rules.
+
+The second helper evaluates an ascii string as a numerical expression
+and returns a value.
+
+Here is an example of how the FOR command could be implemented.  The
+pseudo code below does not show error handling.
+     void Execute_AsciiString( void *interp, const char *string );
+
+     int Evaluate_AsciiExpression( void *interp, const char *string );
+
+     int
+     MyForCommand( void *interp,
+                   int argc,
+                   char **argv )
+     {
+        if( argc != 5 ){
+            SetResult( interp, "WRONG number of parameters");
+            return ERROR;
+        }
+
+        // argv[0] = the ascii string just like C
+
+        // Execute the start statement.
+        Execute_AsciiString( interp, argv[1] );
+
+        // Top of loop test
+        for(;;){
+             i = Evaluate_AsciiExpression(interp, argv[2]);
+             if( i == 0 )
+                 break;
+
+             // Execute the body
+             Execute_AsciiString( interp, argv[3] );
+
+             // Execute the LOOP part
+             Execute_AsciiString( interp, argv[4] );
+         }
+
+         // Return no error
+         SetResult( interp, "" );
+         return SUCCESS;
+     }
+
+Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works in
+the same basic way.
+
+24.6 OpenOCD Tcl Usage
+======================
+
+24.6.1 source and find commands
+-------------------------------
+
+Where: In many configuration files
+Example: source [find FILENAME]
+Remember the parsing rules
+  1. The 'find' command is in square brackets, and is executed with the
+     parameter FILENAME. It should find and return the full path to a
+     file with that name; it uses an internal search path.  The RESULT
+     is a string, which is substituted into the command line in place of
+     the bracketed 'find' command.  (Don't try to use a FILENAME which
+     includes the "#" character.  That character begins Tcl comments.)
+  2. The 'source' command is executed with the resulting filename; it
+     reads a file and executes as a script.
+
+24.6.2 format command
+---------------------
+
+Where: Generally occurs in numerous places.
+Tcl has no command like printf(), instead it has format, which is really
+more like sprintf().  Example
+         set x 6
+         set y 7
+         puts [format "The answer: %d" [expr {$x * $y}]]
+  1. The SET command creates 2 variables, X and Y.
+  2. The double [nested] EXPR command performs math
+     The EXPR command produces numerical result as a string.
+     Refer to Rule #1
+  3. The format command is executed, producing a single string
+     Refer to Rule #1.
+  4. The PUTS command outputs the text.
+
+24.6.3 Body or Inlined Text
+---------------------------
+
+Where: Various TARGET scripts.
+     #1 Good
+        proc someproc {} {
+            ... multiple lines of stuff ...
+        }
+        $_TARGETNAME configure -event FOO someproc
+     #2 Good - no variables
+        $_TARGETNAME configure -event foo "this ; that;"
+     #3 Good Curly Braces
+        $_TARGETNAME configure -event FOO {
+             puts "Time: [date]"
+        }
+     #4 DANGER DANGER DANGER
+        $_TARGETNAME configure -event foo "puts \"Time: [date]\""
+  1. The $_TARGETNAME is an OpenOCD variable convention.
+     $_TARGETNAME represents the last target created, the value changes
+     each time a new target is created.  Remember the parsing rules.
+     When the ascii text is parsed, the $_TARGETNAME becomes a simple
+     string, the name of the target which happens to be a TARGET
+     (object) command.
+  2. The 2nd parameter to the '-event' parameter is a TCBODY
+     There are 4 examples:
+       1. The TCLBODY is a simple string that happens to be a proc name
+       2. The TCLBODY is several simple commands separated by semicolons
+       3. The TCLBODY is a multi-line {curly-brace} quoted string
+       4. The TCLBODY is a string with variables that get expanded.
+
+     In the end, when the target event FOO occurs the TCLBODY is
+     evaluated.  Method #1 and #2 are functionally identical.  For
+     Method #3 and #4 it is more interesting.  What is the TCLBODY?
+
+     Remember the parsing rules.  In case #3, {curly-braces} mean the
+     $VARS and [square-brackets] are expanded later, when the EVENT
+     occurs, and the text is evaluated.  In case #4, they are replaced
+     before the "Target Object Command" is executed.  This occurs at the
+     same time $_TARGETNAME is replaced.  In case #4 the date will never
+     change.  {BTW: [date] is a bad example; at this writing,
+     Jim/OpenOCD does not have a date command}
+
+24.6.4 Global Variables
+-----------------------
+
+Where: You might discover this when writing your own procs
+In simple terms: Inside a PROC, if you need to access a global variable
+you must say so.  See also "upvar".  Example:
+     proc myproc { } {
+          set y 0 #Local variable Y
+          global x #Global variable X
+          puts [format "X=%d, Y=%d" $x $y]
+     }
+
+24.7 Other Tcl Hacks
+====================
+
+Dynamic variable creation
+     # Dynamically create a bunch of variables.
+     for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} {
+         # Create var name
+         set vn [format "BIT%d" $x]
+         # Make it a global
+         global $vn
+         # Set it.
+         set $vn [expr {1 << $x}]
+     }
+Dynamic proc/command creation
+     # One "X" function - 5 uart functions.
+     foreach who {A B C D E}
+        proc [format "show_uart%c" $who] { } "show_UARTx $who"
+     }
+
+
+File: openocd.info,  Node: License,  Next: OpenOCD Concept Index,  Prev: Tcl Crash Course,  Up: Top
+
+Appendix A The GNU Free Documentation License.
+**********************************************
+
+                      Version 1.2, November 2002
+
+     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
+     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
+
+     Everyone is permitted to copy and distribute verbatim copies
+     of this license document, but changing it is not allowed.
+
+  0. PREAMBLE
+
+     The purpose of this License is to make a manual, textbook, or other
+     functional and useful document "free" in the sense of freedom: to
+     assure everyone the effective freedom to copy and redistribute it,
+     with or without modifying it, either commercially or
+     noncommercially.  Secondarily, this License preserves for the
+     author and publisher a way to get credit for their work, while not
+     being considered responsible for modifications made by others.
+
+     This License is a kind of "copyleft", which means that derivative
+     works of the document must themselves be free in the same sense.
+     It complements the GNU General Public License, which is a copyleft
+     license designed for free software.
+
+     We have designed this License in order to use it for manuals for
+     free software, because free software needs free documentation: a
+     free program should come with manuals providing the same freedoms
+     that the software does.  But this License is not limited to
+     software manuals; it can be used for any textual work, regardless
+     of subject matter or whether it is published as a printed book.  We
+     recommend this License principally for works whose purpose is
+     instruction or reference.
+
+  1. APPLICABILITY AND DEFINITIONS
+
+     This License applies to any manual or other work, in any medium,
+     that contains a notice placed by the copyright holder saying it can
+     be distributed under the terms of this License.  Such a notice
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+     to use that work under the conditions stated herein.  The
+     "Document", below, refers to any such manual or work.  Any member
+     of the public is a licensee, and is addressed as "you".  You accept
+     the license if you copy, modify or distribute the work in a way
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+
+     A "Modified Version" of the Document means any work containing the
+     Document or a portion of it, either copied verbatim, or with
+     modifications and/or translated into another language.
+
+     A "Secondary Section" is a named appendix or a front-matter section
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+     The "Invariant Sections" are certain Secondary Sections whose
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+     is not allowed to be designated as Invariant.  The Document may
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+
+     The "Cover Texts" are certain short passages of text that are
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+
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+
+     The "Title Page" means, for a printed book, the title page itself,
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+     works in formats which do not have any title page as such, "Title
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+
+     A section "Entitled XYZ" means a named subunit of the Document
+     whose title either is precisely XYZ or contains XYZ in parentheses
+     following text that translates XYZ in another language.  (Here XYZ
+     stands for a specific section name mentioned below, such as
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+
+     The Document may include Warranty Disclaimers next to the notice
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+     this License, but only as regards disclaiming warranties: any other
+     implication that these Warranty Disclaimers may have is void and
+     has no effect on the meaning of this License.
+
+  2. VERBATIM COPYING
+
+     You may copy and distribute the Document in any medium, either
+     commercially or noncommercially, provided that this License, the
+     copyright notices, and the license notice saying this License
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+     you may accept compensation in exchange for copies.  If you
+     distribute a large enough number of copies you must also follow the
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+
+     You may also lend copies, under the same conditions stated above,
+     and you may publicly display copies.
+
+  3. COPYING IN QUANTITY
+
+     If you publish printed copies (or copies in media that commonly
+     have printed covers) of the Document, numbering more than 100, and
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+
+     If the required texts for either cover are too voluminous to fit
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+     adjacent pages.
+
+     If you publish or distribute Opaque copies of the Document
+     numbering more than 100, you must either include a machine-readable
+     Transparent copy along with each Opaque copy, or state in or with
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+     year after the last time you distribute an Opaque copy (directly or
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+
+     It is requested, but not required, that you contact the authors of
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+     to give them a chance to provide you with an updated version of the
+     Document.
+
+  4. MODIFICATIONS
+
+     You may copy and distribute a Modified Version of the Document
+     under the conditions of sections 2 and 3 above, provided that you
+     release the Modified Version under precisely this License, with the
+     Modified Version filling the role of the Document, thus licensing
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+     possesses a copy of it.  In addition, you must do these things in
+     the Modified Version:
+
+       A. Use in the Title Page (and on the covers, if any) a title
+          distinct from that of the Document, and from those of previous
+          versions (which should, if there were any, be listed in the
+          History section of the Document).  You may use the same title
+          as a previous version if the original publisher of that
+          version gives permission.
+
+       B. List on the Title Page, as authors, one or more persons or
+          entities responsible for authorship of the modifications in
+          the Modified Version, together with at least five of the
+          principal authors of the Document (all of its principal
+          authors, if it has fewer than five), unless they release you
+          from this requirement.
+
+       C. State on the Title page the name of the publisher of the
+          Modified Version, as the publisher.
+
+       D. Preserve all the copyright notices of the Document.
+
+       E. Add an appropriate copyright notice for your modifications
+          adjacent to the other copyright notices.
+
+       F. Include, immediately after the copyright notices, a license
+          notice giving the public permission to use the Modified
+          Version under the terms of this License, in the form shown in
+          the Addendum below.
+
+       G. Preserve in that license notice the full lists of Invariant
+          Sections and required Cover Texts given in the Document's
+          license notice.
+
+       H. Include an unaltered copy of this License.
+
+       I. Preserve the section Entitled "History", Preserve its Title,
+          and add to it an item stating at least the title, year, new
+          authors, and publisher of the Modified Version as given on the
+          Title Page.  If there is no section Entitled "History" in the
+          Document, create one stating the title, year, authors, and
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+          previous sentence.
+
+       J. Preserve the network location, if any, given in the Document
+          for public access to a Transparent copy of the Document, and
+          likewise the network locations given in the Document for
+          previous versions it was based on.  These may be placed in the
+          "History" section.  You may omit a network location for a work
+          that was published at least four years before the Document
+          itself, or if the original publisher of the version it refers
+          to gives permission.
+
+       K. For any section Entitled "Acknowledgements" or "Dedications",
+          Preserve the Title of the section, and preserve in the section
+          all the substance and tone of each of the contributor
+          acknowledgements and/or dedications given therein.
+
+       L. Preserve all the Invariant Sections of the Document, unaltered
+          in their text and in their titles.  Section numbers or the
+          equivalent are not considered part of the section titles.
+
+       M. Delete any section Entitled "Endorsements".  Such a section
+          may not be included in the Modified Version.
+
+       N. Do not retitle any existing section to be Entitled
+          "Endorsements" or to conflict in title with any Invariant
+          Section.
+
+       O. Preserve any Warranty Disclaimers.
+
+     If the Modified Version includes new front-matter sections or
+     appendices that qualify as Secondary Sections and contain no
+     material copied from the Document, you may at your option designate
+     some or all of these sections as invariant.  To do this, add their
+     titles to the list of Invariant Sections in the Modified Version's
+     license notice.  These titles must be distinct from any other
+     section titles.
+
+     You may add a section Entitled "Endorsements", provided it contains
+     nothing but endorsements of your Modified Version by various
+     parties--for example, statements of peer review or that the text
+     has been approved by an organization as the authoritative
+     definition of a standard.
+
+     You may add a passage of up to five words as a Front-Cover Text,
+     and a passage of up to 25 words as a Back-Cover Text, to the end of
+     the list of Cover Texts in the Modified Version.  Only one passage
+     of Front-Cover Text and one of Back-Cover Text may be added by (or
+     through arrangements made by) any one entity.  If the Document
+     already includes a cover text for the same cover, previously added
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+     one, on explicit permission from the previous publisher that added
+     the old one.
+
+     The author(s) and publisher(s) of the Document do not by this
+     License give permission to use their names for publicity for or to
+     assert or imply endorsement of any Modified Version.
+
+  5. COMBINING DOCUMENTS
+
+     You may combine the Document with other documents released under
+     this License, under the terms defined in section 4 above for
+     modified versions, provided that you include in the combination all
+     of the Invariant Sections of all of the original documents,
+     unmodified, and list them all as Invariant Sections of your
+     combined work in its license notice, and that you preserve all
+     their Warranty Disclaimers.
+
+     The combined work need only contain one copy of this License, and
+     multiple identical Invariant Sections may be replaced with a single
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+     by adding at the end of it, in parentheses, the name of the
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+     the list of Invariant Sections in the license notice of the
+     combined work.
+
+     In the combination, you must combine any sections Entitled
+     "History" in the various original documents, forming one section
+     Entitled "History"; likewise combine any sections Entitled
+     "Acknowledgements", and any sections Entitled "Dedications".  You
+     must delete all sections Entitled "Endorsements."
+
+  6. COLLECTIONS OF DOCUMENTS
+
+     You may make a collection consisting of the Document and other
+     documents released under this License, and replace the individual
+     copies of this License in the various documents with a single copy
+     that is included in the collection, provided that you follow the
+     rules of this License for verbatim copying of each of the documents
+     in all other respects.
+
+     You may extract a single document from such a collection, and
+     distribute it individually under this License, provided you insert
+     a copy of this License into the extracted document, and follow this
+     License in all other respects regarding verbatim copying of that
+     document.
+
+  7. AGGREGATION WITH INDEPENDENT WORKS
+
+     A compilation of the Document or its derivatives with other
+     separate and independent documents or works, in or on a volume of a
+     storage or distribution medium, is called an "aggregate" if the
+     copyright resulting from the compilation is not used to limit the
+     legal rights of the compilation's users beyond what the individual
+     works permit.  When the Document is included in an aggregate, this
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+     are not themselves derivative works of the Document.
+
+     If the Cover Text requirement of section 3 is applicable to these
+     copies of the Document, then if the Document is less than one half
+     of the entire aggregate, the Document's Cover Texts may be placed
+     on covers that bracket the Document within the aggregate, or the
+     electronic equivalent of covers if the Document is in electronic
+     form.  Otherwise they must appear on printed covers that bracket
+     the whole aggregate.
+
+  8. TRANSLATION
+
+     Translation is considered a kind of modification, so you may
+     distribute translations of the Document under the terms of section
+     4.  Replacing Invariant Sections with translations requires special
+     permission from their copyright holders, but you may include
+     translations of some or all Invariant Sections in addition to the
+     original versions of these Invariant Sections.  You may include a
+     translation of this License, and all the license notices in the
+     Document, and any Warranty Disclaimers, provided that you also
+     include the original English version of this License and the
+     original versions of those notices and disclaimers.  In case of a
+     disagreement between the translation and the original version of
+     this License or a notice or disclaimer, the original version will
+     prevail.
+
+     If a section in the Document is Entitled "Acknowledgements",
+     "Dedications", or "History", the requirement (section 4) to
+     Preserve its Title (section 1) will typically require changing the
+     actual title.
+
+  9. TERMINATION
+
+     You may not copy, modify, sublicense, or distribute the Document
+     except as expressly provided for under this License.  Any other
+     attempt to copy, modify, sublicense or distribute the Document is
+     void, and will automatically terminate your rights under this
+     License.  However, parties who have received copies, or rights,
+     from you under this License will not have their licenses terminated
+     so long as such parties remain in full compliance.
+
+  10. FUTURE REVISIONS OF THIS LICENSE
+
+     The Free Software Foundation may publish new, revised versions of
+     the GNU Free Documentation License from time to time.  Such new
+     versions will be similar in spirit to the present version, but may
+     differ in detail to address new problems or concerns.  See
+     .
+
+     Each version of the License is given a distinguishing version
+     number.  If the Document specifies that a particular numbered
+     version of this License "or any later version" applies to it, you
+     have the option of following the terms and conditions either of
+     that specified version or of any later version that has been
+     published (not as a draft) by the Free Software Foundation.  If the
+     Document does not specify a version number of this License, you may
+     choose any version ever published (not as a draft) by the Free
+     Software Foundation.
+
+ADDENDUM: How to use this License for your documents
+====================================================
+
+To use this License in a document you have written, include a copy of
+the License in the document and put the following copyright and license
+notices just after the title page:
+
+       Copyright (C)  YEAR  YOUR NAME.
+       Permission is granted to copy, distribute and/or modify this document
+       under the terms of the GNU Free Documentation License, Version 1.2
+       or any later version published by the Free Software Foundation;
+       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
+       Texts.  A copy of the license is included in the section entitled ``GNU
+       Free Documentation License''.
+
+If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
+replace the "with...Texts."  line with this:
+
+         with the Invariant Sections being LIST THEIR TITLES, with
+         the Front-Cover Texts being LIST, and with the Back-Cover Texts
+         being LIST.
+
+If you have Invariant Sections without Cover Texts, or some other
+combination of the three, merge those two alternatives to suit the
+situation.
+
+If your document contains nontrivial examples of program code, we
+recommend releasing these examples in parallel under your choice of free
+software license, such as the GNU General Public License, to permit
+their use in free software.
+
+
+File: openocd.info,  Node: OpenOCD Concept Index,  Next: Command and Driver Index,  Prev: License,  Up: Top
+
+OpenOCD Concept Index
+*********************
+
+[index]
+* Menu:
+
+* aarch64:                               Architecture and Core Commands.
+                                                             (line  966)
+* about:                                 About.              (line    6)
+* adaptive clocking:                     Debug Adapter Configuration.
+                                                             (line 1344)
+* adaptive clocking <1>:                 FAQ.                (line    6)
+* ambiqmicro:                            Flash Commands.     (line  666)
+* apollo:                                Flash Commands.     (line  666)
+* ARC:                                   Architecture and Core Commands.
+                                                             (line 1793)
+* Architecture Specific Commands:        Architecture and Core Commands.
+                                                             (line    6)
+* ARM:                                   Architecture and Core Commands.
+                                                             (line  273)
+* ARM semihosting:                       OpenOCD Project Setup.
+                                                             (line  314)
+* ARM semihosting <1>:                   Architecture and Core Commands.
+                                                             (line  314)
+* ARM semihosting <2>:                   Architecture and Core Commands.
+                                                             (line  326)
+* ARM semihosting <3>:                   Architecture and Core Commands.
+                                                             (line  337)
+* ARM semihosting <4>:                   Architecture and Core Commands.
+                                                             (line  348)
+* ARM semihosting <5>:                   Architecture and Core Commands.
+                                                             (line  357)
+* ARM semihosting <6>:                   Architecture and Core Commands.
+                                                             (line  378)
+* ARM semihosting <7>:                   Architecture and Core Commands.
+                                                             (line  387)
+* ARM11:                                 Architecture and Core Commands.
+                                                             (line  655)
+* ARM7:                                  Architecture and Core Commands.
+                                                             (line  401)
+* ARM9:                                  Architecture and Core Commands.
+                                                             (line  401)
+* ARM9 <1>:                              Architecture and Core Commands.
+                                                             (line  439)
+* ARM920T:                               Architecture and Core Commands.
+                                                             (line  459)
+* ARM926ej-s:                            Architecture and Core Commands.
+                                                             (line  484)
+* ARM966E:                               Architecture and Core Commands.
+                                                             (line  498)
+* ARMv4:                                 Architecture and Core Commands.
+                                                             (line  394)
+* ARMv5:                                 Architecture and Core Commands.
+                                                             (line  394)
+* ARMv6:                                 Architecture and Core Commands.
+                                                             (line  651)
+* ARMv7:                                 Architecture and Core Commands.
+                                                             (line  689)
+* ARMv8:                                 Architecture and Core Commands.
+                                                             (line  688)
+* ARMv8-A:                               Architecture and Core Commands.
+                                                             (line  966)
+* at91sam3:                              Flash Commands.     (line  782)
+* at91sam4:                              Flash Commands.     (line  837)
+* at91sam4l:                             Flash Commands.     (line  842)
+* at91samd:                              Flash Commands.     (line  704)
+* ath79:                                 Flash Commands.     (line  608)
+* Atheros ath79 SPI driver:              Flash Commands.     (line  608)
+* atsame5:                               Flash Commands.     (line  853)
+* atsamv:                                Flash Commands.     (line  906)
+* autoprobe:                             TAP Declaration.    (line  328)
+* board config file:                     Config File Guidelines.
+                                                             (line   68)
+* breakpoint:                            General Commands.   (line  404)
+* bscan_spi:                             Flash Commands.     (line  329)
+* CFI:                                   Flash Commands.     (line  294)
+* command line options:                  Running.            (line    6)
+* commands:                              General Commands.   (line    6)
+* Common Flash Interface:                Flash Commands.     (line  294)
+* config command:                        Server Configuration.
+                                                             (line   13)
+* config file, board:                    Config File Guidelines.
+                                                             (line   68)
+* config file, interface:                Debug Adapter Configuration.
+                                                             (line    6)
+* config file, overview:                 OpenOCD Project Setup.
+                                                             (line  139)
+* config file, target:                   Config File Guidelines.
+                                                             (line  298)
+* config file, user:                     OpenOCD Project Setup.
+                                                             (line  139)
+* configuration stage:                   Server Configuration.
+                                                             (line   13)
+* Connecting to GDB:                     GDB and OpenOCD.    (line   27)
+* Core Specific Commands:                Architecture and Core Commands.
+                                                             (line    6)
+* Cortex-A:                              Architecture and Core Commands.
+                                                             (line  692)
+* Cortex-M:                              Architecture and Core Commands.
+                                                             (line  907)
+* Cortex-R:                              Architecture and Core Commands.
+                                                             (line  727)
+* CPU type:                              CPU Configuration.  (line   60)
+* CTI:                                   Architecture and Core Commands.
+                                                             (line  225)
+* DAP declaration:                       TAP Declaration.    (line  384)
+* DCC:                                   Architecture and Core Commands.
+                                                             (line  417)
+* DCC <1>:                               Architecture and Core Commands.
+                                                             (line 2233)
+* developers:                            Developers.         (line    6)
+* directory search:                      Running.            (line    6)
+* disassemble:                           Architecture and Core Commands.
+                                                             (line  284)
+* disassemble <1>:                       Architecture and Core Commands.
+                                                             (line  979)
+* dongles:                               Debug Adapter Hardware.
+                                                             (line    6)
+* dotted name:                           TAP Declaration.    (line   98)
+* ETB:                                   Architecture and Core Commands.
+                                                             (line   14)
+* ETM:                                   Architecture and Core Commands.
+                                                             (line   14)
+* ETM <1>:                               Architecture and Core Commands.
+                                                             (line  897)
+* Etrace Commands:                       Nuclei Commands.    (line   27)
+* event, reset-init:                     Config File Guidelines.
+                                                             (line  184)
+* events:                                Reset Configuration.
+                                                             (line  226)
+* events <1>:                            TAP Declaration.    (line  227)
+* events <2>:                            CPU Configuration.  (line  498)
+* Extended Commands:                     Nuclei Commands.    (line   67)
+* faq:                                   FAQ.                (line    6)
+* fespi:                                 Flash Commands.     (line  641)
+* Firmware recovery:                     Utility Commands.   (line   45)
+* flash configuration:                   Flash Commands.     (line   36)
+* flash erasing:                         Flash Commands.     (line  102)
+* flash programming:                     Flash Commands.     (line  102)
+* flash protection:                      Flash Commands.     (line  230)
+* flash reading:                         Flash Commands.     (line  102)
+* flash writing:                         Flash Commands.     (line  102)
+* FPGA:                                  PLD/FPGA Commands.  (line    6)
+* Freedom E SPI:                         Flash Commands.     (line  641)
+* FTDI:                                  Debug Adapter Hardware.
+                                                             (line    6)
+* GDB:                                   Server Configuration.
+                                                             (line  179)
+* GDB <1>:                               GDB and OpenOCD.    (line    6)
+* GDB configuration:                     Server Configuration.
+                                                             (line  179)
+* GDB server:                            Server Configuration.
+                                                             (line  128)
+* GDB target:                            CPU Configuration.  (line    6)
+* Generic JTAG2SPI driver:               Flash Commands.     (line  329)
+* halt:                                  General Commands.   (line  103)
+* hwthread:                              GDB and OpenOCD.    (line  307)
+* image dumping:                         General Commands.   (line  342)
+* image loading:                         General Commands.   (line  342)
+* initialization:                        Server Configuration.
+                                                             (line    6)
+* init_board procedure:                  Config File Guidelines.
+                                                             (line  249)
+* init_targets procedure:                Config File Guidelines.
+                                                             (line  522)
+* init_target_events procedure:          Config File Guidelines.
+                                                             (line  567)
+* interface config file:                 Debug Adapter Configuration.
+                                                             (line    6)
+* IPDBG:                                 Boundary Scan Commands.
+                                                             (line   78)
+* IPDBG JTAG-Host server:                Boundary Scan Commands.
+                                                             (line   78)
+* ITM:                                   Architecture and Core Commands.
+                                                             (line  897)
+* Jim-Tcl:                               About Jim-Tcl.      (line    6)
+* jrc:                                   TAP Declaration.    (line  265)
+* JTAG:                                  About.              (line   15)
+* JTAG <1>:                              Debug Adapter Configuration.
+                                                             (line 1224)
+* JTAG autoprobe:                        TAP Declaration.    (line  328)
+* JTAG Commands:                         JTAG Commands.      (line    6)
+* JTAG Route Controller:                 TAP Declaration.    (line  265)
+* jtagspi:                               Flash Commands.     (line  329)
+* kinetis:                               Flash Commands.     (line 1091)
+* kinetis_ke:                            Flash Commands.     (line 1185)
+* libdcc:                                Architecture and Core Commands.
+                                                             (line 2233)
+* Linux-ARM DCC support:                 Architecture and Core Commands.
+                                                             (line 2233)
+* logfile:                               Running.            (line    6)
+* lpcspifi:                              Flash Commands.     (line  450)
+* memory access:                         General Commands.   (line  304)
+* message level:                         General Commands.   (line   73)
+* microMIPS:                             Architecture and Core Commands.
+                                                             (line 1265)
+* MIPS32:                                Architecture and Core Commands.
+                                                             (line 1265)
+* MIPS64:                                Architecture and Core Commands.
+                                                             (line 1265)
+* NAND:                                  Flash Commands.     (line 2330)
+* NAND configuration:                    Flash Commands.     (line 2385)
+* NAND erasing:                          Flash Commands.     (line 2465)
+* NAND other commands:                   Flash Commands.     (line 2556)
+* NAND programming:                      Flash Commands.     (line 2465)
+* NAND programming <1>:                  Flash Commands.     (line 2478)
+* NAND programming <2>:                  Flash Commands.     (line 2531)
+* NAND reading:                          Flash Commands.     (line 2432)
+* NAND verification:                     Flash Commands.     (line 2531)
+* NAND writing:                          Flash Commands.     (line 2478)
+* Nuclei Commands:                       Nuclei Commands.    (line    6)
+* Nuclei SPI:                            Flash Commands.     (line  647)
+* nuspi:                                 Flash Commands.     (line  647)
+* NXP SPI Flash Interface:               Flash Commands.     (line  450)
+* object command:                        CPU Configuration.  (line  337)
+* OctoSPI:                               Flash Commands.     (line  487)
+* PLD:                                   PLD/FPGA Commands.  (line    6)
+* port:                                  Server Configuration.
+                                                             (line  116)
+* printer port:                          Debug Adapter Hardware.
+                                                             (line    6)
+* profiling:                             General Commands.   (line  510)
+* Programming using GDB:                 GDB and OpenOCD.    (line  127)
+* QuadSPI:                               Flash Commands.     (line  487)
+* RAM testing:                           Utility Commands.   (line    9)
+* reset:                                 General Commands.   (line  103)
+* Reset Configuration:                   Reset Configuration.
+                                                             (line    6)
+* reset-init handler:                    Config File Guidelines.
+                                                             (line  184)
+* RPC:                                   Tcl Scripting API.  (line   65)
+* RPC Notifications:                     Tcl Scripting API.  (line   83)
+* RPC trace output:                      Tcl Scripting API.  (line  100)
+* RTCK:                                  Debug Adapter Hardware.
+                                                             (line    6)
+* RTCK <1>:                              Debug Adapter Configuration.
+                                                             (line 1344)
+* RTCK <2>:                              FAQ.                (line    6)
+* RTOS:                                  GDB and OpenOCD.    (line  307)
+* RTOS Commands:                         GDB and OpenOCD.    (line  299)
+* RTOS Support:                          GDB and OpenOCD.    (line  211)
+* scan chain:                            TAP Declaration.    (line   28)
+* security:                              Server Configuration.
+                                                             (line  116)
+* Serial Peripheral Interface:           Debug Adapter Configuration.
+                                                             (line 1268)
+* Serial Vector Format:                  Boundary Scan Commands.
+                                                             (line   13)
+* Serial Wire Debug:                     Debug Adapter Configuration.
+                                                             (line 1239)
+* server:                                Server Configuration.
+                                                             (line  116)
+* Show CPU Info:                         Nuclei Commands.    (line   11)
+* Single Wire Interface Module:          Debug Adapter Configuration.
+                                                             (line 1275)
+* SMI:                                   Flash Commands.     (line  467)
+* SMP:                                   Config File Guidelines.
+                                                             (line  425)
+* SMP <1>:                               GDB and OpenOCD.    (line  307)
+* SPI:                                   Debug Adapter Configuration.
+                                                             (line 1268)
+* SPI <1>:                               Flash Commands.     (line  329)
+* SPIFI:                                 Flash Commands.     (line  450)
+* STMicroelectronics QuadSPI/OctoSPI Interface: Flash Commands.
+                                                             (line  487)
+* STMicroelectronics Serial Memory Interface: Flash Commands.
+                                                             (line  467)
+* stmqspi:                               Flash Commands.     (line  487)
+* stmsmi:                                Flash Commands.     (line  467)
+* str9xpec:                              Flash Commands.     (line 2195)
+* SVF:                                   Boundary Scan Commands.
+                                                             (line   13)
+* SWD:                                   Debug Adapter Configuration.
+                                                             (line 1239)
+* SWD multi-drop:                        Debug Adapter Configuration.
+                                                             (line 1255)
+* SWIM:                                  Debug Adapter Configuration.
+                                                             (line 1275)
+* swm050:                                Flash Commands.     (line 2273)
+* SWO:                                   Architecture and Core Commands.
+                                                             (line  737)
+* SWO <1>:                               Architecture and Core Commands.
+                                                             (line  897)
+* SWV:                                   Architecture and Core Commands.
+                                                             (line  737)
+* SWV <1>:                               Architecture and Core Commands.
+                                                             (line  897)
+* TAP:                                   About.              (line   15)
+* TAP configuration:                     TAP Declaration.    (line    6)
+* TAP declaration:                       TAP Declaration.    (line    6)
+* TAP events:                            TAP Declaration.    (line  227)
+* TAP naming convention:                 TAP Declaration.    (line  121)
+* TAP state names:                       JTAG Commands.      (line  125)
+* target config file:                    Config File Guidelines.
+                                                             (line  298)
+* target events:                         CPU Configuration.  (line  498)
+* target initialization:                 General Commands.   (line  103)
+* target type:                           CPU Configuration.  (line   60)
+* target, current:                       CPU Configuration.  (line   18)
+* target, list:                          CPU Configuration.  (line   18)
+* tcl:                                   About Jim-Tcl.      (line    6)
+* Tcl:                                   Tcl Crash Course.   (line    6)
+* Tcl Scripting API:                     Tcl Scripting API.  (line    6)
+* Tcl scripts:                           Tcl Scripting API.  (line    5)
+* TCP port:                              Server Configuration.
+                                                             (line  116)
+* TPIU:                                  Architecture and Core Commands.
+                                                             (line  737)
+* tracing:                               Architecture and Core Commands.
+                                                             (line   14)
+* tracing <1>:                           Architecture and Core Commands.
+                                                             (line  737)
+* tracing <2>:                           Architecture and Core Commands.
+                                                             (line  897)
+* tracing <3>:                           Architecture and Core Commands.
+                                                             (line 2233)
+* translation:                           Config File Guidelines.
+                                                             (line  612)
+* Transport:                             Debug Adapter Configuration.
+                                                             (line 1202)
+* USB Adapter:                           Debug Adapter Hardware.
+                                                             (line    6)
+* user config file:                      OpenOCD Project Setup.
+                                                             (line  139)
+* Using GDB as a non-intrusive memory inspector: GDB and OpenOCD.
+                                                             (line  167)
+* Utility Commands:                      Utility Commands.   (line    5)
+* variable names:                        Config File Guidelines.
+                                                             (line  152)
+* vector_catch:                          OpenOCD Project Setup.
+                                                             (line  213)
+* vector_catch <1>:                      Architecture and Core Commands.
+                                                             (line  444)
+* vector_catch <2>:                      Architecture and Core Commands.
+                                                             (line  624)
+* vector_catch <3>:                      Architecture and Core Commands.
+                                                             (line  677)
+* vector_catch <4>:                      Architecture and Core Commands.
+                                                             (line  932)
+* vector_table:                          Architecture and Core Commands.
+                                                             (line  639)
+* watchpoint:                            General Commands.   (line  404)
+* wiggler:                               Debug Adapter Hardware.
+                                                             (line    6)
+* xcf:                                   Flash Commands.     (line  414)
+* Xilinx Platform flash driver:          Flash Commands.     (line  414)
+* Xilinx Serial Vector Format:           Boundary Scan Commands.
+                                                             (line   44)
+* XScale:                                Architecture and Core Commands.
+                                                             (line  512)
+* XSVF:                                  Boundary Scan Commands.
+                                                             (line   44)
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/doc/info/openocd.info-3 b/flash_code_20260525/flash_code/openocd/win/2025.10/doc/info/openocd.info-3
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zULYF{9)l21e)k-HH;mMws>jG~iJUM(!mwdfcymAPd#fY$fFr$nWgiQ
z)+RSHQb9S*NKIHkO+9x;HF7g++WUmf2BS0!Eh!->6tavY{(TDgdS#B^SmBxv`9t
z_r8Kg0-NU9tjx<}}8|*S-I`g=Yk%y)VeMZ){
zMNSyunwDmCspEtTJvm_HZ8nI3!9uFn;%#c}NRRaUq^*o7n$A?`IgpV*)5r8yMyx;U
zgb|wgUS(8p9<~!kes}M`)O0E8)9MjvHqIc;tnodNoX7~d&vw>`(Jr%!$qgf%t~)Yf
NDvg~mk~aI*e*] [\fB\-\-search\fR ] [\fB\-\-debug\fR ] [\fB\-\-log_output\fR ] [\fB\-\-command\fR ] [\fB\-\-help\fR] [\fB\-\-version\fR]
+.SH "DESCRIPTION"
+.B OpenOCD
+is an on\-chip debugging, in\-system programming and boundary\-scan
+testing tool for various microcontrollers and other embedded devices.
+.PP
+Various different types of debug adapters as well as transport protocols like
+JTAG and SWD are supported by OpenOCD, please check the \fIopenocd\fR info page
+for the complete list.
+.PP
+User interaction is realized through a telnet command line interface,
+a gdb (the GNU debugger) remote protocol server, and a simplified RPC
+connection that can be used to interface with OpenOCD's Jim Tcl engine.
+.SH "OPTIONS"
+.TP
+.B "\-f, \-\-file "
+This is a shortcut for a \fB\-c "[script \fI\fB]"\fR
+command, using a search path to load the configuration file
+.IR  .
+In order to specify multiple config files, you can use multiple
+.B \-\-file
+arguments. If no such \fB\-c\fR
+options are included, the first config file
+.B openocd.cfg
+in the search path will be used.
+.TP
+.B "\-s, \-\-search "
+Add
+.I 
+to the search path used for config files and scripts.
+The search path begins with the current directory,
+then includes these additional directories before other
+components such as the standard OpenOCD script libraries.
+.TP
+.B "\-d, \-\-debug "
+Set debug level. Possible values are:
+.br
+.RB "  * " 0 " (errors)"
+.br
+.RB "  * " 1 " (warnings)"
+.br
+.RB "  * " 2 " (informational messages)"
+.br
+.RB "  * " 3 " (debug messages)"
+.br
+The default level is
+.BR 2 .
+.TP
+.B "\-l, \-\-log_output "
+Redirect log output to the file
+.IR  .
+Per default the log output is printed on
+.BR stderr .
+.TP
+.B "\-c, \-\-command "
+Add the command
+.I 
+to a list of commands executed on server startup.
+Note that you will need to explicitly invoke
+.I init
+if the command requires access to a target or flash.
+.TP
+.TP
+.B "\-h, \-\-help"
+Show a help text and exit.
+.TP
+.B "\-v, \-\-version"
+Show version information and exit.
+.SH "BUGS"
+Please report any bugs on the mailing list at
+.BR openocd\-devel@lists.sourceforge.net .
+.SH "LICENCE"
+.B OpenOCD
+is covered by the GNU General Public License (GPL), version 2 or later.
+.PP
+The full documentation for
+.B openocd
+is maintained as a Texinfo manual. If the
+.BR info
+(or
+.BR pinfo )
+and
+.BR openocd
+programs are properly installed at your site, the command
+.B info openocd
+should give you access to the complete manual.
+.SH "AUTHORS"
+Please see the file AUTHORS.
+.PP
+This manual page was written by Uwe Hermann .
+It is licensed under the terms of the GNU GPL (version 2 or later).
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/doc/pdf/openocd.pdf b/flash_code_20260525/flash_code/openocd/win/2025.10/doc/pdf/openocd.pdf
new file mode 100644
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+}
+
+proc show_normalize_bitfield { VALUE MSB LSB } {
+    set m [create_mask $MSB $LSB]
+    set mr [expr {$VALUE & $m}]
+    set sr [expr {$mr >> $LSB}]
+    echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
+   return $sr
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/8devices-lima.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/8devices-lima.cfg
new file mode 100644
index 0000000..a094cae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/8devices-lima.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Product page:
+# https://www.8devices.com/products/lima
+#
+# Location of JTAG pins:
+# J2 GPIO0	JTAG TCK
+# J2 GPIO1	JTAG TDI
+# J2 GPIO2	JTAG TDO
+# J2 GPIO3	JTAG TMS
+# J2 RST	directly connected to RESET_L of the SoC and can be used as
+#               JTAG SRST. Note: this pin will also reset the debug engine.
+# J1 +3,3V	Can be use as JTAG Vref
+# J1 or J2 GND	Can be used for JTAG GND
+#
+# This board is powered from mini USB connecter which is also used
+# as USB to UART converted based on FTDI FT230XQ chip
+
+source [find target/qualcomm_qca4531.cfg]
+
+proc board_init { } {
+	qca4531_ddr2_550_550_init
+}
+
+$_TARGETNAME configure -event reset-init {
+	board_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/actux3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/actux3.cfg
new file mode 100644
index 0000000..7c2ce06
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/actux3.cfg
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# board config file for AcTux3/XBA IXP42x board
+# Date:   2010-12-16
+# Author: Michael Schwingen 
+
+reset_config trst_and_srst separate
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+source [find target/ixp42x.cfg]
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init { init_actux3 }
+
+proc init_actux3 { } {
+    ##########################################################################
+    # setup expansion bus CS
+    ##########################################################################
+    mww 0xc4000000  0xbd113842  ;#CS0  : Flash, write enabled @0x50000000
+    mww 0xc4000004  0x94d10013  ;#CS1
+    mww 0xc4000008  0x95960003  ;#CS2
+    mww 0xc400000c  0x00000000  ;#CS3
+    mww 0xc4000010  0x80900003  ;#CS4
+    mww 0xc4000014  0x9d520003  ;#CS5
+    mww 0xc4000018  0x81860001  ;#CS6
+    mww 0xc400001c  0x80900003  ;#CS7
+
+    ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3
+
+    #mww 0xc4000020  0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000
+
+    ixp42x_set_bigendian
+
+    flash probe 0
+}
+
+proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } {
+    echo "writing bootloader: $FILE"
+    flash write_image erase $FILE 0x50000000 bin
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
+
+init
+reset init
+
+# setup to debug u-boot in flash
+proc uboot_debug {} {
+    gdb breakpoint_override hard
+    xscale vector_catch 0xFF
+
+    xscale vector_table low  1 0xe59ff018
+    xscale vector_table low  2 0xe59ff018
+    xscale vector_table low  3 0xe59ff018
+    xscale vector_table low  4 0xe59ff018
+    xscale vector_table low  5 0xe59ff018
+    xscale vector_table low  6 0xe59ff018
+    xscale vector_table low  7 0xe59ff018
+
+    xscale vector_table high 1 0xe59ff018
+    xscale vector_table high 2 0xe59ff018
+    xscale vector_table high 3 0xe59ff018
+    xscale vector_table high 4 0xe59ff018
+    xscale vector_table high 5 0xe59ff018
+    xscale vector_table high 6 0xe59ff018
+    xscale vector_table high 7 0xe59ff018
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/adapteva_parallella1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/adapteva_parallella1.cfg
new file mode 100644
index 0000000..d6336a8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/adapteva_parallella1.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Adapteva Parallella-I board (via Porcupine-1 adapter board)
+#
+
+reset_config srst_only
+
+source [find target/zynq_7000.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/adsp-sc584-ezbrd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/adsp-sc584-ezbrd.cfg
new file mode 100644
index 0000000..366a24a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/adsp-sc584-ezbrd.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Analog Devices ADSP-SC584-EZBRD evaluation board
+#
+# Evaluation boards by Analog Devices (and designs derived from them) use a
+# non-standard 10-pin 0.05" ARM Cortex Debug Connector.  In this bastardized
+# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST.
+#
+# As a result, a standards-compliant debug pod will force /TRST active,
+# putting the processor's debug interface into reset and preventing usage.
+#
+# A connector adapter must be employed on these boards to isolate or remap
+# /TRST so that it is only asserted when intended.
+
+# Analog expects users to use their proprietary ICE-1000 / ICE-2000 with all
+# ADSP-SC58x designs, but this is an ARM target (and subject to the
+# qualifications above) many ARM debug pods should be compatible.
+
+#source [find interface/cmsis-dap.cfg]
+source [find interface/jlink.cfg]
+
+# Analog's silicon supports SWD and JTAG, but their proprietary ICE is limited
+# to JTAG.  (This is presumably why their connector pinout was modified.)
+# SWD is chosen here, as it is more efficient and doesn't require /TRST.
+
+transport select swd
+
+# chosen speed is 'safe' choice, but your adapter may be capable of more
+adapter speed 400
+
+source [find target/adsp-sc58x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/advantech_imx8qm_dmsse20.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/advantech_imx8qm_dmsse20.cfg
new file mode 100644
index 0000000..a867b2d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/advantech_imx8qm_dmsse20.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for Advantech IMX8QM DMSSE20
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+# board has an i.MX8QM with 4 Cortex-A53 cores and 2 Cortex-A72
+set CHIPNAME imx8qm
+set CHIPCORES 6
+
+# source SoC configuration
+source [find tcl/target/imx8qm.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/alphascale_asm9260_ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/alphascale_asm9260_ek.cfg
new file mode 100644
index 0000000..33a8354
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/alphascale_asm9260_ek.cfg
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/alphascale_asm9260t.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event reset-init {
+	echo "Configure clock"
+	# Enable SRAM clk
+	mww 0x80040024 0x4
+	# Enable IRQ clk
+	mww 0x80040034 0x100
+	# Enable DMA0,1 clk
+	mww 0x80040024 0x600
+	# Make sysre syspll is enabled
+	mww 0x80040238 0x750
+	#CPU = PLLCLK/2
+	mww 0x8004017C 0x2
+	#SYSAHBCLK = CPUCLK/2
+	mww 0x80040180 0x2
+	# Set PLL freq to 480MHz
+	mww 0x80040100 480
+	# normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
+	sleep 100
+
+	# select PLL as main source
+	mww 0x80040120 0x1
+	# disable and enable main clk to update changes?
+	mww 0x80040124 0x0
+	mww 0x80040124 0x1
+
+	echo "Configure memory"
+	#enable EMI CLK
+	mww 0x80040024 0x40
+
+	# configure memory controller for internal SRAM
+	mww 0x80700000 0x1188
+	# change default emi clk delay
+	mww 0x8004034C 0xA0503
+	# make sure chip_select_register2_low has correct value (why?)
+	mww 0x8070001c 0x20000000
+	# set type to sdram and size to 32MB
+	mww 0x8070005c 0xa
+	# configure internal SDRAM timing
+	mww 0x80700004 0x024996d9
+	# configure Static Memory timing
+	mww 0x80700094 0x00542b4f
+
+	echo "Configure uart4"
+	# enable pinctrl clk
+	mww 0x80040024 0x2000000
+	# mux GPIO3_0 and GPIO3_1 to UART4
+	mww 0x80044060 0x2
+	mww 0x80044064 0x2
+	# configure UART4CLKDIV
+	mww 0x800401a8 0x1
+	# enable uart4 clk
+	mww 0x80040024 0x8000
+	# clear softrst and clkgate on uart4
+	mww 0x80010008 0xC0000000
+	# set bandrate 115200 12M
+	mww 0x80010030 0x00062070
+	# enable Rx&Tx
+	mww 0x80010024 0x301
+	# clear hw control
+	mww 0x80010028 0xc000
+}
+
+$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
+$_TARGETNAME arm7_9 fast_memory_access enable
+$_TARGETNAME arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/altera_sockit.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/altera_sockit.cfg
new file mode 100644
index 0000000..bbd87d6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/altera_sockit.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Cyclone V SocKit board
+# http://www.altera.com/b/arrow-sockit.html
+#
+# Software support page:
+# http://www.rocketboards.org/
+
+# openocd does not currently support the on-board USB Blaster II.
+# Install the JTAG header and use a USB Blaster instead.
+adapter driver usb_blaster
+
+source [find target/altera_fpgasoc.cfg]
+
+# If the USB Blaster II were supported, these settings would be needed
+#usb_blaster vid_pid 0x09fb 0x6810
+#usb_blaster device_desc "USB-Blaster II"
+
+adapter speed 100
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/am3517evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/am3517evm.cfg
new file mode 100644
index 0000000..0b19be6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/am3517evm.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# DANGER!!!! early work in progress for this PCB/target.
+#
+# The most basic operations work well enough that it is
+# useful to have this in the repository for cooperation
+# alpha testing purposes.
+#
+# TI AM3517
+#
+# http://focus.ti.com/docs/prod/folders/print/am3517.html
+# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
+# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
+
+set CHIPTYPE "am35x"
+source [find target/amdm37x.cfg]
+
+# The TI-14 JTAG connector does not have srst.  CPU reset is handled in
+# hardware.
+reset_config trst_only
+
+# "amdm37x_dbginit am35x.cpu" needs to be run after init.
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ampere_emag8180.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ampere_emag8180.cfg
new file mode 100644
index 0000000..736be12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ampere_emag8180.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# OpenOCD Board Configuration for eMAG Development Platform
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+#
+
+#
+# Configure JTAG speed
+#
+
+adapter speed 2000
+
+#
+# Configure Resets
+#
+
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+source [find target/ampere_emag.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ampere_qs_mq_1s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ampere_qs_mq_1s.cfg
new file mode 100644
index 0000000..bc649ed
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ampere_qs_mq_1s.cfg
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
+# Ampere Altra Max ("Mystique") processors
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+
+# Argument Description
+#
+# JTAGFREQ
+# Set the JTAG clock frequency
+# Syntax: -c "set JTAGFREQ {freq_in_khz}"
+#
+# SYSNAME
+# Set the system name
+# If not specified, defaults to "qs"
+# Syntax: -c "set SYSNAME {qs}"
+#
+# Life-Cycle State (LCS)
+# If not specified, defaults to "Secure LCS"
+# LCS=0, "Secure LCS"
+# LCS=1, "Chip Manufacturing LCS"
+# Syntax: -c "set LCS {0}"
+# Syntax: -c "set LCS {1}"
+#
+# CORELIST_S0
+# Specify available physical cores by number
+# Example syntax to connect to physical cores 16 and 17 for S0
+# Syntax: -c "set CORELIST_S0 {16 17}"
+#
+# COREMASK_S0_LO
+# Specify available physical cores 0-63 by mask
+# Example syntax to connect to physical cores 16 and 17 for S0
+# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
+#
+# COREMASK_S0_HI
+# Specify available physical cores 64 and above by mask
+# Example syntax to connect to physical cores 94 and 95 for S0
+# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
+#
+# PHYS_IDX
+# Enable OpenOCD ARMv8 core target physical indexing
+# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
+# Syntax: -c "set PHYS_IDX {}"
+
+#
+# Configure JTAG speed
+#
+
+if { [info exists JTAGFREQ] } {
+	adapter speed $JTAGFREQ
+} else {
+	adapter speed 100
+}
+
+#
+# Set the system name
+#
+
+if { [info exists SYSNAME] } {
+	set _SYSNAME $SYSNAME
+} else {
+	set _SYSNAME qs
+}
+
+#
+# Configure Resets
+#
+
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] } {
+	set CHIPNAME ${_SYSNAME}0
+	if { [info exists CORELIST_S0] } {
+		set CORELIST $CORELIST_S0
+	} else {
+		if { [info exists COREMASK_S0_LO] } {
+			set COREMASK_LO $COREMASK_S0_LO
+		} else {
+			set COREMASK_LO 0x0
+		}
+
+		if { [info exists COREMASK_S0_HI] } {
+			set COREMASK_HI $COREMASK_S0_HI
+		} else {
+			set COREMASK_HI 0x0
+		}
+	}
+} else {
+	set CHIPNAME ${_SYSNAME}0
+	set COREMASK_LO 0x1
+	set COREMASK_HI 0x0
+}
+
+source [find target/ampere_qs_mq.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ampere_qs_mq_2s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ampere_qs_mq_2s.cfg
new file mode 100644
index 0000000..76d82d2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ampere_qs_mq_2s.cfg
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
+# Ampere Altra Max ("Mystique") processors
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+
+# Argument Description
+#
+# JTAGFREQ
+# Set the JTAG clock frequency
+# Syntax: -c "set JTAGFREQ {freq_in_khz}"
+#
+# SYSNAME
+# Set the system name
+# If not specified, defaults to "qs"
+# Syntax: -c "set SYSNAME {qs}"
+#
+# Life-Cycle State (LCS)
+# If not specified, defaults to "Secure LCS"
+# LCS=0, "Secure LCS"
+# LCS=1, "Chip Manufacturing LCS"
+# Syntax: -c "set LCS {0}"
+# Syntax: -c "set LCS {1}"
+#
+# CORELIST_S0, CORELIST_S1
+# Specify available physical cores by number
+# Example syntax to connect to physical cores 16 and 17 for S0 and S1
+# Syntax: -c "set CORELIST_S0 {16 17}"
+# Syntax: -c "set CORELIST_S1 {16 17}"
+#
+# COREMASK_S0_LO, COREMASK_S1_LO
+# Specify available physical cores 0-63 by mask
+# Example syntax to connect to physical cores 16 and 17 for S0 and S1
+# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
+# Syntax: -c "set COREMASK_S1_LO {0x0000000000030000}"
+#
+# COREMASK_S0_HI, COREMASK_S1_HI
+# Specify available physical cores 64 and above by mask
+# Example syntax to connect to physical cores 94 and 95 for S0 and S1
+# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
+# Syntax: -c "set COREMASK_S1_HI {0x00000000C0000000}"
+#
+# SPLITSMP
+# Group all ARMv8 cores per socket into individual SMP sessions
+# If not specified, group ARMv8 cores from both sockets into one SMP session
+# Syntax: -c "set SPLITSMP {}"
+#
+# PHYS_IDX
+# Enable OpenOCD ARMv8 core target physical indexing
+# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
+# Syntax: -c "set PHYS_IDX {}"
+
+#
+# Configure JTAG speed
+#
+
+if { [info exists JTAGFREQ] } {
+	adapter speed $JTAGFREQ
+} else {
+	adapter speed 100
+}
+
+#
+# Set the system name
+#
+
+if { [info exists SYSNAME] } {
+	set _SYSNAME $SYSNAME
+} else {
+	set _SYSNAME qs
+}
+
+#
+# Configure Board level SMP configuration if necessary
+#
+
+if { ![info exists SPLITSMP] } {
+	# Group dual chip into a single SMP configuration
+	set SMP_STR "target smp"
+	set CORE_INDEX_OFFSET 0
+	set DUAL_SOCKET_SMP_ENABLED ""
+}
+
+#
+# Configure Resets
+#
+
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \
+     [info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } {
+	set CHIPNAME ${_SYSNAME}1
+	if { [info exists CORELIST_S1] } {
+		set CORELIST $CORELIST_S1
+	} else {
+		if { [info exists COREMASK_S1_LO] } {
+			set COREMASK_LO $COREMASK_S1_LO
+		} else {
+			set COREMASK_LO 0x0
+		}
+
+		if { [info exists COREMASK_S1_HI] } {
+			set COREMASK_HI $COREMASK_S1_HI
+		} else {
+			set COREMASK_HI 0x0
+		}
+	}
+	source [find target/ampere_qs_mq.cfg]
+
+	if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
+		if { [info exists MQ_ENABLE] } {
+			set CORE_INDEX_OFFSET 128
+		} else {
+			set CORE_INDEX_OFFSET 80
+		}
+	}
+
+	set CHIPNAME ${_SYSNAME}0
+	if { [info exists CORELIST_S0] } {
+		set CORELIST $CORELIST_S0
+	} else {
+		if { [info exists COREMASK_S0_LO] } {
+			set COREMASK_LO $COREMASK_S0_LO
+		} else {
+			set COREMASK_LO 0x0
+		}
+
+		if { [info exists COREMASK_S0_HI] } {
+			set COREMASK_HI $COREMASK_S0_HI
+		} else {
+			set COREMASK_HI 0x0
+		}
+	}
+	source [find target/ampere_qs_mq.cfg]
+} else {
+	set CHIPNAME ${_SYSNAME}1
+	set COREMASK_LO 0x0
+	set COREMASK_HI 0x0
+	source [find target/ampere_qs_mq.cfg]
+
+	if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
+		if { [info exists MQ_ENABLE] } {
+			set CORE_INDEX_OFFSET 128
+		} else {
+			set CORE_INDEX_OFFSET 80
+		}
+	}
+
+	set CHIPNAME ${_SYSNAME}0
+	set COREMASK_LO 0x1
+	set COREMASK_HI 0x0
+	source [find target/ampere_qs_mq.cfg]
+}
+
+if { [info exists DUAL_SOCKET_SMP_ENABLED] } {
+	# For dual socket SMP configuration, evaluate the string
+	eval $SMP_STR
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/arm_evaluator7t.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/arm_evaluator7t.cfg
new file mode 100644
index 0000000..0fb8778
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/arm_evaluator7t.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This board is from ARM and has an samsung s3c45101x01 chip
+
+source [find target/samsung_s3c4510.cfg]
+
+#
+# FIXME:
+#  Add (A) sdram configuration
+#  Add (B) flash cfi programming configuration
+#
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/arm_musca_a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/arm_musca_a.cfg
new file mode 100644
index 0000000..b4880d1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/arm_musca_a.cfg
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration script for ARM Musca-A development board
+#
+# For now we do not support Musca A flash programming using OpenOCD. However, a
+# work area is configured for flash programming speed up.
+#
+# GDB considers all memory as RAM unless target supplies a memory map.
+# OpenOCD will only send memory map if flash banks are configured. Otherwise,
+# configure GDB after connection by issuing following commands:
+# (gdb) mem 0x10200000 0x109FFFFF ro
+# (gdb) mem 0x00200000 0x009FFFFF ro
+# (gdb) set mem inaccessible-by-default off
+
+# ARM Musca A board supports both JTAG and SWD transports.
+source [find target/swj-dp.tcl]
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+global _CHIPNAME
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME MUSCA_A
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x6ba00477
+}
+
+# Enable CPU1 debugging as a separate GDB target
+set _ENABLE_CPU1 1
+
+# Musca A1 has 32KB SRAM banks. Override default work-area-size to 8KB per CPU
+set WORKAREASIZE_CPU0 0x2000
+set WORKAREASIZE_CPU1 0x2000
+
+# Set SRAM bank 1 to be used for work area. Override here if needed.
+set WORKAREAADDR_CPU0 0x30008000
+set WORKAREAADDR_CPU1 0x3000A000
+
+source [find target/arm_corelink_sse200.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/arty_s7.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/arty_s7.cfg
new file mode 100644
index 0000000..eaa15ab
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/arty_s7.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Arty S7: Spartan7 25/50 FPGA Board for Makers and Hobbyists
+#
+# https://www.xilinx.com/products/boards-and-kits/1-pnziih.html
+# https://store.digilentinc.com/arty-s7-spartan-7-fpga-board-for-makers-and-hobbyists/
+
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# Xilinx Spartan7-25/50 FPGA (XC7S{25,50}-CSGA324)
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+
+adapter speed 25000
+
+# Usage:
+#
+# Load Bitstream into FPGA:
+#    openocd -f board/arty_s7.cfg -c "init;\
+#    pld load 0 bitstream.bit;\
+#    shutdown"
+#
+# Write Bitstream to Flash:
+#    openocd -f board/arty_s7.cfg -c "init;\
+#    jtagspi_init 0 bscan_spi_xc7s??.bit;\
+#    jtagspi_program bitstream.bin 0;\
+#    xc7_program xc7.tap;\
+#    shutdown"
+#
+# jtagspi flash proxies can be found at:
+# https://github.com/quartiq/bscan_spi_bitstreams
+#
+# For the Spartan 50 variant, use
+#  - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s50.bit
+# For the Spartan 25 variant, use
+#  - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s25.bit
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/asus-rt-n16.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/asus-rt-n16.cfg
new file mode 100644
index 0000000..a02bab8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/asus-rt-n16.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# http://wikidevi.com/wiki/ASUS_RT-N16
+#
+
+set partition_list {
+    CFE		{ Bootloader			0xbc000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0xbc040000 0x01fa0000 }
+    nvram	{ "Config space"		0xbdfe0000 0x00020000 }
+}
+
+source [find target/bcm4718.cfg]
+
+# External 32MB NOR Flash (Macronix MX29GL256EHTI2I-90Q)
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 1 1 $_TARGETNAME x16_as_x8
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/asus-rt-n66u.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/asus-rt-n66u.cfg
new file mode 100644
index 0000000..dda0f33
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/asus-rt-n66u.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# http://wikidevi.com/wiki/Asus_RT-N66U
+#
+
+echo "ATTENTION: you need to solder a 4.7-10k pullup resistor to pin 21 of flash IC"
+echo "to enable JTAG, see http://wl500g.info/album.php?albumid=28&attachmentid=8991 ,"
+echo "there is an unpopulated footprint near U8.\n"
+
+set partition_list {
+    CFE		{ Bootloader			0xbc000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0xbc040000 0x01fa0000 }
+    nvram	{ "Config space"		0xbdfe0000 0x00020000 }
+}
+
+source [find target/bcm4706.cfg]
+
+# External 32MB NOR Flash (Spansion S29GL256P10TF101
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91cap7a-stk-sdram.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91cap7a-stk-sdram.cfg
new file mode 100644
index 0000000..6da917a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91cap7a-stk-sdram.cfg
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
+#
+# use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME cap7
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x40700f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start {
+	# start off real slow when we're running off internal RC oscillator
+	adapter speed 32
+}
+
+proc peek32 {address} {
+	return [read_memory $address 32 1]
+}
+
+# Wait for an expression to be true with a timeout
+proc wait_state {expression} {
+	for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {
+		if {[uplevel 1 $expression] == 0} {
+			return
+		}
+	}
+	return -code 1 "Timed out"
+}
+
+# Use a global variable here to be able to tinker interactively with
+# post reset jtag frequency.
+global post_reset_khz
+# Danger!!!! Even 16MHz kinda works with this target, but
+# it needs to be as low as 2000kHz to be stable.
+set post_reset_khz 2000
+
+$_TARGETNAME configure -event reset-init {
+	echo "Configuring master clock"
+	# disable watchdog
+	mww 0xfffffd44 0xff008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# Enable main oscillator
+	mww 0xFFFFFc20  0x00000f01
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
+
+	# Set PLLA to 96MHz
+	mww 0xFFFFFc28 0x20072801
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
+
+	# Select prescaler
+	mww 0xFFFFFC30 0x00000004
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
+
+	# Select master clock to 48MHz
+	mww 0xFFFFFC30 0x00000006
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
+
+	echo "Master clock ok."
+
+	# Now that we're up and running, crank up speed!
+	global post_reset_khz ;	adapter speed $post_reset_khz
+
+	echo "Configuring the SDRAM controller..."
+
+	# Configure EBI Chip select for SDRAM
+	mww 0xFFFFEF30 0x00000102
+
+	# Enable clock on EBI PIOs
+	mww 0xFFFFFC10 0x00000004
+
+	# Configure PIO for SDRAM
+	mww 0xFFFFF470 0xFFFF0000
+	mww 0xFFFFF474 0x00000000
+	mww 0xFFFFF404 0xFFFF0000
+
+	# Configure SDRAMC CR
+	mww 0xFFFFEA08 0xA63392F9
+
+	# NOP command
+	mww 0xFFFFEA00 0x1
+	mww 0x20000000 0
+
+	# Precharge All Banks command
+	mww 0xFFFFEA00 0x2
+	mww 0x20000000 0
+
+	# Set 1st CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000010 0x00000001
+
+	# Set 2nd CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000020 0x00000002
+
+	# Set 3rd CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000030 0x00000003
+
+	# Set 4th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000040 0x00000004
+
+	# Set 5th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000050 0x00000005
+
+	# Set 6th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000060 0x00000006
+
+	# Set 7th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000070 0x00000007
+
+	# Set 8th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000080 0x00000008
+
+	# Set LMR operation
+	mww 0xFFFFEA00 0x00000003
+
+	# Perform LMR burst=1, lat=2
+	mww 0x20000020 0xCAFEDEDE
+
+	# Set Refresh Timer
+	mww 0xFFFFEA04 0x00000203
+
+	# Set Normal mode
+	mww 0xFFFFEA00 0x00000000
+	mww 0x20000000 0x00000000
+
+	#remap internal memory at address 0x0
+	mww 0xffffef00 0x3
+
+	echo "SDRAM configuration ok."
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+#set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91eb40a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91eb40a.cfg
new file mode 100644
index 0000000..60c6c6e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91eb40a.cfg
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#Script for AT91EB40a
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME at91eb40a
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+#flash driver
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x01000000 0x200000 2 2 $_TARGETNAME
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+$_TARGETNAME configure -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+	echo "Running reset init script for AT91EB40A"
+	# Reset script for AT91EB40a
+	reg cpsr 0x000000D3
+	mww 0xFFE00020 0x1
+	mww 0xFFE00024 0x00000000
+	mww 0xFFE00000 0x01002539
+	mww 0xFFFFF124 0xFFFFFFFF
+	mww 0xffff0010 0x100
+	mww 0xffff0034 0x100
+}
+
+# This target is pretty snappy...
+adapter speed 16000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91rm9200-dk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91rm9200-dk.cfg
new file mode 100644
index 0000000..3751103
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91rm9200-dk.cfg
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is for the "at91rm9200-DK" (not the EK) eval board.
+#
+# The two are probably very simular.... I have DK...
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
+
+#flash bank       
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME
+
+
+proc at91rm9200_dk_init { } {
+    # Try to run at 1khz... Yea, that slow!
+    # Chip is really running @ 32khz
+    adapter speed 8
+
+    mww 0xfffffc64 0xffffffff
+    ##  disable all clocks but system clock
+    mww 0xfffffc04 0xfffffffe
+    ##  disable all clocks to pioa and piob
+    mww 0xfffffc14 0xffffffc3
+    ##  master clock = slow cpu = slow
+    ##  (means the CPU is running at 32khz!)
+    mww 0xfffffc30 0
+    ##  main osc enable
+    mww 0xfffffc20 0x0000ff01
+    ##  program pllA
+    mww 0xfffffc28 0x20263e04
+    ##  program pllB
+    mww 0xfffffc2c 0x10483e0e
+    ##  let pll settle... sleep 100msec
+    sleep 100
+    ##  switch to fast clock
+    mww 0xfffffc30 0x202
+    ## Sleep some - (go read)
+    sleep 100
+
+    #========================================
+    # CPU now runs at 180mhz
+    # SYS runs at 60mhz.
+    adapter speed 40000
+    #========================================
+
+
+    ##  set memc for all memories
+    mww 0xffffff60 0x02
+    ##  program smc controller
+    mww 0xffffff70 0x3284
+    ##  init sdram
+    mww 0xffffff98 0x7fffffd0
+    ##  all banks precharge
+    mww 0xffffff80 0x02
+    ##  touch sdram chip to make it work
+    mww 0x20000000 0
+    ##  sdram controller mode register
+    mww 0xffffff90 0x04
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    ##  sdram controller mode register
+    ##  Refresh, etc....
+    mww 0xffffff90 0x03
+    mww 0x20000080 0
+    mww 0xffffff94 0x1f4
+    mww 0x20000080 0
+    mww 0xffffff90 0x10
+    mww 0x20000000 0
+    mww 0xffffff00 0x01
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91rm9200-ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91rm9200-ek.cfg
new file mode 100644
index 0000000..e38914e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91rm9200-ek.cfg
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD 
+#
+# under GPLv2 Only
+#
+# This is for the "at91rm9200-ek" eval board.
+#
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
+
+## flash bank       
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+
+# The chip may run @ 32khz, so set a really low JTAG speed
+adapter speed 8
+
+proc at91rm9200_ek_init { } {
+	# Try to run at 1khz... Yea, that slow!
+	# Chip is really running @ 32khz
+	adapter speed 8
+
+	mww 0xfffffc64 0xffffffff
+	## disable all clocks but system clock
+	mww 0xfffffc04 0xfffffffe
+	## disable all clocks to pioa and piob
+	mww 0xfffffc14 0xffffffc3
+	## master clock = slow cpu = slow
+	## (means the CPU is running at 32khz!)
+	mww 0xfffffc30 0
+	## main osc enable
+	mww 0xfffffc20 0x0000ff01
+	## MC_PUP
+	mww 0xFFFFFF50 0x00000000
+	## MC_PUER: Memory controller protection unit disable
+	mww 0xFFFFFF54 0x00000000
+	## EBI_CFGR
+	mww 0xFFFFFF64 0x00000000
+	## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
+	mww 0xFFFFFF70 0x00003284
+
+	## Init Clocks
+	## CKGR_PLLAR
+	mww 0xFFFFFC28 0x2000BF05
+	## PLLAR: 179,712000 MHz for PCK
+	mww 0xFFFFFC28 0x20263E04
+	sleep 100
+	## PMC_MCKR
+	mww 0xFFFFFC30 0x00000100
+	sleep 100
+	## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
+	mww 0xFFFFFC30 0x00000202
+	sleep 100
+
+	#========================================
+	# CPU now runs at 180mhz
+	# SYS runs at 60mhz.
+	adapter speed 40000
+	#========================================
+
+	## Init SDRAM
+	## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
+	mww 0xFFFFF870 0xFFFF0000
+	## PIOC_BSR:
+	mww 0xFFFFF874 0x00000000
+	## PIOC_PDR:
+	mww 0xFFFFF804 0xFFFF0000
+	## EBI_CSA : CS1=SDRAM
+	mww 0xFFFFFF60 0x00000002
+	## EBI_CFGR:
+	mww 0xFFFFFF64 0x00000000
+	## SDRC_CR :
+	mww 0xFFFFFF98 0x2188c155
+	## SDRC_MR : Precharge All
+	mww 0xFFFFFF90 0x00000002
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Refresh
+	mww 0xFFFFFF90 0x00000004
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Load Mode Register
+	mww 0xFFFFFF90 0x00000003
+	## access SDRAM
+	mww 0x20000080 0x00000000
+	## SDRC_TR : Write refresh rate
+	mww 0xFFFFFF94 0x000002E0
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Normal Mode
+	mww 0xFFFFFF90 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91sam9261-ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91sam9261-ek.cfg
new file mode 100644
index 0000000..c2d97b0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91sam9261-ek.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Atmel AT91SAM9261-EK eval board
+################################################################################
+
+source [find mem_helper.tcl]
+source [find target/at91sam9261.cfg]
+uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9261.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+scan_chain
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }
+$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
+
+proc at91sam9261ek_reset_init { } {
+
+	;# for ppla at 199 Mhz
+	set config(master_pll_div)	15
+	set config(master_pll_mul)	162
+
+	;# for ppla at 239 Mhz
+	;# set master_pll_div	1
+	;# set master_pll_mul	13
+
+	set val	$::AT91_WDT_WDV							;# Counter Value
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]		;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]			;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
+
+	set config(wdt_mr_val) $val
+
+	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
+	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBICSA
+	set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
+
+	;# SDRAMC_CR - Configuration register
+	set val $::AT91_SDRAMC_NC_9
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (2 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (3 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (8 << 28)}]		;# Exit Self Refresh to Active Delay
+
+	set config(sdram_cr_val) $val
+
+	set config(sdram_tr_val) 0x13c
+
+	set config(sdram_base) $::AT91_CHIPSELECT_1
+	at91sam9_reset_init $config
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91sam9263-ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91sam9263-ek.cfg
new file mode 100644
index 0000000..328a792
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91sam9263-ek.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Atmel AT91SAM9263-EK eval board
+################################################################################
+
+source [find mem_helper.tcl]
+source [find target/at91sam9263.cfg]
+uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9263.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+scan_chain
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }
+$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
+
+proc at91sam9263ek_reset_init { } {
+
+	set config(master_pll_div)	14
+	set config(master_pll_mul)	171
+
+	set val	$::AT91_WDT_WDV							;# Counter Value
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]		;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]			;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
+
+	set config(wdt_mr_val) $val
+
+	set config(sdram_piod) 1
+	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
+	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBI0CSA
+
+	set val	$::AT91_MATRIX_EBI0_DBPUC
+	set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}]
+	set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}]
+	set config(matrix_ebicsa_val) $val
+
+	;# SDRAMC_CR - Configuration register
+	set val $::AT91_SDRAMC_NC_9
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (1 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (2 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (1 << 28)}]		;# Exit Self Refresh to Active Delay
+
+	set config(sdram_cr_val) $val
+
+	set config(sdram_tr_val) 0x13c
+
+	set config(sdram_base) $::AT91_CHIPSELECT_1
+	at91sam9_reset_init $config
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91sam9g20-ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91sam9g20-ek.cfg
new file mode 100644
index 0000000..22a38a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/at91sam9g20-ek.cfg
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#################################################################################################
+#												#
+# Author: Gary Carlson (gcarlson@carlson-minot.com)						#
+# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8.	#
+#												#
+#################################################################################################
+
+source [find target/at91sam9g20.cfg]
+
+set _FLASHTYPE nandflash_cs3
+
+# Set reset type.  Note that the AT91SAM9G20-EK board has the trst signal disconnected.  Therefore
+# the reset needs to be configured for "srst_only".  If for some reason, a zero-ohm jumper is
+# added to the board to connect the trst signal, then this parameter may need to be changed.
+
+reset_config srst_only
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
+# AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
+# some powerful features, we want to have a special function that handles "reset init".  To do this we declare
+# an event handler where these special activities can take place.
+
+scan_chain
+$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
+$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
+
+# NandFlash configuration and definition
+
+nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800
+at91sam9 cle 0 22
+at91sam9 ale 0 21
+at91sam9 rdy_busy 0 0xfffff800 13
+at91sam9 ce 0 0xfffff800 14
+
+proc read_register {register} {
+	return [read_memory $register 32 1]
+}
+
+proc at91sam9g20_reset_start { } {
+
+	# Make sure that the jtag is running slow, since there are a number of different ways the board
+	# can be configured coming into this state that can cause communication problems with the jtag
+	# adapter.  Also since this call can be made following a "reset init" where fast memory accesses
+	# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
+	# jtag speed without causing GDB keep alive problem.
+
+	arm7_9 fast_memory_access disable
+	adapter speed 2                 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+	halt                            ;# Make sure processor is halted, or error will result in following steps.
+	wait_halt 10000
+	mww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.
+}
+
+proc at91sam9g20_reset_init { } {
+
+	# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
+	# a number of steps that must be carefully performed.  The process outline below follows the
+	# recommended procedure outlined in the AT91SAM9G20 technical manual.
+	#
+	# Several key and very important things to keep in mind:
+	# The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This
+	# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
+	# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+	mww 0xfffffd44 0x00008000	;# WDT_MR : disable watchdog.
+
+	# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
+	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
+
+	mww 0xfffffc20 0x00004001
+	while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
+
+	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
+	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+	mww 0xfffffc28 0x202a3f01
+	while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
+
+	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00000101
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Now change PMC_MCKR register to select PLLA.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00001302
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Processor and master clocks are now operating and stable at maximum frequency possible:
+	#	-> MCLK = 132.096 MHz
+	#	-> PCLK = 396.288 MHz
+
+	# Switch over to adaptive clocking.
+
+	adapter speed 0
+
+	# Enable faster DCC downloads and memory accesses.
+
+	arm7_9 dcc_downloads enable
+	arm7_9 fast_memory_access enable
+
+	# To be able to use external SDRAM, several peripheral configuration registers must
+	# be modified.  The first change is made to PIO_ASR to select peripheral functions
+	# for D15 through D31.  The second change is made to the PIO_PDR register to disable
+	# this for D15 through D31.
+
+	mww 0xfffff870 0xffff0000
+	mww 0xfffff804 0xffff0000
+
+	# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+	# using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
+	# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+	mww 0xffffef1c 0x000100a
+
+	# The AT91SAM9G20-EK evaluation board has built-in NandFlash.  The exact physical timing characteristics
+	# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+	# a number of registers.  The first step involves setting up the general I/O pins on the processor
+	# to be able to interface and support the external memory.
+
+	mww 0xfffffc10 0x00000010	;# PMC_PCER : enable PIOC clock
+	mww 0xfffff800 0x00006000	;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+	mww 0xfffff810 0x00004000	;# PIOC_OER : enable output on 14
+	mww 0xfffff814 0x00002000	;# PIOC_ODR : disable output on 13
+    	mww 0xfffff830 0x00004000	;# PIOC_SODR : set 14 to disable NAND
+
+	# The exact physical timing characteristics for the memory type used on the current board
+	# (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
+	# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
+	# is a little tedious to do here.  If you have questions about how to do this, Atmel has
+	# a decent application note #6255B that covers this process.
+
+	mww 0xffffec30 0x00020002	;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
+	mww 0xffffec34 0x04040404	;# SMC_PULSE3 : 4 clock cycle pulse for all signals
+	mww 0xffffec38 0x00070006	;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
+	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+
+	mww 0xffffe800 0x00000001	;# ECC_CR : reset the ECC parity registers
+	mww 0xffffe804 0x00000002	;# ECC_MR : page size is 2112 words (word is 8 bits)
+
+	# Identify NandFlash bank 0.
+
+	nand probe nandflash_cs3
+
+	# The AT91SAM9G20-EK evaluation board has built-in serial data flash also.
+
+	# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
+	# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference
+	# for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
+	# into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock
+	# of 132.096 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:
+	#
+	#	CAS latency = 3 cycles
+	#	TXSR = 10 cycles
+	#	TRAS = 6 cycles
+	#	TRCD = 3 cycles
+	#	TRP = 3 cycles
+	#	TRC = 9 cycles
+	#	TWR = 2 cycles
+	#	9 column, 13 row, 4 banks
+	#	refresh equal to or less then 7.8 us for commercial/industrial rated devices
+	#
+	#	Thus SDRAM_CR = 0xa6339279
+
+	mww 0xffffea08 0xa6339279
+
+	# Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
+	# the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x00000001
+	mww 0x20000000 0
+
+	# Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
+	# value into the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x00000002
+	mww 0x20000000 0
+
+	# Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing
+	# zero values eight times into the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+
+	# Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
+	# the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x3
+	mww 0x20000000 0
+
+	# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting
+	# memory location for the SDRAM.
+
+	mww 0xffffea00 0x0
+	mww 0x20000000 0
+
+	# Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
+
+	mww 0xffffea04 0x0000039c
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_at91sam7s-ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_at91sam7s-ek.cfg
new file mode 100644
index 0000000..9cf85df
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_at91sam7s-ek.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Atmel AT91SAM7S-EK
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
+
+set CHIPNAME at91sam7s256
+
+source [find target/at91sam7sx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_at91sam9260-ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_at91sam9260-ek.cfg
new file mode 100644
index 0000000..56fce3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_at91sam9260-ek.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Atmel AT91SAM9260-EK eval board
+#
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9260.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
+        sleep 10                          ;# wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	mww 0xfffff870 0xffff0000         ;# PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         ;# PIO_PDR  : Disable PIO function for D15..D31
+
+        mww 0xffffef1c 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_at91sam9rl-ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_at91sam9rl-ek.cfg
new file mode 100644
index 0000000..cc3d974
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_at91sam9rl-ek.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+#
+# Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
+#
+# Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9rl.cfg]
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc28 0x2031bf03         ;# CKGR_PLLR: Set PLL Register for 200 MHz
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLL is selected (100 MHz)
+        sleep 10                          ;# wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	mww 0xfffff670 0xffff0000         ;# PIO_ASR  : Select peripheral function for D16..D31 (PIOB)
+        mww 0xfffff604 0xffff0000         ;# PIO_PDR  : Disable PIO function for D16..D31 (PIOB)
+
+        mww 0xffffef20 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3n_ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3n_ek.cfg
new file mode 100644
index 0000000..af2fd95
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3n_ek.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration for Atmel's SAM3N-EK
+#
+
+reset_config srst_only
+
+set CHIPNAME at91sam3n4c
+
+adapter speed 32
+
+source [find target/at91sam3nXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3s_ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3s_ek.cfg
new file mode 100644
index 0000000..136e31d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3s_ek.cfg
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam3sXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3u_ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3u_ek.cfg
new file mode 100644
index 0000000..c308003
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3u_ek.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam3u4e.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3x_ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3x_ek.cfg
new file mode 100644
index 0000000..c321cfb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam3x_ek.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam3ax_8x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4e_ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4e_ek.cfg
new file mode 100644
index 0000000..61191a9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4e_ek.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an SAM4E-EK board with a single SAM4E16 chip.
+# http://www.atmel.com/tools/sam4e-ek.aspx
+
+# chip name
+set CHIPNAME SAM4E16E
+
+source [find target/at91sam4sXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4l8_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4l8_xplained_pro.cfg
new file mode 100644
index 0000000..d0c4516
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4l8_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAM4L8 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAM4L8-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAM4LC8CA
+
+source [find target/at91sam4lXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4s_ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4s_ek.cfg
new file mode 100644
index 0000000..7e4bb83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4s_ek.cfg
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam4sXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4s_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4s_xplained_pro.cfg
new file mode 100644
index 0000000..92191c7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_sam4s_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAM4S Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAM4S-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAM4SD32C
+
+source [find target/at91sam4sd32x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samc20_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samc20_xplained_pro.cfg
new file mode 100644
index 0000000..3ac89a5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samc20_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMC20 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samc20j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samc21_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samc21_xplained_pro.cfg
new file mode 100644
index 0000000..5ad6ccf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samc21_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMC21 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMC21-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samc21j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd10_xplained_mini.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd10_xplained_mini.cfg
new file mode 100644
index 0000000..f9f1d24
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd10_xplained_mini.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMD10 Xplained mini evaluation kit.
+# http://www.atmel.com/tools/atsamd10-xmini.aspx
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd10d14
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd11_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd11_xplained_pro.cfg
new file mode 100644
index 0000000..724c921
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd11_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMD11 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd11d14
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd20_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd20_xplained_pro.cfg
new file mode 100644
index 0000000..1492958
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd20_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMD20 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMD20-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd20j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd21_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd21_xplained_pro.cfg
new file mode 100644
index 0000000..f55b6b9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samd21_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMD21 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd21j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_same70_xplained.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_same70_xplained.cfg
new file mode 100644
index 0000000..f20e2a3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_same70_xplained.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAME70 Xplained evaluation kit.
+# http://www.atmel.com/tools/ATSAME70-XPLD.aspx
+#
+# Connect using the EDBG chip on the dev kit over USB
+source [find interface/cmsis-dap.cfg]
+
+set CHIPNAME atsame70q21
+
+source [find target/atsamv.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samg53_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samg53_xplained_pro.cfg
new file mode 100644
index 0000000..060750c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samg53_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMG53 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMG53-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAMG53N19
+
+source [find target/at91samg5x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samg55_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samg55_xplained_pro.cfg
new file mode 100644
index 0000000..147dc73
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samg55_xplained_pro.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMG55 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMG55-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAMG55J19
+
+source [find target/at91samg5x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_saml21_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_saml21_xplained_pro.cfg
new file mode 100644
index 0000000..8e62eb2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_saml21_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAML21 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91saml21j18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samr21_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samr21_xplained_pro.cfg
new file mode 100644
index 0000000..cd6d28e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samr21_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMR21 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samr21g18
+
+source [find target/at91samdXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samv71_xplained_ultra.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samv71_xplained_ultra.cfg
new file mode 100644
index 0000000..9368f61
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/atmel_samv71_xplained_ultra.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Atmel SAMV71 Xplained Ultra evaluation kit.
+# http://www.atmel.com/tools/ATSAMV71-XULT.aspx
+#
+# To connect using the EDBG chip on the dev kit over USB, you will
+# first need to source [find interface/cmsis-dap.cfg]
+# however, since this board also has a SWD+ETM connector, we don't
+# automatically source that file here.
+
+set CHIPNAME samv71
+
+source [find target/atsamv.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/avnet_ultrazed-eg.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/avnet_ultrazed-eg.cfg
new file mode 100644
index 0000000..6701fd1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/avnet_ultrazed-eg.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# AVNET UltraZED EG StarterKit
+# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2
+#
+source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
+# jtag transport only
+transport select jtag
+# reset lines are not wired
+reset_config none
+
+# slow default clock
+adapter speed 1000
+
+set CHIPNAME uscale
+
+source [find target/xilinx_zynqmp.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/balloon3-cpu.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/balloon3-cpu.cfg
new file mode 100644
index 0000000..3ee840b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/balloon3-cpu.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
+# The board has separate JTAG ports for cpu and CPLD/FPGA devices
+# Chaining is done on IO interfaces if desired.
+
+source [find target/pxa270.cfg]
+
+# The board supports separate reset lines
+# Override this in the interface config for parallel dongles
+reset_config trst_and_srst separate
+
+# flash bank       
+# 29LV650 64Mbit Flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bcm28155_ap.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bcm28155_ap.cfg
new file mode 100644
index 0000000..99da948
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bcm28155_ap.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BCM28155_AP
+
+adapter speed 20000
+
+set CHIPNAME bcm28155
+source [find target/bcm281xx.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bemicro_cycloneiii.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bemicro_cycloneiii.cfg
new file mode 100644
index 0000000..3c92b50
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bemicro_cycloneiii.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BeMicro Cyclone III
+
+
+adapter driver ftdi
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+ftdi vid_pid 0x0403 0xa4a0
+reset_config none
+transport select jtag
+
+adapter speed 10000
+
+source [find fpga/altera-cycloneiii.cfg]
+
+#quartus_cpf --option=bitstream_compression=off -c output_files\cycloneiii_blinker.sof cycloneiii_blinker.rbf
+
+#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load cycloneiii.pld cycloneiii_blinker.rbf"
+# "ipdbg create-hub cycloneiii.ipdbghub -tap cycloneiii.tap -ir 0x00e"
+# "cycloneiii.ipdbghub ipdbg start -tool 0 -port 5555"
+
+
+set JTAGSPI_CHAIN_ID cycloneiii.pld
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bluefield.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bluefield.cfg
new file mode 100644
index 0000000..e96a74e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bluefield.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration for BlueField SoC.
+#
+
+source [find interface/rshim.cfg]
+source [find target/bluefield.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bt-homehubv1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bt-homehubv1.cfg
new file mode 100644
index 0000000..bbb6fa4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/bt-homehubv1.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# BT HomeHub v1
+#
+
+set partition_list {
+    CFE       { Bootloader              0xbe400000 0x00020000 }
+    firmware  { "Kernel+rootfs"         0xbe420000 0x007d0000 }
+    fisdir    { "FIS Directory"         0xbebf0000 0x0000f000 }
+    nvram     { "Config space"          0xbebff000 0x00001000 }
+}
+
+source [find target/bcm6348.cfg]
+
+set _FLASHNAME $_CHIPNAME.norflash
+flash bank $_FLASHNAME cfi 0xbe400000 0x00800000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/calao-usb-a9260.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/calao-usb-a9260.cfg
new file mode 100644
index 0000000..52fede0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/calao-usb-a9260.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# CALAO Systems USB-A9260 (C01 and C02)
+
+adapter driver ftdi
+ftdi device_desc "USB-A9260"
+ftdi vid_pid 0x0403 0x6001 0x0403 0x6010
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+
+transport select jtag
+
+source [find target/at91sam9260.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/calao-usb-a9g20-c01.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/calao-usb-a9g20-c01.cfg
new file mode 100644
index 0000000..d201786
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/calao-usb-a9g20-c01.cfg
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# CALAO Systems USB-A9G20-C01
+# Authors: Gregory Hermant, Jean-Christophe PLAGNIOL-VILLARD, Wolfram Sang
+
+adapter driver ftdi
+ftdi device_desc "USB-A9G20"
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+
+transport select jtag
+
+source [find target/at91sam9g20.cfg]
+source [find mem_helper.tcl]
+
+proc at91sam9g20_reset_start { } {
+
+        # Make sure that the jtag is running slow, since there are a number of different ways the board
+        # can be configured coming into this state that can cause communication problems with the jtag
+        # adapter.  Also since this call can be made following a "reset init" where fast memory accesses
+        # are enabled, Need to temporarily shut this down so that the RSTC_MR register can be written at slower
+        # jtag speed without causing GDB keep alive problem.
+
+        arm7_9 fast_memory_access disable
+        adapter speed 2                   ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+        halt 0                            ;# Make sure processor is halted, or error will result in following steps.
+        wait_halt 10000
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+proc at91sam9g20_reset_init { } {
+
+        # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
+        # a number of steps that must be carefully performed.  The process outline below follows the
+        # recommended procedure outlined in the AT91SAM9G20 technical manual.
+        #
+        # Several key and very important things to keep in mind:
+        # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This
+        # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
+        # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+        mww 0xfffffd44 0x00008000      ;# WDT_MR : disable watchdog.
+
+        # Set oscillator bypass bit (12.00 MHz external oscillator) in CKGR_MOR register.
+
+        mww 0xfffffc20 0x00000002
+
+        # Set PLLA Register for 798.000 MHz (divider: bypass, multiplier: 132).
+        # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+        mww 0xfffffc28 0x20843F02
+        while { [expr { [mrw 0xfffffc68] & 0x02 } ] != 2 } { sleep 1 }
+
+        # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+        # Wait for MCKRDY signal from PMC_SR to assert.
+
+        mww 0xfffffc30 0x00001300
+        while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
+
+        # Now change PMC_MCKR register to select PLLA.
+        # Wait for MCKRDY signal from PMC_SR to assert.
+
+        mww 0xfffffc30 0x00001302
+        while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
+
+        # Processor and master clocks are now operating and stable at maximum frequency possible:
+        #       -> MCLK = 133.000 MHz
+        #       -> PCLK = 400.000 MHz
+
+        # Switch to fast JTAG speed
+
+        adapter speed 9500
+
+        # Enable faster DCC downloads.
+
+        arm7_9 dcc_downloads enable
+        arm7_9 fast_memory_access enable
+
+        # To be able to use external SDRAM, several peripheral configuration registers must
+        # be modified.  The first change is made to PIO_ASR to select peripheral functions
+        # for D15 through D31.  The second change is made to the PIO_PDR register to disable
+        # this for D15 through D31.
+
+        mww 0xfffff870 0xffff0000
+        mww 0xfffff804 0xffff0000
+
+        # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+        # using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
+        # the board to the 1.8V VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+        mww 0xffffef1c 0x000000a
+
+        # The USB-A9G20 Embedded computer has built-in NandFlash.  The exact physical timing characteristics
+        # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+        # four registers in order:  SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
+
+        mww 0xffffec30 0x00020002
+        mww 0xffffec34 0x04040404
+        mww 0xffffec38 0x00070007
+        mww 0xffffec3c 0x00030003
+
+        # Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
+        # are based on 2 x Micron LPSDRAM MT48H16M16LFBF-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference
+        # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
+        # into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock
+        # of 133.000 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:
+        #
+        #       CAS latency = 3 cycles
+        #       TXSR = 10 cycles
+        #       TRAS = 6 cycles
+        #       TRCD = 3 cycles
+        #       TRP = 3 cycles
+        #       TRC = 9 cycles
+        #       TWR = 2 cycles
+        #       9 column, 13 row, 4 banks
+        #       refresh equal to or less then 7.8 us for commercial/industrial rated devices
+        #
+        #       Thus SDRAM_CR = 0xa6339279
+
+        mww 0xffffea08 0xa6339279
+
+        # Memory Device Type: SDRAM (low-power would be 0x1)
+        mww 0xffffea24 0x00000000
+
+        # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
+        # the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x00000001
+        mww 0x20000000 0
+
+        # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
+        # value into the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x00000002
+        mww 0x20000000 0
+
+        # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing
+        # zero values eight times into the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x4
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+
+        # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
+        # the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x3
+        mww 0x20000000 0
+
+        # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting
+        # memory location for the SDRAM.
+
+        mww 0xffffea00 0x0
+        mww 0x20000000 0
+
+        # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
+
+        mww 0xffffea04 0x0000039c
+}
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
+$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/certuspro_evaluation.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/certuspro_evaluation.cfg
new file mode 100644
index 0000000..ba2f17c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/certuspro_evaluation.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# https://www.latticesemi.com/products/developmentboardsandkits/certuspro-nx-versa-board
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+reset_config none
+transport select jtag
+adapter speed 10000
+
+source [find fpga/lattice_certuspro.cfg]
+
+#openocd -f board/certuspro_evaluation.cfg -c "init" -c "pld load certuspro.pld shared_folder/certuspro_blinker_impl_1.bit"
+
+set JTAGSPI_CHAIN_ID certuspro.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init certuspro.pld "" -1
+#jtagspi_program shared_folder/certuspro_blinker_impl1.bit 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/colibri.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/colibri.cfg
new file mode 100644
index 0000000..b44985d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/colibri.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Toradex Colibri PXA270
+source [find target/pxa270.cfg]
+reset_config trst_and_srst srst_push_pull
+adapter srst pulse_width 40
+
+# CS0 -- one bank of CFI flash, 32 MBytes
+# the bank is 32-bits wide, two 16-bit chips in parallel
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/crossbow_tech_imote2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/crossbow_tech_imote2.cfg
new file mode 100644
index 0000000..07ce8c7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/crossbow_tech_imote2.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Crossbow Technology iMote2
+
+set  CHIPNAME imote2
+source [find target/pxa270.cfg]
+
+# longer-than-normal reset delay
+adapter srst delay 800
+
+reset_config trst_and_srst separate
+
+# works for P30 flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/csb337.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/csb337.cfg
new file mode 100644
index 0000000..f75abbe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/csb337.cfg
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Cogent CSB337
+#   http://cogcomp.com/csb_csb337.htm
+
+source [find target/at91rm9200.cfg]
+
+# boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+
+# ETM9 trace port connector present on this board, 16 data pins.
+if { [info exists ETM_DRIVER] } {
+	etm config $_TARGETNAME 16 normal half $ETM_DRIVER
+	# OpenOCD may someday support a real trace port driver...
+	# system config file would need to configure it.
+} else {
+	etm config $_TARGETNAME 16 normal half dummy
+	etm_dummy config $_TARGETNAME
+}
+
+proc csb337_clk_init { } {
+	# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
+	adapter speed 8
+
+	# CKGR_MOR:  start main oscillator (3.6864 MHz)
+	mww 0xfffffc20 0xff01
+	sleep 10
+
+	# CKGR_PLLAR:  start PLL A for CPU and peripherals (184.32 MHz)
+	mww 0xfffffc28 0x20313e01
+	# CKGR_PLLBR:  start PLL B for USB timing (96 MHz, with div2)
+	mww 0xfffffc2c 0x12703e18
+	# let PLLs lock
+	sleep 10
+
+	# PMC_MCKR:  switch to CPU clock = PLLA, master clock = CPU/4
+	mww 0xfffffc30 0x0302
+	sleep 20
+
+	# CPU is in Normal Mode ... allows faster JTAG clock speed
+	adapter speed 40000
+}
+
+proc csb337_nor_init { } {
+	# SMC_CSR0:  adjust timings (10 wait states)
+	mww 0xffffff70 0x1100318a
+
+	flash probe 0
+}
+
+proc csb337_sdram_init { } {
+	# enable PIOC clock
+	mww 0xfffffc10 0x0010
+	# PC31..PC16 are D31..D16, with internal pullups like D15..D0
+	mww 0xfffff870 0xffff0000
+	mww 0xfffff874 0x0
+	mww 0xfffff804 0xffff0000
+
+	# SDRC_CR: set timings
+	mww 0xffffff98 0x2188b0d5
+
+	# SDRC_MR: issue all banks precharge to SDRAM
+	mww 0xffffff90 2
+	mww 0x20000000 0
+
+	# SDRC_MR: 8 autorefresh cycles
+	mww 0xffffff90 4
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+
+	# SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
+	mww 0xffffff90 3
+	mww 0x20000080 0
+
+	# SDRC_TR: set refresh rate
+	mww 0xffffff94 0x200
+	mww 0x20000000 0
+
+	# SDRC_MR: normal mode, 32 bit bus
+	mww 0xffffff90 0
+	mww 0x20000000 0
+}
+
+# The rm9200 chip has just been reset.  Bring it up far enough
+# that we can write flash or run code from SDRAM.
+proc csb337_reset_init { } {
+	csb337_clk_init
+
+	# EBI_CSA:  CS0 = NOR, CS1 = SDRAM
+	mww 0xffffff60 0x02
+
+	csb337_nor_init
+	csb337_sdram_init
+
+	# Update CP15 control register ... we don't seem to be able to
+	# read/modify/write its value through a TCL variable, so just
+	# write it.  Fields are zero unless listed here ... and note
+	# that OpenOCD numbers this register "2", not "1" (!).
+	#
+	#  - Core to use Async Clocking mode (so it uses 184 MHz most
+	#    of the time instead of limiting to the master clock rate):
+	#	iA(31) = 1, nF(30) = 1
+	#  - Icache on (it's disabled now, slowing i-fetches)
+	#	I(12) = 1
+	#  - Reserved/ones
+	#	6:3 = 1
+	arm920t cp15 2 0xc0001078
+}
+
+$_TARGETNAME configure -event reset-init {csb337_reset_init}
+
+arm7_9 fast_memory_access enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/csb732.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/csb732.cfg
new file mode 100644
index 0000000..6df1750
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/csb732.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Cogent CSB732 board has a single i.MX35 chip
+source [find target/imx35.cfg]
+
+# Determined by trial and error
+reset_config trst_and_srst combined
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { csb732_init }
+
+# Bare-bones initialization of core clocks and SDRAM
+proc csb732_init { } {
+
+	# Disable fast writing only for init
+	memwrite burst disable
+
+	# All delay loops are omitted.
+	# We assume the interpreter latency is enough.
+
+	# Allow access to all coprocessors
+	arm mcr 15 0 15 1 0 0x2001
+
+	# Disable MMU, caches, write buffer
+	arm mcr 15 0 1 0 0 0x78
+
+	# Grant manager access to all domains
+	arm mcr 15 0 3 0 0 0xFFFFFFFF
+
+	# Set ARM clock to 532 MHz, AHB to 133 MHz
+	mww 0x53F80004 0x1000
+
+	# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
+	mww 0x53F8001C 0xB2C01
+
+	set ESDMISC 0xB8001010
+	set ESDCFG0 0xB8001004
+	set ESDCTL0 0xB8001000
+
+	# Enable DDR
+	mww $ESDMISC 0x4
+
+	# Timing
+	mww $ESDCFG0 0x007fff3f
+
+	# CS0
+	mww $ESDCTL0 0x92120080
+
+	# Precharge all dummy write
+	mww 0x80000400 0
+
+	# Enable CS) auto-refresh
+	mww $ESDCTL0 0xA2120080
+
+	# Refresh twice (dummy writes)
+	mww 0x80000000 0
+	mww 0x80000000 0
+
+	# Enable CS0 load mode register
+	mww $ESDCTL0 0xB2120080
+
+	# Dummy writes
+	mwb 0x80000033 0x01
+	mwb 0x81000000 0x01
+
+	mww $ESDCTL0 0x82226080
+	mww 0x80000000 0
+
+	# Re-enable fast writing
+	memwrite burst enable
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/da850evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/da850evm.cfg
new file mode 100644
index 0000000..12de3a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/da850evm.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#DA850 EVM board
+# http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939
+# http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
+
+source [find target/omapl138.cfg]
+
+reset_config trst_and_srst separate
+
+#currently any pinmux/timing must be setup by UBL before openocd can do debug
+#TODO: implement pinmux/timing on reset like in board/dm365evm.cfg
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digi_connectcore_wi-9c.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digi_connectcore_wi-9c.cfg
new file mode 100644
index 0000000..0ff4742
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digi_connectcore_wi-9c.cfg
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target: DIGI ConnectCore Wi-9C
+######################################
+
+reset_config trst_and_srst
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME ns9360
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+  # This config file was defaulting to big endian..
+   set  _ENDIAN big
+}
+
+
+# What's a good fallback frequency for this board if RCLK is
+# not available??
+jtag_rclk 1000
+
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926031
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+adapter srst delay 200
+jtag_ntrst_delay 0
+
+
+######################
+# Target configuration
+######################
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x90600104 0x33313333
+	mww 0xA0700000 0x00000001  ;# Enable the memory controller.
+	mww 0xA0700024 0x00000006  ;# Set the refresh counter 6
+	mww 0xA0700028 0x00000001  ;#
+	mww 0xA0700030 0x00000001  ;# Set the precharge period
+	mww 0xA0700034 0x00000004  ;# Active to precharge command period is 16 clock cycles
+	mww 0xA070003C 0x00000001  ;# tAPR
+	mww 0xA0700040 0x00000005  ;# tDAL
+	mww 0xA0700044 0x00000001  ;# tWR
+	mww 0xA0700048 0x00000006  ;# tRC 32 clock cycles
+	mww 0xA070004C 0x00000006  ;# tRFC 32 clock cycles
+	mww 0xA0700054 0x00000001  ;# tRRD
+	mww 0xA0700058 0x00000001  ;# tMRD
+	mww 0xA0700100 0x00004280  ;# Dynamic Config 0 (cs4)
+	mww 0xA0700120 0x00004280  ;# Dynamic Config 1 (cs5)
+	mww 0xA0700140 0x00004280  ;# Dynamic Config 2 (cs6)
+	mww 0xA0700160 0x00004280  ;# Dynamic Config 3 (cs7)
+	#
+	mww 0xA0700104 0x00000203  ;# CAS latency is 2 at 100 MHz
+	mww 0xA0700124 0x00000203  ;# CAS latency is 2 at 100 MHz
+	mww 0xA0700144 0x00000203  ;# CAS latency is 2 at 100 MHz
+	mww 0xA0700164 0x00000203  ;# CAS latency is 2 at 100 MHz
+	#
+	mww 0xA0700020 0x00000103  ;# issue SDRAM PALL command
+	#
+	mww 0xA0700024 0x00000001  ;# Set the refresh counter to be as small as possible
+	#
+	# Add some dummy writes to give the SDRAM time to settle, it needs two
+	# AHB clock cycles, here we poke in the debugger flag, this lets
+	# the software know that we are in the debugger
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	#
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	#
+	mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30
+	mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command
+	#
+	# Next we perform a read of RAM.
+	# mw = move word.
+	mdw 0x00022000
+	# mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
+	#
+	mww 0xA0700020 0x00000003   ;# issue SDRAM NORMAL command
+	mww 0xA0700100 0x00084280   ;# Enable buffer access
+	mww 0xA0700120 0x00084280   ;# Enable buffer access
+	mww 0xA0700140 0x00084280   ;# Enable buffer access
+	mww 0xA0700160 0x00084280   ;# Enable buffer access
+
+	#Set byte lane state (static mem 1)"
+	mww 0xA0700220 0x00000082
+	#Flash Start
+	mww 0xA09001F8 0x50000000
+	#Flash Mask Reg
+	mww 0xA09001FC 0xFF000001
+	mww 0xA0700028 0x00000001
+
+	#  RAMAddr = 0x00020000
+	#  RAMSize = 0x00004000
+
+	# Set the processor mode
+	reg cpsr 0xd3
+}
+
+$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
+
+#####################
+# Flash configuration
+#####################
+
+#M29DW323DB - not working
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_analog_discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_analog_discovery.cfg
new file mode 100644
index 0000000..1bc239b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_analog_discovery.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent Analog Discovery
+#
+# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,842,1018&Prod=ANALOG-DISCOVERY
+#
+# Config is based on data from
+# https://github.com/bvanheu/urjtag-ad/commit/8bd883ee01d134f94b79cbbd00df42cd03bafd71
+#
+
+adapter driver ftdi
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6014
+
+ftdi layout_init 0x8008 0x800b
+
+adapter speed 25000
+
+source [find cpld/xilinx-xc6s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_anvyl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_anvyl.cfg
new file mode 100644
index 0000000..e820028
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_anvyl.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Digilent Anvyl with Xilinx Spartan-6 FPGA
+# https://digilent.com/reference/programmable-logic/anvyl/start
+# Almost the same setup as the Digilent Nexys Video board or the Digilent HS1
+# adapter.
+adapter driver ftdi
+adapter speed 30000
+
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6010
+
+# channel 0 is the JTAG channel
+# channel 1 is a user serial channel to pins on the FPGA
+ftdi channel 0
+
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0088 0x008b
+reset_config none
+
+# Enable sampling on falling edge for high JTAG speeds.
+ftdi tdo_sample_edge falling
+
+transport select jtag
+
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_atlys.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_atlys.cfg
new file mode 100644
index 0000000..568253b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_atlys.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://digilentinc.com/atlys/
+#
+# The Digilent Atlys normally requires proprietary tools to program and will
+# enumerate as:
+#   ID 1443:0007 Digilent Development board JTAG
+#
+# However, the ixo-usb-jtag project provides an alternative open firmware for
+# the on board programmer. When using this firmware the board will then
+# enumerate as:
+#   ID 16c0:06ad Van Ooijen Technische Informatica
+# (With SerialNumber == hw_nexys)
+#
+# See the interface/usb-jtag.cfg for more information.
+
+source [find interface/usb-jtag.cfg]
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_cmod_s7.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_cmod_s7.cfg
new file mode 100644
index 0000000..4fa45a1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_cmod_s7.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# digilent CMOD S7
+# https://digilent.com/reference/programmable-logic/cmod-s7/reference-manual
+
+
+adapter driver ftdi
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+ftdi vid_pid 0x0403 0x6010
+reset_config none
+transport select jtag
+
+adapter speed 10000
+
+source [find cpld/xilinx-xc7.cfg]
+
+# "ipdbg create-hub xc7.ipdbghub -tap xc7.tap -ir 0x02"
+# "xc7.ipdbghub ipdbg start -tool 0 -port 5555"
+#openocd -f board/digilent_cmod_s7.cfg -c "init" -c "pld load xc7.pld shared_folder/cmod_s7_fast.bit"
+
+set JTAGSPI_CHAIN_ID xc7.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init xc7.pld "shared_folder/bscan_spi_xc7s25.bit" 0xab
+#jtagspi_program shared_folder/cmod_s7_fast.bit 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_nexys2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_nexys2.cfg
new file mode 100644
index 0000000..c1c5b2a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_nexys2.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# https://digilent.com/reference/programmable-logic/nexys-2/start
+#
+# The Digilent Nexy2 normally requires proprietary tools to program and will
+# enumerate as:
+#   ID 1443:0005 1443 ONBOARD USB
+#
+# However, the ixo-usb-jtag project provides an alternative open firmware for
+# the on board programmer. When using this firmware the board will then
+# enumerate as:
+#   ID 16c0:06ad ixo.de USB-JTAG-IF (With SerialNumber == hw_nexys)
+#
+# See the interface/usb-jtag.cfg for more information.
+
+source [find interface/usb-jtag.cfg]
+source [find cpld/xilinx-xcf-s.cfg]
+source [find fpga/xilinx-xc3s.cfg]
+
+# Usage:
+#
+# Load Bitstream into FPGA:
+#    openocd -f board/digilent_nexys2.cfg -c "init;\
+#    pld load 0 bitstream.bit;\
+#    shutdown"
+
+# Read Unique Device Identifier (DNA):
+#    openocd -f board/digilent_nexys2.cfg -c "init;\
+#    xilinx_print_dna [xc3s_get_dna xc3s.tap];\
+#    shutdown"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_nexys_video.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_nexys_video.cfg
new file mode 100644
index 0000000..b60ec91
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_nexys_video.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Digilent Nexys Video with Xilinx Artix-7 FPGA
+# https://reference.digilentinc.com/programmable-logic/nexys-video/start
+
+adapter driver ftdi
+adapter speed 30000
+
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6010
+
+# channel 0 is dedicated for Digilent's DPTI Interface
+# channel 1 is used for JTAG
+ftdi channel 1
+
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0088 0x008b
+reset_config none
+
+# Enable sampling on falling edge for high JTAG speeds.
+ftdi tdo_sample_edge falling
+
+transport select jtag
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_zedboard.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_zedboard.cfg
new file mode 100644
index 0000000..010e8c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/digilent_zedboard.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent Zedboard Rev.C, Rev.D with Xilinx Zynq chip
+#
+# http://zedboard.com/product/zedboard
+#
+
+source [find interface/ftdi/digilent_jtag_smt2.cfg]
+
+reset_config srst_only srst_push_pull
+
+source [find target/zynq_7000.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/diolan_lpc4350-db1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/diolan_lpc4350-db1.cfg
new file mode 100644
index 0000000..c55621d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/diolan_lpc4350-db1.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Diolan LPC-4350-DB1 development board
+#
+
+set CHIPNAME lpc4350
+
+source [find target/lpc4350.cfg]
+
+flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/diolan_lpc4357-db1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/diolan_lpc4357-db1.cfg
new file mode 100644
index 0000000..155328a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/diolan_lpc4357-db1.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Diolan LPC-4357-DB1 development board
+#
+
+set CHIPNAME lpc4357
+
+source [find target/lpc4357.cfg]
+
+flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dk-tm4c129.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dk-tm4c129.cfg
new file mode 100644
index 0000000..27bd432
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dk-tm4c129.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti_dk-tm4c129.cfg"
+
+source [find board/ti_dk-tm4c129.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dm355evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dm355evm.cfg
new file mode 100644
index 0000000..0dbffa8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dm355evm.cfg
@@ -0,0 +1,203 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# DM355 EVM board
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
+#   http://c6000.spectrumdigital.com/evmdm355/
+
+source [find target/ti_dm355.cfg]
+
+reset_config trst_and_srst separate
+
+# NOTE:  disable or replace this call to dm355evm_init if you're
+# debugging new UBL code from SRAM.
+$_TARGETNAME configure -event reset-init { dm355evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm355evm_init {} {
+	global dm355
+
+	echo "Initialize DM355 EVM board"
+
+	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
+	jtag_rclk 1500
+
+	########################
+	# PLL1		= 432 MHz (/8, x144)
+	# ...SYSCLK1	= 216 MHz (/2)  ... ARM, MJCP
+	# ...SYSCLK2	= 108 MHz (/4)  ... Peripherals
+	# ...SYSCLK3	= 27  MHz (/16) ... VPBE, DAC
+	# ...SYSCLK4	= 108 MHz (/4)  ... VPSS
+	#	pll1.{prediv,div1,div2} are fixed
+	#	pll1.postdiv set in MISC (for *this* speed grade)
+
+	set addr [dict get $dm355 pllc1]
+	set pll_divs [dict create]
+	dict set pll_divs div3 16
+	dict set pll_divs div4 4
+	pll_v02_setup $addr 144 $pll_divs
+
+	# ARM is now running at 216 MHz, so JTAG can go faster
+	jtag_rclk 20000
+
+	########################
+	# PLL2		= 342 MHz (/8, x114)
+	# ....SYSCLK1	= 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock
+	#	pll2.{postdiv,div1} are fixed
+
+	set addr [dict get $dm355 pllc2]
+	set pll_divs [dict create]
+	dict set pll_divs div1 1
+	dict set pll_divs prediv 8
+	pll_v02_setup $addr 114 $pll_divs
+
+	########################
+	# PINMUX
+
+	# All Video Inputs
+	davinci_pinmux $dm355 0 0x00007f55
+	# All Video Outputs
+	davinci_pinmux $dm355 1 0x00145555
+	# EMIFA (NOTE: more could be set up for use as GPIOs)
+	davinci_pinmux $dm355 2 0x00000c08
+	# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+	davinci_pinmux $dm355 3 0x1bff55ff
+	# MMC/SD0 instead of MS; SPI0
+	davinci_pinmux $dm355 4 0x00000000
+
+	########################
+	# PSC setup (minimal)
+
+	# DDR EMIF/13, AEMIF/14, UART0/19
+	psc_enable 13
+	psc_enable 14
+	psc_enable 19
+	psc_go
+
+	########################
+	# DDR2 EMIF
+
+	# VTPIOCR impedance calibration
+	set addr [dict get $dm355 sysbase]
+	set addr [expr {$addr + 0x70}]
+
+	# clear CLR, LOCK, PWRDN; wait a clock; set CLR
+	mmw $addr 0 0x20c0
+	mmw $addr 0x2000 0
+
+	# wait for READY
+        while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
+
+	# set IO_READY; then LOCK and PWRSAVE; then PWRDN
+	mmw $addr 0x4000 0
+	mmw $addr 0x0180 0
+	mmw $addr 0x0040 0
+
+	# NOTE:  this DDR2 initialization sequence borrows from
+	# both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
+
+	# reset (then re-enable) DDR controller
+	psc_reset 13
+	psc_go
+	psc_enable 13
+	psc_go
+
+	# now set it up for Micron MT47H64M16HR-37E @ 171 MHz
+
+	set addr [dict get $dm355 ddr_emif]
+
+	# DDRPHYCR1
+	mww [expr {$addr + 0xe4}] 0x50006404
+
+	# PBBPR -- burst priority
+	mww [expr {$addr + 0x20}] 0xfe
+
+	# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
+	mmw [expr {$addr + 0x08}] 0x00800000 0
+	mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
+
+	# SDTIMR0, SDTIMR1
+	mww [expr {$addr + 0x10}] 0x2a923249
+	mww [expr {$addr + 0x14}] 0x4c17c763
+
+	# SDCR -- relock SDTIM*
+	mmw [expr {$addr + 0x08}] 0 0x00008000
+
+	# SDRCR -- refresh rate (171 MHz * 7.8usec)
+	mww [expr {$addr + 0x0c}] 1336
+
+	########################
+	# ASYNC EMIF
+
+	set addr [dict get $dm355 a_emif]
+
+	# slow/pessimistic timings
+	set nand_timings 0x40400204
+	# fast (25% faster page reads)
+	#set nand_timings 0x0400008c
+
+	# AWCCR
+	mww [expr {$addr + 0x04}] 0xff
+	# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
+	mww [expr {$addr + 0x10}] $nand_timings
+	# CS1 == dm9000 Ethernet
+	mww [expr {$addr + 0x14}] 0x00a00505
+	# NANDFCR -- only CS0 has NAND
+	mww [expr {$addr + 0x60}] 0x01
+
+	# default: both chipselects to the NAND socket are used
+	nand probe 0
+	nand probe 1
+
+	########################
+	# UART0
+
+	set addr [dict get $dm355 uart0]
+
+	# PWREMU_MGNT -- rx + tx in reset
+	mww [expr {$addr + 0x30}] 0
+
+	# DLL, DLH -- 115200 baud
+	mwb [expr {$addr + 0x20}] 0x0d
+	mwb [expr {$addr + 0x24}] 0x00
+
+	# FCR - clear and disable FIFOs
+	mwb [expr {$addr + 0x08}] 0x07
+	mwb [expr {$addr + 0x08}] 0x00
+
+	# IER - disable IRQs
+	mwb [expr {$addr + 0x04}] 0x00
+
+	# LCR - 8-N-1
+	mwb [expr {$addr + 0x0c}] 0x03
+
+	# MCR - no flow control or loopback
+	mwb [expr {$addr + 0x10}] 0x00
+
+	# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
+	mww [expr {$addr + 0x30}] 0xe001
+
+
+	########################
+
+	# turn on icache - set I bit in cp15 register c1
+	arm mcr 15 0 0 1 0 0x00051078
+}
+
+# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
+#
+# NOTE:  "hwecc4" here presumes that if you're using the standard 2GB NAND
+# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
+# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
+# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
+set _FLASHNAME $_CHIPNAME.boot
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
+
+# FIXME
+#  - support writing UBL with its header (new layout only with new ROMs)
+#  - support writing ABL/U-Boot with its header (new layout)
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dm365evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dm365evm.cfg
new file mode 100644
index 0000000..15db24c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dm365evm.cfg
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# DM365 EVM board -- Beta
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
+#   http://support.spectrumdigital.com/boards/evmdm365
+
+source [find target/ti_dm365.cfg]
+
+# NOTE:  in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
+# connector, so it doesn't affect generation of the reset signal.
+# Accordingly, resets require something else.  ICEpick could do it;
+# but its docs aren't generally available.
+#
+# At this writing, newer boards aren't available ... so assume no SRST.
+# Also ICEpick docs aren't available ... so we must use watchdog reset,
+# and hope the CPU isn't wedged or in a WFI loop (either of which can
+# block access to CPU and thus watchdog registers).
+
+reset_config trst_only
+$_TARGETNAME configure -event reset-assert "davinci_wdog_reset"
+
+# SW5.1 routes CS0: NAND vs OneNAND.
+# SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)
+# for boot-from-flash, those must agree with SW4.3:1 settings.
+
+if { [info exists CS0MODE] } {
+	# NAND or OneNAND
+	set CS0 $CS0MODE
+} else {
+	set CS0 ""
+	echo "WARNING:  CS0 configuration not known"
+	proc cs0_setup {a_emif} {}
+	proc flashprobe {} {}
+}
+
+set a_emif [dict get $dm365 a_emif]
+
+# As shipped:  boot from NAND.
+if { $CS0 == "NAND" } {
+	echo "CS0 NAND"
+
+	# NAND socket has two chipselects.  Default MT29F16G08FAA chip
+	# has 1GByte on each one.
+	# NOTE:  "hwecc4" here presumes that you're not updating anything
+	# that needs infix layout (e.g. UBL, old U-Boot, etc)
+	nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif
+	nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif
+
+	proc cs0_setup {a_emif} {
+		global dm365
+
+		# 8 bit EMIF
+		davinci_pinmux $dm365 2 0x00000016
+
+		# slow/pessimistic timings
+		set nand_timings 0x40400204
+		# fast (25% faster page reads)
+		#set nand_timings 0x0400008c
+
+		# CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
+		mww [expr {$a_emif + 0x10}] $nand_timings
+
+		# NANDFCR -- CS0 has NAND
+		mww [expr {$a_emif + 0x60}] 0x01
+	}
+	proc flashprobe {} {
+		nand probe 0
+		nand probe 1
+	}
+
+} elseif { $CS0 == "OneNAND" } {
+	echo "CS0 OneNAND"
+
+	# No support for this OneNAND in OpenOCD (yet) or Linux ...
+	# REVISIT OneNAND timings not verified to work!
+	echo "WARNING -- OneNAND not yet tested!"
+
+	proc cs0_setup {a_emif} {
+		global dm365
+
+		# 16 bit EMIF
+		davinci_pinmux $dm365 2 0x00000055
+
+		# CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
+		mww [expr {$a_emif + 0x10}] 0x00000001
+
+		# ONENANDCTRL -- CS0 has OneNAND, enable sync reads
+		mww [expr {$a_emif + 0x5c}] 0x0441
+	}
+	proc flashprobe {} { }
+}
+
+# NOTE:  disable or replace this call to dm365evm_init if you're
+# debugging new UBL/NANDboot code from SRAM.
+$_TARGETNAME configure -event reset-init { dm365evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm365evm_init {} {
+	global dm365
+
+	echo "Initialize DM365 EVM board"
+
+	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
+	adapter speed 1500
+
+	# FIXME -- PLL init
+
+	########################
+	# PINMUX setup
+
+	davinci_pinmux $dm365 0 0x00fd0000
+	davinci_pinmux $dm365 1 0x00145555
+	# mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand
+	davinci_pinmux $dm365 3 0x375affff
+	davinci_pinmux $dm365 4 0x55556555
+
+	########################
+	# PSC setup (minimal)
+
+	# DDR EMIF/13, AEMIF/14, UART0/19
+	psc_enable 13
+	psc_enable 14
+	psc_enable 19
+	psc_go
+
+	# FIXME setup DDR2 (needs PLL)
+
+	########################
+	# ASYNC EMIF
+
+	set a_emif [dict get $dm365 a_emif]
+
+	# AWCCR
+	mww [expr {$a_emif + 0x04}] 0xff
+	# CS0 == NAND or OneNAND
+	cs0_setup $a_emif
+	# CS1 == CPLD
+	mww [expr {$a_emif + 0x14}] 0x00a00505
+
+	# FIXME setup UART0
+
+	flashprobe
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dm6446evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dm6446evm.cfg
new file mode 100644
index 0000000..1236b86
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dm6446evm.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# DM6446 EVM board
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html
+#   http://c6000.spectrumdigital.com/davincievm/
+# EVM is just the board; buy that at Spectrum.
+# The "kit" from TI also has: video camera, LCD video monitor, more.
+
+source [find target/ti_dm6446.cfg]
+
+# J4 controls what CS2 hooks up to, usually NOR or NAND flash.
+# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings.
+# S3.3 controls AEMIF bus width.
+
+if { [info exists J4_OPTION] } {
+	# NOR, NAND, SRAM, ...
+	set CS2_MODE $J4_OPTION
+} else {
+	set CS2_MODE ""
+}
+
+# ARM boot:
+#  S3.1 = 0, S3.2 = 0	==> ROM/UBL boot via NAND (J4 == NAND)
+#  S3.1 = 1, S3.2 = 0	==> AEMIF boot (J4 == NOR or SRAM)
+#  S3.1 = 0, S3.2 = 1	==> ROM/UBL boot via HPI
+#  S3.1 = 1, S3.2 = 1	==> ROM/UBL boot via UART (J4 == don't care)
+# AEMIF bus width:
+#  S3.3 = 0		==> 8 bit bus width
+#  S3.3 = 1		==> 16 bit bus width
+# DSP boot:
+#  S3.4 = 0		==> controlled by ARM
+
+if { $CS2_MODE == "NOR" } {
+	# 16 Mbytes address space; 16 bit bus width
+	# (older boards used 32MB parts, with upper 16 MB unusable)
+	set _FLASHNAME $_CHIPNAME.flash
+	flash bank $_FLASHNAME cfi 0x02000000 0x01000000 2 2 $_TARGETNAME
+	proc flashprobe {} { flash probe 0 }
+} elseif { $CS2_MODE == "NAND" } {
+	# 64 Mbyte small page; 8 bit bus width
+	nand device davinci $_TARGETNAME 0x02000000 hwecc1 0x01e00000
+	proc flashprobe {} { nand probe 0 }
+} elseif { $CS2_MODE == "SRAM" } {
+	# 4 Mbyte address space; 16 bit bus width
+	# loaded via JTAG or HPI
+	proc flashprobe {} {}
+} else {
+	# maybe it's HPI boot?  can't tell...
+	echo "WARNING:  CS2/flash configuration not recognized"
+	proc flashprobe {} {}
+}
+
+# NOTE:  disable or replace this call to dm6446evm_init if you're
+# debugging new UBL code from SRAM (for NAND boot).
+$_TARGETNAME configure -event reset-init { dm6446evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm6446evm_init {} {
+
+	echo "Initialize DM6446 EVM board"
+
+	# FIXME initialize everything:
+	#  - PLL1
+	#  - PLL2
+	#  - PINMUX
+	#  - PSC
+	#  - DDR
+	#  - AEMIF
+	#  - UART0
+	#  - icache
+
+	flashprobe
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dp_busblaster_v3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dp_busblaster_v3.cfg
new file mode 100644
index 0000000..5599617
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dp_busblaster_v3.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Dangerous Prototypes - Bus Blaster
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+# To reprogram the on-board CPLD do:
+# openocd -f board/dp_busblaster_v3.cfg -c "adapter speed 1000; init; svf ; shutdown"
+#
+
+source [find interface/ftdi/dp_busblaster.cfg]
+ftdi channel 1
+
+jtag newtap xc2c32a tap -expected-id 0x06e1c093 -irlen 8
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dp_busblaster_v4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dp_busblaster_v4.cfg
new file mode 100644
index 0000000..2c2f0e9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dp_busblaster_v4.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Dangerous Prototypes - Bus Blaster
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+# The Bus Blaster has a configurable buffer between the FTDI FT2232H
+# and the JTAG header which allows it to emulate various debugger
+# types. This config works with KT-Link compatible implementation from
+# https://raw.githubusercontent.com/dergraaf/busblaster_v4/master/ktlink/ktlink.svf
+#
+# To reprogram the on-board CPLD do:
+# openocd -f board/dp_busblaster_v4.cfg -c "adapter speed 1000; init; svf ; shutdown"
+#
+
+source [find interface/ftdi/dp_busblaster.cfg]
+ftdi channel 1
+
+jtag newtap xc2c64a tap -expected-id 0x06e5c093 -irlen 8
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dptechnics_dpt-board-v1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dptechnics_dpt-board-v1.cfg
new file mode 100644
index 0000000..3ab2c68
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/dptechnics_dpt-board-v1.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Product page:
+# https://www.dptechnics.com/en/products/dpt-board-v1.html
+#
+# JTAG is a 5 pin array located close to main module in following order:
+# 1. JTAG TCK
+# 2. JTAG TDO
+# 3. JTAG TDI
+# 4. JTAG TMS
+# 5. GND	The GND is located near letter G of word JTAG on board.
+#
+# Two RST pins are connected to:
+# 1. GND
+# 2. GPIO11	this pin is located near letter R of word RST.
+#
+# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
+# with 10K resistor connected to V3.3 pin.
+#
+# This board is powered from micro USB connector. No real reset pin or button, for
+# example RESET_L is available.
+
+source [find target/atheros_ar9331.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	ar9331_25mhz_pll_init
+	sleep 1
+	ar9331_ddr2_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ecp5_evaluation.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ecp5_evaluation.cfg
new file mode 100644
index 0000000..71769f6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ecp5_evaluation.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Lattice ECP5 evaluation Kit
+# https://www.latticesemi.com/view_document?document_id=52479
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+reset_config none
+transport select jtag
+adapter speed 6000
+
+source [find fpga/lattice_ecp5.cfg]
+
+#openocd -f board/ecp5_evaluation.cfg -c "init" -c "pld load ecp5.pld shared_folder/ecp5_blinker_impl1.bit"
+#ipdbg create-hub ecp5.ipdbghub -tap ecp5.tap -ir 0x32
+#ecp5.ipdbghub ipdbg start -tool 0 -port 5555
+
+set JTAGSPI_CHAIN_ID ecp5.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init ecp5.pld "" -1
+#jtagspi_program shared_folder/ecp5_blinker_impl1_slow.bit 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/efikamx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/efikamx.cfg
new file mode 100644
index 0000000..9083543
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/efikamx.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Genesi USA EfikaMX
+#  http://www.genesi-usa.com/products/efika
+
+# Fall back to 6MHz if RTCK is not supported
+jtag_rclk 6000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 6000 }
+
+source [find target/imx51.cfg]
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/efm32.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/efm32.cfg
new file mode 100644
index 0000000..0ffab04
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/efm32.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for EFM32 boards with on-board SEGGER J-Link
+#
+# Tested with Tiny, Giant and Zero Gecko Starter Kit.
+#
+
+source [find interface/jlink.cfg]
+transport select swd
+adapter speed 1000
+
+set CHIPNAME efm32
+source [find target/efm32.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/eir.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/eir.cfg
new file mode 100644
index 0000000..d634249
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/eir.cfg
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Elector Internet Radio board
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+source [find target/at91sam7se512.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	# WDT_MR, disable watchdog
+	mww 0xFFFFFD44 0x00008000
+
+	# RSTC_MR, enable user reset
+	mww 0xfffffd08 0xa5000001
+
+	# CKGR_MOR
+	mww 0xFFFFFC20 0x00000601
+	sleep 10
+
+	# CKGR_PLLR
+	mww 0xFFFFFC2C 0x00481c0e
+	sleep 10
+
+	# PMC_MCKR
+	mww 0xFFFFFC30 0x00000007
+	sleep 10
+
+	# PMC_IER
+	mww 0xFFFFFF60 0x00480100
+
+	#
+	# Enable SDRAM interface.
+	#
+
+	# Enable SDRAM control at PIO A.
+	mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
+	mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
+
+	# Enable address bus (A0, A2-A11, A13-A17) at PIO B
+	mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
+	mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
+
+	# Enable 16 bit data bus at PIO C
+	mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
+	mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
+
+	# Enable SDRAM chip select
+	mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
+
+	# Set SDRAM characteristics in configuration register.
+	# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
+	mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
+	sleep 10
+
+	# Issue 16 bit SDRAM command: NOP
+	mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 16 bit SDRAM command: Precharge all
+	mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 8 auto-refresh cycles
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 16 bit SDRAM command: Set mode register
+	mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
+	mww 0x20000014 0xcafedede
+
+	# Set refresh rate count ???
+	mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
+
+	# Issue 16 bit SDRAM command: Normal mode
+	mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000180
+
+	#
+	# Enable external reset key.
+	#
+	mww 0xfffffd08 0xa5000001
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s1968.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s1968.cfg
new file mode 100644
index 0000000..c794a17
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s1968.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S1968 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s1968
+#
+
+# NOTE:  to use J-Link instead of the on-board interface,
+# you may also need to reduce adapter speed to be about 1200.
+# source [find interface/jlink.cfg]
+
+# include the FT2232 interface config for on-board JTAG interface
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# include the target config
+set WORKAREASIZE 0x2000
+set CHIPNAME lm3s1968
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s3748.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s3748.cfg
new file mode 100644
index 0000000..705cb64
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s3748.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris lm3s3748 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s3748
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# 20k working area
+set WORKAREASIZE 0x4000
+set CHIPNAME lm3s3748
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s6965.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s6965.cfg
new file mode 100644
index 0000000..ee4e15f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s6965.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S6965 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s6965
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# 20k working area
+set WORKAREASIZE 0x5000
+set CHIPNAME lm3s6965
+# include the target config
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s811-revb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s811-revb.cfg
new file mode 100644
index 0000000..f968eec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s811-revb.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S811 Evaluation Kits (rev B and earlier)
+#
+# http://www.ti.com/tool/ek-lm3s811
+#
+
+# NOTE: newer 811-EK boards (rev C and above) shouldn't use this.
+# use board/ek-lm3s811.cfg
+source [find interface/ftdi/luminary-lm3s811.cfg]
+
+# include the target config
+set WORKAREASIZE 0x2000
+set CHIPNAME lm3s811
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s811.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s811.cfg
new file mode 100644
index 0000000..0cf36c2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s811.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S811 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s811
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+# NOTE:  older '811-EK boards (before rev C) shouldn't use this.
+source [find interface/ftdi/luminary.cfg]
+
+# include the target config
+set WORKAREASIZE 0x2000
+set CHIPNAME lm3s811
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s8962.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s8962.cfg
new file mode 100644
index 0000000..71a1b10
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s8962.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S8962 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s8962
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# 64k working area
+set WORKAREASIZE 0x10000
+set CHIPNAME lm3s8962
+# include the target config
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s9b9x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s9b9x.cfg
new file mode 100644
index 0000000..289a2cc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s9b9x.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S9B9x Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s9b90
+# http://www.ti.com/tool/ek-lm3s9b92
+#
+
+# NOTE:  using the bundled FT2232 JTAG/SWD/SWO interface is optional!
+# so is using in JTAG mode, as done here.
+source [find interface/ftdi/luminary-icdi.cfg]
+
+set WORKAREASIZE 0x4000
+set CHIPNAME lm3s9b9x
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s9d92.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s9d92.cfg
new file mode 100644
index 0000000..08bbbdb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm3s9d92.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI/Luminary Stellaris LM3S9D92 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s9d92
+#
+
+# NOTE:  using the bundled FT2232 JTAG/SWD/SWO interface is optional!
+# so is using in JTAG mode, as done here.
+source [find interface/ftdi/luminary-icdi.cfg]
+
+# 64k working area
+set WORKAREASIZE 0x10000
+set CHIPNAME lm3s9d92
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm4f120xl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm4f120xl.cfg
new file mode 100644
index 0000000..db8b201
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm4f120xl.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Stellaris Launchpad ek-lm4f120xl Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm4f120xl
+#
+
+#
+# NOTE: using the bundled ICDI interface is optional!
+# This interface is not ftdi based as previous boards were
+#
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME lm4f120h5qr
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm4f232.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm4f232.cfg
new file mode 100644
index 0000000..89b2c3c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-lm4f232.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Stellaris LM4F232 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm4f232
+#
+
+#
+# NOTE: using the bundled ICDI interface is optional!
+# This interface is not ftdi based as previous boards were
+#
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME lm4f23x
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-tm4c123gxl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-tm4c123gxl.cfg
new file mode 100644
index 0000000..d569e58
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-tm4c123gxl.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti_ek-tm4c123gxl.cfg"
+
+source [find board/ti_ek-tm4c123gxl.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-tm4c1294xl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-tm4c1294xl.cfg
new file mode 100644
index 0000000..5c11674
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ek-tm4c1294xl.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti_ek-tm4c1294xl.cfg"
+
+source [find board/ti_ek-tm4c1294xl.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/embedded-artists_lpc2478-32.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/embedded-artists_lpc2478-32.cfg
new file mode 100644
index 0000000..ef61060
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/embedded-artists_lpc2478-32.cfg
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Embedded Artists eval board for LPC2478
+# http://www.embeddedartists.com/
+
+# Target device: LPC2478
+set CCLK 72000
+source [find target/lpc2478.cfg]
+
+# Helper
+#
+proc read_register {register} {
+    return [read_memory $register 32 1]
+}
+
+proc init_board {} {
+    # Delays on reset lines
+    adapter srst delay 500
+    jtag_ntrst_delay 1
+
+    # Adaptive JTAG clocking through RTCK.
+    #
+    jtag_rclk 20
+
+    global _TARGETNAME
+    global _CHIPNAME
+
+    # A working area will help speeding the flash programming
+    $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0
+
+    # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
+    flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
+
+    # Event handlers
+    #
+    $_TARGETNAME configure -event reset-start {
+        # Back to the slow JTAG clock
+        jtag_rclk 20
+    }
+
+    $_TARGETNAME configure -event reset-init {
+        arm core_state arm
+        arm7_9 dcc_downloads enable     ;# Speed up downloads by using DCC transfer
+        arm7_9 fast_memory_access enable
+
+        # Peripheral clocks
+        mww 0xE01FC0C4 0x04280FFE       ;# PCONP: (reset value)
+
+        # Map the user flash to the vector table area (0x00...0x3F)
+        mww 0xE01FC040 0x00000001       ;# MEMMAP: User flash
+
+        # Memory accelerator module
+        mww 0xE01FC004 0x00000003       ;# MAMTIM: 3 clock cycles
+        mww 0xE01FC000 0x00000002       ;# MAMCR: fully enabled
+
+        # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
+        mww 0xE002C014 0x55010115       ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
+                                         # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
+                                         # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
+        mww 0xE002C018 0x55555555       ;# PINSEL6: P3.0...P3.15=D0...D15
+        mww 0xE002C01C 0x55555555       ;# PINSEL7: P3.16...P3.31=D16...D31
+        mww 0xE002C020 0x55555555       ;# PINSEL8: P4.0...P4.15=A0...A15
+        mww 0xE002C024 0x50051555       ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
+                                         # P4.25=WE, P4.30=CS0, P4.31=CS1
+        mww 0xFFE08000 0x00000001       ;# EMCControl: Enable EMC
+
+        # Start PLL, then use faster JTAG clock
+        enable_pll
+        jtag_rclk 3000
+
+        # 16-bit flash @ CS0 (SST39VF3201-70)
+        mww 0xFFE08200 0x00080081       ;# EMCStaticConfig0: 16 bit, PB=1, buffers on
+        mww 0xFFE08204 0x00000000       ;# EMCStaticWaitWen0
+        mww 0xFFE08208 0x00000000       ;# EMCStaticWaitOen0
+        mww 0xFFE0820C 0x00000005       ;# EMCStaticWaitRd0
+        mww 0xFFE08210 0x00000005       ;# EMCStaticWaitPage0
+        mww 0xFFE08214 0x00000003       ;# EMCStaticWaitWr0
+        mww 0xFFE08218 0x00000001       ;# EMCStaticWaitTurn0
+
+        # 8-bit NAND @ CS1
+        # TODO
+
+        # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
+        mww 0xFFE08028 0x00000001       ;# EMCDynamicReadConfig
+        mww 0xFFE08030 0x00000001       ;# EMCDynamicRP
+        mww 0xFFE08034 0x00000003       ;# EMCDynamicRAS
+        mww 0xFFE08038 0x00000005       ;# EMCDynamicSREX
+        mww 0xFFE0803C 0x00000001       ;# EMCDynamicAPR
+        mww 0xFFE08040 0x00000005       ;# EMCDynamicDAL
+        mww 0xFFE08044 0x00000001       ;# EMCDynamicWR
+        mww 0xFFE08048 0x00000005       ;# EMCDynamicRC
+        mww 0xFFE0804C 0x00000005       ;# EMCDynamicRFC
+        mww 0xFFE08050 0x00000005       ;# EMCDynamicXSR
+        mww 0xFFE08054 0x00000001       ;# EMCDynamicRRD
+        mww 0xFFE08058 0x00000001       ;# EMCDynamicMRD
+        #
+        mww 0xFFE08104 0x00000202       ;# EMCDynamicRasCas0
+        mww 0xFFE08100 0x00005488       ;# EMCDynamicConfig0
+        sleep 100
+        mww 0xFFE08020 0x00000183       ;# EMCDynamicControl: Clock on continuously, NOP
+        sleep 10
+        mww 0xFFE08020 0x00000103       ;# EMCDynamicControl: PRECHARGE-ALL
+        mww 0xFFE08024 0x00000046       ;# EMCDynamicRefresh
+        sleep 100
+        mww 0xFFE08020 0x00000083       ;# EMCDynamicControl: MODE
+        mdw 0xA0011000 1                ;# Set SDRAM mode register
+        mww 0xFFE08020 0x00000000       ;# EMCDynamicControl: NORMAL
+        mww 0xFFE08100 0x00085488       ;# EMCDynamicConfig0: Enable buffers
+    }
+
+    $_TARGETNAME configure -event gdb-attach {
+        # Without this gdb-attach will first time as probe will fail
+        reset init
+    }
+}
+
+# Enable the PLL.
+# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
+# Note: The PLL output runs at a frequency N times the desired CPU clock.
+#       It in unavoidable that the CPU clock drops down to (4 MHz/N) during
+#       the initialization!
+#       Here: N=4
+#       Note that if the PLL is already active at the time this script is
+#       called, the effective value of N is the value of CCLKCFG at that time!
+#
+proc enable_pll {} {
+    # Disconnect PLL in case it is already connected
+    if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} {
+        # Disconnect it, but leave it enabled
+        # (This MUST be done in two steps)
+        mww 0xE01FC080 0x00000001       ;# PLLCON: disconnect PLL
+        mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+        mww 0xE01FC08C 0x00000055       ;# PLLFEED
+    }
+    # Disable PLL (as it might already be enabled at this time!)
+    mww 0xE01FC080 0x00000000       ;# PLLCON: disable PLL
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+
+    # Setup PLL to generate 288 MHz from internal RC oscillator
+    mww 0xE01FC10C 0x00000000       ;# CLKSRCSEL: IRC
+    mww 0xE01FC084 0x00000023       ;# PLLCFG: N=1, M=36
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+    mww 0xE01FC080 0x00000001       ;# PLLCON: enable PLL
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+    sleep 100
+    mww 0xE01FC104 0x00000003       ;# CCLKCFG: divide by 4 (72 MHz)
+    mww 0xE01FC080 0x00000003       ;# PLLCON: connect PLL
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/emcraft_imx8m-som-bsb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/emcraft_imx8m-som-bsb.cfg
new file mode 100644
index 0000000..7b9f7b1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/emcraft_imx8m-som-bsb.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for Emcraft IMX8M-SOM-BSB
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# SRST and TRST are wired up
+reset_config trst_and_srst
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+# board has an i.MX8MQ with 4 Cortex-A53 cores
+set CHIPNAME imx8mq
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/emcraft_twr-vf6-som-bsb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/emcraft_twr-vf6-som-bsb.cfg
new file mode 100644
index 0000000..57efa8f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/emcraft_twr-vf6-som-bsb.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# EmCraft Systems TWR-VF6-SOM-BSB
+#
+# http://www.emcraft.com/products/259#twr-kit
+#
+
+source [find board/emcraft_vf6-som.cfg]
+
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/emcraft_vf6-som.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/emcraft_vf6-som.cfg
new file mode 100644
index 0000000..0a6f0f8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/emcraft_vf6-som.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# EmCraft Systems Vybrid VF6 SOM
+#
+# http://www.emcraft.com/products/259#som
+#
+
+set CHIPNAME vf610
+source [find target/vybrid_vf6xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-bridge.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-bridge.cfg
new file mode 100644
index 0000000..17146e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-bridge.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32 connected via ESP USB Bridge board
+#
+# For example, OpenOCD can be started for ESP32 debugging on
+#
+#   openocd -f board/esp32-bridge.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_bridge.cfg]
+# ESP32 chip id defined in the idf esp_chip_model_t
+espusbjtag chip_id 1
+# Source the ESP32 configuration file
+source [find target/esp32.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-ethernet-kit-3.3v.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-ethernet-kit-3.3v.cfg
new file mode 100644
index 0000000..3bfe84b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-ethernet-kit-3.3v.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-ETHERNET-KIT board.
+#
+# For example, OpenOCD can be started for ESP32 debugging on
+#
+#   openocd -f board/esp32-ethernet-kit-3.3v.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+set ESP32_FLASH_VOLTAGE 3.3
+# Source the ESP32 configuration file
+source [find target/esp32.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-wrover-kit-1.8v.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-wrover-kit-1.8v.cfg
new file mode 100644
index 0000000..9aa3954
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-wrover-kit-1.8v.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-WROVER-KIT board.
+#
+# For example, OpenOCD can be started for ESP32 debugging on
+#
+#   openocd -f board/esp32-wrover-kit-1.8v.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+set ESP32_FLASH_VOLTAGE 1.8
+# Source the ESP32 configuration file
+source [find target/esp32.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-wrover-kit-3.3v.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-wrover-kit-3.3v.cfg
new file mode 100644
index 0000000..ce62436
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32-wrover-kit-3.3v.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-WROVER-KIT board.
+#
+# For example, OpenOCD can be started for ESP32 debugging on
+#
+#   openocd -f board/esp32-wrover-kit-3.3v.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+set ESP32_FLASH_VOLTAGE 3.3
+# Source the ESP32 configuration file
+source [find target/esp32.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c2-ftdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c2-ftdi.cfg
new file mode 100644
index 0000000..bc2b82f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c2-ftdi.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C2 connected via ESP-Prog.
+#
+# For example, OpenOCD can be started for ESP32-C2 debugging on
+#
+#   openocd -f board/esp32c2-ftdi.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+# Source the ESP32-C2 configuration file
+source [find target/esp32c2.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c3-builtin.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c3-builtin.cfg
new file mode 100644
index 0000000..9e19b1b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c3-builtin.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C3 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-C3 debugging on
+#
+#   openocd -f board/esp32c3-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-C3 configuration file
+source [find target/esp32c3.cfg]
+
+adapter speed 40000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c3-ftdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c3-ftdi.cfg
new file mode 100644
index 0000000..5595374
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c3-ftdi.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C3 connected via ESP-Prog.
+#
+# For example, OpenOCD can be started for ESP32-C3 debugging on
+#
+#   openocd -f board/esp32c3-ftdi.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+# Source the ESP32-C3 configuration file
+source [find target/esp32c3.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c6-builtin.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c6-builtin.cfg
new file mode 100644
index 0000000..abc96b2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32c6-builtin.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C6 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-C6 debugging on
+#
+#   openocd -f board/esp32c6-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-C6 configuration file
+source [find target/esp32c6.cfg]
+
+adapter speed 40000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32h2-builtin.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32h2-builtin.cfg
new file mode 100644
index 0000000..1ce5961
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32h2-builtin.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C3 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-C3 debugging on
+#
+#   openocd -f board/esp32c3-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-C3 configuration file
+source [find target/esp32h2.cfg]
+
+adapter speed 40000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s2-bridge.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s2-bridge.cfg
new file mode 100644
index 0000000..b87be8b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s2-bridge.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S2 connected via ESP USB Bridge board
+#
+# For example, OpenOCD can be started for ESP32-S2 debugging on
+#
+#   openocd -f board/esp32s2-bridge.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_bridge.cfg]
+# ESP32S2 chip id defined in the idf esp_chip_model_t
+espusbjtag chip_id 2
+# Source the ESP32-S2 configuration file
+source [find target/esp32s2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s2-kaluga-1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s2-kaluga-1.cfg
new file mode 100644
index 0000000..783ea21
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s2-kaluga-1.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S2 Kaluga board.
+#
+# For example, OpenOCD can be started for ESP32-S2 debugging on
+#
+#   openocd -f board/esp32s2-kaluga-1.cfg
+#
+
+source [find interface/ftdi/esp32s2_kaluga_v1.cfg]
+source [find target/esp32s2.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+# On ESP32-S2, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s3-bridge.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s3-bridge.cfg
new file mode 100644
index 0000000..a42e257
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s3-bridge.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S3 connected via ESP USB Bridge board
+#
+# For example, OpenOCD can be started for ESP32-S3 debugging on
+#
+#   openocd -f board/esp32s3-bridge.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_bridge.cfg]
+# ESP32S3 chip id defined in the idf esp_chip_model_t
+espusbjtag chip_id 9
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s3-builtin.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s3-builtin.cfg
new file mode 100644
index 0000000..353099c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s3-builtin.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S3 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-S3 debugging on
+#
+#   openocd -f board/esp32s3-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
+
+adapter speed 40000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s3-ftdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s3-ftdi.cfg
new file mode 100644
index 0000000..6070664
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/esp32s3-ftdi.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S3 connected via ESP-Prog.
+#
+# For example, OpenOCD can be started for ESP32-S3 debugging on
+#
+#   openocd -f board/esp32s3-ftdi.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ethernut3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ethernut3.cfg
new file mode 100644
index 0000000..384db1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ethernut3.cfg
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Ethernut 3 board configuration file
+#
+# http://www.ethernut.de/en/hardware/enut3/
+
+
+# AT91R40008-66AU ARM7TDMI Microcontroller
+# 256kB internal RAM
+source [find target/at91r40008.cfg]
+
+
+# AT49BV322A-70TU NOR Flash
+# 2M x 16 mode at address 0x10000000
+# Common flash interface supported
+#
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
+
+
+# Micrel MIC2775-29YM5 Supervisor
+# Reset output will remain active for 280ms (maximum)
+#
+adapter srst delay 300
+jtag_ntrst_delay 300
+
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+adapter speed 16000
+
+
+# Target events
+#
+$_TARGETNAME configure -event reset-init { board_init }
+
+# Initialize board hardware
+#
+proc board_init { } {
+	board_remap
+	flash probe 0
+}
+
+# Memory remap
+#
+proc board_remap {{VERBOSE 0}} {
+	# CS0: NOR flash
+	#      16MB @ 0x10000000
+	#      16-bit data bus
+	#      4 wait states
+	#
+	mww 0xffe00000 0x1000212d
+
+	# CS1: Ethernet controller
+	#      1MB @ 0x20000000
+	#      16-bit data bus
+	#      2 wait states
+	#      Byte select access
+	#
+	mww 0xffe00004 0x20003025
+
+	# CS2: CPLD registers
+	#      1MB @ 0x21000000
+	#      8-bit data bus
+	#      2 wait states
+	#
+	mww 0xffe00008 0x21002026
+
+	# CS3: Expansion bus
+	#      1MB @ 0x22000000
+	#      8-bit data bus
+	#      8 wait states
+	#
+	mww 0xffe00010 0x22002e3e
+
+	# Remap command
+	#
+	mww 0xffe00020 0x00000001
+
+	if {$VERBOSE != 0} {
+		echo "0x00000000 RAM"
+		echo "0x10000000 Flash"
+		echo "0x20000000 Ethernet"
+		echo "0x21000000 CPLD"
+		echo "0x22000000 Expansion"
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/evb-lan9255.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/evb-lan9255.cfg
new file mode 100644
index 0000000..3fd6f60
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/evb-lan9255.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip LAN9255 evaluation board
+# https://www.microchip.com/en-us/development-tool/EV25Y25A
+#
+
+set CHIPNAME same53
+
+source [find target/atsame5x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/frdm-kl25z.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/frdm-kl25z.cfg
new file mode 100644
index 0000000..68dc48d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/frdm-kl25z.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an Freescale Freedom eval board with a single MKL25Z128VLK4 chip.
+# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL25Z
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# increase working area to 16KB
+set WORKAREASIZE 0x4000
+
+# chip name
+set CHIPNAME MKL25Z128VLK4
+
+reset_config srst_only
+
+source [find target/kl25.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/frdm-kl46z.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/frdm-kl46z.cfg
new file mode 100644
index 0000000..3fb7205
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/frdm-kl46z.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an Freescale Freedom eval board with a single MKL46Z256VLL4 chip.
+# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL46Z
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# increase working area to 16KB
+set WORKAREASIZE 0x4000
+
+# chip name
+set CHIPNAME MKL46Z256VLL4
+
+reset_config srst_only
+
+source [find target/kl46.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/fsl_imx6q_sabresd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/fsl_imx6q_sabresd.cfg
new file mode 100644
index 0000000..faeeafb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/fsl_imx6q_sabresd.cfg
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration file for the Freescale IMX6Q Sabre SD EVM
+#
+# This board does not have an embedded JTAG adapter, you must source
+# a suitable adapter configuration before sourcing this file.
+
+# Sabre SD has a standard ARM-20 JTAG connector with
+# nTRST and nSRST available.
+reset_config trst_and_srst
+
+# the only possible transport is JTAG
+transport select jtag
+
+# iMX6Q POR gates JTAG and the chip is completely incommunicado
+# over JTAG for at least 10ms after nSRST is deasserted
+adapter srst delay 11
+
+# Source generic iMX6Q target configuration
+set CHIPNAME imx6q
+source [find target/imx6.cfg]
+
+# function to apply initial configuration after a reset. It
+# provides a basic pad configuration and also DDR memory and clocks
+# sufficient to load and execute a boot loader (e.g. barebox) from
+# DDR memory. This list is extracted from the barebox flash image
+# header.
+proc apply_dcd { } {
+	mww 0x020e05a8 0x00000030
+	mww 0x020e05b0 0x00000030
+	mww 0x020e0524 0x00000030
+	mww 0x020e051c 0x00000030
+	mww 0x020e0518 0x00000030
+	mww 0x020e050c 0x00000030
+	mww 0x020e05b8 0x00000030
+	mww 0x020e05c0 0x00000030
+	mww 0x020e05ac 0x00020030
+	mww 0x020e05b4 0x00020030
+	mww 0x020e0528 0x00020030
+	mww 0x020e0520 0x00020030
+	mww 0x020e0514 0x00020030
+	mww 0x020e0510 0x00020030
+	mww 0x020e05bc 0x00020030
+	mww 0x020e05c4 0x00020030
+	mww 0x020e056c 0x00020030
+	mww 0x020e0578 0x00020030
+	mww 0x020e0588 0x00020030
+	mww 0x020e0594 0x00020030
+	mww 0x020e057c 0x00020030
+	mww 0x020e0590 0x00003000
+	mww 0x020e0598 0x00003000
+	mww 0x020e058c 0x00000000
+	mww 0x020e059c 0x00003030
+	mww 0x020e05a0 0x00003030
+	mww 0x020e0784 0x00000030
+	mww 0x020e0788 0x00000030
+	mww 0x020e0794 0x00000030
+	mww 0x020e079c 0x00000030
+	mww 0x020e07a0 0x00000030
+	mww 0x020e07a4 0x00000030
+	mww 0x020e07a8 0x00000030
+	mww 0x020e0748 0x00000030
+	mww 0x020e074c 0x00000030
+	mww 0x020e0750 0x00020000
+	mww 0x020e0758 0x00000000
+	mww 0x020e0774 0x00020000
+	mww 0x020e078c 0x00000030
+	mww 0x020e0798 0x000c0000
+	mww 0x021b081c 0x33333333
+	mww 0x021b0820 0x33333333
+	mww 0x021b0824 0x33333333
+	mww 0x021b0828 0x33333333
+	mww 0x021b481c 0x33333333
+	mww 0x021b4820 0x33333333
+	mww 0x021b4824 0x33333333
+	mww 0x021b4828 0x33333333
+	mww 0x021b0018 0x00081740
+	mww 0x021b001c 0x00008000
+	mww 0x021b000c 0x555a7975
+	mww 0x021b0010 0xff538e64
+	mww 0x021b0014 0x01ff00db
+	mww 0x021b002c 0x000026d2
+	mww 0x021b0030 0x005b0e21
+	mww 0x021b0008 0x09444040
+	mww 0x021b0004 0x00025576
+	mww 0x021b0040 0x00000027
+	mww 0x021b0000 0x831a0000
+	mww 0x021b001c 0x04088032
+	mww 0x021b001c 0x0408803a
+	mww 0x021b001c 0x00008033
+	mww 0x021b001c 0x0000803b
+	mww 0x021b001c 0x00428031
+	mww 0x021b001c 0x00428039
+	mww 0x021b001c 0x09408030
+	mww 0x021b001c 0x09408038
+	mww 0x021b001c 0x04008040
+	mww 0x021b001c 0x04008048
+	mww 0x021b0800 0xa1380003
+	mww 0x021b4800 0xa1380003
+	mww 0x021b0020 0x00005800
+	mww 0x021b0818 0x00022227
+	mww 0x021b4818 0x00022227
+	mww 0x021b083c 0x434b0350
+	mww 0x021b0840 0x034c0359
+	mww 0x021b483c 0x434b0350
+	mww 0x021b4840 0x03650348
+	mww 0x021b0848 0x4436383b
+	mww 0x021b4848 0x39393341
+	mww 0x021b0850 0x35373933
+	mww 0x021b4850 0x48254A36
+	mww 0x021b080c 0x001f001f
+	mww 0x021b0810 0x001f001f
+	mww 0x021b480c 0x00440044
+	mww 0x021b4810 0x00440044
+	mww 0x021b08b8 0x00000800
+	mww 0x021b48b8 0x00000800
+	mww 0x021b001c 0x00000000
+	mww 0x021b0404 0x00011006
+	mww 0x020c4068 0x00c03f3f
+	mww 0x020c406c 0x0030fc03
+	mww 0x020c4070 0x0fffc000
+	mww 0x020c4074 0x3ff00000
+	mww 0x020c4078 0x00fff300
+	mww 0x020c407c 0x0f0000c3
+	mww 0x020c4080 0x000003ff
+	mww 0x020e0010 0xf00000cf
+	mww 0x020e0018 0x007f007f
+	mww 0x020e001c 0x007f007f
+}
+
+# disable watchdog
+proc disable_wdog { } {
+	mwh 0x020bc000 0x30
+}
+
+# This function applies the initial configuration after a "reset init"
+# command
+proc imx6q_sabresd_init { } {
+	disable_wdog
+	apply_dcd
+}
+
+# prevent cortex-a code from asserting SRST again
+$_TARGETNAME.0 configure -event reset-assert { }
+# hook the init function into the reset-init event
+$_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init }
+# set a slow default JTAG clock, can be overridden later
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gatemate_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gatemate_eval.cfg
new file mode 100644
index 0000000..c4d3f3d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gatemate_eval.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# GateMateTM FPGA Evaluation Board
+# https://www.colognechip.com/programmable-logic/gatemate-evaluation-board/
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0014 0x011b
+reset_config none
+transport select jtag
+adapter speed 6000
+
+source [find fpga/gatemate.cfg]
+
+set JTAGSPI_CHAIN_ID gatemate.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init gatemate.pld "" -1
+#jtagspi_program workspace/blink/blink_slow.cfg.bit 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/glyn_tonga2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/glyn_tonga2.cfg
new file mode 100644
index 0000000..d847bec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/glyn_tonga2.cfg
@@ -0,0 +1,201 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9)
+#
+# http://toshiba-mikrocontroller.de/sites/TMPA900CPUBOARDStarter.htm
+#
+# Hardware on the S0-DIMM module:
+#   - Toshiba TMPA900CMXBG (ARM9, ARM926EJ-S, max. 200MHz)
+#   - DDR SDRAM: Hynix H5MS5162DFR-J3M (64Mbyte, x16, 1.8V, 166/83MHz at CL3/2)
+#   - NAND flash: Samsung K9F2G08U0B-PIB0 (256M x 8 Bit, 3.3V)
+#   - Ethernet: SMSC LAN9221I-ABZJ (10/100Mbit, Non-PCI, 16 bit interface)
+#
+
+source [find target/tmpa900.cfg]
+
+########################
+# Target configuration #
+########################
+
+# Initial JTAG speed should not exceed 1/6 of the initial CPU clock
+# frequency (24MHz). Be conservative and use 1/8 of the frequency.
+# (24MHz / 8 = 3MHz)
+adapter speed 3000
+
+$_TARGETNAME configure -event reset-start {
+	# Upon reset, set the JTAG frequency to 3MHz again, see above.
+	echo "Setting JTAG speed to 3MHz until clocks are initialized."
+	adapter speed 3000
+
+	# Halt the CPU.
+	halt
+
+	# Disable faster memory access for now.
+	arm7_9 fast_memory_access disable
+}
+
+$_TARGETNAME configure -event reset-init {
+	# Setup clocks, and initialize SRAM and DDR SDRAM.
+	tonga2_init
+
+	# At this point the CPU is running at 192MHz, increase JTAG speed.
+	# Tests showed that 15MHz works OK, higher speeds can cause problems,
+	# though. Not sure if this is a CPU issue or JTAG adapter issue.
+	echo "Increasing JTAG speed to 15MHz."
+	adapter speed 15000
+
+	# Enable faster memory access.
+	arm7_9 fast_memory_access enable
+}
+
+proc tonga2_init { } {
+	######################
+	# PLL initialization #
+	######################
+
+	# Clock overview (see datasheet chapter 3.5.2, page 57):
+	#   - fs: Low-frequency oscillator
+	#   - fOSCH: High-frequency oscillator (24MHz on this board)
+	#   - fPLL = fOSCH * multiplier (where multiplier can be 6 or 8)
+	#   - fFCLK = fPLL / gear (where gear can be 1/2/4/8)
+	#   - fHCLK is always fFCLK/2. fPCLK is also fFCLK/2.
+	#
+	# We select multiplier = 8 and gear = 1, so
+	#   fFCLK = fOSCH * 8 / 1 = 192MHz.
+
+	# SYSCR3 (System Control Register 3): Disable and configure PLL.
+	#   - PLL operation control: off
+	#   - PLL constant value setting 1: always 0, as per datasheet
+	#   - PLL constant value setting 2: x8 (multiplier = 8)
+	mww 0xf005000c 0x00000007
+
+	# SYSCR4 (System Control Register 4): Configure PLL.
+	#   - PLL constant value setting 3: 140MHz or more
+	#   - PLL constant value setting 4: always 1, as per datasheet
+	#   - PLL constant value setting 5: 140MHz or more
+	mww 0xf0050010 0x00000065
+
+	# SYSCR3 (System Control Register 3): Enable PLL.
+	#   - PLL operation control: on
+	#   - All other bits remain set as above.
+	mww 0xf005000c 0x00000087
+
+	# Wait for PLL to stabilize.
+	sleep 10
+
+	# SYSCR2 (System Control Register 2): Switch from fOSCH to fPLL.
+	#   - Selection of the PLL output clock: fPLL
+	mww 0xf0050008 0x00000002
+
+	# SYSCR1 (System Control Register 1):
+	#   - Clock gear programming: fc/1 (i.e., gear = 1, don't divide).
+	mww 0xf0050004 0x00000000
+
+	# CLKCR5 (Clock Control Register 5): Set bits 3 and 6. The datasheet
+	# says the bits are reserved, but also recommends "Write as one".
+	mww 0xf0050054 0x00000048
+
+
+	##############################################################
+	# Dynamic Memory Controller (DMC) / DDR SDRAM initialization #
+	##############################################################
+
+	# PMC (Power Management Controller):
+	# PMCDRV (External Port "Driverbility" control register):
+	# Bits DRV_MEM0/DRV_MEM1 (memory relation port drive power):
+	mww 0xf0020260 0x00000003	;# Select 1.8V +/- 0.1V
+
+	# Setup DDR SDRAM timing parameters for our specific chip.
+	mww 0xf4310014 0x00000004	;# cas_latency = 2
+	mww 0xf4310018 0x00000001	;# t_dqss = 1
+	mww 0xf431001c 0x00000002	;# t_mrd = 2
+	mww 0xf4310020 0x0000000a	;# t_ras = 10
+	mww 0xf4310024 0x0000000a	;# t_rc = 10
+	mww 0xf4310028 0x00000013	;# t_rcd = 3, schedule_rcd = 2
+	mww 0xf431002c 0x0000010a	;# t_rfc = 10, schedule_rfc = 8
+	mww 0xf4310030 0x00000013	;# t_rp = 3, schedule_rp = 2
+	mww 0xf4310034 0x00000002	;# t_rrd = 2
+	mww 0xf4310038 0x00000002	;# t_wr = 2
+	mww 0xf431003c 0x00000001	;# t_wtr = 1
+	mww 0xf4310040 0x0000000a	;# t_xp = 10
+	mww 0xf4310044 0x0000000c	;# t_xsr = 12
+	mww 0xf4310048 0x00000014	;# t_esr = 20
+
+	# dmc_memory_cfg_5 (DMC Memory Configuration register):
+	# Set memory configuration:
+	# column_bits = 10, row_bits = 13, ap-bit = 10, power_down_prd = 0,
+	# auto_power_down = disable, stop_mem_clock = disable, memory_burst = 4
+	mww 0xf431000c 0x00010012
+
+	# dmc_user_config_5 (DMC user_config register):
+	# Data bus width of DDR SDRAM: 16 bit
+	mww 0xf4310304 0x00000058
+
+	# dmc_refresh_prd_5 (DMC Refresh Period register):
+	# Auto refresh: every 2656 (0xa60) DMCSCLK periods.
+	mww 0xf4310010 0x00000a60
+
+	# dmc_chip_0_cfg_5 (DMC chip_0_cfg registers):
+	#   - SDRAM address structure: bank, row, column
+	#   - address_match = 01000000 (start address [31:24])
+	#   - address_mask  = 11111100 (start address [31:24] mask value)
+	mww 0xf4310200 0x000140fc
+
+	# Initialize the DDR SDRAM chip.
+	# dmc_direct_cmd_5 (DMC Direct Command register).
+	# See datasheet chapter 3.10.5.1, page 268.
+	mww 0xf4310008 0x000c0000	;# RAM init: NOP
+	mww 0xf4310008 0x00000000	;# RAM init: Precharge all
+	mww 0xf4310008 0x00040000	;# RAM init: Autorefresh
+	mww 0xf4310008 0x00040000	;# RAM init: Autorefresh
+	mww 0xf4310008 0x00080032	;# RAM init: addr_13_to_0 = 0x32
+	mww 0xf4310008 0x000c0000	;# RAM init: NOP
+	mww 0xf4310008 0x000a0000	;# RAM init: bank_addr = bank 2
+
+	# dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg registers):
+	# Set min./max. QoS values.
+	#   - 0x5: Enable QoS, max. QoS = 1
+	#   - 0xb: Enable QoS, min. QoS = 2
+	mww 0xf4310100 0x00000005	;# AHB0: CPU Data
+	mww 0xf4310104 0x00000005	;# AHB1: CPU Inst
+	mww 0xf4310108 0x0000000b	;# AHB2: LCDC
+	mww 0xf431010c 0x00000005	;# AHB3: LCDDA, USB
+	mww 0xf4310110 0x00000005	;# AHB4: DMA1
+	mww 0xf4310114 0x00000005	;# AHB5: DMA2
+
+	# dmc_memc_cmd_5 (DMC Memory Controller Command register):
+	# Change DMC state to ready.
+	mww 0xf4310004 0x00000000	;# memc_cmd = "Go"
+
+	# EBI: SMC Timeout register
+	mww 0xf00a0050 0x00000001	;# smc_timeout = 1
+
+
+	########################################################
+	# Static Memory Controller (SMC) / SRAM initialization #
+	########################################################
+
+	# smc_set_cycles_5 (SMC Set Cycles register):
+	# tRC = 10, tWC = 10, tCEOE = 7, tWP = 5, tPC=2, tTR=2
+	mww 0xf4311014 0x0004afaa
+
+	# smc_set_opmode_5 (SMC Set Opmode register):
+	# Memory data bus width = 16 bits, async read mode, read burst
+	# length = 1 beat, async write mode, write burst length = 1 beat,
+	# byte enable (SMCBE0-1) timing = SMCCSn timing, memory burst boundary
+	# split setting = burst can cross any address boundary
+	mww 0xf4311018 0x00000001
+
+	# smc_direct_cmd_5 (SMC Direct Command register):
+	# cmd_type = UpdateRegs, chip_select = CS1
+	mww 0xf4311010 0x00c00000
+
+	echo "Clocks, SRAM, and DDR SDRAM are now initialized."
+}
+
+#######################
+# Flash configuration #
+#######################
+
+# TODO: Implement NAND support.
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gowin_runber.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gowin_runber.cfg
new file mode 100644
index 0000000..6cb0736
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gowin_runber.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Gowin RUNBER FPGA Development Board
+# https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+reset_config none
+transport select jtag
+adapter speed 6000
+
+source [find fpga/gowin_gw1n.cfg]
+
+
+#openocd -f board/gowin_runber.cfg  -c "init" -c "pld load 0 impl/pnr/gw1n_blinker.fs"
+#ipdbg create-hub gw1n.ipdbghub -tap gw1n.tap -ir 0x42
+#gw1n.ipdbghubipdbg start  -tool 0 -port 5555
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gti/espressobin.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gti/espressobin.cfg
new file mode 100644
index 0000000..d1492df
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gti/espressobin.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# config for ESPRESSObin from
+# Globalscale Technologies Inc.
+
+# srst is isolated through missing resistor
+reset_config trst_only
+
+source [find target/marvell/88f3720.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gumstix-aerocore.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gumstix-aerocore.cfg
new file mode 100644
index 0000000..ddadc88
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/gumstix-aerocore.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# JTAG for the STM32F4x chip used on the Gumstix AeroCore is available on
+# the first interface of a Quad FTDI chip.  nTRST is bit 4.
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6011
+
+ftdi layout_init 0x0000 0x001b
+ftdi layout_signal nTRST -data 0x0010
+
+source [find target/stm32f4x.cfg]
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hammer.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hammer.cfg
new file mode 100644
index 0000000..79d58ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hammer.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
+# http://www.tincantools.com
+
+source [find target/samsung_s3c2410.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	# Reset Script for the TinCanTools S3C2410 Based Hammer Module
+	# http://www.tincantools.com
+	#
+	# Setup primary clocks and initialize the SDRAM
+	mww 0x53000000 0x00000000
+	mww 0x4a000008 0xffffffff
+	mww 0x4a00000c 0x000007ff
+	mww 0x4c000000 0x00ffffff
+	mww 0x4c000014 0x00000003
+	mww 0x4c000004 0x000a1031
+	mww 0x48000000 0x11111122
+	mww 0x48000004 0x00000700
+	mww 0x48000008 0x00000700
+	mww 0x4800000c 0x00000700
+	mww 0x48000010 0x00000700
+	mww 0x48000014 0x00000700
+	mww 0x48000018 0x00000700
+	mww 0x4800001c 0x00018005
+	mww 0x48000020 0x00018005
+	mww 0x48000024 0x009c0459
+	mww 0x48000028 0x000000b2
+	mww 0x4800002c 0x00000030
+	mww 0x48000030 0x00000030
+	flash probe 0
+}
+
+
+#flash configuration
+#flash bank        [driver_options ...]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x1000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxdb500sys.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxdb500sys.cfg
new file mode 100644
index 0000000..68e1cda
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxdb500sys.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for paired K4S561632C (64MB) "
+  mww 0x00100140 0
+  mww 0x00100144 0x03C13261
+  mww 0x00100140 0x030D0121
+
+  puts "Configuring SRAM nCS0 for 150ns paired Par. Flash (x32)"
+  mww 0x00100100 0x0201000E
+
+  flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+flash bank parflash cfi 0xC0000000 0x02000000 4 4 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxeb500hmi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxeb500hmi.cfg
new file mode 100644
index 0000000..a814365
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxeb500hmi.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads disable
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for MT48LC8M32 (32MB) "
+  mww 0x00100140 0
+  mww 0x00100144 0x03C23251
+  mww 0x00100140 0x030D0111
+
+  puts "Configuring SRAM nCS0 for 150ns Par. Flash (x16)"
+  mww 0x00100100 0x0101000E
+
+  flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxhx10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxhx10.cfg
new file mode 100644
index 0000000..e116a6c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxhx10.cfg
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx10.cfg]
+
+# Usually it is not needed to set srst_pulls_trst
+# but sometimes it does not work without it. If you encounter
+# problems try to line below
+# reset_config trst_and_srst srst_pulls_trst
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
+
+# Par. Flash can only be accessed if DIP switch on the board is set in proper
+# position and init_sdrambus was called. Don't call these functions if the DIP
+# switch is in invalid position, as some outputs may collide. This is why this
+# function is not called automatically
+proc flash_init { } {
+  puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+  mww 0x101C0100 0x01010008
+
+  flash probe 0
+}
+
+proc mread32 {addr} {
+  return [read_memory $addr 32 1]
+}
+
+proc init_clocks { } {
+  puts "Enabling all clocks "
+  set accesskey [mread32 0x101c0070]
+  mww  0x101c0070 $accesskey
+
+  mww  0x101c0028 0x00007511
+}
+
+proc init_sdrambus { } {
+  puts "Initializing external SDRAM Bus 16 Bit "
+  set accesskey [mread32 0x101c0070]
+  mww  0x101c0070 $accesskey
+  mww  0x101c0C40 0x00000050
+
+  puts "Configuring SDRAM controller for K4S561632E (32MB) "
+  mww 0x101C0140 0
+  sleep 100
+  #mww 0x101C0144 0x00a13262
+  mww 0x101C0144 0x00a13251
+  mww 0x101C0148 0x00000033
+  mww 0x101C0140 0x030d0121
+}
+
+$_TARGETNAME configure -event reset-init {
+  halt
+  wait_halt 1000
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  init_clocks
+#  init_sdrambus
+
+  puts ""
+  puts "-------------------------------------------------"
+  puts "Call 'init_clocks' to enable all clocks"
+  puts "Call 'init_sdrambus' to enable external SDRAM bus"
+  puts "-------------------------------------------------"
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxhx50.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxhx50.cfg
new file mode 100644
index 0000000..8aef6ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxhx50.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx50.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
+  mww 0x1C000140 0
+  mww 0x1C000144 0x00A12151
+  mww 0x1C000140 0x030D0001
+
+  puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+  mww 0x1C000100 0x01010008
+
+  flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxhx500.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxhx500.cfg
new file mode 100644
index 0000000..9ddf657
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxhx500.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  sleep 100
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
+  mww 0x00100140 0
+  mww 0x00100144 0x03C23251
+  mww 0x00100140 0x030D0001
+
+  puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+  mww 0x00100100 0x01010008
+
+  flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank       
+flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxsb100.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxsb100.cfg
new file mode 100644
index 0000000..b59ea17
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hilscher_nxsb100.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+  halt
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  sdram_fix
+
+  puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
+  mww 0x00100140 0
+  mww 0x00100144 0x03C23251
+  mww 0x00100140 0x030D0001
+
+}
+
+init
+reset init
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_lpc1768stick.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_lpc1768stick.cfg
new file mode 100644
index 0000000..52cf370
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_lpc1768stick.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hitex LPC1768 Stick
+#
+# http://www.hitex.com/?id=1602
+#
+
+reset_config trst_and_srst
+
+source [find interface/ftdi/hitex_lpc1768stick.cfg]
+
+source [find target/lpc17xx.cfg]
+
+
+# startup @ 500kHz
+adapter speed 500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_lpc2929.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_lpc2929.cfg
new file mode 100644
index 0000000..35007c0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_lpc2929.cfg
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hitex eval board for LPC2929/LPC2939
+# http://www.hitex.com/
+
+# Delays on reset lines
+adapter srst delay 50
+jtag_ntrst_delay 1
+
+# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
+# Adaptive clocking through RTCK is not supported.
+adapter speed 2000
+
+# Target device: LPC29xx with ETB
+# The following variables are used by the LPC2900 script:
+#   HAS_ETB             Must be set to 1. The CPU on this board has ETB.
+#   FLASH_CLOCK         CPU frequency at the time of flash programming (in kHz)
+set HAS_ETB             1
+set FLASH_CLOCK         112000
+source [find target/lpc2900.cfg]
+
+# A working area will help speeding the flash programming
+#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0
+$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0
+
+# Event handlers
+$_TARGETNAME configure -event reset-start {
+  # Back to the slow JTAG clock
+  adapter speed 2000
+}
+
+# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
+set _FLASHNAME $_CHIPNAME.extflash
+flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
+
+
+$_TARGETNAME configure -event reset-init {
+  # Flash
+  mww 0x20200010 0x00000007     ;# FBWST: 7 wait states, not cached
+
+  # Use PLL
+  mww 0xFFFF8020 0x00000001     ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
+  mww 0xFFFF8070 0x01000000     ;# SYS_CLK_CONF: Crystal
+  mww 0xFFFF8028 0x00000005     ;# PLL: (power down)
+  mww 0xFFFF8028 0x01060004     ;# PLL: M=7, 2P=2 (power up)
+                                 # --> f=112 MHz, fcco=224 MHz
+  sleep 100
+  mww 0xFFFF8070 0x02000000     ;# SYS_CLK_CONF: PLL
+
+  # Increase JTAG speed
+  adapter speed 6000
+
+  # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
+  mww 0xE0001138 0x0000001F     ;# P1.14 = D0
+  mww 0xE000113C 0x0000001F     ;# P1.15 = D1
+  mww 0xE0001140 0x0000001F     ;# P1.16 = D2
+  mww 0xE0001144 0x0000001F     ;# P1.17 = D3
+  mww 0xE0001148 0x0000001F     ;# P1.18 = D4
+  mww 0xE000114C 0x0000001F     ;# P1.19 = D5
+  mww 0xE0001150 0x0000001F     ;# P1.20 = D6
+  mww 0xE0001154 0x0000001F     ;# P1.21 = D7
+  mww 0xE0001200 0x0000001F     ;# P2.0  = D8
+  mww 0xE0001204 0x0000001F     ;# P2.1  = D9
+  mww 0xE0001208 0x0000001F     ;# P2.2  = D10
+  mww 0xE000120C 0x0000001F     ;# P2.3  = D11
+  mww 0xE0001210 0x0000001F     ;# P2.4  = D12
+  mww 0xE0001214 0x0000001F     ;# P2.5  = D13
+  mww 0xE0001218 0x0000001F     ;# P2.6  = D14
+  mww 0xE000121C 0x0000001F     ;# P2.7  = D15
+  mww 0xE0001104 0x00000007     ;# P1.1  = A1
+  mww 0xE0001108 0x00000007     ;# P1.2  = A2
+  mww 0xE000110C 0x00000007     ;# P1.3  = A3
+  mww 0xE0001110 0x00000007     ;# P1.4  = A4
+  mww 0xE0001114 0x00000007     ;# P1.5  = A5
+  mww 0xE0001118 0x00000007     ;# P1.6  = A6
+  mww 0xE000111C 0x00000007     ;# P1.7  = A7
+  mww 0xE0001028 0x00000007     ;# P0.10 = A8
+  mww 0xE000102C 0x00000007     ;# P0.11 = A9
+  mww 0xE0001030 0x00000007     ;# P0.12 = A10
+  mww 0xE0001034 0x00000007     ;# P0.13 = A11
+  mww 0xE0001038 0x00000007     ;# P0.14 = A12
+  mww 0xE000103C 0x00000007     ;# P0.15 = A13
+  mww 0xE0001048 0x00000007     ;# P0.18 = A14
+  mww 0xE000104C 0x00000007     ;# P0.19 = A15
+  mww 0xE0001050 0x00000007     ;# P0.20 = A16
+  mww 0xE0001054 0x00000007     ;# P0.21 = A17
+  mww 0xE0001058 0x00000007     ;# P0.22 = A18
+  mww 0xE000105C 0x00000007     ;# P0.23 = A19
+  mww 0xE0001238 0x00000007     ;# P2.14 = BLS0
+  mww 0xE000123C 0x00000007     ;# P2.15 = BLS1
+  mww 0xE0001300 0x00000007     ;# P3.0  = CS6
+  mww 0xE0001304 0x00000007     ;# P3.1  = CS7
+  mww 0xE0001130 0x00000007     ;# P1.12 = OE_N
+  mww 0xE0001134 0x00000007     ;# P1.13 = WE_N
+  mww 0x600000BC 0x00000041     ;# Bank6 16-bit mode, RBLE=1
+  mww 0x600000B4 0x00000000     ;# Bank6 WSTOEN=0
+  mww 0x600000AC 0x00000005     ;# Bank6 WST1=5
+  mww 0x600000B8 0x00000001     ;# Bank6 WSTWEN=1
+  mww 0x600000B0 0x00000006     ;# Bank6 WST2=6
+  mww 0x600000A8 0x00000002     ;# Bank6 IDCY=2
+  mww 0x600000D8 0x00000041     ;# Bank7 16-bit mode, RBLE=1
+  mww 0x600000D0 0x00000000     ;# Bank7 WSTOEN=0
+  mww 0x600000C8 0x0000000A     ;# Bank7 WST1=10
+  mww 0x600000D4 0x00000001     ;# Bank7 WSTWEN=1
+  mww 0x600000CC 0x0000000C     ;# Bank7 WST2=8
+  mww 0x600000C4 0x00000002     ;# Bank7 IDCY=2
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_stm32-performancestick.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_stm32-performancestick.cfg
new file mode 100644
index 0000000..bab5964
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_stm32-performancestick.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hitex stm32 performance stick
+
+reset_config trst_and_srst
+
+source [find interface/ftdi/stm32-stick.cfg]
+
+set  CHIPNAME stm32_hitex
+source [find target/stm32f1x.cfg]
+
+# configure str750 connected to jtag chain
+# FIXME -- source [find target/str750.cfg] after cleaning that up
+jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041
+
+# for some reason this board like to startup @ 500kHz
+adapter speed 500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_str9-comstick.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_str9-comstick.cfg
new file mode 100644
index 0000000..a508046
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/hitex_str9-comstick.cfg
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hitex STR9-comStick
+# http://www.hitex.com/index.php?id=383
+# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
+
+source [find interface/ftdi/hitex_str9-comstick.cfg]
+
+# set jtag speed
+adapter speed 3000
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#
+# FIXME use the standard str912 target config; that script might need
+# updating to "-ignore-version" for the boundary scan TAP
+#
+#	source [find target/str912.cfg]
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists FLASHTAPID] } {
+   set _FLASHTAPID $FLASHTAPID
+} else {
+   set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+   # Found on STR9-comStick, revision STR912CS-A1
+   set _BSTAPID1 0x1457f041
+   # Found on STR9-comStick, revision STR912CS-A2
+   set _BSTAPID2 0x2457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	#jtag_rclk 3000
+
+	# -- Enable 96K RAM
+	# PFQBC enabled / DTCM & AHB wait-states disabled
+	mww 0x5C002034 0x0191
+
+	str9x flash_config 0 4 2 0 0x80000
+	flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+
+#flash bank     
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/iar_lpc1768.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/iar_lpc1768.cfg
new file mode 100644
index 0000000..d8d669e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/iar_lpc1768.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Board from IAR KickStart Kit for LPC1768
+# See www.iar.com and also
+# http://www.olimex.com/dev/lpc-1766stk.html
+#
+
+source [find target/lpc17xx.cfg]
+
+# The chip has just been reset.
+#
+$_TARGETNAME configure -event reset-init {
+	# FIXME update the core clock to run at 100 MHz;
+	# and update JTAG clocking similarly; then
+	# make CCLK match,
+
+	flash probe 0
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/iar_str912_sk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/iar_str912_sk.cfg
new file mode 100644
index 0000000..d94c0ce
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/iar_str912_sk.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IAR str912-sk evaluation kick start board has an str912
+
+source [find target/str912.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/icnova_imx53_sodimm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/icnova_imx53_sodimm.cfg
new file mode 100644
index 0000000..c4e8bde
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/icnova_imx53_sodimm.cfg
@@ -0,0 +1,450 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#################################################################################################
+# Author: Benjamin Tietz                                         ;#
+# based on work from: Wjatscheslaw Stoljarski (Slawa)    ;#
+# Kiwigrid GmbH                                                                                ;#
+# Generated for In-Circuit i.MX53 SO-Dimm                                                      ;#
+#################################################################################################
+
+# The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip
+source [find target/imx53.cfg]
+# Helper for common memory read/modify/write procedures
+source [find mem_helper.tcl]
+
+echo "i.MX53 SO-Dimm board lodaded."
+
+# Set reset type
+#reset_config srst_only
+
+adapter speed 3000
+
+# Slow speed to be sure it will work
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+
+$_TARGETNAME configure -event "reset-assert" {
+	echo "Resetting ...."
+	#cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-init { sodimm_init }
+
+global AIPS1_BASE_ADDR
+set AIPS1_BASE_ADDR     0x53F00000
+global AIPS2_BASE_ADDR
+set AIPS2_BASE_ADDR     0x63F00000
+
+proc sodimm_init { } {
+	echo "Reset-init..."
+	; # halt the CPU
+	halt
+
+	echo "HW version [format %x [mrw 0x48]]"
+
+	dap apsel 1
+	DCD
+
+	; # ARM errata ID #468414
+	set tR [arm mrc 15 0 1 0 1]
+	arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]	; # enable L1NEON bit
+
+	init_l2cc
+	init_aips
+	init_clock
+
+	dap apsel 0
+
+	; # Force ARM state
+	; #reg cpsr 0x000001D3
+	arm core_state arm
+
+	jtag_rclk 3000
+#	adapter speed 3000
+}
+
+
+# L2CC Cache setup/invalidation/disable
+proc init_l2cc { } {
+	; #/* explicitly disable L2 cache */
+	; #mrc 15, 0, r0, c1, c0, 1
+	set tR [arm mrc 15 0 1 0 1]
+	; #bic r0, r0, #0x2
+	; #mcr 15, 0, r0, c1, c0, 1
+	arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
+
+	; #/* reconfigure L2 cache aux control reg */
+	; #mov r0, #0xC0                   /* tag RAM */
+	; #add r0, r0, #0x4                /* data RAM */
+	; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+	; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+	; #orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	; #mcr 15, 1, r0, c9, c0, 2
+	arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
+}
+
+
+# AIPS setup - Only setup MPROTx registers.
+# The PACR default values are good.
+proc init_aips { } {
+	; # Set all MPROTx to be non-bufferable, trusted for R/W,
+	; # not forced to user-mode.
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set VAL			0x77777777
+
+#	dap apsel 1
+	mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
+#	dap apsel 0
+}
+
+
+proc init_clock { } {
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set CCM_BASE_ADDR	[expr {$AIPS1_BASE_ADDR + 0x000D4000}]
+	set CLKCTL_CCSR         0x0C
+	set CLKCTL_CBCDR	0x14
+	set CLKCTL_CBCMR        0x18
+	set PLL1_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00080000}]
+	set PLL2_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00084000}]
+	set PLL3_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00088000}]
+	set PLL4_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x0008C000}]
+	set CLKCTL_CSCMR1	0x1C
+	set CLKCTL_CDHIPR	0x48
+	set PLATFORM_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x000A0000}]
+	set CLKCTL_CSCDR1	0x24
+	set CLKCTL_CCDR		0x04
+
+	; # Switch ARM to step clock
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
+
+	return
+	echo "not returned"
+	setup_pll $PLL1_BASE_ADDR 800
+	setup_pll $PLL3_BASE_ADDR 400
+
+	; # Switch peripheral to PLL3
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL2_BASE_ADDR 400
+
+	; # Switch peripheral to PLL2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
+
+	; # change uart clk parent to pll2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
+
+	; # make sure change is effective
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL3_BASE_ADDR 216
+
+	setup_pll $PLL4_BASE_ADDR 455
+
+	; # Set the platform clock dividers
+	mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
+
+	mww [expr {$CCM_BASE_ADDR + 0x10}] 0
+
+	; # Switch ARM back to PLL 1.
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
+
+	; # make uart div=6
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
+
+	; # Restore the default values in the Gate registers
+	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
+
+	; # for cko - for ARM div by 8
+	mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
+}
+
+
+proc setup_pll { PLL_ADDR CLK } {
+	set PLL_DP_CTL		0x00
+	set PLL_DP_CONFIG   	0x04
+	set PLL_DP_OP		0x08
+	set PLL_DP_HFS_OP	0x1C
+	set PLL_DP_MFD		0x0C
+	set PLL_DP_HFS_MFD	0x20
+	set PLL_DP_MFN		0x10
+	set PLL_DP_HFS_MFN	0x24
+
+	if {$CLK == 1000} {
+		set DP_OP	[expr {(10 << 4) + ((1 - 1) << 0)}]
+		set DP_MFD	[expr {12 - 1}]
+		set DP_MFN	5
+	} elseif {$CLK == 850} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	41
+	} elseif {$CLK == 800} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 700} {
+		set DP_OP	[expr {(7 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	7
+	} elseif {$CLK == 600} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 665} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {96 - 1}]
+		set DP_MFN	89
+	} elseif {$CLK == 532} {
+		set DP_OP	[expr {(5 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	13
+	} elseif {$CLK == 455} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	71
+	} elseif {$CLK == 400} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 216} {
+		set DP_OP	[expr {(6 << 4) + ((3 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	3
+	} else {
+		error "Error (setup_dll): clock not found!"
+	}
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
+
+	mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
+}
+
+
+proc CPU_2_BE_32 { L } {
+	return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
+}
+
+
+# Device Configuration Data
+proc DCD { } {
+#	dap apsel 1
+#*========================================================================================== ======
+# Initialization script for 32 bit DDR3 (CS0+CS1)
+#*========================================================================================== ======
+# Remux D24/D25 to perform Flash-access
+	mww 0x53fa818C 0x00000000 ; #EIM_RW
+	mww 0x53fa8180 0x00000000 ; #EIM_CS0
+	mww 0x53fa8188 0x00000000 ; #EIM_OE
+	mww 0x53fa817C 0x00000000 ; #A16
+	mww 0x53fa8178 0x00000000 ; #A17
+	mww 0x53fa8174 0x00000000 ; #A18
+	mww 0x53fa8170 0x00000000 ; #A19
+	mww 0x53fa816C 0x00000000 ; #A20
+	mww 0x53fa8168 0x00000000 ; #A21
+	mww 0x53fa819C 0x00000000 ; #DA0
+	mww 0x53fa81A0 0x00000000 ; #DA1
+	mww 0x53fa81A4 0x00000000 ; #DA2
+	mww 0x53fa81A8 0x00000000 ; #DA3
+	mww 0x53fa81AC 0x00000000 ; #DA4
+	mww 0x53fa81B0 0x00000000 ; #DA5
+	mww 0x53fa81B4 0x00000000 ; #DA6
+	mww 0x53fa81B8 0x00000000 ; #DA7
+	mww 0x53fa81BC 0x00000000 ; #DA8
+	mww 0x53fa81C0 0x00000000 ; #DA9
+	mww 0x53fa81C4 0x00000000 ; #DA10
+	mww 0x53fa81C8 0x00000000 ; #DA11
+	mww 0x53fa81CC 0x00000000 ; #DA12
+	mww 0x53fa81D0 0x00000000 ; #DA13
+	mww 0x53fa81D4 0x00000000 ; #DA14
+	mww 0x53fa81D8 0x00000000 ; #DA15
+	mww 0x53fa8118 0x00000000 ; #D16
+	mww 0x53fa811C 0x00000000 ; #D17
+	mww 0x53fa8120 0x00000000 ; #D18
+	mww 0x53fa8124 0x00000000 ; #D19
+	mww 0x53fa8128 0x00000000 ; #D20
+	mww 0x53fa812C 0x00000000 ; #D21
+	mww 0x53fa8130 0x00000000 ; #D22
+	mww 0x53fa8134 0x00000000 ; #D23
+	mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24
+	mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25
+	mww 0x53fa8144 0x00000000 ; #D26
+	mww 0x53fa8148 0x00000000 ; #D27
+	mww 0x53fa814C 0x00000000 ; #D28
+	mww 0x53fa8150 0x00000000 ; #D29
+	mww 0x53fa8154 0x00000000 ; #D30
+	mww 0x53fa8158 0x00000000 ; #D31
+
+# DDR3 IOMUX configuration
+#* Global pad control options */
+	mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+	mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
+	mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+	mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+	mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
+	mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency
+	mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+	mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency
+	mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
+	mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+	mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+	mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+	mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
+	mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+	mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS
+	mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+	mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+#	mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
+	mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
+	mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS
+	mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS
+	mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS
+	mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX
+	mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS
+	mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS
+#	mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode
+#	mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode
+#	mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+#	mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
+
+#* Data bus byte lane pad drive strength control options */
+#	mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS
+#	mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+#	mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
+#	mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS
+#	mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+#	mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
+#	mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS
+#	mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+#	mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
+#	mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS
+#	mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+#	mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
+
+#* SDCLK pad drive strength control options */
+#	mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
+#	mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
+
+#* Control and addr bus pad drive strength control options */
+#	mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+#	mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+#	mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
+#	mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE
+
+#	mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+#	mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+
+# Initialize DDR3 memory - Micron MT41J128M16-187Er
+#** Keep for now, same setting as CPU3 board **#
+	mww 0x63fd901c 0x00008000
+#	mww 0x63fd904c 0x01680172 ; #write leveling reg 0
+#	mww 0x63fd9050 0x0021017f ; #write leveling reg 1
+	mww 0x63fd9088 0x32383535 ; #read delay lines
+	mww 0x63fd9090 0x40383538 ; #write delay lines
+#	mww 0x63fd90F8 0x00000800 ; #Measure unit
+	mww 0x63fd907c 0x0136014d ; #DQS gating 0
+	mww 0x63fd9080 0x01510141 ; #DQS gating 1
+#* CPU3 Board settingr
+# Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
+#	mww 0x63fd9018 0x00091740 ; #Misc register:
+#* Quick Silver board setting
+# Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
+	mww 0x63fd9018 0x00011740 ; #Misc register
+
+# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
+#	mww 0x63fd9000 0xc3190000 ; #Main control register
+# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
+	mww 0x63fd9000 0x83190000 ; #Main control register
+# tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
+	mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0
+# tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
+	mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1
+# tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
+	mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2
+	mww 0x63fd902c 0x000026d2 ; #command delay (default)
+	mww 0x63fd9030 0x009f0e21 ; #out of reset delays
+# Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
+	mww 0x63fd9008 0x12273030 ; #ODT timings
+# tCKE=3; tCKSRX=5; tCKSRE=5
+	mww 0x63fd9004 0x0002002d
+#Power down control
+#**********************************
+#DDR device configuration:
+#**********************************
+#**********************************
+# CS0:
+#**********************************
+	mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)
+# Full array self refresh
+# Rtt_WR disabled (no ODT at IO CMOS operation)
+# Manual self refresh
+# CWS=5
+	mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.
+	mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)
+# out impedance = RZQ/7
+# Rtt_nom disabled (no ODT at IO CMOS operation)
+# Aditive latency off
+# write leveling disabled
+# tdqs (differential?) disabled
+
+	mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0
+	mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)
+#**********************************
+# CS1:
+#**********************************
+#	mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.
+#	mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.
+#	mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7
+#	mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.
+#	mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)
+#**********************************
+
+
+	mww 0x63fd9020 0x00001800 ; # Refresh control register
+	mww 0x63fd9040 0x04b80003 ; # ZQ HW control
+	mww 0x63fd9058 0x00022227 ; # ODT control register
+
+	mww 0x63fd901c 0x00000000
+
+# CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)
+#	mww 0x53FA8314 = 0
+#	mww 0x53FA8320 0x4
+#	mww 0x53FD4060 0x01e900f0
+
+#	dap apsel 0
+}
+
+# IRAM
+$_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1
+
+flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME
+
+# vim:filetype=tcl
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/icnova_sam9g45_sodimm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/icnova_sam9g45_sodimm.cfg
new file mode 100644
index 0000000..7efa8c2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/icnova_sam9g45_sodimm.cfg
@@ -0,0 +1,276 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#################################################################################################
+#												                                                #
+# Author: Lars Poeschel (larsi@wh2.tu-dresden.de)												#
+# Generated for In-Circuit ICnova SAM9G45 SODIMM												#
+# http://www.ic-board.de/product_info.php?info=p214_ICnova-SAM9G45-SODIMM.html|ICnova			#
+#																								#
+#################################################################################################
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+source [find target/at91sam9g45.cfg]
+
+# Set reset type.
+# reset_config trst_and_srst
+
+# adapter srst delay 200
+# jtag_ntrst_delay 200
+
+
+# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
+# AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
+# some powerful features, we want to have a special function that handles "reset init".  To do this we declare
+# an event handler where these special activities can take place.
+
+scan_chain
+$_TARGETNAME configure -event reset-init {at91sam9g45_init}
+
+# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
+# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+$_TARGETNAME configure -event reset-start {at91sam9g45_start}
+
+
+# NandFlash configuration and definition
+# Future TBD
+# Flash configuration
+# flash bank cfi     
+set _FLASHNAME $_CHIPNAME.flash
+# set _NANDNAME $_CHIPNAME.nand
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+# nand device $_NANDNAME at91sam9 $_TARGETNAME 0x40000000 0xFFFFE800
+
+
+proc read_register {register} {
+	return [read_memory $register 32 1]
+}
+
+proc at91sam9g45_start { } {
+
+	# Make sure that the the jtag is running slow, since there are a number of different ways the board
+	# can be configured coming into this state that can cause communication problems with the jtag
+	# adapter.  Also since this call can be made following a "reset init" where fast memory accesses
+	# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
+	# jtag speed without causing GDB keep alive problem.
+
+	arm7_9 fast_memory_access disable
+    # Slow-speed oscillator enabled at reset, so run jtag speed slow.
+	adapter speed 4
+    # Make sure processor is halted, or error will result in following steps.
+	halt
+	wait_halt 10000
+    # RSTC_MR : enable user reset.
+	mww 0xfffffd08 0xa5000501
+}
+
+
+proc at91sam9g45_init { } {
+
+	# At reset AT91SAM9G45 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
+	# a number of steps that must be carefully performed.  The process outline below follows the
+	# recommended procedure outlined in the AT91SAM9G45 technical manual.
+	#
+	# Several key and very important things to keep in mind:
+	# The SDRAM parts used currently on the board are -75 grade parts.  This
+	# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
+	# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+	# Make sure processor is halted, or error will result in following steps.
+	halt
+	# RSTC_MR : enable user reset.
+	mww 0xfffffd08 0xa5000501
+	# WDT_MR : disable watchdog.
+	mww 0xfffffd44 0x00008000
+
+	# Enable the main 15.000 MHz oscillator in CKGR_MOR register.
+	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
+
+	mww 0xfffffc20 0x00004001
+	while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
+
+	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
+	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+	#mww 0xfffffc28 0x202a3f01
+	mww 0xfffffc28 0x20c73f03
+	while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
+
+	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	#mww 0xfffffc30 0x00000101
+	mww 0xfffffc30 0x00001301
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Now change PMC_MCKR register to select PLLA.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00001302
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Processor and master clocks are now operating and stable at maximum frequency possible:
+	#	-> MCLK = 132.096 MHz
+	#	-> PCLK = 396.288 MHz
+
+	# Switch over to adaptive clocking.
+
+	adapter speed 6000
+
+	# Enable faster DCC downloads.
+
+	arm7_9 dcc_downloads enable
+
+	# To be able to use external SDRAM, several peripheral configuration registers must
+	# be modified.  The first change is made to PIO_ASR to select peripheral functions
+	# for D15 through D31.  The second change is made to the PIO_PDR register to disable
+	# this for D15 through D31.
+
+#	mww 0xfffff870 0xffff0000
+#	mww 0xfffff804 0xffff0000
+
+	# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+	# using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
+	# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+	# mww 0xffffef1c 0x000100a
+
+	# The ICnova SAM9G45 SODIMM has built-in NandFlash.  The exact physical timing characteristics
+	# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+	# four registers in order:  SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
+
+	# mww 0xffffec30 0x00020002
+	# mww 0xffffec34 0x04040404
+	# mww 0xffffec38 0x00070007
+	# mww 0xffffec3c 0x00030003
+
+	# Identify NandFlash bank 0.  Disabled at the moment because a memory driver is not yet complete.
+
+#	nand probe 0
+
+    # SMC_SETUP0 : Setup SMC for NOR Flash
+	mww 0xffffe800 0x0012000a
+    # SMC_PULSE0
+	mww 0xffffe804 0x3b38343b
+    # SMC_CYCLE0
+	mww 0xffffe808 0x003f003f
+    # SMC_MODE0
+	mww 0xffffe80c 0x00001000
+    # Identify flash bank 0
+	flash probe 0
+
+	# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
+	# are based on 2 x Samsung K4T51083QG memory.
+
+	# 0. Enable DDR2 Clock
+	mww 0xfffffc00 0x4
+	# 1. Program memory device type
+	# 1.1 configure the DDR controller
+	mww 0xffffe620 0x16
+	# 1.2 program the DDR controller
+	mww 0xffffe608 0x3d
+
+	# 2. program memory device features
+	# 2.1 assume timings for 7.5ns min clock period
+	mww 0xffffe60c 0x21128226
+	# 2.2 pSDDRC->HDDRSDRC2_T1PR
+	mww 0xffffe610 0x02c8100e
+	# 2.3 pSDDRC->HDDRSDRC2_T2PR
+	mww 0xffffe614 0x01000702
+	# 3. NOP
+	mww 0xffffe600 0x1
+	mww 0x70000000 0x1
+	# 3.1 delay 200us
+	sleep 1
+	# jim tcl alternative: after ms
+	# after 0.2
+
+	# 4. NOP
+	mww 0xffffe600 0x1
+	mww 0x70000000 0x1
+	# 4.1 delay 400ns
+
+	# 5. set all bank precharge
+	mww 0xffffe600 0x2
+	mww 0x70000000 0x1
+	# 5.1 delay 400ns
+
+	# 6. set EMR operation (EMRS2)
+	mww 0xffffe600 0x5
+	mww 0x74000000 0x1
+	# 6.1 delay 2 cycles
+
+	# 7. set EMR operation (EMRS3)
+	mww 0xffffe600 0x5
+	mww 0x76000000 0x1
+	# 7.1 delay 2 cycles
+
+	# 8. set EMR operation (EMRS1)
+	mww 0xffffe600 0x5
+	mww 0x72000000 0x1
+	# 8.1 delay 200 cycles (400Mhz -> 5 * 10^-7s)
+	sleep 1
+
+	# 9. Enable DLL Reset (set DLL bit)
+	set CR  [expr {[read_register 0xffffe608] | 0x80}]
+	mww 0xffffe608 $CR
+
+	# 10. mode register cycle to reset the DLL
+	mww 0xffffe600 0x5
+	mww 0x70000000 0x1
+	# 10.1 delay 2 cycles
+
+	# 11. set all bank precharge
+	mww 0xffffe600 0x2
+	mww 0x70000000 0x1
+	# 11.1 delay 400 ns
+
+	# 12. two auto-refresh (CBR) cycles are provided.
+	mww 0xffffe600 0x4
+	mww 0x70000000 0x1
+	# 12.1 delay 10 cycles
+	# 12.2 2nd cycle (schreiben des Mode Register sparen wir uns)
+	mww 0x70000000 0x1
+	# 12.3 delay 10 cycles
+
+	# 13. disable DLL reset (clear DLL bit)
+	set CR  [expr {[read_register 0xffffe608] & 0xffffff7f}]
+	mww 0xffffe608 $CR
+
+	# 14. mode register set cycle
+	mww 0xffffe600 0x3
+	mww 0x70000000 0x1
+
+	# 15. program OCD field (set OCD bits)
+	set CR  [expr {[read_register 0xffffe608] | 0x7000}]
+	mww 0xffffe608 $CR
+
+	# 16. (EMRS1)
+	mww 0xffffe600 0x5
+	mww 0x72000000 0x1
+	# 16.1 delay 2 cycles
+
+	# 17. disable OCD field (clear OCD bits)
+	set CR  [expr {[read_register 0xffffe608] & 0xffff8fff}]
+	mww 0xffffe608 $CR
+
+	# 18. (EMRS1)
+	mww 0xffffe600 0x5
+	mww 0x76000000 0x1
+	# 18.1 delay 2 cycles
+
+	# 19. normal mode command
+	mww 0xffffe600 0x0
+	mww 0x70000000 0x1
+
+	# 20. perform write to any address
+	#mww 0x70000000 0x1
+
+	# 21. write refresh rate into the count field of the refresh rate register
+	mww 0xffffe604 0x24b
+	# 21.1 delay (500 * 6 cycles)
+
+	arm7_9 fast_memory_access enable
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx27ads.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx27ads.cfg
new file mode 100644
index 0000000..79d3c51
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx27ads.cfg
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IMX27 ADS eval board has a single IMX27 chip
+# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
+source [find target/imx27.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { imx27ads_init }
+
+# The IMX27 ADS board has a NOR flash on CS0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
+
+proc imx27ads_init { } {
+	# This setup puts RAM at 0xA0000000
+
+	# reset the board correctly
+	reset run
+	reset halt
+
+	mww 0x10000000 0x20040304
+	mww 0x10020000 0x00000000
+	mww 0x10000004 0xDFFBFCFB
+	mww 0x10020004 0xFFFFFFFF
+
+	sleep 100
+
+	# ========================================
+	#  Configure DDR on CSD0 -- initial reset
+	# ========================================
+	mww 0xD8001010 0x00000008
+
+	# ========================================
+	#  Configure PSRAM on CS5
+	# ========================================
+	mww 0xd8002050 0x0000dcf6
+	mww 0xd8002054 0x444a4541
+	mww 0xd8002058 0x44443302
+
+	#  ========================================
+	#         Configure16 bit NorFlash on CS0
+	#  ========================================
+	mww 0xd8002000 0x0000CC03
+	mww 0xd8002004 0xa0330D01
+	mww 0xd8002008 0x00220800
+
+	# ========================================
+	#  Configure CPLD on CS4
+	# ========================================
+	mww 0xd8002040 0x0000DCF6
+	mww 0xd8002044 0x444A4541
+	mww 0xd8002048 0x44443302
+
+	# ========================================
+	#  Configure DDR on CSD0 -- wait 5000 cycle
+	# ========================================
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
+
+	mww 0xD8001010 0x00000004
+
+	mww 0xD8001004 0x00795729
+
+	mww 0xD8001000 0x92200000
+	mww 0xA0000F00 0x0
+
+	mww 0xD8001000 0xA2200000
+	mww 0xA0000F00 0x0
+	mww 0xA0000F00 0x0
+
+	mww 0xD8001000 0xB2200000
+	mwb 0xA0000033 0xFF
+	mwb 0xA1000000 0xAA
+
+	mww 0xD8001000 0x82228085
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx27lnst.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx27lnst.cfg
new file mode 100644
index 0000000..24f6ed8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx27lnst.cfg
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Linuxstamp-mx27 is board has a single IMX27 chip
+# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
+source [find target/imx27.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { imx27lnst_init }
+
+proc imx27lnst_init { } {
+	# This setup puts RAM at 0xA0000000
+
+	# reset the board correctly
+	adapter speed 500
+	reset run
+	reset halt
+
+	mww 0x10000000 0x20040304
+	mww 0x10020000 0x00000000
+	mww 0x10000004 0xDFFBFCFB
+	mww 0x10020004 0xFFFFFFFF
+
+	sleep 100
+
+	# ========================================
+	#  Configure DDR on CSD0 -- initial reset
+	# ========================================
+	mww 0xD8001010 0x00000008
+
+	sleep 100
+
+	# ========================================
+	#  Configure DDR on CSD0 -- wait 5000 cycle
+	# ========================================
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
+
+	mww 0xD8001010 0x00000004
+
+	mww 0xD8001004 0x00795729
+
+	#mww 0xD8001000 0x92200000
+	mww 0xD8001000 0x91120000
+	mww 0xA0000F00 0x0
+
+	#mww 0xD8001000 0xA2200000
+	mww 0xD8001000 0xA1120000
+	mww 0xA0000F00 0x0
+	mww 0xA0000F00 0x0
+
+	#mww 0xD8001000 0xB2200000
+	mww 0xD8001000 0xB1120000
+	mwb 0xA0000033 0xFF
+	mwb 0xA1000000 0xAA
+
+	#mww 0xD8001000 0x82228085
+	mww 0xD8001000 0x81128080
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx28evk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx28evk.cfg
new file mode 100644
index 0000000..cc13c51
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx28evk.cfg
@@ -0,0 +1,170 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IMX28EVK eval board has a IMX28 chip
+# Tested on SCH-26241 Rev D board with Olimex ARM-USB-OCD
+# Date:	201-02-01
+# Authors: James Robinson & Fabio Estevam
+
+source [find target/imx28.cfg]
+$_TARGETNAME configure -event gdb-attach { imx28evk_init }
+$_TARGETNAME configure -event reset-init { imx28evk_init }
+
+proc imx28evk_init { } {
+
+	halt
+
+	#****************************
+	# VDDD setting
+	#****************************
+	# set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e
+	mww 0x80044010 0x0003F503
+	mww 0x80044040 0x0002041E
+
+	#****************************
+	# CLOCK set up
+	#****************************
+	# Power up PLL0 HW_CLKCTRL_PLL0CTRL0
+	mww 0x80040000 0x00020000
+	# Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0
+	# EMI - first set DIV_EMI to div-by-2 before programming frac divider
+	mww 0x800400F0 0x80000002
+
+
+	# CPU: CPUFRAC=19 480*18/29=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz
+	mww 0x800401B0 0x92921613
+	# Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR
+	mww 0x800401D8 0x00040080
+	# HCLK = 227MHz,HW_CLKCTRL_HBUS DIV =0x2
+	mww 0x80040060 0x00000002
+
+	#****************************
+	# POWER up DCDD_VDDA (DDR2)
+	#****************************
+	# Now set the voltage level to 1.8V HW_POWER_VDDACTRL bits TRC=0xC
+	mww 0x80044050 0x0000270C
+
+	#****************************
+	# DDR2 DCDD_VDDA
+	#****************************
+	# First set up pin muxing and drive strength
+	# Ungate module clock and bring out of reset HW_PINCTRL_CTRL_CLR
+	mww 0x80018008 0xC0000000
+
+	#****************************
+	# EMI PAD setting
+	#****************************
+	# Set up drive strength for EMI pins
+	mww 0x80019B80 0x00030000
+	#IOMUXC_SW_PAD_CTL_GRP_CTLDS
+
+	# Set up pin muxing for EMI, HW_PINCTRL_MUXSEL10, 11, 12, 13
+	mww 0x800181A8 0xFFFFFFFF
+	mww 0x800181B8 0xFFFFFFFF
+	mww 0x800181C8 0xFFFFFFFF
+	mww 0x800181D8 0xFFFFFFFF
+
+	#** Ungate EMI clock in CCM
+	mww 0x800400F0 0x00000002
+
+	#============================================================================
+	# DDR Controller Registers
+	#============================================================================
+	# Manufacturer:    Elpida
+	# Device Part Number:    EDE1116AEBG
+	# Clock Freq.:     200MHz
+	# Density:         1Gb
+	# Chip Selects:    1
+	# Number of Banks: 8
+	# Row address:     13
+	# Column address:  10
+	#============================================================================
+	mww 0x800E0000 0x00000000
+	mww 0x800E0040 0x00000000
+	mww 0x800E0054 0x00000000
+	mww 0x800E0058 0x00000000
+	mww 0x800E005C 0x00000000
+	mww 0x800E0060 0x00000000
+	mww 0x800E0064 0x00000000
+	mww 0x800E0068 0x00010101
+	mww 0x800E006C 0x01010101
+	mww 0x800E0070 0x000f0f01
+	mww 0x800E0074 0x0102020A
+	mww 0x800E007C 0x00010101
+	mww 0x800E0080 0x00000100
+	mww 0x800E0084 0x00000100
+	mww 0x800E0088 0x00000000
+	mww 0x800E008C 0x00000002
+	mww 0x800E0090 0x01010000
+	mww 0x800E0094 0x07080403
+	mww 0x800E0098 0x06005003
+	mww 0x800E009C 0x0A0000C8
+	mww 0x800E00A0 0x02009C40
+	mww 0x800E00A4 0x0002030C
+	mww 0x800E00A8 0x0036B009
+	mww 0x800E00AC 0x031A0612
+	mww 0x800E00B0 0x02030202
+	mww 0x800E00B4 0x00C8001C
+	mww 0x800E00C0 0x00011900
+	mww 0x800E00C4 0xffff0303
+	mww 0x800E00C8 0x00012100
+	mww 0x800E00CC 0xffff0303
+	mww 0x800E00D0 0x00012100
+	mww 0x800E00D4 0xffff0303
+	mww 0x800E00D8 0x00012100
+	mww 0x800E00DC 0xffff0303
+	mww 0x800E00E0 0x00000003
+	mww 0x800E00E8 0x00000000
+	mww 0x800E0108 0x00000612
+	mww 0x800E010C 0x01000f02
+	mww 0x800E0114 0x00000200
+	mww 0x800E0118 0x00020007
+	mww 0x800E011C 0xf4004a27
+	mww 0x800E0120 0xf4004a27
+	mww 0x800E012C 0x07400300
+	mww 0x800E0130 0x07400300
+	mww 0x800E013C 0x00000005
+	mww 0x800E0140 0x00000000
+	mww 0x800E0144 0x00000000
+	mww 0x800E0148 0x01000000
+	mww 0x800E014C 0x01020408
+	mww 0x800E0150 0x08040201
+	mww 0x800E0154 0x000f1133
+	mww 0x800E015C 0x00001f04
+	mww 0x800E0160 0x00001f04
+	mww 0x800E016C 0x00001f04
+	mww 0x800E0170 0x00001f04
+	mww 0x800E0288 0x00010000
+	mww 0x800E028C 0x00030404
+	mww 0x800E0290 0x00000003
+	mww 0x800E02AC 0x01010000
+	mww 0x800E02B0 0x01000000
+	mww 0x800E02B4 0x03030000
+	mww 0x800E02B8 0x00010303
+	mww 0x800E02BC 0x01020202
+	mww 0x800E02C0 0x00000000
+	mww 0x800E02C4 0x02030303
+	mww 0x800E02C8 0x21002103
+	mww 0x800E02CC 0x00061200
+	mww 0x800E02D0 0x06120612
+	mww 0x800E02D4 0x04420442
+	# Mode register 0 for CS1 and CS0, ok to program CS1 even if not used
+	mww 0x800E02D8 0x00000000
+	# Mode register 0 for CS2 and CS3, not supported in this processor
+	mww 0x800E02DC 0x00040004
+	# Mode register 1 for CS1 and CS0, ok to program CS1 even if not used
+	mww 0x800E02E0 0x00000000
+	# Mode register 1 for CS2 and CS3, not supported in this processor
+	mww 0x800E02E4 0x00000000
+	# Mode register 2 for CS1 and CS0, ok to program CS1 even if not used
+	mww 0x800E02E8 0x00000000
+	# Mode register 2 for CS2 and CS3, not supported in this processor
+	mww 0x800E02EC 0x00000000
+	# Mode register 3 for CS1 and CS0, ok to program CS1 even if not used
+	mww 0x800E02F0 0x00000000
+	# Mode register 3 for CS2 and CS3, not supported in this processor
+	mww 0x800E02F4 0xffffffff
+
+	#**  start controller **#
+	mww 0x800E0040 0x00000001
+	# bit[0]: start
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx31pdk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx31pdk.cfg
new file mode 100644
index 0000000..65fa520
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx31pdk.cfg
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IMX31PDK eval board has a single IMX31 chip
+source [find target/imx31.cfg]
+source [find target/imx.cfg]
+$_TARGETNAME configure -event reset-init { imx31pdk_init }
+
+proc self_test {} {
+	echo "Running 100 iterations of test."
+	dump_image /ram/test 0x80000000 0x40000
+	for {set i 0} {$i < 100} {set i [expr {$i+1}]} {
+		echo "Iteration $i"
+		reset init
+		mww 0x80000000 0x12345678 0x10000
+		load_image /ram/test 0x80000000 bin
+		verify_image /ram/test 0x80000000 bin
+	}
+}
+
+
+# Slow fallback frequency
+# measure_clk indicates ca. 3-4MHz.
+jtag_rclk 1000
+
+proc imx31pdk_init { } {
+
+	imx3x_reset
+
+	# This setup puts RAM at 0x80000000
+
+	mww 0x53FC0000 0x040
+	mww 0x53F80000 0x074B0B7D
+
+	# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
+	#mww 0x53F80004 0xFF871D50
+	#mww 0x53F80010 0x00271C1B
+
+	# Start 16 bit NorFlash Initialization on CS0
+	mww 0xb8002000 0x0000CC03
+	mww 0xb8002004 0xa0330D01
+	mww 0xb8002008 0x00220800
+
+	# Configure CPLD on CS4
+	mww 0xb8002040 0x0000DCF6
+	mww 0xb8002044 0x444A4541
+	mww 0xb8002048 0x44443302
+
+	# SDCLK
+	mww 0x43FAC26C 0
+
+	# CAS
+	mww 0x43FAC270 0
+
+	# RAS
+	mww 0x43FAC274 0
+
+	# CS2 (CSD0)
+	mww 0x43FAC27C 0x1000
+
+	# DQM3
+	mww 0x43FAC284 0
+
+	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
+	mww 0x43FAC288 0
+	mww 0x43FAC28C 0
+	mww 0x43FAC290 0
+	mww 0x43FAC294 0
+	mww 0x43FAC298 0
+	mww 0x43FAC29C 0
+	mww 0x43FAC2A0 0
+	mww 0x43FAC2A4 0
+	mww 0x43FAC2A8 0
+	mww 0x43FAC2AC 0
+	mww 0x43FAC2B0 0
+	mww 0x43FAC2B4 0
+	mww 0x43FAC2B8 0
+	mww 0x43FAC2BC 0
+	mww 0x43FAC2C0 0
+	mww 0x43FAC2C4 0
+	mww 0x43FAC2C8 0
+	mww 0x43FAC2CC 0
+	mww 0x43FAC2D0 0
+	mww 0x43FAC2D4 0
+	mww 0x43FAC2D8 0
+	mww 0x43FAC2DC 0
+
+	# Initialization script for 32 bit DDR on MX31 ADS
+	mww 0xB8001010 0x00000004
+	mww 0xB8001004 0x006ac73a
+	mww 0xB8001000 0x92100000
+	mww 0x80000f00 0x12344321
+	mww 0xB8001000 0xa2100000
+	mww 0x80000000 0x12344321
+	mww 0x80000000 0x12344321
+	mww 0xB8001000 0xb2100000
+	mwb 0x80000033 0xda
+	mwb 0x81000000 0xff
+	mww 0xB8001000 0x82226080
+	mww 0x80000000 0xDEADBEEF
+	mww 0xB8001010 0x0000000c
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx35pdk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx35pdk.cfg
new file mode 100644
index 0000000..41206c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx35pdk.cfg
@@ -0,0 +1,254 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The IMX35PDK eval board has a single IMX35 chip
+source [find target/imx35.cfg]
+source [find target/imx.cfg]
+$_TARGETNAME configure -event reset-init { imx35pdk_init }
+
+# Stick to *really* low clock rate or reset will fail
+# without RTCK / RCLK
+jtag_rclk 10
+
+proc imx35pdk_init { } {
+
+	imx3x_reset
+
+	mww 0x43f00040 0x00000000
+	mww 0x43f00044 0x00000000
+	mww 0x43f00048 0x00000000
+	mww 0x43f0004C 0x00000000
+	mww 0x43f00050 0x00000000
+	mww 0x43f00000 0x77777777
+	mww 0x43f00004 0x77777777
+	mww 0x53f00040 0x00000000
+	mww 0x53f00044 0x00000000
+	mww 0x53f00048 0x00000000
+	mww 0x53f0004C 0x00000000
+	mww 0x53f00050 0x00000000
+	mww 0x53f00000 0x77777777
+	mww 0x53f00004 0x77777777
+
+	# clock setup
+	mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
+	mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
+
+	#=================================================
+	# WEIM config
+	#=================================================
+	# CS0U
+	mww 0xB8002000 0x0000CC03
+	# CS0L
+	mww 0xB8002004 0xA0330D01
+	# CS0A
+	mww 0xB8002008 0x00220800
+	# CS5U
+	mww 0xB8002050 0x0000dcf6
+	# CS5L
+	mww 0xB8002054 0x444a4541
+	# CS5A
+	mww 0xB8002058 0x44443302
+
+	# IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
+	mww 0x43FAC368 0x00000006
+	mww 0x43FAC36C 0x00000006
+	mww 0x43FAC370 0x00000006
+	mww 0x43FAC374 0x00000006
+	mww 0x43FAC378 0x00000006
+	mww 0x43FAC37C 0x00000006
+	mww 0x43FAC380 0x00000006
+	mww 0x43FAC384 0x00000006
+	mww 0x43FAC388 0x00000006
+	mww 0x43FAC38C 0x00000006
+	mww 0x43FAC390 0x00000006
+	mww 0x43FAC394 0x00000006
+	mww 0x43FAC398 0x00000006
+	mww 0x43FAC39C 0x00000006
+	mww 0x43FAC3A0 0x00000006
+	mww 0x43FAC3A4 0x00000006
+	mww 0x43FAC3A8 0x00000006
+	mww 0x43FAC3AC 0x00000006
+	mww 0x43FAC3B0 0x00000006
+	mww 0x43FAC3B4 0x00000006
+	mww 0x43FAC3B8 0x00000006
+	mww 0x43FAC3BC 0x00000006
+	mww 0x43FAC3C0 0x00000006
+	mww 0x43FAC3C4 0x00000006
+	mww 0x43FAC3C8 0x00000006
+	mww 0x43FAC3CC 0x00000006
+	mww 0x43FAC3D0 0x00000006
+	mww 0x43FAC3D4 0x00000006
+	mww 0x43FAC3D8 0x00000006
+
+	# DDR data bus SD 0 through 31
+	mww 0x43FAC3DC 0x00000082
+	mww 0x43FAC3E0 0x00000082
+	mww 0x43FAC3E4 0x00000082
+	mww 0x43FAC3E8 0x00000082
+	mww 0x43FAC3EC 0x00000082
+	mww 0x43FAC3F0 0x00000082
+	mww 0x43FAC3F4 0x00000082
+	mww 0x43FAC3F8 0x00000082
+	mww 0x43FAC3FC 0x00000082
+	mww 0x43FAC400 0x00000082
+	mww 0x43FAC404 0x00000082
+	mww 0x43FAC408 0x00000082
+	mww 0x43FAC40C 0x00000082
+	mww 0x43FAC410 0x00000082
+	mww 0x43FAC414 0x00000082
+	mww 0x43FAC418 0x00000082
+	mww 0x43FAC41c 0x00000082
+	mww 0x43FAC420 0x00000082
+	mww 0x43FAC424 0x00000082
+	mww 0x43FAC428 0x00000082
+	mww 0x43FAC42c 0x00000082
+	mww 0x43FAC430 0x00000082
+	mww 0x43FAC434 0x00000082
+	mww 0x43FAC438 0x00000082
+	mww 0x43FAC43c 0x00000082
+	mww 0x43FAC440 0x00000082
+	mww 0x43FAC444 0x00000082
+	mww 0x43FAC448 0x00000082
+	mww 0x43FAC44c 0x00000082
+	mww 0x43FAC450 0x00000082
+	mww 0x43FAC454 0x00000082
+	mww 0x43FAC458 0x00000082
+
+	# DQM setup
+	mww 0x43FAC45c 0x00000082
+	mww 0x43FAC460 0x00000082
+	mww 0x43FAC464 0x00000082
+	mww 0x43FAC468 0x00000082
+
+	mww 0x43FAC46c 0x00000006
+	mww 0x43FAC470 0x00000006
+	mww 0x43FAC474 0x00000006
+	mww 0x43FAC478 0x00000006
+	mww 0x43FAC47c 0x00000006
+	mww 0x43FAC480 0x00000006	;# CSD0
+	mww 0x43FAC484 0x00000006	;# CSD1
+	mww 0x43FAC488 0x00000006
+	mww 0x43FAC48c 0x00000006
+	mww 0x43FAC490 0x00000006
+	mww 0x43FAC494 0x00000006
+	mww 0x43FAC498 0x00000006
+	mww 0x43FAC49c 0x00000006
+	mww 0x43FAC4A0 0x00000006
+	mww 0x43FAC4A4 0x00000006	;# RAS
+	mww 0x43FAC4A8 0x00000006	;# CAS
+	mww 0x43FAC4Ac 0x00000006	;# SDWE
+	mww 0x43FAC4B0 0x00000006 	;# SDCKE0
+	mww 0x43FAC4B4 0x00000006  ;# SDCKE1
+	mww 0x43FAC4B8 0x00000002  ;# SDCLK
+
+	# SDQS0 through SDQS3
+	mww 0x43FAC4Bc 0x00000082
+	mww 0x43FAC4C0 0x00000082
+	mww 0x43FAC4C4 0x00000082
+	mww 0x43FAC4C8 0x00000082
+
+
+	# *==================================================
+	#  Initialization script for 32 bit DDR2 on RINGO 3DS
+	# *==================================================
+
+	#--------------------------------------------
+	# Init CCM
+	#--------------------------------------------
+	mww 0x53F80028 0x7D000028
+
+	#--------------------------------------------
+	# Init IOMUX for JTAG
+	#--------------------------------------------
+	mww 0x43FAC5EC 0x000000C3
+	mww 0x43FAC5F0 0x000000C3
+	mww 0x43FAC5F4 0x000000F3
+	mww 0x43FAC5F8 0x000000F3
+	mww 0x43FAC5FC 0x000000F3
+	mww 0x43FAC600 0x000000F3
+	mww 0x43FAC604 0x000000F3
+
+
+	# ESD_MISC : enable DDR2
+	mww 0xB8001010 0x00000304
+
+	#--------------------------------------------
+	# Init 32-bit DDR2 memory on CSD0
+	# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
+	#--------------------------------------------
+
+	# ESD_ESDCFG0 : set timing parameters
+	mww 0xB8001004 0x007ffC2f
+
+	# ESD_ESDCTL0 : select Prechare-All mode
+	mww 0xB8001000 0x92220000
+	# DDR2 : Prechare-All
+	mww 0x80000400 0x12345678
+
+	# ESD_ESDCTL0 : select Load-Mode-Register mode
+	mww 0xB8001000 0xB2220000
+	# DDR2 : Load reg EMR2
+	mwb 0x84000000 0xda
+	# DDR2 : Load reg EMR3
+	mwb 0x86000000 0xda
+	# DDR2 : Load reg EMR1 -- enable DLL
+	mwb 0x82000400 0xda
+	# DDR2 : Load reg MR -- reset DLL
+	mwb 0x80000333 0xda
+
+	# ESD_ESDCTL0 : select Prechare-All mode
+	mww 0xB8001000 0x92220000
+	# DDR2 : Prechare-All
+	mwb 0x80000400 0x12345678
+
+	# ESD_ESDCTL0 : select Manual-Refresh mode
+	mww 0xB8001000 0xA2220000
+	# DDR2 : Manual-Refresh 2 times
+	mww 0x80000000 0x87654321
+	mww 0x80000000 0x87654321
+
+	# ESD_ESDCTL0 : select Load-Mode-Register mode
+	mww 0xB8001000 0xB2220000
+	# DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
+	mwb 0x80000233 0xda
+	# DDR2 : Load reg EMR1 -- OCD default
+	mwb 0x82000780 0xda
+	# DDR2 : Load reg EMR1 -- OCD exit
+	mwb 0x82000400 0xda	;# ODT disabled
+
+	# ESD_ESDCTL0 : select normal-operation mode
+	# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
+	# disable PWT & PRCT
+	# disable Auto-Refresh
+	mww 0xB8001000 0x82220080
+
+	## ESD_ESDCTL0 : enable Auto-Refresh
+	mww 0xB8001000 0x82228080
+	## ESD_ESDCTL1 : enable Auto-Refresh
+	mww 0xB8001008 0x00002000
+
+
+	#***********************************************
+	# Adjust the ESDCDLY5 register
+	#***********************************************
+	# Vary DQS_ABS_OFFSET5 for writes
+	mww 0xB8001020 0x00F48000	;# this is the default value
+	mww 0xB8001024 0x00F48000	;# this is the default value
+	mww 0xB8001028 0x00F48000	;# this is the default value
+	mww 0xB800102c 0x00F48000	;# this is the default value
+
+
+	#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
+	mww 0xB8001010 0x00000384
+	# wait a while
+	sleep 1000
+	# now clear the force measurement bit
+	mww 0xB8001010 0x00000304
+
+	# dummy write to DDR memory to set DQS low
+	mww 0x80000000 0x00000000
+
+	mww 0x30000100 0x0
+	mww 0x30000104 0x31024
+
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx53-m53evk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx53-m53evk.cfg
new file mode 100644
index 0000000..6f9210a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx53-m53evk.cfg
@@ -0,0 +1,320 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#######################################
+# DENX M53EVK                         #
+# http://www.denx-cs.de/?q=M53EVK     #
+# Author: Marek Vasut  #
+# Based on imx53loco.cfg              #
+#######################################
+
+# The DENX M53EVK has on-board JTAG adapter
+source [find interface/ftdi/m53evk.cfg]
+# The DENX M53EVK board has a single i.MX53 chip
+source [find target/imx53.cfg]
+# Helper for common memory read/modify/write procedures
+source [find mem_helper.tcl]
+
+echo "iMX53 M53EVK board lodaded."
+
+# Set reset type
+reset_config trst_and_srst separate trst_open_drain srst_open_drain
+
+# Run at 6 MHz
+adapter speed 6000
+
+$_TARGETNAME configure -event "reset-assert" {
+	echo "Resetting ...."
+	#cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-init { m53evk_init }
+
+global AIPS1_BASE_ADDR
+set AIPS1_BASE_ADDR     0x53F00000
+global AIPS2_BASE_ADDR
+set AIPS2_BASE_ADDR     0x63F00000
+
+proc m53evk_init { } {
+	echo "Reset-init..."
+	; # halt the CPU
+	halt
+
+	echo "HW version [format %x [mrw 0x48]]"
+
+	dap apsel 1
+	DCD
+
+	; # ARM errata ID #468414
+	set tR [arm mrc 15 0 1 0 1]
+	arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]	; # enable L1NEON bit
+
+	init_l2cc
+	init_aips
+	init_clock
+
+	dap apsel 0
+
+	; # Force ARM state
+	; #reg cpsr 0x000001D3
+	arm core_state arm
+}
+
+
+# L2CC Cache setup/invalidation/disable
+proc init_l2cc { } {
+	; #/* explicitly disable L2 cache */
+	; #mrc 15, 0, r0, c1, c0, 1
+	set tR [arm mrc 15 0 1 0 1]
+	; #bic r0, r0, #0x2
+	; #mcr 15, 0, r0, c1, c0, 1
+	arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
+
+	; #/* reconfigure L2 cache aux control reg */
+	; #mov r0, #0xC0                   /* tag RAM */
+	; #add r0, r0, #0x4                /* data RAM */
+	; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+	; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+	; #orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	; #mcr 15, 1, r0, c9, c0, 2
+	arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
+}
+
+
+# AIPS setup - Only setup MPROTx registers.
+# The PACR default values are good.
+proc init_aips { } {
+	; # Set all MPROTx to be non-bufferable, trusted for R/W,
+	; # not forced to user-mode.
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set VAL			0x77777777
+
+#	dap apsel 1
+	mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
+#	dap apsel 0
+}
+
+
+proc init_clock { } {
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set CCM_BASE_ADDR	[expr {$AIPS1_BASE_ADDR + 0x000D4000}]
+	set CLKCTL_CCSR         0x0C
+	set CLKCTL_CBCDR	0x14
+	set CLKCTL_CBCMR        0x18
+	set PLL1_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00080000}]
+	set PLL2_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00084000}]
+	set PLL3_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00088000}]
+	set PLL4_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x0008C000}]
+	set CLKCTL_CSCMR1	0x1C
+	set CLKCTL_CDHIPR	0x48
+	set PLATFORM_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x000A0000}]
+	set CLKCTL_CSCDR1	0x24
+	set CLKCTL_CCDR		0x04
+
+	; # Switch ARM to step clock
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
+
+	return
+	echo "not returned"
+	setup_pll $PLL1_BASE_ADDR 800
+	setup_pll $PLL3_BASE_ADDR 400
+
+	; # Switch peripheral to PLL3
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL2_BASE_ADDR 400
+
+	; # Switch peripheral to PLL2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
+
+	; # change uart clk parent to pll2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
+
+	; # make sure change is effective
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL3_BASE_ADDR 216
+
+	setup_pll $PLL4_BASE_ADDR 455
+
+	; # Set the platform clock dividers
+	mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
+
+	mww [expr {$CCM_BASE_ADDR + 0x10}] 0
+
+	; # Switch ARM back to PLL 1.
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
+
+	; # make uart div=6
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
+
+	; # Restore the default values in the Gate registers
+	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
+
+	; # for cko - for ARM div by 8
+	mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
+}
+
+
+proc setup_pll { PLL_ADDR CLK } {
+	set PLL_DP_CTL		0x00
+	set PLL_DP_CONFIG   	0x04
+	set PLL_DP_OP		0x08
+	set PLL_DP_HFS_OP	0x1C
+	set PLL_DP_MFD		0x0C
+	set PLL_DP_HFS_MFD	0x20
+	set PLL_DP_MFN		0x10
+	set PLL_DP_HFS_MFN	0x24
+
+	if {$CLK == 1000} {
+		set DP_OP	[expr {(10 << 4) + ((1 - 1) << 0)}]
+		set DP_MFD	[expr {12 - 1}]
+		set DP_MFN	5
+	} elseif {$CLK == 850} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	41
+	} elseif {$CLK == 800} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 700} {
+		set DP_OP	[expr {(7 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	7
+	} elseif {$CLK == 600} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 665} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {96 - 1}]
+		set DP_MFN	89
+	} elseif {$CLK == 532} {
+		set DP_OP	[expr {(5 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	13
+	} elseif {$CLK == 455} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	71
+	} elseif {$CLK == 400} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 216} {
+		set DP_OP	[expr {(6 << 4) + ((3 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	3
+	} else {
+		error "Error (setup_dll): clock not found!"
+	}
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
+
+	mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
+}
+
+
+proc CPU_2_BE_32 { L } {
+	return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
+}
+
+
+# Device Configuration Data
+proc DCD { } {
+#	dap apsel 1
+	mww 0x53fa86f4 0x00000000	 ;# GRP_DDRMODE_CTL
+	mww 0x53fa8714 0x00000000	 ;# GRP_DDRMODE
+	mww 0x53fa86fc 0x00000000	 ;# GRP_DDRPKE
+	mww 0x53fa8724 0x04000000	 ;# GRP_DDR_TYPE
+
+	mww 0x53fa872c 0x00300000	 ;# GRP_B3DS
+	mww 0x53fa8554 0x00300000	 ;# DRAM_DQM3
+	mww 0x53fa8558 0x00300040	 ;# DRAM_SDQS3
+
+	mww 0x53fa8728 0x00300000	 ;# GRP_B2DS
+	mww 0x53fa8560 0x00300000	 ;# DRAM_DQM2
+	mww 0x53fa8568 0x00300040	 ;# DRAM_SDQS2
+
+	mww 0x53fa871c 0x00300000	 ;# GRP_B1DS
+	mww 0x53fa8594 0x00300000	 ;# DRAM_DQM1
+	mww 0x53fa8590 0x00300040	 ;# DRAM_SDQS1
+
+	mww 0x53fa8718 0x00300000	 ;# GRP_B0DS
+	mww 0x53fa8584 0x00300000	 ;# DRAM_DQM0
+	mww 0x53fa857c 0x00300040	 ;# DRAM_SDQS0
+
+	mww 0x53fa8578 0x00300000	 ;# DRAM_SDCLK_0
+	mww 0x53fa8570 0x00300000	 ;# DRAM_SDCLK_1
+
+	mww 0x53fa8574 0x00300000	 ;# DRAM_CAS
+	mww 0x53fa8588 0x00300000	 ;# DRAM_RAS
+	mww 0x53fa86f0 0x00300000	 ;# GRP_ADDDS
+	mww 0x53fa8720 0x00300000	 ;# GRP_CTLDS
+
+	mww 0x53fa8564 0x00300040	 ;# DRAM_SDODT1
+	mww 0x53fa8580 0x00300040	 ;# DRAM_SDODT0
+
+	# Initialize DDR2 memory
+	mww 0x63fd9088 0x32383535
+	mww 0x63fd9090 0x40383538
+	mww 0x63fd907c 0x0136014d
+	mww 0x63fd9080 0x01510141
+
+	mww 0x63fd9018 0x00011740
+	mww 0x63fd9000 0xc3190000
+	mww 0x63fd900c 0x555952e3
+	mww 0x63fd9010 0xb68e8b63
+	mww 0x63fd9014 0x01ff00db
+	mww 0x63fd902c 0x000026d2
+	mww 0x63fd9030 0x009f0e21
+	mww 0x63fd9008 0x12273030
+	mww 0x63fd9004 0x0002002d
+	mww 0x63fd901c 0x00008032
+	mww 0x63fd901c 0x00008033
+	mww 0x63fd901c 0x00028031
+	mww 0x63fd901c 0x092080b0
+	mww 0x63fd901c 0x04008040
+	mww 0x63fd901c 0x0000803a
+	mww 0x63fd901c 0x0000803b
+	mww 0x63fd901c 0x00028039
+	mww 0x63fd901c 0x09208138
+	mww 0x63fd901c 0x04008048
+	mww 0x63fd9020 0x00001800
+	mww 0x63fd9040 0x04b80003
+	mww 0x63fd9058 0x00022227
+	mww 0x63fd901c 0x00000000
+#	dap apsel 0
+}
+
+# vim:filetype=tcl
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx53loco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx53loco.cfg
new file mode 100644
index 0000000..fcc2f4d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx53loco.cfg
@@ -0,0 +1,317 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+##################################################################################
+# Author: Wjatscheslaw Stoljarski (Slawa)  #
+# Kiwigrid GmbH                                                                  #
+##################################################################################
+
+# The IMX53LOCO (QSB) board has a single IMX53 chip
+source [find target/imx53.cfg]
+# Helper for common memory read/modify/write procedures
+source [find mem_helper.tcl]
+
+echo "iMX53 Loco board lodaded."
+
+# Set reset type
+#reset_config srst_only
+
+adapter speed 3000
+
+# Slow speed to be sure it will work
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+
+#adapter srst delay 200
+#jtag_ntrst_delay 200
+
+$_TARGETNAME configure -event "reset-assert" {
+	echo "Resetting ...."
+	#cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-init { loco_init }
+
+global AIPS1_BASE_ADDR
+set AIPS1_BASE_ADDR     0x53F00000
+global AIPS2_BASE_ADDR
+set AIPS2_BASE_ADDR     0x63F00000
+
+proc loco_init { } {
+	echo "Reset-init..."
+	; # halt the CPU
+	halt
+
+	echo "HW version [format %x [mrw 0x48]]"
+
+	dap apsel 1
+	DCD
+
+	; # ARM errata ID #468414
+	set tR [arm mrc 15 0 1 0 1]
+	arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]	; # enable L1NEON bit
+
+	init_l2cc
+	init_aips
+	init_clock
+
+	dap apsel 0
+
+	; # Force ARM state
+	; #reg cpsr 0x000001D3
+	arm core_state arm
+
+	jtag_rclk 3000
+#	adapter speed 3000
+}
+
+
+# L2CC Cache setup/invalidation/disable
+proc init_l2cc { } {
+	; #/* explicitly disable L2 cache */
+	; #mrc 15, 0, r0, c1, c0, 1
+	set tR [arm mrc 15 0 1 0 1]
+	; #bic r0, r0, #0x2
+	; #mcr 15, 0, r0, c1, c0, 1
+	arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
+
+	; #/* reconfigure L2 cache aux control reg */
+	; #mov r0, #0xC0                   /* tag RAM */
+	; #add r0, r0, #0x4                /* data RAM */
+	; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+	; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+	; #orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	; #mcr 15, 1, r0, c9, c0, 2
+	arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
+}
+
+
+# AIPS setup - Only setup MPROTx registers.
+# The PACR default values are good.
+proc init_aips { } {
+	; # Set all MPROTx to be non-bufferable, trusted for R/W,
+	; # not forced to user-mode.
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set VAL			0x77777777
+
+#	dap apsel 1
+	mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
+#	dap apsel 0
+}
+
+
+proc init_clock { } {
+	global AIPS1_BASE_ADDR
+	global AIPS2_BASE_ADDR
+	set CCM_BASE_ADDR	[expr {$AIPS1_BASE_ADDR + 0x000D4000}]
+	set CLKCTL_CCSR         0x0C
+	set CLKCTL_CBCDR	0x14
+	set CLKCTL_CBCMR        0x18
+	set PLL1_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00080000}]
+	set PLL2_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00084000}]
+	set PLL3_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00088000}]
+	set PLL4_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x0008C000}]
+	set CLKCTL_CSCMR1	0x1C
+	set CLKCTL_CDHIPR	0x48
+	set PLATFORM_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x000A0000}]
+	set CLKCTL_CSCDR1	0x24
+	set CLKCTL_CCDR		0x04
+
+	; # Switch ARM to step clock
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
+
+	return
+	echo "not returned"
+	setup_pll $PLL1_BASE_ADDR 800
+	setup_pll $PLL3_BASE_ADDR 400
+
+	; # Switch peripheral to PLL3
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL2_BASE_ADDR 400
+
+	; # Switch peripheral to PLL2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
+
+	; # change uart clk parent to pll2
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
+
+	; # make sure change is effective
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
+
+	setup_pll $PLL3_BASE_ADDR 216
+
+	setup_pll $PLL4_BASE_ADDR 455
+
+	; # Set the platform clock dividers
+	mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
+
+	mww [expr {$CCM_BASE_ADDR + 0x10}] 0
+
+	; # Switch ARM back to PLL 1.
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
+
+	; # make uart div=6
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
+
+	; # Restore the default values in the Gate registers
+	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
+
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
+
+	; # for cko - for ARM div by 8
+	mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
+}
+
+
+proc setup_pll { PLL_ADDR CLK } {
+	set PLL_DP_CTL		0x00
+	set PLL_DP_CONFIG   	0x04
+	set PLL_DP_OP		0x08
+	set PLL_DP_HFS_OP	0x1C
+	set PLL_DP_MFD		0x0C
+	set PLL_DP_HFS_MFD	0x20
+	set PLL_DP_MFN		0x10
+	set PLL_DP_HFS_MFN	0x24
+
+	if {$CLK == 1000} {
+		set DP_OP	[expr {(10 << 4) + ((1 - 1) << 0)}]
+		set DP_MFD	[expr {12 - 1}]
+		set DP_MFN	5
+	} elseif {$CLK == 850} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	41
+	} elseif {$CLK == 800} {
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 700} {
+		set DP_OP	[expr {(7 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	7
+	} elseif {$CLK == 600} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 665} {
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {96 - 1}]
+		set DP_MFN	89
+	} elseif {$CLK == 532} {
+		set DP_OP	[expr {(5 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
+		set DP_MFN	13
+	} elseif {$CLK == 455} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
+		set DP_MFN	71
+	} elseif {$CLK == 400} {
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
+		set DP_MFN	1
+	} elseif {$CLK == 216} {
+		set DP_OP	[expr {(6 << 4) + ((3 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
+		set DP_MFN	3
+	} else {
+		error "Error (setup_dll): clock not found!"
+	}
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
+
+	mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
+
+	mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
+
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
+}
+
+
+proc CPU_2_BE_32 { L } {
+	return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
+}
+
+
+# Device Configuration Data
+proc DCD { } {
+#	dap apsel 1
+	mww 0x53FA8554 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+	mww 0x53FA8558 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
+	mww 0x53FA8560 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+	mww 0x53FA8564 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT
+	mww 0x53FA8568 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
+	mww 0x53FA8570 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
+	mww 0x53FA8574 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+	mww 0x53FA8578 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
+	mww 0x53FA857c 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
+	mww 0x53FA8580 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+	mww 0x53FA8584 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+	mww 0x53FA8588 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+	mww 0x53FA8590 0x00300040	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
+	mww 0x53FA8594 0x00300000	;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+	mww 0x53FA86f0 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_ADDDS
+	mww 0x53FA86f4 0x00000000	;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+	mww 0x53FA86fc 0x00000000	;# IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+	mww 0x53FA8714 0x00000000	;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode
+	mww 0x53FA8718 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_B0DS
+	mww 0x53FA871c 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_B1DS
+	mww 0x53FA8720 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_CTLDS
+	mww 0x53FA8724 0x04000000	;# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0=
+	mww 0x53FA8728 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_B2DS
+	mww 0x53FA872c 0x00300000	;# IOMUXC_SW_PAD_CTL_GRP_B3DS
+
+	# Initialize DDR2 memory
+	mww 0x63FD9088 0x35343535	;# ESDCTL_RDDLCTL
+	mww 0x63FD9090 0x4d444c44	;# ESDCTL_WRDLCTL
+	mww 0x63FD907c 0x01370138	;# ESDCTL_DGCTRL0
+	mww 0x63FD9080 0x013b013c	;# ESDCTL_DGCTRL1
+	mww 0x63FD9018 0x00011740	;# ESDCTL_ESDMISC
+	mww 0x63FD9000 0xc3190000	;# ESDCTL_ESDCTL
+	mww 0x63FD900c 0x9f5152e3	;# ESDCTL_ESDCFG0
+	mww 0x63FD9010 0xb68e8a63	;# ESDCTL_ESDCFG1
+	mww 0x63FD9014 0x01ff00db	;# ESDCTL_ESDCFG2
+	mww 0x63FD902c 0x000026d2	;# ESDCTL_ESDRWD
+	mww 0x63FD9030 0x009f0e21	;# ESDCTL_ESDOR
+	mww 0x63FD9008 0x12273030	;# ESDCTL_ESDOTC
+	mww 0x63FD9004 0x0002002d	;# ESDCTL_ESDPDC
+	mww 0x63FD901c 0x00008032	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x00008033	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x00028031	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x052080b0	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x04008040	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x0000803a	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x0000803b	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x00028039	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x05208138	;# ESDCTL_ESDSCR
+	mww 0x63FD901c 0x04008048	;# ESDCTL_ESDSCR
+	mww 0x63FD9020 0x00005800	;# ESDCTL_ESDREF
+	mww 0x63FD9040 0x04b80003	;# ESDCTL_ZQHWCTRL
+	mww 0x63FD9058 0x00022227	;# ESDCTL_ODTCTRL
+	mww 0x63FD901C 0x00000000	;# ESDCTL_ESDSCR
+#	dap apsel 0
+}
+
+# vim:filetype=tcl
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx8mp-evk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx8mp-evk.cfg
new file mode 100644
index 0000000..898f3b7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/imx8mp-evk.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for NXP MC-IMX8MP-EVK
+#
+# Board includes FTDI-based JTAG adapter: interface/ftdi/imx8mp-evk.cfg
+#
+
+transport select jtag
+adapter speed 1000
+reset_config srst_only
+adapter srst delay 100
+
+set CHIPNAME imx8mp
+set CHIPCORES 4
+
+source [find target/imx8m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/insignal_arndale.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/insignal_arndale.cfg
new file mode 100644
index 0000000..c7c28b3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/insignal_arndale.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# InSignal Arndale board
+#
+
+source [find target/exynos5250.cfg]
+
+# Experimentally determined highest working speed
+adapter speed 200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kasli.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kasli.cfg
new file mode 100644
index 0000000..d85e1ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kasli.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter driver ftdi
+ftdi device_desc "Quad RS232-HS"
+ftdi vid_pid 0x0403 0x6011
+ftdi channel 0
+ftdi layout_init 0x0008 0x000b
+# adapter usb location 1:8
+
+reset_config none
+transport select jtag
+adapter speed 25000
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+source [find fpga/xilinx-xadc.cfg]
+source [find fpga/xilinx-dna.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kc100.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kc100.cfg
new file mode 100644
index 0000000..2fd6965
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kc100.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Knovative KC-100 cable modem
+
+# TNETC4401PYP, 208-QFP U3
+source [find target/tnetc4401.cfg]
+
+# 14-pin EJTAG on JP1. Standard pinout, 1-3-5-7-9-11 = nTRST-TDI-TDO-TMS-TCK-nSRST. Use 2 for GND.
+# Was initially disabled in hardware; had to add a solder bridge reenabling R124, R125 on back.
+reset_config trst_and_srst separate
+
+# 16Mb Intel CFI flash. Note this CPU has an internal ROM at 0x1FC0000 (phys) for cold boot.
+# All that really does is some minimal checks before jumping to external flash at 0x00000000 phys.
+# That is remapped to 0xB0000000 uncached, 0x90000000 cached.
+flash bank intel cfi 0xB0000000 0x200000 2 2 $_TARGETNAME
+
+# Perform this after a clean reboot, halt, and reset init (which should also leave it halted).
+proc kc100_dump_flash {} {
+	echo "Probing 48 TSOP Intel CFI flash chip (2MB)..."
+	flash probe intel
+	echo "Dumping 2MB flash chip to flashdump.bin.
+	flash read_bank 0 flashdump.bin 0 0x200000
+}
+
+#TODO figure out memory init sequence to be able to dump from cached segment instead
+
+# There is also a serial console on JP2, 3-5-6 = TX-RX-GND. 9600/8/N/1.
+
+# Possibly of note, this modem's ancient ethernet port does not support Auto-MDIX.
+
+# This modem in many ways appears to be essentially a clone of the SB5120. See usbjtag.com.
+# The firmware/OS is also susceptible to many of the same procedures in "Hacking the Cable Modem"
+# by DerEngel (Ryan Harris), available from No Starch Press.
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kc705.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kc705.cfg
new file mode 100644
index 0000000..fad9fff
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kc705.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html
+
+source [find interface/ftdi/digilent-hs1.cfg]
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+source [find fpga/xilinx-xadc.cfg]
+source [find fpga/xilinx-dna.cfg]
+adapter speed 25000
+
+# example command to write bitstream, soft-cpu bios and runtime:
+# openocd -f board/kc705.cfg -c "init;\
+# jtagspi_init 0 bscan_spi_xc7k325t.bit;\
+# jtagspi_program bitstream-kc705.bin 0;\
+# jtagspi_program bios.bin 0xaf0000;\
+# jtagspi_program runtime.fbi 0xb00000;\
+# xc7_program xc7.tap;\
+# exit"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kcu105.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kcu105.cfg
new file mode 100644
index 0000000..1510a06
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kcu105.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx ultrascale
+# http://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
+
+source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
+
+set CHIP XCKU040
+source [find cpld/xilinx-xcu.cfg]
+
+source [find cpld/jtagspi.cfg]
+
+adapter speed 25000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/keil_mcb1700.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/keil_mcb1700.cfg
new file mode 100644
index 0000000..6efbd63
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/keil_mcb1700.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Keil MCB1700 eval board
+#
+# http://www.keil.com/mcb1700/picture.asp
+#
+
+source [find target/lpc17xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/keil_mcb2140.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/keil_mcb2140.cfg
new file mode 100644
index 0000000..bb1d10b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/keil_mcb2140.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Keil MCB2140 eval board
+#
+# http://www.keil.com/mcb2140/picture.asp
+#
+
+source [find target/lpc2148.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kindle2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kindle2.cfg
new file mode 100644
index 0000000..8c032cb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kindle2.cfg
@@ -0,0 +1,183 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Board configuration file for Amazon Kindle Model No. D00701 and D00801
+# AKA Kindle 2nd generation and Kindle DX
+# using a Freescale MCIMX31LDVKN5D i.MX31 processor
+#
+# Pins at J9 40-Pin FFC-A:
+#  1 - GND
+# 16 - TRSTB
+# 17 - TDI
+# 18 - TMS
+# 19 - TCK
+# 20 - RTCK
+# 21 - TDO
+# 22 - DE
+# 25 - BOOT_MODE4
+# 27 - BOOT_MODE2
+
+source [find target/imx31.cfg]
+source [find target/imx.cfg]
+
+$_TARGETNAME configure -event reset-init { kindle2_init }
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
+
+# 8MiB NOR Flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xa0000000 0x800000 2 2 $_TARGETNAME
+
+# 16kiB internal SRAM
+$_TARGETNAME configure -work-area-phys 0x1fffc000 \
+	-work-area-size 0x4000 -work-area-backup 0
+
+# FIXME: currently SRST is not wired to the system
+reset_config trst_only
+jtag_ntrst_assert_width 10
+jtag_ntrst_delay 30
+
+# this is broken but enabled by default
+arm11 memwrite burst disable
+
+adapter speed 1000
+ftdi tdo_sample_edge falling
+
+proc kindle2_init {} {
+	imx3x_reset
+	kindle2_clock_setup
+	disable_mmu_and_cache
+	kindle2_misc_init
+	kindle2_sdram_init
+	arm core_state arm
+}
+
+proc kindle2_clock_setup {} {
+	# CCMR: clock from FPM/CKIL
+	mww 0x53f80000  0x074b0b7b
+	# IPU_CONF
+	mww 0x53fc0000  0x040
+	# 398MHz
+	mww 0x53f80004 0xff871650
+	mww 0x53f80010 0x00331c23
+}
+
+proc kindle2_misc_init { } {
+	# AIPS1
+	mww 0x43f00040 0x0
+	mww 0x43f00044 0x0
+	mww 0x43f00048 0x0
+	mww 0x43f0004c 0x0
+	mww 0x43f00050 0x0
+	mww 0x43f00000 0x77777777
+	mww 0x43f00004 0x77777777
+
+	# AIPS2
+	mww 0x53f00040 0x0
+	mww 0x53f00044 0x0
+	mww 0x53f00048 0x0
+	mww 0x53f0004c 0x0
+	mww 0x53f00050 0x0
+	mww 0x53f00000 0x77777777
+	mww 0x53f00004 0x77777777
+
+	# Start 16 bit NorFlash Initialization on CS0
+	mww 0xb8002000 0x0000cc03
+	mww 0xb8002004 0xa0330d01
+	mww 0xb8002008 0x00220800
+}
+
+proc disable_mmu_and_cache {} {
+	# Mode Supervisor, disable FIQ, IRQ and imprecise data aborts
+	reg cpsr 0x1d3
+
+	# flush entire BTAC
+	arm mcr 15 0 7 5 6 0
+	# invalidate instruction and data cache
+	# MCR CP15, 0, R1, C7, C7, 0
+	arm mcr 15 0 7 7 0
+
+	# clean and invalidate cache
+	arm mcr 15 0 7 15 0
+
+	# disable MMU and caches
+	arm mcr 15 0 1 0 0 0
+
+	arm mcr 15 0 15 2 4 0
+
+	# invalidate TLBs
+	arm mcr 15 0 8 7 0 0
+
+	# Drain the write buffer
+	arm mcr 15 0 7 10 4 0
+
+	# start from AIPS 2GB region
+	arm mcr 15 0 15 2 4 0x40000015
+}
+
+proc kindle2_sdram_init {} {
+	#--------------------------------------------
+	# Samsung K4X1G323PC-8GC3 32Mx32 Mobile DDR SDRAM
+	#--------------------------------------------
+	# SDCLK
+	mww 0x43fac26c 0
+
+	# CAS
+	mww 0x43fac270 0
+
+	# RAS
+	mww 0x43fac274 0
+
+	# CS2 (CSD0)
+	mww 0x43fac27c 0x1000
+
+	# DQM3
+	mww 0x43fac284 0
+
+	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2dc)
+	mww 0x43fac288 0
+	mww 0x43fac28c 0
+	mww 0x43fac290 0
+	mww 0x43fac294 0
+	mww 0x43fac298 0
+	mww 0x43fac29c 0
+	mww 0x43fac2a0 0
+	mww 0x43fac2a4 0
+	mww 0x43fac2a8 0
+	mww 0x43fac2ac 0
+	mww 0x43fac2b0 0
+	mww 0x43fac2b4 0
+	mww 0x43fac2b8 0
+	mww 0x43fac2bc 0
+	mww 0x43fac2c0 0
+	mww 0x43fac2c4 0
+	mww 0x43fac2c8 0
+	mww 0x43fac2cc 0
+	mww 0x43fac2d0 0
+	mww 0x43fac2d4 0
+	mww 0x43fac2d8 0
+	mww 0x43fac2dc 0
+
+	# ?
+	mww 0xb8002000 0x00006602
+	mww 0xb8002004 0x00000501
+	mww 0xb8002008 0x00000000
+
+	# LPDDR1 Initialization script
+	mww 0xb8001010 0x00000002
+	mww 0xb8001010 0x00000004
+	# ESDCFG0: set timing parameters
+	mww 0xb8001004 0x007fff7f
+	# ESDCTL0: select Prechare-All mode
+	mww 0xb8001000 0x92100000
+	mww 0x80000f00 0x12344321
+	# ESDCTL0: Auto Refresh
+	mww 0xb8001000 0xa2100000
+	mww 0x80000000 0x12344321
+	mww 0x80000000 0x12344321
+	# ESDCTL0: Load Mode Register
+	mww 0xb8001000 0xb2100000
+	mwb 0x80000033 0xda
+	mwb 0x81000000 0xff
+	# ESDCTL0: enable Auto-Refresh
+	mww 0xb8001000 0x82226080
+	mww 0x80000000 0xdeadbeef
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kontron_sl28.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kontron_sl28.cfg
new file mode 100644
index 0000000..9816f38
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kontron_sl28.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Kontron SMARC-sAL28
+
+transport select jtag
+reset_config srst_only srst_nogate
+
+jtag newtap unknown0 tap -irlen 12
+
+set _CPUS 2
+source [find target/ls1028a.cfg]
+
+source [find tcl/cpld/altera-epm240.cfg]
+
+adapter speed 2000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kwikstik.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kwikstik.cfg
new file mode 100644
index 0000000..ade0c91
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/kwikstik.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale KwikStik development board
+#
+
+#
+# JLINK interface is onboard
+#
+source [find interface/jlink.cfg]
+
+source [find target/k40.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/la_fonera-fon2200.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/la_fonera-fon2200.cfg
new file mode 100644
index 0000000..b0b2966
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/la_fonera-fon2200.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/atheros_ar2315.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lambdaconcept_ecpix-5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lambdaconcept_ecpix-5.cfg
new file mode 100644
index 0000000..19b9c1c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lambdaconcept_ecpix-5.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# LambdaConcept ECPIX-5
+# http://docs.lambdaconcept.com/ecpix-5/
+# Currently there are following board variants:
+# ECPIX-5 45F - LFE5UM5G-45F
+# ECPIX-5 85F - LFE5UM5G-85F
+#
+# This boards have two JTAG interfaces:
+# - CN4, micro USB port connected to FT2232HQ chip:
+#        ADBUS0 TCK
+#        ADBUS1 TDI
+#        ADBUS2 TDO
+#        ADBUS3 TMS
+#        BDBUS0 UART_TXD
+#        BDBUS1 UART_RXD
+#   This interface should be used with following config:
+#        interface/ftdi/lambdaconcept_ecpix-5.cfg
+# - CN3, 6 pin connector
+# See schematics for more details:
+# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF
+#
+# No reset lines are implemented. So it is not possible to remote reset the FPGA
+# by using any of this interfaces
+
+source [find interface/ftdi/lambdaconcept_ecpix-5.cfg]
+source [find fpga/lattice_ecp5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lemaker_hikey.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lemaker_hikey.cfg
new file mode 100644
index 0000000..fc04435
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lemaker_hikey.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# board configuration for LeMaker Hikey
+#
+
+# board does not feature anything but JTAG
+transport select jtag
+
+# SRST-only reset configuration
+reset_config srst_only srst_push_pull
+
+source [find target/hi6220.cfg]
+
+# make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# examine remaining cores
+	foreach _core $args {
+		${_TARGETNAME}$_core arp_examine
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/linksys-wag200g.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/linksys-wag200g.cfg
new file mode 100644
index 0000000..26900a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/linksys-wag200g.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Linksys WAG200G Router
+#
+# The stock firmware Flash layout is organized as follow:
+#
+#   Start       End         Device
+#   0x90000000  0x90020000  /dev/mtdblock/2
+#   0x90020000  0x900d0000  /dev/mtdblock/1
+#   0x900d0000  0x903a0000  /dev/mtdblock/0
+#   0x903a0000  0x903e0000  /dev/mtdblock/5
+#   0x903e0000  0x903f0000  /dev/mtdblock/3
+#   0x903f0000  0x90400000  /dev/mtdblock/4
+
+set partition_list {
+    adam2	{ "Adam2 bootloader"		0x90000000 0x00020000 }
+    kernel	{ "Kernel"			0x90020000 0x000b0000 }
+    rootfs	{ "Root FS"			0x900d0000 0x002d0000 }
+    lang	{ "Minix language part"		0x903a0000 0x00040000 }
+    config	{ "Firmware config"		0x903e0000 0x00010000 }
+    adam2env	{ "Adam2 environment"		0x903f0000 0x00010000 }
+}
+
+source [find target/ti-ar7.cfg]
+
+# External 4MB MXIC 29LV320MBTC Flash (Manufacturer/Device: 0x00c2 0x227e)
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/linksys-wrt54gl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/linksys-wrt54gl.cfg
new file mode 100644
index 0000000..58dfec3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/linksys-wrt54gl.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Linksys WRT54GL v1.1
+#
+
+source [find target/bcm5352e.cfg]
+
+set partition_list {
+    CFE		{ Bootloader			0x1c000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0x1c040000 0x003b0000 }
+    nvram	{ "Config space"		0x1c3f0000 0x00010000 }
+}
+
+# External 4MB NOR Flash (Intel TE28F320C3BD90 or similar)
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x1c000000 0x00400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/linksys_nslu2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/linksys_nslu2.cfg
new file mode 100644
index 0000000..536f97e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/linksys_nslu2.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for the LinkSys (CISCO) NSLU2 board
+# It is an Intel XSCALE IXP420 CPU.
+
+source [find target/ixp42x.cfg]
+# The _TARGETNAME is set by the above.
+
+$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lisa-l.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lisa-l.cfg
new file mode 100644
index 0000000..1607fb8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lisa-l.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# the Lost Illusions Serendipitous Autopilot
+# http://paparazzi.enac.fr/wiki/Lisa
+
+# Work-area size (RAM size) = 20kB for STM32F103RB device
+set WORKAREASIZE 0x5000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/logicpd_imx27.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/logicpd_imx27.cfg
new file mode 100644
index 0000000..8365d4f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/logicpd_imx27.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The LogicPD Eval IMX27 eval board has a single IMX27 chip
+source [find target/imx27.cfg]
+
+# The Logic PD board has a NOR flash on CS0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
+
+#
+# FIX ME, Add support to
+#
+# (A) hard reset the board.
+# (B) Initialize the SDRAM on the board
+#
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lpc1850_spifi_generic.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lpc1850_spifi_generic.cfg
new file mode 100644
index 0000000..167b624
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lpc1850_spifi_generic.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Generic LPC1850 board w/ SPIFI flash.
+# This config file is intended as an example of how to
+# use the lpcspifi flash driver, but it should be functional
+# for most LPC1850 boards utilizing SPIFI flash.
+
+set CHIPNAME lpc1850
+
+source [find target/lpc1850.cfg]
+
+#A large working area greatly reduces flash write times
+set _WORKAREASIZE 0x4000
+
+$_CHIPNAME.m3 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
+
+#Configure the flash bank; 0x14000000 is the base address for
+#lpc43xx/lpc18xx family micros.
+flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m3
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lpc4350_spifi_generic.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lpc4350_spifi_generic.cfg
new file mode 100644
index 0000000..8a017ec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lpc4350_spifi_generic.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Generic LPC4350 board w/ SPIFI flash.
+# This config file is intended as an example of how to
+# use the lpcspifi flash driver, but it should be functional
+# for most LPC4350 boards utilizing SPIFI flash.
+
+set CHIPNAME lpc4350
+
+source [find target/lpc4350.cfg]
+
+#Configure the flash bank; 0x14000000 is the base address for
+#lpc43xx/lpc18xx family micros.
+flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lubbock.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lubbock.cfg
new file mode 100644
index 0000000..e4de385
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/lubbock.cfg
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel "Lubbock" Development Board with PXA255 (dbpxa255)
+#  Obsolete; this was Intel's original PXA255 development system
+#  Board also had CPU cards for SA1100, PXA210, PXA250, and more.
+
+source [find target/pxa255.cfg]
+
+adapter srst delay 250
+jtag_ntrst_delay 250
+
+# NOTE: until after pinmux and such are set up, only CS0 is
+# available ... not 2nd bank of CFI, or FPGA, SRAM, ENET, etc.
+
+# CS0, CS1 -- two banks of CFI flash, 32 MBytes each
+# each bank is 32-bits wide, two 16-bit chips in parallel
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
+
+# CS2 low -- FPGA registers
+# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
+$_TARGETNAME configure -work-area-phys 0x0a0f0000
+
+$_TARGETNAME configure -event reset-assert-pre \
+	"$_TARGETNAME configure -work-area-size 0"
+
+# Make the hex led display a number, assuming CS2 is set up
+# and all digits have been enabled through the FPGA.
+proc hexled {u32} {
+	mww 0x08000010 $u32
+}
+
+# CS3 -- Ethernet
+# CS4 -- SA1111
+# CS5 -- PCMCIA
+
+# NOTE:  system console normally uses the FF UART connector
+
+proc lubbock_init {target} {
+
+	echo "Initialize PXA255 Lubbock board"
+
+	# (1) pinmux
+
+	# GPSR0..GPSR2
+	mww 0x40e00018 0x00008000
+	mww 0x40e0001c 0x00FC0382
+	mww 0x40e00020 0x0001FFFF
+	# GPDR0..GPDR2
+	mww 0x40e0000c 0x0060A800
+	mww 0x40e00010 0x00FF0382
+	mww 0x40e00014 0x0001C000
+	# GAFR0_[LU]..GAFR2_[LU]
+	mww 0x40e00054 0x98400000
+	mww 0x40e00058 0x00002950
+	mww 0x40e0005c 0x000A9558
+	mww 0x40e00060 0x0005AAAA
+	mww 0x40e00064 0xA0000000
+	mww 0x40e00068 0x00000002
+
+	# write PSSR, enable GPIOs
+	mww 0x40f00000 0x00000020
+
+	# write LED ctrl register ... ones disable
+	# high byte, 8 hex leds; low byte, 8 discretes
+	mwh 0x08000040 0xf0ff
+
+	hexled 0x0000
+
+	# (2) Address space setup
+
+	# MSC0/MSC1/MSC2
+	mww 0x48000008 0x23f223f2
+	mww 0x4800000c 0x3ff1a441
+	mww 0x48000010 0x7ff97ff1
+	# pcmcia/cf
+	mww 0x48000014 0x00000000
+	mww 0x48000028 0x00010504
+	mww 0x4800002c 0x00010504
+	mww 0x48000030 0x00010504
+	mww 0x48000034 0x00010504
+	mww 0x48000038 0x00004715
+	mww 0x4800003c 0x00004715
+
+	hexled 0x1111
+
+	# (3) SDRAM setup
+	# REVISIT this looks dubious ... no refresh cycles
+	mww 0x48000004 0x03CA4018
+	mww 0x48000004 0x004B4018
+	mww 0x48000004 0x000B4018
+	mww 0x48000004 0x000BC018
+	mww 0x48000000 0x00001AC8
+	mww 0x48000000 0x00001AC9
+
+	mww 0x48000040 0x00000000
+
+	# FIXME -- setup:
+	#  CLOCKS (and faster JTAG)
+	#  enable icache
+
+	# FIXME SRAM isn't working
+	# $target configure -work-area-size 0x10000
+
+	hexled 0x2222
+
+	flash probe 0
+	flash probe 1
+
+	hexled 0xcafe
+}
+$_TARGETNAME configure -event reset-init "lubbock_init $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/marsohod.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/marsohod.cfg
new file mode 100644
index 0000000..2be8391
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/marsohod.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marsohod CPLD Development and Education board
+#
+# http://marsohod.org/howtostart/plata
+#
+
+# Recommended MBFTDI programmer
+source [find interface/ftdi/mbftdi.cfg]
+adapter speed 2000
+transport select jtag
+
+# Altera MAXII EPM240T100C CPLD
+source [find cpld/altera-epm240.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/marsohod2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/marsohod2.cfg
new file mode 100644
index 0000000..9575100
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/marsohod2.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marsohod2 FPGA Development and Education board
+#
+# http://www.marsohod.org/prodmarsohod2
+#
+
+# Built-in MBFTDI programmer
+source [find interface/ftdi/mbftdi.cfg]
+adapter speed 2000
+transport select jtag
+
+# Cyclone III EP3C10E144 FPGA
+source [find fpga/altera-ep3c10.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/marsohod3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/marsohod3.cfg
new file mode 100644
index 0000000..b4f2d30
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/marsohod3.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marsohod3 FPGA Development and Education board
+#
+# http://www.marsohod.org/plata-marsokhod3
+#
+
+# Built-in MBFTDI programmer
+source [find interface/ftdi/mbftdi.cfg]
+adapter speed 2000
+transport select jtag
+
+# MAX10 10M50SAE144C8GES FPGA
+source [find fpga/altera-10m50.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mbed-lpc11u24.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mbed-lpc11u24.cfg
new file mode 100644
index 0000000..9f5be88
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mbed-lpc11u24.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an mbed eval board with a single NXP LPC11U24 chip.
+# http://mbed.org/handbook/mbed-NXP-LPC11U24
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# NXP LPC11U24 Cortex-M0 with 32kB Flash and 8kB SRAM
+set WORKAREASIZE 0x2000
+
+source [find target/lpc11xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mbed-lpc1768.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mbed-lpc1768.cfg
new file mode 100644
index 0000000..62b0911
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mbed-lpc1768.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an mbed eval board with a single NXP LPC1768 chip.
+# http://mbed.org/handbook/mbed-NXP-LPC1768
+#
+
+source [find interface/cmsis-dap.cfg]
+
+source [find target/lpc17xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mcb1700.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mcb1700.cfg
new file mode 100644
index 0000000..8ab6e88
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mcb1700.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Keil MCB1700 PCB with 1768
+#
+# Reset init script sets it to 100MHz
+set CCLK 100000
+
+source [find target/lpc17xx.cfg]
+
+global MCB1700_CCLK
+set MCB1700_CCLK $CCLK
+
+$_TARGETNAME configure -event reset-start {
+	# Start *real slow* as we do not know the
+    # state the boot rom left the clock in
+	adapter speed 10
+}
+
+# Set up 100MHz clock to CPU
+$_TARGETNAME configure -event reset-init {
+    # PLL0CON: Disable PLL
+	mww 0x400FC080 0x00000000
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+    # CCLK=PLL/4 (=100 MHz)
+	mww 0x400FC104 0x00000003
+    # CLKSRCSEL: Clock source = internal RC oscillator
+	mww 0x400FC10C 0x00000000
+
+    # PLL0CFG: M=50,N=1 -> PLL=400 MHz
+	mww 0x400FC084 0x00000031
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+	# PLL0CON: Enable PLL
+	mww 0x400FC080 0x00000001
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+	sleep 50
+
+    # PLL0CON: Connect PLL
+	mww 0x400FC080 0x00000003
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+	# Dividing CPU clock by 8 should be pretty conservative
+	#
+	#
+	global MCB1700_CCLK
+	adapter speed [expr {$MCB1700_CCLK / 8}]
+
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+	# Bit Symbol Value Description Reset
+	# value
+	# 0 MAP Memory map control. 0
+	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+	# 1 User mode. The on-chip Flash memory is mapped to address 0.
+	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+	#
+	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+
+	mww 0x400FC040 0x01
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_explorer16.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_explorer16.cfg
new file mode 100644
index 0000000..6b528d6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_explorer16.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Microchip Explorer 16 with PIC32MX360F512L PIM module.
+# http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en024858
+
+# TAPID for PIC32MX360F512L
+set CPUTAPID 0x30938053
+
+# use 32k working area
+set WORKAREASIZE 32768
+
+source [find target/pic32mx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_sama5d27_som1_kit1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_sama5d27_som1_kit1.cfg
new file mode 100644
index 0000000..8e92040
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_sama5d27_som1_kit1.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip SAMA5D27-SOM1-EK1
+# https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMA5D27-SOM1-EK1
+# This board provide two jtag interfaces:
+# J11 - 10 pin interface
+# J10 - USB interface connected to the J-Link-OB.
+#       This functionality is implemented with an ATSAM3U4C microcontroller and
+#       provides JTAG functions and a bridge USB/Serial debug port (CDC).
+#
+# Jumper J7 disables the J-Link-OB-ATSAM3U4C JTAG functionality.
+# - Jumper J7 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional.
+# - Jumper J7 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG
+#   controller can be used through the 10-pin JTAG port J11.
+
+source [find interface/jlink.cfg]
+reset_config srst_only
+
+source [find target/at91sama5d2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_same51_curiosity_nano.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_same51_curiosity_nano.cfg
new file mode 100644
index 0000000..32e2885
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_same51_curiosity_nano.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip SAME51 Curiosity Nano evaluation kit.
+#
+# https://www.microchip.com/en-us/development-tool/EV76S68A
+#
+
+source [find interface/cmsis-dap.cfg]
+
+set CHIPNAME same51
+
+source [find target/atsame5x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_same54_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_same54_xplained_pro.cfg
new file mode 100644
index 0000000..3588165
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_same54_xplained_pro.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Microchip (former Atmel) SAM E54 Xplained Pro evaluation kit.
+# http://www.microchip.com/developmenttools/productdetails.aspx?partno=atsame54-xpro
+#
+
+source [find interface/cmsis-dap.cfg]
+
+set CHIPNAME same54
+
+source [find target/atsame5x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_saml11_xplained_pro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_saml11_xplained_pro.cfg
new file mode 100644
index 0000000..c2fcd65
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/microchip_saml11_xplained_pro.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Microchip (formerly Atmel) SAM L11 Xplained Pro Evaluation Kit.
+# https://www.microchip.com/DevelopmentTools/ProductDetails/dm320205
+#
+
+source [find interface/cmsis-dap.cfg]
+adapter speed 1000
+
+set CHIPNAME saml11
+source [find target/atsaml1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mini2440.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mini2440.cfg
new file mode 100644
index 0000000..5642cb1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mini2440.cfg
@@ -0,0 +1,321 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#-------------------------------------------------------------------------
+# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
+# NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
+# 64 MB NAND (Samsung K9D1208V0M)
+# B Findlay  08/09
+#
+#   ----------- Important notes to help you on your way ----------
+# README:
+#     NOR/NAND Boot Switch - I have not read the vivi source, but from
+#     what I could tell from reading the registers it appears that vivi
+#     loads itself into DRAM and then flips NFCONT (0x4E000004) bits
+#     Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
+#     FLASH at the bottom 64MB of memory. This essentially takes the
+#     NOR Flash out of the circuit so you can't trash it.
+#
+#     I adapted the samsung_s3c2440.cfg file which is why I did not
+#     include "source [find target/samsung_s3c2440.cfg]".  I believe
+#     the -work-area-phys 0x200000 is incorrect, but also had to pad
+#     some additional resets.  I didn't modify it as if it is working
+#     for someone, the work-area-phys is not used by most.
+#
+#     JTAG ADAPTER SPECIFIC
+#     IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
+#     FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
+#     This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
+#     necessary to FORCE setting the clock. Normally this should be configured
+#     in the openocd.cfg file, but was placed here as it can be a tough
+#     problem to figure out.  THIS MAY NOT FIX YOUR PROBLEM.. I modified
+#     the openOCD driver jlink.c and posted it here. It may eventually end
+#     up changed in openOCD, but its a hack in the driver and really should
+#     be in the jtag layer (core.c me thinks), but haven't done it yet. My
+#     hack for jlink.c may be found here.
+#
+#     http://forum.sparkfun.com/viewtopic.php?t=16763&sid=946e65abdd3bab39cc7d90dee33ff135
+#
+#     Note: Also if you have a USB JTAG, you will need the USB library installed
+#     on your system "libusb-dev" or the make of openocd will fail. I *think*
+#     it's apt-get install libusb-dev.  When I made my config I only included
+#     --enable-jlink and --enable-usbdevs
+#
+#     I HAVE NOT Tested this thoroughly, so there could still be problems.
+#     But it should get you way ahead of the game from where I started.
+#     If you find problems (and fixes) please post them to
+#     openocd-development@lists.berlios.de and join the developers and
+#     check in fixes to this and anything else you find.  I do not
+#     provide support, but if you ask really nice and I see anything
+#     obvious I will tell you.. mostly just dig, fix, and submit to openocd.
+#
+#     best!   brfindla@yahoo.com   Nashua, NH USA
+#
+#     Recommended resources:
+#       - first two are the best Mini2440 resources anywhere
+#       - maintained by buserror... thanks guy!
+#
+#       http://bliterness.blogspot.com/
+#       http://code.google.com/p/mini2440/
+#
+#       others....
+#
+#       http://forum.sparkfun.com/viewforum.php?f=18
+#       http://labs.kernelconcepts.de/Publications/Micro24401/
+#       http://www.friendlyarm.net/home
+#       http://www.amontec.com/jtag_pinout.shtml
+#
+#-------------------------------------------------------------------------
+#
+#
+# Your openocd.cfg file should contain:
+# source [find interface/.cfg]
+# source [find board/mini2440.cfg]
+#
+#
+#
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+#-------------------------------------------------------------------------
+# Target configuration for the Samsung 2440 system on chip
+# Tested on a S3C2440 Evaluation board by keesj
+# Processor : ARM920Tid(wb) rev 0 (v4l)
+# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
+#  (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+#-------------------------------------------------------------------------
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME s3c2440
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+  # this defaults to a bigendian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0032409d
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x40000000  -work-area-size 0x4000 -work-area-backup 1
+
+#reset configuration
+adapter srst delay 100
+jtag_ntrst_delay 100
+reset_config trst_and_srst
+
+#-------------------------------------------------------------------------
+# JTAG ADAPTER SPECIFIC
+# IMPORTANT! See README at top of this file.
+#-------------------------------------------------------------------------
+
+    adapter speed 12000
+
+#-------------------------------------------------------------------------
+# GDB Setup
+#-------------------------------------------------------------------------
+
+    gdb breakpoint_override hard
+
+#------------------------------------------------
+# ARM SPECIFIC
+#------------------------------------------------
+
+    targets
+  #  arm7_9 dcc_downloads enable
+  #  arm7_9 fast_memory_access enable
+
+
+    nand device s3c2440 0
+
+    adapter srst delay 100
+    jtag_ntrst_delay 100
+    reset_config trst_and_srst
+    init
+
+    echo " "
+    echo "-------------------------------------------"
+    echo "--- login with - telnet localhost 4444  ---"
+    echo "--- then type help_2440                 ---"
+    echo "-------------------------------------------"
+    echo " "
+
+
+
+#------------------------------------------------
+# Processor Initialialization
+# Note: Processor writes can only occur when
+# the state is in SYSTEM. When you call init_2440
+# one of the first lines will tell you what state
+# you are in. If a linux image is booting
+# when you run this, it will not work
+# a vivi boot loader will run with this just
+# fine. The reg values were obtained by a combination
+# of figuring them out fromt the manual, and looking
+# at post vivi values with the debugger. Don't
+# place too much faith in them, but seem to work.
+#------------------------------------------------
+
+proc init_2440 { } {
+
+    halt
+    s3c2440.cpu curstate
+
+    #-----------------------------------------------
+    # Set Processor Clocks - mini2440 xtal=12mHz
+    # we set main clock for 405mHZ
+    # we set the USB Clock for 48mHz
+    # OM2 OM3 pulled to ground so main clock and
+    # usb clock are off 12mHz xtal
+    #-----------------------------------------------
+
+    mww phys 0x4C000014 0x00000005 ;#  Clock Divider control Reg
+    mww phys 0x4C000000 0xFFFFFFFF ;#  LOCKTIME count register
+    mww phys 0x4C000008 0x00038022 ;#  UPPLCON  USB clock config Reg
+    mww phys 0x4C000004 0x0007F021 ;#  MPPLCON  Proc clock config Reg
+
+    #-----------------------------------------------
+    # Configure Memory controller
+    # BWSCON configures all banks, NAND, NOR, DRAM
+    # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
+    #-----------------------------------------------
+
+    mww phys 0x48000000 0x22111112 ;#  BWSCON - Bank and Bus Width
+    mww phys 0x48000010 0x00001112 ;#  BANKCON4 - ?
+    mww phys 0x4800001c 0x00018009 ;#  BANKCON6 - DRAM
+    mww phys 0x48000020 0x00018009 ;#  BANKCON7 - DRAM
+    mww phys 0x48000024 0x008E04EB ;#  REFRESH  - DRAM
+    mww phys 0x48000028 0x000000B2 ;#  BANKSIZE - DRAM
+    mww phys 0x4800002C 0x00000030 ;#  MRSRB6 - DRAM
+    mww phys 0x48000030 0x00000030 ;#  MRSRB7 - DRAM
+
+    #-----------------------------------------------
+    # Now port configuration for enables for memory
+    # and other stuff.
+    #-----------------------------------------------
+
+    mww phys 0x56000000	0x007FFFFF ;#  GPACON
+
+    mww phys 0x56000010	0x00295559 ;#  GPBCON
+    mww phys 0x56000018	0x000003FF ;#  GPBUP (PULLUP ENABLE)
+    mww phys 0x56000014	0x000007C2 ;#  GPBDAT
+
+    mww phys 0x56000020	0xAAAAA6AA ;#  GPCCON
+    mww phys 0x56000028	0x0000FFFF ;#  GPCUP
+    mww phys 0x56000024	0x00000020 ;#  GPCDAT
+
+    mww phys 0x56000030	0xAAAAAAAA ;#  GPDCON
+    mww phys 0x56000038	0x0000FFFF ;#  GPDUP
+
+    mww phys 0x56000040	0xAAAAAAAA ;#  GPECON
+    mww phys 0x56000048	0x0000FFFF ;#  GPEUP
+
+    mww phys 0x56000050	0x00001555 ;#  GPFCON
+    mww phys 0x56000058	0x0000007F ;#  GPFUP
+    mww phys 0x56000054	0x00000000 ;#  GPFDAT
+
+    mww phys 0x56000060	0x00150114 ;#  GPGCON
+    mww phys 0x56000068	0x0000007F ;#  GPGUP
+
+    mww phys 0x56000070	0x0015AAAA ;#  GPHCON
+    mww phys 0x56000078	0x000003FF ;#  GPGUP
+
+}
+
+
+
+proc flash_config { } {
+
+    #-----------------------------------------
+    # Finish Flash Configuration
+    #-----------------------------------------
+
+    halt
+
+    #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
+    nand probe 0
+    nand list
+}
+
+proc flash_uboot { } {
+
+	# flash the u-Boot binary and reboot into it
+	init_2440
+	flash_config
+	nand erase 0 0x0 0x40000
+	nand write 0 /tftpboot/u-boot-nand512.bin 0 oob_softecc_kw
+	resume
+}
+
+
+proc load_uboot { } {
+        echo " "
+        echo " "
+        echo "----------------------------------------------------------"
+        echo "---- Load U-Boot into RAM and execute it.              ---"
+        echo "---- NOTE: loads, partially runs, and hangs            ---"
+        echo "---- U-Boot is fine, this image runs from vivi.        ---"
+        echo "---- I burned u-boot into NAND so I didn't finish      ---"
+        echo "---- debugging it. I am leaving this here as it is     ---"
+        echo "---- part of the way there if you want to fix it.      ---"
+        echo "----                                                   ---"
+        echo "---- mini2440 U-boot here:                             ---"
+        echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git  ---"
+        echo "---- Also this:                                        ---"
+        echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
+        echo "----------------------------------------------------------"
+
+	init_2440
+	echo "Loading /tftpboot/u-boot-nand512.bin"
+	load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
+	echo "Verifying image...."
+	verify_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
+	echo "jumping to u-boot"
+        #bp 0x33f80068 4 hw
+        reg 0 0
+        reg 1 0
+        reg 2 0
+        reg 3 0
+        reg 4 0x33f80000
+      	resume 0x33f80000
+}
+
+       # this may help a little bit debugging the load_uboot
+proc s {} {
+        step
+        reg
+        arm disassemble 0x33F80068 0x10
+}
+
+proc help_2440 {} {
+    echo " "
+    echo " "
+    echo "-----------------------------------------------------------"
+    echo "---- The following mini2440 funcs are supported        ----"
+    echo "----   init_2440 - initialize clocks, DRAM, IO         ----"
+    echo "----   flash_config - configures nand flash            ----"
+    echo "----   load_uboot - loads uboot into ram               ----"
+    echo "----   flash_uboot - flashes uboot to nand (untested)  ----"
+    echo "----   help_2440 - this help display                   ----"
+    echo "-----------------------------------------------------------"
+    echo " "
+    echo " "
+}
+
+
+#----------------------------------------------------------------------------
+#----------------------------------- END ------------------------------------
+#----------------------------------------------------------------------------
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mini6410.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mini6410.cfg
new file mode 100644
index 0000000..276e718
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/mini6410.cfg
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a tiny6410
+# Processor       : ARM1176
+# Info : JTAG tap: s3c6410.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2)
+# Info : JTAG tap: s3c6410.cpu tap/device found: 0x07b76f0f (mfg: 0x787, part: 0x7b76, ver: 0x0)
+
+source [find target/samsung_s3c6410.cfg]
+
+proc init_6410 {} {
+	halt
+	reg cpsr 0x1D3
+	arm mcr 15 0 15 2 4 0x70000013
+
+	#-----------------------------------------------
+	# Clock and Timer Setting
+	#-----------------------------------------------
+	mww 0x7e004000 0		;# WATCHDOG 	- Disable
+	mww 0x7E00F120 0x0003		;# MEM_SYS_CFG	- CS0:8 bit, Mem1:32bit, CS2=NAND
+	#mww 0x7E00F120 0x1000		;# MEM_SYS_CFG	- CS0:16bit, Mem1:32bit, CS2=SROMC
+	#mww 0x7E00F120 0x1002		;# MEM_SYS_CFG	- CS0:16bit, Mem1:32bit, CS2=OND
+	mww 0x7E00F900 0x805e		;# OTHERS	- Change SYNCMUX[6] to “1”
+	sleep 1000
+	mww 0x7E00F900 0x80de		;# OTHERS	- Assert SYNCREQ&VICSYNCEN to “1”(rb1004modify)
+	sleep 1000			;#		- Others[11:8] to 0xF
+	mww 0x7E00F000 0xffff		;# APLL_LOCK	- APLL LockTime
+	mww 0x7E00F004 0xffff		;# MPLL_LOCK	- MPLL LockTime
+	mww 0x7E00F020 0x1047310	;# CLK_DIV0 	- ARMCLK:HCLK:PCLK = 1:4:16
+	mww 0x7E00F00c 0x81900302	;# APLL_CON 	- A:400, P:3, S:2 => 400MHz
+	mww 0x7E00F010 0x81900303	;# MPLL_CON 	- M:400, P:3, S:3 => 200MHz
+	mww 0x7E00F01c 0x3		;# CLK_SRC 	- APLL,MPLL Clock Select
+
+	#-----------------------------------------------
+	# DRAM initialization
+	#-----------------------------------------------
+	mww 0x7e001004 0x4		;# P1MEMCCMD	- Enter the config state
+	mww 0x7e001010 0x30C		;# P1REFRESH	- Refresh Period register (7800ns), 100MHz
+#	mww 0x7e001010 0x40e		;# P1REFRESH	- Refresh Period register (7800ns), 133MHz
+	mww 0x7e001014 0x6		;# P1CASLAT	- CAS Latency = 3
+	mww 0x7e001018 0x1		;# P1T_DQSS
+	mww 0x7e00101c 0x2		;# P1T_MRD
+	mww 0x7e001020 0x7		;# P1T_RAS	- 45 ns
+	mww 0x7e001024 0xA		;# P1T_RC	- 67.5 ns
+	mww 0x7e001028 0xC		;# P1T_RCD	- 22.5 ns
+	mww 0x7e00102C 0x10B		;# P1T_RFC	- 80 ns
+	mww 0x7e001030 0xC		;# P1T_RP	- 22.5 ns
+	mww 0x7e001034 0x3		;# P1T_RRD	- 15 ns
+	mww 0x7e001038 0x3		;# P1T_WR	- 15 ns
+	mww 0x7e00103C 0x2		;# P1T_WTR
+	mww 0x7e001040 0x2		;# P1T_XP
+	mww 0x7e001044 0x11		;# P1T_XSR	- 120 ns
+	mww 0x7e001048 0x11		;# P1T_ESR
+
+	#-----------------------------------------------
+	# Memory Configuration Registers
+	#-----------------------------------------------
+	mww 0x7e00100C 0x00010012 	;# P1MEMCFG	- 1 CKE, 1Chip, 4burst, Alw, AP[10],ROW/Column bit
+	mww 0x7e00104C 0x0B41 		;# P1MEMCFG2	- Read delay 1 Cycle, mDDR, 32bit, Sync.
+	mww 0x7e001200 0x150F0 		;# CHIP_N_CFG	- 0x150F0 for 256M, 0x150F8 for 128M
+
+	#-----------------------------------------------
+	# Memory Direct Commands
+	#-----------------------------------------------
+	mww 0x7e001008 0xc0000		;# Chip0 Direct Command :NOP5
+	mww 0x7e001008 0x0		;# Chip0 Direct Command :PreCharge al
+	mww 0x7e001008 0x40000		;# Chip0 Direct Command :AutoRefresh
+	mww 0x7e001008 0x40000		;# Chip0 Direct Command :AutoRefresh
+	mww 0x7e001008 0xA0000		;# EMRS, DS:Full, PASR:Full
+	mww 0x7e001008 0x80032		;# MRS, CAS3, BL4
+	mww 0x7e001004 0x0		;# Enable DMC1
+}
+
+proc install_6410_uboot {} {
+	# write U-boot magic number
+	mww 0x50000000 0x24564236
+	mww 0x50000004 0x20764316
+	load_image u-boot_nand-ram256.bin 0x50008000 bin
+	load_image u-boot_nand-ram256.bin 0x57E00000 bin
+
+	#Kick in
+	reg pc 0x57E00000
+	resume
+}
+
+proc init_6410_flash {} {
+	halt
+	nand probe 0
+	nand list
+}
+
+
+adapter speed 1000
+adapter srst delay 100
+jtag_ntrst_delay 100
+reset_config trst_and_srst
+
+gdb breakpoint_override hard
+
+targets
+nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
+
+init
+echo " "
+echo " "
+echo "-------------------------------------------------------------------"
+echo "---- The following mini6410/tiny6410 functions are available:  ----"
+echo "----   init_6410 - initialize clock, timer, DRAM               ----"
+echo "----   init_6410_flash - initializes NAND flash support        ----"
+echo "----   install_6410_uboot - copies u-boot image into RAM and   ----"
+echo "----                        runs it                            ----"
+echo "-------------------------------------------------------------------"
+echo " "
+echo " "
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/minispartan6.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/minispartan6.cfg
new file mode 100644
index 0000000..011cc54
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/minispartan6.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# https://www.scarabhardware.com/minispartan6/
+
+source [find interface/ftdi/minispartan6.cfg]
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
+
+# example command to read the device dna of the FPGA on the board;
+# openocd -f board/minispartan6.cfg -c "init;xc6s_print_dna xc6s.tap;shutdown"
+
+# example command to write bitstream
+# openocd -f board/minispartan6.cfg -c "init;\
+# jtagspi_init 0 bscan_spi_xc6slx??.bit;\
+# jtagspi_program bitstream.bin 0;\
+# xc6s_program xc6s.tap;\
+# shutdown"
+#
+# jtagspi flash procies can be found in the contrib/loaders/flash/fpga/
+# directory, with prebuilt versions available at
+# https://github.com/jordens/bscan_spi_bitstreams
+#
+# For the SLX25 variant, use
+#  - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx25.bit
+# For the SLX9 variant, use
+#  - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx9.bit
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nds32_corvettef1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nds32_corvettef1.cfg
new file mode 100644
index 0000000..7300ce0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nds32_corvettef1.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ADP-Corvette-F1 R1.0
+# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r1/
+# ADP-Corvette-F1 R2.0
+# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r2/
+
+adapter speed     10000
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+reset_config srst_only
+
+source [find target/nds32v5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nds32_xc7.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nds32_xc7.cfg
new file mode 100644
index 0000000..82c00ac
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nds32_xc7.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ADP-XC7K160/410
+# http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/
+
+source [find target/nds32v5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/netgear-dg834v3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/netgear-dg834v3.cfg
new file mode 100644
index 0000000..a993888
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/netgear-dg834v3.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Netgear DG834v3 Router
+# Internal 4Kb RAM (@0x80000000)
+# Flash is located at 0x90000000 (CS0) and RAM is located at 0x94000000 (CS1)
+#
+
+set partition_list {
+    loader	{ "Bootloader (ADAM2)"		0x90000000 0x00020000 }
+    firmware	{ "Kernel+rootfs"		0x90020000 0x003d0000 }
+    config	{ "Bootloader config space"	0x903f0000 0x00010000 }
+}
+
+source [find target/ti-ar7.cfg]
+
+# External 16MB SDRAM - disabled as we use internal sram
+#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000
+
+# External 4MB NOR Flash
+set _FLASHNAME $_CHIPNAME.norflash
+flash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/netgear-wg102.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/netgear-wg102.cfg
new file mode 100644
index 0000000..0a7dad5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/netgear-wg102.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/atheros_ar2313.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event reset-init {
+	mips32 cp0 12 0 0x10400000
+
+	# configure sdram controller
+	mww 0xb8300004 0x0e03
+	sleep 100
+	mww 0xb8300004 0x0e01
+	mww 0xb8300008 0x10
+	sleep 500
+	mww 0xb8300004 0x0e02
+
+	mww 0xb8300000 0x6c0088
+	mww 0xb8300008 0x57e
+	mww 0xb8300004 0x0e00
+	mww 0xb8300004 0xb00
+
+	# configure flash
+	#                 0x00000001 - 0x01 << FLASHCTL_IDCY_S
+	#                 0x000000e0 - 0x07 << FLASHCTL_WST1_S
+	# FLASHCTL_RBLE   0x00000400 - Read byte lane enable
+	#                 0x00003800 - 0x07 << FLASHCTL_WST2_S
+	# FLASHCTL_AC_8M  0x00060000 - Size of flash
+	# FLASHCTL_E      0x00080000 - Flash bank enable (added)
+	# FLASHCTL_WP     0x04000000 - write protect. If used, CFI mode won't work!!
+	# FLASHCTL_MWx16  0x10000000 - 16bit mode. Do not use it!!
+	# FLASHCTL_MWx8   0x00000000 - 8bit mode.
+	mww 0xb8400000 0x000d3ce1
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbe000000 0x00400000 1 1 $_TARGETNAME x16_as_x8
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf51822_mkit.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf51822_mkit.cfg
new file mode 100644
index 0000000..266d710
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf51822_mkit.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic Semiconductor PCA10024 board (aka nRF51822-mKIT)
+#
+
+source [find interface/cmsis-dap.cfg]
+source [find target/nrf51.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf51_dk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf51_dk.cfg
new file mode 100644
index 0000000..7ddae2d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf51_dk.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic Semiconductor NRF51 Development Kit (nRF6824)
+#
+
+source [find interface/jlink.cfg]
+
+transport select swd
+
+source [find target/nrf51.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf52_dk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf52_dk.cfg
new file mode 100644
index 0000000..7366bf9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf52_dk.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic Semiconductor NRF52 Development Kit (nRF52832)
+#
+
+source [find interface/jlink.cfg]
+
+transport select swd
+
+source [find target/nrf52.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf52_ftx232.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf52_ftx232.cfg
new file mode 100644
index 0000000..c3c69a8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nordic_nrf52_ftx232.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# nordic module NRF52 (nRF52832/52840) attached to an adafruit ft232h module
+# or any FT232H/FT2232H/FT4232H based board/module
+#
+
+source [find interface/ftdi/ft232h-module-swd.cfg]
+#source [find interface/ftdi/minimodule-swd.cfg]
+
+transport select swd
+
+source [find target/nrf52.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/novena-internal-fpga.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/novena-internal-fpga.cfg
new file mode 100644
index 0000000..c36938c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/novena-internal-fpga.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Novena open hardware and F/OSS-friendly computing platform
+#
+# Design documentation:
+# http://www.kosagi.com/w/index.php?title=Novena_PVT_Design_Source
+#
+# +-------------+--------------+------+-------+---------+
+# | Pad name    | Schematic    | GPIO | sysfs | JTAG    |
+# +-------------+--------------+------+-------+---------+
+# | DISP0_DAT13 | FPGA_RESET_N | 5-07 |  135  | RESET_N |
+# | DISP0_DAT14 | FPGA_TCK     | 5-08 |  136  | TCK     |
+# | DISP0_DAT15 | FPGA_TDI     | 5-09 |  137  | TDI     |
+# | DISP0_DAT16 | FPGA_TDO     | 5-10 |  138  | TDO     |
+# | DISP0_DAT17 | FPGA_TMS     | 5-11 |  139  | TMS     |
+# +-------------+--------------+------+-------+---------+
+
+adapter driver sysfsgpio
+
+transport select jtag
+
+# TCK TMS TDI TDO
+sysfsgpio jtag_nums 136 139 137 138
+
+source [find cpld/xilinx-xc6s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/npcx_evb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/npcx_evb.cfg
new file mode 100644
index 0000000..4f28bc9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/npcx_evb.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Nuvoton NPCX Evaluation Board
+
+source [find interface/jlink.cfg]
+transport select swd
+
+source [find target/npcx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nuclei-evalsoc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nuclei-evalsoc.cfg
new file mode 100644
index 0000000..2f941c0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nuclei-evalsoc.cfg
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed 1000
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+# change to on to enable cJTAG 2-wire OSCAN1 protocol
+# ocan1_mode -> nscan1_mode in 2023.10 Nuclei OpenOCD release
+# ftdi oscan1_mode off
+ftdi nscan1_mode off
+
+## bindto 0.0.0.0 can be used to cover all available interfaces.
+## Uncomment bindto line to enable remote machine debug
+# bindto 0.0.0.0
+
+# specify adapter serial to select a ftdi chip if you have multiple jtag devices
+# adapter serial "FT6S9RD6"
+
+transport select jtag
+
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
+
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME nuspi 0x20000000 0 0 0 $_TARGETNAME
+
+init
+
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+}
+halt
+
+# We must turn on this because otherwise the IDE version debug cannot download the program into flash
+
+flash protect 0 0 last off
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/numato_mimas_a7.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/numato_mimas_a7.cfg
new file mode 100644
index 0000000..82d6a56
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/numato_mimas_a7.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Numato Mimas A7 - Artix 7 FPGA Board
+#
+# https://numato.com/product/mimas-a7-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet
+#
+# Note: Connect external DC power supply if programming a heavy design onto FPGA.
+#       Programming while powering via USB may lead to programming failure.
+#       Therefore, prefer external power supply.
+
+adapter driver ftdi
+ftdi device_desc "Mimas Artix 7 FPGA Module"
+ftdi vid_pid 0x2a19 0x1009
+
+# channel 0 is for custom purpose by users (like uart, fifo etc)
+# channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers)
+ftdi channel 1
+ftdi tdo_sample_edge falling
+
+
+# FTDI Pin Layout
+#
+# +--------+-------+-------+-------+-------+-------+-------+-------+
+# | DBUS7  | DBUS6 | DBUS5 | DBUS4 | DBUS3 | DBUS2 | DBUS1 | DBUS0 |
+# +--------+-------+-------+-------+-------+-------+-------+-------+
+# | PROG_B | OE_N  |  NC   |  NC   |  TMS  |  TDO  |  TDI  |  TCK  |
+# +--------+-------+-------+-------+-------+-------+-------+-------+
+#
+# OE_N is JTAG buffer output enable signal (active-low)
+# PROG_B is not used, so left as input to FTDI.
+#
+ftdi layout_init 0x0008 0x004b
+reset_config none
+adapter speed 30000
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/numato_opsis.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/numato_opsis.cfg
new file mode 100644
index 0000000..ea07ff3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/numato_opsis.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://opsis.hdmi2usb.tv
+#
+# The Numato Opsis is an FPGA based, open video platform.
+#
+# The board is supported via ixo-usb-jtag project. See the
+# interface/usb-jtag.cfg for more information.
+
+source [find interface/usb-jtag.cfg]
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp/frdm-kv11z-jlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp/frdm-kv11z-jlink.cfg
new file mode 100644
index 0000000..725a37b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp/frdm-kv11z-jlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration file for NXP FRDM-KV11Z development boards.
+#
+# This configuration file is only for FRDM-KV11Z development boards with the
+# SEGGER J-Link OpenSDA firmware, see:
+# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/
+
+source [find interface/jlink.cfg]
+
+# Set working area size to 16 KiB.
+set WORKAREASIZE 0x4000
+
+# Set the chip name.
+set CHIPNAME kv11z
+
+transport select swd
+
+source [find target/kx.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp/frdm-kv31f-jlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp/frdm-kv31f-jlink.cfg
new file mode 100644
index 0000000..e55a01c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp/frdm-kv31f-jlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration file for NXP FRDM-KV31F development boards.
+#
+# This configuration file is only for FRDM-KV31F development boards with the
+# SEGGER J-Link OpenSDA firmware, see:
+# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/
+
+source [find interface/jlink.cfg]
+
+# Set working area size to 32 KiB.
+set WORKAREASIZE 0x8000
+
+# Set the chip name.
+set CHIPNAME kv31f
+
+transport select swd
+
+source [find target/kx.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_frdm-k64f.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_frdm-k64f.cfg
new file mode 100644
index 0000000..1581c95
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_frdm-k64f.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an NXP Freedom eval board with a single MK64FN1M0VLL12 chip.
+# https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# Set working area to 16 KiB
+set WORKAREASIZE 0x4000
+
+set CHIPNAME k64f
+reset_config srst_only
+
+source [find target/kx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_frdm-ls1012a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_frdm-ls1012a.cfg
new file mode 100644
index 0000000..17a50c9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_frdm-ls1012a.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP FRDM-LS1012A (Freedom)
+#
+
+#
+# NXP Kinetis K20
+#
+source [find interface/cmsis-dap.cfg]
+transport select jtag
+
+# Also offers a 10-pin 0.05" CoreSight JTAG connector.
+
+source [find target/ls1012a.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_imx7sabre.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_imx7sabre.cfg
new file mode 100644
index 0000000..9b0c743
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_imx7sabre.cfg
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP IMX7SABRE board
+# use on-board JTAG header
+transport select jtag
+
+# set a safe speed, can be overridden
+adapter speed 1000
+
+# reset configuration has TRST and SRST support
+reset_config trst_and_srst srst_push_pull
+# need at least 100ms delay after SRST release for JTAG
+adapter srst delay 100
+
+# source the target file
+source [find target/imx7.cfg]
+# import mrw proc
+source [find mem_helper.tcl]
+
+# function to disable the on-chip watchdog
+proc imx7_disable_wdog { } {
+        # echo "disable watchdog power-down counter"
+        mwh phys 0x30280008 0x00
+}
+
+proc imx7_uart_dbgconf { } {
+	# disable response to debug_req signal for uart1
+	mww phys 0x308600b4 0x0a60
+}
+
+proc check_bits_set_32 { addr mask } {
+    while { [expr {[mrw $addr] & $mask} == 0] } { }
+}
+
+proc apply_dcd { } {
+    # echo "apply dcd"
+
+    mww phys 0x30340004 0x4F400005
+    # Clear then set bit30 to ensure exit from DDR retention
+    mww phys 0x30360388 0x40000000
+    mww phys 0x30360384 0x40000000
+
+    mww phys 0x30391000 0x00000002
+    mww phys 0x307a0000 0x01040001
+    mww phys 0x307a01a0 0x80400003
+    mww phys 0x307a01a4 0x00100020
+    mww phys 0x307a01a8 0x80100004
+    mww phys 0x307a0064 0x00400046
+    mww phys 0x307a0490 0x00000001
+    mww phys 0x307a00d0 0x00020083
+    mww phys 0x307a00d4 0x00690000
+    mww phys 0x307a00dc 0x09300004
+    mww phys 0x307a00e0 0x04080000
+    mww phys 0x307a00e4 0x00100004
+    mww phys 0x307a00f4 0x0000033f
+    mww phys 0x307a0100 0x09081109
+    mww phys 0x307a0104 0x0007020d
+    mww phys 0x307a0108 0x03040407
+    mww phys 0x307a010c 0x00002006
+    mww phys 0x307a0110 0x04020205
+    mww phys 0x307a0114 0x03030202
+    mww phys 0x307a0120 0x00000803
+    mww phys 0x307a0180 0x00800020
+    mww phys 0x307a0184 0x02000100
+    mww phys 0x307a0190 0x02098204
+    mww phys 0x307a0194 0x00030303
+    mww phys 0x307a0200 0x00000016
+    mww phys 0x307a0204 0x00171717
+    mww phys 0x307a0214 0x04040404
+    mww phys 0x307a0218 0x0f040404
+    mww phys 0x307a0240 0x06000604
+    mww phys 0x307a0244 0x00000001
+    mww phys 0x30391000 0x00000000
+    mww phys 0x30790000 0x17420f40
+    mww phys 0x30790004 0x10210100
+    mww phys 0x30790010 0x00060807
+    mww phys 0x307900b0 0x1010007e
+    mww phys 0x3079009c 0x00000d6e
+    mww phys 0x30790020 0x08080808
+    mww phys 0x30790030 0x08080808
+    mww phys 0x30790050 0x01000010
+    mww phys 0x30790050 0x00000010
+
+    mww phys 0x307900c0 0x0e407304
+    mww phys 0x307900c0 0x0e447304
+    mww phys 0x307900c0 0x0e447306
+
+    check_bits_set_32 0x307900c4 0x1
+
+    mww phys 0x307900c0 0x0e447304
+    mww phys 0x307900c0 0x0e407304
+
+
+    mww phys 0x30384130 0x00000000
+    mww phys 0x30340020 0x00000178
+    mww phys 0x30384130 0x00000002
+    mww phys 0x30790018 0x0000000f
+
+    check_bits_set_32 0x307a0004 0x1
+}
+
+# disable internal reset-assert handling to
+# allow reset-init to work
+$_TARGETNAME.0 configure -event reset-assert ""
+$_TARGETNAME.1 configure -event reset-assert ""
+$_TARGETNAME_2 configure -event reset-assert ""
+
+$_TARGETNAME.0 configure -event reset-init {
+    global _CHIPNAME
+    imx7_disable_wdog
+    imx7_uart_dbgconf
+    apply_dcd
+    $_CHIPNAME.dap memaccess 0
+}
+
+target smp $_TARGETNAME.0 $_TARGETNAME.1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_imx8mp-evk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_imx8mp-evk.cfg
new file mode 100644
index 0000000..4e101d4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_imx8mp-evk.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for NXP IMX8M Plus EVK
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+
+# board has an i.MX8MP with 4 Cortex-A55 cores
+set CHIPNAME imx8mp
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8mp.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_lpc-link2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_lpc-link2.cfg
new file mode 100644
index 0000000..52f13fa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_lpc-link2.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP LPC-Link2
+#
+# http://www.nxp.com/board/OM13054.html
+# https://www.lpcware.com/lpclink2
+# http://embeddedartists.com/products/lpcxpresso/lpclink2.php
+#
+
+source [find target/lpc4370.cfg]
+
+# W25Q80BVSSIG w/ 1 MB flash
+flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_mcimx8m-evk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_mcimx8m-evk.cfg
new file mode 100644
index 0000000..bcd0f67
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_mcimx8m-evk.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for NXP MC-IMX8M-EVK
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+# board has an i.MX8MQ with 4 Cortex-A53 cores
+set CHIPNAME imx8mq
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_rdb-ls1046a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_rdb-ls1046a.cfg
new file mode 100644
index 0000000..fde1829
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_rdb-ls1046a.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1046ARDB (Reference Design Board)
+# This is for the "console" USB port on the front panel
+# You must ensure that SW4-7 is in the "off" position
+
+# NXP K20
+# The firmware implements the old CMSIS-DAP v1 USB HID interface
+# You must pass --enable-cmsis-dap to ./configure to enable it
+source [find interface/cmsis-dap.cfg]
+
+transport select jtag
+reset_config srst_only
+
+source [find target/ls1046a.cfg]
+
+# The adapter can't handle 10MHz
+adapter speed 5000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_rdb-ls1088a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_rdb-ls1088a.cfg
new file mode 100644
index 0000000..40483f2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/nxp_rdb-ls1088a.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1088ARDB (Reference Design Board)
+# This is for the "main" JTAG connector J55
+
+transport select jtag
+reset_config srst_only
+
+# To access the CPLD, populate J48 and add `-c 'set CWTAP 1'` to your command
+# line. At the time of this writing, programming is unsupported.
+if { [info exists CWTAP] } {
+	source [find cpld/altera-epm240.cfg]
+} else {
+	source [find target/ls1088a.cfg]
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_LPC2378STK.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_LPC2378STK.cfg
new file mode 100644
index 0000000..23588ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_LPC2378STK.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#####################################################
+# Olimex LPC2378STK eval board
+#
+# http://olimex.com/dev/lpc-2378stk.html
+#
+# Author: Sten, debian@sansys-electronic.com
+#####################################################
+#
+
+source [find target/lpc2378.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_lpc_h2148.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_lpc_h2148.cfg
new file mode 100644
index 0000000..96ae405
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_lpc_h2148.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex LPC-H2148 eval board
+#
+# http://www.olimex.com/dev/lpc-h2148.html
+#
+
+source [find target/lpc2148.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_sam7_ex256.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_sam7_ex256.cfg
new file mode 100644
index 0000000..9924f27
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_sam7_ex256.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
+
+source [find target/at91sam7x256.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_sam7_la2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_sam7_la2.cfg
new file mode 100644
index 0000000..d91432b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_sam7_la2.cfg
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/at91sam7a2.cfg]
+
+# delays needed to get stable reads of cpu state
+jtag_ntrst_delay 10
+adapter srst delay 200
+
+# board uses pullup and connects only srst
+reset_config srst_open_drain
+
+# srst is connected to NRESET of CPU and fully resets everything...
+reset_config srst_only srst_pulls_trst
+
+adapter speed 1
+$_TARGETNAME configure -event reset-start {
+	adapter speed 1
+}
+
+$_TARGETNAME configure -event reset-init {
+	# init script from http://www.mikrocontroller.net/topic/107462
+	# AT91SAM7A2
+	# AMC (advanced memory controller)
+
+	echo "setting up AMC"
+	# AMC_CS0 - FLASH 1MB (0x40000000-0x400FFFFF) + DM9000E (0x40100000)
+	mww 0xFFE00000 0x40003EBD
+
+	# AMC_CS1 - RAM low 2MB (0x40400000-0x405FFFFF)
+	mww 0xFFE00004 0x404030A9
+
+	# AMC_CS2 - RAM high 2MB (0x40800000-0x405FFFFF)
+	#mww 0xFFE00008 0x404030A9
+	# changed to  0x40_8_
+	mww 0xFFE00008 0x408030A9
+
+	# AMC_MCR
+	mww 0xFFE00024 0x00000004
+
+	# AMC_RCR force remap
+	mww 0xFFE00020 0x00000001
+
+	echo "set up AMC"
+	sleep 100
+
+	# the following base addresses from the original script did not correspond to those from datasheet
+	# changed bases from 0xFF000000 to 0xFFF00000
+
+	# disable watchdog, to prevent unwanted resets
+	mww 0xFFFA0068 0x00000000
+	echo "disabled watchdog"
+
+	sleep 50
+
+	# disable PLL
+	mww 0xFFFEC004 0x18070004
+
+	# PLL = 10 ==> Coreclock = 6Mhz*10/2 = 30 Mhz
+	mww 0xFFFEC010 0x762D800A
+
+	# enable PLL
+	mww 0xFFFEC000 0x23050004
+	echo "set up pll"
+
+	sleep 100
+	adapter speed 5000
+}
+
+$_TARGETNAME arm7_9 dcc_downloads enable
+$_TARGETNAME arm7_9 fast_memory_access enable
+
+# remap:  ram at 0, flash at 0x40000000, like reset-init above does
+$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1
+flash bank onboard.flash cfi 0x40000000 0x00100000 2 2 at91sam7a2.cpu
+
+# boot: ram at 0x300000, flash at 0x0, useful if board is in funny configuration
+#$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
+#flash bank onboard1.flash cfi 0x00000000 0x00100000 2 2 at91sam7a2.cpu
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_sam9_l9260.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_sam9_l9260.cfg
new file mode 100644
index 0000000..7491a0e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_sam9_l9260.cfg
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Olimex SAM9-L9260 Development Board
+#
+# http://www.olimex.com/dev/sam9-L9260.html
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+#                     PMC configured for external 18.432 MHz crystal
+#
+# 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
+# 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
+# Dataflash : 1 x Atmel AT45DB161D, 16Mbit
+#
+################################################################################
+
+source [find target/at91sam9260.cfg]
+
+# NTRST_E jumper is enabled by default, so we don't need to override the reset
+# config.
+#reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+	# At reset, CPU runs at 32.768 kHz.  JTAG frequency must be 6 times slower if
+	# RCLK is not supported.
+	jtag_rclk 5
+	halt
+
+	# RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may
+	# be enabled... use physical address.
+	mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
+
+	##
+	# Clock configuration for 99.328 MHz main clock.
+	##
+    echo "Setting up clock"
+	mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup
+	sleep 20                  ;# wait 20 ms (need 15.6 ms for startup)
+	mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz)
+	sleep 10                  ;# wait 10 ms
+	mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
+	sleep 20                  ;# wait 20 ms (need 1.9 ms for startup)
+	mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
+	sleep 10                  ;# wait 10 ms
+	mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
+
+	# Increase JTAG speed to 6 MHz if RCLK is not supported.
+	jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
+
+	##
+	# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
+	##
+    echo "Configuring SDRAM"
+	mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
+	mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
+
+	mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
+
+	mww 0xffffea00 0x1        ;# SDRAMC_MR : issue NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2        ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4        ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3        ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0        ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+
+	mww 0xffffea04 0x2b6      ;# SDRAMC_TR : set refresh timer count to 7 us
+
+    ##
+    # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
+    ##
+    echo "Configuring NAND flash"
+    mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
+    mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+    mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
+    mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
+    mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
+    mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
+
+    mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
+
+    mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
+    mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
+    mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
+    mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+                               #             3 TDF cycles, no optimization
+
+    mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
+    mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
+
+    nand probe at91sam9260.flash
+
+    ##
+    # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
+    ##
+    echo "Setting up dataflash"
+    mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
+                               #            2(SPI0_SPCK), and 11(SPI0_NPCS1)
+    mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
+    mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
+    mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
+
+    mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
+    mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
+    mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
+
+    mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
+                               #             250ns delay before SPCK, 250ns b/n tx
+
+    mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
+    mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
+}
+
+nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800
+at91sam9 cle 0 22
+at91sam9 ale 0 21
+at91sam9 rdy_busy 0 0xfffff800 13
+at91sam9 ce 0 0xfffff800 14
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_h103.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_h103.cfg
new file mode 100644
index 0000000..92ca7ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_h103.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Olimex STM32-H103 eval board
+# http://olimex.com/dev/stm32-h103.html
+
+# Work-area size (RAM size) = 20kB for STM32F103RB device
+set WORKAREASIZE 0x5000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_h107.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_h107.cfg
new file mode 100644
index 0000000..c199cdc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_h107.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex STM32-H107
+#
+# http://olimex.com/dev/stm32-h107.html
+#
+
+# Work-area size (RAM size) = 64kB for STM32F107VC device
+set WORKAREASIZE 0x10000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_h405.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_h405.cfg
new file mode 100644
index 0000000..f2f1d7f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_h405.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Olimex STM32-H405 eval board
+# https://www.olimex.com/Products/ARM/ST/STM32-H405/
+
+# Work-area size (RAM size) = 128kB for STM32F405RG device
+set WORKAREASIZE 0x20000
+
+source [find target/stm32f4x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_p107.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_p107.cfg
new file mode 100644
index 0000000..9511030
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/olimex_stm32_p107.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex STM32-P107
+#
+# http://olimex.com/dev/stm32-p107.html
+#
+
+# Work-area size (RAM size) = 64kB for STM32F107VC device
+set WORKAREASIZE 0x10000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/omap2420_h4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/omap2420_h4.cfg
new file mode 100644
index 0000000..ec16965
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/omap2420_h4.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OMAP2420 SDP board ("H4")
+
+source [find target/omap2420.cfg]
+
+# NOTE: this assumes you're *NOT* using a TI-14 connector.
+reset_config trst_and_srst separate
+
+# Board configs can vary a *LOT* ... parts, jumpers, etc.
+# This GP board boots from cs0 using NOR (2x32M), and also
+# has 64M NAND on cs6.
+flash bank h4.u10 cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
+flash bank h4.u11 cfi 0x06000000 0x02000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/openrd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/openrd.cfg
new file mode 100644
index 0000000..f6c8317
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/openrd.cfg
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell OpenRD
+
+source [find interface/ftdi/openrd.cfg]
+source [find target/feroceon.cfg]
+
+adapter speed 2000
+
+$_TARGETNAME configure \
+	-work-area-phys 0x10000000 \
+	-work-area-size 65536 \
+	-work-area-backup 0
+
+arm7_9 dcc_downloads enable
+
+# this assumes the hardware default peripherals location before u-Boot moves it
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME orion 0 0xd8000000
+
+proc openrd_init { } {
+
+	# We need to assert DBGRQ while holding nSRST down.
+	# However DBGACK will be set only when nSRST is released.
+	# Furthermore, the JTAG interface doesn't respond at all when
+	# the CPU is in the WFI (wait for interrupts) state, so it is
+	# possible that initial tap examination failed.  So let's
+	# re-examine the target again here when nSRST is asserted which
+	# should then succeed.
+	adapter assert srst
+	feroceon.cpu arp_examine
+	halt 0
+	adapter deassert srst
+	wait_halt
+
+	arm mcr 15 0 0 1 0 0x00052078
+
+	mww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register
+	mww 0xD0001404 0x37543000 ;#  Dunit Control Low Register
+	mww 0xD0001408 0x22125451 ;#  DDR SDRAM Timing (Low) Register
+	mww 0xD000140C 0x00000A33 ;#  DDR SDRAM Timing (High) Register
+	mww 0xD0001410 0x000000CC ;#  DDR SDRAM Address Control Register
+	mww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register
+	mww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register
+	mww 0xD000141C 0x00000C52 ;#  DDR SDRAM Mode Register
+	mww 0xD0001420 0x00000004 ;#  DDR SDRAM Extended Mode Register
+	mww 0xD0001424 0x0000F17F ;#  Dunit Control High Register
+	mww 0xD0001428 0x00085520 ;#  Dunit Control High Register
+	mww 0xD000147c 0x00008552 ;#  Dunit Control High Register
+	mww 0xD0001504 0x0FFFFFF1 ;#  CS0n Size Register
+	mww 0xD0001508 0x10000000 ;#  CS1n Base Register
+	mww 0xD000150C 0x0FFFFFF5 ;#  CS1n Size Register
+	mww 0xD0001514 0x00000000 ;#  CS2n Size Register
+	mww 0xD000151C 0x00000000 ;#  CS3n Size Register
+	mww 0xD0001494 0x00120012 ;#  DDR2 SDRAM ODT Control (Low) Register
+	mww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister
+	mww 0xD000149C 0x0000E40F ;#  DDR2 Dunit ODT Control Register
+	mww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register
+	mww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+
+	mww 0xD0010000 0x01111111 ;#  MPP  0 to 7
+	mww 0xD0010004 0x11113322 ;#  MPP  8 to 15
+	mww 0xD0010008 0x00001111 ;#  MPP 16 to 23
+
+	mww 0xD0010418 0x003E07CF ;#  NAND Read Parameters REgister
+	mww 0xD001041C 0x000F0F0F ;#  NAND Write Parameters Register
+	mww 0xD0010470 0x01C7D943 ;#  NAND Flash Control Register
+
+}
+
+proc openrd_reflash_uboot { } {
+
+	# reflash the u-Boot binary and reboot into it
+	openrd_init
+	nand probe 0
+	nand erase 0 0x0 0xa0000
+	nand write 0 uboot.bin 0 oob_softecc_kw
+	resume
+
+}
+
+proc openrd_load_uboot { } {
+
+	# load u-Boot into RAM and execute it
+	openrd_init
+	load_image uboot.elf
+	verify_image uboot.elf
+	resume 0x00600000
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/or1k_generic.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/or1k_generic.cfg
new file mode 100644
index 0000000..b6cf3a0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/or1k_generic.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# If you want to use the VJTAG TAP or the XILINX BSCAN,
+# you must set your FPGA TAP ID here
+
+set FPGATAPID 0x020b30dd
+
+# Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN)
+if { [info exists TAP_TYPE] == 0} {
+   set TAP_TYPE VJTAG
+}
+
+# Set your chip name
+set CHIPNAME or1200
+
+source [find target/or1k.cfg]
+
+# Set the servers polling period to 1ms (needed to JSP Server)
+poll_period 1
+
+# Set the adapter speed
+adapter speed 3000
+
+# Enable the target description feature
+gdb target_description enable
+
+# Add a new register in the cpu register list. This register will be
+# included in the generated target descriptor file.
+# format is addreg [name] [address] [feature] [reg_group]
+addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
+
+# Override default init_reset
+proc init_reset {mode} {
+	soft_reset_halt
+	resume
+}
+
+# Target initialization
+init
+echo "Halting processor"
+halt
+
+foreach name [target names] {
+	set y [$name cget -endian]
+	set z [$name cget -type]
+	puts [format "Chip is %s, Endian: %s, type: %s" \
+	      $name $y $z]
+}
+
+set c_blue  "\033\[01;34m"
+set c_reset "\033\[0m"
+
+puts [format "%sTarget ready...%s" $c_blue $c_reset]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/osk5912.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/osk5912.cfg
new file mode 100644
index 0000000..0759a27
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/osk5912.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://omap.spectrumdigital.com/osk5912/
+
+source [find target/omap5912.cfg]
+
+# NOTE: this assumes you're using the ARM 20-pin ("Multi-ICE")
+# JTAG connector, and accordingly have J1 connecting pins 1 & 2.
+# The TI-14 pin needs "trst_only", and J1 connecting 2 & 3.
+reset_config trst_and_srst separate
+
+# NOTE:  boards with XOMAP parts wire nSRST to nPWRON_RESET.
+# That resets everything -- including JTAG and EmbeddedICE.
+# So they must use "reset_config srst_pulls_trst".
+
+# NOTE:  an expansion board could add a trace connector ... if
+# it does, change this appropriately.  And reset_config too,
+# assuming JTAG_DIS reroutes JTAG to that connector.
+etm config $_TARGETNAME 8 demultiplexed full dummy
+etm_dummy config $_TARGETNAME
+
+# standard boards populate two 16 MB chips, but manufacturing
+# options or an expansion board could change this config.
+flash bank osk.u1 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
+flash bank osk.u2 cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
+
+proc osk5912_init {} {
+	omap5912_reset
+
+	# detect flash
+	flash probe 0
+	flash probe 1
+}
+$_TARGETNAME configure -event reset-init { osk5912_init }
+
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/phone_se_j100i.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/phone_se_j100i.cfg
new file mode 100644
index 0000000..70387ee
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/phone_se_j100i.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Sony Ericsson J100I Phone
+#
+# more information can be found on
+# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
+#
+source [find target/ti_calypso.cfg]
+
+# external flash
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x400000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/phytec_lpc3250.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/phytec_lpc3250.cfg
new file mode 100644
index 0000000..036b16f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/phytec_lpc3250.cfg
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/lpc3250.cfg]
+
+adapter srst delay 200
+jtag_ntrst_delay 1
+adapter speed 200
+reset_config trst_and_srst separate
+
+arm7_9 dcc_downloads enable
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+
+$_TARGETNAME configure -event reset-start {
+             arm7_9 fast_memory_access disable
+             adapter speed 200
+}
+
+$_TARGETNAME configure -event reset-end {
+             adapter speed 6000
+             arm7_9 fast_memory_access enable
+}
+
+$_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
+
+# Bare-bones initialization of core clocks and SDRAM
+proc phytec_lpc3250_init { } {
+        # Set clock dividers
+        #   ARMCLK = 266.5 MHz
+        #   HCLK   = 133.25 MHz
+        #   PERIPHCLK = 13.325 MHz
+        mww 0x400040BC 0
+        mww 0x40004050 0x140
+        mww 0x40004040 0x4D
+        mww 0x40004058 0x16250
+
+        # Init PLLs
+        mww 0x40004044 0x006
+        sleep 1 busy
+        mww 0x40004044 0x106
+        sleep 1 busy
+        mww 0x40004044 0x006
+        sleep 1 busy
+        mww 0x40004048 0x2
+
+        # Init SDRAM with 133 MHz timings
+        mww 0x40028134 0x00FFFFFF
+        mww 0x4002802C 0x00000008
+
+        mww 0x31080000 1
+        mww 0x31080008 0
+        mww 0x40004068 0x1C000
+        mww 0x31080028 0x11
+
+        mww 0x31080400 0
+        mww 0x31080440 0
+        mww 0x31080460 0
+        mww 0x31080480 0
+
+        # Delays
+        mww 0x31080030 1
+        mww 0x31080034 6
+        mww 0x31080038 10
+        mww 0x31080044 1
+        mww 0x31080048 9
+        mww 0x3108004C 12
+        mww 0x31080050 10
+        mww 0x31080054 1
+        mww 0x31080058 1
+        mww 0x3108005C 0
+
+        mww 0x31080100 0x5680
+        mww 0x31080104 0x302
+
+        # Init sequence
+        mww 0x31080020 0x193
+        sleep 1 busy
+        mww 0x31080024 1
+        mww 0x31080020 0x113
+        sleep 1 busy
+        mww 0x31080020 0x013
+        sleep 1 busy
+        mww 0x31080024 65
+        mww 0x31080020 0x093
+        mdw 0x80020000
+        mww 0x31080020 0x013
+
+        # SYS_CTRL remapping
+        mww 0x40004014 1
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pic-p32mx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pic-p32mx.cfg
new file mode 100644
index 0000000..0703220
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pic-p32mx.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Olimex PIC-P32MX has a PIC32MX
+
+set CPUTAPID 0x40916053
+source [find target/pic32mx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pico-debug.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pico-debug.cfg
new file mode 100644
index 0000000..ba59f86
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pico-debug.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# pico-debug is a virtual CMSIS-DAP debug adapter
+# it runs on the very same RP2040 target being debugged without additional hardware
+# https://github.com/majbthrd/pico-debug
+
+source [find interface/cmsis-dap.cfg]
+adapter speed 4000
+
+set CHIPNAME rp2040
+source [find target/rp2040-core0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pipistrello.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pipistrello.cfg
new file mode 100644
index 0000000..17584a0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pipistrello.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://pipistrello.saanlima.com/
+
+source [find interface/ftdi/pipistrello.cfg]
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
+
+# example command to write bitstream, soft-cpu bios and runtime:
+# openocd -f board/pipistrello.cfg -c "init;\
+# jtagspi_init 0 bscan_spi_xc6slx45.bit;\
+# jtagspi_program bitstream-pistrello.bin 0;\
+# jtagspi_program bios.bin 0x170000;\
+# jtagspi_program runtime.fbi 0x180000;\
+# xc6s_program xc6s.tap;\
+# exit"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/propox_mmnet1001.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/propox_mmnet1001.cfg
new file mode 100644
index 0000000..0e12604
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/propox_mmnet1001.cfg
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+## Chip:
+set CHIPNAME at91sam9260
+set CPUTAPID 0x0792603f
+set ENDIAN little
+source [find target/at91sam9260.cfg]
+
+$_TARGETNAME configure -event reset-init {at91sam_init}
+
+
+proc at91sam_init { } {
+
+	# at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
+	jtag_rclk 4
+
+	# Enable user reset and disable watchdog
+	mww 0xfffffd08 0xa5000501         ;# RSTC_MR : enable user reset
+	mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	# Oscillator setup
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator (18.432 MHz)
+	sleep 20                          ;# wait 20 ms
+	mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+	sleep 10                          ;# wait 10 ms
+
+	# now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz
+	jtag_rclk 2000
+
+	mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
+	sleep 20                          ;# wait 20 ms
+	mww 0xfffffc2c 0x207c3f0c         ;# CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)
+	sleep 10                          ;# wait 10 ms
+	mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler
+	sleep 10                          ;# wait 10 ms
+	mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected
+	sleep 10                          ;# wait 10 ms
+
+	# now we are running at 198.656 MHz kHz => full speed jtag
+	jtag_rclk 30000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	# Configure PIO Controller for SDRAM data-lines D16-D31
+	# PC16-PC31 = Peripheral A: D16-D32
+	mww 0xfffff844 0xffff0000	;# Interrupt Disable
+	mww 0xfffff854 0xffff0000	;# Multi-Drive Disable
+	mww 0xfffff860 0xffff0000	;# Pull-Up Disable
+	mww 0xfffff870 0xffff0000	;# PIO_ASR : Select peripheral A function for D15..D31
+	mww 0xfffff804 0xffff0000	;# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)
+	mww 0xfffffc10 0x00000010	;# Enable PIO-C Clock in PMC (PID=4)
+
+	# SD-Ram setup
+	mww 0xffffef1c 0x2			;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+	mww 0xffffea08 0x85227259	;# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))
+	mww 0xffffea00 0x1			;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2			;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (1st)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (3th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (4th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (5th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (6th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (7th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			;# SDRAMC_MR : issue an 'Auto-Refresh' command (8th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x3			;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0			;# SDRAMC_MR : Normal Mode
+	mww 0x20000000 0
+	mww 0xFFFFEA04 0x30d		;# SDRAM Refresh Time Register
+								 #  datasheet: 8k refresh cycles / 64 ms
+								 #  MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pxa255_sst.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pxa255_sst.cfg
new file mode 100644
index 0000000..8d00dfe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/pxa255_sst.cfg
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# A PXA255 test board with SST 39LF400A flash
+#
+# At reset the memory map is as follows. Note that
+# the memory map changes later on as the application
+# starts...
+#
+# RAM at 0x4000000
+# Flash at 0x00000000
+#
+source [find target/pxa255.cfg]
+
+# Target name is set by above
+$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
+
+# flash bank       [options]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
+
+proc pxa255_sst_init {} {
+	xscale cp15   15      0x00002001  ;#Enable CP0 and CP13 access
+	#
+	# setup GPIO
+	#
+	mww    0x40E00018  0x00008000  ;#CPSR0
+	sleep   20
+	mww    0x40E0001C  0x00000002  ;#GPSR1
+	sleep   20
+	mww    0x40E00020  0x00000008  ;#GPSR2
+	sleep   20
+	mww    0x40E0000C  0x00008000  ;#GPDR0
+	sleep   20
+	mww    0x40E00054  0x80000000  ;#GAFR0_L
+	sleep   20
+	mww    0x40E00058  0x00188010  ;#GAFR0_H
+	sleep   20
+	mww    0x40E0005C  0x60908018  ;#GAFR1_L
+	sleep   20
+	mww    0x40E0000C  0x0280E000  ;#GPDR0
+	sleep   20
+	mww    0x40E00010  0x821C88B2  ;#GPDR1
+	sleep   20
+	mww    0x40E00014  0x000F03DB  ;#GPDR2
+	sleep   20
+	mww    0x40E00000  0x000F03DB  ;#GPLR0
+	sleep   20
+
+
+	mww    0x40F00004  0x00000020  ;#PSSR
+	sleep   20
+
+	#
+	# setup memory controller
+	#
+	mww    0x48000008  0x01111998  ;#MSC0
+	sleep   20
+	mww    0x48000010  0x00047ff0  ;#MSC2
+	sleep   20
+	mww    0x48000014  0x00000000  ;#MECR
+	sleep   20
+	mww    0x48000028  0x00010504  ;#MCMEM0
+	sleep   20
+	mww    0x4800002C  0x00010504  ;#MCMEM1
+	sleep   20
+	mww    0x48000030  0x00010504  ;#MCATT0
+	sleep   20
+	mww    0x48000034  0x00010504  ;#MCATT1
+	sleep   20
+	mww    0x48000038  0x00004715  ;#MCIO0
+	sleep   20
+	mww    0x4800003C  0x00004715  ;#MCIO1
+	sleep   20
+	#
+	mww    0x48000004  0x03CA4018  ;#MDREF
+	sleep   20
+	mww    0x48000004  0x004B4018  ;#MDREF
+	sleep   20
+	mww    0x48000004  0x000B4018  ;#MDREF
+	sleep   20
+	mww    0x48000004  0x000BC018  ;#MDREF
+	sleep   20
+	mww    0x48000000  0x00001AC8  ;#MDCNFG
+	sleep   20
+
+	sleep   20
+
+	mww    0x48000000  0x00001AC9  ;#MDCNFG
+	sleep   20
+	mww    0x48000040  0x00000000  ;#MDMRS
+	sleep   20
+}
+
+$_TARGETNAME configure -event reset-init {pxa255_sst_init}
+
+reset_config trst_and_srst
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+#xscale debug_handler 0  0xFFFF0800      ;# debug handler base address
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/quark_d2000_refboard.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/quark_d2000_refboard.cfg
new file mode 100644
index 0000000..3af5735
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/quark_d2000_refboard.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Quark microcontroller D2000 Reference Board (web search for doc num 333582)
+
+# the board has an onboard FTDI FT232H chip
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6014
+ftdi channel 0
+
+ftdi layout_init 0x0000 0x030b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0100
+
+source [find target/quark_d20xx.cfg]
+
+adapter speed 1000
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/quark_x10xx_board.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/quark_x10xx_board.cfg
new file mode 100644
index 0000000..aa6adaf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/quark_x10xx_board.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# There are many Quark boards that can host the quark_x10xx SoC
+# Galileo is an example board
+
+source [find target/quark_x10xx.cfg]
+
+#default frequency but this can be adjusted at runtime
+adapter speed 4000
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/quicklogic_quickfeather.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/quicklogic_quickfeather.cfg
new file mode 100644
index 0000000..b522eff
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/quicklogic_quickfeather.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# QuickLogic EOS S3 QuickFeather
+# https://www.quicklogic.com/products/eos-s3/quickfeather-development-kit/
+
+source [find target/eos_s3.cfg]
+
+reset_config srst_only
+
+transport select swd
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/radiona_ulx3s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/radiona_ulx3s.cfg
new file mode 100644
index 0000000..eb9b027
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/radiona_ulx3s.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Radiona ULX3S
+# https://radiona.org/ulx3s/
+# Currently there are following board variants:
+# CS-ULX3S-01 - LFE5U 12F
+# CS-ULX3S-02 - LFE5U 45F
+# CS-ULX3S-03 - LFE5U 85F
+#
+# two JTAG interfaces:
+# - US1, micro USB port connected to FT231XQ
+#   This interface should be used with following config:
+#        interface/ft232r/radiona_ulx3s.cfg
+# - J4, 6 pin connector
+#
+# Both of this interfaces share the JTAG lines (TDI, TMS, TCK, TDO) between
+# Lattice ECP5 FPGA chip and ESP32 WiFi controller.
+# Note: TRST_N of the ESP32 is pulled up by default and can be pulled down over
+# J3 interface.
+# See schematics for more information:
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v314.pdf
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v315.pdf
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf
+
+source [find interface/ft232r/radiona_ulx3s.cfg]
+source [find fpga/lattice_ecp5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/redbee.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/redbee.cfg
new file mode 100644
index 0000000..714dfdc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/redbee.cfg
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/mc13224v.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg
new file mode 100644
index 0000000..2d98cc5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Achilles Instant-Development Kit Arria 10 SoC SoM
+# https://www.reflexces.com/products-solutions/achilles-instant-development-kit-arria-10-soc-som
+#
+
+if { [info exists USE_EXTERNAL_DEBUGGER] } {
+	echo "Using external debugger"
+} else {
+	source [find interface/altera-usb-blaster2.cfg]
+	usb_blaster device_desc "Arria10 IDK"
+}
+
+source [find fpga/altera-10m50.cfg]
+source [find target/altera_fpgasoc_arria10.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_dk-s7g2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_dk-s7g2.cfg
new file mode 100644
index 0000000..e310112
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_dk-s7g2.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Renesas Synergy DK-S7G2
+#
+
+source [find interface/jlink.cfg]
+transport select swd
+
+# XXX 19-pin SWD+TRACE connector also available
+
+# Synergy R7FS7G27H2A01CBD
+source [find target/renesas_s7g2.cfg]
+
+# 32 MB QSPI flash (Micron N25Q256A13EF840E)
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_falcon.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_falcon.cfg
new file mode 100644
index 0000000..c796f85
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_falcon.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Renesas R-Car V3U Falcon Board Config
+
+# The Falcon board comes with either an V3U SOC.
+
+echo "\nFalcon:"
+if { ![info exists SOC] } {
+	set SOC V3U
+}
+source [find target/renesas_rcar_gen3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_gr_peach.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_gr_peach.cfg
new file mode 100644
index 0000000..b3823ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_gr_peach.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ/A1H GR-Peach board
+
+reset_config srst_only
+
+source [find target/renesas_r7s72100.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_porter.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_porter.cfg
new file mode 100644
index 0000000..134e9ba
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_porter.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car M2 Evaluation Board
+
+set SOC M2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_salvator-xs.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_salvator-xs.cfg
new file mode 100644
index 0000000..1323c13
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_salvator-xs.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car Gen3 Salvator-X(S) Board Config
+
+# The Salvator-X(S) boards come with either an H3, M3W, or M3N SOC.
+
+echo "\nSalvator-X(S):"
+if { ![info exists SOC] } {
+	set SOC H3
+}
+source [find target/renesas_rcar_gen3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_silk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_silk.cfg
new file mode 100644
index 0000000..dd61e1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_silk.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car E2 Evaluation Board
+
+set SOC E2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_stout.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_stout.cfg
new file mode 100644
index 0000000..69a524b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/renesas_stout.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car H2 Evaluation Board
+
+set SOC H2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rigado_bmd300_ek.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rigado_bmd300_ek.cfg
new file mode 100644
index 0000000..601041d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rigado_bmd300_ek.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Rigado BMD-300 Evaluation Kit
+#
+# https://www.rigado.com/products/modules/bmd-300/
+#
+
+source [find interface/jlink.cfg]
+transport select swd
+adapter speed 1000
+
+source [find target/nrf52.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rpi3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rpi3.cfg
new file mode 100644
index 0000000..fd93a9d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rpi3.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the Raspberry Pi 3 board with BCM2837 chip
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837/README.md
+#
+# Enable JTAG GPIO on Raspberry Pi boards
+# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md
+
+source [find target/bcm2837.cfg]
+transport select jtag
+
+# Raspberry Pi boards only expose Test Reset (TRST) pin, no System Reset (SRST)
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rpi4b.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rpi4b.cfg
new file mode 100644
index 0000000..5b046af
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rpi4b.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the Raspberry Pi 4 model B board with BCM2711 chip
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md
+#
+# Enable JTAG GPIO on Raspberry Pi boards
+# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md
+
+source [find target/bcm2711.cfg]
+transport select jtag
+
+# Raspberry Pi boards only expose Test Reset (TRST) pin, no System Reset (SRST)
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rsc-w910.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rsc-w910.cfg
new file mode 100644
index 0000000..b07f940
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/rsc-w910.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Avalue RSC-W8910 sbc
+# http://www.avalue.com.tw/products/RSC-W910.cfm
+# 2MB NOR Flash
+# 64MB SDRAM
+# 128MB NAND Flash
+
+# Based on Nuvoton nuc910
+source [find target/nuc910.cfg]
+
+#
+# reset only behaves correctly if we use srst_pulls_trst
+#
+reset_config trst_and_srst srst_pulls_trst
+
+adapter speed 1000
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME
+
+set _NANDNAME $_CHIPNAME.nand
+nand device $_NANDNAME nuc910 $_TARGETNAME
+
+#
+# Target events
+#
+
+$_TARGETNAME configure -event reset-start {adapter speed 1000}
+
+$_TARGETNAME configure -event reset-init {
+	# switch on PLL for 200MHz operation
+	# running from 15MHz input clock
+
+	mww 0xB0000200 0x00000030 ;# CLKEN
+	mww 0xB0000204 0x00000f3c ;# CLKSEL
+	mww 0xB0000208 0x05007000 ;# CLKDIV
+	mww 0xB000020C 0x00004f24 ;# PLLCON0
+	mww 0xB0000210 0x00002b63 ;# PLLCON1
+	mww 0xB000000C 0x08817fa6 ;# MFSEL
+	sleep 10
+
+	# we are now running @ 200MHz
+	# enable all openocd speed tweaks
+
+	arm7_9 dcc_downloads enable
+	arm7_9 fast_memory_access enable
+	adapter speed 15000
+
+	# map nor flash to 0x20000000
+	# map sdram to 0x00000000
+
+	mww 0xb0001000 0x000530c1 ;# EBICON
+	mww 0xb0001004 0x40030084 ;# ROMCON
+	mww 0xb0001008 0x000010ee ;# SDCONF0
+	mww 0xb000100C 0x00000000 ;# SDCONF1
+	mww 0xb0001010 0x0000015b ;# SDTIME0
+	mww 0xb0001014 0x0000015b ;# SDTIME1
+	mww 0xb0001018 0x00000000 ;# EXT0CON
+	mww 0xb000101C 0x00000000 ;# EXT1CON
+	mww 0xb0001020 0x00000000 ;# EXT2CON
+	mww 0xb0001024 0x00000000 ;# EXT3CON
+	mww 0xb000102c 0x00ff0048 ;# CKSKEW
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sayma_amc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sayma_amc.cfg
new file mode 100644
index 0000000..b714609
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sayma_amc.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Sayma AMC is an FPGA board for the µTCA AMC format
+# The board is open hardware (CERN OHL) and the gateware and software
+# running on it are open source (ARTIQ, LGPLv3+).
+#
+# https://github.com/m-labs/sinara/wiki/Sayma
+#
+# It contains a Xilinx Kintex Ultrascale 040 FPGA (xcku040).
+# There is a SCANSTA112SM JTAG router on the board which is configured to
+# automatically add devices to the JTAG svcan chain when they are added.
+# Sayma AMC is usually combined with Sayma RTM (rear transition module)
+# which features an Artix 7 FPGA.
+
+adapter driver ftdi
+ftdi device_desc "Quad RS232-HS"
+ftdi vid_pid 0x0403 0x6011
+ftdi channel 0
+# Use this to distinguish multiple boards by topology
+#adapter usb location 5:1
+# sampling on falling edge generally seems to work and accelerates things but
+# is not fully tested
+#ftdi tdo_sample_edge falling
+# EN_USB_JTAG on ADBUS7: out, high
+# USB_nTRST on ADBUS4: out, high, but R46 is DNP
+ftdi layout_init 0x0098 0x008b
+#ftdi layout_signal EN_USB -data 0x0080
+#ftdi layout_signal nTRST -data 0x0010
+reset_config none
+
+adapter speed 5000
+
+transport select jtag
+
+# Add the RTM Artix to the chain. Note that this changes the PLD numbering.
+# Unfortunately openocd TAPs can't be disabled after they have been added and
+# before `init`.
+#source [find cpld/xilinx-xc7.cfg]
+
+set CHIP XCKU040
+source [find cpld/xilinx-xcu.cfg]
+
+set XILINX_USER1 0x02
+set XILINX_USER2 0x03
+set JTAGSPI_IR $XILINX_USER1
+source [find cpld/jtagspi.cfg]
+flash bank xcu.spi1 jtagspi 0 0 0 0 xcu.proxy $XILINX_USER2
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sheevaplug.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sheevaplug.cfg
new file mode 100644
index 0000000..734fab6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sheevaplug.cfg
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell SheevaPlug
+
+source [find interface/ftdi/sheevaplug.cfg]
+source [find target/feroceon.cfg]
+
+adapter speed 2000
+
+$_TARGETNAME configure \
+	-work-area-phys 0x10000000 \
+	-work-area-size 65536 \
+	-work-area-backup 0
+
+arm7_9 dcc_downloads enable
+
+# this assumes the hardware default peripherals location before u-Boot moves it
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME orion 0 0xd8000000
+
+proc sheevaplug_init { } {
+
+	# We need to assert DBGRQ while holding nSRST down.
+	# However DBGACK will be set only when nSRST is released.
+	# Furthermore, the JTAG interface doesn't respond at all when
+	# the CPU is in the WFI (wait for interrupts) state, so it is
+	# possible that initial tap examination failed.  So let's
+	# re-examine the target again here when nSRST is asserted which
+	# should then succeed.
+	adapter assert srst
+	feroceon.cpu arp_examine
+	halt 0
+	adapter deassert srst
+	wait_halt
+
+	arm mcr 15 0 0 1 0 0x00052078
+
+	mww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register
+	mww 0xD0001404 0x39543000 ;#  Dunit Control Low Register
+	mww 0xD0001408 0x22125451 ;#  DDR SDRAM Timing (Low) Register
+	mww 0xD000140C 0x00000833 ;#  DDR SDRAM Timing (High) Register
+	mww 0xD0001410 0x000000CC ;#  DDR SDRAM Address Control Register
+	mww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register
+	mww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register
+	mww 0xD000141C 0x00000C52 ;#  DDR SDRAM Mode Register
+	mww 0xD0001420 0x00000042 ;#  DDR SDRAM Extended Mode Register
+	mww 0xD0001424 0x0000F17F ;#  Dunit Control High Register
+	mww 0xD0001428 0x00085520 ;#  Dunit Control High Register
+	mww 0xD000147c 0x00008552 ;#  Dunit Control High Register
+	mww 0xD0001504 0x0FFFFFF1 ;#  CS0n Size Register
+	mww 0xD0001508 0x10000000 ;#  CS1n Base Register
+	mww 0xD000150C 0x0FFFFFF5 ;#  CS1n Size Register
+	mww 0xD0001514 0x00000000 ;#  CS2n Size Register
+	mww 0xD000151C 0x00000000 ;#  CS3n Size Register
+	mww 0xD0001494 0x003C0000 ;#  DDR2 SDRAM ODT Control (Low) Register
+	mww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister
+	mww 0xD000149C 0x0000F80F ;#  DDR2 Dunit ODT Control Register
+	mww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register
+	mww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+
+	mww 0xD0010000 0x01111111 ;#  MPP  0 to 7
+	mww 0xD0010004 0x11113322 ;#  MPP  8 to 15
+	mww 0xD0010008 0x00001111 ;#  MPP 16 to 23
+
+	mww 0xD0010418 0x003E07CF ;#  NAND Read Parameters REgister
+	mww 0xD001041C 0x000F0F0F ;#  NAND Write Parameters Register
+	mww 0xD0010470 0x01C7D943 ;#  NAND Flash Control Register
+
+}
+
+proc sheevaplug_reflash_uboot { } {
+
+	# reflash the u-Boot binary and reboot into it
+	sheevaplug_init
+	nand probe 0
+	nand erase 0 0x0 0xa0000
+	nand write 0 uboot.bin 0 oob_softecc_kw
+	resume
+
+}
+
+proc sheevaplug_reflash_uboot_env { } {
+
+	# reflash the u-Boot environment variables area
+	sheevaplug_init
+	nand probe 0
+	nand erase 0 0xa0000 0x40000
+	nand write 0 uboot-env.bin 0xa0000 oob_softecc_kw
+	resume
+
+}
+
+proc sheevaplug_load_uboot { } {
+
+	# load u-Boot into RAM and execute it
+	sheevaplug_init
+	load_image uboot.elf
+	verify_image uboot.elf
+	resume 0x00600000
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e31arty-cjtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e31arty-cjtag.cfg
new file mode 100644
index 0000000..58ba23a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e31arty-cjtag.cfg
@@ -0,0 +1,23 @@
+#
+# Be sure you include the speed and interface before this file
+# Example:
+# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty-cjtag.cfg"
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
+
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+  oscan1_ftdi_set_signal nSRST 0
+  oscan1_ftdi_set_signal nSRST z
+}
+halt
+flash protect 0 64 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e31arty-onboard-ftdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e31arty-onboard-ftdi.cfg
new file mode 100644
index 0000000..3d40cfa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e31arty-onboard-ftdi.cfg
@@ -0,0 +1,25 @@
+#
+# Be sure you include the speed and interface before this file
+# Example:
+# -c "adapter_khz 5000" -f "interface/ftdi/arty-onboard-ftdi.cfg" -f "board/sifive-e31arty-onboard-ftdi.cfg"
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 6; # -expected-id 0x0362d093
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+riscv use_bscan_tunnel 5
+
+# Uncomment if hardware has flash
+# flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+}
+halt
+# Uncomment if hardware has flash
+# flash protect 0 64 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e31arty.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e31arty.cfg
new file mode 100644
index 0000000..b3e980f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e31arty.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Be sure you include the speed and interface before this file
+# Example:
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg"
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+  ftdi set_signal nSRST 0
+  ftdi set_signal nSRST z
+}
+halt
+flash protect 0 64 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e51arty.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e51arty.cfg
new file mode 100644
index 0000000..3133c39
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-e51arty.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Be sure you include the speed and interface before this file
+# Example:
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg"
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+  ftdi set_signal nSRST 0
+  ftdi set_signal nSRST z
+}
+halt
+flash protect 0 64 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-hifive1-revb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-hifive1-revb.cfg
new file mode 100644
index 0000000..7fcab0c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-hifive1-revb.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed 4000
+
+adapter driver jlink
+transport select jtag
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 0
+
+riscv set_enable_virt2phys off
+riscv set_enable_virtual off
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME.0
+
+init
+
+jlink jtag 3
+
+halt
+flash protect 0 1 last off
+echo "Ready for Remote Connections"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-hifive1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-hifive1.cfg
new file mode 100644
index 0000000..f69dc4f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/sifive-hifive1.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed     10000
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
+
+#Reset Stretcher logic on FE310 is ~1 second long
+#This doesn't apply if you use
+# ftdi set_signal, but still good to document
+#adapter srst delay 1500
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset -- This type of reset is not implemented yet
+if {[ info exists pulse_srst]} {
+  ftdi set_signal nSRST 0
+  ftdi set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}
+halt
+flash protect 0 64 last off
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/smdk6410.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/smdk6410.cfg
new file mode 100644
index 0000000..be61ae9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/smdk6410.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a SMDK6410
+# Processor       : ARM1176
+# Info:   JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+
+source [find target/samsung_s3c6410.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk.cfg
new file mode 100644
index 0000000..56eed93
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.x
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# 5MHz seems to work good with all cores that might happen in 2.x
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk_v1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk_v1.cfg
new file mode 100644
index 0000000..94aab14
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk_v1.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+adapter speed 10000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk_v2.1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk_v2.1.cfg
new file mode 100644
index 0000000..96391df
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk_v2.1.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
+# 20MHz. 7.5 MHz seems to work fine.
+adapter speed 7500
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk_v2.2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk_v2.2.cfg
new file mode 100644
index 0000000..c1f6a72
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_em_sk_v2.2.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2016,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.2
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_hsdk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_hsdk.cfg
new file mode 100644
index 0000000..24022e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_hsdk.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2019, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys DesignWare ARC HSDK Software Development Platform (HS38 cores)
+#
+
+source [find interface/ftdi/snps_sdp.cfg]
+adapter speed 10000
+
+# ARCs supports only JTAG.
+transport select jtag
+
+# Configure SoC
+source [find target/snps_hsdk.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_hsdk_4xd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_hsdk_4xd.cfg
new file mode 100644
index 0000000..5901533
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/snps_hsdk_4xd.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Copyright (C) 2023 Synopsys, Inc.
+# Artemiy Volkov 
+
+# Adapted from tcl/board/snps_hsdk.cfg.
+
+#
+# Synopsys DesignWare ARC HSDK Software Development Platform (HS47D cores)
+#
+
+source [find interface/ftdi/snps_sdp.cfg]
+adapter speed 10000
+
+# ARCs supports only JTAG.
+transport select jtag
+
+# Configure SoC
+source [find target/snps_hsdk_4xd.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg
new file mode 100644
index 0000000..c22ace8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion SK-FM4-176L-S6E2CC
+#
+
+#
+# FM3 MB9AF312K
+#
+source [find interface/cmsis-dap.cfg]
+
+# There's also an unpopulated 10-pin 0.05" pinout.
+
+#
+# FM4 S6E2CCAJ0A w/ 192 KB SRAM0
+#
+set CHIPNAME s6e2cc
+set CHIPSERIES S6E2CCAJ0A
+set WORKAREASIZE 0x30000
+source [find target/fm4_s6e2cc.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spansion_sk-fm4-u120-9b560.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spansion_sk-fm4-u120-9b560.cfg
new file mode 100644
index 0000000..15477a2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spansion_sk-fm4-u120-9b560.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion SK-FM4-U120-9B560
+#
+
+#
+# FM3 MB9AF312K
+#
+# source [find interface/cmsis-dap.cfg]
+
+#
+# FM4 MB9BF568R w/ 64 KB SRAM0
+#
+set CHIPNAME mb9bf568
+set CHIPSERIES MB9BF568R
+set WORKAREASIZE 0x10000
+source [find target/fm4_mb9bf.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear300evb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear300evb.cfg
new file mode 100644
index 0000000..f2cf596
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear300evb.cfg
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr300 Evaluation board
+# EVALSPEAr300 Rev. 1.0
+# http://www.st.com/spear
+#
+# Date:      2010-11-27
+# Author:    Antonio Borneo 
+
+# The standard board has JTAG SRST not connected.
+# This script targets such boards using quirky code to bypass the issue.
+
+
+source [find mem_helper.tcl]
+source [find target/spear3xx.cfg]
+source [find chip/st/spear/spear3xx_ddr.tcl]
+source [find chip/st/spear/spear3xx.tcl]
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+
+# Serial NOR on SMI CS0. 8Mbyte.
+set _FLASHNAME1 $_CHIPNAME.snor
+flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
+
+if { [info exists BOARD_HAS_SRST] } {
+	# Modified board has SRST on JTAG connector
+	reset_config trst_and_srst separate srst_gates_jtag \
+		trst_push_pull srst_open_drain
+} else {
+	# Standard board has no SRST on JTAG connector
+	reset_config trst_only separate srst_gates_jtag trst_push_pull
+	source [find chip/st/spear/quirk_no_srst.tcl]
+}
+
+$_TARGETNAME configure -event reset-init { spear300evb_init }
+
+proc spear300evb_init {} {
+	reg pc 0xffff0020;	# loop forever
+
+	sp3xx_clock_default
+	sp3xx_common_init
+	sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
+	sp300_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear300evb_mod.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear300evb_mod.cfg
new file mode 100644
index 0000000..4b1d578
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear300evb_mod.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr300 Evaluation board
+# EVALSPEAr300 Rev. 1.0, modified to enable SRST on JTAG connector
+# http://www.st.com/spear
+#
+# List of board modifications to enable SRST, as reported in
+# ST Application Note (FIXME: add reference).
+# - Modifications on the top layer:
+#    1. replace reset chip U4 with a STM6315SDW13F;
+# - Modifications on the bottom layer:
+#    2. add 0 ohm resistor R10. It is located close to JTAG connector.
+#    3. add a 10K ohm pull-up resistor on the reset wire named as
+#       POWERGOOD in the schematic.
+#
+# The easier way to do modification 3, is to use a resistor in package
+# 0603 and solder it between R10 and R54:
+# - one pad soldered with the pad of R54 connected to 3.3V (this
+#   is the pad of R54 far from JTAG connector J4)
+# - the other pad soldered with the nearest pad of R10.
+#
+# Date:      2011-11-18
+# Author:    Antonio Borneo 
+
+
+# Modified boards has SRST on JTAG connector
+set BOARD_HAS_SRST 1
+source [find board/spear300evb.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear310evb20.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear310evb20.cfg
new file mode 100644
index 0000000..c37bd1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear310evb20.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr310 Evaluation board
+# EVALSPEAr310 Rev. 2.0
+# http://www.st.com/spear
+#
+# Date:      2010-08-17
+# Author:    Antonio Borneo 
+
+# The standard board has JTAG SRST not connected.
+# This script targets such boards using quirky code to bypass the issue.
+#
+# Check ST Application Note AN3321 on how to fix SRST on
+# the board, then use the script board/spear310evb20_mod.cfg
+
+
+source [find mem_helper.tcl]
+source [find target/spear3xx.cfg]
+source [find chip/st/spear/spear3xx_ddr.tcl]
+source [find chip/st/spear/spear3xx.tcl]
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+# CFI parallel NOR on EMI CS0. 2x 16bit 8M devices = 16Mbyte.
+set _FLASHNAME0 $_CHIPNAME.pnor
+flash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME
+
+# Serial NOR on SMI CS0. 8Mbyte.
+set _FLASHNAME1 $_CHIPNAME.snor
+flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
+
+if { [info exists BOARD_HAS_SRST] } {
+	# Modified board has SRST on JTAG connector
+	reset_config trst_and_srst separate srst_gates_jtag \
+		trst_push_pull srst_open_drain
+} else {
+	# Standard board has no SRST on JTAG connector
+	reset_config trst_only separate srst_gates_jtag trst_push_pull
+	source [find chip/st/spear/quirk_no_srst.tcl]
+}
+
+$_TARGETNAME configure -event reset-init { spear310evb20_init }
+
+proc spear310evb20_init {} {
+	reg pc 0xffff0020	;# loop forever
+
+	sp3xx_clock_default
+	sp3xx_common_init
+	sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
+	sp310_init
+	sp310_emi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear310evb20_mod.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear310evb20_mod.cfg
new file mode 100644
index 0000000..2c56254
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear310evb20_mod.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr310 Evaluation board
+# EVALSPEAr310 Rev. 2.0, modified to enable SRST on JTAG connector
+# http://www.st.com/spear
+#
+# List of board modifications to enable SRST, as reported in
+# ST Application Note AN3321.
+# - Modifications on the top layer:
+#    1. remove R137 and C57, located near the SMII PHY U18;
+#    2. remove R172 and C75, located near the SMII PHY U19;
+#    3. remove R207 and C90, located near the SMII PHY U20;
+#    4. remove C236, located near the SMII PHY U21;
+#    5. remove U12, located near the JTAG connector;
+#    6. solder together pins 7, 8 and 9 of U12;
+#    7. solder together pins 11, 12, 13, 14, 15, 16, 17 and 18 of U12.
+# - Modifications on the bottom layer:
+#    8. replace reset chip U11 with a STM6315SDW13F;
+#    9. add 0 ohm resistor R329. It is located close to JTAG connector.
+#
+# Date:      2009-10-31
+# Author:    Antonio Borneo 
+
+
+# Modified boards has SRST on JTAG connector
+set BOARD_HAS_SRST 1
+source [find board/spear310evb20.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear320cpu.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear320cpu.cfg
new file mode 100644
index 0000000..df713ea
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear320cpu.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr320 CPU board
+# EVAL_SPEAr320CPU Rev. 2.0
+# http://www.st.com/spear
+#
+# Date:      2011-11-18
+# Author:    Antonio Borneo 
+
+# The standard board has JTAG SRST not connected.
+# This script targets such boards using quirky code to bypass the issue.
+
+
+source [find mem_helper.tcl]
+source [find target/spear3xx.cfg]
+source [find chip/st/spear/spear3xx_ddr.tcl]
+source [find chip/st/spear/spear3xx.tcl]
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+
+# Serial NOR on SMI CS0. 8Mbyte.
+set _FLASHNAME1 $_CHIPNAME.snor
+flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
+
+if { [info exists BOARD_HAS_SRST] } {
+	# Modified board has SRST on JTAG connector
+	reset_config trst_and_srst separate srst_gates_jtag \
+		trst_push_pull srst_open_drain
+} else {
+	# Standard board has no SRST on JTAG connector
+	reset_config trst_only separate srst_gates_jtag trst_push_pull
+	source [find chip/st/spear/quirk_no_srst.tcl]
+}
+
+$_TARGETNAME configure -event reset-init { spear320cpu_init }
+
+if { [info exists DDR_CHIPS] } {
+        set _DDR_CHIPS $DDR_CHIPS
+} else {
+        set _DDR_CHIPS 1
+}
+
+proc spear320cpu_init {} {
+	global _DDR_CHIPS
+	reg pc 0xffff0020;	# loop forever
+
+	sp3xx_clock_default
+	sp3xx_common_init
+	sp3xx_ddr_init "mt47h64m16_3_333_cl5_async" $_DDR_CHIPS
+	sp320_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear320cpu_mod.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear320cpu_mod.cfg
new file mode 100644
index 0000000..d12607d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/spear320cpu_mod.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration for the ST SPEAr320 Evaluation board
+# EVAL_SPEAr320CPU Rev. 2.0, modified to enable SRST on JTAG connector
+# http://www.st.com/spear
+#
+# List of board modifications to enable SRST, as reported in
+# ST Application Note (FIXME: add reference).
+# - Modifications on the bottom layer:
+#    1. replace reset chip U7 with a STM6315SDW13F;
+#    2. add 0 ohm resistor R45. It is located close to JTAG connector.
+#    3. add a 10K ohm pull-up resistor on the reset wire named as
+#       POWERGOOD in the schematic.
+#
+# The easier way to do modification 3, is to use a resistor in package
+# 0603 or 0402 and solder it between R15 and R45:
+# - one pad soldered with the pad of R15 connected to 3.3V (this
+#   is the pad of R15 closer to R45)
+# - the other pad soldered with the nearest pad of R45.
+#
+# Date:      2011-11-18
+# Author:    Antonio Borneo 
+
+
+# Modified boards has SRST on JTAG connector
+set BOARD_HAS_SRST 1
+source [find board/spear320cpu.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_b-l475e-iot01a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_b-l475e-iot01a.cfg
new file mode 100644
index 0000000..3f3db12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_b-l475e-iot01a.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an B-L475E-IOT01A Discovery kit for IoT node with a single STM32L475VGT6 chip.
+# http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
+
+	# PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+
+	# Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+	mmw 0x48001000 0xAAA00000 0x55500000	;# MODER
+	mmw 0x48001008 0xFFF00000 0x00000000	;# OSPEEDR
+	mmw 0x48001024 0xAAAAAA00 0x55555500	;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00160100				;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_8l152r8.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_8l152r8.cfg
new file mode 100644
index 0000000..681b5a2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_8l152r8.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a ST NUCLEO 8L152R8 board with a single STM8L152R8T6 chip.
+# http://www.st.com/en/evaluation-tools/nucleo-8l152r8.html
+
+source [find interface/stlink.cfg]
+
+transport select swim
+
+source [find target/stm8l15xx8.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_8s208rb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_8s208rb.cfg
new file mode 100644
index 0000000..0f6bde2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_8s208rb.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a ST NUCLEO 8S208RB board with a single STM8S208RBT6 chip.
+# https://www.st.com/en/evaluation-tools/nucleo-8s208rb.html
+
+source [find interface/stlink.cfg]
+
+transport select swim
+
+# 128 KiB flash and 2 KiB EEPROM
+set FLASHEND 0x27fff
+set EEPROMEND 0x47ff
+
+source [find target/stm8s.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f0.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f0.cfg
new file mode 100644
index 0000000..00c131f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f0.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for all ST NUCLEO with any STM32F0. Known boards at the moment:
+# STM32F030R8
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997
+# NUCLEO-F072RB
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997
+# STM32F091RC
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260944
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f0x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f103rb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f103rb.cfg
new file mode 100644
index 0000000..892bdda
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f103rb.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO F103RB board with a single STM32F103RBT6 chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259875
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f1x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f3.cfg
new file mode 100644
index 0000000..38f49e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f3.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO F334R8 board with a single STM32F334R8T6 chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260004
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f3x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f4.cfg
new file mode 100644
index 0000000..7617a17
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f4.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for all ST NUCLEO with any STM32F4. Known boards at the moment:
+# STM32F401RET6
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260000
+# STM32F411RET6
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260320
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f7.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f7.cfg
new file mode 100644
index 0000000..41f8b21
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_f7.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32F7 Nucleo development board
+# Known boards: NUCLEO-F746ZG and NUCLEO-F767ZI
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_g0.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_g0.cfg
new file mode 100644
index 0000000..f22a7e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_g0.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for all ST NUCLEO with any STM32G0. Known boards at the moment:
+# NUCLEO-G031K8
+# https://www.st.com/en/evaluation-tools/nucleo-g031k8.html
+# NUCLEO-G070RB
+# https://www.st.com/en/evaluation-tools/nucleo-g070rb.html
+# NUCLEO-G071RB
+# https://www.st.com/en/evaluation-tools/nucleo-g071rb.html
+# NUCLEO-G0B1RE
+# https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32g0x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_g4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_g4.cfg
new file mode 100644
index 0000000..309f7a4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_g4.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for all ST NUCLEO with any STM32G4. Known boards at the moment:
+# NUCLEO-G431KB
+# https://www.st.com/en/evaluation-tools/nucleo-g431kb.html
+# NUCLEO-G431RB
+# https://www.st.com/en/evaluation-tools/nucleo-g431rb.html
+# NUCLEO-G474RE
+# https://www.st.com/en/evaluation-tools/nucleo-g474re.html
+# NUCLEO-G491RE
+# https://www.st.com/en/evaluation-tools/nucleo-g491re.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32g4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_h743zi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_h743zi.cfg
new file mode 100644
index 0000000..be2d42f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_h743zi.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip.
+# http://www.st.com/en/evaluation-tools/nucleo-h743zi.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_h745zi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_h745zi.cfg
new file mode 100644
index 0000000..84865f4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_h745zi.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip.
+
+source [find interface/stlink.cfg]
+transport select dapdirect_swd
+
+# STM32H745xx devices are dual core (Cortex-M7 and Cortex-M4)
+set DUAL_CORE 1
+
+# enable CTI for cross halting both cores
+set USE_CTI 1
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l073rz.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l073rz.cfg
new file mode 100644
index 0000000..317c86e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l073rz.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO-L073RZ board with single STM32L073RZ chip.
+# http://www.st.com/en/evaluation-tools/nucleo-l073rz.html
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x2000
+
+source [find target/stm32l0_dual_bank.cfg]
+
+# There is only system reset line and JTAG/SWD command can be issued when SRST
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l1.cfg
new file mode 100644
index 0000000..d7474d0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l1.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an ST NUCLEO L152RE board with a single STM32L152RET6 chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32l1x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l4.cfg
new file mode 100644
index 0000000..b0a75af
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l4.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Should work with all STM32L4 Nucleo Dev Boards.
+# http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32l4x.cfg]
+
+# use hardware reset
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l5.cfg
new file mode 100644
index 0000000..626914a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_l5.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for STM32L5 Nucleo Dev Boards.
+# http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32l5x.cfg]
+
+# use hardware reset
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_wb55.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_wb55.cfg
new file mode 100644
index 0000000..ab7307c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/st_nucleo_wb55.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration for STM32WB55 Nucleo board (STM32WB55RGV6)
+#
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32wbx.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb007v1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb007v1.cfg
new file mode 100644
index 0000000..69d4585
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb007v1.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an evaluation board with a single BlueNRG-1 chip.
+# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb008v1.html
+set CHIPNAME bluenrg-1
+source [find target/bluenrg-x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb008v1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb008v1.cfg
new file mode 100644
index 0000000..057c0dd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb008v1.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an evaluation board with a single BlueNRG-2 chip.
+# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb007v1.html
+set CHIPNAME bluenrg-2
+source [find target/bluenrg-x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb011v1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb011v1.cfg
new file mode 100644
index 0000000..1163508
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb011v1.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an evaluation board with a single BlueNRG-LP chip.
+set CHIPNAME bluenrg-lp
+source [find target/bluenrg-x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb012v1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb012v1.cfg
new file mode 100644
index 0000000..288cbb2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval-idb012v1.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an evaluation board with a single BlueNRG-LPS chip.
+set CHIPNAME bluenrg-lps
+source [find interface/cmsis-dap.cfg]
+source [find target/bluenrg-x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval_pcc010.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval_pcc010.cfg
new file mode 100644
index 0000000..6e006ba
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/steval_pcc010.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram
+# coming with the STEVAL-PCC010 board
+# http://www.st.com/internet/evalboard/product/251530.jsp
+# or any other board with only a STM32F2x in the JTAG chain
+
+# increase working area to 32KB for faster flash programming
+set WORKAREASIZE 0x8000
+
+source [find target/stm32f2x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm320518_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm320518_eval.cfg
new file mode 100644
index 0000000..04486fc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm320518_eval.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6
+# (64KB) chip.
+# http://www.st.com/internet/evalboard/product/252994.jsp
+#
+
+# increase working area to 8KB
+set WORKAREASIZE 0x2000
+
+# chip name
+set CHIPNAME STM32F051R8T6
+
+source [find target/stm32f0x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm320518_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm320518_eval_stlink.cfg
new file mode 100644
index 0000000..997bb4a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm320518_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6
+# (64KB) chip.
+# http://www.st.com/internet/evalboard/product/252994.jsp
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 8KB
+set WORKAREASIZE 0x2000
+
+# chip name
+set CHIPNAME STM32F051R8T6
+
+source [find target/stm32f0x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32100b_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32100b_eval.cfg
new file mode 100644
index 0000000..ebb5681
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32100b_eval.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32 eval board with a single STM32F100VBT6 chip.
+# http://www.st.com/internet/evalboard/product/247099.jsp
+
+# The chip has only 8KB sram
+set WORKAREASIZE 0x2000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3210b_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3210b_eval.cfg
new file mode 100644
index 0000000..072f542
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3210b_eval.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32 eval board with a single STM32F10x (128KB) chip.
+# http://www.st.com/internet/evalboard/product/176090.jsp
+
+# increase working area to 32KB for faster flash programming
+set WORKAREASIZE 0x8000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3210c_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3210c_eval.cfg
new file mode 100644
index 0000000..ec56f63
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3210c_eval.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32 eval board with a single STM32F107VCT chip.
+# http://www.st.com/internet/evalboard/product/217965.jsp
+
+# increase working area to 32KB for faster flash programming
+set WORKAREASIZE 0x8000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3210e_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3210e_eval.cfg
new file mode 100644
index 0000000..f08e04b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3210e_eval.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32 eval board with a single STM32F103ZET6 chip.
+# http://www.st.com/internet/evalboard/product/204176.jsp
+
+# increase working area to 32KB for faster flash programming
+set WORKAREASIZE 0x8000
+
+source [find target/stm32f1x.cfg]
+
+#
+# configure FSMC Bank 1 (NOR/PSRAM Bank 2) NOR flash
+# M29W128GL70ZA6E
+#
+
+set _FLASHNAME $_CHIPNAME.norflash
+flash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME
+
+proc stm32_enable_fsmc {} {
+
+	echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)"
+
+	# enable gpio (defg) clocks for fsmc
+	# RCC_APB2ENR
+	mww 0x40021018 0x000001E0
+
+	# enable fsmc clock
+	# RCC_AHBENR
+	mww 0x40021014 0x00000114
+
+	# configure gpio to alternate function
+	# GPIOD_CRL
+	mww 0x40011400 0x44BB44BB
+	# GPIOD_CRH
+	mww 0x40011404 0xBBBBBBBB
+
+	# GPIOE_CRL
+	mww 0x40011800 0xBBBBB444
+	# GPIOE_CRH
+	mww 0x40011804 0xBBBBBBBB
+
+	# GPIOF_CRL
+	mww 0x40011C00 0x44BBBBBB
+	# GPIOF_CRH
+	mww 0x40011C04 0xBBBB4444
+
+	# GPIOG_CRL
+	mww 0x40012000 0x44BBBBBB
+	# GPIOG_CRH
+	mww 0x40012004 0x444444B4
+
+	# setup fsmc timings
+	# FSMC_BCR1
+	mww 0xA0000008 0x00001058
+
+	# FSMC_BTR1
+	mww 0xA000000C 0x10000502
+
+	# FSMC_BCR1 - enable fsmc
+	mww 0xA0000008 0x00001059
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32_enable_fsmc
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3220g_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3220g_eval.cfg
new file mode 100644
index 0000000..9782a07
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3220g_eval.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6
+# (128KB) chip.
+# http://www.st.com/internet/evalboard/product/250374.jsp
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F207IGH6
+
+source [find target/stm32f2x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3220g_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3220g_eval_stlink.cfg
new file mode 100644
index 0000000..4233d04
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3220g_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6
+# (128KB) chip.
+# http://www.st.com/internet/evalboard/product/250374.jsp
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F207IGH6
+
+source [find target/stm32f2x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3241g_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3241g_eval.cfg
new file mode 100644
index 0000000..7df373f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3241g_eval.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6
+# (1024KB) chip.
+# http://www.st.com/internet/evalboard/product/252216.jsp
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F417IGH6
+
+source [find target/stm32f4x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3241g_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3241g_eval_stlink.cfg
new file mode 100644
index 0000000..3bccd28
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm3241g_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6
+# (1024KB) chip.
+# http://www.st.com/internet/evalboard/product/252216.jsp
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F417IGH6
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32429i_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32429i_eval.cfg
new file mode 100644
index 0000000..3304ef6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32429i_eval.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6
+# (2048KB) chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F429NIH6
+
+source [find target/stm32f4x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32429i_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32429i_eval_stlink.cfg
new file mode 100644
index 0000000..7d04aa7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32429i_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6
+# (2048KB) chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F429NIH6
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32439i_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32439i_eval.cfg
new file mode 100644
index 0000000..c29d4de
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32439i_eval.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6
+# (2048KB) chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F439NIH6
+
+source [find target/stm32f4x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32439i_eval_stlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32439i_eval_stlink.cfg
new file mode 100644
index 0000000..b9ea084
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32439i_eval_stlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6
+# (2048KB) chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094
+#
+# This is for using the onboard STLINK/V2
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F439NIH6
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm327x6g_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm327x6g_eval.cfg
new file mode 100644
index 0000000..03fe949
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm327x6g_eval.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM327[4|5]6G-EVAL: This is for the STM32F7 eval boards.
+# STM32746G-EVAL
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261639
+# STM32756G-EVAL
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261640
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f0discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f0discovery.cfg
new file mode 100644
index 0000000..398ecc1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f0discovery.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F0 discovery board with a single STM32F051R8T6 chip.
+# http://www.st.com/internet/evalboard/product/253215.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x2000
+source [find target/stm32f0x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f103c8_blue_pill.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f103c8_blue_pill.cfg
new file mode 100644
index 0000000..0b84f72
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f103c8_blue_pill.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32F103C8 "Blue Pill"
+
+# NOTE:
+# There is a fair bit of confusion about whether the "Blue Pill" has 128kB or 64kB flash size.
+# The most likely cause is that there exist a -C8 and a -CB variant of the STM32F103, where
+# the C8 has 64kB, the CB has 128kB as per specification. "Blue Pill" boards are manufactured
+# by a lot of different vendors, some may actually use the CB variant but from a cursory look
+# it very hard to tell them apart ("C8" and "CB" look very similar). Nevertheless, people have
+# tried using the full 128kB of flash on the C8 and found it to be working. Hence this board file
+# overrides the internal size detection. Be aware though that you may be using you particular
+# board outside of its specification. If in doubt, comment the following line.
+set FLASH_SIZE 0x20000
+
+source [find target/stm32f1x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f334discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f334discovery.cfg
new file mode 100644
index 0000000..3ff2968
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f334discovery.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F334 discovery board with a single STM32F334C8T6 chip.
+# As it is one of the few boards with stlink V.2-1, we source the corresponding
+# nucleo file.
+# http://www.st.com/web/en/catalog/tools/FM116/SC959/SS1532/LN1848/PF260318
+
+source [find board/st_nucleo_f3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f3discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f3discovery.cfg
new file mode 100644
index 0000000..73c349a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f3discovery.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F3 discovery board with a single STM32F303VCT6 chip.
+# http://www.st.com/internet/evalboard/product/254044.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f3x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f412g-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f412g-disco.cfg
new file mode 100644
index 0000000..30a9537
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f412g-disco.cfg
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F412G discovery board with a single STM32F412ZGT6 chip.
+# http://www.st.com/en/evaluation-tools/32f412gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000000FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PG06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
+
+	# PB02:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V, PG06:AF10:V
+
+	# Port B: PB02:AF09:V
+	mmw 0x40020400 0x00000020 0x00000010	;# MODER
+	mmw 0x40020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x00000900 0x00000600	;# AFRL
+
+	# Port F: PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x40021400 0x000AA000 0x00055000	;# MODER
+	mmw 0x40021408 0x000FF000 0x00000000	;# OSPEEDR
+	mmw 0x40021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x40021424 0x000000AA 0x00000055	;# AFRH
+
+	# Port G: PG06:AF10:V
+	mmw 0x40021800 0x00002000 0x00001000	;# MODER
+	mmw 0x40021808 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x40021820 0x0A000000 0x05000000	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000003				;# 3 WS for 96 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24001808				;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
+	mww 0x40023808 0x00001000				;# APB1: /2, APB2: /1
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f413h-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f413h-disco.cfg
new file mode 100644
index 0000000..c82d0d4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f413h-disco.cfg
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F413H discovery board with a single STM32F413ZHT6 chip.
+# http://www.st.com/en/evaluation-tools/32f413hdiscovery.html
+
+#
+# Untested!!!
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000000FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PB02: CLK, PD13: BK1_IO3, PE02: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
+
+	# PB02:AF09:V, PD13:AF09:V, PE02:AF09:V, PF09:AF10:V, PF08:AF10:V, PG06:AF10:V
+
+	# Port B: PB02:AF09:V
+	mmw 0x40020400 0x00000020 0x00000010	;# MODER
+	mmw 0x40020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x00000900 0x00000600	;# AFRL
+
+	# Port D: PD13:AF09:V
+	mmw 0x40020C00 0x08000000 0x04000000	;# MODER
+	mmw 0x40020C08 0x0C000000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00900000 0x00600000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	# Port F: PF09:AF10:V, PF08:AF10:V
+	mmw 0x40021400 0x000A0000 0x00050000	;# MODER
+	mmw 0x40021408 0x000F0000 0x00000000	;# OSPEEDR
+	mmw 0x40021424 0x000000AA 0x00000055	;# AFRH
+
+	# Port G: PG06:AF10:V
+	mmw 0x40021800 0x00002000 0x00001000	;# MODER
+	mmw 0x40021808 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x40021820 0x0A000000 0x05000000	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000003				;# 3 WS for 96 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24001808				;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
+	mww 0x40023808 0x00001000				;# APB1: /2, APB2: /1
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f429disc1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f429disc1.cfg
new file mode 100644
index 0000000..0a8e7ef
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f429disc1.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is an STM32F429 discovery board with a single STM32F429ZI chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
+#
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f429discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f429discovery.cfg
new file mode 100644
index 0000000..865602a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f429discovery.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is an STM32F429 discovery board with a single STM32F429ZI chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
+#
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f469discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f469discovery.cfg
new file mode 100644
index 0000000..c9acbbb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f469discovery.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is an STM32F469 discovery board with a single STM32F469NI chip.
+# http://www.st.com/web/catalog/tools/FM116/CL1620/SC959/SS1532/LN1848/PF262395
+#
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f469i-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f469i-disco.cfg
new file mode 100644
index 0000000..63c42c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f469i-disco.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F469I discovery board with a single STM32F469NIH6 chip.
+# http://www.st.com/en/evaluation-tools/32f469idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PF10: CLK, PB06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
+
+	# PB06:AF10:V, PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
+
+	# Port B: PB06:AF10:V
+	mmw 0x40020400 0x00002000 0x00001000	;# MODER
+	mmw 0x40020408 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000000 0x05000000	;# AFRL
+
+	# Port F: PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x40021400 0x002AA000 0x00155000	;# MODER
+	mmw 0x40021408 0x003FF000 0x00000000	;# OSPEEDR
+	mmw 0x40021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x40021424 0x000009AA 0x00000655	;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000005				;# 5 WS for 160 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24002808				;# 160 MHz: HSI, PLLM=8, PLLN=160, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f4discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f4discovery.cfg
new file mode 100644
index 0000000..d96e2db
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f4discovery.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F4 discovery board with a single STM32F407VGT6 chip.
+# http://www.st.com/internet/evalboard/product/252419.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 64KB
+set WORKAREASIZE 0x10000
+
+source [find target/stm32f4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f723e-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f723e-disco.cfg
new file mode 100644
index 0000000..0207956
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f723e-disco.cfg
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F723E discovery board with a single STM32F723IEK6 chip.
+# http://www.st.com/en/evaluation-tools/32f723ediscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
+
+	# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
+
+	# Port B: PB06:AF10:V, PB02:AF09:V
+	mmw 0x40020400 0x00002020 0x00001010	;# MODER
+	mmw 0x40020408 0x00003030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000900 0x05000600	;# AFRL
+
+	# Port C: PC10:AF09:V, PC09:AF09:V
+	mmw 0x40020800 0x00280000 0x00140000	;# MODER
+	mmw 0x40020808 0x003C0000 0x00000000	;# OSPEEDR
+	mmw 0x40020824 0x00000990 0x00000660	;# AFRH
+
+	# Port D: PD13:AF09:V
+	mmw 0x40020C00 0x08000000 0x04000000	;# MODER
+	mmw 0x40020C08 0x0C000000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00900000 0x00600000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00190100				;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 4-byte addresses
+	mww 0xA0001014 0x0D003513				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000006				;# 6 WS for 192 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24003008				;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f746g-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f746g-disco.cfg
new file mode 100644
index 0000000..75ff4ec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f746g-disco.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F746G discovery board with a single STM32F746NGH6 chip.
+# http://www.st.com/en/evaluation-tools/32f746gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PD12: BK1_IO1, PD11: BK1_IO0
+
+	# PB06:AF10:V, PB02:AF09:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PE02:AF09:V
+
+	# Port B: PB06:AF10:V, PB02:AF09:V
+	mmw 0x40020400 0x00002020 0x00001010	;# MODER
+	mmw 0x40020408 0x00003030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000900 0x05000600	;# AFRL
+
+	# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V
+	mmw 0x40020C00 0x0A800000 0x05400000	;# MODER
+	mmw 0x40020C08 0x0FC00000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00999000 0x00666000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000006				;# 6 WS for 192 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24003008				;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f769i-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f769i-disco.cfg
new file mode 100644
index 0000000..cd6383a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f769i-disco.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F769I discovery board with a single STM32F769NIH6 chip.
+# http://www.st.com/en/evaluation-tools/32f769idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
+
+	# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
+
+	# Port B: PB06:AF10:V, PB02:AF09:V
+	mmw 0x40020400 0x00002020 0x00001010	;# MODER
+	mmw 0x40020408 0x00003030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000900 0x05000600	;# AFRL
+
+	# Port C: PC10:AF09:V, PC09:AF09:V
+	mmw 0x40020800 0x00280000 0x00140000	;# MODER
+	mmw 0x40020808 0x003C0000 0x00000000	;# OSPEEDR
+	mmw 0x40020824 0x00000990 0x00000660	;# AFRH
+
+	# Port D: PD13:AF09:V
+	mmw 0x40020C00 0x08000000 0x04000000	;# MODER
+	mmw 0x40020C08 0x0C000000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00900000 0x00600000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00190100				;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# exit qpi mode
+	mww 0xA0001014 0x000033f5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+
+	# 1-line memory-mapped read mode with 4-byte addresses
+	mww 0xA0001014 0x0D003513				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+
+	# 4-line qpi mode
+	mww 0xA0001014 0x00003135				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=EQIO
+
+	# 4-line memory-mapped read mode with 4-byte addresses
+	mww 0xA0001014 0x0F283FEC				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0xA, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=4READ4B
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000006				;# 6 WS for 192 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24003008				;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f7discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f7discovery.cfg
new file mode 100644
index 0000000..6fd6c64
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32f7discovery.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32F7 discovery board with a single STM32F756NGH6 chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641
+
+# This is for using the onboard STLINK/V2-1
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+source [find target/stm32f7x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h735g-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h735g-disco.cfg
new file mode 100644
index 0000000..327a364
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h735g-disco.cfg
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h735g-dk with a single STM32H735IGK6 chip.
+# https://www.st.com/en/evaluation-tools/stm32h735g-dk.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h735igk6
+
+# enable stmqspi
+if {![info exists OCTOSPI1]} {
+	set OCTOSPI1 1
+	set OCTOSPI2 0
+}
+
+source [find target/stm32h7x.cfg]
+
+reset_config srst_only
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x58024540 0x000006FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
+	sleep 1									;# Wait for clock startup
+
+	mww 0x5200B404 0x03010111				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
+	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2
+
+	# PG06: OCSPI1_NCS, PF10: OCSPI1_CLK, PB02: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PD05: OCSPI1_IO5,
+	# PD04: OCSPI1_IO4, PD13: OCSPI1_IO3, PE02: OCSPI1_IO2, PD12: OCSPI1_IO1, PD11: OCSPI1_IO0
+
+	# PB02:AF10:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V
+	# PD04:AF10:V, PE02:AF09:V, PF10:AF09:V, PG09:AF09:V, PG06:AF10:V
+	# Port B: PB02:AF10:V
+	mmw 0x58020400 0x00000020 0x00000010	;# MODER
+	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x5802040C 0x00000000 0x00000030	;# PUPDR
+	mmw 0x58020420 0x00000A00 0x00000500	;# AFRL
+	# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
+	mmw 0x58020C00 0x0A808A00 0x05404500	;# MODER
+	mmw 0x58020C08 0x0FC0CF00 0x00000000	;# OSPEEDR
+	mmw 0x58020C0C 0x00000000 0x0FC0CF00	;# PUPDR
+	mmw 0x58020C20 0xA0AA0000 0x50550000	;# AFRL
+	mmw 0x58020C24 0x00999000 0x00666000	;# AFRH
+	# Port E: PE02:AF09:V
+	mmw 0x58021000 0x00000020 0x00000010	;# MODER
+	mmw 0x58021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x5802100C 0x00000000 0x00000030	;# PUPDR
+	mmw 0x58021020 0x00000900 0x00000600	;# AFRL
+	# Port F: PF10:AF09:V
+	mmw 0x58021400 0x00200000 0x00100000	;# MODER
+	mmw 0x58021408 0x00300000 0x00000000	;# OSPEEDR
+	mmw 0x5802140C 0x00000000 0x00300000	;# PUPDR
+	mmw 0x58021424 0x00000900 0x00000600	;# AFRH
+	# Port G: PG09:AF09:V, PG06:AF10:V
+	mmw 0x58021800 0x00082000 0x00041000	;# MODER
+	mmw 0x58021808 0x000C3000 0x00000000	;# OSPEEDR
+	mmw 0x5802180C 0x00000000 0x000C3000	;# PUPDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x00000090 0x00000060	;# AFRH
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0x52005130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0x52005008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0x5200500C 0x00000005				;# OCTOSPI_DCR2: PRESCALER=5
+
+	mww 0x52005108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0x52005100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0x52005110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0x52005108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0x52005100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0x52005110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global OCTOSPI1
+	global OCTOSPI2
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $OCTOSPI1 } {
+		octospi_init 1
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h745i-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h745i-disco.cfg
new file mode 100644
index 0000000..9da1dae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h745i-disco.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h745i-disco with a single STM32H745XIH6 chip.
+# www.st.com/en/product/stm32h745i-disco.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h745xih6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+	set QUADSPI 1
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
+
+source [find board/stm32h7x_dual_qspi.cfg]
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global QUADSPI
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $QUADSPI } {
+		qspi_init 1
+	}
+}
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h747i-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h747i-disco.cfg
new file mode 100644
index 0000000..7f8eda8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h747i-disco.cfg
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h747i-disco with a single STM32H747XIH6 chip.
+# www.st.com/en/product/stm32h747i-disco.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h747xih6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+	set QUADSPI 1
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
+
+# QUADSPI initialization
+# qpi: 4-line mode
+proc qspi_init { qpi } {
+	global a
+	mmw 0x580244E0 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x580244D4 0x00004000 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PB02: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
+	# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
+
+	# PB02:AF09:V, PD11:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
+	# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
+
+	# Port B: PB02:AF09:V
+	mmw 0x58020400 0x00000020 0x00000010	;# MODER
+	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x58020420 0x00000900 0x00000600	;# AFRL
+	# Port D: PD11:AF09:V
+	mmw 0x58020C00 0x00800000 0x00400000	;# MODER
+	mmw 0x58020C08 0x00C00000 0x00000000	;# OSPEEDR
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x58021400 0x0008A000 0x00045000	;# MODER
+	mmw 0x58021408 0x000CF000 0x00000000	;# OSPEEDR
+	mmw 0x58021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x58021424 0x000000A0 0x00000050	;# AFRH
+	# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
+	mmw 0x58021800 0x20082000 0x10041000	;# MODER
+	mmw 0x58021808 0x200C2000 0x10001000	;# OSPEEDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x09000090 0x06000060	;# AFRH
+	# Port H: PH03:AF09:V, PH02:AF09:V
+	mmw 0x58021C00 0x000000A0 0x00000050	;# MODER
+	mmw 0x58021C08 0x000000F0 0x00000000	;# OSPEEDR
+	mmw 0x58021C20 0x00009900 0x00006600	;# AFRL
+
+	# correct FSIZE is 0x1A, however, this causes trouble when
+	# reading the last bytes at end of bank in *memory mapped* mode
+
+	# for dual flash mode 2 * mt25ql512
+	mww 0x52005000 0x05500058				;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
+	mww 0x52005004 0x001A0200				;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
+
+	mww 0x52005030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
+	mmw 0x52005000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# Exit QPI mode
+	mmw 0x52005000 0x00000002 0				;# QUADSPI_CR: ABORT=1
+	mww 0x52005014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
+	sleep 1
+
+	if { $qpi == 1 } {
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Configure dummy clocks via volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000181			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
+		mwh 0x52005020 0xABAB				;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
+		sleep 1
+
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Enable QPI mode via enhanced volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000161			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
+		mwh 0x52005020 0x3F3F				;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
+		sleep 1
+
+		# Enter QPI mode
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000135			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
+		sleep 1
+
+		# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0F283FEC			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
+	} else {
+		# memory-mapped read mode with 4-byte addresses
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0D003513			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+	}
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global QUADSPI
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $QUADSPI } {
+		qspi_init 1
+	}
+}
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h750b-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h750b-disco.cfg
new file mode 100644
index 0000000..8b254f2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h750b-disco.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h750b-dk with a single STM32H750XBH6 chip.
+# www.st.com/en/product/stm32h750b-dk.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h750xbh6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+	set QUADSPI 1
+}
+
+source [find target/stm32h7x.cfg]
+
+reset_config srst_only
+
+source [find board/stm32h7x_dual_qspi.cfg]
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global QUADSPI
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $QUADSPI } {
+		qspi_init 1
+	}
+}
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h7b3i-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h7b3i-disco.cfg
new file mode 100644
index 0000000..df0d0a6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h7b3i-disco.cfg
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a stm32h7b3i-dk with a single STM32H7B3LIH6Q chip.
+# https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set CHIPNAME stm32h7b3lih6q
+
+# enable stmqspi
+if {![info exists OCTOSPI1]} {
+	set OCTOSPI1 1
+	set OCTOSPI2 0
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x58024540 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
+	sleep 1									;# Wait for clock startup
+
+	mww 0x5200B404 0x03010111				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
+	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2
+
+	# PG06: OCSPI1_NCS, PB02: OCSPI1_CLK, PC05: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PH03: OCSPI1_IO5,
+	# PC01: OCSPI1_IO4, PF06: OCSPI1_IO3, PF07: OCSPI1_IO2, PF09: OCSPI1_IO1, PD11: OCSPI1_IO0
+
+	# PB02:AF09:V, PC05:AF10:V, PC01:AF10:V, PD11:AF09:V, PD07:AF10:V, PF09:AF10:V
+	# PF07:AF10:V, PF06:AF10:V, PG09:AF09:V, PG06:AF10:V, PH03:AF09:V
+	# Port B: PB02:AF09:V
+	mmw 0x58020400 0x00000020 0x00000010	;# MODER
+	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x5802040C 0x00000000 0x00000030	;# PUPDR
+	mmw 0x58020420 0x00000900 0x00000600	;# AFRL
+	# Port C: PC05:AF10:V, PC01:AF10:V
+	mmw 0x58020800 0x00000808 0x00000404	;# MODER
+	mmw 0x58020808 0x00000C0C 0x00000000	;# OSPEEDR
+	mmw 0x5802080C 0x00000000 0x00000C0C	;# PUPDR
+	mmw 0x58020820 0x00A000A0 0x00500050	;# AFRL
+	# Port D: PD11:AF09:V, PD07:AF10:V
+	mmw 0x58020C00 0x00808000 0x00404000	;# MODER
+	mmw 0x58020C08 0x00C0C000 0x00000000	;# OSPEEDR
+	mmw 0x58020C0C 0x00000000 0x00C0C000	;# PUPDR
+	mmw 0x58020C20 0xA0000000 0x50000000	;# AFRL
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF09:AF10:V, PF07:AF10:V, PF06:AF10:V
+	mmw 0x58021400 0x0008A000 0x00045000	;# MODER
+	mmw 0x58021408 0x000CF000 0x00000000	;# OSPEEDR
+	mmw 0x5802140C 0x00000000 0x000CF000	;# PUPDR
+	mmw 0x58021420 0xAA000000 0x55000000	;# AFRL
+	mmw 0x58021424 0x000000A0 0x00000050	;# AFRH
+	# Port G: PG09:AF09:V, PG06:AF10:V
+	mmw 0x58021800 0x00082000 0x00041000	;# MODER
+	mmw 0x58021808 0x000C3000 0x00000000	;# OSPEEDR
+	mmw 0x5802180C 0x00000000 0x000C3000	;# PUPDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x00000090 0x00000060	;# AFRH
+	# Port H: PH03:AF09:V
+	mmw 0x58021C00 0x00000080 0x00000040	;# MODER
+	mmw 0x58021C08 0x000000C0 0x00000000	;# OSPEEDR
+	mmw 0x58021C0C 0x00000000 0x000000C0	;# PUPDR
+	mmw 0x58021C20 0x00009000 0x00006000	;# AFRL
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0x52005130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0x52005008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0x5200500C 0x00000005				;# OCTOSPI_DCR2: PRESCALER=5
+
+	mww 0x52005108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0x52005100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0x52005110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0x52005108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0x52005100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0x52005110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global OCTOSPI1
+	global OCTOSPI2
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $OCTOSPI1 } {
+		octospi_init 1
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h7x3i_eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h7x3i_eval.cfg
new file mode 100644
index 0000000..508f10d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h7x3i_eval.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STM32H7[4|5]3I-EVAL: this is for the H7 eval boards.
+# This is an ST EVAL-H743XI board with single STM32H743XI chip.
+# http://www.st.com/en/evaluation-tools/stm32h743i-eval.html
+# This is an ST EVAL-H753XI board with single STM32H753XI chip.
+# http://www.st.com/en/evaluation-tools/stm32h753i-eval.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h7x_dual_qspi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h7x_dual_qspi.cfg
new file mode 100644
index 0000000..0349fad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32h7x_dual_qspi.cfg
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# stm32h754i-disco and stm32h750b-dk dual quad qspi.
+
+# QUADSPI initialization
+# qpi: 4-line mode
+proc qspi_init { qpi } {
+	global a
+	mmw 0x580244E0 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x580244D4 0x00004000 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PF10: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
+	# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
+
+	# PD11:AF09:V, PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
+	# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
+
+	# Port D: PD11:AF09:V
+	mmw 0x58020C00 0x00800000 0x00400000	;# MODER
+	mmw 0x58020C08 0x00C00000 0x00000000	;# OSPEEDR
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x58021400 0x0028A000 0x00145000	;# MODER
+	mmw 0x58021408 0x003CF000 0x00000000	;# OSPEEDR
+	mmw 0x58021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x58021424 0x000009A0 0x00000650	;# AFRH
+	# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
+	mmw 0x58021800 0x20082000 0x10041000	;# MODER
+	mmw 0x58021808 0x200C2000 0x10001000	;# OSPEEDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x09000090 0x06000060	;# AFRH
+	# Port H: PH03:AF09:V, PH02:AF09:V
+	mmw 0x58021C00 0x000000A0 0x00000050	;# MODER
+	mmw 0x58021C08 0x000000F0 0x00000000	;# OSPEEDR
+	mmw 0x58021C20 0x00009900 0x00006600	;# AFRL
+
+	# correct FSIZE is 0x1A, however, this causes trouble when
+	# reading the last bytes at end of bank in *memory mapped* mode
+
+	# for dual flash mode 2 * mt25ql512
+	mww 0x52005000 0x05500058				;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
+	mww 0x52005004 0x001A0200				;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
+
+	mww 0x52005030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
+	mmw 0x52005000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# Exit QPI mode
+	mmw 0x52005000 0x00000002 0				;# QUADSPI_CR: ABORT=1
+	mww 0x52005014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
+	sleep 1
+
+	if { $qpi == 1 } {
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Configure dummy clocks via volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000181			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
+		mwh 0x52005020 0xABAB				;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
+		sleep 1
+
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Enable QPI mode via enhanced volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000161			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
+		mwh 0x52005020 0x3F3F				;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
+		sleep 1
+
+		# Enter QPI mode
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000135			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
+		sleep 1
+
+		# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0F283FEC			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
+	} else {
+		# memory-mapped read mode with 4-byte addresses
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0D003513			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l0discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l0discovery.cfg
new file mode 100644
index 0000000..59aed34
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l0discovery.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32L053 discovery board with a single STM32L053 chip.
+# http://www.st.com/web/en/catalog/tools/PF260319
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x2000
+source [find target/stm32l0.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l476g-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l476g-disco.cfg
new file mode 100644
index 0000000..fe33ffe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l476g-disco.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32L476G discovery board with a single STM32L476VGT6 chip.
+# http://www.st.com/en/evaluation-tools/32l476gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
+
+	# PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+
+	# Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+	mmw 0x48001000 0xAAA00000 0x55500000    ;# MODER
+	mmw 0x48001008 0xFFF00000 0x00000000    ;# OSPEEDR
+	mmw 0x48001024 0xAAAAAA00 0x55555500    ;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l496g-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l496g-disco.cfg
new file mode 100644
index 0000000..823fa6e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l496g-disco.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32L496G discovery board with a single STM32L496AGI6 chip.
+# http://www.st.com/en/evaluation-tools/32l496gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB11: BK1_NCS, PA03: CLK, PA06: BK1_IO3, PA07: BK1_IO2, PB00: BK1_IO1, PB01: BK1_IO0
+
+	# PA07:AF10:V, PA06:AF10:V, PA03:AF10:V, PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
+
+	# Port A: PA07:AF10:V, PA06:AF10:V, PA03:AF10:V
+	mmw 0x48000000 0x0000A080 0x00005040    ;# MODER
+	mmw 0x48000008 0x0000F0C0 0x00000000    ;# OSPEEDR
+	mmw 0x48000020 0xAA00A000 0x55005000    ;# AFRL
+
+	# Port B: PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
+	mmw 0x48000400 0x0080000A 0x00400005    ;# MODER
+	mmw 0x48000408 0x00C0000F 0x00000000    ;# OSPEEDR
+	mmw 0x48000420 0x000000AA 0x00000055    ;# AFRL
+	mmw 0x48000424 0x0000A000 0x00005000    ;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00160100				;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l4discovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l4discovery.cfg
new file mode 100644
index 0000000..64a456b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l4discovery.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Explicitly for the STM32L476 discovery board:
+# http://www.st.com/web/en/catalog/tools/PF261635
+# but perfectly functional for any other STM32L4 board connected via
+# an stlink-v2-1 interface.
+# This is for STM32L4 boards that are connected via stlink-v2-1.
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32l4x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l4p5g-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l4p5g-disco.cfg
new file mode 100644
index 0000000..33bb9a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l4p5g-disco.cfg
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a STM32L4P5G discovery board with a single STM32L4R9AGI6 chip.
+# http://www.st.com/en/evaluation-tools/stm32l4p5g-dk.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set OCTOSPI1 1
+set OCTOSPI2 0
+
+source [find target/stm32l4x.cfg]
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x4002104C 0x001001FF 0				;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000300 0				;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
+	mmw 0x40021058 0x10000000 0				;# RCC_APB1ENR1 |= PWREN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	mmw 0x40007004 0x00000200 0				;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
+
+	mww 0x50061C04 0x07050333				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI2
+	mww 0x50061C08 0x03010111				;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
+
+	# PE11: P1_NCS, PE10: P1_CLK, PG06: P1_DQS, PD07: P1_IO7, PC03: P1_IO6, PD05: P1_IO5
+	# PD04: P1_IO4, PA06: P1_IO3, PA07: P1_IO2, PE13: P1_IO1, PE11: P1_IO0
+
+	# PA07:AF10:V, PA06:AF10:V, PC03:AF10:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
+	# PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V, PG06:AF03:V
+
+	# Port A: PA07:AF10:V, PA06:AF10:V
+	mmw 0x48000000 0x0000A000 0x00005000	;# MODER
+	mmw 0x48000008 0x0000F000 0x00000000	;# OSPEEDR
+	mmw 0x4800000C 0x00000000 0x0000F000	;# PUPDR
+	mmw 0x48000020 0xAA000000 0x55000000	;# AFRL
+	# Port C: PC03:AF10:V
+	mmw 0x48000800 0x00000080 0x00000040	;# MODER
+	mmw 0x48000808 0x000000C0 0x00000000	;# OSPEEDR
+	mmw 0x4800080C 0x00000000 0x000000C0	;# PUPDR
+	mmw 0x48000820 0x0000A000 0x00005000	;# AFRL
+	# Port D: PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
+	mmw 0x48000C00 0x00008A00 0x00004500	;# MODER
+	mmw 0x48000C08 0x0000CF00 0x00000000	;# OSPEEDR
+	mmw 0x48000C0C 0x00000000 0x0000CF00	;# PUPDR
+	mmw 0x48000C20 0xA0AA0000 0x50550000	;# AFRL
+	# Port E: PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+	mmw 0x48001000 0x0AA00000 0x05500000	;# MODER
+	mmw 0x48001008 0x0FF00000 0x00000000	;# OSPEEDR
+	mmw 0x4800100C 0x00000000 0x0FF00000	;# PUPDR
+	mmw 0x48001024 0x00AAAA00 0x00555500	;# AFRH
+	# Port G: PG06:AF03:V
+	mmw 0x48001800 0x00002000 0x00001000	;# MODER
+	mmw 0x48001808 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x4800180C 0x00000000 0x00003000	;# PUPDR
+	mmw 0x48001820 0x03000000 0x0C000000	;# AFRL
+
+	# PG12: P2_NCS, PF04: P2_CLK, PF12: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PG01: P2_IO5
+	# PG00: P2_IO4, PF03: P2_IO3, PF02: P2_IO2, PF01: P2_IO1, PF00: P2_IO0
+
+	# PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
+	# PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
+
+	# Port F: PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
+	mmw 0x48001400 0x020002AA 0x01000155	;# MODER
+	mmw 0x48001408 0x030003FF 0x00000000	;# OSPEEDR
+	mmw 0x4800140C 0x00000000 0x030003FF	;# PUPDR
+	mmw 0x48001420 0x00055555 0x000AAAAA	;# AFRL
+	mmw 0x48001424 0x00050000 0x000A0000	;# AFRH
+	# Port G: PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
+	mmw 0x48001800 0x0228000A 0x01140005	;# MODER
+	mmw 0x48001808 0x033C000F 0x00000000	;# OSPEEDR
+	mmw 0x4800180C 0x00000000 0x033C000F	;# PUPDR
+	mmw 0x48001820 0x00000055 0x000000AA	;# AFRL
+	mmw 0x48001824 0x00050550 0x000A0AA0	;# AFRH
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0xA0001130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0xA0001008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0xA000100C 0x00000001				;# OCTOSPI_DCR2: PRESCALER=1
+
+	mww 0xA0001108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0xA0001100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0xA0001110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0xA0001108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0xA0001100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0xA0001110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000003 0x0000000C	;# 3 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 24000
+
+	octospi_init 1
+}
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l4r9i-disco.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l4r9i-disco.cfg
new file mode 100644
index 0000000..cbb8666
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32l4r9i-disco.cfg
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a STM32L4R9I discovery board with a single STM32L4R9AII6 chip.
+# http://www.st.com/en/evaluation-tools/32l4r9idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set OCTOSPI1 1
+set OCTOSPI2 0
+
+source [find target/stm32l4x.cfg]
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x4002104C 0x001001FF 0				;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000300 0				;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
+	mmw 0x40021058 0x10000000 0				;# RCC_APB1ENR1 |= PWREN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	mmw 0x40007004 0x00000200 0				;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
+
+	mww 0x50061C04 0x00000000				;# OCTOSPIM_P1CR: disable Port 1
+	mww 0x50061C08 0x03010111				;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
+
+	# PG12: P2_NCS, PI06: P2_CLK, PG15: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PH10: P2_IO5,
+	# PH09: P2_IO4, PH08: P2_IO3, PI09: P2_IO2, PI10: P2_IO1, PI11: P2_IO0
+
+	# PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PH10:AF05:V, PH09:AF05:V
+	# PH08:AF05:V, PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
+
+	# Port G: PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V
+	mmw 0x48001800 0x82280000 0x41140000	;# MODER
+	mmw 0x48001808 0xC33C0000 0x00000000	;# OSPEEDR
+	mmw 0x48001824 0x50050550 0xA00A0AA0	;# AFRH
+
+	# Port H: PH10:AF05:V, PH09:AF05:V, PH08:AF05:V
+	mmw 0x48001C00 0x002A0000 0x00150000	;# MODER
+	mmw 0x48001C08 0x003F0000 0x00000000	;# OSPEEDR
+	mmw 0x48001C24 0x00000555 0x00000AAA	;# AFRH
+
+	# Port I: PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
+	mmw 0x48002000 0x00A82000 0x00541000	;# MODER
+	mmw 0x48002008 0x00FC3000 0x00000000	;# OSPEEDR
+	mmw 0x48002020 0x05000000 0x0A000000	;# AFRL
+	mmw 0x48002024 0x00005550 0x0000AAA0	;# AFRH
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0xA0001130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0xA0001008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0xA000100C 0x00000001				;# OCTOSPI_DCR2: PRESCALER=1
+
+	mww 0xA0001108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0xA0001100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0xA0001110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0xA0001108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0xA0001100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0xA0001110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000003 0x0000000C	;# 3 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	octospi_init 1
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32ldiscovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32ldiscovery.cfg
new file mode 100644
index 0000000..e39b522
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32ldiscovery.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32L discovery board with a single STM32L152RBT6 chip.
+# http://www.st.com/internet/evalboard/product/250990.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x4000
+source [find target/stm32l1.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32mp13x_dk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32mp13x_dk.cfg
new file mode 100644
index 0000000..08377ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32mp13x_dk.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# board MB1635x
+# http://www.st.com/en/evaluation-tools/stm32mp135f-dk.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32mp13x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32mp15x_dk2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32mp15x_dk2.cfg
new file mode 100644
index 0000000..0e71e05
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32mp15x_dk2.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# board MB1272B
+# http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html
+# http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32mp15x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32vldiscovery.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32vldiscovery.cfg
new file mode 100644
index 0000000..57852bf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/stm32vldiscovery.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32VL discovery board with a single STM32F100RB chip.
+# http://www.st.com/internet/evalboard/product/250863.jsp
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+set WORKAREASIZE 0x2000
+source [find target/stm32f1x.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/str910-eval.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/str910-eval.cfg
new file mode 100644
index 0000000..b6e9837
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/str910-eval.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# str910-eval eval board
+#
+# Need reset scripts
+reset_config trst_and_srst
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists FLASHTAPID] } {
+   set _FLASHTAPID $FLASHTAPID
+} else {
+   set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+   set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs    -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	#jtag_rclk 3000
+
+	# -- Enable 96K RAM
+	# PFQBC enabled / DTCM & AHB wait-states disabled
+	mww 0x5C002034 0x0191
+
+	str9x flash_config 0 4 2 0 0x80000
+	flash protect 0 0 7 off
+}
+
+#flash bank str9x   0 0  
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/telo.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/telo.cfg
new file mode 100644
index 0000000..721c019
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/telo.cfg
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/c100.cfg]
+# basic register definition for C100
+source [find target/c100regs.tcl]
+# board-config info
+source [find target/c100config.tcl]
+# C100 helper functions
+source [find target/c100helper.tcl]
+
+
+# Telo board & C100 support trst and srst
+# make the reset asserted to
+# allow RC circuit to discharge for: [ms]
+adapter srst pulse_width 100
+jtag_ntrst_assert_width 100
+# don't talk to JTAG after reset for: [ms]
+adapter srst delay 100
+jtag_ntrst_delay 100
+reset_config trst_and_srst separate
+
+
+
+
+# issue telnet: reset init
+# issue gdb: monitor reset init
+$_TARGETNAME configure -event reset-init {
+	adapter speed 100
+	# this will setup Telo board
+	setupTelo
+	#turn up the JTAG speed
+	adapter speed 3000
+	echo "JTAG speek now 3MHz"
+	echo "type helpC100 to get help on C100"
+}
+
+$_TARGETNAME configure -event reset-deassert-post {
+	# Force target into ARM state.
+#	soft_reset_halt ;# not implemented on ARM11
+	echo "Detected SRSRT asserted on C100.CPU"
+
+}
+
+$_TARGETNAME configure -event reset-assert-post {
+  echo "Assering reset"
+  #sleep 10
+}
+
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
+
+
+# boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
+# it's really 16MB but the upper 8mb is controller via gpio
+# openocd does not support 'complex reads/writes' to NOR
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
+
+# writing data to memory does not work without this
+arm11 memwrite burst disable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am243_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am243_launchpad.cfg
new file mode 100644
index 0000000..aa75dda
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am243_launchpad.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM243 Launchpad
+# https://www.ti.com/tool/LP-AM243
+#
+
+# AM243 Launchpad has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am243
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am263_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am263_launchpad.cfg
new file mode 100644
index 0000000..a07a21b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am263_launchpad.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM263 Launchpad
+# https://www.ti.com/tool/LP-AM263
+#
+
+# AM263 Launchpad has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am263
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am273_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am273_launchpad.cfg
new file mode 100644
index 0000000..c17170b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am273_launchpad.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM273 Launchpad
+# https://www.ti.com/tool/LP-AM273
+#
+
+# AM273 Launchpad has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am273
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am335xevm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am335xevm.cfg
new file mode 100644
index 0000000..af058ec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am335xevm.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI AM335x Evaluation Module
+#
+# For more information please see http://www.ti.com/tool/tmdxevm3358
+#
+jtag_rclk 6000
+
+source [find target/am335x.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am437x_idk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am437x_idk.cfg
new file mode 100644
index 0000000..b427762
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am437x_idk.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Texas Instruments AM437x Industrial Development Kit
+
+# The JTAG interface is built directly on the board.
+source [find interface/ftdi/xds100v2.cfg]
+
+transport select jtag
+adapter speed 30000
+
+source [find target/am437x.cfg]
+$_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 }
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am43xx_evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am43xx_evm.cfg
new file mode 100644
index 0000000..005421f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am43xx_evm.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Works on both AM437x GP EVM and AM438x ePOS EVM
+transport select jtag
+adapter speed 16000
+
+source [find target/am437x.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am625_swd_native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am625_swd_native.cfg
new file mode 100644
index 0000000..dc4b205
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am625_swd_native.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments am625
+# Link: https://www.ti.com/product/AM625
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every AM625 platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside AM625 and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC am625
+}
+
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am625evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am625evm.cfg
new file mode 100644
index 0000000..4906fd0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am625evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2021-2022 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments am625 EVM/SK
+# Link: https://www.ti.com/lit/zip/sprr448
+#
+
+# AM625 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am625
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62a7_swd_native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62a7_swd_native.cfg
new file mode 100644
index 0000000..99fc0b0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62a7_swd_native.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM62A7
+# Link: https://www.ti.com/product/AM62A7
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every AM62A7 platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside AM62A7 and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC am62a7
+}
+
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62a7evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62a7evm.cfg
new file mode 100644
index 0000000..e407909
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62a7evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments am62a7 EVM/SK
+# Link: https://www.ti.com/tool/SK-AM62A-LP
+#
+
+# AM62a7 EVM/SK has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am62a7
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62p_swd_native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62p_swd_native.cfg
new file mode 100644
index 0000000..fa549f3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62p_swd_native.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments am62p
+# Link: https://www.ti.com/product/AM62P
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every AM62P platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside AM62P and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC am62p
+}
+
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62pevm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62pevm.cfg
new file mode 100644
index 0000000..2322b3d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am62pevm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments SK-AM62P: https://www.ti.com/lit/zip/sprr487
+#
+
+# AM62P SK/EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am62p
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am642evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am642evm.cfg
new file mode 100644
index 0000000..e97fdcf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am642evm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM642 EVM
+#
+
+# AM642 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am642
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am654evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am654evm.cfg
new file mode 100644
index 0000000..a661f60
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_am654evm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM654 EVM/IDK Base Board
+#
+
+# AM654 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+if { ![info exists SOC] } {
+	set SOC am654
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beagleboard.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beagleboard.cfg
new file mode 100644
index 0000000..6767bd6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beagleboard.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OMAP3 BeagleBoard
+#  http://beagleboard.org
+
+# Fall back to 6MHz if RTCK is not supported
+jtag_rclk 6000
+
+source [find target/omap3530.cfg]
+
+# TI-14 JTAG connector
+reset_config trst_only
+
+# Later run:  omap3_dbginit
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beagleboard_xm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beagleboard_xm.cfg
new file mode 100644
index 0000000..fd176a0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beagleboard_xm.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BeagleBoard xM (DM37x)
+#  http://beagleboard.org
+
+set CHIPTYPE "dm37x"
+source [find target/amdm37x.cfg]
+
+# The TI-14 JTAG connector does not have srst.  CPU reset is handled in
+# hardware.
+reset_config trst_only
+
+# "amdm37x_dbginit dm37x.cpu" needs to be run after init.
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beaglebone-base.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beaglebone-base.cfg
new file mode 100644
index 0000000..566f0a4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beaglebone-base.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# AM335x Beaglebone family base configuration
+#  http://beagleboard.org/bone
+
+source [find target/am335x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beaglebone.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beaglebone.cfg
new file mode 100644
index 0000000..d96e45f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beaglebone.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# AM335x Beaglebone
+#  http://beagleboard.org/bone
+
+# The JTAG interface is built directly on the board.
+source [find interface/ftdi/xds100v2.cfg]
+
+adapter speed 16000
+
+reset_config trst_and_srst
+
+source [find board/ti_beaglebone-base.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beaglebone_black.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beaglebone_black.cfg
new file mode 100644
index 0000000..d72bf09
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_beaglebone_black.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# AM335x Beaglebone Black
+#  http://beagleboard.org/bone
+
+adapter speed 1000
+
+reset_config trst_and_srst
+
+source [find board/ti_beaglebone-base.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_blaze.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_blaze.cfg
new file mode 100644
index 0000000..e28b05b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_blaze.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+jtag_rclk 6000
+
+source [find target/omap4430.cfg]
+
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc13x0_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc13x0_launchpad.cfg
new file mode 100644
index 0000000..f6dfbcd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc13x0_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC13x0 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+transport select jtag
+adapter speed 5500
+source [find target/ti_cc13x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc13x2_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc13x2_launchpad.cfg
new file mode 100644
index 0000000..900842a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc13x2_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC13x2 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc13x2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc26x0_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc26x0_launchpad.cfg
new file mode 100644
index 0000000..431383d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc26x0_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC26x0 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc26x2_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc26x2_launchpad.cfg
new file mode 100644
index 0000000..133f57e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc26x2_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC26x2 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc26x2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc26x2x7_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc26x2x7_launchpad.cfg
new file mode 100644
index 0000000..9e6e72e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc26x2x7_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC1352P7 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc26x2x7.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc3200_launchxl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc3200_launchxl.cfg
new file mode 100644
index 0000000..5f39b8a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc3200_launchxl.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI SimpleLink Wi-Fi CC3200 LaunchPad
+#
+# http://www.ti.com/tool/cc3200-launchxl
+#
+
+source [find interface/ftdi/ti-icdi.cfg]
+
+if { [info exists TRANSPORT] } {
+   transport select $TRANSPORT
+} else {
+   transport select jtag
+}
+
+adapter speed 2500
+
+set WORKAREASIZE 0x40000
+source [find target/ti_cc32xx.cfg]
+
+reset_config srst_only
+adapter srst delay 1100
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc3220sf_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc3220sf_launchpad.cfg
new file mode 100644
index 0000000..fe34554
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc3220sf_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 8500
+transport select swd
+source [find target/ti_cc3220sf.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc32xx_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc32xx_launchpad.cfg
new file mode 100644
index 0000000..343da48
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_cc32xx_launchpad.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC32xx-LaunchXL LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 8500
+transport select swd
+source [find target/ti_cc32xx.cfg]
+
+reset_config srst_only
+adapter srst delay 1100
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_dk-tm4c129.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_dk-tm4c129.cfg
new file mode 100644
index 0000000..d8210e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_dk-tm4c129.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Tiva C DK-TM4C129X Connected Development Kit
+#
+# http://www.ti.com/tool/dk-tm4c129x
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c129xnczad
+
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_ek-tm4c123gxl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_ek-tm4c123gxl.cfg
new file mode 100644
index 0000000..91390fa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_ek-tm4c123gxl.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit
+#
+# http://www.ti.com/tool/ek-tm4c123gxl
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c123gh6pm
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_ek-tm4c1294xl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_ek-tm4c1294xl.cfg
new file mode 100644
index 0000000..63612c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_ek-tm4c1294xl.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Tiva C Series ek-tm4c1294xl Launchpad Evaluation Kit
+#
+# http://www.ti.com/tool/ek-tm4c1294xl
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c1294ncpdt
+
+source [find target/stellaris.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j7200evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j7200evm.cfg
new file mode 100644
index 0000000..cc70056
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j7200evm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J7200 EVM
+#
+
+# J7200 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j7200
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j721e_swd_native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j721e_swd_native.cfg
new file mode 100644
index 0000000..3041c3c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j721e_swd_native.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments TDA4VM/J721E
+# Link: https://www.ti.com/product/TDA4VM
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every TDA4VM platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside TDA4VM and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+        set SOC j721e
+}
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j721evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j721evm.cfg
new file mode 100644
index 0000000..d0c4b74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j721evm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J721E EVM
+#
+
+# J721E EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j721e
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j721s2evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j721s2evm.cfg
new file mode 100644
index 0000000..72418b5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j721s2evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J721s2 EVM
+# Link(SoM): https://www.ti.com/lit/zip/sprr439
+#
+
+# J721s2 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j721s2
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j722s_swd_native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j722s_swd_native.cfg
new file mode 100644
index 0000000..bbe0d50
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j722s_swd_native.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J722S/AM67/TDA4VEN
+# Link: https://www.ti.com/product/AM67
+# Link: https://www.ti.com/product/TDA4VEN-Q1
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every J722S platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside J722S and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC j722s
+}
+
+source [find target/ti_k3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j722sevm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j722sevm.cfg
new file mode 100644
index 0000000..6a5c2d9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j722sevm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Texas Instruments EVM-J722S: https://www.ti.com/lit/zip/sprr495
+#
+
+# J722S EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j722s
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j784s4evm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j784s4evm.cfg
new file mode 100644
index 0000000..d23dc8c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_j784s4evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J784S4 EVM: https://www.ti.com/tool/J784S4XEVM
+# Texas Instruments SK-AM69: https://www.ti.com/tool/SK-AM69
+#
+
+# J784S4/AM69 SK/EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j784s4
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_msp432_launchpad.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_msp432_launchpad.cfg
new file mode 100644
index 0000000..4832b83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_msp432_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI MSP432 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 10000
+transport select swd
+source [find target/ti_msp432.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_pandaboard.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_pandaboard.cfg
new file mode 100644
index 0000000..45092e0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_pandaboard.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+jtag_rclk 6000
+
+source [find target/omap4430.cfg]
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_pandaboard_es.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_pandaboard_es.cfg
new file mode 100644
index 0000000..f837358
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_pandaboard_es.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+jtag_rclk 6000
+
+source [find target/omap4460.cfg]
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_tmdx570ls20susb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_tmdx570ls20susb.cfg
new file mode 100644
index 0000000..9c5ef74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_tmdx570ls20susb.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TMS570 Microcontroller USB Kit
+# http://www.ti.com/tool/TMDX570LS20SUSB
+
+# Board uses a FT2232H to emulate an XDS100v2 JTAG debugger
+# TODO: board also supports an SCI UART on the 2232's B Bus
+source [find interface/ftdi/xds100v2.cfg]
+
+# Processor is TMS570LS20216
+source [find target/ti_tms570ls20xxx.cfg]
+
+reset_config trst_only
+
+# xds100v2 config says add this to the end
+init
+ftdi set_signal PWR_RST 1
+jtag arp_init
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_tmdx570ls31usb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_tmdx570ls31usb.cfg
new file mode 100644
index 0000000..324f003
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/ti_tmdx570ls31usb.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed 1500
+
+source [find interface/ftdi/xds100v2.cfg]
+source [find target/ti_tms570.cfg]
+
+reset_config trst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tocoding_poplar.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tocoding_poplar.cfg
new file mode 100644
index 0000000..5f9dba4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tocoding_poplar.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# board configuration for Tocoding Poplar
+#
+
+# board does not feature anything but JTAG
+transport select jtag
+
+adapter speed 10000
+
+# SRST-only reset configuration
+reset_config srst_only srst_push_pull
+
+source [find target/hi3798.cfg]
+
+# make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# examine remaining cores
+	foreach _core $args {
+		${_TARGETNAME}$_core arp_examine
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/topas910.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/topas910.cfg
new file mode 100644
index 0000000..f45f6e7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/topas910.cfg
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Toshiba TOPAS910 -- TMPA910 Starterkit
+#
+######################################
+
+# We add to the minimal configuration.
+source [find target/tmpa910.cfg]
+
+######################
+# Target configuration
+######################
+
+#$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { topas910_init }
+
+proc topas910_init { } {
+# Init PLL
+# my settings
+	mww 0xf005000c 0x00000007
+	mww 0xf0050010 0x00000065
+	mww 0xf005000c 0x000000a7
+	sleep 10
+	mdw 0xf0050008
+	mww 0xf0050008 0x00000002
+	mww 0xf0050004 0x00000000
+# NEW: set CLKCR5
+	mww 0xf0050054 0x00000040
+#
+	sleep 10
+# Init SDRAM
+#  _PMCDRV          = 0x00000071;
+#  //
+#  // Initialize SDRAM timing parameter
+#  //
+#  _DMC_CAS_LATENCY = 0x00000006;
+#  _DMC_T_DQSS      = 0x00000000;
+#  _DMC_T_MRD       = 0x00000002;
+#  _DMC_T_RAS       = 0x00000007;
+#
+#  _DMC_T_RC        = 0x0000000A;
+#  _DMC_T_RCD       = 0x00000013;
+#
+#  _DMC_T_RFC       = 0x0000010A;
+#
+#  _DMC_T_RP        = 0x00000013;
+#  _DMC_T_RRD       = 0x00000002;
+#  _DMC_T_WR        = 0x00000002;
+#  _DMC_T_WTR       = 0x00000001;
+#  _DMC_T_XP        = 0x0000000A;
+#  _DMC_T_XSR       = 0x0000000B;
+#  _DMC_T_ESR       = 0x00000014;
+#
+#  //
+#  // Configure SDRAM type parameter
+#  _DMC_MEMORY_CFG  = 0x00008011;
+#  _DMC_USER_CONFIG = 0x00000011;
+#  // 32 bit memory interface
+#
+#
+#  _DMC_REFRESH_PRD = 0x00000A60;
+#  _DMC_CHIP_0_CFG  = 0x000140FC;
+#
+#  _DMC_DIRECT_CMD  = 0x000C0000;
+#  _DMC_DIRECT_CMD  = 0x00000000;
+#
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00080031;
+#  //
+#  // Finally start SDRAM
+#  //
+#  _DMC_MEMC_CMD    = MEMC_CMD_GO;
+#  */
+
+	mww 0xf0020260 0x00000071
+	mww 0xf4300014 0x00000006
+	mww 0xf4300018 0x00000000
+	mww 0xf430001C 0x00000002
+	mww 0xf4300020 0x00000007
+	mww 0xf4300024 0x0000000A
+	mww 0xf4300028 0x00000013
+	mww 0xf430002C 0x0000010A
+	mww 0xf4300030 0x00000013
+	mww 0xf4300034 0x00000002
+	mww 0xf4300038 0x00000002
+	mww 0xf430003C 0x00000001
+	mww 0xf4300040 0x0000000A
+	mww 0xf4300044 0x0000000B
+	mww 0xf4300048 0x00000014
+	mww 0xf430000C 0x00008011
+	mww 0xf4300304 0x00000011
+	mww 0xf4300010 0x00000A60
+	mww 0xf4300200 0x000140FC
+	mww 0xf4300008 0x000C0000
+	mww 0xf4300008 0x00000000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00080031
+	mww 0xf4300004 0x00000000
+
+	sleep 10
+#	adapter speed NNNN
+
+# remap off in case of IROM boot
+	mww 0xf0000004 0x00000001
+
+}
+
+# comment the following out if usinf J-Link, it soes not support DCC
+arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/topasa900.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/topasa900.cfg
new file mode 100644
index 0000000..d6ddc44
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/topasa900.cfg
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Thanks to Pieter Conradie for this script!
+# Target:    Toshiba TOPAS900 -- TMPA900 Starterkit
+######################################
+
+# We add to the minimal configuration.
+source [find target/tmpa900.cfg]
+
+######################
+# Target configuration
+######################
+
+#$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { topasa900_init }
+
+proc topasa900_init { } {
+# Init PLL
+# my settings
+	mww 0xf005000c 0x00000007
+	mww 0xf0050010 0x00000065
+	mww 0xf005000c 0x000000a7
+	sleep 10
+	mdw 0xf0050008
+	mww 0xf0050008 0x00000002
+	mww 0xf0050004 0x00000000
+# NEW: set CLKCR5
+	mww 0xf0050054 0x00000040
+#
+# bplan settings
+#	mww 0xf0050004 0x00000000
+#	mww 0xf005000c 0x000000a7
+#	sleep 10
+#	mdw 0xf0050008
+#	mww 0xf0050008 0x00000002
+#	mww 0xf0050010 0x00000065
+#	mww 0xf0050054 0x00000040
+	sleep 10
+# Init SDRAM
+#  _PMCDRV          = 0x00000071;
+#  //
+#  // Initialize SDRAM timing parameter
+#  //
+#  _DMC_CAS_LATENCY = 0x00000006;
+#  _DMC_T_DQSS      = 0x00000000;
+#  _DMC_T_MRD       = 0x00000002;
+#  _DMC_T_RAS       = 0x00000007;
+#
+#  _DMC_T_RC        = 0x0000000A;
+#  _DMC_T_RCD       = 0x00000013;
+#
+#  _DMC_T_RFC       = 0x0000010A;
+#
+#  _DMC_T_RP        = 0x00000013;
+#  _DMC_T_RRD       = 0x00000002;
+#  _DMC_T_WR        = 0x00000002;
+#  _DMC_T_WTR       = 0x00000001;
+#  _DMC_T_XP        = 0x0000000A;
+#  _DMC_T_XSR       = 0x0000000B;
+#  _DMC_T_ESR       = 0x00000014;
+#
+#  //
+#  // Configure SDRAM type parameter
+#  _DMC_MEMORY_CFG  = 0x00008011;
+#  _DMC_USER_CONFIG = 0x00000011;   // 32 bit memory interface
+#
+#
+#  _DMC_REFRESH_PRD = 0x00000A60;
+#  _DMC_CHIP_0_CFG  = 0x000140FC;
+#
+#  _DMC_DIRECT_CMD  = 0x000C0000;
+#  _DMC_DIRECT_CMD  = 0x00000000;
+#
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00080031;
+#  //
+#  // Finally start SDRAM
+#  //
+#  _DMC_MEMC_CMD    = MEMC_CMD_GO;
+#  */
+
+	mww 0xf0020260 0x00000071
+	mww 0xf4300014 0x00000006
+	mww 0xf4300018 0x00000000
+	mww 0xf430001C 0x00000002
+	mww 0xf4300020 0x00000007
+	mww 0xf4300024 0x0000000A
+	mww 0xf4300028 0x00000013
+	mww 0xf430002C 0x0000010A
+	mww 0xf4300030 0x00000013
+	mww 0xf4300034 0x00000002
+	mww 0xf4300038 0x00000002
+	mww 0xf430003C 0x00000001
+	mww 0xf4300040 0x0000000A
+	mww 0xf4300044 0x0000000B
+	mww 0xf4300048 0x00000014
+	mww 0xf430000C 0x00008011
+	mww 0xf4300304 0x00000011
+	mww 0xf4300010 0x00000A60
+	mww 0xf4300200 0x000140FC
+	mww 0xf4300008 0x000C0000
+	mww 0xf4300008 0x00000000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00080031
+	mww 0xf4300004 0x00000000
+
+	sleep 10
+#	adapter speed NNNN
+
+# remap off in case of IROM boot
+	mww 0xf0000004 0x00000001
+
+}
+
+# comment the following out if usinf J-Link, it soes not support DCC
+arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tp-link_tl-mr3020.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tp-link_tl-mr3020.cfg
new file mode 100644
index 0000000..1d1d627
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tp-link_tl-mr3020.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/atheros_ar9331.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	ar9331_25mhz_pll_init
+	sleep 1
+	ar9331_ddr1_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tp-link_wdr4300.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tp-link_wdr4300.cfg
new file mode 100644
index 0000000..9947366
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tp-link_wdr4300.cfg
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/atheros_ar9344.cfg]
+
+reset_config trst_only separate
+
+proc ar9344_40mhz_pll_init {} {
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0x13210f00
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x03000000
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0x13210f00
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000000
+	# QCA_PLL_SRIF_BB_DPLL_BASE_REG
+	mww 0xb8116188 0x03000000
+
+	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
+	mww 0xb8050008 0x0130001C
+	mww 0xb8050008 0x0130001C
+	mww 0xb8050008 0x0130001C
+
+	# QCA_PLL_CPU_PLL_CFG_REG
+	mww 0xb8050000 0x40021380
+	# QCA_PLL_DDR_PLL_CFG_REG
+	mww 0xb8050004 0x40815800
+	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
+	mww 0xb8050008 0x0130801C
+
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0x10810F00
+	mww 0xb81161C0 0x41C00000
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0xD0810F00
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x03000000
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0xD0800F00
+
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x03000000
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x43000000
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x030003E8
+
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0x10810F00
+	mww 0xb8116240 0x41680000
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0xD0810F00
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000000
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0xD0800F00
+
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000000
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x43000000
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000718
+
+	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
+	mww 0xb8050008 0x01308018
+	mww 0xb8050008 0x01308010
+	mww 0xb8050008 0x01308000
+
+	# QCA_PLL_DDR_PLL_DITHER_REG
+	mww 0xb8050044 0x78180200
+	# QCA_PLL_CPU_PLL_DITHER_REG
+	mww 0xb8050048 0x41C00000
+
+}
+
+proc ar9344_ddr_init {} {
+	# QCA_DDR_CTRL_CFG_REG
+	mww 0xb8000108 0x40
+	# QCA_DDR_RD_DATA_THIS_CYCLE_REG
+	mww 0xb8000018 0xFF
+	# QCA_DDR_BURST_REG
+	mww 0xb80000C4 0x74444444
+	# QCA_DDR_BURST2_REG
+	mww 0xb80000C8 0x0222
+	# QCA_AHB_MASTER_TOUT_MAX_REG
+	mww 0xb80000CC 0xFFFFF
+
+	# QCA_DDR_CFG_REG
+	mww 0xb8000000 0xC7D48CD0
+	# QCA_DDR_CFG2_REG
+	mww 0xb8000004 0x9DD0E6A8
+
+	# QCA_DDR_DDR2_CFG_REG
+	mww 0xb80000B8 0x0E59
+	# QCA_DDR_CFG2_REG
+	mww 0xb8000004 0x9DD0E6A8
+
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x08
+	mww 0xb8000010 0x08
+	mww 0xb8000010 0x10
+	mww 0xb8000010 0x20
+	# QCA_DDR_EMR_REG
+	mww 0xb800000C 0x02
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x02
+
+	# QCA_DDR_MR_REG
+	mww 0xb8000008 0x0133
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x1
+	mww 0xb8000010 0x8
+	mww 0xb8000010 0x8
+	mww 0xb8000010 0x4
+	mww 0xb8000010 0x4
+
+	# QCA_DDR_MR_REG
+	mww 0xb8000008 0x33
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x1
+
+	# QCA_DDR_EMR_REG
+	mww 0xb800000C 0x0382
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x2
+	# QCA_DDR_EMR_REG
+	mww 0xb800000C 0x0402
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x2
+
+	# QCA_DDR_REFRESH_REG
+	mww 0xb8000014 0x4270
+
+	# QCA_DDR_TAP_CTRL_0_REG
+	mww 0xb800001C 0x0e
+	# QCA_DDR_TAP_CTRL_1_REG
+	mww 0xb8000020 0x0e
+	# QCA_DDR_TAP_CTRL_2_REG
+	mww 0xb8000024 0x0e
+	# QCA_DDR_TAP_CTRL_3_REG
+	mww 0xb8000028 0x0e
+}
+
+$_TARGETNAME configure -event reset-init {
+
+	# mww 0xb806001c 0x1000000
+	ar9344_40mhz_pll_init
+	sleep 100
+
+	# flash remap
+	# SPI_CONTROL_ADDR
+	mww 0xbF000004 0x43
+
+	ar9344_ddr_init
+	sleep 100
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/trion_t20_bga256.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/trion_t20_bga256.cfg
new file mode 100644
index 0000000..ca44f0b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/trion_t20_bga256.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Trion® T20 BGA256 Development Kit
+# https://www.efinixinc.com/docs/trion20-devkit-ug-v1.5.pdf
+#
+# works after power cycle or pushing sw1.
+# it is because we cannot control CDONE which is connected to ftdi channel 0
+# note from an006: For JTAG programming, T4, T8, T13, and T20 FPGAs use the
+# CRESET_N and SS_N pins in addition to the standard JTAG pins.
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 1
+ftdi layout_init 0x0008 0x008b
+reset_config none
+transport select jtag
+adapter speed 6000
+
+source [find fpga/efinix_trion.cfg]
+
+#openocd -f board/trion_t20_bga256.cfg -c "init" -c "pld load trion.pld outflow/trion_blinker.bit"
+#ipdbg create-hub trion.ipdbghub -tap trion.tap -ir 0x8
+#trion.ipdbghub ipdbg start -tool 0 -port 5555
+
+set JTAGSPI_CHAIN_ID trion.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init trion.pld "trion_jtagspi/outflow/trion_jtagspi.bit" 0xAB
+#jtagspi_program trion_blinker/outflow/trion_blinker.bin 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-k60f120m.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-k60f120m.cfg
new file mode 100644
index 0000000..5914cf0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-k60f120m.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale TWRK60F120M development board
+#
+
+source [find target/k60.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	puts "-event reset-init occurred"
+}
+
+#
+# Definitions for the additional 'program flash' banks
+# (instructions and/or data)
+#
+flash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME
+flash bank pflash.2 kinetis 0x00080000 0x40000 0 4 $_TARGETNAME
+flash bank pflash.3 kinetis 0x000c0000 0x40000 0 4 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-k60n512.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-k60n512.cfg
new file mode 100644
index 0000000..b7743a5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-k60n512.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale TWRK60N512 development board
+#
+
+source [find target/k60.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	puts "-event reset-init occurred"
+}
+
+#
+# Definitions for the additional 'program flash' bank
+# (instructions and/or data)
+#
+flash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-vf65gs10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-vf65gs10.cfg
new file mode 100644
index 0000000..bfc7288
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-vf65gs10.cfg
@@ -0,0 +1,203 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration file for the Freescale VF65GS10 tower board
+#
+# Board has a 20 pin Cortex+ETM debug connector with only nSRST available
+reset_config srst_only
+
+# This configuration file only deals with the hardware JTAG.
+# There is has also an embedded Kinetis K20 with OpenSDA
+# where a CMSIS-DAP application can be installed.
+
+# Source generic VF6xx target configuration
+source [find target/vybrid_vf6xx.cfg]
+
+# basic DDR memory init, setting up pad configuration
+# for DDR first then configuring the DDRMC for the
+# board
+proc ddr_init { } {
+	# iomux ddr
+	mww phys 0x40048220 0x00000180
+	mww phys 0x40048224 0x00000180
+	mww phys 0x40048228 0x00000180
+	mww phys 0x4004822c 0x00000180
+	mww phys 0x40048230 0x00000180
+	mww phys 0x40048234 0x00000180
+	mww phys 0x40048238 0x00000180
+	mww phys 0x4004823c 0x00000180
+	mww phys 0x40048240 0x00000180
+	mww phys 0x40048244 0x00000180
+	mww phys 0x40048248 0x00000180
+	mww phys 0x4004824c 0x00000180
+	mww phys 0x40048250 0x00000180
+	mww phys 0x40048254 0x00000180
+	mww phys 0x40048258 0x00000180
+	mww phys 0x4004825c 0x00000180
+	mww phys 0x40048260 0x00000180
+	mww phys 0x40048264 0x00000180
+	mww phys 0x40048268 0x00000180
+	mww phys 0x4004826c 0x00000180
+	mww phys 0x40048270 0x00000180
+	mww phys 0x40048274 0x00000180
+	mww phys 0x40048278 0x00000180
+	mww phys 0x4004827c 0x00010180
+	mww phys 0x40048280 0x00010180
+	mww phys 0x40048284 0x00010180
+	mww phys 0x40048288 0x00010180
+	mww phys 0x4004828c 0x00010180
+	mww phys 0x40048290 0x00010180
+	mww phys 0x40048294 0x00010180
+	mww phys 0x40048298 0x00010180
+	mww phys 0x4004829c 0x00010180
+	mww phys 0x400482a0 0x00010180
+	mww phys 0x400482a4 0x00010180
+	mww phys 0x400482a8 0x00010180
+	mww phys 0x400482ac 0x00010180
+	mww phys 0x400482b0 0x00010180
+	mww phys 0x400482b4 0x00010180
+	mww phys 0x400482b8 0x00010180
+	mww phys 0x400482bc 0x00010180
+	mww phys 0x400482c0 0x00010180
+	mww phys 0x400482c4 0x00010180
+	mww phys 0x400482c8 0x00010180
+	mww phys 0x400482cc 0x00000180
+	mww phys 0x400482d0 0x00000180
+	mww phys 0x400482d4 0x00000180
+	mww phys 0x400482d8 0x00000180
+	mww phys 0x4004821c 0x000001a0
+	# ddr_ctrl_init
+	mww phys 0x400ae000 0x00000600
+	mww phys 0x400ae008 0x00000020
+	mww phys 0x400ae028 0x00013880
+	mww phys 0x400ae02c 0x00030d40
+	mww phys 0x400ae030 0x0000050c
+	mww phys 0x400ae034 0x15040400
+	mww phys 0x400ae038 0x1406040f
+	mww phys 0x400ae040 0x04040000
+	mww phys 0x400ae044 0x006db00c
+	mww phys 0x400ae048 0x00000403
+	mww phys 0x400ae050 0x01000000
+	mww phys 0x400ae054 0x00060001
+	mww phys 0x400ae058 0x000c0000
+	mww phys 0x400ae05c 0x03000200
+	mww phys 0x400ae060 0x00000006
+	mww phys 0x400ae064 0x00010000
+	mww phys 0x400ae068 0x0c30002c
+	mww phys 0x400ae070 0x00000000
+	mww phys 0x400ae074 0x00000003
+	mww phys 0x400ae078 0x0000000a
+	mww phys 0x400ae07c 0x003001d4
+	mww phys 0x400ae084 0x00010000
+	mww phys 0x400ae088 0x00050500
+	mww phys 0x400ae098 0x00000000
+	mww phys 0x400ae09c 0x04001002
+	mww phys 0x400ae0a4 0x00000001
+	mww phys 0x400ae0c0 0x00460420
+	mww phys 0x400ae108 0x01000200
+	mww phys 0x400ae10c 0x00000040
+	mww phys 0x400ae114 0x00000200
+	mww phys 0x400ae118 0x00000040
+	mww phys 0x400ae120 0x00000000
+	mww phys 0x400ae124 0x0a010300
+	mww phys 0x400ae128 0x01014040
+	mww phys 0x400ae12c 0x01010101
+	mww phys 0x400ae130 0x03030100
+	mww phys 0x400ae134 0x01000101
+	mww phys 0x400ae138 0x0700000c
+	mww phys 0x400ae13c 0x00000000
+	mww phys 0x400ae148 0x10000000
+	mww phys 0x400ae15c 0x01000000
+	mww phys 0x400ae160 0x00040000
+	mww phys 0x400ae164 0x00000002
+	mww phys 0x400ae16c 0x00020000
+	mww phys 0x400ae180 0x00002819
+	mww phys 0x400ae184 0x01000000
+	mww phys 0x400ae188 0x00000000
+	mww phys 0x400ae18c 0x00000000
+	mww phys 0x400ae198 0x00000000
+	mww phys 0x400ae1a4 0x00000c00
+	mww phys 0x400ae1a8 0x00000000
+	mww phys 0x400ae1b8 0x0000000c
+	mww phys 0x400ae1c8 0x00000000
+	mww phys 0x400ae1cc 0x00000000
+	mww phys 0x400ae1d4 0x00000000
+	mww phys 0x400ae1d8 0x01010000
+	mww phys 0x400ae1e0 0x02020000
+	mww phys 0x400ae1e4 0x00000202
+	mww phys 0x400ae1e8 0x01010064
+	mww phys 0x400ae1ec 0x00010101
+	mww phys 0x400ae1f0 0x00000064
+	mww phys 0x400ae1f8 0x00000800
+	mww phys 0x400ae210 0x00000506
+	mww phys 0x400ae224 0x00020000
+	mww phys 0x400ae228 0x01000000
+	mww phys 0x400ae22c 0x04070303
+	mww phys 0x400ae230 0x00000040
+	mww phys 0x400ae23c 0x06000080
+	mww phys 0x400ae240 0x04070303
+	mww phys 0x400ae244 0x00000040
+	mww phys 0x400ae248 0x00000040
+	mww phys 0x400ae24c 0x000f0000
+	mww phys 0x400ae250 0x000f0000
+	mww phys 0x400ae25c 0x00000101
+	mww phys 0x400ae268 0x682c4000
+	mww phys 0x400ae26c 0x00000012
+	mww phys 0x400ae278 0x00000006
+	mww phys 0x400ae284 0x00010202
+	mww phys 0x400ae400 0x00002613
+	mww phys 0x400ae440 0x00002613
+	mww phys 0x400ae404 0x00002615
+	mww phys 0x400ae444 0x00002615
+	mww phys 0x400ae408 0x00210000
+	mww phys 0x400ae448 0x00210000
+	mww phys 0x400ae488 0x00210000
+	mww phys 0x400ae40c 0x0001012a
+	mww phys 0x400ae44c 0x0001012a
+	mww phys 0x400ae48c 0x0001012a
+	mww phys 0x400ae410 0x00002400
+	mww phys 0x400ae450 0x00002400
+	mww phys 0x400ae490 0x00002400
+	mww phys 0x400ae4c4 0x00000000
+	mww phys 0x400ae4c8 0x00001100
+	mww phys 0x400ae4d0 0x00010101
+	mww phys 0x400ae000 0x00000601
+}
+
+# clock control init, setting up basic
+# clocks
+proc clock_init { } {
+	# captured from u-boot
+	mww phys 0x4006b040 0xffffffff
+	mww phys 0x4006b044 0xffffffff
+	mww phys 0x4006b048 0xffffffff
+	mww phys 0x4006b04c 0xffffffff
+	mww phys 0x4006b050 0xffffffff
+	mww phys 0x4006b058 0xffffffff
+	mww phys 0x4006b05c 0xffffffff
+	mww phys 0x4006b060 0xffffffff
+	mww phys 0x4006b064 0xffffffff
+	mww phys 0x4006b068 0xffffffff
+	mww phys 0x40050030 0x00002001
+	mww phys 0x40050270 0x80002001
+	mww phys 0x4006b000 0x00011005
+	mww phys 0x4006b008 0x0001ff24
+	mww phys 0x4006b00c 0x00000810
+	mww phys 0x4006b010 0x00cc0000
+	mww phys 0x4006b014 0x01000000
+	mww phys 0x4006b018 0x20000000
+	mww phys 0x4006b01c 0x0000001f
+	mww phys 0x4006b020 0x00000000
+}
+
+# This function applies the initial configuration after a "reset init"
+# command
+proc board_init { } {
+	clock_init
+	ddr_init
+}
+
+# hook the init function into the reset-init event
+${_TARGETNAME}0 configure -event reset-init { board_init }
+# set a slow default JTAG clock, can be overridden later
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-vf65gs10_cmsisdap.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-vf65gs10_cmsisdap.cfg
new file mode 100644
index 0000000..86930c5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/twr-vf65gs10_cmsisdap.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Board configuration file for the Freescale VF65GS10 tower board
+#
+# CMSIS-DAP via USB-OTG connector
+#
+source [find interface/cmsis-dap.cfg]
+
+# only SWD is supported by the CMSIS-DAP on this board
+transport select swd
+
+# Source generic part of twr-vf65gs10 configuration
+source [find board/twr-vf65gs10.cfg]
+
+# override reset configuration
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tx25_stk5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tx25_stk5.cfg
new file mode 100644
index 0000000..5bf8fd0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tx25_stk5.cfg
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# -------------------------------------------------------------------------
+# KaRo TX25 CPU Module on a StarterkitV base board
+# http://www.karo-electronics.com/tx25.html
+# -------------------------------------------------------------------------
+
+
+source [find target/imx25.cfg]
+
+	#-------------------------------------------------------------------------
+	# Declare Nand
+	#-------------------------------------------------------------------------
+
+	nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
+
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { tx25_init }
+
+
+proc tx25_init { } {
+
+	#-------------------------------------------------------------------------
+	# AIPS setup - Only setup MPROTx registers. The PACR default values are good.
+	# Set all MPROTx to be non-bufferable, trusted for R/W,
+	# not forced to user-mode.
+	#-------------------------------------------------------------------------
+
+	mww 0x43f00000 0x77777777
+	mww 0x43f00004 0x77777777
+	mww 0x53f00000 0x77777777
+	mww 0x53f00004 0x77777777
+
+	sleep 100
+
+	#-------------------------------------------------------------------------
+	# MAX (Multi-Layer AHB Crossbar Switch) setup
+	# MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
+	#-------------------------------------------------------------------------
+
+	mww 0x43f04000 0x00043210
+	mww 0x43f04100 0x00043210
+	mww 0x43f04200 0x00043210
+	mww 0x43f04300 0x00043210
+	mww 0x43f04400 0x00043210
+
+	# SGPCR - always park on last master
+	mww 0x43f04010 0x10
+	mww 0x43f04110 0x10
+	mww 0x43f04210 0x10
+	mww 0x43f04310 0x10
+	mww 0x43f04410 0x10
+
+	# MGPCR - restore default values
+	mww 0x43f04800 0x0
+	mww 0x43f04900 0x0
+	mww 0x43f04a00 0x0
+	mww 0x43f04b00 0x0
+	mww 0x43f04c00 0x0
+
+	# Configure M3IF registers
+	# M3IF Control Register (M3IFCTL) for MX25
+	# MRRP[0] = LCDC           on priority list (1 << 0)  = 0x00000001
+	# MRRP[1] = MAX1       not on priority list (0 << 1)  = 0x00000000
+	# MRRP[2] = MAX0       not on priority list (0 << 2)  = 0x00000000
+	# MRRP[3] = USB HOST   not on priority list (0 << 3)  = 0x00000000
+	# MRRP[4] = SDMA       not on priority list (0 << 4)  = 0x00000000
+	# MRRP[5] = SD/ATA/FEC not on priority list (0 << 5)  = 0x00000000
+	# MRRP[6] = SCMFBC     not on priority list (0 << 6)  = 0x00000000
+	# MRRP[7] = CSI        not on priority list (0 << 7)  = 0x00000000
+	#                                                       ----------
+	#                                                       0x00000001
+	mww 0xb8003000 0x00000001
+
+	#-------------------------------------------------------------------------
+	# configure ARM CLK
+	#-------------------------------------------------------------------------
+
+	# Set the Clock CTL (HRM p. 355)
+	mww 0x53F80008 0x20034000
+
+	# Setup Clock Gating CTL 0-2 (HRM p. 357)
+	mww 0x53F8000C 0x1fffffff
+	mww 0x53F80010 0xffffffff
+	mww 0x53F80014 0x000fdfff
+
+	#-------------------------------------------------------------------------
+	# SDRAM initialization
+	#-------------------------------------------------------------------------
+
+	# set to 3.3v SDRAM
+	mww 0x43FAC454 0x00000800
+
+	# reset (set up ESDMISC)
+	mww 0xB8001010 0x00000002
+
+	# Setup for SDRAM Bank 0
+	#-------------------------------------------------------------------------
+
+	# Write ESDCFG0
+	mww 0xB8001004 0x00095728
+
+	# CTL SMode = Precharge command
+	mww 0xB8001000 0x92116480
+	mww 0x80000400 0x00000000
+
+	# CTL SMode = Auto Refresh command
+	mww 0xB8001000 0xA2116480
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+	mww 0x80000000 0x0
+
+	# CTL SMode = Load Mode Register command
+	mww 0xB8001000 0xB2116480
+	mwb 0x80000033 0x00
+
+	# CTL SMode = normal
+	mww 0xB8001000 0x82116480
+
+	# Setup for SDRAM Bank 1
+	#-------------------------------------------------------------------------
+
+	# Write ESDCFG1
+	mww 0xB800100C 0x00095728
+
+	# CTL SMode = Precharge command
+	mww 0xB8001008 0x92116480
+	mww 0x90000400 0x00000000
+
+	# CTL SMode = Auto Refresh command
+	mww 0xB8001008 0xA2116480
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+	mww 0x90000000 0x00000000
+
+	# CTL SMode = Load Mode Register command
+	mww 0xB8001008 0xB2116480
+	mwb 0x90000033 0x00
+
+	# CTL SMode = normal
+	mww 0xB8001008 0x82116480
+
+	# GPIO configuration
+	#-------------------------------------------------------------------------
+
+	mww 0x43FAC02C 0x00000015
+	mww 0x53FD0000 0x01000000
+	mww 0x53FD0004 0x00000080
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tx27_stk5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tx27_stk5.cfg
new file mode 100644
index 0000000..061f1f9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/tx27_stk5.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# KaRo TX27 CPU Module on a StarterkitV base board
+#
+# http://www.karo-electronics.com/tx27.html
+#
+source [find target/imx27.cfg]
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { tx27_init }
+
+proc tx27_init { } {
+	# This setup puts RAM at 0xA0000000
+	# init_aipi (AIPI1.PSR0, AIPI2.PSR0, AIPI1.PSR1 and AIPI2.PSR1)
+	mww 0x10000000 0x20040304
+	mww 0x10020000 0x00000000
+	mww 0x10000004 0xDFFBFCFB
+	mww 0x10020004 0xFFFFFFFF
+
+	sleep 100
+
+	#init_max ( PORT0.MPR, #PORT0.AMPR, #PORT1.MPR, #PORT1.AMPR, #PORT2.MPR, #PORT2.AMPR)
+	mww 0x1003F000 0x00302145
+	mww 0x1003F004 0x00302145
+	mww 0x1003F100 0x00302145
+	mww 0x1003F104 0x00302145
+	mww 0x1003F200 0x00302145
+	mww 0x1003F204 0x00302145
+
+	#init_drive_strength (#DSCR3, #DSCR5, #DSCR6, #DSCR7, #DSCR8 )
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
+
+	#init_sdram_speed
+	#mww 0xD8001010 0x00000004
+	mww 0xD8001010 0x00000024
+
+	mww 0xD8001004 0x00395729
+
+	mww 0xD8001000 0x92120000
+	mww 0xA0000400 0x0
+
+	mww 0xD8001000 0xA2120000
+	mww 0xA0000000 0x0
+	mww 0xA0000000 0x0
+
+	mww 0xD8001000 0xB2120000
+	mdb 0xA0000000
+	mdb 0xA0000033
+
+	mww 0xD8001000 0x82126485
+
+	# =============================================
+	# Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz)
+	# =============================================
+	mww 0xD8002000 0x23524E80
+	mww 0xD8002004 0x10000D03
+	mww 0xD8002008 0x00720900
+
+	nand probe 0
+}
+
+nand device tx27.nand mxc $_TARGETNAME mx27 hwecc biswap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/unknown_at91sam9260.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/unknown_at91sam9260.cfg
new file mode 100644
index 0000000..cab18b6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/unknown_at91sam9260.cfg
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Thanks to Pieter Conradie for this script!
+#
+# Unknown vendor board contains:
+#
+# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
+#                     OSCSEL configured for internal RC oscillator (22 to 42 kHz)
+#
+# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
+# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
+##################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 22 to 42 kHz.
+        # JTAG Frequency must be 6 times slower.
+        jtag_rclk 3
+        halt
+	# RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc28 0x205dbf09         ;# CKGR_PLLAR: Set PLLA Register for 192.512MHz
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
+        sleep 10                          ;# wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	mww 0xffffec00 0x01020102         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+	mww 0xffffec04 0x09070806         ;# SMC_PULSE0
+	mww 0xffffec08 0x000d000b         ;# SMC_CYCLE0
+	mww 0xffffec0c 0x00001003         ;# SMC_MODE0
+
+	flash probe 0                     ;# Identify flash bank 0
+
+	mww 0xfffff870 0xffff0000         ;# PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         ;# PIO_PDR  : Disable PIO function for D15..D31
+        mww 0xfffff860 0xffff0000         ;# PIO_PUDR : Disable D15..D31 pull-ups
+
+        mww 0xffffef1c 0x00010102         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM
+                                           #            VDDIOMSEL set for +3V3 memory
+                                           #            Disable D0..D15 pull-ups
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2a2              ;# SDRAMC_TR : Set refresh timer count to 7us
+}
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/uptech_2410.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/uptech_2410.cfg
new file mode 100644
index 0000000..ba269f5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/uptech_2410.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target Configuration for the Uptech 2410 board.
+# This configuration should also work on smdk2410, but I haven't tested it yet.
+# Author: xionglingfeng@Gmail.com
+
+source [find target/samsung_s3c2410.cfg]
+
+$_TARGETNAME configure -event reset-init { uptech2410_init }
+$_TARGETNAME configure -event gdb-attach { reset init }
+
+proc init_pll_sdram { } {
+	#echo "---------- Initializing PLL and SDRAM ---------"
+	#watchdog timer disable
+	mww phys 0x53000000 0x00000000
+
+	#disable all interrupts
+	mww phys 0x4a000008 0xffffffff
+
+	#disable all sub-interrupts
+	mww phys 0x4a00001c 0x000007ff
+
+	#clear all source pending bits
+	mww phys 0x4a000000 0xffffffff
+
+	#clear all sub-source pending bits
+	mww phys 0x4a000018 0x000007ff
+
+	#clear interrupt pending bit
+	mww phys 0x4a000010 0xffffffff
+
+	#PLL locktime counter
+	mww phys 0x4c000000 0x00ffffff
+
+	#Fin=12MHz Fout=202.8MHz
+	#mww phys 0x4c000004 0x000a1031
+
+	#FCLK:HCLK:PCLK = 1:2:4
+	mww phys 0x4c000014 0x00000003
+
+
+	mww phys 0x48000000 0x11111110
+	mww phys 0x48000004 0x00007FFC
+	mww phys 0x48000008 0x00007FFC
+	mww phys 0x4800000c 0x00000700
+	mww phys 0x48000010 0x00000700
+	mww phys 0x48000014 0x00002E50
+	mww phys 0x48000018 0x00002E50
+	mww phys 0x4800001c 0x00018005
+	mww phys 0x48000020 0x00018005
+	mww phys 0x48000024 0x008c04e9
+	mww phys 0x48000028 0x000000b2
+	mww phys 0x4800002c 0x00000030
+	mww phys 0x48000030 0x00000030
+}
+
+proc uptech2410_init { } {
+	init_pll_sdram
+	#echo "---------- Probing Nand flash ----------"
+	nand probe 0
+	#echo "---------- Enable some functions ----------"
+}
+
+set _NANDNAME $_CHIPNAME.nand
+nand device $_NANDNAME s3c2410 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a53x2_dap.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a53x2_dap.cfg
new file mode 100644
index 0000000..bcf8b44
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a53x2_dap.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CORES 2
+set CHIPNAME a53
+set ACCESSPORT 0
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x80810000 0x80910000}
+set CTIBASE {0x80820000 0x80920000}
+
+# vdebug select transport
+transport select dapdirect_swd
+
+# JTAG reset config, frequency and reset delay
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_swdp_bfm 10ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
+
+swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+source [find target/vd_aarch64.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a53x2_jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a53x2_jtag.cfg
new file mode 100644
index 0000000..0c3eebd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a53x2_jtag.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CORES 2
+set CHIPNAME a53
+set ACCESSPORT 0
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x80810000 0x80910000}
+set CTIBASE {0x80820000 0x80920000}
+set CPUTAPID 0x5ba00477
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
+
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
+jtag arp_init-reset
+
+source [find target/vd_aarch64.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a75x4_dap.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a75x4_dap.cfg
new file mode 100644
index 0000000..5c2a2ef
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a75x4_dap.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CORES 4
+set CHIPNAME a75
+set ACCESSPORT 0x00040000
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
+set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
+
+# vdebug select transport
+transport select dapdirect_swd
+
+# JTAG reset config, frequency and reset delay
+adapter speed 200000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_dap6_bfm 2250ps
+
+# DMA Memories to access backdoor (up to 20)
+#vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
+
+swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+source [find target/vd_aarch64.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a75x4_jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a75x4_jtag.cfg
new file mode 100644
index 0000000..c94a719
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_a75x4_jtag.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CORES 4
+set CHIPNAME a75
+set ACCESSPORT 0x00040000
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
+set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
+set CPUTAPID 0x4ba06477
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 1500000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 333ps
+
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
+jtag arp_init-reset
+
+source [find target/vd_aarch64.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_m4_dap.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_m4_dap.cfg
new file mode 100644
index 0000000..5d3605a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_m4_dap.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex m4 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME m4
+set MEMSTART 0x00000000
+set MEMSIZE 0x10000
+
+# vdebug select transport
+transport select dapdirect_swd
+adapter speed 25000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_swdp_bfm 20ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
+
+swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+source [find target/vd_cortex_m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_m4_jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_m4_jtag.cfg
new file mode 100644
index 0000000..3b32e17
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_m4_jtag.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex m4 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME m4
+set MEMSTART 0x00000000
+set MEMSIZE 0x10000
+set CPUTAPID 0x4ba00477
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 25000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 20ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
+
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
+jtag arp_init-reset
+
+source [find target/vd_cortex_m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_m7_jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_m7_jtag.cfg
new file mode 100644
index 0000000..9a89584
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_m7_jtag.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex m7 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME m7
+set MEMSTART 0x00000000
+set MEMSIZE 0x100000
+set CPUTAPID 0x0ba02477
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $MEMSTART $MEMSIZE
+
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
+jtag arp_init-reset
+
+source [find target/vd_cortex_m.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_pulpissimo_jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_pulpissimo_jtag.cfg
new file mode 100644
index 0000000..a3f5a84
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_pulpissimo_jtag.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV Ibex core with Pulpissimo through JTAG
+
+source [find interface/vdebug.cfg]
+
+set _CHIPNAME ibex
+set _HARTID 0x20
+set _CPUTAPID 0x249511c3
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 12500
+adapter srst delay 10
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 40ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[0\].sram_i.mem_array 0x1c000000 0x8000
+vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[1\].sram_i.mem_array 0x1c008000 0x8000
+vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2\[0\].sram_i.mem_array 0x1c010000 0x80000
+
+# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $_CPUTAPID
+
+jtag arp_init-reset
+
+source [find target/vd_riscv.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_swerv_jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_swerv_jtag.cfg
new file mode 100644
index 0000000..c5d33f2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_swerv_jtag.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV swerv core with Swerv through JTAG
+
+source [find interface/vdebug.cfg]
+
+set _CHIPNAME rv32
+set _HARTID 0x00
+set _CPUTAPID 0x1000008b
+set _MEMSTART 0x00000000
+set _MEMSIZE 0x10000
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.i_ahb_ic.mem $_MEMSTART $_MEMSIZE
+
+# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
+
+jtag arp_init-reset
+
+source [find target/vd_riscv.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_xt8_jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_xt8_jtag.cfg
new file mode 100644
index 0000000..867b9e7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/vd_xt8_jtag.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Xtensa xt8 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME xt8
+set CPUTAPID 0x120034e5
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor, the values come from generated xtensa-core-xt8.cfg
+#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray 0x40000000 0x100000
+#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray 0x3ff00000 0x40000
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
+source  [find target/xtensa-core-xt8.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/verdex.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/verdex.cfg
new file mode 100644
index 0000000..8511120
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/verdex.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Gumstix Verdex XM4 and XL6P (PXA270)
+
+set CHIPNAME verdex
+source [find target/pxa270.cfg]
+
+# The board supports separate reset lines
+# Override this in the interface config for parallel dongles
+reset_config trst_and_srst separate
+
+# XM4 = 400MHz, XL6P = 600MHz...let's run at 0.1*400MHz=40MHz
+adapter speed 40000
+
+# flash bank     
+# XL6P has 32 MB flash
+flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x02000000 2 2 $_TARGETNAME
+# XM4 has 16 MB flash
+#flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/voipac.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/voipac.cfg
new file mode 100644
index 0000000..74e651a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/voipac.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Voipac PXA270/PXA270M module.
+
+set CHIPNAME voipac
+source [find target/pxa270.cfg]
+
+# The board supports separate reset lines
+# Override this in the interface config for parallel dongles
+reset_config trst_and_srst separate
+
+# flash bank     
+flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
+flash bank $_CHIPNAME.flash1 cfi 0x02000000 0x2000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/voltcraft_dso-3062c.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/voltcraft_dso-3062c.cfg
new file mode 100644
index 0000000..fd56a81
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/voltcraft_dso-3062c.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Voltcraft DSO-3062C digital oscilloscope (uses a Samsung S3C2440)
+#
+# http://www.eevblog.com/forum/general-chat/hantek-tekway-dso-hack-get-200mhz-bw-for-free/
+# http://www.mikrocontroller.net/topic/249628
+# http://elinux.org/Das_Oszi
+# http://randomprojects.org/wiki/Voltcraft_DSO-3062C
+#
+
+# Enable this if your JTAG adapter supports multiple transports (JTAG or SWD).
+# Otherwise comment it out, as it will cause an OpenOCD error.
+### transport select jtag
+
+source [find target/samsung_s3c2440.cfg]
+
+adapter speed 16000
+
+# Samsung K9F1208U0C NAND flash chip (64MiB, 3.3V, 8-bit)
+nand device $_CHIPNAME.nand s3c2440 $_TARGETNAME
+
+# arm7_9 fast_memory_access enable
+# arm7_9 dcc_downloads enable
+
+init
+reset
+halt
+scan_chain
+targets
+nand probe 0
+nand list
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/x300t.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/x300t.cfg
new file mode 100644
index 0000000..c57c9d9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/x300t.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for the T-Home X300T / X301T IPTV box,
+# which are based on IPTV reference designs from Kiss/Cisco KMM-3***
+#
+# It has Sigma Designs SMP8634 chip.
+source [find target/smp8634.cfg]
+
+$_TARGETNAME configure -event reset-init { x300t_init }
+
+# 1MB CFI capable flash
+# flash bank       
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xac000000 0x100000 2 2 $_TARGETNAME
+
+proc x300t_init { } {
+	# Setup SDRAM config and flash mapping
+	# initialize ram
+	mww 0xa003fffc 3
+	mww 0xa003fffc 2
+	mww 0xa0030000 0xE34111BA
+	mww 0xa003fffc 0xa4444
+	mww 0xa003fffc 0
+
+	# remap boot vector in CPU local RAM
+	mww 0xa006f000 0x60000
+
+	# map flash to CPU address space REG_BASE_cpu_block+CPU_remap4
+	mww 0x0006f010 0x48000000
+
+	# map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS)
+	mww 0x00061ff0 0x48000000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc-2go.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc-2go.cfg
new file mode 100644
index 0000000..dd78a12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc-2go.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC 2Go
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+set CHIPNAME xmc1100
+set WORKAREASIZE 0x4000
+source [find target/xmc1xxx.cfg]
+
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc1100-boot-kit.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc1100-boot-kit.cfg
new file mode 100644
index 0000000..12ee3e2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc1100-boot-kit.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC1100 Boot Kit
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+set CHIPNAME xmc1100
+set WORKAREASIZE 0x4000
+source [find target/xmc1xxx.cfg]
+
+reset_config srst_only srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4200-application-kit-actuator.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4200-application-kit-actuator.cfg
new file mode 100644
index 0000000..79befaa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4200-application-kit-actuator.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4200 Application Kit - Actuator
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+set CHIPNAME xmc4200
+source [find target/xmc4xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4300-relax.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4300-relax.cfg
new file mode 100644
index 0000000..b748793
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4300-relax.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4300 Relax EtherCAT Kit
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+set CHIPNAME xmc4300
+source [find target/xmc4xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4500-application-kit-general.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4500-application-kit-general.cfg
new file mode 100644
index 0000000..dbb5325
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4500-application-kit-general.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4500 Application Kit - General Purpose
+#
+
+set CHIPNAME xmc4500
+source [find target/xmc4xxx.cfg]
+
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4500-application-kit-sdram.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4500-application-kit-sdram.cfg
new file mode 100644
index 0000000..580dfd8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4500-application-kit-sdram.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4500 Application Kit - SDRAM
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+
+set CHIPNAME xmc4500
+source [find target/xmc4xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4500-relax.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4500-relax.cfg
new file mode 100644
index 0000000..1239f04
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4500-relax.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4500 Relax Kit / Relax Lite Kit
+#
+
+#
+# Segger J-Link Lite XMC4500 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+# There's also an unpopulated 10-pin 0.05" pinout.
+
+set CHIPNAME xmc4500
+source [find target/xmc4xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4700-relax.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4700-relax.cfg
new file mode 100644
index 0000000..ac8ce26
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4700-relax.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4700 Relax Lite Kit / Relax Kit for 5V Shields / Relax Kit
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+# There's also an unpopulated 10-pin 0.05" pinout.
+
+set CHIPNAME xmc4700
+source [find target/xmc4xxx.cfg]
+
+# Relax Kit only: N25Q032A qSPI flash
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4800-relax.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4800-relax.cfg
new file mode 100644
index 0000000..d63159f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmc4800-relax.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4800 Relax EtherCAT Kit
+#
+
+#
+# Segger J-Link Lite XMC4200 on-board
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+# There's also an unpopulated 10-pin 0.05" pinout.
+
+set CHIPNAME xmc4800
+source [find target/xmc4xxx.cfg]
+
+# N25Q032A qSPI flash
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmos_xk-xac-xa8_arm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmos_xk-xac-xa8_arm.cfg
new file mode 100644
index 0000000..2e83977
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xmos_xk-xac-xa8_arm.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# xCORE-XA Core Module
+#
+# https://www.xmos.com/support/boards?product=17940
+#
+
+#
+# J-Link OB STM32F103
+#
+source [find interface/jlink.cfg]
+transport select swd
+
+#
+# XS1-XAU8A-10
+#
+source [find target/xmos_xs1-xau8a-10_arm.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-kc705-ext-dap.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-kc705-ext-dap.cfg
new file mode 100644
index 0000000..ac92c70
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-kc705-ext-dap.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with various external adapters that support DAP, e.g. JLink
+#
+
+adapter speed 5000
+
+# KC705 supports DAP/JTAG
+transport select jtag
+set XTENSA_DAP enable
+set XTENSA_DAP_BASE 0x10000
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-kc705-ext.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-kc705-ext.cfg
new file mode 100644
index 0000000..6be0681
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-kc705-ext.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with various external adapters, e.g. Flyswatter2 or JLink
+#
+
+adapter speed 10000
+
+# KC705 supports JTAG only
+transport select jtag
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-kc705-onboard.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-kc705-onboard.cfg
new file mode 100644
index 0000000..f0a616c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-kc705-onboard.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with on-board (FTDI) adapter or various external adapters
+#
+
+source [find interface/ftdi/xt_kc705_ml605.cfg]
+adapter speed 10000
+
+# KC705 supports JTAG only
+transport select jtag
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-palladium-vdebug-dual.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-palladium-vdebug-dual.cfg
new file mode 100644
index 0000000..447bc1f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-palladium-vdebug-dual.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+source [find interface/vdebug.cfg]
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# Future improvement: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.VJTAG 10ns
+
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Configure dual-core TAP chain
+set XTENSA_NUM_CORES 2
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-palladium-vdebug.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-palladium-vdebug.cfg
new file mode 100644
index 0000000..f14d92d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-palladium-vdebug.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+source [find interface/vdebug.cfg]
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# Future improvement: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.VJTAG 10ns
+
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-rt685-ext.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-rt685-ext.cfg
new file mode 100644
index 0000000..03edb8d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/board/xtensa-rt685-ext.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP RT6XX Developemnt Platform with Xtensa HiFi DSP
+# Can be used with various external adapters that support DAP, e.g. JLink
+#
+
+adapter speed 10000
+
+# RT6XX supports SWD only
+transport select swd
+set XTENSA_DAP enable
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+source [find target/xtensa-core-nxp_rt600.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/aic.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/aic.tcl
new file mode 100644
index 0000000..6657b60
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/aic.tcl
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AIC_SMR      	[expr {$AT91C_BASE_AIC + 0x00000000} ]
+global AIC_SMR
+set AIC_SVR      	[expr {$AT91C_BASE_AIC + 0x00000080} ]
+global AIC_SVR
+set AIC_IVR      	[expr {$AT91C_BASE_AIC + 0x00000100} ]
+global AIC_IVR
+set AIC_FVR      	[expr {$AT91C_BASE_AIC + 0x00000104} ]
+global AIC_FVR
+set AIC_ISR      	[expr {$AT91C_BASE_AIC + 0x00000108} ]
+global AIC_ISR
+set AIC_IPR      	[expr {$AT91C_BASE_AIC + 0x0000010C} ]
+global AIC_IPR
+set AIC_IMR      	[expr {$AT91C_BASE_AIC + 0x00000110} ]
+global AIC_IMR
+set AIC_CISR     	[expr {$AT91C_BASE_AIC + 0x00000114} ]
+global AIC_CISR
+set AIC_IECR     	[expr {$AT91C_BASE_AIC + 0x00000120} ]
+global AIC_IECR
+set AIC_IDCR     	[expr {$AT91C_BASE_AIC + 0x00000124} ]
+global AIC_IDCR
+set AIC_ICCR     	[expr {$AT91C_BASE_AIC + 0x00000128} ]
+global AIC_ICCR
+set AIC_ISCR     	[expr {$AT91C_BASE_AIC + 0x0000012C} ]
+global AIC_ISCR
+set AIC_EOICR    	[expr {$AT91C_BASE_AIC + 0x00000130} ]
+global AIC_EOICR
+set AIC_SPU      	[expr {$AT91C_BASE_AIC + 0x00000134} ]
+global AIC_SPU
+set AIC_DCR      	[expr {$AT91C_BASE_AIC + 0x00000138} ]
+global AIC_DCR
+set AIC_FFER     	[expr {$AT91C_BASE_AIC + 0x00000140} ]
+global AIC_FFER
+set AIC_FFDR     	[expr {$AT91C_BASE_AIC + 0x00000144} ]
+global AIC_FFDR
+set AIC_FFSR     	[expr {$AT91C_BASE_AIC + 0x00000148} ]
+global AIC_FFSR
+
+
+proc aic_enable_disable_list { VAL ENAME DNAME } {
+    global AT91C_ID
+
+    show_mmr32_bits AT91C_ID $VAL
+
+}
+
+proc show_AIC_IPR_helper { NAME ADDR VAL } {
+    aic_enable_disable_list  $VAL "IRQ PENDING" "irq not-pending"
+}
+
+proc show_AIC_IMR_helper { NAME ADDR VAL } {
+    aic_enable_disable_list  $VAL "IRQ ENABLED" "irq disabled"
+}
+
+
+proc show_AIC { } {
+    global AIC_SMR
+    if [catch { set aaa [read_memory $AIC_SMR 32 [expr {32 * 4}]] } msg ] {
+	error [format "%s (%s)" $msg AIC_SMR]
+    }
+    echo "AIC_SMR: Mode & Type"
+    global AT91C_ID
+    for { set x 0 } { $x < 32 } {  } {
+	echo -n "   "
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo  [format "%2d: %5s 0x%08x"  $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+    }
+    global AIC_SVR
+    if [catch { set aaa [read_memory $AIC_SVR 32 [expr {32 * 4}]] } msg ] {
+	error [format "%s (%s)" $msg AIC_SVR]
+    }
+    echo "AIC_SVR: Vectors"
+    for { set x 0 } { $x < 32 } {  } {
+	echo -n "   "
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+	echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) [lindex $aaa $x]]
+	incr x
+    }
+
+    foreach REG {
+	AIC_IVR   AIC_FVR  AIC_ISR
+	AIC_IPR  AIC_IMR  AIC_CISR  AIC_IECR AIC_IDCR
+	AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU  AIC_DCR
+	AIC_FFER AIC_FFDR AIC_FFSR } {
+	if [catch { show_mmr32_reg $REG } msg ] {
+	    error $msg
+	    break
+	}
+    }
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_pio.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_pio.cfg
new file mode 100644
index 0000000..10a1d48
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_pio.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set PIO_PER	0x00	;# Enable Register
+set PIO_PDR	0x04	;# Disable Register
+set PIO_PSR	0x08	;# Status Register
+set PIO_OER	0x10	;# Output Enable Register
+set PIO_ODR	0x14	;# Output Disable Register
+set PIO_OSR	0x18	;# Output Status Register
+set PIO_IFER	0x20	;# Glitch Input Filter Enable
+set PIO_IFDR	0x24	;# Glitch Input Filter Disable
+set PIO_IFSR	0x28	;# Glitch Input Filter Status
+set PIO_SODR	0x30	;# Set Output Data Register
+set PIO_CODR	0x34	;# Clear Output Data Register
+set PIO_ODSR	0x38	;# Output Data Status Register
+set PIO_PDSR	0x3c	;# Pin Data Status Register
+set PIO_IER	0x40	;# Interrupt Enable Register
+set PIO_IDR	0x44	;# Interrupt Disable Register
+set PIO_IMR	0x48	;# Interrupt Mask Register
+set PIO_ISR	0x4c	;# Interrupt Status Register
+set PIO_MDER	0x50	;# Multi-driver Enable Register
+set PIO_MDDR	0x54	;# Multi-driver Disable Register
+set PIO_MDSR	0x58	;# Multi-driver Status Register
+set PIO_PUDR	0x60	;# Pull-up Disable Register
+set PIO_PUER	0x64	;# Pull-up Enable Register
+set PIO_PUSR	0x68	;# Pull-up Status Register
+set PIO_ASR	0x70	;# Peripheral A Select Register
+set PIO_BSR	0x74	;# Peripheral B Select Register
+set PIO_ABSR	0x78	;# AB Status Register
+set PIO_OWER	0xa0	;# Output Write Enable Register
+set PIO_OWDR	0xa4	;# Output Write Disable Register
+set PIO_OWSR	0xa8	;# Output Write Status Register
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_pmc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_pmc.cfg
new file mode 100644
index 0000000..a75cecd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_pmc.cfg
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set	AT91_PMC_SCER		[expr {$AT91_PMC + 0x00}]	;# System Clock Enable Register
+set	AT91_PMC_SCDR		[expr {$AT91_PMC + 0x04}]	;# System Clock Disable Register
+
+set	AT91_PMC_SCSR		[expr {$AT91_PMC + 0x08}]	;# System Clock Status Register
+set		AT91_PMC_PCK		[expr {1 <<  0}]		;# Processor Clock
+set		AT91RM9200_PMC_UDP	[expr {1 <<  1}]		;# USB Devcice Port Clock [AT91RM9200 only]
+set		AT91RM9200_PMC_MCKUDP	[expr {1 <<  2}]		;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
+set		AT91CAP9_PMC_DDR	[expr {1 <<  2}]		;# DDR Clock [CAP9 revC & some SAM9 only]
+set		AT91RM9200_PMC_UHP	[expr {1 <<  4}]		;# USB Host Port Clock [AT91RM9200 only]
+set		AT91SAM926x_PMC_UHP	[expr {1 <<  6}]		;# USB Host Port Clock [AT91SAM926x only]
+set		AT91CAP9_PMC_UHP	[expr {1 <<  6}]		;# USB Host Port Clock [AT91CAP9 only]
+set		AT91SAM926x_PMC_UDP	[expr {1 <<  7}]		;# USB Devcice Port Clock [AT91SAM926x only]
+set		AT91_PMC_PCK0		[expr {1 <<  8}]		;# Programmable Clock 0
+set		AT91_PMC_PCK1		[expr {1 <<  9}]		;# Programmable Clock 1
+set		AT91_PMC_PCK2		[expr {1 << 10}]		;# Programmable Clock 2
+set		AT91_PMC_PCK3		[expr {1 << 11}]		;# Programmable Clock 3
+set		AT91_PMC_HCK0		[expr {1 << 16}]		;# AHB Clock (USB host) [AT91SAM9261 only]
+set		AT91_PMC_HCK1		[expr {1 << 17}]		;# AHB Clock (LCD) [AT91SAM9261 only]
+
+set	AT91_PMC_PCER		[expr {$AT91_PMC + 0x10}]	;# Peripheral Clock Enable Register
+set	AT91_PMC_PCDR		[expr {$AT91_PMC + 0x14}]	;# Peripheral Clock Disable Register
+set	AT91_PMC_PCSR		[expr {$AT91_PMC + 0x18}]	;# Peripheral Clock Status Register
+
+set	AT91_CKGR_UCKR		[expr {$AT91_PMC + 0x1C}]	;# UTMI Clock Register [some SAM9, CAP9]
+set		AT91_PMC_UPLLEN		[expr {1   << 16}]		;# UTMI PLL Enable
+set		AT91_PMC_UPLLCOUNT	[expr {0xf << 20}]		;# UTMI PLL Start-up Time
+set		AT91_PMC_BIASEN		[expr {1   << 24}]		;# UTMI BIAS Enable
+set		AT91_PMC_BIASCOUNT	[expr {0xf << 28}]		;# UTMI BIAS Start-up Time
+
+set	AT91_CKGR_MOR		[expr {$AT91_PMC + 0x20}]	;# Main Oscillator Register [not on SAM9RL]
+set		AT91_PMC_MOSCEN		[expr {1    << 0}]		;# Main Oscillator Enable
+set		AT91_PMC_OSCBYPASS	[expr {1    << 1}]		;# Oscillator Bypass [SAM9x, CAP9]
+set		AT91_PMC_OSCOUNT	[expr {0xff << 8}]		;# Main Oscillator Start-up Time
+
+set	AT91_CKGR_MCFR		[expr {$AT91_PMC + 0x24}]	;# Main Clock Frequency Register
+set		AT91_PMC_MAINF		[expr {0xffff <<  0}]		;# Main Clock Frequency
+set		AT91_PMC_MAINRDY	[expr {1	<< 16}]		;# Main Clock Ready
+
+set	AT91_CKGR_PLLAR		[expr {$AT91_PMC + 0x28}]	;# PLL A Register
+set	AT91_CKGR_PLLBR		[expr {$AT91_PMC + 0x2c}]	;# PLL B Register
+set		AT91_PMC_DIV		[expr {0xff  <<  0}]		;# Divider
+set		AT91_PMC_PLLCOUNT	[expr {0x3f  <<  8}]		;# PLL Counter
+set		AT91_PMC_OUT		[expr {3     << 14}]		;# PLL Clock Frequency Range
+set		AT91_PMC_MUL		[expr {0x7ff << 16}]		;# PLL Multiplier
+set		AT91_PMC_USBDIV		[expr {3     << 28}]		;# USB Divisor (PLLB only)
+set			AT91_PMC_USBDIV_1		[expr {0 << 28}]
+set			AT91_PMC_USBDIV_2		[expr {1 << 28}]
+set			AT91_PMC_USBDIV_4		[expr {2 << 28}]
+set		AT91_PMC_USB96M		[expr {1     << 28}]		;# Divider by 2 Enable (PLLB only)
+set		AT91_PMC_PLLA_WR_ERRATA	[expr {1     << 29}]		;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
+
+set	AT91_PMC_MCKR		[expr {$AT91_PMC + 0x30}]	;# Master Clock Register
+set		AT91_PMC_CSS		[expr {3 <<  0}]		;# Master Clock Selection
+set			AT91_PMC_CSS_SLOW		[expr {0 << 0}]
+set			AT91_PMC_CSS_MAIN		[expr {1 << 0}]
+set			AT91_PMC_CSS_PLLA		[expr {2 << 0}]
+set			AT91_PMC_CSS_PLLB		[expr {3 << 0}]
+set			AT91_PMC_CSS_UPLL		[expr {3 << 0}]	;# [some SAM9 only]
+set		AT91_PMC_PRES		[expr {7 <<  2}]		;# Master Clock Prescaler
+set			AT91_PMC_PRES_1			[expr {0 << 2}]
+set			AT91_PMC_PRES_2			[expr {1 << 2}]
+set			AT91_PMC_PRES_4			[expr {2 << 2}]
+set			AT91_PMC_PRES_8			[expr {3 << 2}]
+set			AT91_PMC_PRES_16		[expr {4 << 2}]
+set			AT91_PMC_PRES_32		[expr {5 << 2}]
+set			AT91_PMC_PRES_64		[expr {6 << 2}]
+set		AT91_PMC_MDIV		[expr {3 <<  8}]		;# Master Clock Division
+set			AT91RM9200_PMC_MDIV_1		[expr {0 << 8}]	;# [AT91RM9200 only]
+set			AT91RM9200_PMC_MDIV_2		[expr {1 << 8}]
+set			AT91RM9200_PMC_MDIV_3		[expr {2 << 8}]
+set			AT91RM9200_PMC_MDIV_4		[expr {3 << 8}]
+set			AT91SAM9_PMC_MDIV_1		[expr {0 << 8}]	;# [SAM9,CAP9 only]
+set			AT91SAM9_PMC_MDIV_2		[expr {1 << 8}]
+set			AT91SAM9_PMC_MDIV_4		[expr {2 << 8}]
+set			AT91SAM9_PMC_MDIV_6		[expr {3 << 8}]	;# [some SAM9 only]
+set			AT91SAM9_PMC_MDIV_3		[expr {3 << 8}]	;# [some SAM9 only]
+set		AT91_PMC_PDIV		[expr {1 << 12}]		;# Processor Clock Division [some SAM9 only]
+set			AT91_PMC_PDIV_1			[expr {0 << 12}]
+set			AT91_PMC_PDIV_2			[expr {1 << 12}]
+set		AT91_PMC_PLLADIV2	[expr {1 << 12}]		;# PLLA divisor by 2 [some SAM9 only]
+set			AT91_PMC_PLLADIV2_OFF		[expr {0 << 12}]
+set			AT91_PMC_PLLADIV2_ON		[expr {1 << 12}]
+
+set	AT91_PMC_USB		[expr {$AT91_PMC + 0x38}]	;# USB Clock Register [some SAM9 only]
+set		AT91_PMC_USBS		[expr {0x1 <<  0}]		;# USB OHCI Input clock selection
+set			AT91_PMC_USBS_PLLA		[expr {0 << 0}]
+set			AT91_PMC_USBS_UPLL		[expr {1 << 0}]
+set		AT91_PMC_OHCIUSBDIV	[expr {0xF <<  8}]		;# Divider for USB OHCI Clock
+
+;# set	AT91_PMC_PCKR(n)	[expr {$AT91_PMC + 0x40 + ((n) * 4)}]	;# Programmable Clock 0-N Registers
+set		AT91_PMC_CSSMCK		[expr {0x1 <<  8}]		;# CSS or Master Clock Selection
+set			AT91_PMC_CSSMCK_CSS		[expr {0 << 8}]
+set			AT91_PMC_CSSMCK_MCK		[expr {1 << 8}]
+
+set	AT91_PMC_IER		[expr {$AT91_PMC + 0x60}]	;# Interrupt Enable Register
+set	AT91_PMC_IDR		[expr {$AT91_PMC + 0x64}]	;# Interrupt Disable Register
+set	AT91_PMC_SR		[expr {$AT91_PMC + 0x68}]	;# Status Register
+set		AT91_PMC_MOSCS		[expr {1 <<  0}]		;# MOSCS Flag
+set		AT91_PMC_LOCKA		[expr {1 <<  1}]		;# PLLA Lock
+set		AT91_PMC_LOCKB		[expr {1 <<  2}]		;# PLLB Lock
+set		AT91_PMC_MCKRDY		[expr {1 <<  3}]		;# Master Clock
+set		AT91_PMC_LOCKU		[expr {1 <<  6}]		;# UPLL Lock [some SAM9, AT91CAP9 only]
+set		AT91_PMC_OSCSEL		[expr {1 <<  7}]		;# Slow Clock Oscillator [AT91CAP9 revC only]
+set		AT91_PMC_PCK0RDY	[expr {1 <<  8}]		;# Programmable Clock 0
+set		AT91_PMC_PCK1RDY	[expr {1 <<  9}]		;# Programmable Clock 1
+set		AT91_PMC_PCK2RDY	[expr {1 << 10}]		;# Programmable Clock 2
+set		AT91_PMC_PCK3RDY	[expr {1 << 11}]		;# Programmable Clock 3
+set	AT91_PMC_IMR		[expr {$AT91_PMC + 0x6c}]	;# Interrupt Mask Register
+
+set AT91_PMC_PROT		[expr {$AT91_PMC + 0xe4}]	;# Protect Register [AT91CAP9 revC only]
+set		AT91_PMC_PROTKEY	0x504d4301	;# Activation Code
+
+set AT91_PMC_VER		[expr {$AT91_PMC + 0xfc}]	;# PMC Module Version [AT91CAP9 only]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_rstc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_rstc.cfg
new file mode 100644
index 0000000..fd17438
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_rstc.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AT91_RSTC_CR		[expr {$AT91_RSTC + 0x00}]	;# Reset Controller Control Register
+set		AT91_RSTC_PROCRST	[expr {1 << 0}]		;# Processor Reset
+set		AT91_RSTC_PERRST	[expr {1 << 2}]		;# Peripheral Reset
+set		AT91_RSTC_EXTRST	[expr {1 << 3}]		;# External Reset
+set		AT91_RSTC_KEY		[expr {0xa5 << 24}]		;# KEY Password
+
+set AT91_RSTC_SR		[expr {$AT91_RSTC + 0x04}]	;# Reset Controller Status Register
+set		AT91_RSTC_URSTS		[expr {1 << 0}]		;# User Reset Status
+set		AT91_RSTC_RSTTYP	[expr {7 << 8}]		;# Reset Type
+set			AT91_RSTC_RSTTYP_GENERAL	[expr {0 << 8}]
+set			AT91_RSTC_RSTTYP_WAKEUP		[expr {1 << 8}]
+set			AT91_RSTC_RSTTYP_WATCHDOG	[expr {2 << 8}]
+set			AT91_RSTC_RSTTYP_SOFTWARE	[expr {3 << 8}]
+set			AT91_RSTC_RSTTYP_USER	[expr {4 << 8}]
+set		AT91_RSTC_NRSTL		[expr {1 << 16}]		;# NRST Pin Level
+set		AT91_RSTC_SRCMP		[expr {1 << 17}]		;# Software Reset Command in Progress
+
+set AT91_RSTC_MR		[expr {$AT91_RSTC + 0x08}]	;# Reset Controller Mode Register
+set		AT91_RSTC_URSTEN	[expr {1 << 0}]		;# User Reset Enable
+set		AT91_RSTC_URSTIEN	[expr {1 << 4}]		;# User Reset Interrupt Enable
+set		AT91_RSTC_ERSTL		[expr {0xf << 8}]		;# External Reset Length
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_wdt.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_wdt.cfg
new file mode 100644
index 0000000..8bba62e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91_wdt.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AT91_WDT_CR		[expr {$AT91_WDT + 0x00}]	;# Watchdog Control Register
+set		AT91_WDT_WDRSTT		[expr {1    << 0}]	;# Restart
+set		AT91_WDT_KEY		[expr {0xa5 << 24}]	;# KEY Password
+
+set AT91_WDT_MR		[expr {$AT91_WDT + 0x04}]	;# Watchdog Mode Register
+set		AT91_WDT_WDV		[expr {0xfff << 0}]	;# Counter Value
+set		AT91_WDT_WDFIEN		[expr {1     << 12}]	;# Fault Interrupt Enable
+set		AT91_WDT_WDRSTEN	[expr {1     << 13}]	;# Reset Processor
+set		AT91_WDT_WDRPROC	[expr {1     << 14}]	;# Timer Restart
+set		AT91_WDT_WDDIS		[expr {1     << 15}]	;# Watchdog Disable
+set		AT91_WDT_WDD		[expr {0xfff << 16}]	;# Delta Value
+set		AT91_WDT_WDDBGHLT	[expr {1     << 28}]	;# Debug Halt
+set		AT91_WDT_WDIDLEHLT	[expr {1     << 29}]	;# Idle Halt
+
+set AT91_WDT_SR		[expr {$AT91_WDT + 0x08}]	;# Watchdog Status Register
+set		AT91_WDT_WDUNF		[expr {1 << 0}]		;# Watchdog Underflow
+set		AT91_WDT_WDERR		[expr {1 << 1}]		;# Watchdog Error
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam7x128.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam7x128.tcl
new file mode 100644
index 0000000..8f46827
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam7x128.tcl
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find bitsbytes.tcl]
+source [find cpu/arm/arm7tdmi.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+set CHIP_MAKER  atmel
+set CHIP_FAMILY at91sam7
+set CHIP_NAME   at91sam7x128
+# how many flash regions.
+set N_FLASH                1
+set FLASH(0,CHIPSELECT)    -1
+set FLASH(0,BASE)          0x00100000
+set FLASH(0,LEN)           $__128K
+set FLASH(0,HUMAN)         "internal flash"
+set FLASH(0,TYPE)          "flash"
+set FLASH(0,RWX)           $RWX_R_X
+set FLASH(0,ACCESS_WIDTH)  $ACCESS_WIDTH_ANY
+# how many ram regions.
+set N_RAM                  1
+set RAM(0,CHIPSELECT)      -1
+set RAM(0,BASE)            0x00200000
+set RAM(0,LEN)             $__32K
+set RAM(0,HUMAN)           "internal ram"
+set RAM(0,TYPE)            "ram"
+set RAM(0,RWX)             $RWX_RWX
+set RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# I AM LAZY... I create 1 region for all MMRs.
+set N_MMREGS    1
+set MMREGS(0,CHIPSELECT)      -1
+set MMREGS(0,BASE)            0xfff00000
+set MMREGS(0,LEN)             0x000fffff
+set MMREGS(0,HUMAN)           "mm-regs"
+set MMREGS(0,TYPE)            "mmr"
+set MMREGS(0,RWX)             $RWX_RW
+set MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# no external memory
+set N_XMEM 0
+
+
+
+
+set AT91C_BASE_SYS       0xFFFFF000
+set AT91C_BASE_AIC       0xFFFFF000
+set AT91C_BASE_PDC_DBGU  0xFFFFF300
+set AT91C_BASE_DBGU      0xFFFFF200
+set AT91C_BASE_PIOA      0xFFFFF400
+set AT91C_BASE_PIOB      0xFFFFF600
+set AT91C_BASE_CKGR      0xFFFFFC20
+set AT91C_BASE_PMC       0xFFFFFC00
+set AT91C_BASE_RSTC      0xFFFFFD00
+set AT91C_BASE_RTTC      0xFFFFFD20
+set AT91C_BASE_PITC      0xFFFFFD30
+set AT91C_BASE_WDTC      0xFFFFFD40
+set AT91C_BASE_VREG      0xFFFFFD60
+set AT91C_BASE_MC        0xFFFFFF00
+set AT91C_BASE_PDC_SPI1  0xFFFE4100
+set AT91C_BASE_SPI1      0xFFFE4000
+set AT91C_BASE_PDC_SPI0  0xFFFE0100
+set AT91C_BASE_SPI0      0xFFFE0000
+set AT91C_BASE_PDC_US1   0xFFFC4100
+set AT91C_BASE_US1       0xFFFC4000
+set AT91C_BASE_PDC_US0   0xFFFC0100
+set AT91C_BASE_US0       0xFFFC0000
+set AT91C_BASE_PDC_SSC   0xFFFD4100
+set AT91C_BASE_SSC       0xFFFD4000
+set AT91C_BASE_TWI       0xFFFB8000
+set AT91C_BASE_PWMC_CH3  0xFFFCC260
+set AT91C_BASE_PWMC_CH2  0xFFFCC240
+set AT91C_BASE_PWMC_CH1  0xFFFCC220
+set AT91C_BASE_PWMC_CH0  0xFFFCC200
+set AT91C_BASE_PWMC      0xFFFCC000
+set AT91C_BASE_UDP       0xFFFB0000
+set AT91C_BASE_TC0       0xFFFA0000
+set AT91C_BASE_TC1       0xFFFA0040
+set AT91C_BASE_TC2       0xFFFA0080
+set AT91C_BASE_TCB       0xFFFA0000
+set AT91C_BASE_CAN_MB0   0xFFFD0200
+set AT91C_BASE_CAN_MB1   0xFFFD0220
+set AT91C_BASE_CAN_MB2   0xFFFD0240
+set AT91C_BASE_CAN_MB3   0xFFFD0260
+set AT91C_BASE_CAN_MB4   0xFFFD0280
+set AT91C_BASE_CAN_MB5   0xFFFD02A0
+set AT91C_BASE_CAN_MB6   0xFFFD02C0
+set AT91C_BASE_CAN_MB7   0xFFFD02E0
+set AT91C_BASE_CAN       0xFFFD0000
+set AT91C_BASE_EMAC      0xFFFDC000
+set AT91C_BASE_PDC_ADC   0xFFFD8100
+set AT91C_BASE_ADC       0xFFFD8000
+
+set AT91C_ID(0) FIQ
+set AT91C_ID(1) SYS
+set AT91C_ID(2) PIOA
+set AT91C_ID(3) PIOB
+set AT91C_ID(4) SPI0
+set AT91C_ID(5) SPI1
+set AT91C_ID(6) US0
+set AT91C_ID(7) US1
+set AT91C_ID(8) SSC
+set AT91C_ID(9) TWI
+set AT91C_ID(10) PWMC
+set AT91C_ID(11) UDP
+set AT91C_ID(12) TC0
+set AT91C_ID(13) TC1
+set AT91C_ID(14) TC2
+set AT91C_ID(15) CAN
+set AT91C_ID(16) EMAC
+set AT91C_ID(17) ADC
+set AT91C_ID(18) ""
+set AT91C_ID(19) ""
+set AT91C_ID(20) ""
+set AT91C_ID(21) ""
+set AT91C_ID(22) ""
+set AT91C_ID(23) ""
+set AT91C_ID(24) ""
+set AT91C_ID(25) ""
+set AT91C_ID(26) ""
+set AT91C_ID(27) ""
+set AT91C_ID(28) ""
+set AT91C_ID(29) ""
+set AT91C_ID(30) IRQ0
+set AT91C_ID(31) IRQ1
+
+source [find chip/atmel/at91/aic.tcl]
+source [find chip/atmel/at91/usarts.tcl]
+source [find chip/atmel/at91/pmc.tcl]
+source [find chip/atmel/at91/rtt.tcl]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam7x256.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam7x256.tcl
new file mode 100644
index 0000000..49d5244
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam7x256.tcl
@@ -0,0 +1,128 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find bitsbytes.tcl]
+source [find cpu/arm/arm7tdmi.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+set CHIP_MAKER  atmel
+set CHIP_FAMILY at91sam7
+set CHIP_NAME   at91sam7x256
+# how many flash regions.
+set N_FLASH                1
+set FLASH(0,CHIPSELECT)    -1
+set FLASH(0,BASE)          0x00100000
+set FLASH(0,LEN)           $__256K
+set FLASH(0,HUMAN)         "internal flash"
+set FLASH(0,TYPE)          "flash"
+set FLASH(0,RWX)           $RWX_R_X
+set FLASH(0,ACCESS_WIDTH)  $ACCESS_WIDTH_ANY
+# how many ram regions.
+set N_RAM                  1
+set RAM(0,CHIPSELECT)      -1
+set RAM(0,BASE)            0x00200000
+set RAM(0,LEN)             $__64K
+set RAM(0,HUMAN)           "internal ram"
+set RAM(0,TYPE)            "ram"
+set RAM(0,RWX)             $RWX_RWX
+set RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# I AM LAZY... I create 1 region for all MMRs.
+set N_MMREGS    1
+set MMREGS(0,CHIPSELECT)      -1
+set MMREGS(0,BASE)            0xfff00000
+set MMREGS(0,LEN)             0x000fffff
+set MMREGS(0,HUMAN)           "mm-regs"
+set MMREGS(0,TYPE)            "mmr"
+set MMREGS(0,RWX)             $RWX_RW
+set MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# no external memory
+set N_XMEM 0
+
+set  AT91C_BASE_SYS              0xFFFFF000
+set  AT91C_BASE_AIC              0xFFFFF000
+set  AT91C_BASE_PDC_DBGU         0xFFFFF300
+set  AT91C_BASE_DBGU             0xFFFFF200
+set  AT91C_BASE_PIOA             0xFFFFF400
+set  AT91C_BASE_PIOB             0xFFFFF600
+set  AT91C_BASE_CKGR             0xFFFFFC20
+set  AT91C_BASE_PMC              0xFFFFFC00
+set  AT91C_BASE_RSTC             0xFFFFFD00
+set  AT91C_BASE_RTTC             0xFFFFFD20
+set  AT91C_BASE_PITC             0xFFFFFD30
+set  AT91C_BASE_WDTC             0xFFFFFD40
+set  AT91C_BASE_VREG             0xFFFFFD60
+set  AT91C_BASE_MC          0xFFFFFF00
+set  AT91C_BASE_PDC_SPI1      0xFFFE4100
+set  AT91C_BASE_SPI1          0xFFFE4000
+set  AT91C_BASE_PDC_SPI0      0xFFFE0100
+set  AT91C_BASE_SPI0          0xFFFE0000
+set  AT91C_BASE_PDC_US1       0xFFFC4100
+set  AT91C_BASE_US1           0xFFFC4000
+set  AT91C_BASE_PDC_US0       0xFFFC0100
+set  AT91C_BASE_US0           0xFFFC0000
+set  AT91C_BASE_PDC_SSC       0xFFFD4100
+set  AT91C_BASE_SSC           0xFFFD4000
+set  AT91C_BASE_TWI           0xFFFB8000
+set  AT91C_BASE_PWMC_CH3      0xFFFCC260
+set  AT91C_BASE_PWMC_CH2      0xFFFCC240
+set  AT91C_BASE_PWMC_CH1      0xFFFCC220
+set  AT91C_BASE_PWMC_CH0      0xFFFCC200
+set  AT91C_BASE_PWMC          0xFFFCC000
+set  AT91C_BASE_UDP           0xFFFB0000
+set  AT91C_BASE_TC0         0xFFFA0000
+set  AT91C_BASE_TC1         0xFFFA0040
+set  AT91C_BASE_TC2         0xFFFA0080
+set  AT91C_BASE_TCB             0xFFFA0000
+set  AT91C_BASE_CAN_MB0         0xFFFD0200
+set  AT91C_BASE_CAN_MB1         0xFFFD0220
+set  AT91C_BASE_CAN_MB2         0xFFFD0240
+set  AT91C_BASE_CAN_MB3         0xFFFD0260
+set  AT91C_BASE_CAN_MB4         0xFFFD0280
+set  AT91C_BASE_CAN_MB5         0xFFFD02A0
+set  AT91C_BASE_CAN_MB6         0xFFFD02C0
+set  AT91C_BASE_CAN_MB7         0xFFFD02E0
+set  AT91C_BASE_CAN             0xFFFD0000
+set  AT91C_BASE_EMAC            0xFFFDC000
+set  AT91C_BASE_PDC_ADC         0xFFFD8100
+set  AT91C_BASE_ADC             0xFFFD8000
+
+set AT91C_ID(0)   "FIQ"
+set AT91C_ID(1)   "SYS"
+set AT91C_ID(2)   "PIOA"
+set AT91C_ID(3)   "PIOB"
+set AT91C_ID(4)   "SPI0"
+set AT91C_ID(5)   "SPI1"
+set AT91C_ID(6)   "US0"
+set AT91C_ID(7)   "US1"
+set AT91C_ID(8)   "SSC"
+set AT91C_ID(9)   "TWI"
+set AT91C_ID(10)   "PWMC"
+set AT91C_ID(11)   "UDP"
+set AT91C_ID(12)   "TC0"
+set AT91C_ID(13)   "TC1"
+set AT91C_ID(14)   "TC2"
+set AT91C_ID(15)   "CAN"
+set AT91C_ID(16)   "EMAC"
+set AT91C_ID(17)   "ADC"
+set AT91C_ID(18)   ""
+set AT91C_ID(19)   ""
+set AT91C_ID(20)   ""
+set AT91C_ID(21)   ""
+set AT91C_ID(22)   ""
+set AT91C_ID(23)   ""
+set AT91C_ID(24)   ""
+set AT91C_ID(25)   ""
+set AT91C_ID(26)   ""
+set AT91C_ID(27)   ""
+set AT91C_ID(28)   ""
+set AT91C_ID(29)   ""
+set AT91C_ID(30)   "IRQ0"
+set AT91C_ID(31)   "IRQ1"
+
+
+source [find chip/atmel/at91/aic.tcl]
+source [find chip/atmel/at91/usarts.tcl]
+source [find chip/atmel/at91/pmc.tcl]
+source [find chip/atmel/at91/rtt.tcl]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9261.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9261.cfg
new file mode 100644
index 0000000..51e7101
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9261.cfg
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Peripheral identifiers/interrupts.
+#
+set AT91_ID_FIQ		0	;# Advanced Interrupt Controller (FIQ)
+set AT91_ID_SYS		1	;# System Peripherals
+set AT91SAM9261_ID_PIOA	2	;# Parallel IO Controller A
+set AT91SAM9261_ID_PIOB	3	;# Parallel IO Controller B
+set AT91SAM9261_ID_PIOC	4	;# Parallel IO Controller C
+set AT91SAM9261_ID_US0	6	;# USART 0
+set AT91SAM9261_ID_US1	7	;# USART 1
+set AT91SAM9261_ID_US2	8	;# USART 2
+set AT91SAM9261_ID_MCI	9	;# Multimedia Card Interface
+set AT91SAM9261_ID_UDP	10	;# USB Device Port
+set AT91SAM9261_ID_TWI	11	;# Two-Wire Interface
+set AT91SAM9261_ID_SPI0	12	;# Serial Peripheral Interface 0
+set AT91SAM9261_ID_SPI1	13	;# Serial Peripheral Interface 1
+set AT91SAM9261_ID_SSC0	14	;# Serial Synchronous Controller 0
+set AT91SAM9261_ID_SSC1	15	;# Serial Synchronous Controller 1
+set AT91SAM9261_ID_SSC2	16	;# Serial Synchronous Controller 2
+set AT91SAM9261_ID_TC0	17	;# Timer Counter 0
+set AT91SAM9261_ID_TC1	18	;# Timer Counter 1
+set AT91SAM9261_ID_TC2	19	;# Timer Counter 2
+set AT91SAM9261_ID_UHP	20	;# USB Host port
+set AT91SAM9261_ID_LCDC	21	;# LDC Controller
+set AT91SAM9261_ID_IRQ0	29	;# Advanced Interrupt Controller (IRQ0)
+set AT91SAM9261_ID_IRQ1	30	;# Advanced Interrupt Controller (IRQ1)
+set AT91SAM9261_ID_IRQ2	31	;# Advanced Interrupt Controller (IRQ2)
+
+
+#
+# User Peripheral physical base addresses.
+#
+set AT91SAM9261_BASE_TCB0		0xfffa0000
+set AT91SAM9261_BASE_TC0		0xfffa0000
+set AT91SAM9261_BASE_TC1		0xfffa0040
+set AT91SAM9261_BASE_TC2		0xfffa0080
+set AT91SAM9261_BASE_UDP		0xfffa4000
+set AT91SAM9261_BASE_MCI		0xfffa8000
+set AT91SAM9261_BASE_TWI		0xfffac000
+set AT91SAM9261_BASE_US0		0xfffb0000
+set AT91SAM9261_BASE_US1		0xfffb4000
+set AT91SAM9261_BASE_US2		0xfffb8000
+set AT91SAM9261_BASE_SSC0		0xfffbc000
+set AT91SAM9261_BASE_SSC1		0xfffc0000
+set AT91SAM9261_BASE_SSC2		0xfffc4000
+set AT91SAM9261_BASE_SPI0		0xfffc8000
+set AT91SAM9261_BASE_SPI1		0xfffcc000
+set AT91_BASE_SYS			0xffffea00
+
+
+#
+# System Peripherals (offset from AT91_BASE_SYS)
+#
+set AT91_SDRAMC	0xffffea00
+set AT91_SMC	0xffffec00
+set AT91_MATRIX	0xffffee00
+set AT91_AIC	0xfffff000
+set AT91_DBGU	0xfffff200
+set AT91_PIOA	0xfffff400
+set AT91_PIOB	0xfffff600
+set AT91_PIOC	0xfffff800
+set AT91_PMC	0xfffffc00
+set AT91_RSTC	0xfffffd00
+set AT91_SHDWC	0xfffffd10
+set AT91_RTT	0xfffffd20
+set AT91_PIT	0xfffffd30
+set AT91_WDT	0xfffffd40
+set AT91_GPBR	0xfffffd50
+
+set AT91_USART0	$AT91SAM9261_BASE_US0
+set AT91_USART1	$AT91SAM9261_BASE_US1
+set AT91_USART2	$AT91SAM9261_BASE_US2
+
+
+#
+# Internal Memory.
+#
+set AT91SAM9261_SRAM_BASE	0x00300000	;# Internal SRAM base address
+set AT91SAM9261_SRAM_SIZE	0x00028000	;# Internal SRAM size (160Kb)
+
+set AT91SAM9261_ROM_BASE	0x00400000	;# Internal ROM base address
+set AT91SAM9261_ROM_SIZE	0x00008000	;# Internal ROM size (32Kb)
+
+set AT91SAM9261_UHP_BASE	0x00500000	;# USB Host controller
+set AT91SAM9261_LCDC_BASE	0x00600000	;# LDC controller
+
+#
+# Cpu Name
+#
+set AT91_CPU_NAME	"AT91SAM9261"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9261_matrix.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9261_matrix.cfg
new file mode 100644
index 0000000..c3656bd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9261_matrix.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AT91_MATRIX_MCFG	[expr {$AT91_MATRIX + 0x00}]	;# Master Configuration Register #
+set		AT91_MATRIX_RCB0	[expr {1 << 0}]		;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
+set		AT91_MATRIX_RCB1	[expr {1 << 1}]		;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
+
+set AT91_MATRIX_SCFG0	[expr {$AT91_MATRIX + 0x04}]	;# Slave Configuration Register 0
+set AT91_MATRIX_SCFG1	[expr {$AT91_MATRIX + 0x08}]	;# Slave Configuration Register 1
+set AT91_MATRIX_SCFG2	[expr {$AT91_MATRIX + 0x0C}]	;# Slave Configuration Register 2
+set AT91_MATRIX_SCFG3	[expr {$AT91_MATRIX + 0x10}]	;# Slave Configuration Register 3
+set AT91_MATRIX_SCFG4	[expr {$AT91_MATRIX + 0x14}]	;# Slave Configuration Register 4
+set		AT91_MATRIX_SLOT_CYCLE		[expr {0xff << 0}]	;# Maximum Number of Allowed Cycles for a Burst
+set		AT91_MATRIX_DEFMSTR_TYPE	[expr {3    << 16}]	;# Default Master Type
+set			AT91_MATRIX_DEFMSTR_TYPE_NONE	[expr {0 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_LAST	[expr {1 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_FIXED	[expr {2 << 16}]
+set		AT91_MATRIX_FIXED_DEFMSTR	[expr {7    << 18}]	;# Fixed Index of Default Master
+
+set AT91_MATRIX_TCR		[expr {$AT91_MATRIX + 0x24}]	;# TCM Configuration Register
+set		AT91_MATRIX_ITCM_SIZE		[expr {0xf << 0}]	;# Size of ITCM enabled memory block
+set			AT91_MATRIX_ITCM_0		[expr {0 << 0}]
+set			AT91_MATRIX_ITCM_16		[expr {5 << 0}]
+set			AT91_MATRIX_ITCM_32		[expr {6 << 0}]
+set			AT91_MATRIX_ITCM_64		[expr {7 << 0}]
+set		AT91_MATRIX_DTCM_SIZE		[expr {0xf << 4}]	;# Size of DTCM enabled memory block
+set			AT91_MATRIX_DTCM_0		[expr {0 << 4}]
+set			AT91_MATRIX_DTCM_16		[expr {5 << 4}]
+set			AT91_MATRIX_DTCM_32		[expr {6 << 4}]
+set			AT91_MATRIX_DTCM_64		[expr {7 << 4}]
+
+set AT91_MATRIX_EBICSA	[expr {$AT91_MATRIX + 0x30}]	;# EBI Chip Select Assignment Register
+set		AT91_MATRIX_CS1A		[expr {1 << 1}]	;# Chip Select 1 Assignment
+set			AT91_MATRIX_CS1A_SMC		[expr {0 << 1}]
+set			AT91_MATRIX_CS1A_SDRAMC		[expr {1 << 1}]
+set		AT91_MATRIX_CS3A		[expr {1 << 3}]	;# Chip Select 3 Assignment
+set			AT91_MATRIX_CS3A_SMC		[expr {0 << 3}]
+set			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	[expr {1 << 3}]
+set		AT91_MATRIX_CS4A		[expr {1 << 4}]	;# Chip Select 4 Assignment
+set			AT91_MATRIX_CS4A_SMC		[expr {0 << 4}]
+set			AT91_MATRIX_CS4A_SMC_CF1	[expr {1 << 4}]
+set		AT91_MATRIX_CS5A		[expr {1 << 5}]	;# Chip Select 5 Assignment
+set			AT91_MATRIX_CS5A_SMC		[expr {0 << 5}]
+set			AT91_MATRIX_CS5A_SMC_CF2	[expr {1 << 5}]
+set		AT91_MATRIX_DBPUC		[expr {1 << 8}]	;# Data Bus Pull-up Configuration
+
+set AT91_MATRIX_USBPUCR	[expr {$AT91_MATRIX + 0x34}]	;# USB Pad Pull-Up Control Register
+set		AT91_MATRIX_USBPUCR_PUON	[expr {1 << 30}]	;# USB Device PAD Pull-up Enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9263.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9263.cfg
new file mode 100644
index 0000000..600c548
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9263.cfg
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Peripheral identifiers/interrupts.
+#
+set AT91_ID_FIQ		0	;# Advanced Interrupt Controller (FIQ)
+set AT91_ID_SYS		1	;# System Peripherals
+set AT91SAM9263_ID_PIOA	2	;# Parallel IO Controller A
+set AT91SAM9263_ID_PIOB	3	;# Parallel IO Controller B
+set AT91SAM9263_ID_PIOCDE	4	;# Parallel IO Controller C, D and E
+set AT91SAM9263_ID_US0	7	;# USART 0
+set AT91SAM9263_ID_US1	8	;# USART 1
+set AT91SAM9263_ID_US2	9	;# USART 2
+set AT91SAM9263_ID_MCI0	10	;# Multimedia Card Interface 0
+set AT91SAM9263_ID_MCI1	11	;# Multimedia Card Interface 1
+set AT91SAM9263_ID_CAN	12	;# CAN
+set AT91SAM9263_ID_TWI	13	;# Two-Wire Interface
+set AT91SAM9263_ID_SPI0	14	;# Serial Peripheral Interface 0
+set AT91SAM9263_ID_SPI1	15	;# Serial Peripheral Interface 1
+set AT91SAM9263_ID_SSC0	16	;# Serial Synchronous Controller 0
+set AT91SAM9263_ID_SSC1	17	;# Serial Synchronous Controller 1
+set AT91SAM9263_ID_AC97C	18	;# AC97 Controller
+set AT91SAM9263_ID_TCB	19	;# Timer Counter 0, 1 and 2
+set AT91SAM9263_ID_PWMC	20	;# Pulse Width Modulation Controller
+set AT91SAM9263_ID_EMAC	21	;# Ethernet
+set AT91SAM9263_ID_2DGE	23	;# 2D Graphic Engine
+set AT91SAM9263_ID_UDP	24	;# USB Device Port
+set AT91SAM9263_ID_ISI	25	;# Image Sensor Interface
+set AT91SAM9263_ID_LCDC	26	;# LCD Controller
+set AT91SAM9263_ID_DMA	27	;# DMA Controller
+set AT91SAM9263_ID_UHP	29	;# USB Host port
+set AT91SAM9263_ID_IRQ0	30	;# Advanced Interrupt Controller (IRQ0)
+set AT91SAM9263_ID_IRQ1	31	;# Advanced Interrupt Controller (IRQ1)
+
+
+#
+# User Peripheral physical base addresses.
+#
+set AT91SAM9263_BASE_UDP		0xfff78000
+set AT91SAM9263_BASE_TCB0		0xfff7c000
+set AT91SAM9263_BASE_TC0		0xfff7c000
+set AT91SAM9263_BASE_TC1		0xfff7c040
+set AT91SAM9263_BASE_TC2		0xfff7c080
+set AT91SAM9263_BASE_MCI0		0xfff80000
+set AT91SAM9263_BASE_MCI1		0xfff84000
+set AT91SAM9263_BASE_TWI		0xfff88000
+set AT91SAM9263_BASE_US0		0xfff8c000
+set AT91SAM9263_BASE_US1		0xfff90000
+set AT91SAM9263_BASE_US2		0xfff94000
+set AT91SAM9263_BASE_SSC0		0xfff98000
+set AT91SAM9263_BASE_SSC1		0xfff9c000
+set AT91SAM9263_BASE_AC97C		0xfffa0000
+set AT91SAM9263_BASE_SPI0		0xfffa4000
+set AT91SAM9263_BASE_SPI1		0xfffa8000
+set AT91SAM9263_BASE_CAN		0xfffac000
+set AT91SAM9263_BASE_PWMC		0xfffb8000
+set AT91SAM9263_BASE_EMAC		0xfffbc000
+set AT91SAM9263_BASE_ISI		0xfffc4000
+set AT91SAM9263_BASE_2DGE		0xfffc8000
+set AT91_BASE_SYS			0xffffe000
+
+#
+# System Peripherals (offset from AT91_BASE_SYS)
+#
+set AT91_ECC0		0xffffe000
+set AT91_SDRAMC0	0xffffe200
+set AT91_SMC0		0xffffe400
+set AT91_ECC1		0xffffe600
+set AT91_SDRAMC1	0xffffe800
+set AT91_SMC1		0xffffea00
+set AT91_MATRIX		0xffffec00
+set AT91_CCFG		0xffffed10
+set AT91_DBGU		0xffffee00
+set AT91_AIC		0xfffff000
+set AT91_PIOA		0xfffff200
+set AT91_PIOB		0xfffff400
+set AT91_PIOC		0xfffff600
+set AT91_PIOD		0xfffff800
+set AT91_PIOE		0xfffffa00
+set AT91_PMC		0xfffffc00
+set AT91_RSTC		0xfffffd00
+set AT91_SHDWC		0xfffffd10
+set AT91_RTT0		0xfffffd20
+set AT91_PIT		0xfffffd30
+set AT91_WDT		0xfffffd40
+set AT91_RTT1		0xfffffd50
+set AT91_GPBR		0xfffffd60
+
+set AT91_USART0	$AT91SAM9263_BASE_US0
+set AT91_USART1	$AT91SAM9263_BASE_US1
+set AT91_USART2	$AT91SAM9263_BASE_US2
+
+set AT91_SMC	$AT91_SMC0
+set AT91_SDRAMC	$AT91_SDRAMC0
+
+#
+# Internal Memory.
+#
+set AT91SAM9263_SRAM0_BASE	0x00300000	;# Internal SRAM 0 base address
+set AT91SAM9263_SRAM0_SIZE	0x00014000	;# Internal SRAM 0 size (80Kb)
+
+set AT91SAM9263_ROM_BASE	0x00400000	;# Internal ROM base address
+set AT91SAM9263_ROM_SIZE	0x00020000	;# Internal ROM size (128Kb)
+
+set AT91SAM9263_SRAM1_BASE	0x00500000	;# Internal SRAM 1 base address
+set AT91SAM9263_SRAM1_SIZE	0x00004000	;# Internal SRAM 1 size (16Kb)
+
+set AT91SAM9263_LCDC_BASE	0x00700000	;# LCD Controller
+set AT91SAM9263_DMAC_BASE	0x00800000	;# DMA Controller
+set AT91SAM9263_UHP_BASE	0x00a00000	;# USB Host controller
+
+#
+# Cpu Name
+#
+set AT91_CPU_NAME	"AT91SAM9263"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9263_matrix.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9263_matrix.cfg
new file mode 100644
index 0000000..20a3107
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9263_matrix.cfg
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set AT91_MATRIX_MCFG0	[expr {$AT91_MATRIX + 0x00}]	;# Master Configuration Register 0
+set AT91_MATRIX_MCFG1	[expr {$AT91_MATRIX + 0x04}]	;# Master Configuration Register 1
+set AT91_MATRIX_MCFG2	[expr {$AT91_MATRIX + 0x08}]	;# Master Configuration Register 2
+set AT91_MATRIX_MCFG3	[expr {$AT91_MATRIX + 0x0C}]	;# Master Configuration Register 3
+set AT91_MATRIX_MCFG4	[expr {$AT91_MATRIX + 0x10}]	;# Master Configuration Register 4
+set AT91_MATRIX_MCFG5	[expr {$AT91_MATRIX + 0x14}]	;# Master Configuration Register 5
+set AT91_MATRIX_MCFG6	[expr {$AT91_MATRIX + 0x18}]	;# Master Configuration Register 6
+set AT91_MATRIX_MCFG7	[expr {$AT91_MATRIX + 0x1C}]	;# Master Configuration Register 7
+set AT91_MATRIX_MCFG8	[expr {$AT91_MATRIX + 0x20}]	;# Master Configuration Register 8
+set		AT91_MATRIX_ULBT	[expr {7 << 0}]	;# Undefined Length Burst Type
+set			AT91_MATRIX_ULBT_INFINITE	[expr {0 << 0}]
+set			AT91_MATRIX_ULBT_SINGLE		[expr {1 << 0}]
+set			AT91_MATRIX_ULBT_FOUR		[expr {2 << 0}]
+set			AT91_MATRIX_ULBT_EIGHT		[expr {3 << 0}]
+set			AT91_MATRIX_ULBT_SIXTEEN	[expr {4 << 0}]
+
+set AT91_MATRIX_SCFG0	[expr {$AT91_MATRIX + 0x40}]	;# Slave Configuration Register 0
+set AT91_MATRIX_SCFG1	[expr {$AT91_MATRIX + 0x44}]	;# Slave Configuration Register 1
+set AT91_MATRIX_SCFG2	[expr {$AT91_MATRIX + 0x48}]	;# Slave Configuration Register 2
+set AT91_MATRIX_SCFG3	[expr {$AT91_MATRIX + 0x4C}]	;# Slave Configuration Register 3
+set AT91_MATRIX_SCFG4	[expr {$AT91_MATRIX + 0x50}]	;# Slave Configuration Register 4
+set AT91_MATRIX_SCFG5	[expr {$AT91_MATRIX + 0x54}]	;# Slave Configuration Register 5
+set AT91_MATRIX_SCFG6	[expr {$AT91_MATRIX + 0x58}]	;# Slave Configuration Register 6
+set AT91_MATRIX_SCFG7	[expr {$AT91_MATRIX + 0x5C}]	;# Slave Configuration Register 7
+set		AT91_MATRIX_SLOT_CYCLE		[expr {0xff << 0}]	;# Maximum Number of Allowed Cycles for a Burst
+set		AT91_MATRIX_DEFMSTR_TYPE	[expr {3    << 16}]	;# Default Master Type
+set			AT91_MATRIX_DEFMSTR_TYPE_NONE	[expr {0 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_LAST	[expr {1 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_FIXED	[expr {2 << 16}]
+set		AT91_MATRIX_FIXED_DEFMSTR	[expr {0xf  << 18}]	;# Fixed Index of Default Master
+set		AT91_MATRIX_ARBT		[expr {3    << 24}]	;# Arbitration Type
+set			AT91_MATRIX_ARBT_ROUND_ROBIN	[expr {0 << 24}]
+set			AT91_MATRIX_ARBT_FIXED_PRIORITY	[expr {1 << 24}]
+
+set AT91_MATRIX_PRAS0	[expr {$AT91_MATRIX + 0x80}]	;# Priority Register A for Slave 0
+set AT91_MATRIX_PRBS0	[expr {$AT91_MATRIX + 0x84}]	;# Priority Register B for Slave 0
+set AT91_MATRIX_PRAS1	[expr {$AT91_MATRIX + 0x88}]	;# Priority Register A for Slave 1
+set AT91_MATRIX_PRBS1	[expr {$AT91_MATRIX + 0x8C}]	;# Priority Register B for Slave 1
+set AT91_MATRIX_PRAS2	[expr {$AT91_MATRIX + 0x90}]	;# Priority Register A for Slave 2
+set AT91_MATRIX_PRBS2	[expr {$AT91_MATRIX + 0x94}]	;# Priority Register B for Slave 2
+set AT91_MATRIX_PRAS3	[expr {$AT91_MATRIX + 0x98}]	;# Priority Register A for Slave 3
+set AT91_MATRIX_PRBS3	[expr {$AT91_MATRIX + 0x9C}]	;# Priority Register B for Slave 3
+set AT91_MATRIX_PRAS4	[expr {$AT91_MATRIX + 0xA0}]	;# Priority Register A for Slave 4
+set AT91_MATRIX_PRBS4	[expr {$AT91_MATRIX + 0xA4}]	;# Priority Register B for Slave 4
+set AT91_MATRIX_PRAS5	[expr {$AT91_MATRIX + 0xA8}]	;# Priority Register A for Slave 5
+set AT91_MATRIX_PRBS5	[expr {$AT91_MATRIX + 0xAC}]	;# Priority Register B for Slave 5
+set AT91_MATRIX_PRAS6	[expr {$AT91_MATRIX + 0xB0}]	;# Priority Register A for Slave 6
+set AT91_MATRIX_PRBS6	[expr {$AT91_MATRIX + 0xB4}]	;# Priority Register B for Slave 6
+set AT91_MATRIX_PRAS7	[expr {$AT91_MATRIX + 0xB8}]	;# Priority Register A for Slave 7
+set AT91_MATRIX_PRBS7	[expr {$AT91_MATRIX + 0xBC}]	;# Priority Register B for Slave 7
+set		AT91_MATRIX_M0PR		[expr {3 << 0}]		;# Master 0 Priority
+set		AT91_MATRIX_M1PR		[expr {3 << 4}]		;# Master 1 Priority
+set		AT91_MATRIX_M2PR		[expr {3 << 8}]		;# Master 2 Priority
+set		AT91_MATRIX_M3PR		[expr {3 << 12}]	;# Master 3 Priority
+set		AT91_MATRIX_M4PR		[expr {3 << 16}]	;# Master 4 Priority
+set		AT91_MATRIX_M5PR		[expr {3 << 20}]	;# Master 5 Priority
+set		AT91_MATRIX_M6PR		[expr {3 << 24}]	;# Master 6 Priority
+set		AT91_MATRIX_M7PR		[expr {3 << 28}]	;# Master 7 Priority
+set		AT91_MATRIX_M8PR		[expr {3 << 0}]		;# Master 8 Priority (in Register B)
+
+set AT91_MATRIX_MRCR	[expr {$AT91_MATRIX + 0x100}]	;# Master Remap Control Register
+set		AT91_MATRIX_RCB0		[expr {1 << 0}]	;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
+set		AT91_MATRIX_RCB1		[expr {1 << 1}]	;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
+set		AT91_MATRIX_RCB2		[expr {1 << 2}]
+set		AT91_MATRIX_RCB3		[expr {1 << 3}]
+set		AT91_MATRIX_RCB4		[expr {1 << 4}]
+set		AT91_MATRIX_RCB5		[expr {1 << 5}]
+set		AT91_MATRIX_RCB6		[expr {1 << 6}]
+set		AT91_MATRIX_RCB7		[expr {1 << 7}]
+set		AT91_MATRIX_RCB8		[expr {1 << 8}]
+
+set AT91_MATRIX_TCMR	[expr {$AT91_MATRIX + 0x114}]	;# TCM Configuration Register
+set		AT91_MATRIX_ITCM_SIZE		[expr {0xf << 0}]	;# Size of ITCM enabled memory block
+set			AT91_MATRIX_ITCM_0		[expr {0 << 0}]
+set			AT91_MATRIX_ITCM_16		[expr {5 << 0}]
+set			AT91_MATRIX_ITCM_32		[expr {6 << 0}]
+set		AT91_MATRIX_DTCM_SIZE		[expr {0xf << 4}]	;# Size of DTCM enabled memory block
+set			AT91_MATRIX_DTCM_0		[expr {0 << 4}]
+set			AT91_MATRIX_DTCM_16		[expr {5 << 4}]
+set			AT91_MATRIX_DTCM_32		[expr {6 << 4}]
+
+set AT91_MATRIX_EBI0CSA	[expr {$AT91_MATRIX + 0x120}]	;# EBI0 Chip Select Assignment Register
+set		AT91_MATRIX_EBI0_CS1A		[expr {1 << 1}]	;# Chip Select 1 Assignment
+set			AT91_MATRIX_EBI0_CS1A_SMC		[expr {0 << 1}]
+set			AT91_MATRIX_EBI0_CS1A_SDRAMC		[expr {1 << 1}]
+set		AT91_MATRIX_EBI0_CS3A		[expr {1 << 3}]	;# Chip Select 3 Assignmen
+set			AT91_MATRIX_EBI0_CS3A_SMC		[expr {0 << 3}]
+set			AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA	[expr {1 << 3}]
+set		AT91_MATRIX_EBI0_CS4A		[expr {1 << 4}]	;# Chip Select 4 Assignment
+set			AT91_MATRIX_EBI0_CS4A_SMC		[expr {0 << 4}]
+set			AT91_MATRIX_EBI0_CS4A_SMC_CF1		[expr {1 << 4}]
+set		AT91_MATRIX_EBI0_CS5A		[expr {1 << 5}]	;# Chip Select 5 Assignment
+set			AT91_MATRIX_EBI0_CS5A_SMC		[expr {0 << 5}]
+set			AT91_MATRIX_EBI0_CS5A_SMC_CF2		[expr {1 << 5}]
+set		AT91_MATRIX_EBI0_DBPUC		[expr {1 << 8}]	;# Data Bus Pull-up Configuration
+set		AT91_MATRIX_EBI0_VDDIOMSEL	[expr {1 << 16}]	;# Memory voltage selection
+set			AT91_MATRIX_EBI0_VDDIOMSEL_1_8V		[expr {0 << 16}]
+set			AT91_MATRIX_EBI0_VDDIOMSEL_3_3V		[expr {1 << 16}]
+
+set AT91_MATRIX_EBI1CSA	[expr {$AT91_MATRIX + 0x124}]	;# EBI1 Chip Select Assignment Register
+set		AT91_MATRIX_EBI1_CS1A		[expr {1 << 1}]	;# Chip Select 1 Assignment
+set			AT91_MATRIX_EBI1_CS1A_SMC		[expr {0 << 1}]
+set			AT91_MATRIX_EBI1_CS1A_SDRAMC		[expr {1 << 1}]
+set		AT91_MATRIX_EBI1_CS2A		[expr {1 << 3}]	;# Chip Select 3 Assignment
+set			AT91_MATRIX_EBI1_CS2A_SMC		[expr {0 << 3}]
+set			AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA	[expr {1 << 3}]
+set		AT91_MATRIX_EBI1_DBPUC		[expr {1 << 8}]	;# Data Bus Pull-up Configuration
+set		AT91_MATRIX_EBI1_VDDIOMSEL	[expr {1 << 16}]	;# Memory voltage selection
+set			AT91_MATRIX_EBI1_VDDIOMSEL_1_8V		[expr {0 << 16}]
+set			AT91_MATRIX_EBI1_VDDIOMSEL_3_3V		[expr {1 << 16}]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9_init.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9_init.cfg
new file mode 100644
index 0000000..a64d6ea
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9_init.cfg
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]]
+
+proc at91sam9_reset_start { } {
+
+	arm7_9 fast_memory_access disable
+
+	jtag_rclk 8
+	halt
+	wait_halt 10000
+	set rstc_mr_val $::AT91_RSTC_KEY
+	set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
+	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
+	mww $::AT91_RSTC_MR $rstc_mr_val	;# RSTC_MR : enable user reset.
+}
+
+proc at91sam9_reset_init { config } {
+
+	mww $::AT91_WDT_MR $config(wdt_mr_val)	;# disable watchdog
+
+	set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
+
+	mww $::AT91_CKGR_MOR $ckgr_mor	;# CKGR_MOR - enable main osc.
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 }
+
+	set pllar_val	$::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog
+	set pllar_val	[expr {$pllar_val | $::AT91_PMC_OUT}]
+	set pllar_val	[expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
+	set pllar_val	[expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}]
+	set pllar_val	[expr {$pllar_val | $config(master_pll_div)}]
+
+	mww $::AT91_CKGR_PLLAR $pllar_val	 ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 }
+
+	;# PCK/2 = MCK Master Clock from PLLA
+	set mckr_val	$::AT91_PMC_CSS_PLLA
+	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PRES_1}]
+	set mckr_val	[expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
+	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PDIV_1}]
+
+	mww $::AT91_PMC_MCKR $mckr_val	;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 }
+
+	## switch JTAG clock to highspeed clock
+	jtag_rclk 0
+
+	arm7_9 dcc_downloads enable	;# Enable faster DCC downloads
+	arm7_9 fast_memory_access enable
+
+	set rstc_mr_val $::AT91_RSTC_KEY
+	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
+	mww $::AT91_RSTC_MR $rstc_mr_val	;# user reset enable
+
+	if { [info exists config(sdram_piod)] } {
+		set pdr_addr	[expr {$::AT91_PIOD + $::PIO_PDR}]
+		set pudr_addr	[expr {$::AT91_PIOD + $::PIO_PUDR}]
+		set asr_addr	[expr {$::AT91_PIOD + $::PIO_ASR}]
+		mww $pdr_addr 0xffff0000				;# define PDC[31:16] as DATA[31:16]
+		mww $pudr_addr 0xffff0000				;# no pull-up for D[31:16]
+		mww $asr_addr 0xffff0000
+	} else {
+		set pdr_addr	[expr {$::AT91_PIOC + $::PIO_PDR}]
+		set pudr_addr	[expr {$::AT91_PIOC + $::PIO_PUDR}]
+		mww $pdr_addr 0xffff0000				;# define PDC[31:16] as DATA[31:16]
+		mww $pudr_addr 0xffff0000				;# no pull-up for D[31:16]
+	}
+
+	mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_NORMAL	;# SDRAMC_MR Mode register
+	mww $::AT91_SDRAMC_TR	$config(sdram_tr_val)		;# SDRAMC_TR - Refresh Timer register
+	mww $::AT91_SDRAMC_CR	$config(sdram_cr_val)		;# SDRAMC_CR - Configuration register
+	mww $::AT91_SDRAMC_MDR	$::AT91_SDRAMC_MD_SDRAM		;# Memory Device Register -> SDRAM
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_PRECHARGE	;# SDRAMC_MR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_REFRESH	;# SDRC_MR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_LMR		;# SDRC_MR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_NORMAL	;# SDRC_MR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+	mww $::AT91_SDRAMC_TR	1200				;# SDRAM_TR
+	mww $config(sdram_base)	0				;# SDRAM_BASE
+
+	mww $::AT91_MATRIX 0xf		;# MATRIX_MCFG - REMAP all masters
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9_sdramc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9_sdramc.cfg
new file mode 100644
index 0000000..658b6c3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9_sdramc.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# SDRAM Controller (SDRAMC) registers
+set AT91_SDRAMC_MR		[expr {$AT91_SDRAMC + 0x00}]	;# SDRAM Controller Mode Register
+set		AT91_SDRAMC_MODE	[expr {0xf << 0}]	;# Command Mode
+set			AT91_SDRAMC_MODE_NORMAL		0
+set			AT91_SDRAMC_MODE_NOP		1
+set			AT91_SDRAMC_MODE_PRECHARGE	2
+set			AT91_SDRAMC_MODE_LMR		3
+set			AT91_SDRAMC_MODE_REFRESH	4
+set			AT91_SDRAMC_MODE_EXT_LMR	5
+set			AT91_SDRAMC_MODE_DEEP		6
+
+set AT91_SDRAMC_TR		[expr {$AT91_SDRAMC + 0x04}]	;# SDRAM Controller Refresh Timer Register
+set		AT91_SDRAMC_COUNT	[expr {0xfff << 0}]		;# Refresh Timer Counter
+
+set AT91_SDRAMC_CR		[expr {$AT91_SDRAMC + 0x08}]	;# SDRAM Controller Configuration Register
+set		AT91_SDRAMC_NC		[expr {3 << 0}]		;# Number of Column Bits
+set			AT91_SDRAMC_NC_8	[expr {0 << 0}]
+set			AT91_SDRAMC_NC_9	[expr {1 << 0}]
+set			AT91_SDRAMC_NC_10	[expr {2 << 0}]
+set			AT91_SDRAMC_NC_11	[expr {3 << 0}]
+set		AT91_SDRAMC_NR		[expr {3 << 2}]		;# Number of Row Bits
+set			AT91_SDRAMC_NR_11	[expr {0 << 2}]
+set			AT91_SDRAMC_NR_12	[expr {1 << 2}]
+set			AT91_SDRAMC_NR_13	[expr {2 << 2}]
+set		AT91_SDRAMC_NB		[expr {1 << 4}]		;# Number of Banks
+set			AT91_SDRAMC_NB_2	[expr {0 << 4}]
+set			AT91_SDRAMC_NB_4	[expr {1 << 4}]
+set		AT91_SDRAMC_CAS		[expr {3 << 5}]		;# CAS Latency
+set			AT91_SDRAMC_CAS_1	[expr {1 << 5}]
+set			AT91_SDRAMC_CAS_2	[expr {2 << 5}]
+set			AT91_SDRAMC_CAS_3	[expr {3 << 5}]
+set		AT91_SDRAMC_DBW		[expr {1 << 7}]		;# Data Bus Width
+set			AT91_SDRAMC_DBW_32	[expr {0 << 7}]
+set			AT91_SDRAMC_DBW_16	[expr {1 << 7}]
+set		AT91_SDRAMC_TWR		[expr {0xf <<  8}]		;# Write Recovery Delay
+set		AT91_SDRAMC_TRC		[expr {0xf << 12}]		;# Row Cycle Delay
+set		AT91_SDRAMC_TRP		[expr {0xf << 16}]		;# Row Precharge Delay
+set		AT91_SDRAMC_TRCD	[expr {0xf << 20}]		;# Row to Column Delay
+set		AT91_SDRAMC_TRAS	[expr {0xf << 24}]		;# Active to Precharge Delay
+set		AT91_SDRAMC_TXSR	[expr {0xf << 28}]		;# Exit Self Refresh to Active Delay
+
+set AT91_SDRAMC_LPR		[expr {$AT91_SDRAMC + 0x10}]	;# SDRAM Controller Low Power Register
+set		AT91_SDRAMC_LPCB		[expr {3 << 0}]	;# Low-power Configurations
+set			AT91_SDRAMC_LPCB_DISABLE		0
+set			AT91_SDRAMC_LPCB_SELF_REFRESH		1
+set			AT91_SDRAMC_LPCB_POWER_DOWN		2
+set			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
+set		AT91_SDRAMC_PASR		[expr {7 << 4}]	;# Partial Array Self Refresh
+set		AT91_SDRAMC_TCSR		[expr {3 << 8}]	;# Temperature Compensated Self Refresh
+set		AT91_SDRAMC_DS			[expr {3 << 10}]	;# Drive Strength
+set		AT91_SDRAMC_TIMEOUT		[expr {3 << 12}]	;# Time to define when Low Power Mode is enabled
+set			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	[expr {0 << 12}]
+set			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	[expr {1 << 12}]
+set			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	[expr {2 << 12}]
+
+set AT91_SDRAMC_IER		[expr {$AT91_SDRAMC + 0x14}]	;# SDRAM Controller Interrupt Enable Register
+set AT91_SDRAMC_IDR		[expr {$AT91_SDRAMC + 0x18}]	;# SDRAM Controller Interrupt Disable Register
+set AT91_SDRAMC_IMR		[expr {$AT91_SDRAMC + 0x1C}]	;# SDRAM Controller Interrupt Mask Register
+set AT91_SDRAMC_ISR		[expr {$AT91_SDRAMC + 0x20}]	;# SDRAM Controller Interrupt Status Register
+set		AT91_SDRAMC_RES		[expr {1 << 0}]		;# Refresh Error Status
+
+set AT91_SDRAMC_MDR		[expr {$AT91_SDRAMC + 0x24}]	;# SDRAM Memory Device Register
+set		AT91_SDRAMC_MD		[expr {3 << 0}]		;# Memory Device Type
+set			AT91_SDRAMC_MD_SDRAM		0
+set			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9_smc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9_smc.cfg
new file mode 100644
index 0000000..c096c4a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/at91sam9_smc.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set		AT91_SMC_READMODE	[expr {1 <<  0}]		;# Read Mode
+set		AT91_SMC_WRITEMODE	[expr {1 <<  1}]		;# Write Mode
+set		AT91_SMC_EXNWMODE	[expr {3 <<  4}]		;# NWAIT Mode
+set			AT91_SMC_EXNWMODE_DISABLE	[expr {0 << 4}]
+set			AT91_SMC_EXNWMODE_FROZEN	[expr {2 << 4}]
+set			AT91_SMC_EXNWMODE_READY		[expr {3 << 4}]
+set		AT91_SMC_BAT		[expr {1 <<  8}]		;# Byte Access Type
+set			AT91_SMC_BAT_SELECT		[expr {0 << 8}]
+set			AT91_SMC_BAT_WRITE		[expr {1 << 8}]
+set		AT91_SMC_DBW		[expr {3 << 12}]		;# Data Bus Width */
+set			AT91_SMC_DBW_8			[expr {0 << 12}]
+set			AT91_SMC_DBW_16			[expr {1 << 12}]
+set			AT91_SMC_DBW_32			[expr {2 << 12}]
+set		AT91_SMC_TDFMODE	[expr {1 << 20}]		;# TDF Optimization - Enabled
+set		AT91_SMC_PMEN		[expr {1 << 24}]		;# Page Mode Enabled
+set		AT91_SMC_PS		[expr {3 << 28}]		;# Page Size
+set			AT91_SMC_PS_4			[expr {0 << 28}]
+set			AT91_SMC_PS_8			[expr {1 << 28}]
+set			AT91_SMC_PS_16			[expr {2 << 28}]
+set			AT91_SMC_PS_32			[expr {3 << 28}]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/hardware.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/hardware.cfg
new file mode 100644
index 0000000..069d4b7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/hardware.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# External Memory Map
+set AT91_CHIPSELECT_0	0x10000000
+set AT91_CHIPSELECT_1	0x20000000
+set AT91_CHIPSELECT_2	0x30000000
+set AT91_CHIPSELECT_3	0x40000000
+set AT91_CHIPSELECT_4	0x50000000
+set AT91_CHIPSELECT_5	0x60000000
+set AT91_CHIPSELECT_6	0x70000000
+set AT91_CHIPSELECT_7	0x80000000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/pmc.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/pmc.tcl
new file mode 100644
index 0000000..0f997ca
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/pmc.tcl
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if [info exists AT91C_MAINOSC_FREQ] {
+    # user set this... let it be.
+} {
+    # 18.432mhz is a common thing...
+    set AT91C_MAINOSC_FREQ 18432000
+}
+global AT91C_MAINOSC_FREQ
+
+if [info exists AT91C_SLOWOSC_FREQ] {
+    # user set this... let it be.
+} {
+    # 32khz is the norm
+    set AT91C_SLOWOSC_FREQ 32768
+}
+global AT91C_SLOWOSC_FREQ
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/rtt.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/rtt.tcl
new file mode 100644
index 0000000..1ef8373
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/rtt.tcl
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}]
+set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}]
+set RTTC_RTVR [expr {$AT91C_BASE_RTTC + 0x08}]
+set RTTC_RTSR [expr {$AT91C_BASE_RTTC + 0x0c}]
+global RTTC_RTMR
+global RTTC_RTAR
+global RTTC_RTVR
+global RTTC_RTSR
+
+proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
+    set rtpres [expr {$VAL & 0x0ffff}]
+    global BIT16 BIT17
+    if { $rtpres == 0 } {
+	set rtpres 65536;
+    }
+    global AT91C_SLOWOSC_FREQ
+    # Nasty hack, make this a float by tacking a .0 on the end
+    # otherwise, jim makes the value an integer
+    set f [expr "$AT91C_SLOWOSC_FREQ.0 / $rtpres.0"]
+    echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
+    if { $VAL & $BIT16 } {
+	echo "\tBit16 -> Alarm IRQ Enabled"
+    } else {
+	echo "\tBit16 -> Alarm IRQ Disabled"
+    }
+    if { $VAL & $BIT17 } {
+	echo "\tBit17 -> RTC Inc IRQ Enabled"
+    } else {
+	echo "\tBit17 -> RTC Inc IRQ Disabled"
+    }
+    # Bit 18 is write only.
+}
+
+proc show_RTTC_RTSR_helper { NAME ADDR VAL } {
+    global BIT0 BIT1
+    if { $VAL & $BIT0 } {
+	echo "\tBit0 -> ALARM PENDING"
+    } else {
+	echo "\tBit0 -> alarm not pending"
+    }
+    if { $VAL & $BIT1 } {
+	echo "\tBit0 -> RTINC PENDING"
+    } else {
+	echo "\tBit0 -> rtinc not pending"
+    }
+}
+
+proc show_RTTC { } {
+
+    show_mmr32_reg RTTC_RTMR
+    show_mmr32_reg RTTC_RTAR
+    show_mmr32_reg RTTC_RTVR
+    show_mmr32_reg RTTC_RTSR
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/sam9_smc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/sam9_smc.cfg
new file mode 100644
index 0000000..87880c7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/sam9_smc.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Setup register
+#
+# ncs_read_setup
+# nrd_setup
+# ncs_write_setup
+# set nwe_setup
+#
+#
+# Pulse register
+#
+# ncs_read_pulse
+# nrd_pulse
+# ncs_write_pulse
+# nwe_pulse
+#
+#
+# Cycle register
+#
+# read_cycle 0
+# write_cycle 0
+#
+#
+# Mode register
+#
+# mode
+# tdf_cycles
+proc sam9_smc_config { cs smc_config } {
+	;# Setup Register for CS n
+	set AT91_SMC_SETUP [expr {$::AT91_SMC + 0x00 + $cs * 0x10}]
+	set val [expr {$smc_config(nwe_setup) << 0}]
+	set val [expr {$val | $smc_config(ncs_write_setup) << 8}]
+	set val [expr {$val | $smc_config(nrd_setup)) << 16}]
+	set val [expr {$val | $smc_config(ncs_read_setup) << 24}]
+	mww $AT91_SMC_SETUP $val
+
+	;# Pulse Register for CS n
+	set AT91_SMC_PULSE [expr {$::AT91_SMC + 0x04 + $cs * 0x10}]
+	set val [expr {$smc_config(nwe_pulse) << 0}]
+	set val [expr {$val | $smc_config(ncs_write_pulse) << 8}]
+	set val [expr {$val | $smc_config(nrd_pulse) << 16}]
+	set val [expr {$val | $smc_config(ncs_read_pulse) << 24}]
+	mww $AT91_SMC_PULSE $val
+
+	;# Cycle Register for CS n
+	set AT91_SMC_CYCLE [expr {$::AT91_SMC + 0x08 + $cs * 0x10}]
+	set val [expr {$smc_config(write_cycle) << 0}]
+	set val [expr {$val | $smc_config(read_cycle) << 16}]
+	mww $AT91_SMC_CYCLE $val
+
+	;# Mode Register for CS n
+	set AT91_SMC_MODE [expr {$::AT91_SMC + 0x0c + $cs * 0x10}]
+	set val [expr {$smc_config(mode) << 0}]
+	set val [expr {$val | $smc_config(tdf_cycles) << 16}]
+	mww $AT91_SMC_MODE $val
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/usarts.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/usarts.tcl
new file mode 100644
index 0000000..62a651b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/atmel/at91/usarts.tcl
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# the DBGU and USARTs are 'almost' indentical'
+set DBGU_CR         [expr {$AT91C_BASE_DBGU + 0x00000000}]
+set DBGU_MR         [expr {$AT91C_BASE_DBGU + 0x00000004}]
+set DBGU_IER        [expr {$AT91C_BASE_DBGU + 0x00000008}]
+set DBGU_IDR        [expr {$AT91C_BASE_DBGU + 0x0000000C}]
+set DBGU_IMR        [expr {$AT91C_BASE_DBGU + 0x00000010}]
+set DBGU_CSR        [expr {$AT91C_BASE_DBGU + 0x00000014}]
+set DBGU_RHR        [expr {$AT91C_BASE_DBGU + 0x00000018}]
+set DBGU_THR        [expr {$AT91C_BASE_DBGU + 0x0000001C}]
+set DBGU_BRGR       [expr {$AT91C_BASE_DBGU + 0x00000020}]
+# no RTOR
+# no TTGR
+# no FIDI
+# no NER
+set DBGU_CIDR       [expr {$AT91C_BASE_DBGU + 0x00000040}]
+set DBGU_EXID       [expr {$AT91C_BASE_DBGU + 0x00000044}]
+set DBGU_FNTR       [expr {$AT91C_BASE_DBGU + 0x00000048}]
+
+
+set USx_CR           0x00000000
+set USx_MR           0x00000004
+set USx_IER          0x00000008
+set USx_IDR          0x0000000C
+set USx_IMR          0x00000010
+set USx_CSR          0x00000014
+set USx_RHR          0x00000018
+set USx_THR          0x0000001C
+set USx_BRGR         0x00000020
+set USx_RTOR         0x00000024
+set USx_TTGR         0x00000028
+set USx_FIDI         0x00000040
+set USx_NER          0x00000044
+set USx_IF           0x0000004C
+
+# Create all the uarts that exist..
+# we blow up if there are >9
+
+
+proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
+    # First - just print it
+
+    set x [show_normalize_bitfield $VAL 3 0]
+    if { $x == 0 } {
+	echo "\tNormal operation"
+    } else {
+	echo [format "\tNon Normal operation mode: 0x%02x" $x]
+    }
+
+    set x [show_normalize_bitfield $VAL 11 9]
+    set s "unknown"
+    switch -exact $x {
+	0 { set s "Even" }
+	1 { set s "Odd" }
+	2 { set s "Force=0" }
+	3 { set s "Force=1" }
+	* {
+	    set $x [expr {$x & 6}]
+	    switch -exact $x {
+		4 { set s "None" }
+		6 { set s "Multidrop Mode" }
+	    }
+	}
+    }
+    echo [format "\tParity: %s " $s]
+
+    set x [expr {5 + [show_normalize_bitfield $VAL 7 6]}]
+    echo [format "\tDatabits: %d" $x]
+
+    set x [show_normalize_bitfield $VAL 13 12]
+    switch -exact $x {
+	0 { echo "\tStop bits: 1" }
+	1 { echo "\tStop bits: 1.5" }
+	2 { echo "\tStop bits: 2" }
+	3 { echo "\tStop bits: Illegal/Reserved" }
+    }
+}
+
+# For every possbile usart...
+foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } {
+    set n AT91C_BASE_[set WHO]
+    set str ""
+
+    # Only if it exists on the chip
+    if [ info exists $n ] {
+	# Hence: $n - is like AT91C_BASE_USx
+	# For every sub-register
+	foreach REG {CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER IF}	{
+	    # vn = variable name
+	    set vn [set WHO]_[set REG]
+	    # vn = USx_IER
+	    # vv = variable value
+	    set vv [expr "$$n + [set USx_[set REG]]"]
+	    # And VV is the address in memory of that register
+
+
+	    # make that VN a GLOBAL so others can find it
+	    global $vn
+	    set $vn $vv
+
+	    # Create a command for this specific register.
+	    proc show_$vn { } "show_mmr32_reg $vn"
+
+	    # Add this command to the Device(as a whole) command
+	    set str "$str\nshow_$vn"
+	}
+	# Now - create the DEVICE(as a whole) command
+	set fn show_$WHO
+	proc $fn { } $str
+    }
+}
+
+# The Debug Uart is special..
+set str ""
+
+
+# For every sub-register
+foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR
+    DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} {
+
+    # Create a command for this specific register.
+    proc show_$REG { } "show_mmr32_reg $REG"
+
+    # Add this command to the Device(as a whole) command
+    set str "$str\nshow_$REG"
+}
+
+# Now - create the DEVICE(as a whole) command
+proc show_DBGU { } $str
+
+unset str
+
+proc show_DBGU_MR_helper { NAME ADDR VAL } { show_mmr_USx_MR_helper $NAME $ADDR $VAL }
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/spear/quirk_no_srst.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/spear/quirk_no_srst.tcl
new file mode 100644
index 0000000..e8640f4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/spear/quirk_no_srst.tcl
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Quirks to bypass missing SRST on JTAG connector
+# EVALSPEAr310 Rev. 2.0
+# http://www.st.com/spear
+#
+# Date:      2010-08-17
+# Author:    Antonio Borneo 
+
+# For boards that have JTAG SRST not connected.
+# We use "arm9 vector_catch reset" to catch button reset event.
+
+
+$_TARGETNAME configure -event reset-assert sp_reset_assert
+$_TARGETNAME configure -event reset-deassert-post sp_reset_deassert_post
+
+# keeps the name of the SPEAr target
+global sp_target_name
+set sp_target_name $_TARGETNAME
+
+# Keeps the argument of "reset" command (run, init, halt).
+global sp_reset_mode
+set sp_reset_mode ""
+
+# Helper procedure. Returns 0 is target is halted.
+proc sp_is_halted {} {
+	global sp_target_name
+
+	return [expr {[string compare [$sp_target_name curstate] "halted" ] == 0}]
+}
+
+# wait for reset button to be pressed, causing CPU to get halted
+proc sp_reset_deassert_post {} {
+	global sp_reset_mode
+
+	set bar(0) |
+	set bar(1) /
+	set bar(2) -
+	set bar(3) \\
+
+	poll on
+	echo "====> Press reset button on the board <===="
+	for {set i 0} { [sp_is_halted] == 0 } { set i [expr {$i + 1}]} {
+		echo -n "$bar([expr {$i & 3}])\r"
+		sleep 200
+	}
+
+	# Remove catch reset event
+	arm9 vector_catch none
+
+	# CPU is halted, but we typed "reset run" ...
+	if { [string compare $sp_reset_mode "run"] == 0 } {
+		resume
+	}
+}
+
+# Override reset-assert, since no SRST available
+# Catch reset event
+proc sp_reset_assert {} {
+	arm9 vector_catch reset
+}
+
+# Override default init_reset{mode} to catch parameter "mode"
+proc init_reset {mode} {
+	global sp_reset_mode
+
+	set sp_reset_mode $mode
+
+	# We need to detect CPU get halted, so exit from halt
+	if { [sp_is_halted] } {
+		echo "Resuming CPU to detect reset"
+		resume
+	}
+
+	# Execute default init_reset{mode}
+	jtag arp_init-reset
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/spear/spear3xx.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/spear/spear3xx.tcl
new file mode 100644
index 0000000..474ebe3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/spear/spear3xx.tcl
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Generic init scripts for all ST SPEAr3xx family
+# http://www.st.com/spear
+#
+# Date:      2010-09-23
+# Author:    Antonio Borneo 
+
+
+# Initialize internal clock
+# Default:
+# - Crystal =  24 MHz
+# - PLL1    = 332 MHz
+# - PLL2    = 332 MHz
+# - CPU_CLK = 332 MHz
+# - DDR_CLK = 332 MHz async
+# - HCLK    = 166 MHz
+# - PCLK    =  83 MHz
+proc sp3xx_clock_default {} {
+	mww 0xfca00000 0x00000002	;# set sysclk slow
+	mww 0xfca00014 0x0ffffff8	;# set pll timeout to minimum (100us ?!?)
+
+	# DDRCORE disable to change frequency
+	set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}]
+	mww 0xfca8002c $val
+	mww 0xfca8002c $val ;# Yes, write twice!
+
+	# programming PLL1
+	mww 0xfca8000c 0xa600010c	;# M=166 P=1 N=12
+	mww 0xfca80008 0x00001c0a	;# power down
+	mww 0xfca80008 0x00001c0e	;# enable
+	mww 0xfca80008 0x00001c06	;# strobe
+	mww 0xfca80008 0x00001c0e
+	while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 }
+
+	# programming PLL2
+	mww 0xfca80018 0xa600010c	;# M=166, P=1, N=12
+	mww 0xfca80014 0x00001c0a	;# power down
+	mww 0xfca80014 0x00001c0e	;# enable
+	mww 0xfca80014 0x00001c06	;# strobe
+	mww 0xfca80014 0x00001c0e
+	while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 }
+
+	mww 0xfca80028 0x00000082	;# enable plltimeen
+	mww 0xfca80024 0x00000511	;# set hclkdiv="/2" & pclkdiv="/2"
+
+	mww 0xfca00000 0x00000004	;# setting SYSCTL to NORMAL mode
+	while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 }
+
+	# Select source of DDR clock
+	#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
+	mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2
+
+	# DDRCORE enable after change frequency
+	mmw 0xfca8002c 0x20000000 0x00000000
+}
+
+proc sp3xx_common_init {} {
+	mww 0xfca8002c 0xfffffff8	;# enable clock of all peripherals
+	mww 0xfca80038 0x00000000	;# remove reset of all peripherals
+
+	mww 0xfca80034 0x0000ffff	;# enable all RAS clocks
+	mww 0xfca80040 0x00000000	;# remove all RAS resets
+
+	mww 0xfca800e4 0x78000008	;# COMP1V8_REG
+	mww 0xfca800ec 0x78000008	;# COMP3V3_REG
+
+	mww 0xfc000000 0x10000f5f	;# init SMI and set HW mode
+	mww 0xfc000000 0x00000f5f
+
+	# Initialize Bus Interconnection Matrix
+	# All ports Round-Robin and lowest priority
+	mww 0xfca8007c 0x80000007
+	mww 0xfca80080 0x80000007
+	mww 0xfca80084 0x80000007
+	mww 0xfca80088 0x80000007
+	mww 0xfca8008c 0x80000007
+	mww 0xfca80090 0x80000007
+	mww 0xfca80094 0x80000007
+	mww 0xfca80098 0x80000007
+	mww 0xfca8009c 0x80000007
+}
+
+
+# Specific init scripts for ST SPEAr300
+proc sp300_init {} {
+	mww 0x99000000 0x00003fff	;# RAS function enable
+}
+
+
+# Specific init scripts for ST SPEAr310
+proc sp310_init {} {
+	mww 0xb4000008 0x00002ff4	;# RAS function enable
+
+	mww 0xfca80050 0x00000001	;# Enable clk mem port 1
+
+	mww 0xfca8013c 0x2f7bc210	;# plgpio_pad_drv
+	mww 0xfca80140 0x017bdef6
+}
+
+proc sp310_emi_init {} {
+	# set EMI pad strength
+	mmw 0xfca80134 0x0e000000 0x00000000
+	mmw 0xfca80138 0x0e739ce7 0x00000000
+	mmw 0xfca8013c 0x00039ce7 0x00000000
+
+	# set safe EMI timing as in BootROM
+	#mww 0x4f000000 0x0000000f	;# tAP_0_reg
+	#mww 0x4f000004 0x00000000	;# tSDP_0_reg
+	#mww 0x4f000008 0x000000ff	;# tDPw_0_reg
+	#mww 0x4f00000c 0x00000111	;# tDPr_0_reg
+	#mww 0x4f000010 0x00000002	;# tDCS_0_reg
+
+	# set fast EMI timing as in Linux
+	mww 0x4f000000 0x00000010	;# tAP_0_reg
+	mww 0x4f000004 0x00000005	;# tSDP_0_reg
+	mww 0x4f000008 0x0000000a	;# tDPw_0_reg
+	mww 0x4f00000c 0x0000000a	;# tDPr_0_reg
+	mww 0x4f000010 0x00000005	;# tDCS_0_re
+
+	# 32bit wide, 8/16/32bit access
+	mww 0x4f000014 0x0000000e	;# control_0_reg
+	mww 0x4f000094 0x0000003f	;# ack_reg
+}
+
+
+# Specific init scripts for ST SPEAr320
+proc sp320_init {} {
+	mww 0xb300000c 0xffffac04	;# RAS function enable
+	mww 0xb3000010 0x00000001	;# RAS mode select
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/spear/spear3xx_ddr.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/spear/spear3xx_ddr.tcl
new file mode 100644
index 0000000..0696221
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/spear/spear3xx_ddr.tcl
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Init scripts to configure DDR controller of SPEAr3xx
+# http://www.st.com/spear
+# Original values taken from XLoader source code
+#
+# Date:      2010-09-23
+# Author:    Antonio Borneo 
+
+
+proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
+	if { $ddr_chips != 1 && $ddr_chips != 2 } {
+		error "Only 1 or 2 DDR chips permitted. Wrong value $ddr_chips"
+	}
+
+	if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
+		ddr_spr3xx_mt47h64m16_3_333_cl5_async $ddr_chips
+		set ddr_size 0x08000000
+	## add here new DDR chip definition. Prototype:
+	#} elseif { $ddr_type == "?????" } {
+	#	????? $ddr_chips
+	#	set ddr_size 0x?????
+	} else {
+		error "sp3xx_ddr_init: unrecognized DDR type $ddr_type"
+	}
+
+	# MPMC START
+	mww 0xfc60001c 0x01000100
+
+	if { $ddr_chips == 2 } {
+		echo [format \
+			"Double chip DDR memory. Total memory size 0x%08x byte" \
+			[expr {2 * $ddr_size}]]
+	} else {
+		echo [format \
+			"Single chip DDR memory. Memory size 0x%08x byte" \
+			$ddr_size]
+	}
+}
+
+
+# from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S
+proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {ddr_chips} {
+	# DDR_PAD_REG
+	mww 0xfca800f0 0x00003aa5
+
+	# Use "1:2 sync" only when DDR clock source is PLL1 and
+	# HCLK is half of PLL1
+	mww 0xfc600000 0x00000001	;# MEMCTL_AHB_SET_00 # This is async
+	mww 0xfc600004 0x00000000	;# MEMCTL_AHB_SET_01
+#	mww 0xfc600000 0x02020201	;# MEMCTL_AHB_SET_00 # This is 1:2 sync
+#	mww 0xfc600004 0x02020202	;# MEMCTL_AHB_SET_01
+
+	mww 0xfc600008 0x01000000	;# MEMCTL_RFSH_SET_00
+	mww 0xfc60000c 0x00000101	;# MEMCTL_DLL_SET_00
+	mww 0xfc600010 0x00000101	;# MEMCTL_GP_00
+	mww 0xfc600014 0x01000000	;# MEMCTL_GP_01
+	mww 0xfc600018 0x00010001	;# MEMCTL_GP_02
+	mww 0xfc60001c 0x00000100	;# MEMCTL_GP_03
+	mww 0xfc600020 0x00010001	;# MEMCTL_GP_04
+	if { $ddr_chips == 2 } {
+		mww 0xfc600024 0x01020203	;# MEMCTL_GP_05
+		mww 0xfc600028 0x01000102	;# MEMCTL_GP_06
+		mww 0xfc60002c 0x02000202	;# MEMCTL_AHB_SET_02
+	} else {
+		mww 0xfc600024 0x00000201	;# MEMCTL_GP_05
+		mww 0xfc600028 0x02000001	;# MEMCTL_GP_06
+		mww 0xfc60002c 0x02000201	;# MEMCTL_AHB_SET_02
+	}
+	mww 0xfc600030 0x04040105	;# MEMCTL_AHB_SET_03
+	mww 0xfc600034 0x03030302	;# MEMCTL_AHB_SET_04
+	mww 0xfc600038 0x02040101	;# MEMCTL_AHB_SET_05
+	mww 0xfc60003c 0x00000002	;# MEMCTL_AHB_SET_06
+	mww 0xfc600044 0x03000405	;# MEMCTL_DQS_SET_0
+	mww 0xfc600048 0x03040002	;# MEMCTL_TIME_SET_01
+	mww 0xfc60004c 0x04000305	;# MEMCTL_TIME_SET_02
+	mww 0xfc600050 0x0505053f	;# MEMCTL_AHB_RELPR_00
+	mww 0xfc600054 0x05050505	;# MEMCTL_AHB_RELPR_01
+	mww 0xfc600058 0x04040405	;# MEMCTL_AHB_RELPR_02
+	mww 0xfc60005c 0x04040404	;# MEMCTL_AHB_RELPR_03
+	mww 0xfc600060 0x03030304	;# MEMCTL_AHB_RELPR_04
+	mww 0xfc600064 0x03030303	;# MEMCTL_AHB_RELPR_05
+	mww 0xfc600068 0x02020203	;# MEMCTL_AHB_RELPR_06
+	mww 0xfc60006c 0x02020202	;# MEMCTL_AHB_RELPR_07
+	mww 0xfc600070 0x01010102	;# MEMCTL_AHB_RELPR_08
+	mww 0xfc600074 0x01010101	;# MEMCTL_AHB_RELPR_09
+	mww 0xfc600078 0x00000001	;# MEMCTL_AHB_RELPR_10
+	mww 0xfc600088 0x0a0c0a00	;# MEMCTL_DQS_SET_1
+	mww 0xfc60008c 0x0000023f	;# MEMCTL_GP_07
+	mww 0xfc600090 0x00050a00	;# MEMCTL_GP_08
+	mww 0xfc600094 0x11000000	;# MEMCTL_GP_09
+	mww 0xfc600098 0x00001302	;# MEMCTL_GP_10
+	mww 0xfc60009c 0x00001c1c	;# MEMCTL_DLL_SET_01
+	mww 0xfc6000a0 0x7c000000	;# MEMCTL_DQS_OUT_SHIFT
+	mww 0xfc6000a4 0x005c0000	;# MEMCTL_WR_DQS_SHIFT
+	mww 0xfc6000a8 0x2b050e00	;# MEMCTL_TIME_SET_03
+	mww 0xfc6000ac 0x00640064	;# MEMCTL_AHB_PRRLX_00
+	mww 0xfc6000b0 0x00640064	;# MEMCTL_AHB_PRRLX_01
+	mww 0xfc6000b4 0x00000064	;# MEMCTL_AHB_PRRLX_02
+	mww 0xfc6000b8 0x00000000	;# MEMCTL_OUTRANGE_LGTH
+	mww 0xfc6000bc 0x00200020	;# MEMCTL_AHB_RW_SET_00
+	mww 0xfc6000c0 0x00200020	;# MEMCTL_AHB_RW_SET_01
+	mww 0xfc6000c4 0x00200020	;# MEMCTL_AHB_RW_SET_02
+	mww 0xfc6000c8 0x00200020	;# MEMCTL_AHB_RW_SET_03
+	mww 0xfc6000cc 0x00200020	;# MEMCTL_AHB_RW_SET_04
+	mww 0xfc6000d8 0x00000a24	;# MEMCTL_TREF
+	mww 0xfc6000dc 0x00000000	;# MEMCTL_EMRS3_DATA
+	mww 0xfc6000e0 0x5b1c00c8	;# MEMCTL_TIME_SET_04
+	mww 0xfc6000e4 0x00c8002e	;# MEMCTL_TIME_SET_05
+	mww 0xfc6000e8 0x00000000	;# MEMCTL_VERSION
+	mww 0xfc6000ec 0x0001046b	;# MEMCTL_TINIT
+	mww 0xfc6000f0 0x00000000	;# MEMCTL_OUTRANGE_ADDR_01
+	mww 0xfc6000f4 0x00000000	;# MEMCTL_OUTRANGE_ADDR_02
+	mww 0xfc600104 0x001c0000	;# MEMCTL_DLL_DQS_DELAY_BYPASS_0
+	mww 0xfc600108 0x0019001c	;# MEMCTL_DLL_SET_02
+	mww 0xfc60010c 0x00100000	;# MEMCTL_DLL_SET_03
+	mww 0xfc600110 0x001e007a	;# MEMCTL_DQS_SET_2
+	mww 0xfc600188 0x00000000	;# MEMCTL_USER_DEF_REG_0
+	mww 0xfc60018c 0x00000000	;# MEMCTL_USER_DEF_REG_1
+	mww 0xfc600190 0x01010001	;# MEMCTL_GP_11
+	mww 0xfc600194 0x01000000	;# MEMCTL_GP_12
+	mww 0xfc600198 0x00000001	;# MEMCTL_GP_13
+	mww 0xfc60019c 0x00400000	;# MEMCTL_GP_14
+	mww 0xfc6001a0 0x00000000	;# MEMCTL_EMRS2_DATA_X
+	mww 0xfc6001a4 0x00000000	;# MEMCTL_LWPWR_CNT
+	mww 0xfc6001a8 0x00000000	;# MEMCTL_LWPWR_REG
+	mww 0xfc6001ac 0x00860000	;# MEMCTL_GP_15
+	mww 0xfc6001b0 0x00000002	;# MEMCTL_TPDEX
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/stm32/stm32.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/stm32/stm32.tcl
new file mode 100644
index 0000000..3826a57
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/stm32/stm32.tcl
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find bitsbytes.tcl]
+source [find cpu/arm/cortex_m3.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+source [find chip/st/stm32/stm32_regs.tcl]
+source [find chip/st/stm32/stm32_rcc.tcl]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/stm32/stm32_rcc.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/stm32/stm32_rcc.tcl
new file mode 100644
index 0000000..afa4cbf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/stm32/stm32_rcc.tcl
@@ -0,0 +1,291 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set RCC_CR            [expr {$RCC_BASE + 0x00}]
+set RCC_CFGR          [expr {$RCC_BASE + 0x04}]
+set RCC_CIR           [expr {$RCC_BASE + 0x08}]
+set RCC_APB2RSTR      [expr {$RCC_BASE + 0x0c}]
+set RCC_APB1RSTR      [expr {$RCC_BASE + 0x10}]
+set RCC_AHBENR        [expr {$RCC_BASE + 0x14}]
+set RCC_APB2ENR       [expr {$RCC_BASE + 0x18}]
+set RCC_APB1ENR       [expr {$RCC_BASE + 0x1c}]
+set RCC_BDCR          [expr {$RCC_BASE + 0x20}]
+set RCC_CSR           [expr {$RCC_BASE + 0x24}]
+
+
+proc show_RCC_CR { } {
+    if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {
+	error $msg
+    }
+
+    show_mmr_bitfield  0  0 $val HSI      { OFF ON }
+    show_mmr_bitfield  1  1 $val HSIRDY   { NOTRDY RDY  }
+    show_mmr_bitfield  7  3 $val HSITRIM  { _NUMBER_ }
+    show_mmr_bitfield 15  8 $val HSICAL   { _NUMBER_ }
+    show_mmr_bitfield 16 16 $val HSEON    { OFF ON }
+    show_mmr_bitfield 17 17 $val HSERDY   { NOTRDY RDY  }
+    show_mmr_bitfield 18 18 $val HSEBYP   { NOTBYPASSED BYPASSED }
+    show_mmr_bitfield 19 19 $val CSSON    { OFF ON }
+    show_mmr_bitfield 24 24 $val PLLON    { OFF ON }
+    show_mmr_bitfield 25 25 $val PLLRDY   { NOTRDY RDY }
+}
+
+proc show_RCC_CFGR { } {
+    if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
+	error $msg
+    }
+
+
+    show_mmr_bitfield  1  0 $val  SW     { HSI HSE PLL ILLEGAL }
+    show_mmr_bitfield  3  2 $val  SWS    { HSI HSE PLL ILLEGAL }
+    show_mmr_bitfield  7  4 $val  HPRE   { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }
+    show_mmr_bitfield 10  8 $val  PPRE1  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
+    show_mmr_bitfield 13 11 $val  PPRE2  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
+    show_mmr_bitfield 15 14 $val  ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }
+    show_mmr_bitfield 16 16 $val  PLLSRC { HSI_div_2 HSE }
+    show_mmr_bitfield 17 17 $val  PLLXTPRE { hse_div1 hse_div2 }
+    show_mmr_bitfield 21 18 $val  PLLMUL { x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }
+    show_mmr_bitfield 22 22 $val  USBPRE { div1 div1_5 }
+    show_mmr_bitfield 26 24 $val  MCO    { none none none none SysClk HSI HSE PLL_div2 }
+}
+
+
+proc show_RCC_CIR { } {
+    if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
+	error $msg
+    }
+
+}
+
+proc show_RCC_APB2RSTR { } {
+    if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {
+	error $msg
+    }
+    for { set x 0 } { $x < 32 } { incr x } {
+	set bits($x) xxx
+    }
+    set bits(15) adc3
+    set bits(14) usart1
+    set bits(13) tim8
+    set bits(12) spi1
+    set bits(11) tim1
+    set bits(10) adc2
+    set bits(9) adc1
+    set bits(8) iopg
+    set bits(7) iopf
+    set bits(6) iope
+    set bits(5) iopd
+    set bits(4) iopc
+    set bits(3) iopb
+    set bits(2) iopa
+    set bits(1) xxx
+    set bits(0) afio
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC_APB1RSTR { } {
+    if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {
+	error $msg
+    }
+    set bits(31) xxx
+    set bits(30) xxx
+    set bits(29) dac
+    set bits(28) pwr
+    set bits(27) bkp
+    set bits(26) xxx
+    set bits(25) can
+    set bits(24) xxx
+    set bits(23) usb
+    set bits(22) i2c2
+    set bits(21) i2c1
+    set bits(20) uart5
+    set bits(19) uart4
+    set bits(18) uart3
+    set bits(17) uart2
+    set bits(16) xxx
+    set bits(15) spi3
+    set bits(14) spi2
+    set bits(13) xxx
+    set bits(12) xxx
+    set bits(11) wwdg
+    set bits(10) xxx
+    set bits(9) xxx
+    set bits(8) xxx
+    set bits(7) xxx
+    set bits(6) xxx
+    set bits(5) tim7
+    set bits(4) tim6
+    set bits(3) tim5
+    set bits(2) tim4
+    set bits(1) tim3
+    set bits(0) tim2
+    show_mmr32_bits bits $val
+
+}
+
+proc show_RCC_AHBENR   { } {
+    if [ catch { set val [ show_mmr32_reg RCC_AHBENR  ] } msg ] {
+	error $msg
+    }
+    set bits(31) xxx
+    set bits(30) xxx
+    set bits(29) xxx
+    set bits(28) xxx
+    set bits(27) xxx
+    set bits(26) xxx
+    set bits(25) xxx
+    set bits(24) xxx
+    set bits(23) xxx
+    set bits(22) xxx
+    set bits(21) xxx
+    set bits(20) xxx
+    set bits(19) xxx
+    set bits(18) xxx
+    set bits(17) xxx
+    set bits(16) xxx
+    set bits(15) xxx
+    set bits(14) xxx
+    set bits(13) xxx
+    set bits(12) xxx
+    set bits(11) xxx
+    set bits(10) sdio
+    set bits(9) xxx
+    set bits(8) fsmc
+    set bits(7) xxx
+    set bits(6) crce
+    set bits(5) xxx
+    set bits(4) flitf
+    set bits(3) xxx
+    set bits(2) sram
+    set bits(1) dma2
+    set bits(0) dma1
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC_APB2ENR  { } {
+    if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {
+	error $msg
+    }
+    set bits(31) xxx
+    set bits(30) xxx
+    set bits(29) xxx
+    set bits(28) xxx
+    set bits(27) xxx
+    set bits(26) xxx
+    set bits(25) xxx
+    set bits(24) xxx
+    set bits(23) xxx
+    set bits(22) xxx
+    set bits(21) xxx
+    set bits(20) xxx
+    set bits(19) xxx
+    set bits(18) xxx
+    set bits(17) xxx
+    set bits(16) xxx
+    set bits(15) adc3
+    set bits(14) usart1
+    set bits(13) tim8
+    set bits(12) spi1
+    set bits(11) tim1
+    set bits(10) adc2
+    set bits(9) adc1
+    set bits(8) iopg
+    set bits(7) iopf
+    set bits(6) iope
+    set bits(5) iopd
+    set bits(4) iopc
+    set bits(3) iopb
+    set bits(2) iopa
+    set bits(1) xxx
+    set bits(0) afio
+    show_mmr32_bits bits $val
+
+}
+
+proc show_RCC_APB1ENR  { } {
+    if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {
+	error $msg
+    }
+    set bits(31) xxx
+    set bits(30) xxx
+    set bits(29) dac
+    set bits(28) pwr
+    set bits(27) bkp
+    set bits(26) xxx
+    set bits(25) can
+    set bits(24) xxx
+    set bits(23) usb
+    set bits(22) i2c2
+    set bits(21) i2c1
+    set bits(20) usart5
+    set bits(19) usart4
+    set bits(18) usart3
+    set bits(17) usart2
+    set bits(16) xxx
+    set bits(15) spi3
+    set bits(14) spi2
+    set bits(13) xxx
+    set bits(12) xxx
+    set bits(11) wwdg
+    set bits(10) xxx
+    set bits(9) xxx
+    set bits(8) xxx
+    set bits(7) xxx
+    set bits(6) xxx
+    set bits(5) tim7
+    set bits(4) tim6
+    set bits(3) tim5
+    set bits(2) tim4
+    set bits(1) tim3
+    set bits(0) tim2
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC_BDCR     { } {
+    if [ catch { set val [ show_mmr32_reg RCC_BDCR    ] } msg ] {
+	error $msg
+    }
+    for { set x 0 } { $x < 32 } { incr x } {
+	set bits($x) xxx
+    }
+    set bits(0) lseon
+    set bits(1) lserdy
+    set bits(2) lsebyp
+    set bits(8) rtcsel0
+    set bits(9) rtcsel1
+    set bits(15) rtcen
+    set bits(16) bdrst
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC_CSR      { } {
+    if [ catch { set val [ show_mmr32_reg RCC_CSR     ] } msg ] {
+	error $msg
+    }
+    for { set x 0 } { $x < 32 } { incr x } {
+	set bits($x) xxx
+    }
+    set bits(0) lsion
+    set bits(1) lsirdy
+    set bits(24) rmvf
+    set bits(26) pin
+    set bits(27) por
+    set bits(28) sft
+    set bits(29) iwdg
+    set bits(30) wwdg
+    set bits(31) lpwr
+    show_mmr32_bits bits $val
+}
+
+proc show_RCC { } {
+
+    show_RCC_CR
+    show_RCC_CFGR
+    show_RCC_CIR
+    show_RCC_APB2RSTR
+    show_RCC_APB1RSTR
+    show_RCC_AHBENR
+    show_RCC_APB2ENR
+    show_RCC_APB1ENR
+    show_RCC_BDCR
+    show_RCC_CSR
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/stm32/stm32_regs.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/stm32/stm32_regs.tcl
new file mode 100644
index 0000000..07ff1aa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/st/stm32/stm32_regs.tcl
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# /* Peripheral and SRAM base address in the alias region */
+set PERIPH_BB_BASE        0x42000000
+set SRAM_BB_BASE          0x22000000
+
+# /*Peripheral and SRAM base address in the bit-band region */
+set SRAM_BASE             0x20000000
+set PERIPH_BASE           0x40000000
+
+# /*FSMC registers base address */
+set FSMC_R_BASE           0xA0000000
+
+# /*Peripheral memory map */
+set APB1PERIPH_BASE       [set PERIPH_BASE]
+set APB2PERIPH_BASE       [expr {$PERIPH_BASE + 0x10000}]
+set AHBPERIPH_BASE        [expr {$PERIPH_BASE + 0x20000}]
+
+set TIM2_BASE             [expr {$APB1PERIPH_BASE + 0x0000}]
+set TIM3_BASE             [expr {$APB1PERIPH_BASE + 0x0400}]
+set TIM4_BASE             [expr {$APB1PERIPH_BASE + 0x0800}]
+set TIM5_BASE             [expr {$APB1PERIPH_BASE + 0x0C00}]
+set TIM6_BASE             [expr {$APB1PERIPH_BASE + 0x1000}]
+set TIM7_BASE             [expr {$APB1PERIPH_BASE + 0x1400}]
+set RTC_BASE              [expr {$APB1PERIPH_BASE + 0x2800}]
+set WWDG_BASE             [expr {$APB1PERIPH_BASE + 0x2C00}]
+set IWDG_BASE             [expr {$APB1PERIPH_BASE + 0x3000}]
+set SPI2_BASE             [expr {$APB1PERIPH_BASE + 0x3800}]
+set SPI3_BASE             [expr {$APB1PERIPH_BASE + 0x3C00}]
+set USART2_BASE           [expr {$APB1PERIPH_BASE + 0x4400}]
+set USART3_BASE           [expr {$APB1PERIPH_BASE + 0x4800}]
+set UART4_BASE            [expr {$APB1PERIPH_BASE + 0x4C00}]
+set UART5_BASE            [expr {$APB1PERIPH_BASE + 0x5000}]
+set I2C1_BASE             [expr {$APB1PERIPH_BASE + 0x5400}]
+set I2C2_BASE             [expr {$APB1PERIPH_BASE + 0x5800}]
+set CAN_BASE              [expr {$APB1PERIPH_BASE + 0x6400}]
+set BKP_BASE              [expr {$APB1PERIPH_BASE + 0x6C00}]
+set PWR_BASE              [expr {$APB1PERIPH_BASE + 0x7000}]
+set DAC_BASE              [expr {$APB1PERIPH_BASE + 0x7400}]
+
+set AFIO_BASE             [expr {$APB2PERIPH_BASE + 0x0000}]
+set EXTI_BASE             [expr {$APB2PERIPH_BASE + 0x0400}]
+set GPIOA_BASE            [expr {$APB2PERIPH_BASE + 0x0800}]
+set GPIOB_BASE            [expr {$APB2PERIPH_BASE + 0x0C00}]
+set GPIOC_BASE            [expr {$APB2PERIPH_BASE + 0x1000}]
+set GPIOD_BASE            [expr {$APB2PERIPH_BASE + 0x1400}]
+set GPIOE_BASE            [expr {$APB2PERIPH_BASE + 0x1800}]
+set GPIOF_BASE            [expr {$APB2PERIPH_BASE + 0x1C00}]
+set GPIOG_BASE            [expr {$APB2PERIPH_BASE + 0x2000}]
+set ADC1_BASE             [expr {$APB2PERIPH_BASE + 0x2400}]
+set ADC2_BASE             [expr {$APB2PERIPH_BASE + 0x2800}]
+set TIM1_BASE             [expr {$APB2PERIPH_BASE + 0x2C00}]
+set SPI1_BASE             [expr {$APB2PERIPH_BASE + 0x3000}]
+set TIM8_BASE             [expr {$APB2PERIPH_BASE + 0x3400}]
+set USART1_BASE           [expr {$APB2PERIPH_BASE + 0x3800}]
+set ADC3_BASE             [expr {$APB2PERIPH_BASE + 0x3C00}]
+
+set SDIO_BASE             [expr {$PERIPH_BASE + 0x18000}]
+
+set DMA1_BASE             [expr {$AHBPERIPH_BASE + 0x0000}]
+set DMA1_Channel1_BASE    [expr {$AHBPERIPH_BASE + 0x0008}]
+set DMA1_Channel2_BASE    [expr {$AHBPERIPH_BASE + 0x001C}]
+set DMA1_Channel3_BASE    [expr {$AHBPERIPH_BASE + 0x0030}]
+set DMA1_Channel4_BASE    [expr {$AHBPERIPH_BASE + 0x0044}]
+set DMA1_Channel5_BASE    [expr {$AHBPERIPH_BASE + 0x0058}]
+set DMA1_Channel6_BASE    [expr {$AHBPERIPH_BASE + 0x006C}]
+set DMA1_Channel7_BASE    [expr {$AHBPERIPH_BASE + 0x0080}]
+set DMA2_BASE             [expr {$AHBPERIPH_BASE + 0x0400}]
+set DMA2_Channel1_BASE    [expr {$AHBPERIPH_BASE + 0x0408}]
+set DMA2_Channel2_BASE    [expr {$AHBPERIPH_BASE + 0x041C}]
+set DMA2_Channel3_BASE    [expr {$AHBPERIPH_BASE + 0x0430}]
+set DMA2_Channel4_BASE    [expr {$AHBPERIPH_BASE + 0x0444}]
+set DMA2_Channel5_BASE    [expr {$AHBPERIPH_BASE + 0x0458}]
+set RCC_BASE              [expr {$AHBPERIPH_BASE + 0x1000}]
+set CRC_BASE              [expr {$AHBPERIPH_BASE + 0x3000}]
+
+# /*Flash registers base address */
+set FLASH_R_BASE          [expr {$AHBPERIPH_BASE + 0x2000}]
+# /*Flash Option Bytes base address */
+set OB_BASE               0x1FFFF800
+
+# /*FSMC Bankx registers base address */
+set FSMC_Bank1_R_BASE     [expr {$FSMC_R_BASE + 0x0000}]
+set FSMC_Bank1E_R_BASE    [expr {$FSMC_R_BASE + 0x0104}]
+set FSMC_Bank2_R_BASE     [expr {$FSMC_R_BASE + 0x0060}]
+set FSMC_Bank3_R_BASE     [expr {$FSMC_R_BASE + 0x0080}]
+set FSMC_Bank4_R_BASE     [expr {$FSMC_R_BASE + 0x00A0}]
+
+# /*Debug MCU registers base address */
+set DBGMCU_BASE           0xE0042000
+
+# /*System Control Space memory map */
+set SCS_BASE              0xE000E000
+
+set SysTick_BASE          [expr {$SCS_BASE + 0x0010}]
+set NVIC_BASE             [expr {$SCS_BASE + 0x0100}]
+set SCB_BASE              [expr {$SCS_BASE + 0x0D00}]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/ti/lm3s/lm3s.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/ti/lm3s/lm3s.tcl
new file mode 100644
index 0000000..324aad0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/ti/lm3s/lm3s.tcl
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find chip/ti/lm3s/lm3s_regs.tcl]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/ti/lm3s/lm3s_regs.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/ti/lm3s/lm3s_regs.tcl
new file mode 100644
index 0000000..1e86e29
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/chip/ti/lm3s/lm3s_regs.tcl
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#*****************************************************************************
+#
+# The following are defines for the System Control register addresses.
+#
+#*****************************************************************************
+
+set SYSCTL_DID0             0x400FE000  ;# Device Identification 0
+set SYSCTL_DID1             0x400FE004  ;# Device Identification 1
+set SYSCTL_DC0              0x400FE008  ;# Device Capabilities 0
+set SYSCTL_DC1              0x400FE010  ;# Device Capabilities 1
+set SYSCTL_DC2              0x400FE014  ;# Device Capabilities 2
+set SYSCTL_DC3              0x400FE018  ;# Device Capabilities 3
+set SYSCTL_DC4              0x400FE01C  ;# Device Capabilities 4
+set SYSCTL_DC5              0x400FE020  ;# Device Capabilities 5
+set SYSCTL_DC6              0x400FE024  ;# Device Capabilities 6
+set SYSCTL_DC7              0x400FE028  ;# Device Capabilities 7
+set SYSCTL_DC8              0x400FE02C  ;# Device Capabilities 8 ADC
+                                        ;# Channels
+set SYSCTL_PBORCTL          0x400FE030  ;# Brown-Out Reset Control
+set SYSCTL_LDOPCTL          0x400FE034  ;# LDO Power Control
+set SYSCTL_SRCR0            0x400FE040  ;# Software Reset Control 0
+set SYSCTL_SRCR1            0x400FE044  ;# Software Reset Control 1
+set SYSCTL_SRCR2            0x400FE048  ;# Software Reset Control 2
+set SYSCTL_RIS              0x400FE050  ;# Raw Interrupt Status
+set SYSCTL_IMC              0x400FE054  ;# Interrupt Mask Control
+set SYSCTL_MISC             0x400FE058  ;# Masked Interrupt Status and
+                                        ;# Clear
+set SYSCTL_RESC             0x400FE05C  ;# Reset Cause
+set SYSCTL_RCC              0x400FE060  ;# Run-Mode Clock Configuration
+set SYSCTL_PLLCFG           0x400FE064  ;# XTAL to PLL Translation
+set SYSCTL_GPIOHSCTL        0x400FE06C  ;# GPIO High-Speed Control
+set SYSCTL_GPIOHBCTL        0x400FE06C  ;# GPIO High-Performance Bus
+                                        ;# Control
+set SYSCTL_RCC2             0x400FE070  ;# Run-Mode Clock Configuration 2
+set SYSCTL_MOSCCTL          0x400FE07C  ;# Main Oscillator Control
+set SYSCTL_RCGC0            0x400FE100  ;# Run Mode Clock Gating Control
+                                        ;# Register 0
+set SYSCTL_RCGC1            0x400FE104  ;# Run Mode Clock Gating Control
+                                        ;# Register 1
+set SYSCTL_RCGC2            0x400FE108  ;# Run Mode Clock Gating Control
+                                        ;# Register 2
+set SYSCTL_SCGC0            0x400FE110  ;# Sleep Mode Clock Gating Control
+                                        ;# Register 0
+set SYSCTL_SCGC1            0x400FE114  ;# Sleep Mode Clock Gating Control
+                                        ;# Register 1
+set SYSCTL_SCGC2            0x400FE118  ;# Sleep Mode Clock Gating Control
+                                        ;# Register 2
+set SYSCTL_DCGC0            0x400FE120  ;# Deep Sleep Mode Clock Gating
+                                        ;# Control Register 0
+set SYSCTL_DCGC1            0x400FE124  ;# Deep-Sleep Mode Clock Gating
+                                        ;# Control Register 1
+set SYSCTL_DCGC2            0x400FE128  ;# Deep Sleep Mode Clock Gating
+                                        ;# Control Register 2
+set SYSCTL_DSLPCLKCFG       0x400FE144  ;# Deep Sleep Clock Configuration
+set SYSCTL_CLKVCLR          0x400FE150  ;# Clock Verification Clear
+set SYSCTL_PIOSCCAL         0x400FE150  ;# Precision Internal Oscillator
+                                        ;# Calibration
+set SYSCTL_PIOSCSTAT        0x400FE154  ;# Precision Internal Oscillator
+                                        ;# Statistics
+set SYSCTL_LDOARST          0x400FE160  ;# Allow Unregulated LDO to Reset
+                                        ;# the Part
+set SYSCTL_I2SMCLKCFG       0x400FE170  ;# I2S MCLK Configuration
+set SYSCTL_DC9              0x400FE190  ;# Device Capabilities 9 ADC
+                                        ;# Digital Comparators
+set SYSCTL_NVMSTAT          0x400FE1A0  ;# Non-Volatile Memory Information
+
+set SYSCTL_RCC_USESYSDIV    0x00400000  ;# Enable System Clock Divider
+set SYSCTL_RCC2_BYPASS2     0x00000800  ;# PLL Bypass 2
+set SYSCTL_RCC_MOSCDIS      0x00000001  ;# Main Oscillator Disable
+
+set SYSCTL_SRCR0            0x400FE040  ;# Software Reset Control 0
+set SYSCTL_SRCR1            0x400FE044  ;# Software Reset Control 1
+set SYSCTL_SRCR2            0x400FE048  ;# Software Reset Control 2
+
+set SYSCTL_MISC             0x400FE058  ;# Masked Interrupt Status and Clear
+
+set FLASH_FMA               0x400FD000  ;# Flash Memory Address
+set FLASH_FMD               0x400FD004  ;# Flash Memory Data
+set FLASH_FMC               0x400FD008  ;# Flash Memory Control
+set FLASH_FCRIS             0x400FD00C  ;# Flash Controller Raw Interrupt Status
+set FLASH_FCIM              0x400FD010  ;# Flash Controller Interrupt Mask
+set FLASH_FCMISC            0x400FD014  ;# Flash Controller Masked Interrupt Status and Clear
+set FLASH_FMC2              0x400FD020  ;#  Flash Memory Control 2
+set FLASH_FWBVAL            0x400FD030  ;# Flash Write Buffer Valid
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-5m570z-cpld.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-5m570z-cpld.cfg
new file mode 100644
index 0000000..4504a80
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-5m570z-cpld.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# file altera-5m570z-cpld.cfg replaced by altera-maxv.cfg
+echo "DEPRECATED: use altera-maxv.cfg instead of deprecated altera-5m570z-cpld.cfg"
+
+#just to be backward compatible:
+#tap will be 5m570z.tap instead of maxv.tap:
+set CHIPNAME 5m570z
+source [find cpld/altera-maxv.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-epm240.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-epm240.cfg
new file mode 100644
index 0000000..185925a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-epm240.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# file altera-epm240.cfg replaced by altera-maxii.cfg
+echo "DEPRECATED: use altera-maxii.cfg instead of deprecated altera-epm240.cfg"
+
+#just to be backward compatible:
+#tap will be epm240.tap instead of maxii.tap:
+set CHIPNAME epm240
+source [find cpld/altera-maxii.cfg]
+
+# 200ns seems like a good speed
+# c.f. Table 5-34: MAX II JTAG Timing Parameters
+adapter speed 5000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-max10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-max10.cfg
new file mode 100644
index 0000000..a2ed00a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-max10.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# see MAX 10 FPGA Device Architecture
+# Table 3-1: IDCODE Information for MAX 10 Devices
+# Intel MAX 10M02 0x31810dd
+# Intel MAX 10M04 0x318a0dd
+# Intel MAX 10M08 0x31820dd
+# Intel MAX 10M16 0x31830dd
+# Intel MAX 10M25 0x31840dd
+# Intel MAX 10M40 0x318d0dd
+# Intel MAX 10M50 0x31850dd
+# Intel MAX 10M02 0x31010dd
+# Intel MAX 10M04 0x310a0dd
+# Intel MAX 10M08 0x31020dd
+# Intel MAX 10M16 0x31030dd
+# Intel MAX 10M25 0x31040dd
+# Intel MAX 10M40 0x310d0dd
+# Intel MAX 10M50 0x31050dd
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME max10
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \
+	-expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \
+	-expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \
+	-expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \
+	-expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-maxii.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-maxii.cfg
new file mode 100644
index 0000000..2dee37f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-maxii.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Altera MAXII CPLD
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME maxii
+}
+
+# see MAX II Device Handbook
+# Table 3-3: 32-Bit MAX II Device IDCODE
+# Version     Part Number             Manuf. ID        LSB
+# 0000        0010 0000 1010 0001     000 0110 1110    1
+jtag newtap $_CHIPNAME tap -irlen 10 \
+	-expected-id 0x020a10dd \
+	-expected-id 0x020a20dd \
+	-expected-id 0x020a30dd \
+	-expected-id 0x020a40dd \
+	-expected-id 0x020a50dd \
+	-expected-id 0x020a60dd
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-maxv.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-maxv.cfg
new file mode 100644
index 0000000..03fad07
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/altera-maxv.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Altera MAXV 5M24OZ/5M570Z CPLD
+# see MAX V Device Handbook
+# Table 6-3: 32-Bit MAX V Device IDCODE
+# 5M40Z 5M80Z 5M160Z 5M240Z: 0x020A50DD
+# 5M570Z:                    0x020A60DD
+# 5M1270Z:                   0x020A30DD
+# 5M1270Z 5M2210Z:           0x020A40DD
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME maxv
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 \
+  -expected-id 0x020A50DD -expected-id 0x020A60DD \
+  -expected-id 0x020A30DD -expected-id 0x020A40DD
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/jtagspi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/jtagspi.cfg
new file mode 100644
index 0000000..a7f02b9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/jtagspi.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _USER1 0x02
+
+if { [info exists JTAGSPI_IR] } {
+	set _JTAGSPI_IR $JTAGSPI_IR
+} elseif {[info exists JTAGSPI_CHAIN_ID]} {
+	set _JTAGSPI_CHAIN_ID $JTAGSPI_CHAIN_ID
+} else {
+	set _JTAGSPI_IR $_USER1
+}
+
+if { [info exists TARGETNAME] } {
+	set _TARGETNAME $TARGETNAME
+} else {
+	set _TARGETNAME $_CHIPNAME.proxy
+}
+
+if { [info exists FLASHNAME] } {
+	set _FLASHNAME $FLASHNAME
+} else {
+	set _FLASHNAME $_CHIPNAME.spi
+}
+
+target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
+if { [info exists _JTAGSPI_IR] } {
+	flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
+} else {
+    flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID
+}
+
+# initialize jtagspi flash
+# chain_id: identifier of pld (you can get a list with 'pld devices')
+# proxy_bit: file with bitstream connecting JTAG and SPI interface in the PLD.
+# release_from_pwr_down_cmd: optional, command sent to spi flash before probing.
+#                            ex: 0xAB to release from power-dowm.
+#                            Just omit it to not send a command.
+
+proc jtagspi_init {chain_id proxy_bit {release_from_pwr_down_cmd -1}} {
+	# load proxy bitstream $proxy_bit and probe spi flash
+	global _FLASHNAME
+	if { $proxy_bit ne "" } {
+		pld load $chain_id $proxy_bit
+	}
+	reset halt
+	if {$release_from_pwr_down_cmd != -1} {
+		jtagspi cmd $_FLASHNAME 0 $release_from_pwr_down_cmd
+	}
+	flash probe $_FLASHNAME
+}
+
+proc jtagspi_program {bin addr} {
+	# write and verify binary file $bin at offset $addr
+	global _FLASHNAME
+	flash write_image erase $bin $addr
+	flash verify_bank $_FLASHNAME $bin $addr
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/lattice-lc4032ze.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/lattice-lc4032ze.cfg
new file mode 100644
index 0000000..479180f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/lattice-lc4032ze.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Lattice ispMACH 4000ZE family, device LC4032ZE
+# just configure a tap
+jtag newtap LC4032ZE tap -irlen 8 -expected-id  0x01806043
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc3s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc3s.cfg
new file mode 100644
index 0000000..a886739
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc3s.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx spartan3
+# https://docs.xilinx.com/v/u/en-US/ug332
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc3s
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x01414093 \
+	-expected-id 0x0141C093 \
+	-expected-id 0x01428093 \
+	-expected-id 0x01434093 \
+	-expected-id 0x01440093 \
+	-expected-id 0x01448093 \
+	-expected-id 0x01450093 \
+	-expected-id 0x01C10093 \
+	-expected-id 0x01C1A093 \
+	-expected-id 0x01C22093 \
+	-expected-id 0x01C2E093 \
+	-expected-id 0x01C3A093 \
+	-expected-id 0x0140C093 \
+	-expected-id 0x02210093 \
+	-expected-id 0x02218093 \
+	-expected-id 0x02220093 \
+	-expected-id 0x02228093 \
+	-expected-id 0x02230093 \
+	-expected-id 0x02610093 \
+	-expected-id 0x02618093 \
+	-expected-id 0x02620093 \
+	-expected-id 0x02628093 \
+	-expected-id 0x02630093 \
+	-expected-id 0x03840093 \
+	-expected-id 0x0384e093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc4v.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc4v.cfg
new file mode 100644
index 0000000..3eb46eb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc4v.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 4
+# https://docs.xilinx.com/v/u/en-US/ug071
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc4v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+	-expected-id 0x01658093 \
+	-expected-id 0x01E58093 \
+	-expected-id 0x0167C093 \
+	-expected-id 0x02068093 \
+	-expected-id 0x01E64093 \
+	-expected-id 0x016A4093 \
+	-expected-id 0x02088093 \
+	-expected-id 0x016B4093 \
+	-expected-id 0x020B0093 \
+	-expected-id 0x016D8093 \
+	-expected-id 0x01700093 \
+	-expected-id 0x01718093 \
+	-expected-id 0x01734093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg
new file mode 100644
index 0000000..14dde02
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 4
+# https://docs.xilinx.com/v/u/en-US/ug071
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc4vfx
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \
+	-expected-id 0x01E8C093 \
+	-expected-id 0x01EB4093 \
+	-expected-id 0x01EE4093 \
+	-expected-id 0x01F14093 \
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc5v.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc5v.cfg
new file mode 100644
index 0000000..f88bbc1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc5v.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 5
+# https://docs.xilinx.com/v/u/en-US/ug191
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc5v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+	-expected-id 0x0286E093 \
+	-expected-id 0x02896093 \
+	-expected-id 0x028AE093 \
+	-expected-id 0x028D6093 \
+	-expected-id 0x028EC093 \
+	-expected-id 0x0290C093 \
+	-expected-id 0x0295C093 \
+	-expected-id 0x02A56093 \
+	-expected-id 0x02A6E093 \
+	-expected-id 0x02A96093 \
+	-expected-id 0x02AAE093 \
+	-expected-id 0x02AD6093 \
+	-expected-id 0x02AEC093 \
+	-expected-id 0x02B0C093 \
+	-expected-id 0x02B5C093 \
+	-expected-id 0x02E72093 \
+	-expected-id 0x02E9A093 \
+	-expected-id 0x02ECE093 \
+	-expected-id 0x02F3E093 \
+	-expected-id 0x03276093 \
+	-expected-id 0x032C6093 \
+	-expected-id 0x04502093 \
+	-expected-id 0x0453E093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg
new file mode 100644
index 0000000..7420233
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 5
+# https://docs.xilinx.com/v/u/en-US/ug191
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc5vfx
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \
+	-expected-id 0x032D8093 \
+	-expected-id 0x03300093 \
+	-expected-id 0x03334093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc6s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc6s.cfg
new file mode 100644
index 0000000..862c4aa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc6s.cfg
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx spartan6
+# http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc6s
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x04000093 \
+	-expected-id 0x04001093 \
+	-expected-id 0x04002093 \
+	-expected-id 0x04004093 \
+	-expected-id 0x04024093 \
+	-expected-id 0x04008093 \
+	-expected-id 0x04028093 \
+	-expected-id 0x0400E093 \
+	-expected-id 0x0402E093 \
+	-expected-id 0x04011093 \
+	-expected-id 0x04031093 \
+	-expected-id 0x0401D093 \
+	-expected-id 0x0403D093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x1A 0x1B
+
+set XC6S_CFG_IN 0x05
+set XC6S_JSHUTDOWN 0x0d
+set XC6S_JPROGRAM 0x0b
+set XC6S_JSTART 0x0c
+set XC6S_BYPASS 0x3f
+
+proc xc6s_program {tap} {
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program'"
+	global XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS
+	irscan $tap $XC6S_JSHUTDOWN
+	irscan $tap $XC6S_JPROGRAM
+	irscan $tap $XC6S_JSTART
+	irscan $tap $XC6S_BYPASS
+}
+
+#xtp038 and xc3sprog approach
+proc xc6s_program_iprog {tap} {
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program_iprog'"
+	global XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN
+	irscan $tap $XC6S_JSHUTDOWN
+	runtest 16
+	irscan $tap $XC6S_CFG_IN
+	# xtp038 IPROG 16bit flipped
+	drscan $tap 16 0xffff 16 0x9955 16 0x66aa 16 0x850c 16 0x7000 16 0x0004
+	irscan $tap $XC6S_JSTART
+	runtest 32
+	irscan $tap $XC6S_BYPASS
+	runtest 1
+}
+
+set XC6S_ISC_ENABLE 0x10
+set XC6S_ISC_DISABLE 0x16
+set XC6S_ISC_DNA 0x30
+
+# Get the "Device DNA" from the Spartan 6.
+# Most Xilinx FPGA devices contain an embedded, unique device identifier called
+# the "Device DNA". The identifier is nonvolatile, permanently programmed into
+# the FPGA, and is unchangeable providing a great serial / tracking number.
+proc xc6s_get_dna {tap} {
+	global XC6S_ISC_ENABLE XC6S_ISC_DISABLE XC6S_ISC_DNA
+	irscan $tap $XC6S_ISC_ENABLE
+	runtest 64
+	irscan $tap $XC6S_ISC_DNA
+	# Device DNA is 57 bits long, but we can only read 32bits at a time
+	# with OpenOCD.
+	set dna [drscan $tap 16 0 16 0 16 0 9 0]
+	runtest 64
+	irscan $tap $XC6S_ISC_DISABLE
+	runtest 64
+
+	# Convert the binary data into the order impact uses
+	scan $dna "%x %x %x %x" v1 v2 v3 v4
+	set bin_dna [string reverse [concat [format "%09b" $v4][format "%016b" $v3][format "%016b" $v2][format "%016b" $v1]]]
+
+	# Return a hex version of binary
+	scan [format "0b%s" $bin_dna] "%i" hex_dna
+	return $hex_dna
+}
+
+# Print out the "Device DNA" in the same format that impact uses.
+proc xc6s_print_dna {tap} {
+	set hex_dna [xc6s_get_dna $tap]
+
+	puts [format "DNA = %57b (0x%x)\n" $hex_dna $hex_dna]
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc6v.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc6v.cfg
new file mode 100644
index 0000000..d37439c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc6v.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 6
+# https://www.xilinx.com/support/documentation/user_guides/ug360.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc6v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+	-expected-id 0x042A2093 \
+	-expected-id 0x042A4093 \
+	-expected-id 0x042A8093 \
+	-expected-id 0x042AC093 \
+	-expected-id 0x04244093 \
+	-expected-id 0x0424A093 \
+	-expected-id 0x0424C093 \
+	-expected-id 0x04250093 \
+	-expected-id 0x04252093 \
+	-expected-id 0x04256093 \
+	-expected-id 0x0423A093 \
+	-expected-id 0x04286093 \
+	-expected-id 0x04288093 \
+	-expected-id 0x042C4093 \
+	-expected-id 0x042CA093 \
+	-expected-id 0x042CC093 \
+	-expected-id 0x042D0093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7.cfg
new file mode 100644
index 0000000..6f8f4ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7.cfg
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (spartan, artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7
+}
+
+# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x03622093 \
+	-expected-id 0x03620093 \
+	-expected-id 0x037C4093 \
+	-expected-id 0x0362F093 \
+	-expected-id 0x037C8093 \
+	-expected-id 0x037C7093 \
+	-expected-id 0x037C3093 \
+	-expected-id 0x0362E093 \
+	-expected-id 0x037C2093 \
+	-expected-id 0x0362D093 \
+	-expected-id 0x0362C093 \
+	-expected-id 0x03632093 \
+	-expected-id 0x03631093 \
+	-expected-id 0x03636093 \
+	-expected-id 0x03647093 \
+	-expected-id 0x0364C093 \
+	-expected-id 0x03651093 \
+	-expected-id 0x03747093 \
+	-expected-id 0x03656093 \
+	-expected-id 0x03752093 \
+	-expected-id 0x03751093 \
+	-expected-id 0x03671093 \
+	-expected-id 0x03667093 \
+	-expected-id 0x03682093 \
+	-expected-id 0x03687093 \
+	-expected-id 0x03692093 \
+	-expected-id 0x03691093 \
+	-expected-id 0x03696093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x22 0x23
+
+set XC7_JSHUTDOWN 0x0d
+set XC7_JPROGRAM 0x0b
+set XC7_JSTART 0x0c
+set XC7_BYPASS 0x3f
+
+proc xc7_program {tap} {
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc7_program'"
+	global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
+	irscan $tap $XC7_JSHUTDOWN
+	irscan $tap $XC7_JPROGRAM
+	runtest 60000
+	#JSTART prevents this from working...
+	#irscan $tap $XC7_JSTART
+	runtest 2000
+	irscan $tap $XC7_BYPASS
+	runtest 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7v.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7v.cfg
new file mode 100644
index 0000000..8385948
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7v.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# https://bsdl.info/view.htm?sid=08e275a0cd3ac38988ca59b002289d77
+# https://bsdl.info/view.htm?sid=44dae65d3cf9593188ca59b002289d77
+#
+# this config file is for XC7VX1140T and XC7V2000T only.
+# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7vh870t.cfg or xilinx-xc7.cfg
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7v
+}
+
+#0x036D5093: XC7VX1140T
+#0x036By093: XC7V2000T
+#y = xx11 = 3, 7, B or F
+
+jtag newtap $_CHIPNAME tap -irlen 24 -ignore-version \
+	-expected-id 0x036B3093 -expected-id 0x036B7093 \
+	-expected-id 0x036BB093 -expected-id 0x036BF093 \
+	-expected-id 0x036D5093
+
+#CFG_OUT_SLR0 0x124924
+#CFG_IN_SLR0  0x164924
+#CFG_OUT_SLR1 0x904924
+#CFG_IN_SLR1  0x905924
+#CFG_OUT_SLR2 0x924124
+#CFG_IN_SLR2  0x924164
+#CFG_OUT_SLR3 0x924904
+#CFG_IN_SLR3  0x924905
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+# cfg_out cfg_in jprogb jstart jshutdown
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x2CB2CB 0x30C30C 0x34D34D
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7vh580t.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7vh580t.cfg
new file mode 100644
index 0000000..3748049
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7vh580t.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# https://bsdl.info/view.htm?sid=65c6b2cfe1467b4988ca59b002289d77
+#
+# this config file is for xc7vh580t only.
+# for other virtex-7 devices use xilinx-xc7vh870t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7vh580t
+}
+
+jtag newtap $_CHIPNAME tap -irlen 22 -ignore-version -expected-id 0x036D9093
+
+#CFG_OUT_SLR0 0x0492A0
+#CFG_IN_SLR0  0x0592A0
+#CFG_OUT_SLR1 0x2412A0
+#CFG_IN_SLR1  0x2416A0
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+# cfg_out cfg_in jprogb jstart jshutdown
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x0B2EA0 0x0C32A0 0x0D36A0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7vh870t.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7vh870t.cfg
new file mode 100644
index 0000000..25e2e63
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xc7vh870t.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# https://bsdl.info/view.htm?sid=d9ff0bb764df004588ca59b002289d77
+#
+# this config file is for xc7vh870t only.
+# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7vh870t
+}
+
+jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093
+
+#CFG_OUT_SLR0 0x0492A092A0
+#CFG_IN_SLR0  0x0592A092A0
+#CFG_OUT_SLR1 0x2412A092A0
+#CFG_IN_SLR1  0x2416A092A0
+#CFG_OUT_SLR2 0x2492A012A0
+#CFG_IN_SLR2  0x2492A016A0
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+# cfg_out cfg_in jprogb jstart jshutdown
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFFFFFF 0x3FFFFFFFFF 0x0B2EA02EA0 0x0C32A032A0 0x0D36A036A0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcf-p.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcf-p.cfg
new file mode 100644
index 0000000..7b6d384
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcf-p.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xcf
+}
+
+# IDs acquired from Xilinx's DS123.pdf
+# XCF08P 5057093
+# XCF16P 5058093
+# XCF32P 5059093
+# The 4 top bits (28:31) are the device revision. Ignore it.
+jtag newtap $_CHIPNAME flash -irlen 16 -ignore-version \
+	-expected-id 0x05057093 \
+	-expected-id 0x05058093 \
+	-expected-id 0x05059093
+
+target create xcf.flash testee -chain-position $_CHIPNAME.flash
+flash bank XCF_P xcf 0 0 0 0 xcf.flash
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcf-s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcf-s.cfg
new file mode 100644
index 0000000..417ecff
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcf-s.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xcf
+}
+
+# IDs acquired from Xilinx's DS123.pdf
+# XCF01S 5044093
+# XCF02S 5045093
+# XCF04S 5046093
+# The 4 top bits (28:31) are the device revision. Ignore it.
+jtag newtap $_CHIPNAME flash -irlen 8 -ignore-version \
+	-expected-id 0x05044093 \
+	-expected-id 0x05045093 \
+	-expected-id 0x05046093
+
+target create xcf.flash testee -chain-position $_CHIPNAME.flash
+flash bank XCF_S xcf 0 0 0 0 xcf.flash
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcr3256.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcr3256.cfg
new file mode 100644
index 0000000..4668e54
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcr3256.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#xilinx coolrunner xcr3256
+#simple device - just configure a tap
+jtag newtap xcr tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id  0x0494c093
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcu.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcu.cfg
new file mode 100644
index 0000000..63a67da
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpld/xilinx-xcu.cfg
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx Ultrascale (Kintex, Virtex, Zynq)
+# https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xcu
+}
+
+# The various chips in the Ultrascale family have different IR length.
+# Set $CHIP before including this file to determine the device.
+array set _XCU_DATA {
+	XCKU025         {0x03824093  6}
+	XCKU035         {0x03823093  6}
+	XCKU040         {0x03822093  6}
+	XCKU060         {0x03919093  6}
+	XCKU060_CIV     {0x0381b093  6}
+	XCKU095         {0x03844093  6}
+	XCKU095_CIV     {0x03845093  6}
+	XCKU3P          {0x04A63093  6}
+	XCKU5P          {0x04A62093  6}
+	XCKU9P          {0x0484A093  6}
+	XCKU11P         {0x04A4E093  6}
+	XCKU11P_CIV     {0x04A51093  6}
+	XCKU13P         {0x04A52093  6}
+	XCKU15P         {0x04A56093  6}
+	XCKU15P_CIV     {0x04A59093  6}
+	XCVU065         {0x03939093  6}
+	XCVU065_CIV     {0x0393b093  6}
+	XCVU080         {0x03843093  6}
+	XCVU080_CIV     {0x03845093  6}
+	XCVU095         {0x03842093  6}
+	XCVU2P          {0x04aea093  6}
+	XCVU3P          {0x04B39093  6}
+	XCVU3P_CIV      {0x04b3d093  6}
+	XCAU10P         {0x04AC4033  6}
+	XCAU10P_FFVB676 {0x04AC4093  6}
+	XCAU15P         {0x04AC2033  6}
+	XCAU15P_FFVB676 {0x04AC2093  6}
+	XCAU20P         {0x04A65093  6}
+	XCAU25P         {0x04A64093  6}
+	XCKU5P_CIV      {0x04A64093  6}
+	XCKU19P         {0x04ACF093  6}
+	XCKU19P_CIV     {0x04AD3093  6}
+	XCKU085         {0x0380F093 12}
+	XCKU115         {0x0390D093 12}
+	XCVU125         {0x0392D093 12}
+	XCVU125_CIV     {0x0392f093 12}
+	XCVU5P          {0x04B2B093 12}
+	XCVU5P_CIV      {0x04b2f093 12}
+	XCVU7P          {0x04B29093 12}
+	XCVU7P_CIV      {0x04b2d093 12}
+	XCVU160         {0x03933093 18}
+	XCVU190         {0x03931093 18}
+	XCVU440         {0x0396D093 18}
+	XCVU440_CIV     {0x0396f093 18}
+	XCVU9P          {0x04B31093 18}
+	XCVU9P_CIV      {0x04b35093 18}
+	XCVU11P         {0x04B49093 18}
+	XCVU11P_CIV     {0x04b4f093 18}
+	XCU200_FSGD2104 {0x04b37093 18}
+	XCU250          {0x04b57093 24}
+	XCVU13P         {0x04B51093 24}
+	XCVU13P_CIV     {0x04b55093 24}
+	XCVU15P         {0x04ba3093 24}
+	XCVU19P         {0x04ba1093 24}
+	XCVU19P_CIV     {0x04ba5093 24}
+}
+
+if { ![info exists CHIP] } {
+	error "set CHIP to one of "[concat [array names _XCU_DATA]]
+}
+
+if { ![llength [array names _XCU_DATA $CHIP]] } {
+	error "unknown CHIP: "$CHIP
+}
+
+set _EXPID [lindex $_XCU_DATA($CHIP) 0]
+set _IRLEN [lindex $_XCU_DATA($CHIP) 1]
+
+# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
+jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+
+# set the correct instruction codes for jtag hub and
+# at least the right code for jprogb, jstart and jshutdown for SSI devices
+if { $_IRLEN == 6 } {
+	virtex2 set_user_codes $_CHIPNAME.pld 0x2 0x3 0x22 0x23
+} elseif {$_IRLEN == 12 } {
+	puts "loading bitstream through jtag will not work, but reprogram (refresh)"
+	virtex2 set_instr_codes $_CHIPNAME.pld 0x905 0x904 0x2cb 0x30c 0x34d
+	virtex2 set_user_codes $_CHIPNAME.pld 0x0a4 0x0e4 0x8a4 0x8e4
+} elseif {$_IRLEN == 18 } {
+	puts "loading bitstream through jtag will not work, but reprogram (refresh)"
+	virtex2 set_instr_codes $_CHIPNAME.pld 0x24905 0x24904 0x0b2cb 0x0c30c 0x0d34d
+	virtex2 set_user_codes $_CHIPNAME.pld 0x000a4 0x000e4 0x008a4 0x008e4
+} else {
+	puts "loading bitstream through jtag will not work, but reprogram (refresh)"
+	virtex2 set_instr_codes $_CHIPNAME.pld 0x924905 0x924904 0x2cb2cb 0x30c30c 0x34d34d
+	virtex2 set_user_codes $_CHIPNAME.pld 0x0a4924 0x0e4924 0x8a4924 0x8e4924
+}
+
+set XCU_JSHUTDOWN 0x0d
+set XCU_JPROGRAM 0x0b
+set XCU_JSTART 0x0c
+set XCU_BYPASS 0x3f
+
+proc xcu_program {tap} {
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xcu_program'"
+	global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS
+	irscan $tap $XCU_JSHUTDOWN
+	irscan $tap $XCU_JPROGRAM
+	runtest 60000
+	#JSTART prevents this from working...
+	#irscan $tap $XCU_JSTART
+	runtest 2000
+	irscan $tap $XCU_BYPASS
+	runtest 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/common.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/common.tcl
new file mode 100644
index 0000000..e0de70b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/common.tcl
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+# Things common to all ARCs
+
+# It is assumed that target is already halted.
+proc arc_common_reset { {target ""} } {
+        if { $target != "" } {
+                targets $target
+        }
+
+        halt
+
+        # 1. Interrupts are disabled (STATUS32.IE)
+        # 2. The status register flags are cleared.
+        # All fields, except the H bit, are set to 0 when the processor is Reset.
+
+        arc jtag set-aux-reg 0xA 0x1
+
+        # 3. The loop count, loop start, and loop end registers are cleared.
+        arc jtag set-core-reg 60 0
+        arc jtag set-aux-reg 0x2 0
+        arc jtag set-aux-reg 0x3 0
+
+        # Program execution begins at the address referenced by the four byte reset
+        # vector located at the interrupt vector base address, which is the first
+        # entry (offset 0x00) in the vector table.
+        set int_vector_base [arc jtag get-aux-reg 0x25]
+        set start_pc [read_memory $int_vector_base 32 1]
+        arc jtag set-aux-reg 0x6 $start_pc
+
+        # It is OK to do uncached writes - register cache will be invalidated by
+        # the reset_assert() function.
+}
+
+# vim:expandtab:
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/em.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/em.tcl
new file mode 100644
index 0000000..13c5b43
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/em.tcl
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+source [find cpu/arc/v2.tcl]
+
+proc arc_em_examine_target { {target ""} } {
+	# Will set current target
+	arc_v2_examine_target $target
+}
+
+proc arc_em_init_regs { } {
+	arc_v2_init_regs
+
+	[target current] configure \
+		-event examine-end "arc_em_examine_target [target current]"
+}
+
+# Scripts in "target" folder should call this function instead of direct
+# invocation of arc_common_reset.
+proc arc_em_reset { {target ""} } {
+	arc_v2_reset $target
+
+	# Set DEBUG.ED bit to enable clock in actionpoint module.
+	# This is specific to ARC EM.
+	set debug [arc jtag get-aux-reg 5]
+	if { !($debug & (1 << 20)) } {
+		arc jtag set-aux-reg 5 [expr {$debug | (1 << 20)}]
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/hs.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/hs.tcl
new file mode 100644
index 0000000..28e04f9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/hs.tcl
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+source [find cpu/arc/v2.tcl]
+
+proc arc_hs_examine_target { target } {
+	# Will set current target for us.
+	arc_v2_examine_target $target
+}
+
+proc arc_hs_init_regs { } {
+	arc_v2_init_regs
+
+	[target current] configure \
+		-event examine-end "arc_hs_examine_target [target current]"
+}
+
+# Scripts in "target" folder should call this function instead of direct
+# invocation of arc_common_reset.
+proc arc_hs_reset { {target ""} } {
+	arc_v2_reset $target
+
+	# Invalidate L2 cache if there is one.
+	set l2_config [$target arc jtag get-aux-reg 0x901]
+	# Will return 0, if cache is not present and register doesn't exist.
+	set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+	if { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } {
+		puts "L2 cache is present and not disabled"
+
+		# Wait until BUSY bit is 0.
+		puts "Invalidating L2 cache..."
+		$target arc jtag set-aux-reg 0x905 1
+		# Dummy read of SLC_AUX_CACHE_CTRL bit, as described in:
+		# https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854
+		set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+		set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+		while { ($l2_ctrl & 0x100) != 0 } {
+			set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+		}
+
+		# Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate
+		# operation already flushed everything.
+		if { ($l2_ctrl & 0x40) == 0 } {
+			puts "Flushing L2 cache..."
+			$target arc jtag set-aux-reg 0x904 1
+			set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+			set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+			while { [expr {$l2_ctrl & 0x100}] != 0 } {
+				set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+			}
+		}
+
+		puts "L2 cache has been flushed and invalidated."
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/v2.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/v2.tcl
new file mode 100644
index 0000000..b24a67d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arc/v2.tcl
@@ -0,0 +1,346 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+source [find cpu/arc/common.tcl]
+
+# Currently 'examine_target' can only read JTAG registers and set properties -
+# but it shouldn't write any of registers - writes will be cached, but cache
+# will be invalidated before flushing after examine_target, and changes will be
+# lost.  Perhaps that would be fixed later - perhaps writes shouldn't be cached
+# after all.  But if write to register is really needed from TCL - then it
+# should be done via "arc jtag" for now.
+proc arc_v2_examine_target { {target ""} } {
+	# Set current target, because OpenOCD event handlers don't do this for us.
+	if { $target != "" } {
+		targets $target
+	}
+
+	# Those registers always exist. DEBUG and DEBUGI are formally optional,
+	# however they come with JTAG interface, and so far there is no way
+	# OpenOCD can communicate with target without JTAG interface.
+	arc set-reg-exists identity pc status32 bta debug lp_start lp_end \
+		eret erbta erstatus ecr efa
+
+	# 32 core registers
+	arc set-reg-exists \
+		r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10 r11 r12 \
+		r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 \
+		gp fp sp ilink r30 blink lp_count pcl
+
+	# Actionpoints
+	if { [arc get-reg-field ap_build version] == 5 } {
+		set ap_build_type [arc get-reg-field ap_build type]
+		# AP_BUILD.TYPE > 0b0110 is reserved in current ISA.
+		# Current ISA supports up to 8 actionpoints.
+		if { $ap_build_type < 8 } {
+			# Two LSB bits of AP_BUILD.TYPE define amount of actionpoints:
+			# 0b00 - 2 actionpoints
+			# 0b01 - 4 actionpoints
+			# 0b10 - 8 actionpoints
+			# 0b11 - reserved.
+			set ap_num [expr {0x2 << ($ap_build_type & 3)}]
+			# Expression on top may produce 16 action points - which is a
+			# reserved value for now.
+			if { $ap_num < 16 } {
+				# Enable actionpoint registers
+				for {set i 0} {$i < $ap_num} {incr i} {
+					arc set-reg-exists ap_amv$i ap_amm$i ap_ac$i
+				}
+
+				# Set amount of actionpoints
+				arc num-actionpoints $ap_num
+			}
+		}
+	}
+
+	# DCCM
+	set dccm_version [arc get-reg-field dccm_build version]
+	if { $dccm_version == 3 || $dccm_version == 4 } {
+		arc set-reg-exists aux_dccm
+	}
+
+	# ICCM
+	if { [arc get-reg-field iccm_build version] == 4 } {
+		arc set-reg-exists aux_iccm
+	}
+
+	# MPU
+	if { [arc get-reg-field mpu_build version] >= 2 &&
+		 [arc get-reg-field mpu_build version] <= 4 } {
+		arc set-reg-exists mpu_en mpu_ecr
+		set mpu_regions [arc get-reg-field mpu_build regions]
+		for {set i 0} {$i < $mpu_regions} {incr i} {
+			arc set-reg-exists mpu_rdp$i mpu_rdb$i
+		}
+
+		# Secure MPU
+		if { [arc get-reg-field mpu_build version] == 4 } {
+			arc set-reg-exists mpu_index mpu_rstart mpu_rend mpu_rper
+		}
+	}
+}
+
+proc arc_v2_init_regs { } {
+	# XML features
+	set core_feature "org.gnu.gdb.arc.core.v2"
+	set aux_min_feature "org.gnu.gdb.arc.aux-minimal"
+	set aux_other_feature "org.gnu.gdb.arc.aux-other"
+
+	# Describe types
+	# Types are sorted alphabetically according to their name.
+	arc add-reg-type-struct -name ap_build_t -bitfield version 0 7 \
+		-bitfield type 8 11
+	arc add-reg-type-struct -name ap_control_t -bitfield at 0 3 -bitfield tt 4 5 \
+		-bitfield m 6 6 -bitfield p 7 7 -bitfield aa 8 8 -bitfield q 9 9
+	# Cycles field added in version 4.
+	arc add-reg-type-struct -name dccm_build_t -bitfield version 0 7 \
+		-bitfield size0 8 11 -bitfield size1 12 15 -bitfield cycles 17 19
+
+	arc add-reg-type-struct -name debug_t \
+		-bitfield fh 1 1   -bitfield ah 2 2   -bitfield asr 3 10 \
+		-bitfield is 11 11 -bitfield ep 19 19 -bitfield ed 20 20 \
+		-bitfield eh 21 21 -bitfield ra 22 22 -bitfield zz 23 23 \
+		-bitfield sm 24 26 -bitfield ub 28 28 -bitfield bh 29 29 \
+		-bitfield sh 30 30 -bitfield ld 31 31
+
+	arc add-reg-type-struct -name ecr_t \
+		-bitfield parameter 0 7 \
+		-bitfield cause 8 15 \
+		-bitfield vector 16 23 \
+		-bitfield U 30 30 \
+		-bitfield P 31 31
+	arc add-reg-type-struct -name iccm_build_t -bitfield version 0 7 \
+		-bitfield iccm0_size0  8 11 -bitfield iccm1_size0 12 15 \
+		-bitfield iccm0_size1 16 19 -bitfield iccm1_size1 20 23
+	arc add-reg-type-struct -name identity_t \
+		-bitfield arcver 0 7 -bitfield arcnum 8 15 -bitfield chipid 16 31
+	arc add-reg-type-struct -name isa_config_t -bitfield version 0 7 \
+		-bitfield pc_size 8 11 -bitfield lpc_size 12 15 -bitfield addr_size 16 19 \
+		-bitfield b 20 20 -bitfield a 21 21 -bitfield n 22 22 -bitfield l 23 23 \
+		-bitfield c 24 27 -bitfield d 28 31
+	arc add-reg-type-struct -name mpu_build_t -bitfield version 0 7 \
+		-bitfield regions 8 15 \
+		-bitfield s 16 16 \
+		-bitfield i 17 17
+	arc add-reg-type-struct -name mpu_ecr_t \
+		-bitfield MR 0 7 \
+		-bitfield VT 8 9 \
+		-bitfield EC_CODE 16 31
+	arc add-reg-type-struct -name mpu_en_t \
+		-bitfield UE  3  3 -bitfield UW   4  4 -bitfield UR 5 5 \
+		-bitfield KE  6  6 -bitfield KW   7  7 -bitfield KR 8 8 \
+		-bitfield S  15 15 -bitfield SID 16 23 \
+		-bitfield EN 30 30
+	arc add-reg-type-struct -name mpu_index_t \
+		-bitfield I 0 3 -bitfield M 30 30 -bitfield D 31 31
+	arc add-reg-type-struct -name mpu_rper_t \
+		-bitfield V 0 0 \
+		-bitfield UE 3 3 -bitfield UW 4 4 -bitfield UR 5 5 \
+		-bitfield KE 6 6 -bitfield KW 7 7 -bitfield KR 8 8 \
+		-bitfield S 15 15 -bitfield SID 16 23
+	arc add-reg-type-flags -name status32_t \
+		-flag   H  0 -flag E0   1 -flag E1   2 -flag E2  3 \
+		-flag  E3  4 -flag AE   5 -flag DE   6 -flag  U  7 \
+		-flag   V  8 -flag  C   9 -flag  N  10 -flag  Z 11 \
+		-flag   L 12 -flag DZ  13 -flag SC  14 -flag ES 15 \
+		-flag RB0 16 -flag RB1 17 -flag RB2 18 \
+		-flag  AD 19 -flag US  20 -flag IE  31
+
+	# Core registers
+	set core_regs {
+		r0       0  uint32
+		r1       1  uint32
+		r2       2  uint32
+		r3       3  uint32
+		r4       4  uint32
+		r5       5  uint32
+		r6       6  uint32
+		r7       7  uint32
+		r8       8  uint32
+		r9       9  uint32
+		r10      10 uint32
+		r11      11 uint32
+		r12      12 uint32
+		r13      13 uint32
+		r14      14 uint32
+		r15      15 uint32
+		r16      16 uint32
+		r17      17 uint32
+		r18      18 uint32
+		r19      19 uint32
+		r20      20 uint32
+		r21      21 uint32
+		r22      22 uint32
+		r23      23 uint32
+		r24      24 uint32
+		r25      25 uint32
+		gp       26 data_ptr
+		fp       27 data_ptr
+		sp       28 data_ptr
+		ilink    29 code_ptr
+		r30      30 uint32
+		blink    31 code_ptr
+		r32      32 uint32
+		r33      33 uint32
+		r34      34 uint32
+		r35      35 uint32
+		r36      36 uint32
+		r37      37 uint32
+		r38      38 uint32
+		r39      39 uint32
+		r40      40 uint32
+		r41      41 uint32
+		r42      42 uint32
+		r43      43 uint32
+		r44      44 uint32
+		r45      45 uint32
+		r46      46 uint32
+		r47      47 uint32
+		r48      48 uint32
+		r49      49 uint32
+		r50      50 uint32
+		r51      51 uint32
+		r52      52 uint32
+		r53      53 uint32
+		r54      54 uint32
+		r55      55 uint32
+		r56      56 uint32
+		r57      57 uint32
+		accl     58 uint32
+		acch     59 uint32
+		lp_count 60 uint32
+		limm     61 uint32
+		reserved 62 uint32
+		pcl      63 code_ptr
+	}
+	foreach {reg count type} $core_regs {
+		arc add-reg -name $reg -num $count -core -type $type -g \
+			-feature $core_feature
+	}
+
+	# AUX min
+	set aux_min {
+		0x6 pc       code_ptr
+		0x2 lp_start code_ptr
+		0x3 lp_end   code_ptr
+		0xA status32 status32_t
+	}
+	foreach {num name type} $aux_min {
+		arc add-reg -name $name -num $num -type $type -feature $aux_min_feature -g
+	}
+
+	# AUX other
+	set aux_other {
+		0x004 identity	identity_t
+		0x005 debug		debug_t
+		0x018 aux_dccm	int
+		0x208 aux_iccm	int
+
+		0x220 ap_amv0	uint32
+		0x221 ap_amm0	uint32
+		0x222 ap_ac0	ap_control_t
+		0x223 ap_amv1	uint32
+		0x224 ap_amm1	uint32
+		0x225 ap_ac1	ap_control_t
+		0x226 ap_amv2	uint32
+		0x227 ap_amm2	uint32
+		0x228 ap_ac2	ap_control_t
+		0x229 ap_amv3	uint32
+		0x22A ap_amm3	uint32
+		0x22B ap_ac3	ap_control_t
+		0x22C ap_amv4	uint32
+		0x22D ap_amm4	uint32
+		0x22E ap_ac4	ap_control_t
+		0x22F ap_amv5	uint32
+		0x230 ap_amm5	uint32
+		0x231 ap_ac5	ap_control_t
+		0x232 ap_amv6	uint32
+		0x233 ap_amm6	uint32
+		0x234 ap_ac6	ap_control_t
+		0x235 ap_amv7	uint32
+		0x236 ap_amm7	uint32
+		0x237 ap_ac7	ap_control_t
+
+		0x400 eret		code_ptr
+		0x401 erbta		code_ptr
+		0x402 erstatus	status32_t
+		0x403 ecr		ecr_t
+		0x404 efa		data_ptr
+
+		0x409 mpu_en	mpu_en_t
+
+		0x412 bta		code_ptr
+
+		0x420 mpu_ecr	mpu_ecr_t
+		0x422 mpu_rdb0	int
+		0x423 mpu_rdp0	int
+		0x424 mpu_rdb1	int
+		0x425 mpu_rdp1	int
+		0x426 mpu_rdb2	int
+		0x427 mpu_rdp2	int
+		0x428 mpu_rdb3	int
+		0x429 mpu_rdp3	int
+		0x42A mpu_rdb4	int
+		0x42B mpu_rdp4	int
+		0x42C mpu_rdb5	int
+		0x42D mpu_rdp5	int
+		0x42E mpu_rdb6	int
+		0x42F mpu_rdp6	int
+		0x430 mpu_rdb7	int
+		0x431 mpu_rdp7	int
+		0x432 mpu_rdb8	int
+		0x433 mpu_rdp8	int
+		0x434 mpu_rdb9	int
+		0x435 mpu_rdp9	int
+		0x436 mpu_rdb10	int
+		0x437 mpu_rdp10	int
+		0x438 mpu_rdb11	int
+		0x439 mpu_rdp11	int
+		0x43A mpu_rdb12	int
+		0x43B mpu_rdp12	int
+		0x43C mpu_rdb13	int
+		0x43D mpu_rdp13	int
+		0x43E mpu_rdb14	int
+		0x43F mpu_rdp14	int
+		0x440 mpu_rdb15	int
+		0x441 mpu_rdp15	int
+		0x448 mpu_index	mpu_index_t
+		0x449 mpu_rstart uint32
+		0x44A mpu_rend	uint32
+		0x44B mpu_rper	mpu_rper_t
+		0x44C mpu_probe uint32
+	}
+	foreach {num name type} $aux_other {
+		arc add-reg -name $name -num $num -type $type -feature $aux_other_feature
+	}
+
+	# AUX BCR
+	set bcr {
+		0x6D mpu_build
+		0x74 dccm_build
+		0x76 ap_build
+		0x78 iccm_build
+		0xC1 isa_config
+	}
+	foreach {num reg} $bcr {
+		arc add-reg -name $reg -num $num -type ${reg}_t -bcr -feature $aux_other_feature
+	}
+
+	[target current] configure \
+		-event examine-end "arc_v2_examine_target [target current]"
+}
+
+proc arc_v2_reset { {target ""} } {
+	arc_common_reset $target
+
+	# Disable all actionpoints.  Cannot write via regcache yet, because it will
+	# not be flushed and all changes to registers will get lost.  Therefore has
+	# to write directly via JTAG layer...
+	set num_ap [arc num-actionpoints]
+	for {set i 0} {$i < $num_ap} {incr i} {
+		arc jtag set-aux-reg [expr {0x222 + $i * 3}] 0
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm7tdmi.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm7tdmi.tcl
new file mode 100644
index 0000000..e407a23
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm7tdmi.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   arm7tdmi
+set CPU_ARCH   armv4t
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm920.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm920.tcl
new file mode 100644
index 0000000..1c5a8ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm920.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   arm920
+set CPU_ARCH   armv4t
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm946.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm946.tcl
new file mode 100644
index 0000000..602d4d7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm946.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   arm946
+set CPU_ARCH   armv5te
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm966.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm966.tcl
new file mode 100644
index 0000000..0e64312
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/arm966.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   arm966
+set CPU_ARCH   armv5te
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/cortex_m3.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/cortex_m3.tcl
new file mode 100644
index 0000000..0791664
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/arm/cortex_m3.tcl
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set CPU_TYPE   arm
+set CPU_NAME   cortex_m3
+set CPU_ARCH   armv7
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/nuclei/cpuinfo.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/nuclei/cpuinfo.tcl
new file mode 100644
index 0000000..db69983
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/cpu/nuclei/cpuinfo.tcl
@@ -0,0 +1,376 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc get_register {reg} {
+	set reg_info [get_reg $reg]
+	return [lindex $reg_info 1]
+}
+
+proc get_memory {addr} {
+	return [read_memory $addr 32 1]
+}
+
+proc extract_field {val which} {
+	set part_a [expr $val&$which]
+	set part_b [expr $which&[expr ~[expr $which-1]]]
+	return [expr $part_a/$part_b]
+}
+
+proc pow_of_two {n} {
+	return [expr 1<<$n]
+}
+
+proc linesz {n} {
+	switch $n {
+		"0" {
+			return 0
+		}
+		default {
+			pow_of_two [expr $n-1]
+		}
+	}
+}
+
+proc show_safety_mechanism {safetyMode} {
+	switch $safetyMode {
+		"0" {
+			puts -nonewline " No-Safety-Mechanism"
+		}
+		"1" {
+			puts -nonewline " Lockstep"
+		}
+		"2" {
+			puts -nonewline " Lockstep+SplitMode"
+		}
+		"3" {
+			puts -nonewline " ASIL-B"
+		}
+	}
+}
+
+proc show_vpu_degree {degree} {
+	switch $degree {
+		"0" {
+			puts -nonewline " DLEN=VLEN/2"
+		}
+		"1" {
+			puts -nonewline " DLEN=VLEN"
+		}
+	}
+}
+
+proc format_display {bytes} {
+	if [expr $bytes/[expr 1024*1024*1024]] {
+		puts -nonewline [format " %dGB" [expr $bytes/[expr 1024*1024*1024]]]
+	} elseif [expr $bytes/[expr 1024*1024]] {
+		puts -nonewline [format " %dMB" [expr $bytes/[expr 1024*1024]]]
+	} elseif [expr $bytes/[expr 1024]] {
+		puts -nonewline [format " %dKB" [expr $bytes/[expr 1024]]]
+	} else {
+		puts -nonewline [format " %dByte" $bytes]
+	}
+}
+
+proc show_cache_info {set way lsize ecc} {
+	format_display [expr $set*$way*$lsize]
+	puts -nonewline [format "(set=%d," $set]
+	puts -nonewline [format "way=%d," $way]
+	puts -nonewline [format "lsize=%d," $lsize]
+	puts -nonewline [format "ecc=%d)" [expr !!$ecc]]
+}
+
+proc nuclei_cpuinfo {} {
+
+	set riscv_info [riscv info]
+	dict for {key value} $riscv_info {
+		if {$key == "hart.xlen"} {
+			set xlen $value
+		}
+	}
+
+	puts "-----Nuclei RISC-V CPU Configuration Information-----"
+
+	set marchid [get_register marchid]
+	if {$marchid != 0} {
+		puts [format "         MARCHID: %lx" $marchid]
+	}
+
+	set mimpid [get_register mimpid]
+	if {$mimpid != 0} {
+		puts [format "          MIMPID: %lx" $mimpid]
+	}
+
+	set misa [get_register misa]
+	if {$misa != 0} {
+		puts -nonewline "             ISA:"
+		if {$xlen == 32} {
+			puts -nonewline " RV32"
+		} else {
+			puts -nonewline " RV64"
+		}
+		for {set i 0}  {$i < 26} {incr i} {
+			if [expr 1&[expr $misa>>$i]] {
+				if {88 == [expr 65+$i]} {
+					puts -nonewline " NICE"
+				} else {
+					puts -nonewline [format " %c" [expr 65+$i]]
+				}
+			}
+		}
+	}
+
+	set mcfg_info [get_register mcfg_info]
+	if [expr $mcfg_info&[expr 1<<12]] {
+		puts -nonewline " Xxldspn1x"
+	}
+	if [expr $mcfg_info&[expr 1<<13]] {
+		puts -nonewline " Xxldspn2x"
+	}
+	if [expr $mcfg_info&[expr 1<<14]] {
+		puts -nonewline " Xxldspn3x"
+	}
+	if [expr $mcfg_info&[expr 1<<15]] {
+		puts -nonewline " Zc Xxlcz"
+	}
+	if [expr $mcfg_info&[expr 1<<19]] {
+		puts -nonewline " Smwg"
+	}
+	puts ""
+
+	if {$mcfg_info != 0} {
+		puts -nonewline "            MCFG:"
+		if [expr $mcfg_info&[expr 1<<0]] {
+			puts -nonewline " TEE"
+		}
+		if [expr $mcfg_info&[expr 1<<1]] {
+			puts -nonewline " ECC"
+		}
+		if [expr $mcfg_info&[expr 1<<2]] {
+			puts -nonewline " ECLIC"
+		}
+		if [expr $mcfg_info&[expr 1<<3]] {
+			puts -nonewline " PLIC"
+		}
+		if [expr $mcfg_info&[expr 1<<4]] {
+			puts -nonewline " FIO"
+		}
+		if [expr $mcfg_info&[expr 1<<5]] {
+			puts -nonewline " PPI"
+		}
+		if [expr $mcfg_info&[expr 1<<6]] {
+			puts -nonewline " NICE"
+		}
+		if [expr $mcfg_info&[expr 1<<7]] {
+			puts -nonewline " ILM"
+		}
+		if [expr $mcfg_info&[expr 1<<8]] {
+			puts -nonewline " DLM"
+		}
+		if [expr $mcfg_info&[expr 1<<9]] {
+			puts -nonewline " ICACHE"
+		}
+		if [expr $mcfg_info&[expr 1<<10]] {
+			puts -nonewline " DCACHE"
+		}
+		if [expr $mcfg_info&[expr 1<<11]] {
+			puts -nonewline " SMP"
+		}
+		if [expr $mcfg_info&[expr 1<<12]] {
+			puts -nonewline " DSP-N1"
+		}
+		if [expr $mcfg_info&[expr 1<<13]] {
+			puts -nonewline " DSP-N2"
+		}
+		if [expr $mcfg_info&[expr 1<<14]] {
+			puts -nonewline " DSP-N3"
+		}
+		if [expr $mcfg_info&[expr 1<<15]] {
+			puts -nonewline " ZC_XLCZ_EXT"
+		}
+		if [expr $mcfg_info&[expr 1<<16]] {
+			puts -nonewline " IREGION"
+		}
+		if [expr $mcfg_info&[expr 1<<19]] {
+			puts -nonewline " SEC_MODE"
+		}
+		if [expr $mcfg_info&[expr 1<<20]] {
+			puts -nonewline " ETRACE"
+		}
+		if [expr $mcfg_info&[expr 1<<23]] {
+			puts -nonewline " VNICE"
+		}
+		show_safety_mechanism [extract_field $mcfg_info [expr 0x3<<21]]
+		show_vpu_degree [extract_field $mcfg_info [expr 0x3<<17]]
+		puts ""
+
+		if [expr $mcfg_info&[expr 1<<7]] {
+			set micfg_info [get_register micfg_info]
+			if {$micfg_info != 0} {
+				puts -nonewline "             ILM:"
+				format_display [expr [pow_of_two [expr [extract_field $micfg_info [expr 0x1F<<16]]-1]]*256]
+				if [expr $micfg_info&[expr 1<<21]] {
+					puts -nonewline " execute-only"
+				}
+				if [expr $micfg_info&[expr 1<<22]] {
+					puts -nonewline " has-ecc"
+				}
+				puts ""
+			}
+		}
+
+		if [expr $mcfg_info&[expr 1<<8]] {
+			set mdcfg_info [get_register mdcfg_info]
+			if {$mdcfg_info != 0} {
+				puts -nonewline "             DLM:"
+				format_display [expr [pow_of_two [expr [extract_field $mdcfg_info [expr 0x1F<<16]]-1]]*256]
+				if [expr $mdcfg_info&[expr 1<<21]] {
+					puts -nonewline " has-ecc"
+				}
+				puts ""
+			}
+		}
+
+		if [expr $mcfg_info&[expr 1<<9]] {
+			set micfg_info [get_register micfg_info]
+			if {$micfg_info != 0} {
+				puts -nonewline "          ICACHE:"
+				show_cache_info [pow_of_two [expr [extract_field $micfg_info 0xF]+3]] \
+								[expr [extract_field $micfg_info [expr 7<<4]]+1] \
+								[pow_of_two [expr [extract_field $micfg_info [expr 7<<7]]+2]] \
+								[extract_field $mcfg_info [expr 0x1<<1]]
+				puts ""
+			}
+		}
+
+		if [expr $mcfg_info&[expr 1<<10]] {
+			set mdcfg_info [get_register mdcfg_info]
+			if {$mdcfg_info != 0} {
+				puts -nonewline "          DCACHE:"
+				show_cache_info [pow_of_two [expr [extract_field $mdcfg_info 15]+3]] \
+								[expr [extract_field $mdcfg_info [expr 7<<4]]+1] \
+								[pow_of_two [expr [extract_field $mdcfg_info [expr 7<<7]]+2]] \
+								[extract_field $mcfg_info [expr 0x1<<1]]
+				puts ""
+			}
+		}
+
+		if [expr $mcfg_info&[expr 1<<3]] {
+			set mtlbcfg_info [get_register mtlbcfg_info]
+			puts -nonewline "             TLB:"
+			puts -nonewline [format " MainTLB(set=%lu" [pow_of_two [expr [extract_field $mtlbcfg_info 0xF]+3]]]
+			puts -nonewline [format " way=%lu" [expr [extract_field $mtlbcfg_info [expr 0x7<<4]]+1]]
+			puts -nonewline [format " entry=%lu" [linesz [extract_field $mtlbcfg_info [expr 0x7<<7]]]]
+			puts -nonewline [format " ecc=%lu)" [extract_field $mtlbcfg_info [expr 0x1<<10]]]
+			puts -nonewline [format " ITLB(entry=%lu)" [linesz [extract_field $mtlbcfg_info [expr 0x7<<16]]]]
+			puts -nonewline [format " DTLB(entry=%lu)" [linesz [extract_field $mtlbcfg_info [expr 0x7<<19]]]]
+			puts ""
+		}
+
+		if [expr $mcfg_info&[expr 1<<16]] {
+			set mirgb_info [get_register mirgb_info]
+			puts -nonewline "         IREGION:"
+			set iregion_base [expr $mirgb_info&[expr ~0x3FF]]
+			puts -nonewline [format " 0x%lx" $iregion_base]
+			format_display [expr [pow_of_two [expr [extract_field $mirgb_info [expr 0x1F<<1]]-1]]*1024]
+			puts ""
+			puts "                  Unit        Size        Address"
+			puts [format "                  INFO        64KB        0x%lx" $iregion_base]
+			puts [format "                  DEBUG       64KB        0x%lx" [expr $iregion_base+0x10000]]
+			if [expr $mcfg_info&[expr 1<<2]] {
+				puts [format "                  ECLIC       64KB        0x%lx" [expr $iregion_base+0x20000]]
+			}
+			puts [format "                  TIMER       64KB        0x%lx" [expr $iregion_base+0x30000]]
+			if [expr $mcfg_info&[expr 1<<11]] {
+				puts [format "                  SMP         64KB        0x%lx" [expr $iregion_base+0x40000]]
+			}
+			set smp_cfg [get_memory [expr $iregion_base+0x40004]]
+			if [expr $mcfg_info&[expr 1<<2]] {
+				if {[extract_field $smp_cfg [expr 31<<1]] >= 2} {
+					puts [format "                  CIDU        64KB        0x%lx" [expr $iregion_base+0x50000]]
+				}
+			}
+			if [expr $mcfg_info&[expr 1<<3]] {
+				puts [format "                  PLIC        64MB        0x%lx" [expr $iregion_base+0x4000000]]
+			}
+
+			if [expr $mcfg_info&[expr 1<<11]] {
+				puts -nonewline "         SMP_CFG:"
+				puts -nonewline [format " CC_PRESENT=%ld" [extract_field $smp_cfg 0x1]]
+				puts -nonewline [format " SMP_CORE_NUM=%ld" [extract_field $smp_cfg [expr 0x3F<<1]]]
+				puts -nonewline [format " IOCP_NUM=%ld" [extract_field $smp_cfg [expr 0x3F<<7]]]
+				puts [format " PMON_NUM=%ld" [extract_field $smp_cfg [expr 0x3F<<13]]]
+			}
+
+			if [expr $mcfg_info&[expr 1<<2]] {
+				set clic_base [expr $iregion_base+0x20000]
+				set clic_cfg [expr $clic_base+0x0]
+				set clic_info [expr $clic_base+0x4]
+				set clic_mth [expr $clic_base+0x8]
+				set clic_cfg_value [get_memory $clic_cfg]
+				set clic_info_value [get_memory $clic_info]
+				set clic_mth_value [get_memory $clic_mth]
+				puts -nonewline "         ECLIC:"
+				puts -nonewline [format " VERSION=0x%x" [extract_field $clic_info_value [expr 0xFF<<13]]]
+				puts -nonewline [format " NUM_INTERRUPT=%x" [extract_field $clic_info_value [expr 0xFFF<<0]]]
+				puts -nonewline [format " CLICINTCTLBITS=%x" [extract_field $clic_info_value [expr 0xF<<21]]]
+				puts -nonewline [format " MTH=%x" [extract_field $clic_mth_value [expr 0xFF<<24]]]
+				puts [format " NLBITS=%x" [extract_field $clic_cfg_value [expr 0xF<<1]]]
+			}
+
+			if [expr $smp_cfg&1] {
+				puts -nonewline "         L2CACHE:"
+				set cc_cfg [get_memory [expr $iregion_base+0x40008]]
+				show_cache_info [pow_of_two [extract_field $cc_cfg 0xF]] \
+								[expr [extract_field $cc_cfg [expr 0xF<<4]]+1] \
+								[pow_of_two [expr [extract_field $cc_cfg [expr 0x7<<8]]+2]] \
+								[extract_field $cc_cfg [expr 0x1<<11]]
+				puts ""
+			}
+
+			puts "     INFO-Detail:"
+			set mpasize [get_memory $iregion_base]
+			puts [format "                  mpasize : %ld" $mpasize]
+			set cmo_info [get_memory [expr $iregion_base+4]]
+			if [expr $cmo_info&1] {
+				puts [format "                  cbozero : %dByte" \
+					[pow_of_two [expr [extract_field $cmo_info [expr 0xF<<6]]+2]]]
+				puts [format "                  cmo     : %dByte" \
+					[pow_of_two [expr [extract_field $cmo_info [expr 0xF<<2]]+2]]]
+				if [expr $cmo_info&2] {
+					puts "                  has_prefecth"
+				}
+			}
+			set mcppi_cfg_lo [get_memory [expr $iregion_base+0x80]]
+			set mcppi_cfg_hi [get_memory [expr $iregion_base+0x84]]
+			if [expr $mcppi_cfg_lo&1] {
+				if {$xlen == 32} {
+					puts -nonewline [format "                  cppi    : 0x%lx" \
+						[expr $mcppi_cfg_lo&[expr ~0x3FF]]]
+				} else {
+					puts -nonewline [format "                  cppi    : 0x%lx" \
+						[expr [expr $mcppi_cfg_hi<<32]|[expr $mcppi_cfg_lo&[expr ~0x3FF]]]]
+				}
+				format_display [expr [pow_of_two [expr [extract_field $mcppi_cfg_lo [expr 0x1F<<1]-1]]]*1024]
+				puts " "
+			}
+			puts ""
+		}
+
+		if [expr $mcfg_info&[expr 1<<4]] {
+			set mfiocfg_info [get_register mfiocfg_info]
+			puts -nonewline "             FIO:"
+			puts -nonewline [format " 0x%lx" [expr $mfiocfg_info&[expr ~0x3FF]]]
+			format_display [expr [pow_of_two [expr [extract_field $mfiocfg_info [expr 0x1F<<1]]-1]]*1024]
+			puts ""
+		}
+
+		if [expr $mcfg_info&[expr 1<<5]] {
+			set mppicfg_info [get_register mppicfg_info]
+			puts -nonewline "             PPI:"
+			puts -nonewline [format " 0x%lx" [expr $mppicfg_info&[expr ~0x3FF]]]
+			format_display [expr [pow_of_two [expr [extract_field $mppicfg_info [expr 0x1F<<1]]-1]]*1024]
+			puts ""
+		}
+	}
+
+	puts "----End of cpuinfo-----"
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-10m50.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-10m50.cfg
new file mode 100644
index 0000000..94228d2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-10m50.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# file altera-10m50.cfg replaced by altera-max10.cfg
+echo "DEPRECATED: use altera-max10.cfg instead of deprecated altera-10m50.cfg"
+
+#just to be backward compatible:
+#tap will be 10m50.tap instead of max10.tap:
+set CHIPNAME 10m50
+source [find cpld/altera-max10.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-arriaii.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-arriaii.cfg
new file mode 100644
index 0000000..9cf680d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-arriaii.cfg
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Arria II FPGA
+# Arria II Device Handbook
+# Table 11–2. 32-Bit IDCODE for Arria II Devices
+
+#GX:
+#EP2AGX45:  0x025120dd
+#EP2AGX65:  0x025020dd
+#EP2AGX95:  0x025130dd
+#EP2AGX125: 0x025030dd
+#EP2AGX190: 0x025140dd
+#EP2AGX260: 0x025040dd
+#EP2AGZ225: 0x024810dd
+#EP2AGZ300: 0x0240a0dd
+#EP2AGZ350: 0x024820dd
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME arriaii
+}
+
+array set _ARRIA_2_DATA {
+  0x025120dd {1227 1174 EP2AGX45}
+  0x025020dd {1227   -1 EP2AGX65}
+  0x025130dd {1467   -1 EP2AGX95}
+  0x025030dd {1467   -1 EP2AGX125}
+  0x025140dd {1971   -1 EP2AGX190}
+  0x025040dd {1971   -1 EP2AGX260}
+  0x024810dd {2274   -1 EP2AGZ225}
+  0x0240a0dd {2682   -1 EP2AGZ300}
+  0x024820dd {2682   -1 EP2AGZ350}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _ARRIA_2_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_ARRIA_2_DATA}"
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cyclone10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cyclone10.cfg
new file mode 100644
index 0000000..0898c74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cyclone10.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone 10 FPGA
+# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html
+# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cyclone10
+}
+
+array set _CYCLONE_10_DATA {
+  0x020f10dd { 603 226 10cl006_10cl010}
+  0x020f20dd {1080 409 10cl016}
+  0x020f30dd { 732 286 10cl025}
+  0x020f40dd {1632 604 10cl040}
+  0x020f50dd {1164 442 10cl055}
+  0x020f60dd {1314 502 10cl080}
+  0x020f70dd {1620 613 10cl120}
+  0x02e120dd {1339  -1 GX085}
+  0x02e320dd {1339  -1 GX105}
+  0x02e720dd {1339  -1 GX150}
+  0x02ef20dd {1339  -1 GX220}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_10_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclone10
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_10_DATA}"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cycloneiii.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cycloneiii.cfg
new file mode 100644
index 0000000..b0da418
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cycloneiii.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone III FPGA
+# see Cyclone III Device Handbook
+# Table 12-2: Device IDCODE for Cyclone III Device Family
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cycloneiii
+}
+
+array set _CYCLONE_3_DATA {
+  0x020f10dd { 603 226 EP3C5_EP3C10}
+  0x020f20dd {1080 409 EP3C16}
+  0x020f30dd { 732 286 EP3C25}
+  0x020f40dd {1632 604 EP3C40}
+  0x020f50dd {1164 442 EP3C55}
+  0x020f60dd {1314 502 EP3C80}
+  0x020f70dd {1620 613 EP3C120}
+  0x027010dd {1314 226 EP3CLS70}
+  0x027000dd {1314 226 EP3CLS100}
+  0x027030dd {1314 409 EP3CLS150}
+  0x027020dd {1314 409 EP3CLS200}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_3_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_3_DATA}"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cycloneiv.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cycloneiv.cfg
new file mode 100644
index 0000000..44eb89d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cycloneiv.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone IV FPGA
+# see Cyclone IV Device Handbook
+# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cycloneiv
+}
+
+array set _CYCLON_4_DATA {
+  0x020f10dd { 603  226 EP4CE6_EP4CE10}
+  0x020f20dd {1080  409 EP4CE15}
+  0x020f30dd { 732  286 EP4CE22}
+  0x020f40dd {1632  604 EP4CE30_EP4CE40}
+  0x020f50dd {1164  442 EP4CE55}
+  0x020f60dd {1314  502 EP4CE75}
+  0x020f70dd {1620  613 EP4CE115}
+  0x028010dd { 260  229 EP4CGX15}
+  0x028120dd { 494  463 EP4CGX22}
+  0x028020dd { 494  463 EP4CGX30}
+  0x028230dd {1006  943 EP4CGX30}
+  0x028130dd {1006  943 EP4CGX50}
+  0x028030dd {1006  943 EP4CGX75}
+  0x028140dd {1495 1438 EP4CGX110}
+  0x028040dd {1495 1438 EP4CGX150}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLON_4_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_4_DATA}"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cyclonev.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cyclonev.cfg
new file mode 100644
index 0000000..8d19cd8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-cyclonev.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone 5 FPGA
+# see Cyclone V Device Handbook
+# Table 9-1: IDCODE Information for Cyclone V Devices
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cyclonev
+}
+
+array set _CYCLONE_5_DATA {
+  0x02b150dd { 864 163 5CEA2}
+  0x02d020dd {1485  19 5CSEA6_5CSXC6_5CSTD6}
+  0x02b040dd {1728  -1 5CGXC9_5CGTD9}
+  0x02b050dd { 864 163 5CEA4}
+  0x02b030dd {1488  19 5CGXC7_5CGTD7}
+  0x02d120dd {1485  -1 5CSEA5_5CSXC5_5CSTD5}
+  0x02b220dd {1104  19 5CEA5}
+  0x02b020dd {1104  19 5CGXC5_5CGTD5}
+  0x02d010dd {1197  -1 5CSEA4_5CSXC4}
+  0x02b120dd {1104  19 5CGXC4}
+  0x02b140dd {1728  -1 5CEA9}
+  0x02b010dd { 720  19 5CGXC3}
+  0x02b130dd {1488  19 5CEA7}
+  0x02d110dd {1197  -1 5CSEA2_5CSXC2}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_5_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
+
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_5_DATA}"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-ep3c10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-ep3c10.cfg
new file mode 100644
index 0000000..d7a92d7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera-ep3c10.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# file altera-ep3c10.cfg replaced by altera-cycloneiii.cfg
+echo "DEPRECATED: use altera-cycloneiii.cfg instead of deprecated altera-ep3c10.cfg"
+
+#just to be backward compatible:
+#tap will be ep3c10.tap instead of cycloneiii.tap:
+set CHIPNAME ep3c10
+source [find fpga/altera-cycloneiii.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera_common_init.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera_common_init.cfg
new file mode 100644
index 0000000..683a844
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/altera_common_init.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc set_bscan_checkpos_on_setup {chipname data} {
+  set tapid_w_version [jtag cget $chipname.tap -idcode]
+  set version_mask 0x0fffffff
+  set tapid [format 0x%08x [expr {$tapid_w_version & $version_mask}]]
+  intel set_bscan $chipname.pld [lindex $data($tapid) 0]
+  intel set_check_pos $chipname.pld [lindex $data($tapid) 1]
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/efinix_titanium.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/efinix_titanium.cfg
new file mode 100644
index 0000000..3c2cdd7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/efinix_titanium.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# efinix titanium
+# https://www.efinixinc.com/docs/an048-jtag-bst-titanium-v1.0.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME titanium
+}
+
+jtag newtap $_CHIPNAME tap -irlen 5 -ignore-version \
+	-expected-id 0x10661A79 \
+	-expected-id 0x00360A79 \
+	-expected-id 0x10660A79 \
+	-expected-id 0x00681A79 \
+	-expected-id 0x00688A79 \
+	-expected-id 0x00682A79 \
+	-expected-id 0x0068CA79 \
+	-expected-id 0x00680A79 \
+	-expected-id 0x00684A79
+
+pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family titanium
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/efinix_trion.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/efinix_trion.cfg
new file mode 100644
index 0000000..1c789f5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/efinix_trion.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# efinix trion
+# https://www.efinixinc.com/docs/an021-jtag-bst-trion-v1.0.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME trion
+}
+
+jtag newtap $_CHIPNAME tap -irlen 4 -ignore-version \
+	-expected-id 0x00210A79 \
+	-expected-id 0x00240A79 \
+	-expected-id 0x00220A79
+
+pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family trion
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/gatemate.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/gatemate.cfg
new file mode 100644
index 0000000..e8f3382
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/gatemate.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# GateMateTM FPGA
+# https://www.colognechip.com/programmable-logic/gatemate/
+# https://colognechip.com/docs/ds1001-gatemate1-datasheet-latest.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME gatemate
+}
+
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x20000001
+
+pld create $_CHIPNAME.pld gatemate -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/gowin_gw1n.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/gowin_gw1n.cfg
new file mode 100644
index 0000000..5e85066
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/gowin_gw1n.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Gowin FPGA IDCODEs
+# from JTAG Programming and Configuration Guide
+# http://cdn.gowinsemi.com.cn/TN653E.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME gw1n
+}
+
+jtag newtap $_CHIPNAME tap -irlen 8 -ignore-version \
+	-expected-id 0x0900281B \
+	-expected-id 0x0900381B \
+	-expected-id 0x0100681B \
+	-expected-id 0x0300081B \
+	-expected-id 0x0300181B \
+	-expected-id 0x0120681B \
+	-expected-id 0x0100381B \
+	-expected-id 0x1100381B \
+	-expected-id 0x0100981B \
+	-expected-id 0x1100581B \
+	-expected-id 0x1100481B \
+	-expected-id 0x0100181B \
+	-expected-id 0x1100181B \
+	-expected-id 0x0100481B
+
+pld create $_CHIPNAME.pld gowin -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_certus.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_certus.cfg
new file mode 100644
index 0000000..9ddb7d8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_certus.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME certus
+}
+
+# Lattice Certus
+#
+# Certus NX LFD2NX-17     0x310f0043
+# Certus NX LFD2NX-40     0x310f1043
+
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+	-expected-id 0x310F1043 -expected-id 0x310F0043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_certuspro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_certuspro.cfg
new file mode 100644
index 0000000..acaaa57
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_certuspro.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME certuspro
+}
+
+# Lattice CertusPro
+#
+# 0x010f4043 - LFCPNX-100
+# 0x     043 - LFCPNX-50
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+	-expected-id 0x010f4043
+#    -expected-id 0x01112043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_ecp2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_ecp2.cfg
new file mode 100644
index 0000000..5b01787
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_ecp2.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ecp2
+}
+
+# Lattice ECP2 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP2M
+#
+# LFE2M20E: 0x01279043
+# LFE2M35E: 0x0127A043
+# LFE2M50E: 0x0127B043
+# LFE2M70E: 0x0127C043
+# LFE2M100E: 0x0127D043
+# LFEC2_6E: 0x01270043
+# LFEC2_12E: 0x01271043
+# LFEC2_20E: 0x01272043
+# LFEC2_35E: 0x01274043
+# LFEC2_50E: 0x01273043
+# LFEC2_70E: 0x01275043
+
+jtag newtap $_CHIPNAME tap -irlen 8  \
+	-expected-id 0x01279043 -expected-id 0x0127A043 -expected-id 0x0127B043 \
+	-expected-id 0x0127C043 -expected-id 0x0127D043 -expected-id 0x01270043 \
+	-expected-id 0x01271043 -expected-id 0x01272043 -expected-id 0x01274043 \
+	-expected-id 0x01273043 -expected-id 0x01275043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_ecp3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_ecp3.cfg
new file mode 100644
index 0000000..21c8ffa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_ecp3.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ecp3
+}
+
+# Lattice ECP3 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP3
+#
+# LFE3_17:  0x01010043
+# LFE3_35:  0x01012043
+# LFE3_95:  0x01014043 and LFE3_70
+# LFE3_150: 0x01015043
+
+jtag newtap $_CHIPNAME tap -irlen 8  \
+	-expected-id 0x01010043 -expected-id 0x01012043 \
+	-expected-id 0x01014043 -expected-id 0x01015043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_ecp5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_ecp5.cfg
new file mode 100644
index 0000000..cdc63f0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_ecp5.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ecp5
+}
+
+# Lattice ECP5 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/ECP5
+#
+# 0x01111043 - LAE5UM_25F/LFE5UM_25F
+# 0x01112043 - LAE5UM_45F/LFE5UM_45F
+# 0x01113043 - LAE5UM_85F/LFE5UM_85
+# 0x21111043 - LFE5U_12F
+# 0x41111043 - LFE5U_25F
+# 0x41112043 - LFE5U_45F
+# 0x41113043 - LFE5U_85F
+# 0x81111043 - LFE5UM5G-25
+# 0x81112043 - LFE5UM5G-45
+# 0x81113043 - LFE5UM5G-85
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+	-expected-id 0x01111043 -expected-id 0x01112043 -expected-id 0x01113043 \
+	-expected-id 0x21111043 -expected-id 0x41111043 -expected-id 0x41112043 \
+	-expected-id 0x41113043 -expected-id 0x81111043 -expected-id 0x81112043 \
+	-expected-id 0x81113043
+
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_machxo3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_machxo3.cfg
new file mode 100644
index 0000000..37fa054
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/lattice_machxo3.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME machxo3
+}
+
+# Lattice MachXO3 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/MachXO3
+#
+# 0x412b2043 - LCMXO3L_1300E_XXUWG36/XXMG121
+# 0x412b3043 - LCMXO3L_2100E_XXMG121/XXMG256/XXUWG49
+# 0x412b4043 - LCMXO3L_4300E_XXMG121/XXMG324/XXUWG81
+# 0x412b5043 - LCMXO3L_6900E_XXMG256/XXMG324
+# 0x412b6043 - LCMXO3L_9400E_XXBG256/XXMG256
+# 0x412bb043 - LCMXO3L_2100C_XXBG256
+# 0x412bc043 - LCMXO3L_4300C_XXBG256/XXBG324
+# 0x412bd043 - LCMXO3L_6900C_XXBG256/XXBG324/XXBG400
+# 0x412be043 - LCMXO3L_9400C_XXBG256/XXBG400/XXBG484
+# 0x612b2043 - LCMXO3LF_1300E_XXMG121/XXUWG36
+# 0x612b3043 - LCMXO3LF_2100E_XXMG121/XXMG256/XXUWG49
+# 0x612b4043 - LCMXO3LF_4300E_XXMG121/XXMG256/XXMG324/XXUWG81
+# 0x612b5043 - LCMXO3LF_6900E_XXMG256/XXMG324
+# 0x612b6043 - LCMXO3LF_9400E_XXBG256/XXMG256
+# 0x612bb043 - LCMXO3LF_2100C_XXBG256
+# 0x612bc043 - LCMXO3LF_4300C_XXBG256/XXBG324
+# 0x612bd043 - LCMXO3LF_6900C_XXBG256/XXBG324/XXBG400
+# 0x612be043 - LCMXO3LF_9400C_XXBG256/XXBG400/XXBG484
+# 0xc12b2043 - LCMXO3L_640E_XXMG121
+# 0xc12b4043 - LCMXO3L_2100E_XXMG324
+# 0xc12bb043 - LCMXO3L_1300C_XXBG256/XXMG256
+# 0xc12bc043 - LCMXO3L_2100C_XXBG324
+# 0xc12bd043 - LCMXO3L_4300C_XXBG400
+# 0xe12b2043 - LCMXO3LF_640E_XXMG121
+# 0xe12b3043 - LCMXO3LF_1300E_XXMG256
+# 0xe12b4043 - LCMXO3LF_2100E_XXMG324
+# 0xe12bb043 - LCMXO3LF_1300C_XXBG256
+# 0xe12bc043 - LCMXO3LF_2100C_XXBG324
+# 0xe12bd043 - LCMXO3LF_4300C_XXBG400
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+	-expected-id 0x412b2043 -expected-id 0x412b3043 -expected-id 0x412b4043 \
+	-expected-id 0x412b5043 -expected-id 0x412b6043 -expected-id 0x412bb043 \
+	-expected-id 0x412bc043 -expected-id 0x412bd043 -expected-id 0x412be043 \
+	-expected-id 0x612b2043 -expected-id 0x612b3043 -expected-id 0x612b4043 \
+	-expected-id 0x612b5043 -expected-id 0x612b6043 -expected-id 0x612bb043 \
+	-expected-id 0x612bc043 -expected-id 0x612bd043 -expected-id 0x612be043 \
+	-expected-id 0xc12b2043 -expected-id 0xc12b4043 -expected-id 0xc12bb043 \
+	-expected-id 0xc12bc043 -expected-id 0xc12bd043 -expected-id 0xe12b2043 \
+	-expected-id 0xe12b3043 -expected-id 0xe12b4043 -expected-id 0xe12bb043 \
+	-expected-id 0xe12bc043 -expected-id 0xe12bd043
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/xilinx-dna.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/xilinx-dna.cfg
new file mode 100644
index 0000000..6b16b78
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/xilinx-dna.cfg
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Spartan3: Table 9-5 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
+proc xilinx_dna_addr {chip} {
+	array set addrs {
+		Spartan3 0x31
+		Spartan6 0x30
+		Series7 0x17
+	}
+	return $addrs($chip)
+}
+
+# Get the "Device DNA".
+# Most Xilinx FPGA devices contain an embedded, unique device identifier.
+# The identifier is nonvolatile, permanently programmed into
+# the FPGA, and is unchangeable providing a great serial / tracking number.
+# This function returns the DNA as a 64 bit integer with the 7 LSBs zeroed.
+# This is compatible with the FUSE DNA which contains all 64 bits.
+proc xilinx_get_dna {tap chip} {
+	set XC7_ISC_ENABLE 0x10
+	set XC7_ISC_DISABLE 0x16
+	set XC7_ISC_DNA [xilinx_dna_addr $chip]
+
+	irscan $tap $XC7_ISC_ENABLE
+	runtest 64
+	irscan $tap $XC7_ISC_DNA
+	scan [drscan $tap 32 0 32 0] "%08x %08x" hi lo
+	runtest 64
+	irscan $tap $XC7_ISC_DISABLE
+	runtest 64
+	# openocd interprets DR scans as LSB first, bit-reverse it
+	return [scan [string reverse [format "%032b%032bb0" $lo $hi]] "%i"]
+}
+
+# Print out the "Device DNA" in the same format that impact uses.
+proc xilinx_print_dna {dna} {
+	set dna [expr {$dna >> 64 - 57}]
+	echo [format "DNA = %057b (0x%016x)" $dna $dna]
+}
+
+proc xc7_get_dna {tap} {
+	return [xilinx_get_dna $tap Series7]
+}
+
+proc xc6s_get_dna {tap} {
+	return [xilinx_get_dna $tap Spartan6]
+}
+
+proc xc3s_get_dna {tap} {
+	return [xilinx_get_dna $tap Spartan3]
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/xilinx-xadc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/xilinx-xadc.cfg
new file mode 100644
index 0000000..fdaf3a9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/xilinx-xadc.cfg
@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx XADC support for 7 Series FPGAs
+#
+# The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
+# temperature, internal power supply rail voltages as well as external
+# voltages. The XADC is available both from fabric as well as through the
+# JTAG TAP.
+#
+# This code implements access through the JTAG TAP.
+#
+# https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
+
+# build a 32 bit DRP command for the XADC DR
+proc xadc_cmd {cmd addr data} {
+	array set cmds {
+		NOP 0x00
+		READ 0x01
+		WRITE 0x02
+	}
+	return [expr {($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)}]
+}
+
+# XADC register addresses
+# Some addresses (status registers 0-3) have special function when written to.
+proc XADC {key} {
+	array set addrs {
+		TEMP 0x00
+		LOCK 0x00
+		VCCINT 0x01
+		VCCAUX 0x02
+		VAUXEN 0x02
+		VPVN 0x03
+		RESET 0x03
+		VREFP 0x04
+		VREFN 0x05
+		VCCBRAM 0x06
+		SUPAOFFS 0x08
+		ADCAOFFS 0x09
+		ADCAGAIN 0x0a
+		VCCPINT 0x0d
+		VCCPAUX 0x0e
+		VCCODDR 0x0f
+		VAUX0 0x10
+		VAUX1 0x11
+		VAUX2 0x12
+		VAUX3 0x13
+		VAUX4 0x14
+		VAUX5 0x15
+		VAUX6 0x16
+		VAUX7 0x17
+		VAUX8 0x18
+		VAUX9 0x19
+		VAUX10 0x1a
+		VAUX11 0x1b
+		VAUX12 0x1c
+		VAUX13 0x1d
+		VAUX14 0x1e
+		VAUX15 0x1f
+		SUPBOFFS 0x30
+		ADCBOFFS 0x31
+		ADCBGAIN 0x32
+		FLAG 0x3f
+		CFG0 0x40
+		CFG1 0x41
+		CFG2 0x42
+		SEQ0 0x48
+		SEQ1 0x49
+		SEQ2 0x4a
+		SEQ3 0x4b
+		SEQ4 0x4c
+		SEQ5 0x4d
+		SEQ6 0x4e
+		SEQ7 0x4f
+		ALARM0 0x50
+		ALARM1 0x51
+		ALARM2 0x52
+		ALARM3 0x53
+		ALARM4 0x54
+		ALARM5 0x55
+		ALARM6 0x56
+		ALARM7 0x57
+		ALARM8 0x58
+		ALARM9 0x59
+		ALARM10 0x5a
+		ALARM11 0x5b
+		ALARM12 0x5c
+		ALARM13 0x5d
+		ALARM14 0x5e
+		ALARM15 0x5f
+	}
+	return $addrs($key)
+}
+
+# Select the XADC DR
+proc xadc_select {tap} {
+	set XADC_IR 0x37
+	irscan $tap $XADC_IR
+	runtest 10
+}
+
+# XADC transfer
+proc xadc_xfer {tap cmd addr data} {
+	set ret [drscan $tap 32 [xadc_cmd $cmd $addr $data]]
+	runtest 10
+	return [expr "0x$ret"]
+}
+
+# XADC register write
+proc xadc_write {tap addr data} {
+	xadc_xfer $tap WRITE $addr $data
+}
+
+# XADC register read, non-pipelined
+proc xadc_read {tap addr} {
+	xadc_xfer $tap READ $addr 0
+	return [xadc_xfer $tap NOP 0 0]
+}
+
+# convert 16 bit register code from ADC measurement on
+# external voltages (VAUX) to Volt
+proc xadc_volt {code} {
+	return [expr {$code * 1./(1 << 16)}]
+}
+
+# convert 16 bit temperature measurement to Celsius
+proc xadc_temp {code} {
+	return [expr {$code * 503.975/(1 << 16) - 273.15}]
+}
+
+# convert 16 bit suppply voltage measurement to Volt
+proc xadc_sup {code} {
+	return [expr {$code * 3./(1 << 16)}]
+}
+
+# perform a single channel measurement using default settings
+proc xadc_single {tap ch} {
+	set cfg0 [xadc_read $tap [XADC CFG0]]
+	set cfg1 [xadc_read $tap [XADC CFG1]]
+	# set channel
+	xadc_write $tap [XADC CFG0] $cfg0
+	# single channel, disable the sequencer
+	xadc_write $tap [XADC CFG1] 0x3000
+	# leave some time for the conversion
+	runtest 100
+	set ret [xadc_read $tap [XADC $ch]]
+	# restore CFG0/1
+	xadc_write $tap [XADC CFG0] $cfg0
+	xadc_write $tap [XADC CFG1] $cfg1
+	return $ret
+}
+
+# measure all internal voltages
+proc xadc_report {tap} {
+	xadc_select $tap
+	echo "TEMP [format %.2f [xadc_temp [xadc_single $tap TEMP]]] C"
+	foreach ch [list VCCINT VCCAUX VCCBRAM VPVN VREFP VREFN \
+		VCCPINT VCCPAUX VCCODDR] {
+		echo "$ch [format %.3f [xadc_sup [xadc_single $tap $ch]]] V"
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/xilinx-xc3s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/xilinx-xc3s.cfg
new file mode 100644
index 0000000..7c17206
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/fpga/xilinx-xc3s.cfg
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx Spartan3 generation
+# https://www.xilinx.com/support/documentation/user_guides/ug331.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc3s
+}
+
+# Table 12-4 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
+# the 4 top bits (28:31) are the die stepping, ignore them.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x02210093 \
+	-expected-id 0x02218093 \
+	-expected-id 0x02220093 \
+	-expected-id 0x02228093 \
+	-expected-id 0x02230093 \
+	-expected-id 0x02610093 \
+	-expected-id 0x02618093 \
+	-expected-id 0x02620093 \
+	-expected-id 0x02628093 \
+	-expected-id 0x02630093 \
+	-expected-id 0x03840093 \
+	-expected-id 0x0384E093 \
+	-expected-id 0x01C10093 \
+	-expected-id 0x01C1A093 \
+	-expected-id 0x01C22093 \
+	-expected-id 0x01C2E093 \
+	-expected-id 0x01C3A093 \
+	-expected-id 0x0140C093 \
+	-expected-id 0x01414093 \
+	-expected-id 0x0141C093 \
+	-expected-id 0x01428093 \
+	-expected-id 0x01434093 \
+	-expected-id 0x01440093 \
+	-expected-id 0x01448093 \
+	-expected-id 0x01450093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+
+source [find fpga/xilinx-dna.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/altera-usb-blaster.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/altera-usb-blaster.cfg
new file mode 100644
index 0000000..cc6057b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/altera-usb-blaster.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Altera USB-Blaster
+#
+# http://www.altera.com/literature/ug/ug_usb_blstr.pdf
+#
+
+adapter driver usb_blaster
+usb_blaster lowlevel_driver ftdi
+# These are already the defaults.
+# usb_blaster vid_pid 0x09FB 0x6001
+# usb_blaster device_desc "USB-Blaster"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/altera-usb-blaster2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/altera-usb-blaster2.cfg
new file mode 100644
index 0000000..93f9809
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/altera-usb-blaster2.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Altera USB-Blaster II
+#
+
+adapter driver usb_blaster
+usb_blaster vid_pid 0x09fb 0x6010 0x09fb 0x6810
+usb_blaster lowlevel_driver ublast2
+usb_blaster firmware /path/to/quartus/blaster_6810.hex
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/angie.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/angie.cfg
new file mode 100644
index 0000000..26cbe39
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/angie.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2023 by NanoXplore, France - all rights reserved
+#
+# configuration file for ANGIE Adapter from NanoXplore.
+#
+
+adapter driver angie
+adapter speed 10000
+reset_config trst_and_srst trst_push_pull srst_open_drain
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/arm-jtag-ew.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/arm-jtag-ew.cfg
new file mode 100644
index 0000000..a064a42
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/arm-jtag-ew.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-JTAG-EW
+#
+# http://www.olimex.com/dev/arm-jtag-ew.html
+#
+
+adapter driver arm-jtag-ew
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ast2600-gpiod.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ast2600-gpiod.cfg
new file mode 100644
index 0000000..5cad02f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ast2600-gpiod.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Use AST2600 GPIO through linuxgpiod
+#
+# +-----------+-------------+-------------+
+# | signal    | GPIO name   | gpio offset |
+# +-----------+-------------+-------------+
+# | TCK/SWCLK | GPIOI2      | 66          |
+# | TMS/SWDIO | GPIOI3      | 67          |
+# | TDI       | GPIOI1      | 65          |
+# | TDO       | GPIOI4      | 68          |
+# | nTRST     | GPIOI0      | 64          |
+# +-----------+-------------+-------------+
+
+adapter driver linuxgpiod
+
+adapter gpio trst 64 -chip 0
+adapter gpio tdi 65 -chip 0
+adapter gpio tck 66 -chip 0
+adapter gpio swclk 66 -chip 0
+adapter gpio tms 67 -chip 0
+adapter gpio swdio 67 -chip 0
+adapter gpio tdo 68 -chip 0
+
+reset_config trst_only separate trst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/at91rm9200.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/at91rm9200.cfg
new file mode 100644
index 0000000..caef997
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/at91rm9200.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Various Atmel AT91RM9200 boards
+#
+# TODO: URL?
+#
+
+adapter driver at91rm9200
+at91rm9200_device rea_ecr
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/beaglebone-jtag-native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/beaglebone-jtag-native.cfg
new file mode 100644
index 0000000..0240e5d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/beaglebone-jtag-native.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# BeagleBone native GPIO interface for JTAG
+#
+# This is best used with a fast buffer but it is also suitable for a direct
+# connection if the target voltage matches the host's IO voltage (typically
+# 3.3V) and the cable is short.
+#
+# DO NOT APPLY VOLTAGE TO THE GPIO PINS UNTIL SYS_RESETN IS HIGH.
+#
+# Do not forget the GND connection.
+
+adapter driver am335xgpio
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on the system clock, calibrated for stock 1 GHz BeagleBoneBlack
+# am335xgpio speed SPEED_COEFF SPEED_OFFSET
+am335xgpio speed_coeffs 600000 575
+
+# BeagleBone pin P9_41
+adapter gpio tdo 20 -chip 0
+
+# BeagleBone pin P9_12
+adapter gpio tdi 28 -chip 1
+
+# BeagleBone pin P9_18
+adapter gpio tms 4 -chip 0
+
+# BeagleBone pin P9_22
+adapter gpio tck 2 -chip 0
+
+# BeagleBone pin P9_16
+adapter gpio led 19 -chip 1
+
+# BeagleBone pin P8_18
+adapter gpio srst 1 -chip 2
+reset_config srst_only srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/beaglebone-swd-native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/beaglebone-swd-native.cfg
new file mode 100644
index 0000000..6c40849
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/beaglebone-swd-native.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# BeagleBone native GPIO interface for SWD
+#
+# This is best used with a fast buffer but it is also suitable for a direct
+# connection if the target voltage matches the host's IO voltage (typically
+# 3.3V) and the cable is short.
+#
+# DO NOT APPLY VOLTAGE TO THE GPIO PINS UNTIL SYS_RESETN IS HIGH.
+#
+# Do not forget the GND connection.
+
+adapter driver am335xgpio
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on the system clock, calibrated for stock 1 GHz BeagleBoneBlack
+# am335xgpio speed SPEED_COEFF SPEED_OFFSET
+am335xgpio speed_coeffs 600000 575
+
+# BeagleBone pin P9_22
+adapter gpio swclk 2 -chip 0
+
+# BeagleBone pin P9_18
+adapter gpio swdio 4 -chip 0
+
+# BeagleBone pin P9_12
+adapter gpio swdio_dir 28 -chip 1
+
+# USR0 LED
+adapter gpio led 21 -chip 1
+
+# BeagleBone pin P8_18
+adapter gpio srst 1 -chip 2
+reset_config srst_only srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/buspirate.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/buspirate.cfg
new file mode 100644
index 0000000..8f613a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/buspirate.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Buspirate with OpenOCD support
+#
+# http://dangerousprototypes.com/bus-pirate-manual/
+#
+
+adapter driver buspirate
+
+# you need to specify port on which BP lives
+#buspirate port /dev/ttyUSB0
+
+# communication speed setting
+buspirate speed normal ;# or fast
+
+# voltage regulator Enabled = 1 Disabled = 0
+#buspirate vreg 0
+
+# pin mode normal or open-drain (jtag only)
+#buspirate mode normal
+
+# pullup state Enabled = 1 Disabled = 0
+#buspirate pullup 0
+
+# this depends on the cable, you are safe with this option
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/chameleon.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/chameleon.cfg
new file mode 100644
index 0000000..b73d129
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/chameleon.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Amontec Chameleon POD
+#
+# http://www.amontec.com/chameleon.shtml
+#
+
+adapter driver parport
+parport cable chameleon
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/cmsis-dap.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/cmsis-dap.cfg
new file mode 100644
index 0000000..15efe80
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/cmsis-dap.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# ARM CMSIS-DAP compliant adapter
+#
+# http://www.keil.com/support/man/docs/dapdebug/
+#
+
+adapter driver cmsis-dap
+
+# Optionally specify the serial number of CMSIS-DAP usb device.
+# adapter serial 02200201E6661E601B98E3B9
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/dln-2-gpiod.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/dln-2-gpiod.cfg
new file mode 100644
index 0000000..c9e3388
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/dln-2-gpiod.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Use DLN-2 GPIO through linuxgpiod
+#
+# +-----------+-------------+-------------+
+# | signal    | DLN-2       | gpio offset |
+# +-----------+-------------+-------------+
+# | nSRST     | J3.1  (PA0) | 0           |
+# | TDO       | J3.2  (PA1) | 1           |
+# | TCK/SWCLK | J3.3  (PA2) | 2           |
+# | TMS/SWDIO | J3.4  (PA3) | 3           |
+# | TDI       | J3.5  (PA4) | 4           |
+# | nTRST     | J3.6  (PA5) | 5           |
+# | LED       | J3.7  (PA6) | 6           |
+# | GND       | J3.12 (GND) |             |
+# +-----------+-------------+-------------+
+
+adapter driver linuxgpiod
+
+adapter gpio srst 0 -chip 0
+adapter gpio tdo 1 -chip 0
+adapter gpio tck 2 -chip 0
+adapter gpio swclk 2 -chip 0
+adapter gpio tms 3 -chip 0
+adapter gpio swdio 3 -chip 0
+adapter gpio tdi 4 -chip 0
+adapter gpio trst 5 -chip 0
+adapter gpio led 6 -chip 0
+
+reset_config trst_and_srst separate srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/dummy.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/dummy.cfg
new file mode 100644
index 0000000..34e6558
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/dummy.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Dummy interface (for testing purposes)
+#
+
+adapter driver dummy
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/esp_usb_bridge.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/esp_usb_bridge.cfg
new file mode 100644
index 0000000..9342239
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/esp_usb_bridge.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# ESP USB Bridge jtag adapter
+#
+
+adapter driver esp_usb_jtag
+
+espusbjtag vid_pid 0x303a 0x1002
+espusbjtag caps_descriptor 0x030A  # string descriptor index:10
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/esp_usb_jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/esp_usb_jtag.cfg
new file mode 100644
index 0000000..40427d0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/esp_usb_jtag.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Espressif builtin USB-JTAG adapter
+#
+
+adapter driver esp_usb_jtag
+
+espusbjtag vid_pid 0x303a 0x1001
+espusbjtag caps_descriptor 0x2000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/estick.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/estick.cfg
new file mode 100644
index 0000000..1daaf7c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/estick.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# eStick
+#
+# http://code.google.com/p/estick-jtag/
+#
+
+adapter driver opendous
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/flashlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/flashlink.cfg
new file mode 100644
index 0000000..d552c50
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/flashlink.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# ST FlashLINK JTAG parallel cable
+#
+# http://www.st.com/internet/evalboard/product/94023.jsp
+# http://www.st.com/stonline/products/literature/um/7889.pdf
+#
+
+if { [info exists PARPORTADDR] } {
+   set _PARPORTADDR $PARPORTADDR
+} else {
+   set _PARPORTADDR 0
+}
+
+adapter driver parport
+parport port $_PARPORTADDR
+parport cable flashlink
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ft232r.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ft232r.cfg
new file mode 100644
index 0000000..94eed02
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ft232r.cfg
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter driver ft232r
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ft232r/radiona_ulx3s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ft232r/radiona_ulx3s.cfg
new file mode 100644
index 0000000..3fc3d71
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ft232r/radiona_ulx3s.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# This adapter is integrated in to Radiona ULX3S board:
+# 	board/radiona_ulx3s.cfg
+# See schematics for the ft232r layout:
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf
+
+adapter driver ft232r
+adapter speed 1000
+ft232r vid_pid 0x0403 0x6015
+ft232r tck_num DSR
+ft232r tms_num DCD
+ft232r tdi_num RI
+ft232r tdo_num CTS
+ft232r trst_num RTS
+ft232r srst_num DTR
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/100ask-openjtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/100ask-openjtag.cfg
new file mode 100644
index 0000000..5ab9252
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/100ask-openjtag.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# www.100ask.org OpenJTAG
+#
+# http://www.100ask.net/OpenJTAG.html
+#
+# Schematics are available from
+# https://blog.matthiasbock.net/wp-content/uploads/2015/04/100ask-JTAGv3.pdf
+#
+
+adapter driver ftdi
+ftdi device_desc "USB<=>JTAG&RS232"
+ftdi vid_pid 0x1457 0x5118
+
+ftdi layout_init 0x0f08 0x0f1b
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/arty-onboard-ftdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/arty-onboard-ftdi.cfg
new file mode 100644
index 0000000..0edc615
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/arty-onboard-ftdi.cfg
@@ -0,0 +1,7 @@
+interface ftdi
+# ftdi_device_desc "Arty On-board FTDI interface"
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+ftdi layout_init 0x0088 0x008b
+reset_config none
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg
new file mode 100644
index 0000000..6256aa0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Ashling Opella-LD
+#
+# https://www.ashling.com/Opella-LD/
+#
+
+adapter driver ftdi
+ftdi device_desc "Opella-LD Debug Probe"
+ftdi vid_pid 0x0B6B 0x0040
+ftdi tdo_sample_edge falling
+ftdi layout_init 0x0A68 0xFF7B
+ftdi channel 0
+ftdi layout_signal JTAGOE -ndata 0x0010
+ftdi layout_signal nTRST -data 0x0020
+ftdi layout_signal nSRST -data 0x0040
+ftdi layout_signal SWD_EN -data 0x0100
+ftdi layout_signal SWDIO_OE -data 0x0200
+ftdi layout_signal LED -ndata 0x0800
+transport select jtag
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ashling-opella-ld-swd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ashling-opella-ld-swd.cfg
new file mode 100644
index 0000000..4a4e4e0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ashling-opella-ld-swd.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Ashling Opella-LD
+#
+# https://www.ashling.com/Opella-LD/
+#
+
+adapter driver ftdi
+ftdi device_desc "Opella-LD Debug Probe"
+ftdi vid_pid 0x0B6B 0x0040
+ftdi layout_init 0x0860 0x0b7b
+ftdi channel 0
+ftdi layout_signal JTAGOE -data 0x0010
+ftdi layout_signal nTRST -data 0x0020
+ftdi layout_signal nSRST -data 0x0040
+ftdi layout_signal SWD_EN -data 0x0100
+ftdi layout_signal SWDIO_OE -data 0x0200
+ftdi layout_signal LED -ndata 0x0800
+transport select swd
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/axm0432.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/axm0432.cfg
new file mode 100644
index 0000000..5008399
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/axm0432.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Axiom axm0432
+#
+# http://www.axman.com
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Symphony SoundBite"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0c08 0x0c2b
+ftdi layout_signal nTRST -data 0x0800
+ftdi layout_signal nSRST -data 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/c232hm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/c232hm.cfg
new file mode 100644
index 0000000..23c8f3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/c232hm.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# FTDI USB Hi-Speed to MPSSE Cable
+#
+# http://www.ftdichip.com/Products/Cables/USBMPSSE.htm
+#
+# C232HM-DDHSL-0 and C232HM-EDSL-0 provide 3.3V and 5V on pin 1 (Red),
+# respectively.
+#
+# Adapter: http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_C232HM_MPSSE_CABLE.PDF
+# Chip: http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf
+# See pinout/colors at end of this file.
+#
+# Tech notes:
+# http://www.ftdichip.com/Support/Documents/AppNotes/AN_135_MPSSE_Basics.pdf
+# http://www.ftdichip.com/Support/Documents/AppNotes/AN_129_FTDI_Hi_Speed_USB_To_JTAG_Example.pdf
+
+adapter driver ftdi
+#ftdi device_desc "C232HM-DDHSL-0"
+#ftdi device_desc "C232HM-EDHSL-0"
+
+# Common PID for FT232H
+ftdi vid_pid 0x0403 0x6014
+
+# Layout
+# High data byte 0x40 configures red LED on ACBUS6 initially high (unlit, since active-low)
+# Low data byte 0x08 configures TMS on ACBUS3 initially high (asserted); TCK, TDI low
+# High direction byte 0x40 configures red LED on ACBUS6 as high (output)
+# Low direction byte 0x0b configures TDO on ACBUS2 as low (input)
+ftdi layout_init 0x4008 0x400b
+
+# ---A*BUS-------CCCCCCCC|DDDDDDDD
+# --------\______76543210|76543210
+# LED	0x4000 = 01000000|00000000 = ACBUS6
+#GPIOL0	0x0010 = 00000000|00010000 = ADBUS4
+#GPIOL1	0x0020 = 00000000|00100000 = ADBUS5
+#GPIOL2	0x0040 = 00000000|01000000 = ADBUS6
+#GPIOL3	0x0080 = 00000000|10000000 = ADBUS7
+# -ndata treats the LED as active-low for expected behavior (toggle when transferring)
+ftdi layout_signal LED -ndata 0x4000
+# Available for aliasing as desired
+ftdi layout_signal GPIOL0 -data 0x0010 -oe 0x0010
+ftdi layout_signal GPIOL1 -data 0x0020 -oe 0x0020
+ftdi layout_signal GPIOL2 -data 0x0040 -oe 0x0040
+ftdi layout_signal GPIOL3 -data 0x0080 -oe 0x0080
+
+# C232HM		FT232H	JTAG/Other
+# Num	Color	Name	Func
+# 1		Red		VCC		Optionally, can power the board if it is not using its own power supply.
+# 2		Orange	ADBUS0	TCK
+# 3		Yellow  ADBUS1	TDI
+# 4		Green	ADBUS2	TDO
+# 5		Brown   ADBUS3	TMS
+# 6		Grey	ADBUS4	GPIOL0
+# 7		Purple	ADBUS5	GPIOL1
+# 8		White	ADBUS6	GPIOL2
+# 9		Blue	ADBUS7	GPIOL3
+# 10	Black	GND		Connect to ground
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/cortino.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/cortino.cfg
new file mode 100644
index 0000000..8bc8d6e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/cortino.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hitex Cortino
+#
+# http://www.hitex.com/index.php?id=cortino
+#
+
+adapter driver ftdi
+ftdi device_desc "Cortino"
+ftdi vid_pid 0x0640 0x0032
+
+ftdi layout_init 0x0108 0x010b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200 -oe 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent-hs1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent-hs1.cfg
new file mode 100644
index 0000000..6a632ed
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent-hs1.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# this supports JTAG-HS1 and JTAG-SMT1
+# (the later being the OEM on-board version)
+
+adapter driver ftdi
+ftdi device_desc "Digilent Adept USB Device"
+ftdi vid_pid 0x0403 0x6010
+# channel 1 does not have any functionality
+ftdi channel 0
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0088 0x008b
+reset_config none
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent-hs2-cjtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent-hs2-cjtag.cfg
new file mode 100644
index 0000000..3daf461
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent-hs2-cjtag.cfg
@@ -0,0 +1,17 @@
+adapter driver ftdi
+ftdi device_desc "Digilent Adept USB Device"
+ftdi vid_pid 0x0403 0x6014
+
+ftdi channel 0
+ftdi layout_init 0x60e8 0x60eb
+
+reset_config none
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -ndata 0x6000 -oe 0x6000
+
+ftdi layout_signal TMSC_EN -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent-hs2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent-hs2.cfg
new file mode 100644
index 0000000..89c9e4b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent-hs2.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# this supports JTAG-HS2 (and apparently Nexys4 as well)
+
+# ADBUS5 controls TMS tri-state buffer enable
+# ACBUS6=SEL_TMS controls mux to TMS output buffer: 0=TMS 1=TDI
+# ACBUS5=SEL_TDO controls mux to TDO input: 0=TDO 1=TMS
+
+adapter driver ftdi
+ftdi device_desc "Digilent Adept USB Device"
+ftdi vid_pid 0x0403 0x6014
+
+ftdi channel 0
+ftdi layout_init 0x00e8 0x60eb
+ftdi layout_signal SWD_EN -data 0x6000
+ftdi layout_signal SWDIO_OE -data 0x20
+
+reset_config none
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent_jtag_hs3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent_jtag_hs3.cfg
new file mode 100644
index 0000000..78a233f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent_jtag_hs3.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent JTAG-HS3
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6014
+ftdi device_desc "Digilent USB Device"
+
+# From Digilent support:
+# The SRST pin is [...] 0x20 and 0x10 is the /OE (active low output enable)
+
+ftdi layout_init 0x2088 0x308b
+ftdi layout_signal nSRST -data 0x2000 -noe 0x1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent_jtag_smt2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent_jtag_smt2.cfg
new file mode 100644
index 0000000..ac623a7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent_jtag_smt2.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent JTAG-SMT2
+#
+# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,1053&Prod=JTAG-SMT2
+#
+# Config is based on data from
+# http://electronix.ru/forum/index.php?showtopic=114633&view=findpost&p=1215497 and ZedBoard schematics
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6014
+
+ftdi layout_init 0x20e8 0x3feb
+ftdi layout_signal nSRST -data 0x2000
+ftdi layout_signal GPIO2 -data 0x2000
+ftdi layout_signal GPIO1 -data 0x0200
+ftdi layout_signal GPIO0 -data 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg
new file mode 100644
index 0000000..38236bc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Digilent JTAG-SMT2-NC
+#
+# http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/
+# https://reference.digilentinc.com/_media/jtag_smt2nc/jtag-smt2-nc_rm.pdf
+#
+# Based on reference sheet (above) and Xilinx KCU105 schematics
+# https://www.xilinx.com/products/boards-and-kits/kcu105.html#documentation
+#
+# Note that the digilent_jtag_smt2 layout does not work and hangs while
+# the ftdi device_desc from digilent_hs2 is wrong.
+
+adapter driver ftdi
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6014
+ftdi channel 0
+ftdi layout_init 0x00e8 0x60eb
+reset_config none
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/dlp-usb1232h.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/dlp-usb1232h.cfg
new file mode 100644
index 0000000..67fee6b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/dlp-usb1232h.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# DLP Design DLP-USB1232H USB-to-UART/FIFO interface module
+#
+# http://www.dlpdesign.com/usb/usb1232h.shtml
+#
+# Schematics for OpenOCD usage:
+# http://randomprojects.org/wiki/DLP-USB1232H_and_OpenOCD_based_JTAG_adapter
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on schematics and code"
+echo "in ft2232.c. Please report your experience with this file to openocd-devel"
+echo "mailing list, so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/dp_busblaster.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/dp_busblaster.cfg
new file mode 100644
index 0000000..373e122
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/dp_busblaster.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Dangerous Prototypes - Bus Blaster
+#
+# The Bus Blaster has a configurable buffer between the FTDI FT2232H and the
+# JTAG header which allows it to emulate various debugger types. It comes
+# configured as a JTAGkey device.
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+
+echo "Info : If you need SWD support, flash KT-Link buffer from https://github.com/bharrisau/busblaster
+and use dp_busblaster_kt-link.cfg instead"
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/dp_busblaster_kt-link.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/dp_busblaster_kt-link.cfg
new file mode 100644
index 0000000..222ca38
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/dp_busblaster_kt-link.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Dangerous Prototypes - Bus Blaster (with KT-Link buffer)
+#
+# The Bus Blaster has a configurable buffer between the FTDI FT2232H
+# and the JTAG header which allows it to emulate various debugger
+# types. This config works with KT-Link compatible implementation from
+# https://github.com/bharrisau/busblaster and is SWD-enabled.
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x8c28 0xff3b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+ftdi layout_signal LED -ndata 0x8000
+ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000
+ftdi layout_signal SWDIO_OE -ndata 0x1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/esp32_devkitj_v1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/esp32_devkitj_v1.cfg
new file mode 100644
index 0000000..1b455a9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/esp32_devkitj_v1.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Driver for the FT2232H JTAG chip on the Espressif DevkitJ board
+# (and most other FT2232H and FT232H based boards)
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010 0x0403 0x6014
+
+# interface 1 is the uart
+ftdi channel 0
+
+# TCK, TDI, TDO, TMS: ADBUS0-3
+# LEDs: ACBUS4-7
+
+ftdi layout_init 0x0008 0xf00b
+ftdi layout_signal LED -data 0x1000
+ftdi layout_signal LED2 -data 0x2000
+ftdi layout_signal LED3 -data 0x4000
+ftdi layout_signal LED4 -data 0x8000
+
+# ESP32 series chips do not have a TRST input, and the SRST line is connected to the EN pin.
+# The target code doesn't handle SRST reset properly yet, so this is commented out:
+# ftdi layout_signal nSRST -oe 0x0020
+# reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg
new file mode 100644
index 0000000..1880bcb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Driver for the FT2232H JTAG chip on the Espressif Kaluga-1 ESP32-S2 board
+# (and most other FT2232H and FT232H based boards)
+#
+# JTAG DIP switch (labelled SW5 in the schematic) should be "ON" for lines
+# labelled TCK, TDO, TDI and TWS, to connect the FT2232H to the ESP32-S2.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010 0x0403 0x6014
+
+# interface 1 is the uart
+ftdi channel 0
+
+# TCK, TDI, TDO, TMS: ADBUS0-3
+# TRST/SRST: ADBUS5 (unused for now)
+# LEDs: ACBUS3-4 (inverted)
+
+ftdi layout_init 0x0008 0x180b
+ftdi layout_signal LED -ndata 0x0800
+ftdi layout_signal LED2 -ndata 0x1000
+
+# ESP32* series chips do not have a TRST input, and the SRST line is connected
+# to the EN pin.
+# The target code doesn't handle SRST reset properly yet, so this is
+# commented out:
+# ftdi layout_signal nSRST -oe 0x0020
+# reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flossjtag-noeeprom.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flossjtag-noeeprom.cfg
new file mode 100644
index 0000000..1008e1a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flossjtag-noeeprom.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# FlossJTAG
+#
+# http://github.com/esden/floss-jtag
+#
+# This is the pre v0.3 Floss-JTAG compatible config file. It can also be used
+# for newer versions of Floss-JTAG with empty or not populated EEPROM. If you
+# have several Floss-JTAG connected you have to use the USB ID to select a
+# specific one.
+#
+# If you have a Floss-JTAG WITH EEPROM that is programmed, use the
+# flossjtag.cfg file.
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flossjtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flossjtag.cfg
new file mode 100644
index 0000000..90ba63a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flossjtag.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# FlossJTAG
+#
+# http://github.com/esden/floss-jtag
+#
+# This is the v0.3 and v1.0 Floss-JTAG compatible config file. It relies on the
+# existence of an EEPROM on Floss-JTAG containing a name. If you have several
+# Floss-JTAG adapters connected you can use the serial number to select a
+# specific device.
+#
+# If your Floss-JTAG does not have an EEPROM, or the EEPROM is empty, use the
+# flossjtag-noeeprom.cfg file.
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+ftdi device_desc "FLOSS-JTAG"
+# adapter serial "FJ000001"
+
+ftdi layout_init 0x0008 0x180b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
+ftdi layout_signal LED -data 0x0800
+ftdi layout_signal LED2 -data 0x1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flyswatter.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flyswatter.cfg
new file mode 100644
index 0000000..8bce00d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flyswatter.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TinCanTools Flyswatter
+#
+# http://web.archive.org/web/20150419072034/http://www.tincantools.com/JTAG/Flyswatter.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Flyswatter"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0818 0x0cfb
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -oe 0x0020
+ftdi layout_signal LED -data 0x0c00
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flyswatter2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flyswatter2.cfg
new file mode 100644
index 0000000..ebc00fe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/flyswatter2.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TinCanTools Flyswatter2
+#
+# https://www.tincantools.com/product/flyswatter2/
+#
+
+adapter driver ftdi
+ftdi device_desc "Flyswatter2"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0538 0x057b
+ftdi layout_signal LED -ndata 0x0400
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -data 0x0020 -noe 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ft232h-module-swd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ft232h-module-swd.cfg
new file mode 100644
index 0000000..d09ccf1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ft232h-module-swd.cfg
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# ADAFRUIT FTDI FT232H as a SWD direct connect interface
+# Any FT232H based board may work
+#
+# http://www.ftdichip.com/Products/ICs/FT232H.htm
+#
+#
+
+adapter driver ftdi
+
+ftdi vid_pid 0x0403 0x6014
+
+# data MSB..LSB       direction (1:out) MSB..LSB
+# 0000'0000'0011'0000 0000'0000'0011'1011
+ftdi layout_init 0x0030 0x003b
+# 0xfff8 0xfffb
+# Those signal are only required on some platforms or may required to be
+# enabled explicitly (e.g. nrf5x chips).
+ftdi layout_signal nSRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nTRST -data 0x0020 -oe 0x0020
+
+# swd enable
+ftdi layout_signal SWD_EN -data 0
+# tri-state (configure as input) TDO/TIO when reading
+ftdi layout_signal SWDIO_OE -data 0
+
+transport select swd
+
+# re-configure TDO as tri-state
+#ftdi layout_signal TDO -data 0x0002 -oe 0x0002
+#ftdi layout_signal TDI -data 0x0004
+
+# Adafruit      FT232H    JTAG       SWD
+# Name  Pin     Name      Func       Func
+#  D0   J1-3    ADBUS0    TCK        SWDCLK
+#  D1   J1-4    ADBUS1    TDO/DI     SWDIO
+#  D2   J1-5    ADBUS2    TDI/DO     SWDIO
+#  D3   J1-6    ADBUS3    TMS        N/A
+#  D4   J1-7    ADBUS4    (GPIOL0)   /nSRST  optional module reset
+#  D5   J1-8    ADBUS5    (GPIOL1)   /nTRST  optional target reset
+#  D6   J1-9    ADBUS6    (GPIOL2)
+#  D7   J1-10   ADBUS7    (GPIOL3)
+#  C0   J2-1    ACBUS0    (GPIOH0)
+#  C1   J2-2    ACBUS1    (GPIOH1)
+#  C2   J2-3    ACBUS2    (GPIOH2)
+#  C3   J2-4    ACBUS3    (GPIOH3)
+#  C4   J2-5    ACBUS4    (GPIOH4)
+#  C5   J2-6    ACBUS5    (GPIOH5)
+#  C6   J2-7    ACBUS6    (GPIOH6)
+#  C7   J2-8    ACBUS7    (GPIOH7)
+#  C8   J2-9    ACBUS8
+#  C9   J2-10   ACBUS9
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/gw16042.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/gw16042.cfg
new file mode 100644
index 0000000..326a88f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/gw16042.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Gateworks GW16042 JTAG Dongle
+#
+# http://www.gateworks.com/
+#
+# Layout:  FTDI FT2232H
+#   ADBUS0 TCK
+#   ADBUS1 TDI
+#   ADBUS2 TDO (input)
+#   ADBUS3 TMS
+#   ADBUS4 nTRST
+#   ADBUS5 nSRST
+#   ADBUS6 OE (active high) for TRST, TDI, TMS, TCK
+#   ADBUS7 NC
+#   ACBUS0-7 NC
+#   BDBUS0 RXD
+#   BDBUS1 TXD (input)
+#
+
+adapter driver ftdi
+ftdi device_desc "USB-JTAG"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0058 0x007b
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hie-jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hie-jtag.cfg
new file mode 100644
index 0000000..6694df0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hie-jtag.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Hofstädtler Industrie-Electronic (HIE) JTAG Debugger
+#
+# https://www.hofstaedtler.com/jtag
+#
+
+adapter driver ftdi
+ftdi channel 0
+ftdi vid_pid 0x0403 0x6014
+ftdi device_desc "HIE JTAG Debugger"
+
+ftdi layout_init 0x0c08 0x4f1b
+
+# define both Reset signals
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+
+# Toggle USB LED
+ftdi layout_signal LED -ndata 0x4000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg
new file mode 100644
index 0000000..d5d24e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 10-ETM
+#
+# http://de.hilscher.com/products_details_hardware.html?p_id=P_4ce145a5983e6
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX 10-ETM"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg
new file mode 100644
index 0000000..003b9df
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 500-ETM
+#
+# http://de.hilscher.com/files_design/8/NXHX500-ETM_description_Rev01_EN.pdf
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX 500-ETM"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx500_re.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx500_re.cfg
new file mode 100644
index 0000000..97ad380
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx500_re.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 500-RE
+#
+# http://de.hilscher.com/products_details_hardware.html?p_id=P_461ff2053bad1&bs=20
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX 500-RE"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg
new file mode 100644
index 0000000..06280c1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 50-ETM
+#
+# http://de.hilscher.com/files_design/8/NXHX50-ETM_description_Rev01_EN.pdf
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX 50-ETM"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx50_re.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx50_re.cfg
new file mode 100644
index 0000000..f14be62
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hilscher_nxhx50_re.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hilscher NXHX 50-RE
+#
+# http://de.hilscher.com/products_details_hardware.html?p_id=P_483c0f582ad36&bs=20
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NXHX50-RE"
+ftdi vid_pid 0x0640 0x0028
+
+ftdi layout_init 0x0308 0x030b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hitex_lpc1768stick.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hitex_lpc1768stick.cfg
new file mode 100644
index 0000000..91bd5a8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hitex_lpc1768stick.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hitex LPC1768-Stick
+#
+# http://www.hitex.com/?id=1602
+#
+
+
+adapter driver ftdi
+ftdi device_desc "LPC1768-Stick"
+ftdi vid_pid 0x0640 0x0026
+
+ftdi layout_init 0x0388 0x038b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0080 -noe 0x200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hitex_str9-comstick.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hitex_str9-comstick.cfg
new file mode 100644
index 0000000..f698677
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/hitex_str9-comstick.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hitex STR9-comStick
+#
+# http://www.hitex.com/index.php?id=383
+#
+
+adapter driver ftdi
+ftdi device_desc "STR9-comStick"
+ftdi vid_pid 0x0640 0x002c
+
+ftdi layout_init 0x0108 0x010b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0200 -oe 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/icebear.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/icebear.cfg
new file mode 100644
index 0000000..4a76399
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/icebear.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Section5 ICEBear
+#
+# http://section5.ch/icebear
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "ICEbear JTAG adapter"
+ftdi vid_pid 0x0403 0xc140
+
+ftdi layout_init 0x0028 0x002b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/imx8mp-evk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/imx8mp-evk.cfg
new file mode 100644
index 0000000..02564dc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/imx8mp-evk.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration file for NXP MC-IMX8MP-EVK on-board internal JTAG
+#
+# Using this interface requires enabling "remote mode" for the board using the
+# NXP bcu tool (see https://github.com/NXPmicro/bcu)
+#
+#	bcu set_gpio remote_en 1 -board=imx8mpevk
+#
+# The REMOTE_EN gpio is accessible through the same FTDI adapter but it's
+# behind an I2C GPIO expander.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6011
+ftdi channel 0
+
+ftdi layout_init 0x00f8 0x000b
+
+ftdi layout_signal RESET_B	-data 0x0010 -oe 0x0010
+# Called SYS_nRST in schematics
+ftdi layout_signal nSRST	-data 0x0020 -oe 0x0020
+ftdi layout_signal IO_nRST	-data 0x0040 -oe 0x0040
+ftdi layout_signal ONOFF_B	-data 0x0080 -oe 0x0080
+
+ftdi layout_signal GPIO1	-data 0x0100 -oe 0x0100
+ftdi layout_signal GPIO2	-data 0x0200 -oe 0x0200
+ftdi layout_signal GPIO3	-data 0x0400 -oe 0x0400
+ftdi layout_signal GPIO4	-data 0x0800 -oe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/incircuit-icprog.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/incircuit-icprog.cfg
new file mode 100644
index 0000000..81f2872
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/incircuit-icprog.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# In-Circuit's ICprog OpenOCD JTAG Adapter
+# https://shop.in-circuit.de/product_info.php?products_id=112
+#
+# Schematics available at
+# http://wiki.in-circuit.de/images/0/06/610000158A_openocd.pdf
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nSRST -noe 0x0400 -data 0x0800
+ftdi layout_signal nTRST -noe 0x0100 -data 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/iotlab-usb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/iotlab-usb.cfg
new file mode 100644
index 0000000..b7a004e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/iotlab-usb.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is the integrated adapter as found on the IoT-LAB boards
+# https://github.com/iot-lab/iot-lab/wiki
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/isodebug.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/isodebug.cfg
new file mode 100644
index 0000000..0a6e080
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/isodebug.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# isodebug v1
+# 5 kV isolated JTAG/SWD + UART adapter by Unjo AB
+
+adapter driver ftdi
+ftdi vid_pid 0x22b7 0x150d
+
+ftdi layout_init 0x0ff8 0xfffb
+
+ftdi layout_signal LED -ndata 0x0100
+ftdi layout_signal nTRST -data 0x0200
+ftdi layout_signal nSRST -noe 0x0400
+ftdi layout_signal SWDIO_OE -data 0x0008
+
+# Mode signals, either of these needs to be high to drive the JTAG/SWD pins.
+# The power-on state is low for both signals but the init setting above sets
+# JTAG_EN high.
+ftdi layout_signal SWD_EN -data 0x1000
+ftdi layout_signal JTAG_EN -data 0x0800
+
+# In SWD mode, the JTAG_EN signal doubles as SWO_EN_N which switches the
+# second FTDI channel UART RxD to the SWO pin instead of the separate RxD
+# pin. Note that the default init state has this pin high so when OpenOCD
+# starts in SWD mode, SWO is by default disabled. To enable SWO tracing,
+# issue the command 'ftdi set_signal SWO_EN 1' where tracing is configured.
+# To switch back to using the separate UART, SWO_EN needs to be disabled
+# before exiting OpenOCD, or the adapter replugged.
+ftdi layout_signal SWO_EN -nalias JTAG_EN
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg
new file mode 100644
index 0000000..ea60dcf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# DISTORTEC JTAG-lock-pick Tiny 2
+#
+# http://www.distortec.com
+#
+
+adapter driver ftdi
+ftdi device_desc "JTAG-lock-pick Tiny 2"
+ftdi vid_pid 0x0403 0x8220
+
+ftdi layout_init 0x8c28 0xff3b
+ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+ftdi layout_signal SWDIO_OE -ndata 0x1000
+ftdi layout_signal LED -ndata 0x8000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtagkey.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtagkey.cfg
new file mode 100644
index 0000000..1c1c09d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtagkey.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Amontec JTAGkey
+#
+# http://www.amontec.com/jtagkey.shtml
+#
+
+adapter driver ftdi
+ftdi device_desc "Amontec JTAGkey"
+ftdi vid_pid 0x0403 0xcff8
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtagkey2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtagkey2.cfg
new file mode 100644
index 0000000..80df347
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtagkey2.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Amontec JTAGkey2
+#
+# http://www.amontec.com/jtagkey2.shtml
+#
+
+adapter driver ftdi
+ftdi device_desc "Amontec JTAGkey-2"
+ftdi vid_pid 0x0403 0xcff8
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtagkey2p.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtagkey2p.cfg
new file mode 100644
index 0000000..3a76bd0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/jtagkey2p.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Amontec JTAGkey2P
+#
+# http://www.amontec.com/jtagkey2p.shtml
+#
+
+adapter driver ftdi
+ftdi device_desc "Amontec JTAGkey-2P"
+ftdi vid_pid 0x0403 0xcff8
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/kt-link.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/kt-link.cfg
new file mode 100644
index 0000000..61c6b83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/kt-link.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Kristech KT-Link
+#
+# http://www.kristech.eu
+#
+
+adapter driver ftdi
+ftdi device_desc "KT-LINK"
+ftdi vid_pid 0x0403 0xbbe2
+
+ftdi layout_init 0x8c28 0xff3b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
+ftdi layout_signal LED -data 0x8000
+ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000
+ftdi layout_signal SWDIO_OE -ndata 0x1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg
new file mode 100644
index 0000000..df4955f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# This adapter is integrated in to LambdaConcept ECPIX-5 board:
+# 	interface/ftdi/lambdaconcept_ecpix-5.cfg
+# See schematics for the ftdi layout:
+# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF
+
+adapter driver ftdi
+adapter speed 10000
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0xfff8 0xfffb
+transport select jtag
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/lisa-l.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/lisa-l.cfg
new file mode 100644
index 0000000..75c5cbe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/lisa-l.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Lisa/L
+#
+# http://paparazzi.enac.fr/wiki/Lisa
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on schematics and code"
+echo "in ft2232.c. Please report your experience with this file to openocd-devel"
+echo "mailing list, so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Lisa/L"
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 1
+
+ftdi layout_init 0x0008 0x180b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0040 -oe 0x0040
+ftdi layout_signal LED -data 0x1800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/luminary-icdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/luminary-icdi.cfg
new file mode 100644
index 0000000..9142503
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/luminary-icdi.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Luminary Micro Stellaris LM3S9B9x Evaluation Kits
+# In-Circuit Debug Interface (ICDI) Board
+#
+# Essentially all Luminary debug hardware is the same, (with both
+# JTAG and SWD support compatible with ICDI boards.  This ICDI adapter
+# configuration is JTAG-only, but the same hardware handles SWD too.
+#
+# This is a discrete ftdi based debug board which supports ARM's
+# JTAG/SWD connectors in both backwards-compatible 20-pin format and
+# in the new-style compact 10-pin.  There's also an 8-pin connector
+# with serial port support.  It's included with LM3S9B9x eval boards.
+#
+# http://www.luminarymicro.com/products/ek-lm3s9b90.html
+# http://www.luminarymicro.com/products/ek-lm3s9b92.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Luminary Micro ICDI Board"
+ftdi vid_pid 0x0403 0xbcda
+
+ftdi layout_init 0x00a8 0x00eb
+ftdi layout_signal nSRST -noe 0x0020
+ftdi layout_signal SWD_EN -ndata 0x0080
+ftdi layout_signal SWDIO_OE -data 0x0008
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/luminary-lm3s811.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/luminary-lm3s811.cfg
new file mode 100644
index 0000000..98be166
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/luminary-lm3s811.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Luminary Micro Stellaris LM3S811 Evaluation Kit
+#
+# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html
+#
+# NOTE:  this is only for boards *before* Rev C, which adds support
+# for SWO tracing with ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN signals.
+# The "evb_lm3s811" layout doesn't set up those signals.
+#
+# Rev C boards work more like the other Stellaris eval boards.  They
+# need to use the "luminary_icdi" layout to work correctly.
+#
+
+adapter driver ftdi
+ftdi device_desc "LM3S811 Evaluation Board"
+ftdi vid_pid 0x0403 0xbcd9
+
+ftdi layout_init 0x0088 0x008b
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
+ftdi layout_signal SWD_EN -ndata 0x0080
+ftdi layout_signal SWDIO_OE -data 0x0008
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/luminary.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/luminary.cfg
new file mode 100644
index 0000000..27d9a9d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/luminary.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Luminary Micro Stellaris Evaluation Kits
+#
+# http://www.luminarymicro.com/products/evaluation_kits.html
+#
+# There are a number of evaluation kits for Stellaris Cortex-M3 chips.
+# Currently they all bundle ftdi based debug support.  When that is
+# used (instead of an external adapter), use this config file in one
+# of these two modes:
+#
+# - Eval board debug ... debug of the Stellaris chip via port A.
+#
+# - Other board debug ... same thing, but the board acts as a debug
+#   adapter for another board (using a standard ARM JTAG connector).
+#   The Stellaris chip stays in reset.
+#
+# Those support both JTAG and SWD.  SWD is an ARM-only two-wire debug
+# protocol; in 2009, OpenOCD does not support SWD.
+#
+# Port B of the ftdi chip is normally used as a serial link to the
+# Stellaris chip.  On most boards (but not older LM3S811 eval boards),
+# when SWD is used Port B may instead be used to read low-bandwidth
+# "SWO trace" data, including so-called "printf style" output from
+# firmware via the ITM module as well as profile data.
+#
+
+adapter driver ftdi
+ftdi device_desc "Stellaris Evaluation Board"
+ftdi vid_pid 0x0403 0xbcd9
+
+ftdi layout_init 0x00a8 0x00eb
+ftdi layout_signal nSRST -noe 0x0020
+ftdi layout_signal SWD_EN -ndata 0x0080
+ftdi layout_signal SWDIO_OE -data 0x0008
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/m53evk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/m53evk.cfg
new file mode 100644
index 0000000..2d9c304
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/m53evk.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# DENX M53EVK
+#
+# http://www.denx-cs.de/?q=M53EVK
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/mbftdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/mbftdi.cfg
new file mode 100644
index 0000000..09cec9f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/mbftdi.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# MBFTDI
+#
+# http://www.marsohod.org/prodmbftdi
+#
+# Also the Marsohod2 and the Marsohod3 boards
+# include a built-in MBFTDI for FPGA programming.
+# See http://www.marsohod.org/prodmarsohod2
+# and http://www.marsohod.org/plata-marsokhod3 for details.
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0008 0x000b
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/minimodule-swd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/minimodule-swd.cfg
new file mode 100644
index 0000000..3eb2f53
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/minimodule-swd.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Supports SWD using the FT2232H or FT4232H minimodule.
+# Each can support 2 SWD interfaces.
+#
+# FT2232H or FT4232H minimodule channel 0 (Channel A)
+# Connector  FTDI              Target
+# Pin        Name
+# ---------  ------            ------
+# CN2-11     VIO               VDD_IO (Or connect to CN2-5 on the minimodule instead for a 3V3 interface)
+# CN2-2      GND               GND
+# CN2-7      ADBUS0 (TCK)      SWCLK
+# CN2-9      ADBUS2 (TDI/TDO)  SWDIO
+# CN2-10     ADBUS1 (TDO/TDI)  SWDIO
+# CN2-14     ADBUS4 (GPIOL0)   nRESET
+#
+# FT2232H minimodule channel 1 (Channel B)
+# FTDI       Target
+# ----       ------
+# CN2-11  -  VDD_IO
+# CN2-2   -  GND
+# CN3-26  -  SWCLK
+# CN3-25  -  SWDIO
+# CN3-24  -  SWDIO
+# CN3-21  -  nRESET
+#
+# FT4232H minimodule channel 1 (Channel B)
+# FTDI       Target
+# ----       ------
+# CN2-11  -  VDD_IO
+# CN2-2   -  GND
+# CN2-18  -  SWCLK
+# CN2-17  -  SWDIO
+# CN2-20  -  SWDIO
+# CN2-22  -  nRESET
+#
+
+adapter driver ftdi
+
+#Select your module type and channel
+
+#ftdi device_desc "FT2232H MiniModule"
+ftdi vid_pid 0x0403 0x6010
+#ftdi channel 1
+
+#ftdi device_desc "FT4232H MiniModule"
+#ftdi vid_pid 0x0403 0x6011
+#ftdi channel 1
+
+ftdi layout_init 0x0000 0x000b
+ftdi layout_signal nSRST -data 0x0010 -oe 0x0010
+ftdi layout_signal SWD_EN -data 0
+ftdi layout_signal SWDIO_OE -data 0
+
+transport select swd
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/minimodule.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/minimodule.cfg
new file mode 100644
index 0000000..825d7c1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/minimodule.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# FTDI MiniModule
+#
+# http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf
+#
+
+adapter driver ftdi
+ftdi device_desc "FT2232H MiniModule"
+ftdi vid_pid 0x0403 0x6010
+
+# Every pin set as high impedance except TCK, TDI, TDO and TMS
+ftdi layout_init 0x0008 0x000b
+
+# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
+# This choice is arbitrary. Use other GPIO pin if desired.
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/minispartan6.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/minispartan6.cfg
new file mode 100644
index 0000000..f12bae6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/minispartan6.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# https://www.scarabhardware.com/minispartan6/
+# https://github.com/scarabhardware/miniSpartan6-plus/raw/master/miniSpartan6%2B_Rev_B.pdf
+adapter driver ftdi
+# The miniSpartan6+ sadly doesn't have a custom device description, so we just
+# have to hope you got it right.
+#ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+# interface 1 is the uart
+ftdi channel 0
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0008 0x000b
+reset_config none
+# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
+# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
+adapter speed 30000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/miniwiggler.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/miniwiggler.cfg
new file mode 100644
index 0000000..ebaa979
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/miniwiggler.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Infineon DAP miniWiggler V3
+#
+# https://www.infineon.com/cms/en/product/evaluation-boards/kit_miniwiggler_3_usb/
+#
+# Layout:  FTDI FT2232
+#   ADBUS0 TCK
+#   ADBUS1 TDI
+#   ADBUS2 TDO
+#   ADBUS3 TMS
+#   ADBUS4 nOE (output enable)
+#   ADBUS5
+#   ADBUS6
+#   ADBUS7 Blue LED
+#
+#   ACBUS0 nTRST
+#   ACBUS1 nSRST
+#   ACUBS2
+#   ACBUS3
+#   ACBUS4
+#   ACBUS5
+#   ACBUS6
+#   ACBUS7
+#
+
+adapter driver ftdi
+ftdi device_desc "DAS JDS miniWiggler V3.1"
+ftdi vid_pid 0x058b 0x0043
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal nSRST -data 0x0200 -oe 0x0200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/neodb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/neodb.cfg
new file mode 100644
index 0000000..d3b3541
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/neodb.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Openmoko USB JTAG/RS232 adapter
+#
+# http://wiki.openmoko.org/wiki/Debug_Board_v3
+#
+
+adapter driver ftdi
+ftdi device_desc "Debug Board for Neo1973"
+ftdi vid_pid 0x1457 0x5118
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
+ftdi layout_signal nNOR_WP -data 0x0010 -oe 0x0010
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ngxtech.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ngxtech.cfg
new file mode 100644
index 0000000..635333f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ngxtech.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NGX ARM USB JTAG
+#
+# http://shop.ngxtechnologies.com/product_info.php?cPath=26&products_id=30
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, but is assumed to work as this"
+echo "interface uses the same layout as configs that were verified. Please report your"
+echo "experience with this file to openocd-devel mailing list, so it could be marked"
+echo "as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "NGX JTAG"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-jtag-cjtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-jtag-cjtag.cfg
new file mode 100644
index 0000000..6939d00
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-jtag-cjtag.cfg
@@ -0,0 +1,27 @@
+#
+# Olimex ARM JTAG SWD adapter
+# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
+#
+
+#
+# Olimex ARM-USB-TINY-H
+#
+# http://www.olimex.com/dev/arm-usb-tiny-h.html
+#
+
+interface ftdi
+ftdi oscan1_mode on
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi vid_pid 0x15ba 0x002a
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+# oscan1_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg
new file mode 100644
index 0000000..6aa13af
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM JTAG SWD adapter
+# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
+#
+
+transport select swd
+
+ftdi layout_signal SWD_EN -nalias nTRST
+ftdi layout_signal SWDIO_OE -alias TMS
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg
new file mode 100644
index 0000000..36ac587
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg
@@ -0,0 +1,22 @@
+#
+# Olimex ARM-USB-OCD-H (using cJTAG)
+#
+# http://www.olimex.com/dev/arm-usb-ocd-h.html
+#
+
+interface ftdi
+ftdi oscan1_mode on
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
+ftdi vid_pid 0x15ba 0x002b
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+# oscan1_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg
new file mode 100644
index 0000000..cd11ad8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-USB-OCD-H
+#
+# http://www.olimex.com/dev/arm-usb-ocd-h.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
+ftdi vid_pid 0x15ba 0x002b
+
+ftdi layout_init 0x0908 0x0b1b
+ftdi layout_signal nSRST -oe 0x0200
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal LED -data 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg
new file mode 100644
index 0000000..d2261e2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-USB-OCD
+#
+# http://www.olimex.com/dev/arm-usb-ocd.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Olimex OpenOCD JTAG"
+ftdi vid_pid 0x15ba 0x0003
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nSRST -oe 0x0200
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal LED -data 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg
new file mode 100644
index 0000000..13378b3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg
@@ -0,0 +1,27 @@
+#
+# Olimex ARM JTAG SWD adapter
+# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
+#
+
+#
+# Olimex ARM-USB-TINY-H (using cJTAG)
+#
+# http://www.olimex.com/dev/arm-usb-tiny-h.html
+#
+
+interface ftdi
+ftdi oscan1_mode on
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi vid_pid 0x15ba 0x002a
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+# oscan1_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg
new file mode 100644
index 0000000..a2b3e3e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-USB-TINY-H
+#
+# http://www.olimex.com/dev/arm-usb-tiny-h.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi vid_pid 0x15ba 0x002a
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-jtag-tiny.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-jtag-tiny.cfg
new file mode 100644
index 0000000..7d8e81d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/olimex-jtag-tiny.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-USB-TINY
+#
+# http://www.olimex.com/dev/arm-usb-tiny.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Olimex OpenOCD JTAG TINY"
+ftdi vid_pid 0x15ba 0x0004
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/oocdlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/oocdlink.cfg
new file mode 100644
index 0000000..0e99b67
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/oocdlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Joern Kaipf's OOCDLink
+#
+# http://www.joernonline.de/contrexx2/cms/index.php?page=126
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, but is assumed to work as this"
+echo "interface uses the same layout as configs that were verified. Please report your"
+echo "experience with this file to openocd-devel mailing list, so it could be marked"
+echo "as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "OOCDLink"
+ftdi vid_pid 0x0403 0xbaf8
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/opendous_ftdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/opendous_ftdi.cfg
new file mode 100644
index 0000000..5d6f5ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/opendous_ftdi.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Opendous
+#
+# http://code.google.com/p/opendous/wiki/JTAG
+#
+# According to the website, it is similar to jtagkey, but it uses channel B
+# (and it has a different pid number).
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 1
+
+ftdi layout_init 0x0c08 0x0f1b
+ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/openocd-usb-hs.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/openocd-usb-hs.cfg
new file mode 100644
index 0000000..af1f61c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/openocd-usb-hs.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# embedded projects openocd usb adapter v3
+#
+# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/openocd-usb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/openocd-usb.cfg
new file mode 100644
index 0000000..c333d65
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/openocd-usb.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hubert Hoegl's USB to JTAG
+#
+# http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/openrd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/openrd.cfg
new file mode 100644
index 0000000..b6b2d1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/openrd.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marvell OpenRD
+#
+# http://www.marvell.com/products/embedded_processors/developer/kirkwood/openrd.jsp
+#
+
+adapter driver ftdi
+ftdi device_desc "OpenRD JTAGKey FT2232D B"
+ftdi vid_pid 0x0403 0x9e90
+ftdi channel 0
+
+ftdi layout_init 0x0608 0x0f1b
+ftdi layout_signal nTRST -data 0x0200
+ftdi layout_signal nSRST -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/pipistrello.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/pipistrello.cfg
new file mode 100644
index 0000000..29ecd12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/pipistrello.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# http://pipistrello.saanlima.com/
+# http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdf
+adapter driver ftdi
+ftdi device_desc "Pipistrello LX45"
+ftdi vid_pid 0x0403 0x6010
+# interface 1 is the uart
+ftdi channel 0
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0008 0x000b
+reset_config none
+# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
+# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
+adapter speed 10000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/pls_spc5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/pls_spc5.cfg
new file mode 100644
index 0000000..3b3c2d6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/pls_spc5.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# PLS SPC5-UDESTK
+#
+# https://www.st.com/en/development-tools/spc5-udestk.html
+#
+# Reference the SPC56D Discovery schematics.
+#
+# Layout:  FTDI FT2232
+#   ADBUS0 TCK
+#   ADBUS1 TDI
+#   ADBUS2 TDO
+#   ADBUS3 TMS
+#   ADBUS4 TMS
+#   ADBUS5 RTCK
+#   ADBUS6
+#   ADBUS7 LED1
+#
+#   ACBUS0 nTRST
+#   ACBUS1 nSRST (external pull-down)
+#   ACUBS2
+#   ACBUS3
+#   ACBUS4
+#   ACBUS5 nSRST direction (input=L, output=H, external pull-down)
+#   ACBUS6 TMS direction (input=L, output=H, external pull-up)
+#   ACBUS7 LED2
+#
+
+adapter driver ftdi
+ftdi device_desc "PLS USB/JTAG Adapter for SPC5xxx"
+ftdi vid_pid 0x263d 0x4001
+
+ftdi channel 0
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal nSRST -ndata 0x2000 -oe 0x2000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/redbee-econotag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/redbee-econotag.cfg
new file mode 100644
index 0000000..d0d3d83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/redbee-econotag.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Redwire Redbee-Econotag
+#
+# http://www.redwirellc.com/store/node/1
+#
+# The Redbee-Econotag has an onboard FT2232H with:
+#  - FT2232H channel A wired to mc13224v JTAG
+#  - FT2232H channel B wired to mc13224v UART1
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0c08 0x0c2b
+ftdi layout_signal nTRST -data 0x0800
+ftdi layout_signal nSRST -data 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/redbee-usb.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/redbee-usb.cfg
new file mode 100644
index 0000000..9880553
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/redbee-usb.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Redwire Redbee-USB
+#
+# http://www.redwirellc.com
+#
+# The Redbee-USB has an onboard FT2232H with:
+#  - FT2232H channel B wired to mc13224v JTAG
+#  - FT2232H channel A wired to mc13224v UART1
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 1
+
+ftdi layout_init 0x0c08 0x0c2b
+ftdi layout_signal nTRST -data 0x0800
+ftdi layout_signal nSRST -data 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/rowley-cc-arm-swd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/rowley-cc-arm-swd.cfg
new file mode 100644
index 0000000..585d589
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/rowley-cc-arm-swd.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Rowley ARM SWD Adapter
+# http://sites.fastspring.com/rowley/product/armswdadapter
+# https://drive.google.com/file/d/0Bzv7UpKpOQhnTUNNdzI5OUR4WGs/edit?usp=sharing
+#
+
+transport select swd
+
+ftdi layout_signal SWD_EN -nalias nTRST
+ftdi layout_signal SWDIO_OE -alias TMS
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/sheevaplug.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/sheevaplug.cfg
new file mode 100644
index 0000000..29c8688
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/sheevaplug.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Marvel SheevaPlug Development Kit
+#
+# http://www.marvell.com/products/embedded_processors/developer/kirkwood/sheevaplug.jsp
+#
+
+adapter driver ftdi
+ftdi device_desc "SheevaPlug JTAGKey FT2232D B"
+ftdi vid_pid 0x9e88 0x9e8f
+ftdi channel 0
+
+ftdi layout_init 0x0608 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/signalyzer-lite.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/signalyzer-lite.cfg
new file mode 100644
index 0000000..e6c3839
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/signalyzer-lite.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xverve Signalyzer LITE (DT-USB-SLITE)
+#
+# http://www.signalyzer.com
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Signalyzer LITE"
+ftdi vid_pid 0x0403 0xbca1
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/signalyzer.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/signalyzer.cfg
new file mode 100644
index 0000000..fa7a7ed
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/signalyzer.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xverve Signalyzer Tool (DT-USB-ST)
+#
+# http://www.signalyzer.com
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on code in ft2232.c."
+echo "Please report your experience with this file to openocd-devel mailing list,"
+echo "so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Signalyzer"
+ftdi vid_pid 0x0403 0xbca0
+
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/sipeed-rv-debugger.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/sipeed-rv-debugger.cfg
new file mode 100644
index 0000000..ca65398
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/sipeed-rv-debugger.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Interface file for BL702-based SIPEED RV Debugger
+#
+
+adapter driver ftdi
+adapter speed 6000
+
+ftdi device_desc "JTAG Debugger"
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/sipeed-usb-jtag-debugger.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/sipeed-usb-jtag-debugger.cfg
new file mode 100644
index 0000000..8a804ec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/sipeed-usb-jtag-debugger.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Sipeed USB-JTAG/TTL RISC-V Debugger
+#
+# https://www.seeedstudio.com/Sipeed-USB-JTAG-TTL-RISC-V-Debugger-p-2910.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232"
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+
+# Every pin set as high impedance except TCK, TDI, TDO, TMS and RST
+ftdi layout_init 0x0028 0x002b
+
+transport select jtag
+
+# nSRST defined on pin RST of the Debugger (pin ADBUS5 [AD5] on the FT2232D chip)
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/snps_sdp.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/snps_sdp.cfg
new file mode 100644
index 0000000..eb2aecc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/snps_sdp.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Synopsys SDP Mainboard has embdded FT2232 chip, which is similar to Digilent
+# HS-1, except that it uses channel B for JTAG communication, instead of
+# channel A.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x0088 0x008b
+ftdi channel 1
+
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/steppenprobe.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/steppenprobe.cfg
new file mode 100644
index 0000000..f84efe6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/steppenprobe.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Steppenprobe
+# https://github.com/diegoherranz/steppenprobe
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+# Initial Layout
+ftdi layout_init 0x0058 0x99fb
+# Signal        Data    Direction       Notes
+# TCK           0       1 (out)
+# TDI           0       1 (out)
+# TDO           0       0 (in)
+# TMS           1       1 (out)         JTAG IEEE std recommendation
+# LED           1       1 (out)         LED off
+# SWD_EN        0       1 (out)         OpenOCD sets this high for SWD
+# SWDIO_OE      1       1 (out)         Ext. buffer tristated
+# SRST          0       1 (out)         Translates to nSRST=Z
+
+# Unused        0       1 (out)
+# GPIO_A        0       0 (in)
+# GPIO_B        0       0 (in)
+# Unused        0       1 (out)
+# Unused        0       1 (out)
+# GPIO_C        0       0 (in)
+# GPIO_D        0       0 (in)
+# Unused        0       1 (out)
+
+# Signals definition
+ftdi layout_signal LED -ndata 0x0010
+ftdi layout_signal SWD_EN -data 0x0020
+ftdi layout_signal SWDIO_OE -ndata 0x0040
+ftdi layout_signal nSRST -oe 0x0080
+
+ftdi layout_signal GPIO_A -data 0x0200 -oe 0x0200 -input 0x0200
+ftdi layout_signal GPIO_B -data 0x0400 -oe 0x0400 -input 0x0400
+ftdi layout_signal GPIO_C -data 0x2000 -oe 0x2000 -input 0x2000
+ftdi layout_signal GPIO_D -data 0x4000 -oe 0x4000 -input 0x4000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/stm32-stick.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/stm32-stick.cfg
new file mode 100644
index 0000000..1d72d20
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/stm32-stick.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Hitex STM32-PerformanceStick
+#
+# http://www.hitex.com/index.php?id=340
+#
+
+adapter driver ftdi
+ftdi device_desc "STM32-PerformanceStick"
+ftdi vid_pid 0x0640 0x002d
+
+ftdi layout_init 0x0388 0x038b
+ftdi layout_signal nTRST -data 0x0100
+ftdi layout_signal nSRST -data 0x0080 -noe 0x200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/swd-resistor-hack.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/swd-resistor-hack.cfg
new file mode 100644
index 0000000..d9e7158
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/swd-resistor-hack.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Connect TDI to SWDIO via a suitable series resistor (220-470 Ohm or
+# so depending on the drive capability of the target and adapter);
+# connect TDO directly to SWDIO.
+#
+# You also need to have reliable GND connection between the target and
+# adapter. Vref of the adapter should be supplied with a voltage equal
+# to the target's (preferably connect it to Vcc). You can also
+# optionally connect nSRST. Leave everything else unconnected.
+#
+# FTDI                          Target
+# ----                          ------
+# 1  - Vref   ----------------- Vcc
+# 3  - nTRST  -
+# 4  - GND    ----------------- GND
+# 5  - TDI    ---/\470 Ohm/\--- SWDIO
+# 7  - TMS    -
+# 9  - TCK    ----------------- SWCLK
+# 11 - RTCK   -
+# 13 - TDO    ----------------- SWDIO
+# 15 - nSRST  - - - - - - - - - nRESET
+#
+
+transport select swd
+
+ftdi layout_signal SWD_EN -data 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ti-icdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ti-icdi.cfg
new file mode 100644
index 0000000..964de76
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/ti-icdi.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This is an FTDI-based debugging solution as found on some TI boards,
+# e.g. CC3200 LaunchPad.
+#
+# The schematics are identical to luminary-icdi (including SWD
+# support) but the USB IDs are different.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0451 0xc32a
+
+ftdi layout_init 0x00a8 0x00eb
+ftdi layout_signal nSRST -noe 0x0020
+ftdi layout_signal SWD_EN -ndata 0x0080
+ftdi layout_signal SWDIO_OE -data 0x0008
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/tigard.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/tigard.cfg
new file mode 100644
index 0000000..43ce0ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/tigard.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Tigard: An FTDI FT2232H-based multi-protocol tool for hardware hacking.
+# https://github.com/tigard-tools/tigard
+
+adapter driver ftdi
+
+ftdi device_desc "Tigard V1.1"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi channel 1
+
+ftdi layout_init 0x0038 0x003b
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -data 0x0020
+
+# This board doesn't support open-drain reset modes since its output buffer is
+# always enabled.
+reset_config srst_push_pull trst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/tumpa-lite.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/tumpa-lite.cfg
new file mode 100644
index 0000000..e3f12e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/tumpa-lite.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TIAO USB Multi-Protocol Adapter (TUMPA) Lite
+#
+# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-lite-jtag-spi-i2c-serial.html
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x8a99
+
+ftdi layout_init 0x0038 0x087b
+ftdi layout_signal nTRST -data 0x0020 -oe 0x0020
+ftdi layout_signal nSRST -data 0x0010 -oe 0x0010
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/tumpa.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/tumpa.cfg
new file mode 100644
index 0000000..db4311b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/tumpa.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TIAO USB Multi-Protocol Adapter (TUMPA)
+#
+# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-jtag-spi-i2c-serial.html
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x8a98 0x0403 0x6010
+
+ftdi layout_init 0x0038 0x087b
+ftdi layout_signal nTRST -data 0x0020
+ftdi layout_signal nSRST -data 0x0010
+
+reset_config srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/turtelizer2-revB.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/turtelizer2-revB.cfg
new file mode 100644
index 0000000..f90fc58
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/turtelizer2-revB.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# egnite Turtelizer 2 rev B (with SRST only)
+#
+# http://www.ethernut.de/en/hardware/turtelizer/index.html
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, it is based on schematics and code"
+echo "in ft2232.c. Please report your experience with this file to openocd-devel"
+echo "mailing list, so it could be marked as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "Turtelizer JTAG/RS232 Adapter"
+ftdi vid_pid 0x0403 0xbdc8
+
+ftdi layout_init 0x0008 0x0c5b
+ftdi layout_signal nSRST -oe 0x0040
+ftdi layout_signal LED -data 0x0c00
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/turtelizer2-revC.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/turtelizer2-revC.cfg
new file mode 100644
index 0000000..94617a1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/turtelizer2-revC.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# egnite Turtelizer 2 revC (with TRST and SRST)
+#
+# http://www.ethernut.de/en/hardware/turtelizer/index.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Turtelizer JTAG/RS232 Adapter"
+ftdi vid_pid 0x0403 0xbdc8
+
+ftdi layout_init 0x0008 0x0c7b
+ftdi layout_signal nTRST -oe 0x0020
+ftdi layout_signal nSRST -oe 0x0040
+ftdi layout_signal LED -ndata 0x0c00
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/um232h.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/um232h.cfg
new file mode 100644
index 0000000..6be08b5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/um232h.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# FTDI UM232H as a JTAG interface
+#
+# http://www.ftdichip.com/Products/Modules/DevelopmentModules.htm#UM232H
+#
+# This should also work with a UM232H-B, but that has not been tested.
+# Note that UM232H and UM232H-B are 3.3V only.
+#
+
+adapter driver ftdi
+#ftdi device_desc "UM232H"
+ftdi vid_pid 0x0403 0x6014
+
+ftdi layout_init 0xfff8 0xfffb
+ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal nSRST -data 0x0200 -oe 0x0200
+
+# UM232H        FT232H    JTAG
+# Name  Pin     Name      Func
+# AD0   J2-6    ADBUS0    TCK
+# AD1   J2-7    ADBUS1    TDI
+# AD2   J2-8    ADBUS2    TDO
+# AD3   J2-9    ADBUS3    TMS
+# AD4   J2-10   ADBUS4    (GPIOL0)
+# AD5   J2-11   ADBUS5    (GPIOL1)
+# AD6   J2-12   ADBUS6    (GPIOL2)
+# AD7   J2-13   ADBUS7    (GPIOL3)
+# AD0   J1-14   ACBUS0    /TRST
+# AD1   J1-13   ACBUS1    /SRST
+# AD2   J1-12   ACBUS2    (GPIOH2)
+# AD3   J1-11   ACBUS3    (GPIOH3)
+# AD4   J1-10   ACBUS4    (GPIOH4)
+# AD5   J1-9    ACBUS5    (GPIOH5)
+# AD6   J1-8    ACBUS6    (GPIOH6)
+# AD7   J1-7    ACBUS7    (GPIOH7)
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/vpaclink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/vpaclink.cfg
new file mode 100644
index 0000000..ff508f2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/vpaclink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Voipac VPACLink
+#
+# http://voipac.com/27M-JTG-000
+#
+
+echo "WARNING!"
+echo "This file was not tested with real interface, but is assumed to work as this"
+echo "interface uses the same layout as configs that were verified. Please report your"
+echo "experience with this file to openocd-devel mailing list, so it could be marked"
+echo "as working or fixed."
+
+adapter driver ftdi
+ftdi device_desc "VPACLink"
+ftdi vid_pid 0x0403 0x6010
+
+ftdi layout_init 0x0508 0x0f1b
+ftdi layout_signal nTRST -data 0x0200 -noe 0x0100
+ftdi layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/xds100v2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/xds100v2.cfg
new file mode 100644
index 0000000..373df4f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/xds100v2.cfg
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments XDS100v2
+#
+# http://processors.wiki.ti.com/index.php/XDS100#XDS100v2_Features
+#
+# Detailed documentation is available only as CPLD verilog source code
+# to the registered TI users.
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0xa6d0 0x0403 0x6010
+
+ftdi layout_init 0x0038 0x597b
+
+#  8000 z - unused
+#  4000 0 > CPLD loopback          (all target side pins high-Z)
+#  2000 z < !( cable connected )   (open drain on CPLD side for $reasons)
+#  1000 0 > EMU1_oe
+#
+#   800 0 > PWR_RST = clear power-loss flag on rising edge
+#   400 z < !( power-loss flag )
+#   200 z < nSRST
+#   100 0 > nSRST_oe
+#
+#    80 z < RTCK
+#    40 0 > EMU0_oe
+#    20 1 > EMU_EN
+#    10 1 > nTRST
+#
+#     8 1 > TMS
+#     4 z < TDO
+#     2 0 > TDI
+#     1 0 > TCK
+#
+# As long as the power-loss flag is set, all target-side pins are
+# high-Z except the EMU-pins for which the opposite holds unless
+# EMU_EN is high.
+#
+# To use wait-in-reset, drive EMU0 low at power-on reset. If the
+# target normally reuses EMU0 for other purposes, clear EMU_EN to
+# keep the EMU pins high-Z until the target is power-cycled.
+#
+# The LED only turns off at USB suspend, which is also the only way to
+# set the power-loss flag manually. (Can be done in software e.g. by
+# changing the USB configuration to zero.)
+#
+
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -oe 0x0100
+ftdi layout_signal EMU_EN -data 0x0020
+ftdi layout_signal EMU0 -oe 0x0040
+ftdi layout_signal EMU1 -oe 0x1000
+ftdi layout_signal PWR_RST -data 0x0800
+ftdi layout_signal LOOPBACK -data 0x4000
+
+echo "\nInfo : to use this adapter you MUST add ``init; ftdi set_signal PWR_RST 1; jtag arp_init'' to the end of your config file!\n"
+# note: rising edge on PWR_RST is also needed after power-cycling the
+# target
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/xds100v3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/xds100v3.cfg
new file mode 100644
index 0000000..dc72233
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/xds100v3.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments XDS100 ver 3.0
+#
+# http://processors.wiki.ti.com/index.php/XDS100
+#
+
+# Version 3.0 is the same as 2.0 as far as OpenOCD is concerned
+source [find interface/ftdi/xds100v2.cfg]
+
+# The USB ids are different.
+ftdi vid_pid 0x0403 0xa6d1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/xt_kc705_ml605.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/xt_kc705_ml605.cfg
new file mode 100644
index 0000000..dda8c0a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ftdi/xt_kc705_ml605.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Xilinx KC705 / ML605 with Xtensa daughtercard; onboard USB/FT2232
+#
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+# Specify "adapter serial " here as needed
+
+ftdi layout_init 0x0010 0x007b
+ftdi layout_signal nTRST -data 0x0010
+ftdi layout_signal nSRST -ndata 0x0020
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/imx-native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/imx-native.cfg
new file mode 100644
index 0000000..01e42e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/imx-native.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Config for using NXP IMX CPU
+#
+# This is best used with a fast enough buffer but also
+# is suitable for direct connection if the target voltage
+# matches to host voltage and the cable is short enough.
+#
+#
+
+adapter driver imx_gpio
+
+# For most IMX processors 0x0209c000
+imx_gpio_peripheral_base 0x0209c000
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on system clock, calibrated for IMX6UL@528MHz
+# imx_gpio_speed SPEED_COEFF SPEED_OFFSET
+imx_gpio_speed_coeffs 50000 50
+
+# Each of the JTAG lines need a gpio number set: tck tms tdi tdo.
+# Example configuration:
+# imx_gpio_jtag_nums 6 7 8 9
+
+# SWD interface pins: swclk swdio
+# Example configuration:
+imx_gpio_swd_nums 1 6
+
+# imx_gpio_trst_num 10
+# reset_config trst_only
+
+# imx_gpio_srst_num 11
+# reset_config srst_only srst_push_pull
+
+# or if you have both connected,
+# reset_config trst_and_srst srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jlink.cfg
new file mode 100644
index 0000000..181c2cc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jlink.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# SEGGER J-Link
+#
+# http://www.segger.com/jlink.html
+#
+
+adapter driver jlink
+
+# The serial number can be used to select a specific device in case more than
+# one is connected to the host.
+#
+# Example: Select J-Link with serial number 123456789
+#
+# adapter serial 123456789
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jtag_dpi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jtag_dpi.cfg
new file mode 100644
index 0000000..225d4d5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jtag_dpi.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Provide support for the Cadence JTAG BFM
+#
+# Copyright (c) 2020, Ampere Computing LLC
+#
+
+adapter driver jtag_dpi
+
+# Set the DPI JTAG server port
+if { [info exists DPI_PORT] } {
+   set _DPI_PORT $DPI_PORT
+} else {
+   set _DPI_PORT 5555
+}
+
+# Set the DPI JTAG server address
+if { [info exists DPI_ADDRESS] } {
+   set _DPI_ADDRESS $DPI_ADDRESS
+} else {
+   set _DPI_ADDRESS "127.0.0.1"
+}
+
+jtag_dpi set_port $_DPI_PORT
+jtag_dpi set_address $_DPI_ADDRESS
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jtag_hat_rpi2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jtag_hat_rpi2.cfg
new file mode 100644
index 0000000..cd1cbfb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jtag_hat_rpi2.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Blinkinlabs JTAG_Hat
+#
+# https://github.com/blinkinlabs/jtag_hat
+#
+
+adapter driver bcm2835gpio
+
+bcm2835gpio peripheral_base 0x3F000000
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on system clock, calibrated for stock 700MHz
+# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET
+bcm2835gpio speed_coeffs 146203 36
+
+# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
+# Header pin numbers: 23 22 19 21
+adapter gpio tck -chip 0 11
+adapter gpio tms -chip 0 25
+adapter gpio tdi -chip 0 10
+adapter gpio tdo -chip 0 9
+
+# Each of the SWD lines need a gpio number set: swclk swdio
+# Header pin numbers: 23 22
+adapter gpio swclk -chip 0 11
+adapter gpio swdio -chip 0 25
+
+# Direction pin for SWDIO level shifting buffer
+adapter gpio swdio_dir -chip 0 6
+
+# If you define trst or srst, use appropriate reset_config
+# Header pin numbers: TRST - 26, SRST - 18
+
+adapter gpio trst -chip 0 7
+#reset_config trst_only
+
+adapter gpio srst -chip 0 24
+#reset_config srst_only
+
+# or if you have both connected
+#reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jtag_vpi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jtag_vpi.cfg
new file mode 100644
index 0000000..e8164ab
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/jtag_vpi.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter driver jtag_vpi
+
+# Set the VPI JTAG server port
+if { [info exists VPI_PORT] } {
+   set _VPI_PORT $VPI_PORT
+} else {
+   set _VPI_PORT 5555
+}
+
+# Set the VPI JTAG server address
+if { [info exists VPI_ADDRESS] } {
+   set _VPI_ADDRESS $VPI_ADDRESS
+} else {
+   set _VPI_ADDRESS "127.0.0.1"
+}
+
+jtag_vpi set_port $_VPI_PORT
+jtag_vpi set_address $_VPI_ADDRESS
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/kitprog.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/kitprog.cfg
new file mode 100644
index 0000000..eb9ad98
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/kitprog.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Cypress Semiconductor KitProg
+#
+# Note: This is the driver for the proprietary KitPtog protocol. If the
+# KitProg is in CMSIS-DAP mode, you should either use the cmsis-dap
+# interface driver or switch the KitProg to KitProg mode.
+#
+
+adapter driver kitprog
+
+# Optionally specify the serial number of the KitProg you want to use.
+# adapter serial 1926402735485200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/nulink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/nulink.cfg
new file mode 100644
index 0000000..48dc20e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/nulink.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nuvoton Nu-Link in-circuit debugger/programmer
+#
+
+adapter driver hla
+hla layout nulink
+hla device_desc "Nu-Link"
+hla vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201
+
+# Only swd is supported
+transport select hla_swd
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/opendous.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/opendous.cfg
new file mode 100644
index 0000000..9c5a804
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/opendous.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# opendous-jtag
+#
+# http://code.google.com/p/opendous-jtag/
+#
+
+adapter driver opendous
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/openjtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/openjtag.cfg
new file mode 100644
index 0000000..1602352
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/openjtag.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# OpenJTAG
+#
+# www.openjtag.org
+#
+
+adapter driver openjtag
+openjtag device_desc "Open JTAG Project"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/osbdm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/osbdm.cfg
new file mode 100644
index 0000000..e21848d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/osbdm.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# P&E Micro OSBDM (aka OSJTAG) interface
+#
+# http://pemicro.com/osbdm/
+#
+adapter driver osbdm
+reset_config srst_only
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport.cfg
new file mode 100644
index 0000000..8fb1c14
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Parallel port wiggler (many clones available) on port 0x378
+#
+# Addresses: 0x378/LPT1 or 0x278/LPT2 ...
+#
+echo "DEPRECATED: use interface/parport/wiggler.cfg instead of deprecated interface/parport.cfg"
+
+source [find interface/parport/wiggler.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport/dlc5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport/dlc5.cfg
new file mode 100644
index 0000000..24acea7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport/dlc5.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xilinx Parallel Cable III 'DLC 5' (and various clones)
+#
+# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html
+#
+
+if { [info exists PARPORTADDR] } {
+   set _PARPORTADDR $PARPORTADDR
+} else {
+   set _PARPORTADDR 0
+}
+
+adapter driver parport
+parport port $_PARPORTADDR
+parport cable dlc5
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport/wiggler.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport/wiggler.cfg
new file mode 100644
index 0000000..b9fceeb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport/wiggler.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Parallel port wiggler (many clones available) on port 0x378
+#
+# Addresses: 0x378/LPT1 or 0x278/LPT2 ...
+#
+
+if { [info exists PARPORTADDR] } {
+   set _PARPORTADDR $PARPORTADDR
+} else {
+   if {$tcl_platform(platform) eq "windows"} {
+      set _PARPORTADDR 0x378
+   } {
+      set _PARPORTADDR 0
+   }
+}
+
+adapter driver parport
+parport port $_PARPORTADDR
+parport cable wiggler
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport_dlc5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport_dlc5.cfg
new file mode 100644
index 0000000..83f3b56
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/parport_dlc5.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xilinx Parallel Cable III 'DLC 5' (and various clones)
+#
+# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html
+#
+echo "DEPRECATED: use interface/parport/dlc5.cfg instead of deprecated interface/parport_dlc5.cfg"
+
+source [find interface/parport/dlc5.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi-gpio-connector.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi-gpio-connector.cfg
new file mode 100644
index 0000000..af7266b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi-gpio-connector.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Config for Raspberry Pi GPIO header
+#
+# This is best used with a fast enough buffer but also
+# is suitable for direct connection if the target voltage
+# matches RPi's 3.3V and the cable is short enough.
+#
+# Do not forget the GND connection, e.g. pin 20 of the GPIO header.
+#
+
+if { [info exists GPIO_CHIP] } {
+    set _GPIO_CHIP $GPIO_CHIP
+} else {
+    set _GPIO_CHIP 0
+}
+
+# GPIO 25 (pin 22) previously used for TMS/SWDIO is pulled-down by default.
+# The JTAG/SWD specification requires pull-up at the target board
+# for either signal. Connecting the signal pulled-up on the target
+# to the pull-down on the adapter is not a good idea.
+# GPIO 8 is pulled-up by default.
+echo "Warn : TMS/SWDIO moved to GPIO 8 (pin 24). Check the wiring please!"
+
+# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
+# Header pin numbers: 23 24 19 21
+adapter gpio tck -chip $_GPIO_CHIP 11
+adapter gpio tms -chip $_GPIO_CHIP 8
+adapter gpio tdi -chip $_GPIO_CHIP 10
+adapter gpio tdo -chip $_GPIO_CHIP 9
+
+# Each of the SWD lines need a gpio number set: swclk swdio
+# Header pin numbers: 23 24
+adapter gpio swclk -chip $_GPIO_CHIP 11
+adapter gpio swdio -chip $_GPIO_CHIP 8
+
+# If you define trst or srst, use appropriate reset_config
+# Header pin numbers: TRST - 26, SRST - 18
+
+# adapter gpio trst -chip $_GPIO_CHIP 7
+# reset_config trst_only
+
+# adapter gpio srst -chip $_GPIO_CHIP 24
+# reset_config srst_only srst_push_pull
+
+# or if you have both connected,
+# reset_config trst_and_srst srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi-native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi-native.cfg
new file mode 100644
index 0000000..c80f90a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi-native.cfg
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Raspberry Pi used as a bitbang adapter.
+# https://www.raspberrypi.com/documentation/computers/raspberry-pi.html
+
+# Supports all models with 40-pin or 26-pin GPIO connector up to Raspberry Pi 4 B
+# also supports Raspberry Pi Zero, Zero W and Zero 2 W.
+
+# Adapter speed calibration is computed from cpufreq/scaling_max_freq.
+# Adjusts automatically if CPU is overclocked.
+
+adapter driver bcm2835gpio
+
+proc read_file { name } {
+	if {[catch {open $name r} fd]} {
+		return ""
+	}
+	set result [read $fd]
+	close $fd
+	return $result
+}
+
+proc measure_clock {} {
+	set result [exec vcgencmd measure_clock arm]
+	set clock_hz [lindex [split $result "="] 1]
+	expr { $clock_hz / 1000 }
+}
+
+proc get_max_cpu_clock { default } {
+	set clock [read_file /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq]
+	if { $clock > 100000 } {
+		return $clock
+	}
+
+	# cpufreq not available. As the last resort try Broadcom's proprietary utility
+	if {![catch measure_clock clock] && $clock > 100000} {
+		return $clock
+	}
+
+	echo "Warn : Host CPU clock unknown."
+	echo "Warn : Using the highest possible value $default kHz as a safe default."
+	echo "Warn : Expect JTAG/SWD clock significantly slower than requested."
+
+	return $default
+}
+
+set compat [read_file /proc/device-tree/compatible]
+set clocks_per_timing_loop 4
+
+if {[string match *bcm2711* $compat]} {
+	set speed_offset 52
+} elseif {[string match *bcm2837* $compat] || [string match *bcm2710* $compat]} {
+	set speed_offset 34
+} elseif {[string match *bcm2836* $compat] || [string match *bcm2709* $compat]} {
+	set speed_offset 36
+} elseif {[string match *bcm2835* $compat] || [string match *bcm2708* $compat]} {
+	set clocks_per_timing_loop 6
+	set speed_offset 32
+} elseif {[string match *bcm2712* $compat]} {
+	echo "Error: Raspberrypi Pi 5 has moved GPIOs to PCIe connected RP1 chip."
+	echo "Error: Native GPIO handling is not supported, use 'raspberrypi5-gpiod.cfg'"
+	shutdown
+} else {
+	set speed_offset 32
+	echo "Warn : Unknown type of the host SoC. Expect JTAG/SWD clock slower than requested."
+}
+
+set clock [get_max_cpu_clock 2000000]
+set speed_coeff [expr { $clock / $clocks_per_timing_loop }]
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# The coefficients depend on system clock and CPU frequency scaling.
+bcm2835gpio speed_coeffs $speed_coeff $speed_offset
+
+source [find interface/raspberrypi-gpio-connector.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi2-native.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi2-native.cfg
new file mode 100644
index 0000000..fe9186f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi2-native.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/raspberrypi2-native.cfg is deprecated."
+echo "WARNING: Please use interface/raspberrypi-native.cfg for all Raspberry Pi models."
+
+source [find interface/raspberrypi-native.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi5-gpiod.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi5-gpiod.cfg
new file mode 100644
index 0000000..9624ad5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/raspberrypi5-gpiod.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Raspberry Pi 5 used as a bitbang adapter.
+# https://www.raspberrypi.com/documentation/computers/raspberry-pi.html
+
+# Raspberry Pi 5 is not compatible with bcm2835gpio native GPIO driver.
+# The linuxgpiod driver without configurable adapter speed runs at approximately
+# 800 kHz (SWD writes) and 360 kHz (SWD reads)
+
+adapter driver linuxgpiod
+
+proc read_file { name } {
+	if {[catch {open $name r} fd]} {
+		return ""
+	}
+	set result [read $fd]
+	close $fd
+	return $result
+}
+
+set pcie_aspm [read_file /sys/module/pcie_aspm/parameters/policy]
+if {![string match {*\[performance\]*} $pcie_aspm]} {
+	echo "Warn : Switch PCIe power saving off or the first couple of pulses gets clocked as fast as 20 MHz"
+	echo "Warn : Issue 'echo performance | sudo tee /sys/module/pcie_aspm/parameters/policy'"
+}
+
+set GPIO_CHIP 4
+source [find interface/raspberrypi-gpio-connector.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/rlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/rlink.cfg
new file mode 100644
index 0000000..7671a3b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/rlink.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Raisonance RLink
+#
+# http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html
+#
+
+adapter driver rlink
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/rshim.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/rshim.cfg
new file mode 100644
index 0000000..1d5da59
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/rshim.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# BlueField SoC in-circuit debugger/programmer
+#
+
+adapter driver rshim
+transport select dapdirect_swd
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-dap.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-dap.cfg
new file mode 100644
index 0000000..009fdb7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-dap.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/stlink-dap.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
+
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-hla.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-hla.cfg
new file mode 100644
index 0000000..5c4adb8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-hla.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
+# debugger/programmer
+#
+
+echo "DEPRECATED: OpenOCD support for ST-Link HLA transport will be dropped soon!"
+echo "Consider updating your ST-Link firmware to a version >= V2J24 (2015)"
+
+adapter driver hla
+hla layout stlink
+hla device_desc "ST-LINK"
+hla vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
+
+# Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2
+# devices seem to have serial numbers with unreadable characters.  ST-LINK/V2
+# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
+# number reset issues.
+# eg.
+# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-v1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-v1.cfg
new file mode 100644
index 0000000..96ed088
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-v1.cfg
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/stlink-v1.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-v2-1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-v2-1.cfg
new file mode 100644
index 0000000..d2baad4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-v2-1.cfg
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-v2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-v2.cfg
new file mode 100644
index 0000000..400411e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink-v2.cfg
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink.cfg
new file mode 100644
index 0000000..99c81c1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/stlink.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
+# debugger/programmer
+#
+# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect"
+# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect"
+#
+# SWIM transport is natively supported
+#
+
+adapter driver st-link
+st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
+
+# transport select dapdirect_jtag
+# transport select dapdirect_swd
+# transport select swim
+
+# Optionally specify the serial number of usb device
+# e.g.
+# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/sysfsgpio-raspberrypi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/sysfsgpio-raspberrypi.cfg
new file mode 100644
index 0000000..d2095a9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/sysfsgpio-raspberrypi.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Config for using RaspberryPi's expansion header
+#
+# This is best used with a fast enough buffer but also
+# is suitable for direct connection if the target voltage
+# matches RPi's 3.3V
+#
+# Do not forget the GND connection, pin 6 of the expansion header.
+#
+
+adapter driver sysfsgpio
+
+# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
+# Header pin numbers: 23 22 19 21
+sysfsgpio jtag_nums 11 25 10 9
+
+# Each of the SWD lines need a gpio number set: swclk swdio
+# Header pin numbers: 23 22
+sysfsgpio swd_nums 11 25
+
+# If you define trst or srst, use appropriate reset_config
+# Header pin numbers: TRST - 26, SRST - 18
+
+# sysfsgpio trst_num 7
+# reset_config trst_only
+
+# sysfsgpio srst_num 24
+# reset_config srst_only srst_push_pull
+
+# or if you have both connected,
+# reset_config trst_and_srst srst_push_pull
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ti-icdi.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ti-icdi.cfg
new file mode 100644
index 0000000..c13d27e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ti-icdi.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Stellaris In-Circuit Debug Interface (ICDI) Board
+#
+# This is the propriety ICDI interface used on newer boards such as
+# LM4F232 Evaluation Kit - http://www.ti.com/tool/ek-lm4f232
+# Stellaris Launchpad - http://www.ti.com/stellaris-launchpad
+# http://www.ti.com/tool/ek-lm4f232
+#
+
+adapter driver hla
+hla layout ti-icdi
+hla vid_pid 0x1cbe 0x00fd
+
+# Optionally specify the serial number of TI-ICDI devices, for when using
+# multiple devices. Serial numbers can be obtained using lsusb -v
+# Ex.
+# adapter serial "0F003065"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ulink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ulink.cfg
new file mode 100644
index 0000000..89a02e9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/ulink.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Keil ULINK running OpenULINK firmware.
+#
+# http://www.keil.com/ulink1/
+# http://article.gmane.org/gmane.comp.debugging.openocd.devel/17362
+#
+
+adapter driver ulink
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/usb-jtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/usb-jtag.cfg
new file mode 100644
index 0000000..039c748
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/usb-jtag.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ixo-usb-jtag - Emulation of a Altera Bus Blaster I on a Cypress FX2 IC.
+#
+# The ixo-usb-jtag firmware can be loaded onto a bunch of different hardware
+# including;
+#  * Xilinx USB Platform Cable
+#  * Many Digilent boards such as the Nexys, Nexys 2 and Atlys boards
+#  * Many fpga4fun.com boards from such as the Saxo and Xylo boards
+#  * The Numato Opsis
+#
+# Original version - http://www.ixo.de/info/usb_jtag/
+#  Updated version - http://ixo-jtag.sourceforge.net/
+#   Newest version - http://github.com/mithro/ixo-usb-jtag
+#
+# Procedure for using is;
+#  * Get the ixo-usb-jtag firmware for your hardware (or build it yourself).
+#  * Load the firmware using the fxload tool.
+#  * Use openocd.
+#
+# Unless you burn the firmware into the EEPROM on your device, power cycling
+# will require you to reload the firmware using the fxload tool. This can be
+# automated by using udev rules (which can be found in the firmware
+# repository).
+#
+# Ubuntu packages built from mithro's version (with prebuilt firmware and udev
+# rules) can be found at
+# https://launchpad.net/~timvideos/+archive/ubuntu/fpga-support
+#
+# TODO: Refactor the usb_blaster driver to allow loading firmware using any low
+# level driver. Loading firmware is currently only supported on the ublast2
+# driver but ixo-usb-jtag requires the ftdi driver.
+
+adapter driver usb_blaster
+usb_blaster vid_pid 0x16C0 0x06AD
+usb_blaster device_desc "Van Ooijen Technische Informatica"
+# ixo-usb-jtag is only compatible with the ublast1 protocol implemented via the
+# ftdi modes, using ublast2 will cause openocd to hang.
+usb_blaster lowlevel_driver ftdi
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/usbprog.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/usbprog.cfg
new file mode 100644
index 0000000..4f04b14
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/usbprog.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Embedded Projects USBprog
+#
+# http://embedded-projects.net/index.php?page_id=135
+#
+
+adapter driver usbprog
+# USBprog is broken w/short TMS sequences, this is a workaround
+# until the C code can be fixed.
+tms_sequence long
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/vdebug.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/vdebug.cfg
new file mode 100644
index 0000000..63a5955
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/vdebug.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+
+if { [info exists VDEBUGHOST] } {
+	set _VDEBUGHOST $VDEBUGHOST
+} else {
+	set _VDEBUGHOST localhost
+}
+if { [info exists VDEBUGPORT] } {
+	set _VDEBUGPORT $VDEBUGPORT
+} else {
+	set _VDEBUGPORT 8192
+}
+
+adapter driver vdebug
+# vdebug server:port
+vdebug server $_VDEBUGHOST:$_VDEBUGPORT
+
+# example config debug level and log
+#debug_level 3
+#log_output vd_ocd.log
+
+# example config listen on all interfaces, disable tcl/telnet server
+bindto 0.0.0.0
+#gdb port 3333
+#telnet port disabled
+tcl port disabled
+
+# transaction batching: 0 - no batching, 1 - (default) wr, 2 - rw
+vdebug batching 1
+
+# Polling values
+vdebug polling 100 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/vsllink.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/vsllink.cfg
new file mode 100644
index 0000000..f780c89
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/vsllink.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Versaloon Link -- VSLLink
+#
+# http://www.versaloon.com/
+#
+
+adapter driver vsllink
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/xds110.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/xds110.cfg
new file mode 100644
index 0000000..aff0f38
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/interface/xds110.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments XDS110
+#
+# http://processors.wiki.ti.com/index.php/XDS110
+# http://processors.wiki.ti.com/index.php/Emulation_Software_Package#XDS110_Support_Utilities
+#
+
+adapter driver xds110
+
+# Use serial number option to use a specific XDS110
+# when more than one are connected to the host.
+# adapter serial 00000000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/mem_helper.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/mem_helper.tcl
new file mode 100644
index 0000000..0229d54
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/mem_helper.tcl
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Helper for common memory read/modify/write procedures
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+	return [read_memory $reg 32 1]
+}
+
+add_usage_text mrw "address"
+add_help_text mrw "Returns value of word in memory."
+
+# mrh: "memory read halfword", returns value of $reg
+proc mrh {reg} {
+	return [read_memory $reg 16 1]
+}
+
+add_usage_text mrh "address"
+add_help_text mrh "Returns value of halfword in memory."
+
+# mrb: "memory read byte", returns value of $reg
+proc mrb {reg} {
+	return [read_memory $reg 8 1]
+}
+
+add_usage_text mrb "address"
+add_help_text mrb "Returns value of byte in memory."
+
+# mmw: "memory modify word", updates value of $reg
+#       $reg <== ((value & ~$clearbits) | $setbits)
+proc mmw {reg setbits clearbits} {
+	set old [mrw $reg]
+	set new [expr {($old & ~$clearbits) | $setbits}]
+	mww $reg $new
+}
+
+add_usage_text mmw "address setbits clearbits"
+add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/memory.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/memory.tcl
new file mode 100644
index 0000000..8b93b51
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/memory.tcl
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MEMORY
+#
+# All Memory regions have two components.
+#    (1) A count of regions, in the form N_NAME
+#    (2) An array within info about each region.
+#
+# The ARRAY
+#
+#       (  RegionNumber ,  ATTRIBUTE )
+#
+# Where  is one of:
+#
+#     N_FLASH  & FLASH   (internal memory)
+#     N_RAM    & RAM     (internal memory)
+#     N_MMREGS & MMREGS  (for memory mapped registers)
+#     N_XMEM   & XMEM    (off chip memory, ie: flash on cs0, sdram on cs2)
+# or  N_UNKNOWN & UNKNOWN for things that do not exist.
+#
+# We have 1 unknown region.
+set N_UNKNOWN 1
+# All MEMORY regions must have these attributes
+#     CS          - chip select (if internal, use -1)
+set UNKNOWN(0,CHIPSELECT) -1
+#     BASE        - base address in memory
+set UNKNOWN(0,BASE)       0
+#     LEN         - length in bytes
+set UNKNOWN(0,LEN)        $CPU_MAX_ADDRESS
+#     HUMAN       - human name of the region
+set UNKNOWN(0,HUMAN) "unknown"
+#     TYPE        - one of:
+#                       flash, ram, mmr, unknown
+#                    For harvard arch:
+#                       iflash, dflash, iram, dram
+set UNKNOWN(0,TYPE)       "unknown"
+#     RWX         - access ablity
+#                       unix style chmod bits
+#                           0 - no access
+#                           1 - execute
+#                           2 - write
+#                           4 - read
+#                       hence: 7 - readwrite execute
+set RWX_NO_ACCESS     0
+set RWX_X_ONLY        $BIT0
+set RWX_W_ONLY        $BIT1
+set RWX_R_ONLY        $BIT2
+set RWX_RW            [expr {$RWX_R_ONLY + $RWX_W_ONLY}]
+set RWX_R_X           [expr {$RWX_R_ONLY + $RWX_X_ONLY}]
+set RWX_RWX           [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}]
+set UNKNOWN(0,RWX)     $RWX_NO_ACCESS
+
+#     WIDTH       - access width
+#                      8,16,32 [0 means ANY]
+set ACCESS_WIDTH_NONE 0
+set ACCESS_WIDTH_8    $BIT0
+set ACCESS_WIDTH_16   $BIT1
+set ACCESS_WIDTH_32   $BIT2
+set ACCESS_WIDTH_ANY  [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}]
+set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
+
+proc iswithin { ADDRESS BASE LEN } {
+    return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]
+}
+
+proc address_info { ADDRESS } {
+
+    foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
+	if { [info exists $WHERE] } {
+	    set lmt [set N_[set WHERE]]
+	    for { set region 0 } { $region < $lmt } { incr region } {
+		if { [iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN)] } {
+		    return  "$WHERE $region";
+		}
+	    }
+	}
+    }
+
+    # Return the 'unknown'
+    return "UNKNOWN 0"
+}
+
+proc memread32 {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 32 1] } msg ] {
+	return $foo
+    } else {
+	error "memread32: $msg"
+    }
+}
+
+proc memread16 {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 16 1] } msg ] {
+	return $foo
+    } else {
+	error "memread16: $msg"
+    }
+}
+
+proc memread8 {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 8 1] } msg ] {
+	return $foo
+    } else {
+	error "memread8: $msg"
+    }
+}
+
+proc memwrite32 {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 32 $DATA } msg ] {
+	return $DATA
+    } else {
+	error "memwrite32: $msg"
+    }
+}
+
+proc memwrite16 {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 16 $DATA } msg ] {
+	return $DATA
+    } else {
+	error "memwrite16: $msg"
+    }
+}
+
+proc memwrite8 {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 8 $DATA } msg ] {
+	return $DATA
+    } else {
+	error "memwrite8: $msg"
+    }
+}
+
+proc memread32_phys {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 32 1 phys] } msg ] {
+	return $foo
+    } else {
+	error "memread32: $msg"
+    }
+}
+
+proc memread16_phys {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 16 1 phys] } msg ] {
+	return $foo
+    } else {
+	error "memread16: $msg"
+    }
+}
+
+proc memread8_phys {ADDR} {
+    if ![ catch { set foo [read_memory $ADDR 8 1 phys] } msg ] {
+	return $foo
+    } else {
+	error "memread8: $msg"
+    }
+}
+
+proc memwrite32_phys {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 32 $DATA phys } msg ] {
+	return $DATA
+    } else {
+	error "memwrite32: $msg"
+    }
+}
+
+proc memwrite16_phys {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 16 $DATA phys } msg ] {
+	return $DATA
+    } else {
+	error "memwrite16: $msg"
+    }
+}
+
+proc memwrite8_phys {ADDR DATA} {
+    if ![ catch { write_memory $ADDR 8 $DATA phys } msg ] {
+	return $DATA
+    } else {
+	error "memwrite8: $msg"
+    }
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/mmr_helpers.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/mmr_helpers.tcl
new file mode 100644
index 0000000..5c37fcf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/mmr_helpers.tcl
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc proc_exists { NAME } {
+    set n [info commands $NAME]
+    set l [string length $n]
+    return [expr {$l != 0}]
+}
+
+# Give: REGISTER name - must be a global variable.
+proc show_mmr32_reg { NAME } {
+
+    global $NAME
+    # we want $($NAME)
+    set a [set [set NAME]]
+
+    if ![catch { set v [memread32 $a] } msg ] {
+	echo [format "%15s: (0x%08x): 0x%08x" $NAME $a $v]
+
+	# Was a helper defined?
+	set fn show_${NAME}_helper
+	if [ proc_exists $fn ] {
+	    # Then call it
+	    $fn $NAME $a $v
+	}
+	return $v;
+    } else {
+	error [format "%s (%s)" $msg $NAME ]
+    }
+}
+
+
+# Give: NAMES - an array of names accessible
+#               in the callers symbol-scope.
+#       VAL - the bits to display.
+
+proc show_mmr32_bits { NAMES VAL } {
+
+    upvar $NAMES MYNAMES
+
+    set w 5
+    foreach {IDX N} $MYNAMES {
+	set l [string length $N]
+	if { $l > $w } { set w $l }
+    }
+
+    for { set x 24 } { $x >= 0 } { incr x -8 } {
+	echo -n "  "
+	for { set y 7 } { $y >= 0 } { incr y -1 } {
+	    set s $MYNAMES([expr {$x + $y}])
+	    echo -n [format "%2d: %-*s | " [expr {$x + $y}] $w $s ]
+	}
+	echo ""
+
+	echo -n "  "
+	for { set y 7 } { $y >= 0 } { incr y -1 } {
+	    echo -n [format "    %d%*s | " [expr {!!($VAL & (1 << ($x + $y)))}] [expr {$w -1}] ""]
+	}
+	echo ""
+    }
+}
+
+
+proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } {
+    set width [expr {(($MSB - $LSB + 1) + 7) / 4}]
+    set nval [show_normalize_bitfield $VAL $MSB $LSB ]
+    set name0 [lindex $FIELDVALUES 0 ]
+    if [ string compare $name0 _NUMBER_ ] {
+	set sval [lindex $FIELDVALUES $nval]
+    } else {
+	set sval ""
+    }
+    echo [format "%-15s: %d (0x%0*x) %s" $FIELDNAME $nval $width $nval $sval ]
+}
+
+# Give: ADDR - address of the register.
+#       BIT - bit's number.
+
+proc get_mmr_bit { ADDR BIT } {
+	set val [memread32 $ADDR]
+	set bit_val [expr {$val & [expr {1 << $BIT}]}]
+	return $bit_val
+}
+
+
+# Give: ADDR - address of the register.
+#       MSB - MSB bit's number.
+#       LSB - LSB bit's number.
+
+proc get_mmr_bitfield { ADDR MSB LSB } {
+	set rval [memread32 $ADDR]
+	return normalize_bitfield $rval $MSB $LSB
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/1986Be1T.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/1986Be1T.cfg
new file mode 100644
index 0000000..a3172cc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/1986Be1T.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# 1986ВЕ1Т
+# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=236&cntnt01returnid=68
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME 1986ве1т
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      # SWD IDCODE
+      set _CPUTAPID 0x2ba01477
+   }
+}
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# use AHB-Lite SRAM for work area
+$_TARGETNAME configure -work-area-phys 0x20100000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# can't handle overlapping memory regions
+if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
+   flash bank ${_CHIPNAME}_info.flash mdr 0x00000000 0x01000 0 0 $_TARGETNAME 1 1 4
+} else {
+   flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 0 0 $_TARGETNAME 0 32 4
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/K1879x61R.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/K1879x61R.cfg
new file mode 100644
index 0000000..8dd330d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/K1879x61R.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# СБИС К1879ХБ1Я
+# http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/
+
+adapter speed 1000
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME к1879хб1я
+}
+
+if { [info exists ENDIAN] } {
+    set _ENDIAN $ENDIAN
+} else {
+    set _ENDIAN little
+}
+
+if { [info exists DSP_TAPID] } {
+    set _DSP_TAPID $DSP_TAPID
+} else {
+    set _DSP_TAPID 0x2b900f0f
+}
+
+jtag newtap $_CHIPNAME dsp -irlen 4 -expected-id $_DSP_TAPID
+
+if { [info exists CPU_TAPID] } {
+    set _CPU_TAPID $CPU_TAPID
+} else {
+    set _CPU_TAPID 0x07b76f0f
+}
+
+jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
+
+set _TARGETNAME $_CHIPNAME.arm
+target create $_TARGETNAME arm11 -chain-position $_CHIPNAME.arm
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/adsp-sc58x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/adsp-sc58x.cfg
new file mode 100644
index 0000000..3dcfc91
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/adsp-sc58x.cfg
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Analog Devices ADSP-SC58x (ARM Cortex-A5 plus one or two SHARC+ DSPs)
+#
+
+# Evaluation boards by Analog Devices (and designs derived from them) use a
+# non-standard 10-pin 0.05" ARM Cortex Debug Connector.  In this bastardized
+# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST.
+#
+# As a result, a standards-compliant debug pod will force /TRST active,
+# putting the processor's debug interface into reset and preventing usage.
+#
+# A connector adapter must be employed on these boards to isolate or remap
+# /TRST so that it is only asserted when intended.
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ADSP-SC58x
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x3BA02477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create ap0.mem mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -event examine-end {
+   global _TARGETNAME
+   sc58x_enabledebug
+}
+
+proc sc58x_enabledebug {} {
+   # Enable debugging functionality by setting bits in the TAPC_DBGCTL register
+   # it is not possible to halt the target unless these bits have been set
+   ap0.mem mww 0x31131000 0xFFFF
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/aduc702x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/aduc702x.cfg
new file mode 100644
index 0000000..c903710
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/aduc702x.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME aduc702x
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   # This config file was defaulting to big endian..
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+## JTAG scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+##
+## Target configuration
+##
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# allocate the entire SRAM as working area
+$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
+
+## flash configuration
+# only target number is needed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
+
+## If you use the watchdog, the following code makes sure that the board
+## doesn't reboot when halted via JTAG.  Yes, on the older generation
+## AdUC702x, timer3 continues running even when the CPU is halted.
+
+proc watchdog_service {} {
+    global watchdog_hdl
+    mww 0xffff036c 0
+#    echo "watchdog!!"
+    set watchdog_hdl [after 500 watchdog_service]
+}
+
+$_TARGETNAME configure -event reset-halt-post {  watchdog_service }
+$_TARGETNAME configure -event resume-start { global watchdog_hdl; after cancel $watchdog_hdl }
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/aducm360.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/aducm360.cfg
new file mode 100644
index 0000000..5cfb483
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/aducm360.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# This file was created using as references the stm32f1x.cfg and aduc702x.cfg
+#
+source [find target/swj-dp.tcl]
+
+# Chip name
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME aducm360
+}
+
+# Endianness
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# Eventually, the whole SRAM of ADuCM360 will be used (8kB)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x2000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# SWD/JTAG speed
+adapter speed 1000
+
+##
+## Target configuration
+##
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# allocate the working area
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME
+
+adapter srst delay 100
+
+cortex_m reset_config sysresetreq
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/allwinner_v3s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/allwinner_v3s.cfg
new file mode 100644
index 0000000..6c3435e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/allwinner_v3s.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the config for an Allwinner V3/V3s (sun8iw8).
+#
+# Notes:
+# - Single core ARM Cortex-A7 with a maximum frequency of 1.2 GHz.
+# - Thumb-2 Technology
+# - Support NEON Advanced SIMD(Single Instruction Multiple Data)instruction
+#   for acceleration of media and signal processing functions
+# - Support Large Physical Address Extensions(LPAE)
+# - VFPv4 Floating Point Unit
+# - 32KB L1 Instruction cache and 32KB L1 Data cache
+# - 128KB L2 cache
+# - has some integrated DDR2 RAM.
+#
+# Pins related for debug and bootstrap:
+#   JTAG
+# JTAG_TMS	PF0, SDC0_D1
+# JTAG_TDI	PF1, SDC0_D0
+# JTAG_TDO	PF3, SDC0_CMD
+# JTAG_TCK	PF5, SDC0_D2
+#   UART
+# None of UART ports seems to be enabled by ROM.
+# UART0_TX	PF2, SDC0_CLK		Per default disabled
+# UART0_RX	PF4, SDC0_D3 		Per default disabled
+# UART1_TX	PE21			Per default disabled
+# UART1_RX	PE22	 		Per default disabled
+# UART2_TX	PB0			Per default disabled
+# UART2_RX	PB1	 		Per default disabled
+#
+# JTAG is enabled by default after power-on on listed JTAG_* pins. So far the
+# boot sequence is:
+# Time		Action
+# 0000ms	Power ON
+# 0200ms	JTAG enabled
+# 0220ms	JTAG pins switched to SD mode
+#
+# The time frame of 20ms can be not enough to init and halt the CPU. In this
+# case I would recommend to set: "adapter speed 15000"
+# To get more or less precise timings, the board should provide reset pin,
+# or some bench power supply with remote function. In my case I used
+# EEZ H24005 with this command to power on and halt the target:
+# "exec  echo "*TRG" > /dev/ttyACM0; sleep 220; reset halt"
+# After this it is possible to enable JTAG mode again from boot loader or OS.
+# Following DAPs are available:
+# dap[0]->MEM-AP AHB
+# dap[1]->MEM-AP APB->CA7[0]
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME v3s
+}
+
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+# No NRST or SRST is present on the SoC. Boards may provide
+# some sort of Power cycle reset for complete board or SoC.
+# For this case we provide srst_pulls_trst so the board config
+# only needs to set srst_only.
+reset_config none srst_pulls_trst
+
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# Add Cortex A7 core
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/alphascale_asm9260t.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/alphascale_asm9260t.cfg
new file mode 100644
index 0000000..735555e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/alphascale_asm9260t.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME asm9260t
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x079264F3
+}
+
+# And srst_pulls_trst by chip design.
+reset_config srst_pulls_trst
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/altera_fpgasoc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/altera_fpgasoc.cfg
new file mode 100644
index 0000000..a98b346
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/altera_fpgasoc.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Altera cyclone V SoC family, 5Cxxx
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME fpgasoc
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# Subsidiary TAP: fpga
+if { [info exists FPGA_TAPID] } {
+   set _FPGA_TAPID $FPGA_TAPID
+} else {
+   set _FPGA_TAPID 0x02d020dd
+}
+jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID
+
+
+#
+# Cortex-A9 target
+#
+
+# GDB target: Cortex-A9, using DAP, configuring only one core
+# Base addresses of cores:
+# core 0  -  0x80110000
+# core 1  -  0x80112000
+
+# Slow speed to be sure it will work
+adapter speed 1000
+
+set _TARGETNAME1 $_CHIPNAME.cpu.0
+set _TARGETNAME2 $_CHIPNAME.cpu.1
+
+# A9 core 0
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x80110000
+
+$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
+$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
+
+
+# A9 core 1
+#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
+#        -coreid 1 -dbgbase 0x80112000
+
+#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
+#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
+
+proc cycv_dbginit {target} {
+        # General Cortex-A8/A9 debug initialisation
+        cortex_a dbginit
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/altera_fpgasoc_arria10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/altera_fpgasoc_arria10.cfg
new file mode 100644
index 0000000..fe58379
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/altera_fpgasoc_arria10.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel (Altera) Arria10 FPGA SoC
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME arria10
+}
+
+# ARM CoreSight Debug Access Port (dap HPS)
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID
+
+# Subsidiary TAP: fpga (tap)
+# See Intel Arria 10 Handbook
+# https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
+# Intel Arria 10 GX 160  0x02ee20dd
+# Intel Arria 10 GX 220  0x02e220dd
+# Intel Arria 10 GX 270  0x02ee30dd
+# Intel Arria 10 GX 320  0x02e230dd
+# Intel Arria 10 GX 480  0x02e240dd
+# Intel Arria 10 GX 570  0x02ee50dd
+# Intel Arria 10 GX 660  0x02e250dd
+# Intel Arria 10 GX 900  0x02ee60dd
+# Intel Arria 10 GX 1150 0x02e660dd
+# Intel Arria 10 GT 900  0x02e260dd
+# Intel Arria 10 GT 1150 0x02e060dd
+# Intel Arria 10 SX 160  0x02e620dd
+# Intel Arria 10 SX 220  0x02e020dd
+# Intel Arria 10 SX 270  0x02e630dd
+# Intel Arria 10 SX 320  0x02e030dd
+# Intel Arria 10 SX 480  0x02e040dd
+# Intel Arria 10 SX 570  0x02e650dd
+# Intel Arria 10 SX 660  0x02e050dd
+jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \
+	-expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \
+	-expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \
+	-expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \
+	-expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \
+	-expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \
+	-expected-id 0x02e050dd
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+#
+# Cortex-A9 target
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0
+target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \
+	-defer-examine
+target smp $_TARGETNAME.0 $_TARGETNAME.1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/am335x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/am335x.cfg
new file mode 100644
index 0000000..208ebf5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/am335x.cfg
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/icepick.cfg]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME am335x
+}
+
+# set the taps to be enabled by default. this can be overridden
+# by setting DEFAULT_TAPS in a separate configuration file
+# or directly on the command line.
+if { [info exists DEFAULT_TAPS] } {
+	set _DEFAULT_TAPS "$DEFAULT_TAPS"
+} else {
+	set _DEFAULT_TAPS "$_CHIPNAME.tap"
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+#
+# M3 DAP
+#
+if { [info exists M3_DAP_TAPID] } {
+	set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+	set _M3_DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m3_tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
+dap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap
+
+#
+# ICEpick-D (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID 0x0b94402f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+jtag configure $_CHIPNAME.jrc -event setup {
+	global _DEFAULT_TAPS
+	enable_default_taps $_DEFAULT_TAPS
+}
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+#
+# helper function that enables all taps passed as argument
+#
+proc enable_default_taps { taps } {
+	foreach tap $taps {
+		jtag tapenable $tap
+	}
+}
+
+#
+# Cortex-M3 target
+#
+set _TARGETNAME_2 $_CHIPNAME.m3
+target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap
+
+#
+# Cortex-A8 target
+#
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000
+
+# SRAM: 64K at 0x4030.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
+
+
+# when putting the target into 'reset halt', we need to disable the watchdog as
+# it would otherwise trigger while we're in JTAG
+# FIXME: unify with target/am437x.cfg
+source [find mem_helper.tcl]
+set  WDT1_BASE_ADDR                  0x44e35000
+set  WDT1_W_PEND_WSPR                [expr       {$WDT1_BASE_ADDR     +  0x0034}]
+set  WDT1_WSPR                       [expr       {$WDT1_BASE_ADDR     +  0x0048}]
+proc disable_watchdog { } {
+	global WDT1_WSPR
+	global WDT1_W_PEND_WSPR
+	global _TARGETNAME
+
+	set curstate [$_TARGETNAME curstate]
+
+	if { [string compare $curstate halted] == 0 } {
+		set WDT_DISABLE_SEQ1	0xaaaa
+		set WDT_DISABLE_SEQ2	0x5555
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
+
+		# Empty body to make sure this executes as fast as possible.
+		# We don't want any delays here otherwise romcode might start
+		# executing and end up changing state of certain IPs.
+		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
+		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
+	}
+}
+$_TARGETNAME configure -event reset-end { disable_watchdog }
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/am437x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/am437x.cfg
new file mode 100644
index 0000000..5350927
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/am437x.cfg
@@ -0,0 +1,1003 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/icepick.cfg]
+source [find mem_helper.tcl]
+
+###############################################################################
+##				AM437x Registers			     ##
+###############################################################################
+set  PRCM_BASE_ADDR                  0x44df0000
+set  REVISION_PRM                    [expr       {$PRCM_BASE_ADDR     +  0x0000}]
+set  PRM_IRQSTATUS_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0004}]
+set  PRM_IRQENABLE_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0008}]
+set  PRM_IRQSTATUS_M3                [expr       {$PRCM_BASE_ADDR     +  0x000c}]
+set  PRM_IRQENABLE_M3                [expr       {$PRCM_BASE_ADDR     +  0x0010}]
+set  PM_MPU_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0300}]
+set  PM_MPU_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0304}]
+set  RM_MPU_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0314}]
+set  RM_MPU_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0324}]
+set  PM_GFX_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0400}]
+set  PM_GFX_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0404}]
+set  RM_GFX_RSTCTRL                  [expr       {$PRCM_BASE_ADDR     +  0x0410}]
+set  RM_GFX_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0414}]
+set  RM_GFX_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0424}]
+set  RM_RTC_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0524}]
+set  RM_WKUP_RSTCTRL                 [expr       {$PRCM_BASE_ADDR     +  0x2010}]
+set  RM_WKUP_RSTST                   [expr       {$PRCM_BASE_ADDR     +  0x2014}]
+set  CM_L3_AON_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x2800}]
+set  CM_WKUP_DEBUGSS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2820}]
+set  CM_L3S_TSC_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2900}]
+set  CM_WKUP_ADC_TSC_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2920}]
+set  CM_L4_WKUP_AON_CLKSTCTRL        [expr       {$PRCM_BASE_ADDR     +  0x2a00}]
+set  CM_WKUP_L4WKUP_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2a20}]
+set  CM_WKUP_WKUP_M3_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a28}]
+set  CM_WKUP_SYNCTIMER_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a30}]
+set  CM_WKUP_CLKDIV32K_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a38}]
+set  CM_WKUP_USBPHY0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a40}]
+set  CM_WKUP_USBPHY1_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a48}]
+set  CM_WKUP_CLKSTCTRL               [expr       {$PRCM_BASE_ADDR     +  0x2b00}]
+set  CM_WKUP_TIMER0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b20}]
+set  CM_WKUP_TIMER1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b28}]
+set  CM_WKUP_WDT0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b30}]
+set  CM_WKUP_WDT1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b38}]
+set  CM_WKUP_I2C0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b40}]
+set  CM_WKUP_UART0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b48}]
+set  CM_WKUP_SMARTREFLEX0_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b50}]
+set  CM_WKUP_SMARTREFLEX1_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b58}]
+set  CM_WKUP_CONTROL_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2b60}]
+set  CM_WKUP_GPIO0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b68}]
+set  CM_CLKMODE_DPLL_CORE            [expr       {$PRCM_BASE_ADDR     +  0x2d20}]
+set  CM_IDLEST_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d24}]
+set  CM_CLKSEL_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d2c}]
+set  CM_DIV_M4_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d38}]
+set  CM_DIV_M5_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d3c}]
+set  CM_DIV_M6_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d40}]
+set  CM_SSC_DELTAMSTEP_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d48}]
+set  CM_SSC_MODFREQDIV_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d4c}]
+set  CM_CLKMODE_DPLL_MPU             [expr       {$PRCM_BASE_ADDR     +  0x2d60}]
+set  CM_IDLEST_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d64}]
+set  CM_CLKSEL_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d6c}]
+set  CM_DIV_M2_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d70}]
+set  CM_SSC_DELTAMSTEP_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d88}]
+set  CM_SSC_MODFREQDIV_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d8c}]
+set  CM_CLKMODE_DPLL_DDR             [expr       {$PRCM_BASE_ADDR     +  0x2da0}]
+set  CM_IDLEST_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2da4}]
+set  CM_CLKSEL_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2dac}]
+set  CM_DIV_M2_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db0}]
+set  CM_DIV_M4_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db8}]
+set  CM_SSC_DELTAMSTEP_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dc8}]
+set  CM_SSC_MODFREQDIV_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dcc}]
+set  CM_CLKMODE_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2de0}]
+set  CM_IDLEST_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2de4}]
+set  CM_CLKSEL_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2dec}]
+set  CM_DIV_M2_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2df0}]
+set  CM_CLKSEL2_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2e04}]
+set  CM_SSC_DELTAMSTEP_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e08}]
+set  CM_SSC_MODFREQDIV_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e0c}]
+set  CM_CLKDCOLDO_DPLL_PER           [expr       {$PRCM_BASE_ADDR     +  0x2e14}]
+set  CM_CLKMODE_DPLL_DISP            [expr       {$PRCM_BASE_ADDR     +  0x2e20}]
+set  CM_IDLEST_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e24}]
+set  CM_CLKSEL_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e2c}]
+set  CM_DIV_M2_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e30}]
+set  CM_SSC_DELTAMSTEP_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e48}]
+set  CM_SSC_MODFREQDIV_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e4c}]
+set  CM_CLKMODE_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e60}]
+set  CM_IDLEST_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e64}]
+set  CM_CLKSEL_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e6c}]
+set  CM_DIV_M2_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e70}]
+set  CM_CLKSEL2_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e84}]
+set  CM_SSC_DELTAMSTEP_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e88}]
+set  CM_SSC_MODFREQDIV_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e8c}]
+set  CM_SHADOW_FREQ_CONFIG1          [expr       {$PRCM_BASE_ADDR     +  0x2fa0}]
+set  CM_SHADOW_FREQ_CONFIG2          [expr       {$PRCM_BASE_ADDR     +  0x2fa4}]
+set  CM_CLKOUT1_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4100}]
+set  CM_DLL_CTRL                     [expr       {$PRCM_BASE_ADDR     +  0x4104}]
+set  CM_CLKOUT2_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4108}]
+set  CLKSEL_TIMER1MS_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4200}]
+set  CLKSEL_TIMER2_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4204}]
+set  CLKSEL_TIMER3_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4208}]
+set  CLKSEL_TIMER4_CLK               [expr       {$PRCM_BASE_ADDR     +  0x420c}]
+set  CLKSEL_TIMER5_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4210}]
+set  CLKSEL_TIMER6_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4214}]
+set  CLKSEL_TIMER7_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4218}]
+set  CLKSEL_TIMER8_CLK               [expr       {$PRCM_BASE_ADDR     +  0x421c}]
+set  CLKSEL_TIMER9_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4220}]
+set  CLKSEL_TIMER10_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4224}]
+set  CLKSEL_TIMER11_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4228}]
+set  CLKSEL_WDT1_CLK                 [expr       {$PRCM_BASE_ADDR     +  0x422c}]
+set  CLKSEL_SYNCTIMER_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4230}]
+set  CLKSEL_MAC_CLK                  [expr       {$PRCM_BASE_ADDR     +  0x4234}]
+set  CLKSEL_CPTS_RFT_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4238}]
+set  CLKSEL_GFX_FCLK                 [expr       {$PRCM_BASE_ADDR     +  0x423c}]
+set  CLKSEL_GPIO0_DBCLK              [expr       {$PRCM_BASE_ADDR     +  0x4240}]
+set  CLKSEL_LCDC_PIXEL_CLK           [expr       {$PRCM_BASE_ADDR     +  0x4244}]
+set  CLKSEL_ICSS_OCP_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4248}]
+set  CLKSEL_DLL_AGING_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4250}]
+set  CLKSEL_USBPHY32KHZ_GCLK         [expr       {$PRCM_BASE_ADDR     +  0x4260}]
+set  CM_MPU_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8300}]
+set  CM_MPU_MPU_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8320}]
+set  CM_GFX_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8400}]
+set  CM_GFX_GFX_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8420}]
+set  CM_RTC_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8500}]
+set  CM_RTC_RTC_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8520}]
+set  CM_PER_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8800}]
+set  CM_PER_L3_CLKCTRL               [expr       {$PRCM_BASE_ADDR     +  0x8820}]
+set  CM_PER_AES0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8828}]
+set  CM_PER_DES_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8830}]
+set  CM_PER_CRYPTODMA_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8838}]
+set  CM_PER_L3_INSTR_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8840}]
+set  CM_PER_MSTR_EXPS_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8848}]
+set  CM_PER_OCMCRAM_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8850}]
+set  CM_PER_SHA0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8858}]
+set  CM_PER_SLV_EXPS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8860}]
+set  CM_PER_VPFE0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8868}]
+set  CM_PER_VPFE1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8870}]
+set  CM_PER_TPCC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8878}]
+set  CM_PER_TPTC0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8880}]
+set  CM_PER_TPTC1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8888}]
+set  CM_PER_TPTC2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8890}]
+set  CM_PER_DLL_AGING_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8898}]
+set  CM_PER_L4HS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a0}]
+set  CM_PER_L4FW_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a8}]
+set  CM_PER_L3S_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8a00}]
+set  CM_PER_GPMC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a20}]
+set  CM_PER_IEEE5000_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8a28}]
+set  CM_PER_MCASP0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a38}]
+set  CM_PER_MCASP1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a40}]
+set  CM_PER_MMC2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a48}]
+set  CM_PER_QSPI_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a58}]
+set  CM_PER_USB_OTG_SS0_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a60}]
+set  CM_PER_USB_OTG_SS1_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a68}]
+set  CM_PER_ICSS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8b00}]
+set  CM_PER_ICSS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8b20}]
+set  CM_PER_L4LS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8c00}]
+set  CM_PER_L4LS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8c20}]
+set  CM_PER_DCAN0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c28}]
+set  CM_PER_DCAN1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c30}]
+set  CM_PER_EPWMSS0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c38}]
+set  CM_PER_EPWMSS1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c40}]
+set  CM_PER_EPWMSS2_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c48}]
+set  CM_PER_EPWMSS3_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c50}]
+set  CM_PER_EPWMSS4_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c58}]
+set  CM_PER_EPWMSS5_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c60}]
+set  CM_PER_ELM_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8c68}]
+set  CM_PER_GPIO1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c78}]
+set  CM_PER_GPIO2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c80}]
+set  CM_PER_GPIO3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c88}]
+set  CM_PER_GPIO4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c90}]
+set  CM_PER_GPIO5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c98}]
+set  CM_PER_HDQ1W_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8ca0}]
+set  CM_PER_I2C1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8ca8}]
+set  CM_PER_I2C2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cb0}]
+set  CM_PER_MAILBOX0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8cb8}]
+set  CM_PER_MMC0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc0}]
+set  CM_PER_MMC1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc8}]
+set  CM_PER_PKA_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8cd0}]
+set  CM_PER_RNG_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8ce0}]
+set  CM_PER_SPARE0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8ce8}]
+set  CM_PER_SPARE1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8cf0}]
+set  CM_PER_SPI0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d00}]
+set  CM_PER_SPI1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d08}]
+set  CM_PER_SPI2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d10}]
+set  CM_PER_SPI3_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d18}]
+set  CM_PER_SPI4_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d20}]
+set  CM_PER_SPINLOCK_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8d28}]
+set  CM_PER_TIMER2_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d30}]
+set  CM_PER_TIMER3_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d38}]
+set  CM_PER_TIMER4_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d40}]
+set  CM_PER_TIMER5_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d48}]
+set  CM_PER_TIMER6_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d50}]
+set  CM_PER_TIMER7_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d58}]
+set  CM_PER_TIMER8_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d60}]
+set  CM_PER_TIMER9_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d68}]
+set  CM_PER_TIMER10_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d70}]
+set  CM_PER_TIMER11_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d78}]
+set  CM_PER_UART1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d80}]
+set  CM_PER_UART2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d88}]
+set  CM_PER_UART3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d90}]
+set  CM_PER_UART4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d98}]
+set  CM_PER_UART5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8da0}]
+set  CM_PER_USBPHYOCP2SCP0_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8db8}]
+set  CM_PER_USBPHYOCP2SCP1_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8dc0}]
+set  CM_PER_EMIF_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8f00}]
+set  CM_PER_EMIF_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8f20}]
+set  CM_PER_DLL_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8f28}]
+set  CM_PER_EMIF_FW_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8f30}]
+set  CM_PER_OTFA_EMIF_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8f38}]
+set  CM_PER_DSS_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9200}]
+set  CM_PER_DSS_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x9220}]
+set  CM_PER_CPSW_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x9300}]
+set  CM_PER_CPGMAC0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x9320}]
+set  CM_PER_OCPWP_L3_CLKSTCTRL       [expr       {$PRCM_BASE_ADDR     +  0x9400}]
+set  CM_PER_OCPWP_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9420}]
+
+set  CONTROL_BASE_ADDR               0x44e10000
+set  CONTROL_STATUS                  [expr       {$CONTROL_BASE_ADDR  +  0x0040}]
+set  DEVICE_ID                       [expr       {$CONTROL_BASE_ADDR  +  0x0600}]
+set  DEV_FEATURE                     [expr       {$CONTROL_BASE_ADDR  +  0x0604}]
+set  DEV_ATTRIBUTE                   [expr       {$CONTROL_BASE_ADDR  +  0x0610}]
+set  MAC_ID0_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0630}]
+set  MAC_ID0_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x0634}]
+set  MAC_ID1_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0638}]
+set  MAC_ID1_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x063c}]
+set  USB_VID_PID                     [expr       {$CONTROL_BASE_ADDR  +  0x07f4}]
+set  CONTROL_CONF_ECAP0_IN_PWM0_OUT  [expr       {$CONTROL_BASE_ADDR  +  0x0964}]
+set  CONTROL_CONF_SPI4_CS0           [expr       {$CONTROL_BASE_ADDR  +  0x0a5c}]
+set  CONTROL_CONF_SPI2_SCLK          [expr       {$CONTROL_BASE_ADDR  +  0x0a60}]
+set  CONTROL_CONF_SPI2_D0            [expr       {$CONTROL_BASE_ADDR  +  0x0a64}]
+set  CONTROL_CONF_XDMA_EVENT_INTR0   [expr       {$CONTROL_BASE_ADDR  +  0x0a70}]
+set  CONTROL_CONF_XDMA_EVENT_INTR1   [expr       {$CONTROL_BASE_ADDR  +  0x0a74}]
+set  CONTROL_CONF_GPMC_A0            [expr       {$CONTROL_BASE_ADDR  +  0x0840}]
+set  DDR_IO_CTRL                     [expr       {$CONTROL_BASE_ADDR  +  0x0e04}]
+set  VTP_CTRL_REG                    [expr       {$CONTROL_BASE_ADDR  +  0x0e0c}]
+set  VREF_CTRL                       [expr       {$CONTROL_BASE_ADDR  +  0x0e14}]
+set  DDR_CKE_CTRL                    [expr       {$CONTROL_BASE_ADDR  +  0x131c}]
+set  DDR_ADDRCTRL_IOCTRL             [expr       {$CONTROL_BASE_ADDR  +  0x1404}]
+set  DDR_ADDRCTRL_WD0_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x1408}]
+set  DDR_ADDRCTRL_WD1_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x140c}]
+set  DDR_DATA0_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1440}]
+set  DDR_DATA1_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1444}]
+set  DDR_DATA2_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1448}]
+set  DDR_DATA3_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x144c}]
+set  EMIF_SDRAM_CONFIG_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1460}]
+set  EMIF_SDRAM_STATUS_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1464}]
+
+set  GPIO0_BASE_ADDR                 0x44e07000
+set  GPIO0_SYSCONFIG                 [expr       {$GPIO0_BASE_ADDR    +  0x0010}]
+set  GPIO0_SYSSTATUS                 [expr       {$GPIO0_BASE_ADDR    +  0x0114}]
+set  GPIO0_CTRL                      [expr       {$GPIO0_BASE_ADDR    +  0x0130}]
+set  GPIO0_OE                        [expr       {$GPIO0_BASE_ADDR    +  0x0134}]
+set  GPIO0_CLEARDATAOUT              [expr       {$GPIO0_BASE_ADDR    +  0x0190}]
+set  GPIO0_SETDATAOUT                [expr       {$GPIO0_BASE_ADDR    +  0x0194}]
+
+set  GPIO5_BASE_ADDR                 0x48322000
+set  GPIO5_SYSCONFIG                 [expr       {$GPIO5_BASE_ADDR    +  0x0010}]
+set  GPIO5_SYSSTATUS                 [expr       {$GPIO5_BASE_ADDR    +  0x0114}]
+set  GPIO5_CTRL                      [expr       {$GPIO5_BASE_ADDR    +  0x0130}]
+set  GPIO5_OE                        [expr       {$GPIO5_BASE_ADDR    +  0x0134}]
+set  GPIO5_CLEARDATAOUT              [expr       {$GPIO5_BASE_ADDR    +  0x0190}]
+set  GPIO5_SETDATAOUT                [expr       {$GPIO5_BASE_ADDR    +  0x0194}]
+
+set  GPIO1_BASE_ADDR                 0x4804c000
+set  GPIO1_SYSCONFIG                 [expr       {$GPIO1_BASE_ADDR    +  0x0010}]
+set  GPIO1_SYSSTATUS                 [expr       {$GPIO1_BASE_ADDR    +  0x0114}]
+set  GPIO1_CTRL                      [expr       {$GPIO1_BASE_ADDR    +  0x0130}]
+set  GPIO1_OE                        [expr       {$GPIO1_BASE_ADDR    +  0x0134}]
+set  GPIO1_CLEARDATAOUT              [expr       {$GPIO1_BASE_ADDR    +  0x0190}]
+set  GPIO1_SETDATAOUT                [expr       {$GPIO1_BASE_ADDR    +  0x0194}]
+
+set  EMIF_BASE_ADDR                  0x4c000000
+set  EMIF_STATUS                     [expr       {$EMIF_BASE_ADDR     +  0x0004}]
+set  EMIF_SDRAM_CONFIG               [expr       {$EMIF_BASE_ADDR     +  0x0008}]
+set  EMIF_SDRAM_CONFIG_2             [expr       {$EMIF_BASE_ADDR     +  0x000c}]
+set  EMIF_SDRAM_REF_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0010}]
+set  EMIF_SDRAM_REF_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0014}]
+set  EMIF_SDRAM_TIM_1                [expr       {$EMIF_BASE_ADDR     +  0x0018}]
+set  EMIF_SDRAM_TIM_1_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x001c}]
+set  EMIF_SDRAM_TIM_2                [expr       {$EMIF_BASE_ADDR     +  0x0020}]
+set  EMIF_SDRAM_TIM_2_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x0024}]
+set  EMIF_SDRAM_TIM_3                [expr       {$EMIF_BASE_ADDR     +  0x0028}]
+set  EMIF_SDRAM_TIM_3_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x002c}]
+set  EMIF_LPDDR2_NVM_TIM             [expr       {$EMIF_BASE_ADDR     +  0x0030}]
+set  EMIF_LPDDR2_NVM_TIM_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0034}]
+set  EMIF_PWR_MGMT_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x0038}]
+set  EMIF_PWR_MGMT_CTRL_SHDW         [expr       {$EMIF_BASE_ADDR     +  0x003c}]
+set  EMIF_LPDDR2_MODE_REG_DATA       [expr       {$EMIF_BASE_ADDR     +  0x0040}]
+set  EMIF_LPDDR2_MODE_REG_CFG        [expr       {$EMIF_BASE_ADDR     +  0x0050}]
+set  EMIF_OCP_CONFIG                 [expr       {$EMIF_BASE_ADDR     +  0x0054}]
+set  EMIF_OCP_CFG_VAL_1              [expr       {$EMIF_BASE_ADDR     +  0x0058}]
+set  EMIF_OCP_CFG_VAL_2              [expr       {$EMIF_BASE_ADDR     +  0x005c}]
+set  EMIF_IODFT_TLGC                 [expr       {$EMIF_BASE_ADDR     +  0x0060}]
+set  EMIF_IODFT_CTRL_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0064}]
+set  EMIF_IODFT_ADDR_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0068}]
+set  EMIF_IODFT_DATA_MISR_RSLT_1     [expr       {$EMIF_BASE_ADDR     +  0x006c}]
+set  EMIF_IODFT_DATA_MISR_RSLT_2     [expr       {$EMIF_BASE_ADDR     +  0x0070}]
+set  EMIF_IODFT_DATA_MISR_RSLT_3     [expr       {$EMIF_BASE_ADDR     +  0x0074}]
+set  EMIF_PERF_CNT_1                 [expr       {$EMIF_BASE_ADDR     +  0x0080}]
+set  EMIF_PERF_CNT_2                 [expr       {$EMIF_BASE_ADDR     +  0x0084}]
+set  EMIF_PERF_CNT_CFG               [expr       {$EMIF_BASE_ADDR     +  0x0088}]
+set  EMIF_PERF_CNT_SEL               [expr       {$EMIF_BASE_ADDR     +  0x008c}]
+set  EMIF_PERF_CNT_TIM               [expr       {$EMIF_BASE_ADDR     +  0x0090}]
+set  EMIF_MISC_REG                   [expr       {$EMIF_BASE_ADDR     +  0x0094}]
+set  EMIF_DLL_CALIB_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0098}]
+set  EMIF_DLL_CALIB_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x009c}]
+set  EMIF_IRQ_EOI                    [expr       {$EMIF_BASE_ADDR     +  0x00a0}]
+set  EMIF_IRQSTATUS_RAW_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00a4}]
+set  EMIF_IRQSTATUS_SYS              [expr       {$EMIF_BASE_ADDR     +  0x00ac}]
+set  EMIF_IRQENABLE_SET_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00b4}]
+set  EMIF_IRQENABLE_CLR_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00bc}]
+set  EMIF_ZQ_CONFIG                  [expr       {$EMIF_BASE_ADDR     +  0x00c8}]
+set  EMIF_TEMP_ALERT_CONFIG          [expr       {$EMIF_BASE_ADDR     +  0x00cc}]
+set  EMIF_OCP_ERR_LOG                [expr       {$EMIF_BASE_ADDR     +  0x00d0}]
+set  EMIF_RDWR_LVL_RMP_WIN           [expr       {$EMIF_BASE_ADDR     +  0x00d4}]
+set  EMIF_RDWR_LVL_RMP_CTRL          [expr       {$EMIF_BASE_ADDR     +  0x00d8}]
+set  EMIF_RDWR_LVL_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x00dc}]
+set  EMIF_DDR_PHY_CTRL_1             [expr       {$EMIF_BASE_ADDR     +  0x00e4}]
+set  EMIF_DDR_PHY_CTRL_1_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x00e8}]
+set  EMIF_DDR_PHY_CTRL_2             [expr       {$EMIF_BASE_ADDR     +  0x00ec}]
+set  EMIF_PRI_COS_MAP                [expr       {$EMIF_BASE_ADDR     +  0x0100}]
+set  EMIF_CONNID_COS_1_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0104}]
+set  EMIF_CONNID_COS_2_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0108}]
+set  ECC_CTRL                        [expr       {$EMIF_BASE_ADDR     +  0x0110}]
+set  ECC_ADDR_RNG_1                  [expr       {$EMIF_BASE_ADDR     +  0x0114}]
+set  ECC_ADDR_RNG_2                  [expr       {$EMIF_BASE_ADDR     +  0x0118}]
+set  EMIF_RD_WR_EXEC_THRSH           [expr       {$EMIF_BASE_ADDR     +  0x0120}]
+set  COS_CONFIG                      [expr       {$EMIF_BASE_ADDR     +  0x0124}]
+
+set  PHY_STATUS_1                    [expr       {$EMIF_BASE_ADDR     +  0x0144}]
+set  PHY_STATUS_2                    [expr       {$EMIF_BASE_ADDR     +  0x0148}]
+set  PHY_STATUS_3                    [expr       {$EMIF_BASE_ADDR     +  0x014c}]
+set  PHY_STATUS_4                    [expr       {$EMIF_BASE_ADDR     +  0x0150}]
+set  PHY_STATUS_5                    [expr       {$EMIF_BASE_ADDR     +  0x0154}]
+set  PHY_STATUS_6                    [expr       {$EMIF_BASE_ADDR     +  0x0158}]
+set  PHY_STATUS_7                    [expr       {$EMIF_BASE_ADDR     +  0x015c}]
+set  PHY_STATUS_8                    [expr       {$EMIF_BASE_ADDR     +  0x0160}]
+set  PHY_STATUS_9                    [expr       {$EMIF_BASE_ADDR     +  0x0164}]
+set  PHY_STATUS_10                   [expr       {$EMIF_BASE_ADDR     +  0x0168}]
+set  PHY_STATUS_11                   [expr       {$EMIF_BASE_ADDR     +  0x016c}]
+set  PHY_STATUS_12                   [expr       {$EMIF_BASE_ADDR     +  0x0170}]
+set  PHY_STATUS_13                   [expr       {$EMIF_BASE_ADDR     +  0x0174}]
+set  PHY_STATUS_14                   [expr       {$EMIF_BASE_ADDR     +  0x0178}]
+set  PHY_STATUS_15                   [expr       {$EMIF_BASE_ADDR     +  0x017c}]
+set  PHY_STATUS_16                   [expr       {$EMIF_BASE_ADDR     +  0x0180}]
+set  PHY_STATUS_17                   [expr       {$EMIF_BASE_ADDR     +  0x0184}]
+set  PHY_STATUS_18                   [expr       {$EMIF_BASE_ADDR     +  0x0188}]
+set  PHY_STATUS_19                   [expr       {$EMIF_BASE_ADDR     +  0x018c}]
+set  PHY_STATUS_20                   [expr       {$EMIF_BASE_ADDR     +  0x0190}]
+set  PHY_STATUS_21                   [expr       {$EMIF_BASE_ADDR     +  0x0194}]
+set  PHY_STATUS_22                   [expr       {$EMIF_BASE_ADDR     +  0x0198}]
+set  PHY_STATUS_23                   [expr       {$EMIF_BASE_ADDR     +  0x019c}]
+set  PHY_STATUS_24                   [expr       {$EMIF_BASE_ADDR     +  0x01a0}]
+set  PHY_STATUS_25                   [expr       {$EMIF_BASE_ADDR     +  0x01a4}]
+set  PHY_STATUS_26                   [expr       {$EMIF_BASE_ADDR     +  0x01a8}]
+set  PHY_STATUS_27                   [expr       {$EMIF_BASE_ADDR     +  0x01ac}]
+set  PHY_STATUS_28                   [expr       {$EMIF_BASE_ADDR     +  0x01b0}]
+
+set  EXT_PHY_CTRL_1                  [expr       {$EMIF_BASE_ADDR     +  0x0200}]
+set  EXT_PHY_CTRL_1_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0204}]
+set  EXT_PHY_CTRL_2                  [expr       {$EMIF_BASE_ADDR     +  0x0208}]
+set  EXT_PHY_CTRL_2_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x020c}]
+set  EXT_PHY_CTRL_3                  [expr       {$EMIF_BASE_ADDR     +  0x0210}]
+set  EXT_PHY_CTRL_3_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0214}]
+set  EXT_PHY_CTRL_4                  [expr       {$EMIF_BASE_ADDR     +  0x0218}]
+set  EXT_PHY_CTRL_4_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x021c}]
+set  EXT_PHY_CTRL_5                  [expr       {$EMIF_BASE_ADDR     +  0x0220}]
+set  EXT_PHY_CTRL_5_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0224}]
+set  EXT_PHY_CTRL_6                  [expr       {$EMIF_BASE_ADDR     +  0x0228}]
+set  EXT_PHY_CTRL_6_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x022c}]
+set  EXT_PHY_CTRL_7                  [expr       {$EMIF_BASE_ADDR     +  0x0230}]
+set  EXT_PHY_CTRL_7_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0234}]
+set  EXT_PHY_CTRL_8                  [expr       {$EMIF_BASE_ADDR     +  0x0238}]
+set  EXT_PHY_CTRL_8_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x023c}]
+set  EXT_PHY_CTRL_9                  [expr       {$EMIF_BASE_ADDR     +  0x0240}]
+set  EXT_PHY_CTRL_9_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0244}]
+set  EXT_PHY_CTRL_10                 [expr       {$EMIF_BASE_ADDR     +  0x0248}]
+set  EXT_PHY_CTRL_10_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x024c}]
+set  EXT_PHY_CTRL_11                 [expr       {$EMIF_BASE_ADDR     +  0x0250}]
+set  EXT_PHY_CTRL_11_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0254}]
+set  EXT_PHY_CTRL_12                 [expr       {$EMIF_BASE_ADDR     +  0x0258}]
+set  EXT_PHY_CTRL_12_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x025c}]
+set  EXT_PHY_CTRL_13                 [expr       {$EMIF_BASE_ADDR     +  0x0260}]
+set  EXT_PHY_CTRL_13_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0264}]
+set  EXT_PHY_CTRL_14                 [expr       {$EMIF_BASE_ADDR     +  0x0268}]
+set  EXT_PHY_CTRL_14_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x026c}]
+set  EXT_PHY_CTRL_15                 [expr       {$EMIF_BASE_ADDR     +  0x0270}]
+set  EXT_PHY_CTRL_15_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0274}]
+set  EXT_PHY_CTRL_16                 [expr       {$EMIF_BASE_ADDR     +  0x0278}]
+set  EXT_PHY_CTRL_16_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x027c}]
+set  EXT_PHY_CTRL_17                 [expr       {$EMIF_BASE_ADDR     +  0x0280}]
+set  EXT_PHY_CTRL_17_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0284}]
+set  EXT_PHY_CTRL_18                 [expr       {$EMIF_BASE_ADDR     +  0x0288}]
+set  EXT_PHY_CTRL_18_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x028c}]
+set  EXT_PHY_CTRL_19                 [expr       {$EMIF_BASE_ADDR     +  0x0290}]
+set  EXT_PHY_CTRL_19_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0294}]
+set  EXT_PHY_CTRL_20                 [expr       {$EMIF_BASE_ADDR     +  0x0298}]
+set  EXT_PHY_CTRL_20_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x029c}]
+set  EXT_PHY_CTRL_21                 [expr       {$EMIF_BASE_ADDR     +  0x02a0}]
+set  EXT_PHY_CTRL_21_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02a4}]
+set  EXT_PHY_CTRL_22                 [expr       {$EMIF_BASE_ADDR     +  0x02a8}]
+set  EXT_PHY_CTRL_22_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ac}]
+set  EXT_PHY_CTRL_23                 [expr       {$EMIF_BASE_ADDR     +  0x02b0}]
+set  EXT_PHY_CTRL_23_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02b4}]
+set  EXT_PHY_CTRL_24                 [expr       {$EMIF_BASE_ADDR     +  0x02b8}]
+set  EXT_PHY_CTRL_24_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02bc}]
+set  EXT_PHY_CTRL_25                 [expr       {$EMIF_BASE_ADDR     +  0x02c0}]
+set  EXT_PHY_CTRL_25_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02c4}]
+set  EXT_PHY_CTRL_26                 [expr       {$EMIF_BASE_ADDR     +  0x02c8}]
+set  EXT_PHY_CTRL_26_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02cc}]
+set  EXT_PHY_CTRL_27                 [expr       {$EMIF_BASE_ADDR     +  0x02d0}]
+set  EXT_PHY_CTRL_27_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02d4}]
+set  EXT_PHY_CTRL_28                 [expr       {$EMIF_BASE_ADDR     +  0x02d8}]
+set  EXT_PHY_CTRL_28_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02dc}]
+set  EXT_PHY_CTRL_29                 [expr       {$EMIF_BASE_ADDR     +  0x02e0}]
+set  EXT_PHY_CTRL_29_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02e4}]
+set  EXT_PHY_CTRL_30                 [expr       {$EMIF_BASE_ADDR     +  0x02e8}]
+set  EXT_PHY_CTRL_30_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ec}]
+set  EXT_PHY_CTRL_31                 [expr       {$EMIF_BASE_ADDR     +  0x02f0}]
+set  EXT_PHY_CTRL_31_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02f4}]
+set  EXT_PHY_CTRL_32                 [expr       {$EMIF_BASE_ADDR     +  0x02f8}]
+set  EXT_PHY_CTRL_32_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02fc}]
+set  EXT_PHY_CTRL_33                 [expr       {$EMIF_BASE_ADDR     +  0x0300}]
+set  EXT_PHY_CTRL_33_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0304}]
+set  EXT_PHY_CTRL_34                 [expr       {$EMIF_BASE_ADDR     +  0x0308}]
+set  EXT_PHY_CTRL_34_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x030c}]
+set  EXT_PHY_CTRL_35                 [expr       {$EMIF_BASE_ADDR     +  0x0310}]
+set  EXT_PHY_CTRL_35_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0314}]
+set  EXT_PHY_CTRL_36                 [expr       {$EMIF_BASE_ADDR     +  0x0318}]
+set  EXT_PHY_CTRL_36_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x031c}]
+
+set  WDT1_BASE_ADDR                  0x44e35000
+set  WDT1_W_PEND_WSPR                [expr       {$WDT1_BASE_ADDR     +  0x0034}]
+set  WDT1_WSPR                       [expr       {$WDT1_BASE_ADDR     +  0x0048}]
+
+set  RTC_BASE_ADDR                   0x44e3e000
+set  RTC_KICK0R                      [expr       {$RTC_BASE_ADDR      +  0x6c}]
+set  RTC_KICK1R                      [expr       {$RTC_BASE_ADDR      +  0x70}]
+
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME am437x
+}
+
+set JRC_MODULE		icepick_d
+set DEBUGSS_MODULE	debugss
+set M3_MODULE		m3_wakeupss
+
+set JRC_NAME		$_CHIPNAME.$JRC_MODULE
+set DEBUGSS_NAME	$_CHIPNAME.$DEBUGSS_MODULE
+set M3_NAME		$_CHIPNAME.$M3_MODULE
+set _TARGETNAME		$_CHIPNAME.mpuss
+
+#
+# M3 WakeupSS DAP
+#
+if { [info exists M3_DAP_TAPID] } {
+	set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+	set _M3_DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
+jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0"
+dap create $M3_NAME.dap -chain-position $M3_NAME
+
+#
+# DebugSS DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x46b6902f
+}
+jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0"
+dap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME
+
+#
+# ICEpick-D (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b98c02f
+}
+jtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME"
+ # some TCK tycles are required to activate the DEBUG power domain
+jtag configure $JRC_NAME -event post-reset "runtest 100"
+
+#
+# Cortex-A9 target
+#
+target create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000
+
+
+# SRAM: 256K at 0x4030.0000
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000
+
+# Disables watchdog timer after reset otherwise board won't stay in
+# halted state.
+proc disable_watchdog { } {
+	global WDT1_WSPR
+	global WDT1_W_PEND_WSPR
+	global _TARGETNAME
+
+	set curstate [$_TARGETNAME curstate]
+
+	if { [string compare $curstate halted] == 0 } {
+		set WDT_DISABLE_SEQ1	0xaaaa
+		set WDT_DISABLE_SEQ2	0x5555
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
+
+		# Empty body to make sure this executes as fast as possible.
+		# We don't want any delays here otherwise romcode might start
+		# executing and end up changing state of certain IPs.
+		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
+		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
+	}
+}
+
+proc ceil { x y } {
+	return [ expr {($x + $y - 1) / $y} ]
+}
+
+proc device_type { } {
+	global CONTROL_STATUS
+
+	set tmp [ mrw $CONTROL_STATUS ]
+	set tmp [ expr {$tmp & 0x700} ]
+	set tmp [ expr {$tmp >> 8} ]
+
+	return $tmp
+}
+
+proc get_input_clock_frequency { } {
+	global CONTROL_STATUS
+
+	if { [ device_type ] != 3 } {
+		error "Unknown device type\n"
+		return -1
+	}
+
+	set freq [ mrw $CONTROL_STATUS ]
+	set freq [ expr {$freq & 0x00c00000} ]
+	set freq [ expr {$freq >> 22} ]
+
+	switch $freq {
+		0 {
+			set CLKIN 19200000
+		}
+
+		1 {
+			set CLKIN 24000000
+		}
+
+		2 {
+			set CLKIN 25000000
+		}
+
+		3 {
+			set CLKIN 26000000
+		}
+	}
+
+	return $CLKIN
+}
+
+proc mpu_pll_config { CLKIN N M M2 } {
+	global CM_CLKMODE_DPLL_MPU
+	global CM_CLKSEL_DPLL_MPU
+	global CM_DIV_M2_DPLL_MPU
+	global CM_IDLEST_DPLL_MPU
+
+	set clksel [ mrw $CM_CLKSEL_DPLL_MPU ]
+	set div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ]
+
+	mww $CM_CLKMODE_DPLL_MPU 0x4
+	while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { }
+
+	set clksel [ expr {$clksel & (~0x7ffff)} ]
+	set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
+	mww $CM_CLKSEL_DPLL_MPU $clksel
+
+	set div_m2 [ expr {$div_m2 & (~0x1f)} ]
+	set div_m2 [ expr {$div_m2 | $M2} ]
+	mww $CM_DIV_M2_DPLL_MPU $div_m2
+
+	mww $CM_CLKMODE_DPLL_MPU 0x7
+	while { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { }
+
+	echo "MPU DPLL locked"
+}
+
+proc core_pll_config { CLKIN N M M4 M5 M6 } {
+	global CM_CLKMODE_DPLL_CORE
+	global CM_CLKSEL_DPLL_CORE
+	global CM_DIV_M4_DPLL_CORE
+	global CM_DIV_M5_DPLL_CORE
+	global CM_DIV_M6_DPLL_CORE
+	global CM_IDLEST_DPLL_CORE
+
+	set clksel [ mrw $CM_CLKSEL_DPLL_CORE ]
+
+	mww $CM_CLKMODE_DPLL_CORE 0x4
+	while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { }
+
+	set clksel [ expr {$clksel & (~0x7ffff)} ]
+	set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
+	mww $CM_CLKSEL_DPLL_CORE $clksel
+	mww $CM_DIV_M4_DPLL_CORE $M4
+	mww $CM_DIV_M5_DPLL_CORE $M5
+	mww $CM_DIV_M6_DPLL_CORE $M6
+
+	mww $CM_CLKMODE_DPLL_CORE 0x7
+	while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { }
+
+	echo "CORE DPLL locked"
+}
+
+proc per_pll_config { CLKIN N M M2 } {
+	global CM_CLKMODE_DPLL_PER
+	global CM_CLKSEL_DPLL_PER
+	global CM_DIV_M2_DPLL_PER
+	global CM_IDLEST_DPLL_PER
+
+	set x [ expr {$M * $CLKIN / 1000000} ]
+	set y [ expr {($N + 1) * 250} ]
+	set sd [ ceil $x $y ]
+
+	set clksel [ mrw $CM_CLKSEL_DPLL_PER ]
+	set div_m2 [ mrw $CM_DIV_M2_DPLL_PER ]
+
+	mww $CM_CLKMODE_DPLL_PER 0x4
+	while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { }
+
+	set clksel [ expr {$clksel & (~0xff0fffff)} ]
+	set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
+	set clksel [ expr {$clksel | ($sd << 24)} ]
+	mww $CM_CLKSEL_DPLL_PER $clksel
+
+	set div_m2 [ expr {0xffffff80 | $M2} ]
+
+	mww $CM_CLKMODE_DPLL_PER 0x7
+	while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { }
+
+	echo "PER DPLL locked"
+}
+
+proc ddr_pll_config { CLKIN N M M2 M4 } {
+	global CM_CLKMODE_DPLL_DDR
+	global CM_CLKSEL_DPLL_DDR
+	global CM_DIV_M2_DPLL_DDR
+	global CM_DIV_M4_DPLL_DDR
+	global CM_IDLEST_DPLL_DDR
+
+	set clksel [ mrw $CM_CLKSEL_DPLL_DDR ]
+	set div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ]
+
+	mww $CM_CLKMODE_DPLL_DDR 0x4
+	while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { }
+
+	set clksel [ expr {$clksel & (~0x7ffff)} ]
+	set clksel [ expr {$clksel | ($M << 8) | $N} ]
+	mww $CM_CLKSEL_DPLL_DDR $clksel
+
+	set div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ]
+	mww $CM_DIV_M2_DPLL_DDR $div_m2
+	mww $CM_DIV_M4_DPLL_DDR $M4
+
+	mww $CM_CLKMODE_DPLL_DDR 0x7
+	while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { }
+
+	echo "DDR DPLL Locked"
+}
+
+proc config_opp100 { } {
+	set CLKIN [ get_input_clock_frequency ]
+
+	if { $CLKIN == -1 } {
+		return -1
+	}
+
+	switch $CLKIN {
+		24000000 {
+			mpu_pll_config   $CLKIN  0  25   1
+			core_pll_config  $CLKIN  2  125  10  8  4
+			per_pll_config   $CLKIN  9  400  5
+			ddr_pll_config   $CLKIN  2  50   1   2
+		}
+
+		25000000 {
+			mpu_pll_config   $CLKIN  0  24   1
+			core_pll_config  $CLKIN  0  40   10  8  4
+			per_pll_config   $CLKIN  9  384  5
+			ddr_pll_config   $CLKIN  0  16   1   2
+		}
+
+		26000000 {
+			mpu_pll_config   $CLKIN  12  300  1
+			core_pll_config  $CLKIN  12  500  10  8  4
+			per_pll_config   $CLKIN  12  480  5
+			ddr_pll_config   $CLKIN  12  200  1   2
+		}
+
+		19200000 {
+			mpu_pll_config   $CLKIN  3   125  1
+			core_pll_config  $CLKIN  11  625  10  8  4
+			per_pll_config   $CLKIN  7   400  5
+			ddr_pll_config   $CLKIN  2   125  1   2
+		}
+	}
+}
+
+proc emif_prcm_clk_enable { } {
+	global CM_PER_EMIF_FW_CLKCTRL
+	global CM_PER_EMIF_CLKCTRL
+
+	mww $CM_PER_EMIF_FW_CLKCTRL 0x02
+	mww $CM_PER_EMIF_CLKCTRL 0x02
+
+	while { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { }
+}
+
+proc vtp_enable { } {
+	global VTP_CTRL_REG
+
+	set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }]
+	mww $VTP_CTRL_REG $vtp
+
+	set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }]
+	mww $VTP_CTRL_REG $vtp
+
+	set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }]
+	mww $VTP_CTRL_REG $vtp
+
+}
+
+proc config_ddr_ioctrl { } {
+	global DDR_ADDRCTRL_IOCTRL
+	global DDR_ADDRCTRL_WD0_IOCTRL
+	global DDR_ADDRCTRL_WD1_IOCTRL
+	global DDR_CKE_CTRL
+	global DDR_DATA0_IOCTRL
+	global DDR_DATA1_IOCTRL
+	global DDR_DATA2_IOCTRL
+	global DDR_DATA3_IOCTRL
+	global DDR_IO_CTRL
+
+	mww $DDR_ADDRCTRL_IOCTRL	0x84
+	mww $DDR_ADDRCTRL_WD0_IOCTRL	0x00
+	mww $DDR_ADDRCTRL_WD1_IOCTRL	0x00
+	mww $DDR_DATA0_IOCTRL		0x84
+	mww $DDR_DATA1_IOCTRL		0x84
+	mww $DDR_DATA2_IOCTRL		0x84
+	mww $DDR_DATA3_IOCTRL		0x84
+
+	mww $DDR_IO_CTRL		0x00
+	mww $DDR_CKE_CTRL		0x03
+}
+
+proc config_ddr_phy { } {
+	global EMIF_DDR_PHY_CTRL_1
+	global EMIF_DDR_PHY_CTRL_1_SHDW
+
+	global EXT_PHY_CTRL_1
+	global EXT_PHY_CTRL_1_SHDW
+	global EXT_PHY_CTRL_2
+	global EXT_PHY_CTRL_2_SHDW
+	global EXT_PHY_CTRL_3
+	global EXT_PHY_CTRL_3_SHDW
+	global EXT_PHY_CTRL_4
+	global EXT_PHY_CTRL_4_SHDW
+	global EXT_PHY_CTRL_5
+	global EXT_PHY_CTRL_5_SHDW
+	global EXT_PHY_CTRL_6
+	global EXT_PHY_CTRL_6_SHDW
+	global EXT_PHY_CTRL_7
+	global EXT_PHY_CTRL_7_SHDW
+	global EXT_PHY_CTRL_8
+	global EXT_PHY_CTRL_8_SHDW
+	global EXT_PHY_CTRL_9
+	global EXT_PHY_CTRL_9_SHDW
+	global EXT_PHY_CTRL_10
+	global EXT_PHY_CTRL_10_SHDW
+	global EXT_PHY_CTRL_11
+	global EXT_PHY_CTRL_11_SHDW
+	global EXT_PHY_CTRL_12
+	global EXT_PHY_CTRL_12_SHDW
+	global EXT_PHY_CTRL_13
+	global EXT_PHY_CTRL_13_SHDW
+	global EXT_PHY_CTRL_14
+	global EXT_PHY_CTRL_14_SHDW
+	global EXT_PHY_CTRL_15
+	global EXT_PHY_CTRL_15_SHDW
+	global EXT_PHY_CTRL_16
+	global EXT_PHY_CTRL_16_SHDW
+	global EXT_PHY_CTRL_17
+	global EXT_PHY_CTRL_17_SHDW
+	global EXT_PHY_CTRL_18
+	global EXT_PHY_CTRL_18_SHDW
+	global EXT_PHY_CTRL_19
+	global EXT_PHY_CTRL_19_SHDW
+	global EXT_PHY_CTRL_20
+	global EXT_PHY_CTRL_20_SHDW
+	global EXT_PHY_CTRL_21
+	global EXT_PHY_CTRL_21_SHDW
+	global EXT_PHY_CTRL_22
+	global EXT_PHY_CTRL_22_SHDW
+	global EXT_PHY_CTRL_23
+	global EXT_PHY_CTRL_23_SHDW
+	global EXT_PHY_CTRL_24
+	global EXT_PHY_CTRL_24_SHDW
+	global EXT_PHY_CTRL_25
+	global EXT_PHY_CTRL_25_SHDW
+	global EXT_PHY_CTRL_26
+	global EXT_PHY_CTRL_26_SHDW
+	global EXT_PHY_CTRL_27
+	global EXT_PHY_CTRL_27_SHDW
+	global EXT_PHY_CTRL_28
+	global EXT_PHY_CTRL_28_SHDW
+	global EXT_PHY_CTRL_29
+	global EXT_PHY_CTRL_29_SHDW
+	global EXT_PHY_CTRL_30
+	global EXT_PHY_CTRL_30_SHDW
+	global EXT_PHY_CTRL_31
+	global EXT_PHY_CTRL_31_SHDW
+	global EXT_PHY_CTRL_32
+	global EXT_PHY_CTRL_32_SHDW
+	global EXT_PHY_CTRL_33
+	global EXT_PHY_CTRL_33_SHDW
+	global EXT_PHY_CTRL_34
+	global EXT_PHY_CTRL_34_SHDW
+	global EXT_PHY_CTRL_35
+	global EXT_PHY_CTRL_35_SHDW
+	global EXT_PHY_CTRL_36
+	global EXT_PHY_CTRL_36_SHDW
+
+	mww $EMIF_DDR_PHY_CTRL_1	0x8009
+	mww $EMIF_DDR_PHY_CTRL_1_SHDW	0x8009
+
+	set slave_ratio		0x80
+	set gatelvl_init_ratio	0x20
+	set wr_dqs_slave_delay	0x60
+	set rd_dqs_slave_delay	0x60
+	set dq_offset		0x40
+	set gatelvl_init_mode	0x01
+	set wr_data_slave_delay	0x80
+	set gatelvl_num_dq0 0x0f
+	set wrlvl_num_dq0 0x0f
+
+	mww $EXT_PHY_CTRL_1        [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
+	mww $EXT_PHY_CTRL_1_SHDW   [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
+	mww $EXT_PHY_CTRL_26       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_26_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_27       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_27_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_28       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_28_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_29       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_29_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_30       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_30_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
+	mww $EXT_PHY_CTRL_31       0x00
+	mww $EXT_PHY_CTRL_31_SHDW  0x00
+	mww $EXT_PHY_CTRL_32       0x00
+	mww $EXT_PHY_CTRL_32_SHDW  0x00
+	mww $EXT_PHY_CTRL_33       0x00
+	mww $EXT_PHY_CTRL_33_SHDW  0x00
+	mww $EXT_PHY_CTRL_34       0x00
+	mww $EXT_PHY_CTRL_34_SHDW  0x00
+	mww $EXT_PHY_CTRL_35       0x00
+	mww $EXT_PHY_CTRL_35_SHDW  0x00
+	mww $EXT_PHY_CTRL_22       0x00
+	mww $EXT_PHY_CTRL_22_SHDW  0x00
+	mww $EXT_PHY_CTRL_23       [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]
+	mww $EXT_PHY_CTRL_23_SHDW  [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]
+	mww $EXT_PHY_CTRL_24       [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ]
+	mww $EXT_PHY_CTRL_24_SHDW  [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ]
+	mww $EXT_PHY_CTRL_25       [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
+	mww $EXT_PHY_CTRL_25_SHDW  [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
+	mww $EXT_PHY_CTRL_36       [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
+	mww $EXT_PHY_CTRL_36_SHDW  [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
+}
+
+proc config_ddr_timing { } {
+	global EMIF_SDRAM_TIM_1
+	global EMIF_SDRAM_TIM_2
+	global EMIF_SDRAM_TIM_3
+	global EMIF_SDRAM_TIM_1_SHDW
+	global EMIF_SDRAM_TIM_2_SHDW
+	global EMIF_SDRAM_TIM_3_SHDW
+	global EMIF_ZQ_CONFIG
+
+	mww $EMIF_SDRAM_TIM_1		0xeaaad4db
+	mww $EMIF_SDRAM_TIM_1_SHDW	0xeaaad4db
+
+	mww $EMIF_SDRAM_TIM_2		0x266b7fda
+	mww $EMIF_SDRAM_TIM_2_SHDW	0x266b7fda
+
+	mww $EMIF_SDRAM_TIM_3		0x107f8678
+	mww $EMIF_SDRAM_TIM_3_SHDW	0x107f8678
+
+	mww $EMIF_ZQ_CONFIG		0x50074be4
+}
+
+proc config_ddr_pm { } {
+	global EMIF_PWR_MGMT_CTRL
+	global EMIF_PWR_MGMT_CTRL_SHDW
+	global EMIF_DLL_CALIB_CTRL
+	global EMIF_DLL_CALIB_CTRL_SHDW
+	global EMIF_TEMP_ALERT_CONFIG
+
+	mww $EMIF_PWR_MGMT_CTRL		0x00
+	mww $EMIF_PWR_MGMT_CTRL_SHDW	0x00
+	mww $EMIF_DLL_CALIB_CTRL	0x00050000
+	mww $EMIF_DLL_CALIB_CTRL_SHDW	0x00050000
+	mww $EMIF_TEMP_ALERT_CONFIG	0x00
+}
+
+proc config_ddr_priority { } {
+	global EMIF_PRI_COS_MAP
+	global EMIF_CONNID_COS_1_MAP
+	global EMIF_CONNID_COS_2_MAP
+	global EMIF_RD_WR_EXEC_THRSH
+	global COS_CONFIG
+
+	mww $EMIF_PRI_COS_MAP       0x00
+	mww $EMIF_CONNID_COS_1_MAP  0x00
+	mww $EMIF_CONNID_COS_2_MAP  0x0
+	mww $EMIF_RD_WR_EXEC_THRSH  0x0405
+	mww $COS_CONFIG             0x00ffffff
+}
+
+proc config_ddr3 { SDRAM_CONFIG } {
+	global CM_DLL_CTRL
+	global EMIF_IODFT_TLGC
+	global EMIF_RDWR_LVL_CTRL
+	global EMIF_RDWR_LVL_RMP_CTRL
+	global EMIF_SDRAM_CONFIG
+	global EMIF_SDRAM_CONFIG_EXT
+	global EMIF_SDRAM_REF_CTRL
+	global EMIF_SDRAM_REF_CTRL_SHDW
+	global EMIF_STATUS
+	global EXT_PHY_CTRL_36
+	global EXT_PHY_CTRL_36_SHDW
+
+	emif_prcm_clk_enable
+	vtp_enable
+
+	set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }]
+	mww $CM_DLL_CTRL $dll
+	while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }
+
+	config_ddr_ioctrl
+
+	mww $EMIF_SDRAM_CONFIG_EXT	0xc163
+	mww $EMIF_IODFT_TLGC		0x2011
+	mww $EMIF_IODFT_TLGC		0x2411
+	mww $EMIF_IODFT_TLGC		0x2011
+	mww $EMIF_SDRAM_REF_CTRL	0x80003000
+
+	config_ddr_phy
+
+	mww $EMIF_IODFT_TLGC		0x2011
+	mww $EMIF_IODFT_TLGC		0x2411
+	mww $EMIF_IODFT_TLGC		0x2011
+
+	config_ddr_timing
+	config_ddr_pm
+	config_ddr_priority
+
+	mww $EMIF_SDRAM_REF_CTRL	0x3000
+	mww $EMIF_SDRAM_CONFIG		$SDRAM_CONFIG
+
+	mww $EMIF_SDRAM_REF_CTRL	0x0c30
+	mww $EMIF_SDRAM_REF_CTRL_SHDW	0x0c30
+
+	sleep 10
+
+	set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }]
+	mww $EXT_PHY_CTRL_36		$tmp
+	mww $EXT_PHY_CTRL_36_SHDW	$tmp
+
+	mww $EMIF_RDWR_LVL_RMP_CTRL	0x80000000
+	mww $EMIF_RDWR_LVL_CTRL		0x80000000
+
+	while { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { }
+
+	if { [ mrw $EMIF_STATUS ]  & 0x70 } {
+		error "DDR3 Hardware Leveling incomplete!!!"
+	}
+}
+
+proc init_platform { SDRAM_CONFIG } {
+	config_opp100
+	config_ddr3 $SDRAM_CONFIG
+}
+
+$_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 }
+$_TARGETNAME configure -event reset-end { disable_watchdog }
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/amdm37x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/amdm37x.cfg
new file mode 100644
index 0000000..d9adae9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/amdm37x.cfg
@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Copyright (C)   2010-2011   by Karl Kurbjun
+# Copyright (C)   2009-2011   by Øyvind Harboe
+# Copyright (C)   2009        by David Brownell
+# Copyright (C)   2009        by Magnus Lundin
+#
+# TI AM/DM37x Technical Reference Manual (Version R)
+#  http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf
+#
+# This script is based on the AM3517 initialization.  It should be considered
+# preliminary since it needs more complete testing and only the basic
+# operations work.
+#
+
+###############################################################################
+# User modifiable parameters
+###############################################################################
+
+# This script uses the variable CHIPTYPE to determine whether this is an AM35x
+# or DM37x target. If CHIPTYPE is not set it will error out.
+if { [info exists CHIPTYPE] } {
+
+   if { [info exists CHIPNAME] } {
+      set _CHIPNAME $CHIPNAME
+   } else {
+      set _CHIPNAME $CHIPTYPE
+   }
+
+   switch $CHIPTYPE {
+      dm37x {
+         # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
+         set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"
+      }
+      am35x {
+         # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
+         set _JRC_TAPID "-expected-id 0x0b7ae02f -expected-id 0x0b86802f"
+      }
+      default {
+         error "ERROR: CHIPTYPE was set, but it was not set to a valid value.  Acceptable values are \"dm37x\" or \"am35x\"."
+      }
+   }
+} else {
+  error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
+}
+
+# Run the adapter at the fastest acceptable speed with the slowest possible
+# core clock.
+adapter speed 10
+
+###############################################################################
+# JTAG setup
+# The OpenOCD commands are described in the TAP Declaration section
+#  http://openocd.org/doc/html/TAP-Declaration.html
+###############################################################################
+
+# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More
+#  can be read about this module in sprugn4r in chapter 27:  "Debug and
+#  Emulation".  The module is used to route the JTAG chain to the various
+#  subsystems in the chip.
+source [find target/icepick.cfg]
+
+# The TAP order should be described from the TDO connection in OpenOCD to the
+#  TDI pin.  The OpenOCD FAQ describes this in more detail:
+#  http://openocd.org/doc/html/FAQ.html
+
+# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO:
+#
+#  Device   |  TAP number
+#  ---------|------------
+#  DAP      |  3
+#  Sequencer|  2   Note: The sequencer is an ARM968
+#  DSP      |  1
+#  D2D      |  0
+#
+# Right now the only secondary tap enabled is the DAP so the rest are left
+# undescribed.
+
+######
+# Start of Chain Description
+# The Secondary TAPs all have enable functions defined for use with the ICEPick
+# Only the DAP is enabled.  The AM37xx does not have the Sequencer or DSP but
+# the TAP numbers for ICEPick do not change.
+#
+# TODO: A disable function should also be added.
+######
+
+# Secondary TAP: DAP is closest to the TDO output
+# The TAP enable event also needs to be described
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+   "icepick_c_tapenable $_CHIPNAME.jrc 3"
+
+# These taps are only present in the DM37x series.
+if { $CHIPTYPE == "dm37x" } {
+   # Secondary TAP: Sequencer (ARM968) it is not in the chain by default
+   # The ICEPick can be used to enable it in the chain.
+   jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
+   jtag configure $_CHIPNAME.arm2 -event tap-enable \
+      "icepick_c_tapenable $_CHIPNAME.jrc 2"
+
+   # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
+   # The ICEPick can be used to enable it in the chain.
+   jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
+   jtag configure $_CHIPNAME.dsp -event tap-enable \
+      "icepick_c_tapenable $_CHIPNAME.jrc 1"
+}
+
+# Secondary TAP: D2D it is not in the chain by default (-disable)
+# The ICEPick can be used to enable it in the chain.
+# This IRLEN is probably incorrect - not sure where the documentation is.
+jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
+jtag configure $_CHIPNAME.d2d -event tap-enable \
+   "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEPick - it is closest to TDI so last in the chain
+eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
+
+######
+# End of Chain Description
+######
+
+######
+# Start JTAG TAP events
+######
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+# Enable the DAP TAP
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+
+######
+# End JTAG TAP events
+######
+
+###############################################################################
+# Target Setup:
+# This section is described in the OpenOCD documentation under CPU Configuration
+#  http://openocd.org/doc/html/CPU-Configuration.html
+###############################################################################
+
+# Create the CPU target to be used with GDB:  Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+# The DM37x has 64K of SRAM starting at address 0x4020_0000.  Allow the first
+# 16K to be used as a scratchpad for OpenOCD.
+
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
+
+######
+# Start Target Reset Event Setup:
+######
+
+# Set the JTAG clock down to 10 kHz to be sure that it will work with the
+#  slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
+#  *after* PLL and clock tree setup.
+
+$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
+
+# Describe the reset assert process for openocd - this is asserted with the
+# ICEPick
+$_TARGETNAME configure -event "reset-assert" {
+
+   global _CHIPNAME
+
+   # assert warm system reset through ICEPick
+   icepick_c_wreset $_CHIPNAME.jrc
+}
+
+# After the reset is asserted we need to re-initialize debugging and speed up
+# the JTAG clock.
+
+$_TARGETNAME configure -event reset-assert-post {
+
+   global _TARGETNAME
+   amdm37x_dbginit $_TARGETNAME
+   adapter speed 1000
+}
+
+$_TARGETNAME configure -event gdb-attach {
+
+   global _TARGETNAME
+   amdm37x_dbginit $_TARGETNAME
+
+   echo "Halting target"
+   halt
+}
+
+######
+# End Target Reset Event Setup:
+######
+
+###############################################################################
+# Target Functions
+# Add any functions needed for the target here
+###############################################################################
+
+# Run this to enable invasive debugging.  This is run automatically in the
+# reset sequence.
+proc amdm37x_dbginit {target} {
+   # General Cortex-A8 debug initialisation
+   cortex_a dbginit
+
+   # Enable DBGEN signal.  This signal is described in the ARM v7 TRM, but
+   # access to the signal appears to be implementation specific.  TI does not
+   # describe this register much except a quick line that states DBGEM (sic) is
+   # at this address and this bit.
+   $target mww phys 0x5401d030 0x00002000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ampere_emag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ampere_emag.cfg
new file mode 100644
index 0000000..fd68fcd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ampere_emag.cfg
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# OpenOCD Target Configuration for eMAG ARMv8 Processor
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+#
+
+#
+# Configure defaults for target
+# Can be overridden in board configuration file
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME emag
+}
+
+if { [info exists NUMCORES] } {
+	set _NUMCORES $NUMCORES
+} else {
+	set _NUMCORES 32
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4BA00477
+}
+
+#
+# Configure JTAG TAP
+#
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_CPUTAPID
+set _TAPNAME $_CHIPNAME.cpu
+
+set _DAPNAME ${_TAPNAME}_dap
+set _APNUM 1
+dap create $_DAPNAME -chain-position $_TAPNAME
+$_DAPNAME apsel $_APNUM
+
+# Create the DAP AP0 MEM-AP AHB-AP target
+target create AHB mem_ap -endian $_ENDIAN -dap $_DAPNAME -ap-num 0
+
+# Create the DAP AP1 MEM-AP APB-AP target
+target create APB mem_ap -endian $_ENDIAN -dap $_DAPNAME -ap-num 1
+
+#
+# Configure target CPUs
+#
+
+# Build string used to enable smp mode
+set _SMP_STR "target smp"
+
+for {set _i 0} {$_i < $_NUMCORES} {incr _i} {
+	# Format a string to reference which CPU target to use
+	set _TARGETNAME [format "${_TAPNAME}_%02d" $_i]
+
+	# Create and configure Cross Trigger Interface (CTI) - required for halt and resume
+	set _CTINAME $_TARGETNAME.cti
+	cti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr {0xFC020000 + ($_i << 20)}]
+
+	# Create the target
+	target create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_DAPNAME -ap-num $_APNUM -cti $_CTINAME -coreid $_i
+	set _SMP_STR "$_SMP_STR $_TARGETNAME"
+
+	# Clear CTI output/input enables that are not configured by OpenOCD for aarch64
+	$_TARGETNAME configure -event examine-start [subst {
+		$_CTINAME write INEN0 0x00000000
+		$_CTINAME write INEN1 0x00000000
+		$_CTINAME write INEN2 0x00000000
+		$_CTINAME write INEN3 0x00000000
+		$_CTINAME write INEN4 0x00000000
+		$_CTINAME write INEN5 0x00000000
+		$_CTINAME write INEN6 0x00000000
+		$_CTINAME write INEN7 0x00000000
+		$_CTINAME write INEN8 0x00000000
+
+		$_CTINAME write OUTEN2 0x00000000
+		$_CTINAME write OUTEN3 0x00000000
+		$_CTINAME write OUTEN4 0x00000000
+		$_CTINAME write OUTEN5 0x00000000
+		$_CTINAME write OUTEN6 0x00000000
+		$_CTINAME write OUTEN7 0x00000000
+		$_CTINAME write OUTEN8 0x00000000
+	}]
+
+	# Enable OpenOCD HWTHREAD RTOS feature for GDB thread (CPU) selection support
+	# This feature presents CPU cores ("hardware threads") in an SMP system as threads to GDB
+	$_TARGETNAME configure -rtos hwthread
+}
+eval $_SMP_STR
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ampere_qs_mq.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ampere_qs_mq.cfg
new file mode 100644
index 0000000..0e83766
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ampere_qs_mq.cfg
@@ -0,0 +1,333 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# OpenOCD Target Configuration for Ampere Altra ("Quicksilver") and
+# Ampere Altra Max ("Mystique") processors
+#
+# Copyright (c) 2019-2022, Ampere Computing LLC
+
+# Command Line Argument Description
+#
+# SPLITSMP
+# Only used for dual socket systems. Do not use for a single socket setup.
+# Option pertains to the ARMv8 target core naming in a dual socket setup.
+# If specified, name all ARMv8 cores per socket as individual SMP sessions.
+# If not specified, name ARMv8 cores from both sockets as one SMP session.
+# This option is used in conjunction with the SMP_STR board file option.
+# Syntax: -c "set SPLITSMP {}"
+#
+# PHYS_IDX
+# Enable OpenOCD ARMv8 core target physical indexing.
+# If not specified, defaults to OpenOCD ARMv8 core target logical indexing.
+# Syntax: -c "set PHYS_IDX {}"
+#
+# CHIPNAME
+# Specifies the name of the chip.
+# Will typically be either qs, qs0, qs1, mq, mq0 or mq1.
+# If not specified, defaults to qs.
+# Syntax: -c "set CHIPNAME {qs}"
+#
+# SYSNAME
+# Specifies the name of the system.
+# Will typically be either qs or mq.
+# If not specified, defaults to qs.
+# Syntax: -c "set SYSNAME {qs}"
+#
+# Life-Cycle State (LCS)
+# If not specified, defaults to "Secure LCS".
+# LCS=0, "Secure LCS"
+# LCS=1, "Chip Manufacturing LCS"
+# Syntax: -c "set LCS {0}"
+# Syntax: -c "set LCS {1}"
+#
+# CORELIST
+# Specify available physical cores by number.
+# Example syntax to connect to physical cores 16 and 17.
+# Syntax: -c "set CORELIST {16 17}"
+#
+# COREMASK_LO
+# Specify available physical cores 0-63 by mask.
+# Example syntax to connect to physical cores 16 and 17.
+# Syntax: -c "set COREMASK_LO {0x0000000000030000}"
+#
+# COREMASK_HI
+# Specify available physical cores 64 and above by mask.
+# Example syntax to connect to physical cores 94 and 95.
+# Syntax: -c "set COREMASK_HI {0x00000000C0000000}"
+#
+# ARMV8_TAPID
+# Can override the ARMV8 TAPID default value if necessary.
+# Experimental Use. Most users will not use this option.
+# Syntax: -c "set ARMV8_TAPID {0x3BA06477}"
+#
+# SMPMPRO_TAPID
+# Can override the SMPMPRO TAPID default value if necessary.
+# Experimental Use. Most users will not use this option.
+# Syntax: -c "set SMPMPRO_TAPID {0x4BA00477}"
+#
+#
+# Board File Argument Description
+# These optional arguments are defined in the board file and
+# referenced by the target file. See the corresponding board
+# files for examples of their use.
+#
+# SMP_STR
+# This option is used primarily for a dual socket system and it is not
+# recommended for a single socket setup. This option configures whether
+# the SMP ARMv8 core grouping is maintained at the board or target cfg level.
+# Specify the option if the SMP core grouping is defined at the board level.
+# Do not specify if the SMP core grouping is defined at the chip level.
+# If not specified, defaults to SMP core grouping defined per socket.
+# If specified, "SMP_STR=target smp", the SMP core grouping is maintained
+# at the board cfg level.
+# Used in conjunction with the SPLITSMP option to group two chips into
+# a single SMP configuration or maintain as two separate SMP sessions.
+#
+# CORE_INDEX_OFFSET
+# Specifies the starting logical core index value.
+# Used for dual-socket systems.
+# For socket #0, set to 0.
+# For socket #1, set the starting logical core based from
+# the last logical core on socket #0.
+# If not specified, defaults to 0.
+#
+
+#
+# Configure defaults for target.
+# Can be overridden in board configuration file.
+#
+
+if { [info exists SMP_STR] } {
+	# SMP configured at the dual socket board level
+	set _SMP_STR $SMP_STR
+} else {
+	# SMP configured at the single socket target level
+	set _SMP_STR "target smp"
+}
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME qs
+}
+
+if { [info exists SYSNAME] } {
+	set _SYSNAME $SYSNAME
+} else {
+	set _SYSNAME qs
+}
+
+if { [info exists CORE_INDEX_OFFSET] } {
+	set _CORE_INDEX_OFFSET $CORE_INDEX_OFFSET
+} else {
+	set _CORE_INDEX_OFFSET 0
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists ARMV8_TAPID] } {
+	set _ARMV8_TAPID $ARMV8_TAPID
+} else {
+	if { [info exists MQ_ENABLE] } {
+		# Configure for Mystique
+		set _ARMV8_TAPID 0x3BA06477
+		set _MAX_CORE 128
+	} else {
+		# Configure for Quicksilver
+		set _ARMV8_TAPID 0x2BA06477
+		set _MAX_CORE 80
+	}
+}
+
+if { [info exists SMPMPRO_TAPID] } {
+	set _SMPMPRO_TAPID $SMPMPRO_TAPID
+} else {
+	set _SMPMPRO_TAPID 0x4BA00477
+}
+
+if { [info exists CORELIST] } {
+	set _CORELIST $CORELIST
+} else {
+	if { [info exists COREMASK_LO] } {
+		set _COREMASK_LO $COREMASK_LO
+	} else {
+		set _COREMASK_LO 0x0
+	}
+
+	if { [info exists COREMASK_HI] } {
+		set _COREMASK_HI $COREMASK_HI
+	} else {
+		set _COREMASK_HI 0x0
+	}
+
+	set _CORELIST {}
+
+	set _MASK 0x1
+	for {set i 0} {$i < 64} {incr i} {
+		if { [expr {$_COREMASK_LO & $_MASK}] != 0x0 } {
+			set _CORELIST "$_CORELIST $i"
+		}
+		set _MASK [expr {$_MASK << 0x1}]
+	}
+
+	set _MASK 0x1
+	for {} {$i < $_MAX_CORE} {incr i} {
+		if { [expr {$_COREMASK_HI & $_MASK}] != 0x0 } {
+			set _CORELIST "$_CORELIST $i"
+		}
+		set _MASK [expr {$_MASK << 0x1}]
+	}
+}
+
+#
+# Definition of target names
+#
+set _TARGETNAME_PMPRO pmpro
+set _TARGETNAME_SMPRO smpro
+set _TARGETNAME_ARMV8 armv8
+
+#
+# Configure JTAG TAPs - TAP chain declaration order is important
+#
+
+jtag newtap $_CHIPNAME pmpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
+set _TAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.tap
+
+jtag newtap $_CHIPNAME smpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
+set _TAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.tap
+
+jtag newtap $_CHIPNAME armv8.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_ARMV8_TAPID
+set _TAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.tap
+
+set _DAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.dap
+set _DAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.dap
+set _DAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.dap
+
+set _AP_PMPRO_AHB 0
+set _AP_SMPRO_AHB 0
+set _AP_ARMV8_APB 0x00010000
+set _AP_ARMV8_AXI 0x00020000
+
+#
+# Configure JTAG DAPs
+#
+
+dap create $_DAPNAME_PMPRO -chain-position $_TAPNAME_PMPRO -adiv5
+dap create $_DAPNAME_SMPRO -chain-position $_TAPNAME_SMPRO -adiv5
+dap create $_DAPNAME_ARMV8 -chain-position $_TAPNAME_ARMV8 -adiv6
+
+if { [info exists LCS] && [expr {"$LCS"!="0"}] } {
+	#
+	# Create the DAP AHB-AP MEM-AP target for the PMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_PMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
+
+	#
+	# Configure target PMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_PMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
+
+	#
+	# Create the DAP AHB-AP MEM-AP target for the SMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_SMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
+
+	#
+	# Configure target SMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_SMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
+}
+
+# Create the DAP APB-AP MEM-AP target for the ARMV8 cores
+target create $_CHIPNAME.$_TARGETNAME_ARMV8.apb mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB
+
+# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores
+target create $_CHIPNAME.$_TARGETNAME_ARMV8.axi mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_AXI
+
+# Set CSW register value default correctly for AXI accessible device memory:
+# Select the correct Access Port Number
+$_DAPNAME_ARMV8 apsel $_AP_ARMV8_AXI
+# First set the CSW to OpenOCD's internal default
+$_DAPNAME_ARMV8 apcsw default
+# Set Domain[1:0]=b'11  (CSW[14:13]=b'11)
+# Set Cache[3:0]=b'0000 (CSW[27:24]=b'0000)
+# Porter Cfg registers require secure access, AxPROT[1] (CSW[29]) must be b'0'.
+# Set AxPROT[2:0]=b'000 (CSW[30:28]=b'000) for an Unpriveleged, Secure, Data access.
+$_DAPNAME_ARMV8 apcsw 0x00006000 0x7F006000
+
+#
+# Configure target CPUs
+#
+
+set logical_index $_CORE_INDEX_OFFSET
+
+foreach physical_index $_CORELIST {
+	if { [info exists PHYS_IDX] } {
+		set logical_index [expr {$physical_index + $_CORE_INDEX_OFFSET}]
+	}
+
+	# Format a string to reference which CPU target to use
+	if { [info exists SPLITSMP] } {
+		eval "set _TARGETNAME $_CHIPNAME.${_TARGETNAME_ARMV8}_$logical_index"
+	} else {
+		eval "set _TARGETNAME $_SYSNAME.${_TARGETNAME_ARMV8}_$logical_index"
+	}
+
+	# Create and configure Cross Trigger Interface (CTI) - required for halt and resume
+	set _CTINAME $_TARGETNAME.cti
+	set _offset [expr {(0x00100000 * $physical_index) + (0x00200000 * ($physical_index>>1))}]
+	cti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr {0xA0220000 + $_offset}]
+
+	# Create the target
+	target create $_TARGETNAME aarch64 -endian $_ENDIAN \
+		-dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr {0xA0210000 + $_offset}] \
+		-rtos hwthread -cti $_CTINAME -coreid $logical_index
+
+	# Build string used to enable SMP mode for the ARMv8 CPU cores
+	set _SMP_STR "$_SMP_STR $_TARGETNAME"
+
+	# Clear CTI output/input enables that are not configured by OpenOCD for aarch64
+	$_TARGETNAME configure -event reset-init [subst {
+		$_CTINAME write INEN0 0x00000000
+		$_CTINAME write INEN1 0x00000000
+		$_CTINAME write INEN2 0x00000000
+		$_CTINAME write INEN3 0x00000000
+		$_CTINAME write INEN4 0x00000000
+		$_CTINAME write INEN5 0x00000000
+		$_CTINAME write INEN6 0x00000000
+		$_CTINAME write INEN7 0x00000000
+		$_CTINAME write INEN8 0x00000000
+
+		$_CTINAME write OUTEN0 0x00000000
+		$_CTINAME write OUTEN1 0x00000000
+		$_CTINAME write OUTEN2 0x00000000
+		$_CTINAME write OUTEN3 0x00000000
+		$_CTINAME write OUTEN4 0x00000000
+		$_CTINAME write OUTEN5 0x00000000
+		$_CTINAME write OUTEN6 0x00000000
+		$_CTINAME write OUTEN7 0x00000000
+		$_CTINAME write OUTEN8 0x00000000
+	}]
+
+	incr logical_index
+}
+
+if { [info exists SMP_STR] } {
+	# Return updated SMP configuration string back to board level
+	set SMP_STR $_SMP_STR
+} else {
+	# For single socket per SMP configuration, evaluate the string
+	eval $_SMP_STR
+}
+
+if { [info exists CORE_INDEX_OFFSET] } {
+	# For multi-socket, return total number of cores back to board level
+	set CORE_INDEX_OFFSET $logical_index
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ar71xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ar71xx.cfg
new file mode 100644
index 0000000..792b68f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ar71xx.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Atheros AR71xx MIPS 24Kc SoC.
+# tested on PB44 refererence board
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+reset_config trst_and_srst
+
+set CHIPNAME ar71xx
+
+jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
+
+set _TARGETNAME $CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-halt-post {
+	#setup PLL to lowest common denominator 300/300/150 setting
+	mww 0xb8050000 0x000f40a3	;# reset val + CPU:3 DDR:3 AHB:0
+	mww 0xb8050000 0x800f40a3	;# send to PLL
+
+	#next command will reset for PLL changes to take effect
+	mww 0xb8050008 3		;# set reset_switch and clock_switch (resets SoC)
+}
+
+$_TARGETNAME configure -event reset-init {
+	#complete pll initialization
+	mww 0xb8050000 0x800f0080	;# set sw_update bit
+	mww 0xb8050008 0		;# clear reset_switch bit
+	mww 0xb8050000 0x800f00e8       ;# clr pwrdwn & bypass
+	mww 0xb8050008 1		;# set clock_switch bit
+	sleep 1                         ;# wait for lock
+
+	# Setup DDR config and flash mapping
+	mww 0xb8000000 0xefbc8cd0       ;# DDR cfg cdl val (rst: 0x5bfc8d0)
+	mww 0xb8000004 0x8e7156a2       ;# DDR cfg2 cdl val (rst: 0x80d106a8)
+
+	mww 0xb8000010 8		;# force precharge all banks
+	mww 0xb8000010 1 		;# force EMRS update cycle
+	mww 0xb800000c 0                ;# clr ext. mode register
+	mww 0xb8000010 2 		;# force auto refresh all banks
+	mww 0xb8000010 8		;# force precharge all banks
+	mww 0xb8000008 0x31             ;# set DDR mode value CAS=3
+	mww 0xb8000010 1 		;# force EMRS update cycle
+	mww 0xb8000014 0x461b           ;# DDR refresh value
+	mww 0xb8000018 0xffff           ;# DDR Read Data This Cycle value (16bit: 0xffff)
+	mww 0xb800001c 0x7              ;# delay added to the DQS line (normal = 7)
+	mww 0xb8000020 0
+	mww 0xb8000024 0
+	mww 0xb8000028 0
+}
+
+# setup working area somewhere in RAM
+$_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
+
+# serial SPI capable flash
+# flash bank     
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/arm_corelink_sse200.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/arm_corelink_sse200.cfg
new file mode 100644
index 0000000..7327d05
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/arm_corelink_sse200.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs.
+#
+
+global TARGET
+set TARGET $_CHIPNAME
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+#
+# SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB
+# We will configure work area assuming 8-KB bank size in SRAM bank 1.
+# Also SRAM start addresses defaults to secure mode alias.
+# These values can be overridden as per board configuration
+#
+
+global _WORKAREASIZE_CPU0
+if { [info exists WORKAREASIZE_CPU0] } {
+	set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0
+} else {
+	set _WORKAREASIZE_CPU0 0x1000
+}
+
+global _WORKAREAADDR_CPU0
+if { [info exists WORKAREAADDR_CPU0] } {
+	set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0
+} else {
+	set _WORKAREAADDR_CPU0 0x30008000
+}
+
+#
+# Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200
+# Core 0 is the boot core and will always be configured.
+#
+
+target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
+
+${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0
+
+${TARGET}.CPU0 cortex_m reset_config sysresetreq
+
+#
+# Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200
+# Core 1 is optional and locked at boot until core 0 unlocks it.
+#
+
+if { $_ENABLE_CPU1 } {
+	global _WORKAREASIZE_CPU1
+	if { [info exists WORKAREASIZE_CPU1] } {
+		set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1
+	} else {
+		set _WORKAREASIZE_CPU1 0x1000
+	}
+
+	global _WORKAREAADDR_CPU1
+	if { [info exists WORKAREAADDR_CPU1] } {
+		set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1
+	} else {
+		set _WORKAREAADDR_CPU1 0x30009000
+	}
+
+	target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
+
+	${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0
+
+	${TARGET}.CPU1 cortex_m reset_config vectreset
+}
+
+# Make sure the default target is the boot core
+targets ${TARGET}.CPU0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/armada370.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/armada370.cfg
new file mode 100644
index 0000000..ccf4b36
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/armada370.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# armada370 -- support for the Marvell Armada/370 CPU family
+#
+# gerg@uclinux.org, OCT-2013
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME armada370
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+proc armada370_dbginit {target} {
+     cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-assert-post "armada370_dbginit $_TARGETNAME"
+
+dap apsel 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at32ap7000.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at32ap7000.cfg
new file mode 100644
index 0000000..bbae247
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at32ap7000.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Atmel AT32AP7000
+#
+# This is the only core in the now-inactive high end AVR32 product line,
+# with MMU, Java Acceleration, and "pixel coprocessor".  The AP7 line
+# is for "Application Processors" (AP) with 7-stage pipelines.
+#
+# Most current AVR32 parts are in the UC3 flash based microcontroller (UC)
+# product line with 3-stage pipelines and without those extras.
+#
+# All AVR32 parts provide the Nexus Class 3 on-chip debug interfaces
+# through their JTAG interfaces.
+
+jtag newtap ap7 nexus -irlen 5 -expected-id 0x21e8203f
+
+# REVISIT declare an avr32 target ... needs OpenOCD infrastructure
+# for both Nexus (generic) and AVR32 (Atmel-specific).
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91r40008.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91r40008.cfg
new file mode 100644
index 0000000..66d32ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91r40008.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# AT91R40008 target configuration file
+
+# TRST is tied to SRST on the AT91X40 family.
+reset_config srst_only srst_pulls_trst
+
+
+if {[info exists CHIPNAME]} {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91r40008
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Setup the JTAG scan chain.
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91rm9200.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91rm9200.cfg
new file mode 100644
index 0000000..1bc1287
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91rm9200.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Atmel AT91rm9200
+# http://atmel.com/products/at91/
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91rm9200
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x05b0203f
+}
+
+# Never allow the following!
+if { $_CPUTAPID == 0x15b0203f } {
+   echo "-------------------------------------------------------"
+   echo "- ERROR:                                              -"
+   echo "- ERROR: TapID 0x15b0203f is wrong for at91rm9200     -"
+   echo "- ERROR: The chip/board has a JTAG select pin/jumper  -"
+   echo "- ERROR:                                              -"
+   echo "- ERROR: In one position (0x05b0203f) it selects the  -"
+   echo "- ERROR: ARM CPU, in the other position (0x1b0203f)   -"
+   echo "- ERROR: it selects boundary-scan not the ARM         -"
+   echo "- ERROR:                                              -"
+   echo "-------------------------------------------------------"
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# AT91RM9200 has a 16K block of sram @ 0x0020.0000
+$_TARGETNAME configure -work-area-phys 0x00200000 \
+		-work-area-size 0x4000 -work-area-backup 1
+
+# This chip has a DCC ... use it
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3XXX.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3XXX.cfg
new file mode 100644
index 0000000..ba1c3c5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3XXX.cfg
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam3, a Cortex-M3 chip
+#
+# at91sam3u4e
+# at91sam3u2e
+# at91sam3u1e
+# at91sam3u4c
+# at91sam3u2c
+# at91sam3u1c
+#
+# at91sam3s4c
+# at91sam3s4b
+# at91sam3s4a
+# at91sam3s2c
+# at91sam3s2b
+# at91sam3s2a
+# at91sam3s1c
+# at91sam3s1b
+# at91sam3s1a
+#
+# at91sam3A4C
+# at91sam3A8C
+# at91sam3X4C
+# at91sam3X4E
+# at91sam3X8C
+# at91sam3X8E
+# at91sam3X8H
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME sam3
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# 16K is plenty, the smallest chip has this much
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+$_TARGETNAME configure -event gdb-flash-erase-start {
+    halt
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3ax_4x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3ax_4x.cfg
new file mode 100644
index 0000000..4e0cf79
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3ax_4x.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3ax_xx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
+# This is a 256K chip - it has the 2nd bank
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam3 0x0000A0000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3ax_8x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3ax_8x.cfg
new file mode 100644
index 0000000..46d580d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3ax_8x.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3ax_xx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
+# This is a 512K chip - it has the 2nd bank
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3ax_xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3ax_xx.cfg
new file mode 100644
index 0000000..7837f69
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3ax_xx.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam3, a Cortex-M3 chip
+#
+# at91sam3A4C
+# at91sam3A8C
+# at91sam3X4C
+# at91sam3X4E
+# at91sam3X8C
+# at91sam3X8E
+# at91sam3X8H
+source [find target/at91sam3XXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3nXX.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3nXX.cfg
new file mode 100644
index 0000000..9b20373
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3nXX.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration for Atmel's SAM3N series
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME at91sam3n
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3sXX.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3sXX.cfg
new file mode 100644
index 0000000..a2afda2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3sXX.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam3, a Cortex-M3 chip
+#
+# at91sam3s4c
+# at91sam3s4b
+# at91sam3s4a
+# at91sam3s2c
+# at91sam3s2b
+# at91sam3s2a
+# at91sam3s1c
+# at91sam3s1b
+# at91sam3s1a
+
+source [find target/at91sam3XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x00400000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u1c.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u1c.cfg
new file mode 100644
index 0000000..b26662b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u1c.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u1e.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u1e.cfg
new file mode 100644
index 0000000..b26662b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u1e.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u2c.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u2c.cfg
new file mode 100644
index 0000000..b26662b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u2c.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u2e.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u2e.cfg
new file mode 100644
index 0000000..b26662b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u2e.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u4c.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u4c.cfg
new file mode 100644
index 0000000..fb1eeaa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u4c.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
+# This is a 256K chip, it has the 2nd bank
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u4e.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u4e.cfg
new file mode 100644
index 0000000..1c75f82
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3u4e.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common stuff
+source [find target/at91sam3uxx.cfg]
+
+# size is automatically "calculated" by probing
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
+# This is a 256K chip - it has the 2nd bank
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3uxx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3uxx.cfg
new file mode 100644
index 0000000..f084b9b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam3uxx.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam3, a Cortex-M3 chip
+#
+# at91sam3u4e
+# at91sam3u2e
+# at91sam3u1e
+# at91sam3u4c
+# at91sam3u2c
+# at91sam3u1c
+
+source [find target/at91sam3XXX.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4XXX.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4XXX.cfg
new file mode 100644
index 0000000..9c30ddf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4XXX.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# script for ATMEL sam4, a Cortex-M4 chip
+#
+
+#
+# sam4 devices can support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME sam4
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# 16K is plenty, the smallest chip has this much
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4c32x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4c32x.cfg
new file mode 100644
index 0000000..ddcdd12
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4c32x.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4c32, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam4 0x01100000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4cXXX.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4cXXX.cfg
new file mode 100644
index 0000000..a0206ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4cXXX.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4c, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4lXX.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4lXX.cfg
new file mode 100644
index 0000000..0910e30
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4lXX.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4l, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME
+
+# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N
+# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3).
+#
+# smap_reset_deassert configures whether we want to run or halt out of reset,
+# then instruct the SMAP to let us out of reset.
+$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert"
+
+# SRST (wired to RESET_N) resets debug circuitry
+# srst_pulls_trst is not configured here to avoid an error raised in reset halt
+reset_config srst_gates_jtag
+
+# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed.
+# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
+# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
+# but your mileage may vary.
+adapter speed 50
+
+# System RC oscillator RCSYS starts in 3 cycles
+adapter srst delay 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4sXX.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4sXX.cfg
new file mode 100644
index 0000000..2ceca00
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4sXX.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4sd32x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4sd32x.cfg
new file mode 100644
index 0000000..24e25e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam4sd32x.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4sd32, a Cortex-M4 chip
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME at91sam4 0x00500000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7a2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7a2.cfg
new file mode 100644
index 0000000..f8090c7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7a2.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91sam7a2
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7se512.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7se512.cfg
new file mode 100644
index 0000000..2972494
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7se512.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ATMEL sam7se512
+# Example: the "Elektor Internet Radio" - EIR
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME sam7se512
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # Force an error until we get a good number.
+   set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# The target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank       [      ]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7sx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7sx.cfg
new file mode 100644
index 0000000..fee4e9a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7sx.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91sam7s
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -event reset-init {
+        soft_reset_halt
+        # RSTC_CR : Reset peripherals
+        mww 0xfffffd00 0xa5000004
+        # disable watchdog
+	mww 0xfffffd44 0x00008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=73)
+	mww 0xffffff60 0x00490100
+	sleep 100
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank       [      ]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7x256.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7x256.cfg
new file mode 100644
index 0000000..2ebbf22
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7x256.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME sam7x256
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	# disable watchdog
+	mww 0xfffffd44 0x00008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=60)
+	mww 0xffffff60 0x003c0100
+	sleep 100
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank       [      ]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7x512.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7x512.cfg
new file mode 100644
index 0000000..ccdcfa7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam7x512.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME sam7x512
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	# disable watchdog
+	mww 0xfffffd44 0x00008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=60)
+	mww 0xffffff60 0x003c0100
+	sleep 100
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank       [      ]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME.0 at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
+flash bank $_FLASHNAME.1 at91sam7 0 0 0 0 $_TARGETNAME 1 0 0 0 0 0 0 18432
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9.cfg
new file mode 100644
index 0000000..bc90d37
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9
+######################################
+
+if { [info exists AT91_CHIPNAME] } {
+	set _CHIPNAME $AT91_CHIPNAME
+} else {
+	error "you must specify a chip name"
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x0792603f
+}
+
+reset_config trst_and_srst separate trst_push_pull srst_open_drain
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+adapter srst delay 300
+jtag_ntrst_delay 200
+
+adapter speed 3
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9260.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9260.cfg
new file mode 100644
index 0000000..3f74d96
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9260.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9260
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9260
+}
+
+source [find target/at91sam9.cfg]
+
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9260 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
+# Both areas are 4 kB long.
+
+#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x1000 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg
new file mode 100644
index 0000000..47117e9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9260
+######################################
+
+source [find target/at91sam9261.cfg]
+
+reset_config trst_and_srst
+
+adapter speed 4
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+scan_chain
+$_TARGETNAME configure -event reset-start {
+	# at reset chip runs at 32khz
+	adapter speed 8
+}
+
+$_TARGETNAME configure -event reset-init {at91sam_init}
+
+# Flash configuration
+#flash bank  cfi     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
+
+# Faster memory downloads. This is disabled automatically during
+# reset init since all reset init sequences are too short for
+# fast memory access
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+proc at91sam_init { } {
+	mww 0xfffffd08 0xa5000501         ;# RSTC_MR : enable user reset
+	mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+	sleep 20                          ;# wait 20 ms
+	mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+	sleep 10                          ;# wait 10 ms
+	mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
+	sleep 20                          ;# wait 20 ms
+	mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler
+	sleep 10                          ;# wait 10 ms
+	mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected
+	sleep 10                          ;# wait 10 ms
+
+	# Now run at anything fast... ie: 10mhz!
+	adapter speed 10000               ;# Increase JTAG Speed to 6 MHz
+
+	mww 0xffffec00 0x0a0a0a0a         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+	mww 0xffffec04 0x0b0b0b0b         ;# SMC_PULSE0
+	mww 0xffffec08 0x00160016         ;# SMC_CYCLE0
+	mww 0xffffec0c 0x00161003         ;# SMC_MODE0
+
+	mww 0xfffff870 0xffff0000         ;# PIO_ASR : Select peripheral function for D15..D31
+	mww 0xfffff804 0xffff0000         ;# PIO_PDR : Disable PIO function for D15..D31
+
+	mww 0xffffef1c 0x2                ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+	#mww 0xffffea08 0x85227254         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x5d2              ;# SDRAMC_TR : Set refresh timer count to 15us
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9261.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9261.cfg
new file mode 100644
index 0000000..07456b2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9261.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9261
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9261
+}
+
+source [find target/at91sam9.cfg]
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x28000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9263.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9263.cfg
new file mode 100644
index 0000000..3e2585c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9263.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9263
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9263
+}
+
+source [find target/at91sam9.cfg]
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9263 has two SRAM areas,
+# one starting at 0x00300000 of 80KiB
+# and the other  starting at 0x00500000 of 16KiB.
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x14000 -work-area-backup 1
+#$_TARGETNAME configure -work-area-phys 0x00500000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9g10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9g10.cfg
new file mode 100644
index 0000000..6836773
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9g10.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9G10
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9g10
+}
+
+source [find target/at91sam9.cfg]
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9G10 has one SRAM area at 0x00300000 of 16KiB
+
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9g20.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9g20.cfg
new file mode 100644
index 0000000..4fc2048
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9g20.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9G20
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9g20
+}
+
+source [find target/at91sam9.cfg]
+
+# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
+
+adapter speed 5
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
+# Both areas are 16 kB long.
+
+#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9g45.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9g45.cfg
new file mode 100644
index 0000000..5e6e818
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9g45.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9G45
+######################################
+
+if { [info exists CHIPNAME] } {
+	set AT91_CHIPNAME $CHIPNAME
+} else {
+	set AT91_CHIPNAME at91sam9g45
+}
+
+source [find target/at91sam9.cfg]
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9G45 has one SRAM area starting at 0x00300000 of 64 KiB.
+
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x200000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9rl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9rl.cfg
new file mode 100644
index 0000000..b253427
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sam9rl.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Atmel AT91SAM9RL
+######################################
+
+if { [info exists CHIPNAME] } {
+   set AT91_CHIPNAME $CHIPNAME
+} else {
+   set AT91_CHIPNAME at91sam9rl
+}
+
+source [find target/at91sam9.cfg]
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x10000 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sama5d2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sama5d2.cfg
new file mode 100644
index 0000000..30ddc92
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91sama5d2.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# SAMA5D2 devices support both JTAG and SWD transports.
+#
+# The JTAG connection is disabled at reset, and during the ROM Code execution.
+# It is re-enabled when the ROM code jumps in the boot file copied from an
+# external Flash memory into the internalSRAM, or when the ROM code launches
+# the SAM-BA monitor, when no boot file has been found in any external Flash
+# memory.
+# For more JTAG related information see, :
+# https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-sheet-ds60001476G.pdf
+#
+# If JTAGSEL pin:
+# - if enabled, boundary Scan mode is activated. JTAG ID Code value is 0x05B3F03F.
+# - if disabled, ICE mode is activated. Debug Port JTAG IDCODE value is 0x5BA00477
+#
+
+source [find target/swj-dp.tcl]
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x5ba00477
+	} else {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x5ba02477
+	}
+}
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME at91sama5d2
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Cortex-A5 target
+set _TARGETNAME $_CHIPNAME.cpu_a5
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91samdXX.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91samdXX.cfg
new file mode 100644
index 0000000..5132109
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91samdXX.cfg
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip
+#
+
+#
+# samdXX devices only support SWD transports.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91samd
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# SAMD DSU will hold the CPU in reset if TCK is low when RESET_N
+# deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2)
+#
+# dsu_reset_deassert configures whether we want to run or halt out of reset,
+# then instruct the DSU to let us out of reset.
+$_TARGETNAME configure -event reset-deassert-post {
+        at91samd dsu_reset_deassert
+}
+
+# SRST (wired to RESET_N) resets debug circuitry
+# srst_pulls_trst is not configured here to avoid an error raised in reset halt
+reset_config srst_gates_jtag
+
+# Do not use a reset button with other SWD adapter than Atmel's EDBG.
+# DSU usually locks MCU in reset state until you issue a reset command
+# in OpenOCD.
+
+# SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset.
+# Other members of family usually use SYSCLK = 4 MHz after reset.
+# Datasheet does not specify SYSCLK to SWD clock ratio.
+# Usually used SYSCLK/6 is slow, testing shows that debugging can
+# work @ SYSCLK/2 but your mileage may vary.
+# This limit is most probably imposed by incorrectly handled SWD WAIT
+# on some SWD adapters.
+
+adapter speed 400
+
+# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
+# without problem at maximal clock speed. Atmel recommends
+# adapter speed less than 10 * CPU clock.
+# adapter speed 5000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91samg5x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91samg5x.cfg
new file mode 100644
index 0000000..cbe25f6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/at91samg5x.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for the ATMEL samg5x Cortex-M4F chip family
+#
+
+source [find target/at91sam4XXX.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar2313.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar2313.cfg
new file mode 100644
index 0000000..aa962b4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar2313.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar2313
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x00000001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar2315.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar2315.cfg
new file mode 100644
index 0000000..3836763
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar2315.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar2315
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x00000001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar9331.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar9331.cfg
new file mode 100644
index 0000000..931ac10
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar9331.cfg
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Atheros AR9331 is a highly integrated and cost effective
+# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless
+# local area network (WLAN) AP and router platforms.
+#
+# Notes:
+# - MIPS Processor ID (PRId): 0x00019374
+# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
+#   operating at up to 400 MHz
+# - External 16-bit DDR1, DDR2, or SDRAM memory interface
+# - TRST is not available.
+# - EJTAG PrRst signal is not supported
+# - RESET_L pin A72 on the SoC will reset internal JTAG logic.
+#
+
+# Pins related for debug and bootstrap:
+# Name		Pin		Description
+#   JTAG
+# JTAG_TCK	GPIO0, (A27)	Software configurable, default JTAG
+# JTAG_TDI	GPIO6, (B46)	Software configurable, default JTAG
+# JTAG_TDO	GPIO7, (A54)	Software configurable, default JTAG
+# JTAG_TMS	GPIO8, (A52)	Software configurable, default JTAG
+#   Reset
+# RESET_L	-, (A72)	Input only
+# SYS_RST_L	????????	Output reset request or GPIO
+#   Bootstrap
+# MEM_TYPE[1]	GPIO28, (A74)	0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM
+# MEM_TYPE[0]	GPIO12, (A56)
+# FW_DOWNLOAD	GPIO16, (A75)	Used if BOOT_FROM_SPI = 0. 0 - boot from USB
+#                               1 - boot from MDIO.
+# JTAG_MODE(JS)	GPIO11, (B48)	0 - JTAG (Default); 1 - EJTAG
+# BOOT_FROM_SPI	GPIO1, (A77)	0 - ROM boot; 1 - SPI boot
+# SEL_25M_40M	GPIO0, (A78)	0 - 25MHz; 1 - 40MHz
+#   UART
+# UART0_SOUT	GPIO10, (A79)
+# UART0_SIN	GPIO9, (B68)
+
+# Per default we need to use "none" variant to be able properly "reset init"
+# or "reset halt" the CPU.
+reset_config none srst_pulls_trst
+
+# For SRST based variant we still need proper timings.
+# For ETH part the reset should be asserted at least for 10ms
+# Since there is no other information let's take 100ms to be sure.
+adapter srst pulse_width 100
+
+# according to the SoC documentation it should take at least 5ms from
+# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
+# to live.
+adapter srst delay 8
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar9331
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+# provide watchdog helper.
+proc disable_watchdog { } {
+	mww 0xb8060008 0x0
+}
+
+$_TARGETNAME configure -event halted { disable_watchdog }
+
+# Since PrRst is not supported and SRST will reset complete chip
+# with JTAG engine, we need to reset CPU from CPU itself.
+$_TARGETNAME configure -event reset-assert-pre {
+	halt
+}
+
+$_TARGETNAME configure -event reset-assert {
+	catch "mww 0xb806001C 0x01000000"
+}
+
+# To be able to trigger complete chip reset, in case JTAG is blocked
+# or CPU not responding, we still can use this helper.
+proc full_reset { } {
+	reset_config srst_only
+	reset
+	halt
+	reset_config none
+}
+
+proc disable_watchdog { } {
+	;# disable watchdog
+	mww 0xb8060008 0x0
+}
+
+$_TARGETNAME configure -event reset-end { disable_watchdog }
+
+# Section with helpers which can be used by boards
+proc ar9331_25mhz_pll_init {} {
+	mww 0xb8050008 0x00018004	;# bypass PLL; AHB_POST_DIV - ratio 4
+	mww 0xb8050004 0x00000352	;# 34000(ns)/40ns(25MHz) = 0x352 (850)
+	mww 0xb8050000 0x40818000	;# Power down control for CPU PLL
+					;# OUTDIV | REFDIV | DIV_INT
+	mww 0xb8050010 0x001003e8	;# CPU PLL Dither FRAC Register
+					;# (disabled?)
+	mww 0xb8050000 0x00818000	;# Power on | OUTDIV | REFDIV | DIV_INT
+	mww 0xb8050008 0x00008000	;# remove bypass;
+					;# AHB_POST_DIV - ratio 2
+}
+
+proc ar9331_ddr1_init {} {
+	mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
+	mww 0xb8000004 0x9dd0e6a8	;# DDR_CONFIG2 - more DRAM confs
+
+	mww 0xb8000010 0x8	;# Forces a PRECHARGE ALL cycle
+	mww 0xb8000008 0x133	;# mode reg: 0x133 - default
+	mww 0xb8000010 0x1	;# Forces an MRS update cycl
+	mww 0xb800000c 0x2	;# Extended mode register value.
+				;# default 0x2 - Reset to weak driver, DLL on
+	mww 0xb8000010 0x2	;# Forces an EMRS update cycle
+	mww 0xb8000010 0x8	;# Forces a PRECHARGE ALL cycle
+	mww 0xb8000008 0x33	;# mode reg: remove some bit?
+	mww 0xb8000010 0x1	;# Forces an MRS update cycl
+	mww 0xb8000014 0x4186	;# enable refres: bit(14) - set refresh rate
+	mww 0xb800001c 0x8	;# This register is used along with DQ Lane 0,
+				;# DQ[7:0], DQS_0
+	mww 0xb8000020 0x9	;# This register is used along with DQ Lane 1,
+				;# DQ[15:8], DQS_1.
+	mww 0xb8000018 0xff	;# DDR read and capture bit mask.
+				;# Each bit represents a cycle of valid data.
+}
+
+proc ar9331_ddr2_init {} {
+	mww 0xb8000000 0x7fbc8cd0	;# DDR_CONFIG - lots of DRAM confs
+	mww 0xb8000004 0x9dd0e6a8	;# DDR_CONFIG2 - more DRAM confs
+
+	mww 0xb800008c 0x00000a59
+	mww 0xb8000010 0x00000008	;# PRECHARGE ALL cycle
+
+	mww 0xb8000090 0x00000000
+	mww 0xb8000010 0x00000010	;# EMR2S update cycle
+
+	mww 0xb8000094 0x00000000
+	mww 0xb8000010 0x00000020	;# EMR3S update cycle
+
+	mww 0xb800000c 0x00000000
+	mww 0xb8000010 0x00000002	;# EMRS update cycle
+
+	mww 0xb8000008 0x00000100
+	mww 0xb8000010 0x00000001	;# MRS update cycle
+
+	mww 0xb8000010 0x00000008	;# PRECHARGE ALL cycle
+
+	mww 0xb8000010 0x00000004
+	mww 0xb8000010 0x00000004	;# AUTO REFRESH cycle
+
+	mww 0xb8000008 0x00000a33
+	mww 0xb8000010 0x00000001	;# MRS update cycle
+
+	mww 0xb800000c 0x00000382
+	mww 0xb8000010 0x00000002	;# EMRS update cycle
+
+	mww 0xb800000c 0x00000402
+	mww 0xb8000010 0x00000002	;# EMRS update cycle
+
+	mww 0xb8000014 0x00004186	;# DDR_REFRESH
+	mww 0xb800001c 0x00000008	;# DDR_TAP_CTRL0
+	mww 0xb8000020 0x00000009	;# DDR_TAP_CTRL1
+
+	;# DDR read and capture bit mask.
+	;# Each bit represents a cycle of valid data.
+	;# 0xff: use 16-bit DDR
+	mww 0xb8000018 0x000000ff
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar9344.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar9344.cfg
new file mode 100644
index 0000000..d22bb5f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atheros_ar9344.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar9344
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x00000001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+proc test_ar9344_uart0_tx {} {
+	echo "configuring uart0.."
+	mww 0xb802000c 0x87
+	mww 0xb8020000 0x15
+	mww 0xb8020004 0
+	mww 0xb802000c 7
+	mww 0xb8020004 0
+
+	echo "send message: hallo world"
+	mww 0xb8020000 0x68
+	mww 0xb8020000 0x65
+	mww 0xb8020000 0x6c
+	mww 0xb8020000 0x6c
+	mww 0xb8020000 0x6f
+	mww 0xb8020000 0x20
+	mww 0xb8020000 0x77
+	mww 0xb8020000 0x6f
+	mww 0xb8020000 0x72
+	mww 0xb8020000 0x6c
+	mww 0xb8020000 0x64
+	mww 0xb8020000 0x0a
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atmega128.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atmega128.cfg
new file mode 100644
index 0000000..c946919
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atmega128.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# for avr
+
+   set _CHIPNAME avr
+   set _ENDIAN little
+
+# jtag speed
+adapter speed 4500
+
+reset_config srst_only
+adapter srst delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x8970203F
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
+
+#to use it, script will be like:
+#init
+#adapter speed 4500
+#reset init
+#verify_ircapture disable
+#
+#halt
+#wait halt
+#poll
+#avr mass_erase 0
+#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
+#reset run
+#shutdown
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atmega128rfa1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atmega128rfa1.cfg
new file mode 100644
index 0000000..96a83fe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atmega128rfa1.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME avr
+set _ENDIAN little
+
+# jtag speed
+adapter speed 4500
+
+# avr jtag docs never connect RSTN
+reset_config none
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0a70103f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atmega32u4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atmega32u4.cfg
new file mode 100644
index 0000000..9199c74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atmega32u4.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ATmega32U4
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME avr
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4958703f
+}
+
+adapter speed 4500
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atsame5x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atsame5x.cfg
new file mode 100644
index 0000000..5093d41
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atsame5x.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Microchip (former Atmel) SAM E54, E53, E51 and D51 devices
+# with a Cortex-M4 core
+#
+
+#
+# Devices only support SWD transports.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME atsame5
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 32kB (the smallest RAM size is 128kB)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# SAM DSU will hold the CPU in reset if TCK is low when RESET_N
+# deasserts
+#
+# dsu_reset_deassert configures whether we want to run or halt out of reset,
+# then instruct the DSU to let us out of reset.
+$_TARGETNAME configure -event reset-deassert-post {
+        atsame5 dsu_reset_deassert
+}
+
+# SRST (wired to RESET_N) resets debug circuitry
+# srst_pulls_trst is not configured here to avoid an error raised in reset halt
+reset_config srst_gates_jtag
+
+# Do not use a reset button with other SWD adapter than Atmel's EDBG.
+# DSU usually locks MCU in reset state until you issue a reset command
+# in OpenOCD.
+
+# SAM E5x/D51 runs at SYSCLK = 48 MHz from RC oscillator after reset.
+# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
+# without problem at clock speed over 5000 khz. Atmel recommends
+# adapter speed less than 10 * CPU clock.
+adapter speed 2000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atsaml1x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atsaml1x.cfg
new file mode 100644
index 0000000..5a1b8f8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atsaml1x.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Microchip (formerly Atmel) SAM L1x target
+#
+# Note: These devices support SWD only.
+#
+
+transport select swd
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME saml1x
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+swd newdap $_CHIPNAME cpu -expected-id 0x0bf11477
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if {![using_hla]} {
+    cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atsamv.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atsamv.cfg
new file mode 100644
index 0000000..7e9f6c5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/atsamv.cfg
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts
+# The chips are very similar; the SAMV series just has
+# more peripherals and seems like the "flagship" of the
+# family. This script will work for all of them.
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME samv
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bd11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+adapter speed 1800
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/avr32.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/avr32.cfg
new file mode 100644
index 0000000..e16d114
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/avr32.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME avr32
+set _ENDIAN big
+
+set _CPUTAPID 0x21e8203f
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+reset_config trst_and_srst separate
+
+# jtag scan chain
+# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2711.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2711.cfg
new file mode 100644
index 0000000..f8d2b3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2711.cfg
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Broadcom BCM2711 used in Raspberry Pi 4
+# No documentation was found on Broadcom website
+
+# Partial information is available in raspberry pi website:
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm2711
+}
+
+if { [info exists CHIPCORES] } {
+	set _cores $CHIPCORES
+} else {
+	set _cores 4
+}
+
+if { [info exists USE_SMP] } {
+	set _USE_SMP $USE_SMP
+} else {
+	set _USE_SMP 0
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
+adapter speed 4000
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# MEM-AP for direct access
+target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# these addresses are obtained from the ROM table via 'dap info 0' command
+set _DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+	set _CTINAME $_CHIPNAME.cti$_core
+	set _TARGETNAME $_CHIPNAME.cpu$_core
+
+	cti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 0 -baseaddr [lindex $_CTIBASE $_core]
+	target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME
+
+	set _smp_command "$_smp_command $_TARGETNAME"
+}
+
+if {$_USE_SMP} {
+	eval $_smp_command
+}
+
+# default target is cpu0
+targets $_CHIPNAME.cpu0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm281xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm281xx.cfg
new file mode 100644
index 0000000..a70a9c5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm281xx.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BCM281xx
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm281xx
+}
+
+
+# Main CPU DAP
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
+
+
+# Dual Cortex-A9
+set _TARGETNAME0 $_CHIPNAME.cpu0
+set _TARGETNAME1 $_CHIPNAME.cpu1
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000
+target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000
+target smp $_TARGETNAME0 $_TARGETNAME1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2835.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2835.cfg
new file mode 100644
index 0000000..32a0366
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2835.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the Broadcom chip used in the Raspberry Pi Model A, B, B+,
+# the Compute Module, and the Raspberry Pi Zero.
+
+# Partial information is available in raspberry pi website:
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm2835
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x07b7617F
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 5
+adapter speed 4000
+
+target create $_CHIPNAME.cpu0 arm11 -chain-position $_CHIPNAME.cpu
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2836.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2836.cfg
new file mode 100644
index 0000000..0492131
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2836.cfg
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Broadcom chip used in the Raspberry Pi 2 Model B
+
+# Partial information is available in raspberry pi website:
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm2836
+}
+
+if { [info exists CHIPCORES] } {
+	set _cores $CHIPCORES
+} else {
+	set _cores 4
+}
+
+if { [info exists USE_SMP] } {
+	set _USE_SMP $USE_SMP
+} else {
+	set _USE_SMP 0
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
+adapter speed 4000
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# MEM-AP for direct access
+target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# these addresses are obtained from the ROM table via 'dap info 0' command
+set _DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000}
+
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+	set _TARGETNAME $_CHIPNAME.cpu$_core
+
+	target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -coreid $_core -dbgbase [lindex $_DBGBASE $_core]
+	$_TARGETNAME configure -event reset-assert-post { cortex_a dbginit }
+
+	set _smp_command "$_smp_command $_CHIPNAME.cpu$_core"
+}
+
+if {$_USE_SMP} {
+	eval $_smp_command
+}
+
+# default target is cpu0
+targets $_CHIPNAME.cpu0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2837.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2837.cfg
new file mode 100644
index 0000000..749de31
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm2837.cfg
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is the Broadcom chip used in the Raspberry Pi 3,
+# and in later models of the Raspberry Pi 2.
+
+# Partial information is available in raspberry pi website:
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837
+# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837b0
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME bcm2837
+}
+
+if { [info exists CHIPCORES] } {
+	set _cores $CHIPCORES
+} else {
+	set _cores 4
+}
+
+if { [info exists USE_SMP] } {
+	set _USE_SMP $USE_SMP
+} else {
+	set _USE_SMP 0
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
+adapter speed 4000
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# MEM-AP for direct access
+target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# these addresses are obtained from the ROM table via 'dap info 0' command
+set _DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000}
+set _CTIBASE {0x80018000 0x80019000 0x8001a000 0x8001b000}
+
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+	set _CTINAME $_CHIPNAME.cti$_core
+	set _TARGETNAME $_CHIPNAME.cpu$_core
+
+	cti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 0 -baseaddr [lindex $_CTIBASE $_core]
+	target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME
+	$_TARGETNAME configure -event reset-assert-post { aarch64  dbginit }
+
+	set _smp_command "$_smp_command $_TARGETNAME"
+}
+
+if {$_USE_SMP} {
+	eval $_smp_command
+}
+
+# default target is cpu0
+targets $_CHIPNAME.cpu0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm4706.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm4706.cfg
new file mode 100644
index 0000000..e5d8d19
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm4706.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME bcm4706
+set _CPUID 0x1008c17f
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm4718.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm4718.cfg
new file mode 100644
index 0000000..cc21a5e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm4718.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME bcm4718
+set _LVTAPID 0x1471617f
+set _CPUID 0x0008c17f
+
+source [find target/bcm47xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm47xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm47xx.cfg
new file mode 100644
index 0000000..b5365e0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm47xx.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed"
+reset_config none
+
+jtag newtap $_CHIPNAME-lv tap -irlen 32 -ircapture 0x1 -irmask 0x1f -expected-id $_LVTAPID -expected-id $_CPUID
+jtag configure $_CHIPNAME-lv.tap -event setup "jtag tapenable $_CHIPNAME.cpu"
+jtag configure $_CHIPNAME-lv.tap -event tap-disable {}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "switch_lv_to_ejtag"
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
+
+proc switch_lv_to_ejtag {} {
+    global _CHIPNAME
+    poll 0
+    irscan $_CHIPNAME-lv.tap 0x143ff3a
+    drscan $_CHIPNAME-lv.tap 32 1
+    jtag tapdisable $_CHIPNAME-lv.tap
+    poll 1
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm5352e.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm5352e.cfg
new file mode 100644
index 0000000..084ce04
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm5352e.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME bcm5352e
+set _CPUID 0x0535217f
+
+jtag newtap $_CHIPNAME cpu -irlen 8 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm6348.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm6348.cfg
new file mode 100644
index 0000000..b9d4448
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bcm6348.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set _CHIPNAME bcm6348
+set _CPUID 0x0634817f
+
+adapter speed 1000
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bl702.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bl702.cfg
new file mode 100644
index 0000000..5046cd1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bl702.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Bouffalo Labs BL702, BL704 and BL706 target
+#
+# https://en.bouffalolab.com/product/?type=detail&id=8
+#
+# Default JTAG pins: (if not changed by eFuse configuration)
+# TMS - GPIO0
+# TDI - GPIO1
+# TCK - GPIO2
+# TDO - GPIO9
+#
+
+source [find mem_helper.tcl]
+
+transport select jtag
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME bl702
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_mem_access sysbus
+
+$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1
+
+# Internal RC ticks on 32 MHz, so this speed should be safe to use.
+adapter speed 4000
+
+# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
+# CTRL_PWRON_RESET triggers full "power-on like" reset.
+# This means that pinmux configuration to access JTAG is reset as well, and configured back early
+# in BootROM.
+$_TARGETNAME configure -event reset-assert-pre {
+	halt
+
+	# Switch clock to internal RC32M
+	# In HBN_GLB, set ROOT_CLK_SEL = 0
+	mmw 0x4000f030 0x0 0x00000003
+	# Wait for clock switch
+	sleep 10
+
+	# GLB_REG_BCLK_DIS_FALSE
+	mww 0x40000ffc 0x0
+
+	# HCLK is RC32M, so BCLK/HCLK doesn't need divider
+	# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
+	mmw 0x40000000 0x0 0x00FFFF00
+	# Wait for clock to stabilize
+	sleep 10
+
+	# Do reset
+	# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
+	mmw 0x40000018 0x0 0x00000007
+
+	# Since this full software reset resets GPIO pinmux as well, we will lose access
+	# to JTAG right away after writing to register. This chip doesn't support abstract
+	# memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
+	# if write was successful or not, and will print error about that. Since receiving of
+	# this error is expected, we will turn off log printing for a moment,
+	set lvl [lindex [debug_level] 1]
+	debug_level -1
+	# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
+	catch {mmw 0x40000018 0x7 0x0}
+	debug_level $lvl
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bluefield.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bluefield.cfg
new file mode 100644
index 0000000..30ed527
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bluefield.cfg
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BlueField SoC Target
+
+set _CHIPNAME bluefield
+
+# Specify the target device
+#rshim device /dev/rshim0/rshim
+
+# Main DAP
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4ba00477
+}
+
+adapter speed 1500
+
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Initialize the target name and command variable.
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+# CTI relative address
+set $_TARGETNAME.cti(0) 0xC4020000
+set $_TARGETNAME.cti(1) 0xC4120000
+set $_TARGETNAME.cti(2) 0xC8020000
+set $_TARGETNAME.cti(3) 0xC8120000
+set $_TARGETNAME.cti(4) 0xCC020000
+set $_TARGETNAME.cti(5) 0xCC120000
+set $_TARGETNAME.cti(6) 0xD0020000
+set $_TARGETNAME.cti(7) 0xD0120000
+set $_TARGETNAME.cti(8) 0xD4020000
+set $_TARGETNAME.cti(9) 0xD4120000
+set $_TARGETNAME.cti(10) 0xD8020000
+set $_TARGETNAME.cti(11) 0xD8120000
+set $_TARGETNAME.cti(12) 0xDC020000
+set $_TARGETNAME.cti(13) 0xDC120000
+set $_TARGETNAME.cti(14) 0xE0020000
+set $_TARGETNAME.cti(15) 0xE0120000
+
+# Create debug targets for a number of cores starting from core '_core_start'.
+# Adjust the numbers according to board configuration.
+set _core_start 0
+set _cores 16
+
+# Create each core
+for { set _core $_core_start } { $_core < $_core_start + $_cores } { incr _core 1 } {
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
+
+    if { $_core != $_core_start } {
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+# Configure SMP
+if { $_cores > 1 } {
+    eval $_smp_command
+}
+
+# Make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# Examine remaining cores
+	foreach _core $args {
+		${_TARGETNAME}$_core arp_examine
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bluenrg-x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bluenrg-x.cfg
new file mode 100644
index 0000000..afa1b51
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/bluenrg-x.cfg
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# bluenrg-1/2 and bluenrg-lp devices support only SWD transports.
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME bluenrg-1
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 24kB-256bytes
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x5F00
+}
+
+adapter speed 4000
+
+swj_newdap $_CHIPNAME cpu -expected-id 0x0bb11477 -expected-id 0x0bc11477
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+set WDOG_VALUE 0
+set WDOG_VALUE_SET 0
+
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000100 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
+
+# In BlueNRG-X reset pin is actually a shutdown (power-off), so define reset as none
+reset_config none
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+set JTAG_IDCODE_B2 0x0200A041
+set JTAG_IDCODE_B1 0x0
+
+$_TARGETNAME configure -event halted {
+    global WDOG_VALUE
+    global WDOG_VALUE_SET
+    set _JTAG_IDCODE [mrw 0x40000004]
+    if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
+        # Stop watchdog during halt, if enabled. Only Bluenrg-1/2
+        set WDOG_VALUE [mrw 0x40700008]
+        if [expr {$WDOG_VALUE & (1 << 1)}] {
+            set WDOG_VALUE_SET 1
+            mww 0x40700008 [expr {$WDOG_VALUE & 0xFFFFFFFD}]
+        }
+    }
+}
+$_TARGETNAME configure -event resumed {
+    global WDOG_VALUE
+    global WDOG_VALUE_SET
+    set _JTAG_IDCODE [mrw 0x40000004]
+    if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
+        if {$WDOG_VALUE_SET} {
+            # Restore watchdog enable value after resume. Only Bluenrg-1/2
+            mww 0x40700008 $WDOG_VALUE
+            set WDOG_VALUE_SET 0
+           }
+   }
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100.cfg
new file mode 100644
index 0000000..c268ba3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# c100 config.
+# This is ARM1136 dual core
+# this script only configures one core (that is used to run Linux)
+
+# assume no PLL lock, start slowly
+adapter speed 100
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME c100
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x27b3645b
+}
+
+if { [info exists DSPTAPID] } {
+   set _DSPTAPID $DSPTAPID
+} else {
+   set _DSPTAPID 0x27b3645b
+}
+
+jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_DSPTAPID
+
+
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# C100's ARAM 64k SRAM
+$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100config.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100config.tcl
new file mode 100644
index 0000000..2545fa7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100config.tcl
@@ -0,0 +1,413 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# board(-config) specific parameters file.
+
+# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
+proc config {label} {
+    return [dict get [configC100] $label ]
+}
+
+# show the value for the param. with label
+proc showconfig {label} {
+    echo [format "0x%x" [dict get [configC100] $label ]]
+}
+
+# Telo board config
+# when there are more then one board config
+# use soft links to c100board-config.tcl
+# so that only the right board-config gets
+# included (just like include/configs/board-configs.h
+# in u-boot.
+proc configC100 {} {
+    # xtal freq. 24MHz
+    dict set configC100 CFG_REFCLKFREQ	         24000000
+
+    # Amba Clk 165MHz
+    dict set configC100 CONFIG_SYS_HZ_CLOCK      165000000
+    dict set configC100 w_amba 1
+    dict set configC100 x_amba 1
+    # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
+    dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
+
+    # Arm Clk 450MHz, must be a multiple of 25 MHz
+    dict set configC100 CFG_ARM_CLOCK      450000000
+    dict set configC100 w_arm 0
+    dict set configC100 x_arm 1
+    # y = arm_clk * (w+1)*(x+1)*2/xtal_clk
+    dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
+
+
+}
+
+# This should be called for reset init event handler
+proc setupTelo {} {
+
+    # setup GPIO used as control signals for C100
+    setupGPIO
+    # This will allow access to lower 8MB or NOR
+    lowGPIO5
+    # setup NOR size,timing,etc.
+    setupNOR
+    # setup internals + PLL + DDR2
+    initC100
+}
+
+
+proc setupNOR {} {
+    echo "Setting up NOR: 16MB, 16-bit wide bus, CS0"
+    # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
+    set EX_CSEN_REG	    [regs EX_CSEN_REG ]
+    set EX_CS0_SEG_REG	    [regs EX_CS0_SEG_REG ]
+    set EX_CS0_CFG_REG	    [regs EX_CS0_CFG_REG ]
+    set EX_CS0_TMG1_REG	    [regs EX_CS0_TMG1_REG ]
+    set EX_CS0_TMG2_REG	    [regs EX_CS0_TMG2_REG ]
+    set EX_CS0_TMG3_REG	    [regs EX_CS0_TMG3_REG ]
+    set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
+    set EX_MFSM_REG	    [regs EX_MFSM_REG ]
+    set EX_CSFSM_REG	    [regs EX_CSFSM_REG ]
+    set EX_WRFSM_REG	    [regs EX_WRFSM_REG ]
+    set EX_RDFSM_REG	    [regs EX_RDFSM_REG ]
+
+    # enable Expansion Bus Clock + CS0 (NOR)
+    mww $EX_CSEN_REG 0x3
+    # set the address space for CS0=16MB
+    mww $EX_CS0_SEG_REG 0x7ff
+    # set the CS0 bus width to 16-bit
+    mww $EX_CS0_CFG_REG 0x202
+    # set timings to NOR
+    mww $EX_CS0_TMG1_REG 0x03034006
+    mww $EX_CS0_TMG2_REG 0x04040002
+    #mww $EX_CS0_TMG3_REG
+    # set EBUS clock 165/5=33MHz
+    mww $EX_CLOCK_DIV_REG 0x5
+    # everything else is OK with default
+}
+
+proc bootNOR {} {
+    set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
+    set BLOCK_RESET_REG	       [regs BLOCK_RESET_REG]
+    set DDR_RST		       [regs DDR_RST]
+
+    # put DDR controller in reset (so that it comes reset in u-boot)
+    mmw $BLOCK_RESET_REG 0x0 $DDR_RST
+    # setup CS0 controller for NOR
+    setupNOR
+    # make sure we are accessing the lower part of NOR
+    lowGPIO5
+    # set PC to start of NOR (at boot 0x20000000 = 0x0)
+    reg pc $EXP_CS0_BASEADDR
+    # run
+    resume
+}
+proc setupGPIO {} {
+    echo "Setting up GPIO block for Telo"
+    # This is current setup for Telo (see sch. for details):
+    #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
+    #GPIO1 irq line for FXS-FXO
+    #GPIO5 addr22 for NOR flash (access to upper 8MB)
+    #GPIO17 reset for DECT module.
+    #GPIO29 CS_n for NAND
+
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
+    set GPIO_OE_REG		    [regs GPIO_OE_REG]
+
+    # set GPIO29=GPIO17=1, GPIO5=0
+    mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}]
+    # enable [as output] GPIO29,GPIO17,GPIO5
+    mww $GPIO_OE_REG [expr  {1<<29 | 1<<17 | 1<<5}]
+}
+
+proc highGPIO5 {} {
+    echo "GPIO5 high"
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
+    # set GPIO5=1
+    mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0
+}
+
+proc lowGPIO5 {} {
+    echo "GPIO5 low"
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
+    # set GPIO5=0
+    mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}]
+}
+
+proc boardID {id} {
+    # so far built:
+    # 4'b1111
+    dict set boardID 15 name "EVT1"
+    dict set boardID 15 ddr2size 128M
+    # dict set boardID 15 nandsize 1G
+    # dict set boardID 15 norsize 16M
+    # 4'b0000
+    dict set boardID 0 name "EVT2"
+    dict set boardID 0 ddr2size 128M
+    # 4'b0001
+    dict set boardID 1 name "EVT3"
+    dict set boardID 1 ddr2size 256M
+    # 4'b1110
+    dict set boardID 14 name "EVT3_old"
+    dict set boardID 14 ddr2size 128M
+    # 4'b0010
+    dict set boardID 2 name "EVT4"
+    dict set boardID 2 ddr2size 256M
+
+    return $boardID
+}
+
+
+# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
+# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
+proc ooma_board_detect {} {
+    set GPIO_BOOTSTRAP_REG	[regs GPIO_BOOTSTRAP_REG]
+
+    # read the current value of the BOOTSTRAP pins
+    set tmp [mrw $GPIO_BOOTSTRAP_REG]
+    echo [format "GPIO_BOOTSTRAP_REG  (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
+    # extract the GPBP bits
+    set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}]
+
+    # display board ID
+    echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
+    # show it on serial console
+    putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
+    # return the ddr2 size, used to configure DDR2 on a given board.
+    return [dict get [boardID $gpbt] $gpbt ddr2size]
+}
+
+proc configureDDR2regs_256M {} {
+
+    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
+    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
+    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
+    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
+    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
+    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
+    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
+    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
+    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
+    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
+    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
+    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
+    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
+    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
+    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
+    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
+    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
+    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
+    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
+    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
+    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
+
+    set DENALI_CTL_02_VAL 0x0100000000010100
+    set DENALI_CTL_11_VAL 0x433a32164a560a00
+
+    mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
+    # 01_DATA mod [40]=1, enable BA2
+    mw64bit $DENALI_CTL_01_DATA  0x0100010100000001
+    mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
+    mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
+    mw64bit $DENALI_CTL_04_DATA  0x0000010100000001
+    mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
+    mw64bit $DENALI_CTL_06_DATA  0x060a020200020202
+    mw64bit $DENALI_CTL_07_DATA  0x0000000300000206
+    mw64bit $DENALI_CTL_08_DATA  0x6400003f3f0a0209
+    mw64bit $DENALI_CTL_09_DATA  0x1a000000001a1a1a
+    mw64bit $DENALI_CTL_10_DATA  0x0120202020191a18
+    # 11_DATA mod [39-32]=16,more refresh
+    mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
+    mw64bit $DENALI_CTL_12_DATA  0x0000000000000800
+    mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
+    mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
+    mw64bit $DENALI_CTL_15_DATA  0x04f8000000000000
+    mw64bit $DENALI_CTL_16_DATA  0x000000002cca0000
+    mw64bit $DENALI_CTL_17_DATA  0x0000000000000000
+    mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
+    mw64bit $DENALI_CTL_19_DATA  0x00001300c8030600
+    mw64bit $DENALI_CTL_20_DATA  0x0000000081fe00c8
+
+    set wr_dqs_shift 0x40
+    # start DDRC
+    mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]
+    # wait int_status[2] (DRAM init complete)
+    echo -n "Waiting for DDR2 controller to init..."
+    set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+    while { [expr {$tmp & 0x040000}] == 0 } {
+	sleep 1
+	set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+    }
+    echo "done."
+
+    # do ddr2 training sequence
+    # TBD (for now, if you need it, run trainDDR command)
+}
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
+# The values are computed based on Mindspeed and Nanya datasheets
+proc configureDDR2regs_128M {} {
+
+    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
+    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
+    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
+    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
+    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
+    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
+    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
+    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
+    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
+    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
+    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
+    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
+    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
+    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
+    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
+    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
+    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
+    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
+    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
+    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
+    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
+
+
+    set DENALI_CTL_02_VAL 0x0100010000010100
+    set DENALI_CTL_11_VAL 0x433A42124A650A37
+    # set some default values
+    mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
+    mw64bit $DENALI_CTL_01_DATA  0x0100000100000101
+    mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
+    mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
+    mw64bit $DENALI_CTL_04_DATA  0x0201010100000201
+    mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
+    mw64bit $DENALI_CTL_06_DATA  0x050A020200020202
+    mw64bit $DENALI_CTL_07_DATA  0x000000030E0B0205
+    mw64bit $DENALI_CTL_08_DATA  0x6427003F3F0A0209
+    mw64bit $DENALI_CTL_09_DATA  0x1A00002F00001A00
+    mw64bit $DENALI_CTL_10_DATA  0x01202020201A1A1A
+    mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
+    mw64bit $DENALI_CTL_12_DATA  0x0000080000000800
+    mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
+    mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
+    mw64bit $DENALI_CTL_15_DATA  0x0508000000000000
+    mw64bit $DENALI_CTL_16_DATA  0x000020472D200000
+    mw64bit $DENALI_CTL_17_DATA  0x0000000008000000
+    mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
+    mw64bit $DENALI_CTL_19_DATA  0x00001400C8030604
+    mw64bit $DENALI_CTL_20_DATA  0x00000000823600C8
+
+    set wr_dqs_shift 0x40
+    # start DDRC
+    mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]
+    # wait int_status[2] (DRAM init complete)
+    echo -n "Waiting for DDR2 controller to init..."
+    set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+    while { [expr {$tmp & 0x040000}] == 0 } {
+	sleep 1
+	set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+    }
+    # This is not necessary
+    #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL  & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ]
+    echo "done."
+
+    # do ddr2 training sequence
+    # TBD (for now, if you need it, run trainDDR command)
+}
+
+
+
+proc setupUART0 {} {
+    # configure UART0 to 115200, 8N1
+    set GPIO_LOCK_REG      [regs GPIO_LOCK_REG]
+    set GPIO_IOCTRL_REG    [regs GPIO_IOCTRL_REG]
+    set GPIO_IOCTRL_VAL    [regs GPIO_IOCTRL_VAL]
+    set GPIO_IOCTRL_UART0  [regs GPIO_IOCTRL_UART0]
+    set UART0_LCR	            [regs UART0_LCR]
+    set LCR_DLAB		    [regs LCR_DLAB]
+    set UART0_DLL		    [regs UART0_DLL]
+    set UART0_DLH		    [regs UART0_DLH]
+    set UART0_IIR		    [regs UART0_IIR]
+    set UART0_IER		    [regs UART0_IER]
+    set LCR_ONE_STOP		    [regs LCR_ONE_STOP]
+    set LCR_CHAR_LEN_8		    [regs LCR_CHAR_LEN_8]
+    set FCR_XMITRES		    [regs FCR_XMITRES]
+    set FCR_RCVRRES		    [regs FCR_RCVRRES]
+    set FCR_FIFOEN		    [regs FCR_FIFOEN]
+    set IER_UUE			    [regs IER_UUE]
+
+    # unlock writing to IOCTRL register
+    mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
+    # enable UART0
+    mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
+    # baudrate  115200
+    # This should really be amba_clk/(16*115200) but amba_clk=165MHz
+    set tmp 89
+    # Enable Divisor Latch access
+    mmw  $UART0_LCR $LCR_DLAB 0x0
+    # set the divisor to $tmp
+    mww $UART0_DLL [expr {$tmp & 0xff}]
+    mww $UART0_DLH [expr {$tmp >> 8}]
+    # Disable Divisor Latch access
+    mmw  $UART0_LCR 0x0 $LCR_DLAB
+    # set the UART to 8N1
+    mmw  $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0
+    # reset FIFO
+    mmw  $UART0_IIR [expr {$FCR_XMITRES  | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0
+    #  enable FFUART
+    mww $UART0_IER $IER_UUE
+}
+
+proc putcUART0 {char} {
+
+    set UART0_LSR	    [regs UART0_LSR]
+    set UART0_THR	    [regs UART0_THR]
+    set LSR_TEMT	    [regs LSR_TEMT]
+
+    # convert the 'char' to digit
+    set tmp [ scan $char %c ]
+    # /* wait for room in the tx FIFO on FFUART */
+    while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 }
+    mww $UART0_THR $tmp
+    if { $char == "\n" } { putcUART0 \r }
+}
+
+proc putsUART0 {str} {
+    set index 0
+    set len [string length $str]
+    while { $index < $len } {
+	putcUART0 [string index $str $index]
+	set index [expr {$index + 1}]
+    }
+}
+
+
+proc trainDDR2 {} {
+    set ARAM_BASEADDR	[regs ARAM_BASEADDR]
+
+    # you must have run 'reset init' or u-boot
+    # load the training code to ARAM
+    load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
+    # set PC to start of NOR (at boot 0x20000000 = 0x0)
+    reg pc $ARAM_BASEADDR
+    # run
+    resume
+}
+
+proc flashUBOOT {file} {
+    # this will update uboot on NOR partition
+    set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
+
+    # setup CS0 controller for NOR
+    setupNOR
+    # make sure we are accessing the lower part of NOR
+    lowGPIO5
+    flash probe 0
+    echo "Erasing sectors 0-3 for uboot"
+    putsUART0 "Erasing sectors 0-3 for uboot\n"
+    flash erase_sector 0 0 3
+    echo "Programming u-boot"
+    putsUART0 "Programming u-boot..."
+    arm11 memwrite burst enable
+    flash write_image $file $EXP_CS0_BASEADDR
+    arm11 memwrite burst disable
+    putsUART0 "done.\n"
+    putsUART0 "Rebooting, please wait!\n"
+    reboot
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100helper.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100helper.tcl
new file mode 100644
index 0000000..ba0e4fe
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100helper.tcl
@@ -0,0 +1,505 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc helpC100 {} {
+    echo "List of useful functions for C100 processor:"
+    echo "1)  reset init:        will set up your Telo board"
+    echo "2)  setupNOR:          will setup NOR access"
+    echo "3)  showNOR:           will show current NOR config registers for 16-bit, 16MB NOR"
+    echo "4)  setupGPIO:         will setup GPIOs for Telo board"
+    echo "5)  showGPIO:          will show current GPIO config registers"
+    echo "6)  highGPIO5:         will set GPIO5=NOR_addr22=1 to access upper 8MB"
+    echo "7)  lowGPIO5:          will set GPIO5=NOR_addr22=0 to access lower 8MB"
+    echo "8)  showAmbaClk:       will show current config registers for Amba Bus Clock"
+    echo "9)  setupAmbaClk:      will setup Amba Bus Clock=165MHz"
+    echo "10) showArmClk:        will show current config registers for Arm Bus Clock"
+    echo "11) setupArmClk:       will setup Amba Bus Clock=450MHz"
+    echo "12) ooma_board_detect: will show which version of Telo you have"
+    echo "13) setupDDR2:         will configure DDR2 controller, you must have PLLs configured"
+    echo "14) showDDR2:          will show DDR2 config registers"
+    echo "15) showWatchdog:      will show current register config for watchdog"
+    echo "16) reboot:            will trigger watchdog and reboot Telo (hw reset)"
+    echo "17) bootNOR:           will boot Telo from NOR"
+    echo "18) setupUART0:        will configure UART0 for 115200 8N1, PLLs have to be configured"
+    echo "19) putcUART0:         will print a character on UART0"
+    echo "20) putsUART0:         will print a string on UART0"
+    echo "21) trainDDR2:         will run DDR2 training program"
+    echo "22) flashUBOOT:        will program NOR sectors 0-3 with u-boot.bin"
+}
+
+source [find mem_helper.tcl]
+
+# read a 64-bit register (memory mapped)
+proc mr64bit {reg} {
+    return [read_memory $reg 32 2]
+}
+
+
+# write a 64-bit register (memory mapped)
+proc mw64bit {reg value} {
+    set high [expr {$value >> 32}]
+    set low  [expr {$value & 0xffffffff}]
+    #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
+    mww $reg $low
+    mww [expr {$reg+4}] $high
+}
+
+
+proc showNOR {} {
+    echo "This is the current NOR setup"
+    set EX_CSEN_REG	    [regs EX_CSEN_REG ]
+    set EX_CS0_SEG_REG	    [regs EX_CS0_SEG_REG ]
+    set EX_CS0_CFG_REG	    [regs EX_CS0_CFG_REG ]
+    set EX_CS0_TMG1_REG	    [regs EX_CS0_TMG1_REG ]
+    set EX_CS0_TMG2_REG	    [regs EX_CS0_TMG2_REG ]
+    set EX_CS0_TMG3_REG	    [regs EX_CS0_TMG3_REG ]
+    set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
+    set EX_MFSM_REG	    [regs EX_MFSM_REG ]
+    set EX_CSFSM_REG	    [regs EX_CSFSM_REG ]
+    set EX_WRFSM_REG	    [regs EX_WRFSM_REG ]
+    set EX_RDFSM_REG	    [regs EX_RDFSM_REG ]
+
+    echo [format "EX_CSEN_REG      (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
+    echo [format "EX_CS0_SEG_REG   (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
+    echo [format "EX_CS0_CFG_REG   (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
+    echo [format "EX_CS0_TMG1_REG  (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
+    echo [format "EX_CS0_TMG2_REG  (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
+    echo [format "EX_CS0_TMG3_REG  (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
+    echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
+    echo [format "EX_MFSM_REG      (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
+    echo [format "EX_CSFSM_REG     (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
+    echo [format "EX_WRFSM_REG     (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
+    echo [format "EX_RDFSM_REG     (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
+}
+
+
+
+proc showGPIO {} {
+    echo "This is the current GPIO register setup"
+    # GPIO outputs register
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
+    # GPIO Output Enable register
+    set GPIO_OE_REG		    [regs GPIO_OE_REG]
+    set GPIO_HI_INT_ENABLE_REG	    [regs GPIO_HI_INT_ENABLE_REG]
+    set GPIO_LO_INT_ENABLE_REG	    [regs GPIO_LO_INT_ENABLE_REG]
+    # GPIO input register
+    set GPIO_INPUT_REG		    [regs GPIO_INPUT_REG]
+    set APB_ACCESS_WS_REG	    [regs APB_ACCESS_WS_REG]
+    set MUX_CONF_REG		    [regs MUX_CONF_REG]
+    set SYSCONF_REG		    [regs SYSCONF_REG]
+    set GPIO_ARM_ID_REG		    [regs GPIO_ARM_ID_REG]
+    set GPIO_BOOTSTRAP_REG	    [regs GPIO_BOOTSTRAP_REG]
+    set GPIO_LOCK_REG		    [regs GPIO_LOCK_REG]
+    set GPIO_IOCTRL_REG		    [regs GPIO_IOCTRL_REG]
+    set GPIO_DEVID_REG		    [regs GPIO_DEVID_REG]
+
+    echo [format "GPIO_OUTPUT_REG       (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
+    echo [format "GPIO_OE_REG           (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
+    echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
+    echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
+    echo [format "GPIO_INPUT_REG        (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
+    echo [format "APB_ACCESS_WS_REG     (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
+    echo [format "MUX_CONF_REG          (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
+    echo [format "SYSCONF_REG           (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
+    echo [format "GPIO_ARM_ID_REG       (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
+    echo [format "GPIO_BOOTSTRAP_REG    (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
+    echo [format "GPIO_LOCK_REG         (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
+    echo [format "GPIO_IOCTRL_REG       (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
+    echo [format "GPIO_DEVID_REG        (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
+}
+
+
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
+proc showAmbaClk {} {
+    set CFG_REFCLKFREQ		     [config CFG_REFCLKFREQ]
+    set CLKCORE_AHB_CLK_CNTRL	     [regs CLKCORE_AHB_CLK_CNTRL]
+    set PLL_CLK_BYPASS	             [regs PLL_CLK_BYPASS]
+
+    echo [format "CLKCORE_AHB_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
+    set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1]
+    # see if the PLL is in bypass mode
+    set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
+    echo [format "PLL bypass bit: %d" $bypass]
+    if {$bypass == 1} {
+	echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
+    } else {
+	# nope, extract x,y,w and compute the PLL output freq.
+	set x [expr {($value & 0x0001F0000) >> 16}]
+	echo [format "x: %d" $x]
+	set y [expr {($value & 0x00000007F)}]
+	echo [format "y: %d" $y]
+	set w [expr {($value & 0x000000300) >> 8}]
+	echo [format "w: %d" $w]
+	echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
+    }
+}
+
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
+# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
+proc setupAmbaClk {} {
+    set CLKCORE_PLL_STATUS           [regs CLKCORE_PLL_STATUS]
+    set CLKCORE_AHB_CLK_CNTRL	     [regs CLKCORE_AHB_CLK_CNTRL]
+    set ARM_PLL_BY_CTRL	    [regs ARM_PLL_BY_CTRL]
+    set ARM_AHB_BYP	    [regs ARM_AHB_BYP]
+    set PLL_DISABLE	    [regs PLL_DISABLE]
+    set PLL_CLK_BYPASS	    [regs PLL_CLK_BYPASS]
+    set AHB_PLL_BY_CTRL	    [regs AHB_PLL_BY_CTRL]
+    set DIV_BYPASS	    [regs DIV_BYPASS]
+    set AHBCLK_PLL_LOCK	    [regs AHBCLK_PLL_LOCK]
+    set CFG_REFCLKFREQ		 [config CFG_REFCLKFREQ]
+    set CONFIG_SYS_HZ_CLOCK      [config CONFIG_SYS_HZ_CLOCK]
+    set w    [config w_amba]
+    set x    [config x_amba]
+    set y    [config y_amba]
+
+    echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]]
+    #echo [format "setupAmbaClk: w= %d" $w]
+    #echo [format "setupAmbaClk: x= %d" $x]
+    #echo [format "setupAmbaClk: y= %d" $y]
+    # set PLL into BYPASS mode using MUX
+    mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
+    # do an internal PLL bypass
+    mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
+    # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
+    # openocd smallest resolution is 1ms so, wait 1ms
+    sleep 1
+    # disable the PLL
+    mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
+    # wait 1ms
+    sleep 1
+    # enable the PLL
+    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
+    sleep 1
+    # set X, W and X
+    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
+    mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
+    # wait for PLL to lock
+    echo "Waiting for Amba PLL to lock"
+    while {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK == 0} { sleep 1 }
+    # remove the internal PLL bypass
+    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
+    # remove PLL from BYPASS mode using MUX
+    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
+}
+
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
+proc showArmClk {} {
+    set CFG_REFCLKFREQ		[config CFG_REFCLKFREQ]
+    set CLKCORE_ARM_CLK_CNTRL	[regs CLKCORE_ARM_CLK_CNTRL]
+    set PLL_CLK_BYPASS	        [regs PLL_CLK_BYPASS]
+
+    echo [format "CLKCORE_ARM_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
+    set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1]
+    # see if the PLL is in bypass mode
+    set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
+    echo [format "PLL bypass bit: %d" $bypass]
+    if {$bypass == 1} {
+	echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
+    } else {
+	# nope, extract x,y,w and compute the PLL output freq.
+	set x [expr {($value & 0x0001F0000) >> 16}]
+	echo [format "x: %d" $x]
+	set y [expr {($value & 0x00000007F)}]
+	echo [format "y: %d" $y]
+	set w [expr {($value & 0x000000300) >> 8}]
+	echo [format "w: %d" $w]
+	echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
+    }
+}
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
+# Arm Clock is used by two ARM1136 cores
+proc setupArmClk {} {
+    set CLKCORE_PLL_STATUS        [regs CLKCORE_PLL_STATUS]
+    set CLKCORE_ARM_CLK_CNTRL	  [regs CLKCORE_ARM_CLK_CNTRL]
+    set ARM_PLL_BY_CTRL	          [regs ARM_PLL_BY_CTRL]
+    set ARM_AHB_BYP	          [regs ARM_AHB_BYP]
+    set PLL_DISABLE	          [regs PLL_DISABLE]
+    set PLL_CLK_BYPASS	          [regs PLL_CLK_BYPASS]
+    set AHB_PLL_BY_CTRL	          [regs AHB_PLL_BY_CTRL]
+    set DIV_BYPASS	          [regs DIV_BYPASS]
+    set FCLK_PLL_LOCK	          [regs FCLK_PLL_LOCK]
+    set CFG_REFCLKFREQ		[config CFG_REFCLKFREQ]
+    set CFG_ARM_CLOCK		[config CFG_ARM_CLOCK]
+    set w    [config w_arm]
+    set x    [config x_arm]
+    set y    [config y_arm]
+
+    echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]]
+    #echo [format "setupArmClk: w= %d" $w]
+    #echo [format "setupArmaClk: x= %d" $x]
+    #echo [format "setupArmaClk: y= %d" $y]
+    # set PLL into BYPASS mode using MUX
+    mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
+    # do an internal PLL bypass
+    mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
+    # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
+    # openocd smallest resolution is 1ms so, wait 1ms
+    sleep 1
+    # disable the PLL
+    mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
+    # wait 1ms
+    sleep 1
+    # enable the PLL
+    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
+    sleep 1
+    # set X, W and X
+    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
+    mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
+    # wait for PLL to lock
+    echo "Waiting for Amba PLL to lock"
+    while {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK == 0} { sleep 1 }
+    # remove the internal PLL bypass
+    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
+    # remove PLL from BYPASS mode using MUX
+    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
+}
+
+
+
+proc setupPLL {} {
+    echo "PLLs setup"
+    setupAmbaClk
+    setupArmClk
+}
+
+# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
+proc setupDDR2 {} {
+    echo "Configuring DDR2"
+
+    set MEMORY_BASE_ADDR	    [regs  MEMORY_BASE_ADDR]
+    set MEMORY_MAX_ADDR	            [regs  MEMORY_MAX_ADDR]
+    set MEMORY_CR 		    [regs  MEMORY_CR]
+    set BLOCK_RESET_REG		    [regs  BLOCK_RESET_REG]
+    set DDR_RST		            [regs  DDR_RST]
+
+    # put DDR controller in reset (so that it is reset and correctly configured)
+    # this is only necessary if DDR was previously confiured
+    # and not reset.
+    mmw $BLOCK_RESET_REG 0x0 $DDR_RST
+
+    set M [expr {1024 * 1024}]
+    set DDR_SZ_1024M	[expr {1024 * $M}]
+    set DDR_SZ_256M	[expr {256 * $M}]
+    set DDR_SZ_128M	[expr {128 * $M}]
+    set DDR_SZ_64M	[expr {64 * $M}]
+    # ooma_board_detect returns DDR2 memory size
+    set tmp [ooma_board_detect]
+    if {$tmp == "128M"} {
+	echo "DDR2 size 128MB"
+	set ddr_size $DDR_SZ_128M
+    } elseif {$tmp == "256M"} {
+	echo "DDR2 size 256MB"
+	set ddr_size $DDR_SZ_256M
+    } else {
+	echo "Don't know how to handle this DDR2 size?"
+    }
+
+    # Memory setup register
+    mww $MEMORY_MAX_ADDR  [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}]
+    # disable ROM remap
+    mww $MEMORY_CR 0x0
+    # Take DDR controller out of reset
+    mmw $BLOCK_RESET_REG $DDR_RST 0x0
+    # min. 20 ops delay
+    sleep 1
+
+    # This will setup Denali DDR2 controller
+    if {$tmp == "128M"} {
+	configureDDR2regs_128M
+    } elseif {$tmp == "256M"} {
+	configureDDR2regs_256M
+    } else {
+	echo "Don't know how to configure DDR2 setup?"
+    }
+}
+
+
+
+proc showDDR2 {} {
+
+    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
+    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
+    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
+    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
+    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
+    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
+    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
+    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
+    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
+    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
+    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
+    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
+    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
+    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
+    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
+    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
+    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
+    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
+    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
+    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
+    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
+
+    set tmp [mr64bit $DENALI_CTL_00_DATA]
+    echo [format "DENALI_CTL_00_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_01_DATA]
+    echo [format "DENALI_CTL_01_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_02_DATA]
+    echo [format "DENALI_CTL_02_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_03_DATA]
+    echo [format "DENALI_CTL_03_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_04_DATA]
+    echo [format "DENALI_CTL_04_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_05_DATA]
+    echo [format "DENALI_CTL_05_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_06_DATA]
+    echo [format "DENALI_CTL_06_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_07_DATA]
+    echo [format "DENALI_CTL_07_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_08_DATA]
+    echo [format "DENALI_CTL_08_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_09_DATA]
+    echo [format "DENALI_CTL_09_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_10_DATA]
+    echo [format "DENALI_CTL_10_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_11_DATA]
+    echo [format "DENALI_CTL_11_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_12_DATA]
+    echo [format "DENALI_CTL_12_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_13_DATA]
+    echo [format "DENALI_CTL_13_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_14_DATA]
+    echo [format "DENALI_CTL_14_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_15_DATA]
+    echo [format "DENALI_CTL_15_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_16_DATA]
+    echo [format "DENALI_CTL_16_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_17_DATA]
+    echo [format "DENALI_CTL_17_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_18_DATA]
+    echo [format "DENALI_CTL_18_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_19_DATA]
+    echo [format "DENALI_CTL_19_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
+    set tmp [mr64bit $DENALI_CTL_20_DATA]
+    echo [format "DENALI_CTL_20_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
+
+}
+
+proc initC100 {} {
+    # this follows u-boot/cpu/arm1136/start.S
+    set GPIO_LOCK_REG		    [regs GPIO_LOCK_REG]
+    set GPIO_IOCTRL_REG		    [regs GPIO_IOCTRL_REG]
+    set GPIO_IOCTRL_VAL	            [regs GPIO_IOCTRL_VAL]
+    set APB_ACCESS_WS_REG           [regs APB_ACCESS_WS_REG]
+    set ASA_ARAM_BASEADDR	    [regs ASA_ARAM_BASEADDR]
+    set ASA_ARAM_TC_CR_REG	    [regs ASA_ARAM_TC_CR_REG]
+    set ASA_EBUS_BASEADDR	    [regs ASA_EBUS_BASEADDR]
+    set ASA_EBUS_TC_CR_REG	    [regs ASA_EBUS_TC_CR_REG]
+    set ASA_TC_REQIDMAEN	    [regs ASA_TC_REQIDMAEN]
+    set ASA_TC_REQTDMEN	            [regs ASA_TC_REQTDMEN]
+    set ASA_TC_REQIPSECUSBEN        [regs ASA_TC_REQIPSECUSBEN]
+    set ASA_TC_REQARM0EN	    [regs ASA_TC_REQARM0EN]
+    set ASA_TC_REQARM1EN	    [regs ASA_TC_REQARM1EN]
+    set ASA_TC_REQMDMAEN	    [regs ASA_TC_REQMDMAEN]
+    set INTC_ARM1_CONTROL_REG       [regs INTC_ARM1_CONTROL_REG]
+
+
+    # unlock writing to IOCTRL register
+    mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
+    # enable address lines A15-A21
+    mmw $GPIO_IOCTRL_REG 0xf 0x0
+    # set ARM into supervisor mode (SVC32)
+    # disable IRQ, FIQ
+    # Do I need this in JTAG mode?
+    # it really should be done as 'and ~0x1f | 0xd3 but
+    # openocd does not support this yet
+    reg cpsr 0xd3
+    #	/*
+    #	 * flush v4 I/D caches
+    #	 */
+    #	mov	r0, #0
+    #	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+    arm mcr 15 0 7 7 0 0x0
+    #	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+    arm mcr 15 0 8 7 0 0x0
+
+    #	/*
+    #	 * disable MMU stuff and caches
+    #	 */
+    #	mrc	p15, 0, r0, c1, c0, 0
+    arm mrc 15 0 1 0 0
+    #	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+    #	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+    #	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+    #	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+    #	orr	r0, r0, #0x00400000	@ set bit 22 (U)
+    #	mcr	p15, 0, r0, c1, c0, 0
+    arm mcr 15 0 1 0 0 0x401002
+    # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
+    # APB init
+    #    	// Setting APB Bus Wait states to 1, set post write
+    #	(*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
+    mww $APB_ACCESS_WS_REG 0x40
+    # AHB init
+    #	// enable all 6 masters for ARAM
+    mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
+    #	// enable all 6 masters for EBUS
+    mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
+
+    # ARAM init
+    #	// disable pipeline mode in ARAM
+    # I don't think this is documented anywhere?
+    mww $INTC_ARM1_CONTROL_REG 0x1
+    # configure clocks
+    setupPLL
+    # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.
+    setupUART0
+    # enable cache
+    # ? (u-boot does nothing here)
+    # DDR2 memory init
+    setupDDR2
+    putsUART0 "C100 initialization complete.\n"
+    echo "C100 initialization complete."
+}
+
+# show current state of watchdog timer
+proc showWatchdog {} {
+    set TIMER_WDT_HIGH_BOUND	[regs TIMER_WDT_HIGH_BOUND]
+    set TIMER_WDT_CONTROL	[regs TIMER_WDT_CONTROL]
+    set TIMER_WDT_CURRENT_COUNT	[regs TIMER_WDT_CURRENT_COUNT]
+
+    echo [format "TIMER_WDT_HIGH_BOUND    (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
+    echo [format "TIMER_WDT_CONTROL       (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
+    echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
+}
+
+# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
+# this will trigger watchdog reset
+# the sw. reset does not work on C100
+# watchdog reset effectively works as hw. reset
+proc reboot {} {
+    set TIMER_WDT_HIGH_BOUND	[regs TIMER_WDT_HIGH_BOUND]
+    set TIMER_WDT_CONTROL	[regs TIMER_WDT_CONTROL]
+    set TIMER_WDT_CURRENT_COUNT	[regs TIMER_WDT_CURRENT_COUNT]
+
+    # allow the counter to count to high value  before triggering
+    # this is because register writes are slow over JTAG and
+    # I don't want to miss the high_bound==curr_count condition
+    mww $TIMER_WDT_HIGH_BOUND  0xffffff
+    mww $TIMER_WDT_CURRENT_COUNT 0x0
+    echo "JTAG speed lowered to 100kHz"
+    adapter speed 100
+    mww $TIMER_WDT_CONTROL 0x1
+    # wait until the reset
+    echo -n "Waiting for watchdog to trigger..."
+    #while {[mrw $TIMER_WDT_CONTROL] == 1} {
+    #    echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
+    #    sleep 1
+    #
+    #}
+    while {[c100.cpu curstate] != "running"} { sleep 1}
+    echo "done."
+    echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100regs.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100regs.tcl
new file mode 100644
index 0000000..7be8939
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/c100regs.tcl
@@ -0,0 +1,495 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Note that I basically converted
+# u-boot/include/asm-arm/arch/comcerto_100.h
+# defines
+
+# this is a work-around for 'global' not working under Linux
+# access registers by calling this routine.
+# For example:
+# set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]
+proc regs {reg} {
+    return [dict get [regsC100] $reg ]
+}
+
+proc showreg {reg} {
+    echo [format "0x%x" [dict get [regsC100] $reg ]]
+}
+
+proc regsC100 {} {
+#/* memcore */
+#/* device memory base addresses */
+#// device memory sizes
+#/* ARAM SIZE=64K */
+dict set regsC100 ARAM_SIZE		0x00010000
+dict set regsC100 ARAM_BASEADDR	0x0A000000
+
+#/* Hardware Interface Units */
+dict set regsC100 APB_BASEADDR	0x10000000
+#/* APB_SIZE=16M address range */
+dict set regsC100 APB_SIZE		0x01000000
+
+dict set regsC100 EXP_CS0_BASEADDR       0x20000000
+dict set regsC100 EXP_CS1_BASEADDR       0x24000000
+dict set regsC100 EXP_CS2_BASEADDR       0x28000000
+dict set regsC100 EXP_CS3_BASEADDR       0x2C000000
+dict set regsC100 EXP_CS4_BASEADDR       0x30000000
+
+dict set regsC100 DDR_BASEADDR           0x80000000
+
+dict set regsC100 TDM_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x000000}]
+dict set regsC100 PHI_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x010000}]
+dict set regsC100 TDMA_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x020000}]
+dict set regsC100 ASA_DDR_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x040000}]
+dict set regsC100 ASA_ARAM_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x048000}]
+dict set regsC100 TIMER_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x050000}]
+dict set regsC100 ASD_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x060000}]
+dict set regsC100 GPIO_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x070000}]
+dict set regsC100 UART0_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x090000}]
+dict set regsC100 UART1_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x094000}]
+dict set regsC100 SPI_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x098000}]
+dict set regsC100 I2C_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x09C000}]
+dict set regsC100 INTC_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0A0000}]
+dict set regsC100 CLKCORE_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}]
+dict set regsC100 PUI_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}]
+dict set regsC100 GEMAC_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0D0000}]
+dict set regsC100 IDMA_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0E0000}]
+dict set regsC100 MEMCORE_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0F0000}]
+dict set regsC100 ASA_EBUS_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x100000}]
+dict set regsC100 ASA_AAB_BASEADDR	        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x108000}]
+dict set regsC100 GEMAC1_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x190000}]
+dict set regsC100 EBUS_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x1A0000}]
+dict set regsC100 MDMA_BASEADDR		[expr {[dict get $regsC100 APB_BASEADDR ] + 0x1E0000}]
+
+
+#////////////////////////////////////////////////////////////
+#//	AHB block											    //
+#////////////////////////////////////////////////////////////
+dict set regsC100 ASA_ARAM_PRI_REG	[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00}]
+dict set regsC100 ASA_ARAM_TC_REG	[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04}]
+dict set regsC100 ASA_ARAM_TC_CR_REG	[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08}]
+dict set regsC100 ASA_ARAM_STAT_REG	[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C}]
+
+dict set regsC100 ASA_EBUS_PRI_REG	[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00}]
+dict set regsC100 ASA_EBUS_TC_REG	[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04}]
+dict set regsC100 ASA_EBUS_TC_CR_REG	[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08}]
+dict set regsC100 ASA_EBUS_STAT_REG	[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C}]
+
+dict set regsC100 IDMA_MASTER		0
+dict set regsC100 TDMA_MASTER		1
+dict set regsC100 USBIPSEC_MASTER	2
+dict set regsC100 ARM0_MASTER		3
+dict set regsC100 ARM1_MASTER		4
+dict set regsC100 MDMA_MASTER		5
+
+#define IDMA_PRIORITY(level) (level)
+#define TDM_PRIORITY(level) (level << 4)
+#define USBIPSEC_PRIORITY(level) (level << 8)
+#define ARM0_PRIORITY(level) (level << 12)
+#define ARM1_PRIORITY(level) (level << 16)
+#define MDMA_PRIORITY(level) (level << 20)
+
+dict set regsC100 ASA_TC_REQIDMAEN	 [expr {1<<18}]
+dict set regsC100 ASA_TC_REQTDMEN	 [expr {1<<19}]
+dict set regsC100 ASA_TC_REQIPSECUSBEN [expr {1<<20}]
+dict set regsC100 ASA_TC_REQARM0EN	 [expr {1<<21}]
+dict set regsC100 ASA_TC_REQARM1EN	 [expr {1<<22}]
+dict set regsC100 ASA_TC_REQMDMAEN	 [expr {1<<23}]
+
+dict set regsC100 MEMORY_BASE_ADDR	0x80000000
+dict set regsC100 MEMORY_MAX_ADDR	[expr {[dict get $regsC100 ASD_BASEADDR ] + 0x10}]
+dict set regsC100 MEMORY_CR 		[expr {[dict get $regsC100 ASD_BASEADDR ] + 0x14}]
+dict set regsC100 ROM_REMAP_EN	0x1
+
+#define HAL_asb_priority(level) \
+#*(volatile unsigned *)ASA_PRI_REG = level
+
+#define HAL_aram_priority(level) \
+#*(volatile unsigned *)ASA_ARAM_PRI_REG = level
+
+#define HAL_aram_arbitration(arbitration_mask) \
+#*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask
+
+#define HAL_aram_defmaster(mask) \
+#*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24)
+
+#////////////////////////////////////////////////////////////
+#// INTC block						  //
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 INTC_ARM1_CONTROL_REG	[expr {[dict get $regsC100 INTC_BASEADDR ] + 0x18}]
+
+#////////////////////////////////////////////////////////////
+#// TIMER block						  //
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 TIMER0_CNTR_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x00}]
+dict set regsC100 TIMER0_CURR_COUNT	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x04}]
+dict set regsC100 TIMER1_CNTR_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x08}]
+dict set regsC100 TIMER1_CURR_COUNT	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x0C}]
+
+dict set regsC100 TIMER2_CNTR_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x18}]
+dict set regsC100 TIMER2_LBOUND_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x10}]
+dict set regsC100 TIMER2_HBOUND_REG	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x14}]
+dict set regsC100 TIMER2_CURR_COUNT	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x1C}]
+
+dict set regsC100 TIMER3_LOBND	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x20}]
+dict set regsC100 TIMER3_HIBND	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x24}]
+dict set regsC100 TIMER3_CTRL		[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x28}]
+dict set regsC100 TIMER3_CURR_COUNT	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x2C}]
+
+dict set regsC100 TIMER_MASK		[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x40}]
+dict set regsC100 TIMER_STATUS	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}]
+dict set regsC100 TIMER_ACK		[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}]
+dict set regsC100 TIMER_WDT_HIGH_BOUND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD0}]
+dict set regsC100 TIMER_WDT_CONTROL	[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD4}]
+dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD8}]
+
+
+
+#////////////////////////////////////////////////////////////
+#//  EBUS block
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 EX_SWRST_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x00}]
+dict set regsC100 EX_CSEN_REG		        [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x04}]
+dict set regsC100 EX_CS0_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x08}]
+dict set regsC100 EX_CS1_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x0C}]
+dict set regsC100 EX_CS2_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x10}]
+dict set regsC100 EX_CS3_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x14}]
+dict set regsC100 EX_CS4_SEG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x18}]
+dict set regsC100 EX_CS0_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x1C}]
+dict set regsC100 EX_CS1_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x20}]
+dict set regsC100 EX_CS2_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x24}]
+dict set regsC100 EX_CS3_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x28}]
+dict set regsC100 EX_CS4_CFG_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x2C}]
+dict set regsC100 EX_CS0_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x30}]
+dict set regsC100 EX_CS1_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x34}]
+dict set regsC100 EX_CS2_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x38}]
+dict set regsC100 EX_CS3_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x3C}]
+dict set regsC100 EX_CS4_TMG1_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x40}]
+dict set regsC100 EX_CS0_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x44}]
+dict set regsC100 EX_CS1_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x48}]
+dict set regsC100 EX_CS2_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x4C}]
+dict set regsC100 EX_CS3_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x50}]
+dict set regsC100 EX_CS4_TMG2_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x54}]
+dict set regsC100 EX_CS0_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x58}]
+dict set regsC100 EX_CS1_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x5C}]
+dict set regsC100 EX_CS2_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x60}]
+dict set regsC100 EX_CS3_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x64}]
+dict set regsC100 EX_CS4_TMG3_REG		[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x68}]
+dict set regsC100 EX_CLOCK_DIV_REG	        [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x6C}]
+
+dict set regsC100 EX_MFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}]
+dict set regsC100 EX_MFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}]
+dict set regsC100 EX_CSFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x104}]
+dict set regsC100 EX_WRFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x108}]
+dict set regsC100 EX_RDFSM_REG		[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x10C}]
+
+
+dict set regsC100 EX_CLK_EN		0x00000001
+dict set regsC100 EX_CSBOOT_EN	0x00000002
+dict set regsC100 EX_CS0_EN		0x00000002
+dict set regsC100 EX_CS1_EN		0x00000004
+dict set regsC100 EX_CS2_EN		0x00000008
+dict set regsC100 EX_CS3_EN		0x00000010
+dict set regsC100 EX_CS4_EN		0x00000020
+
+dict set regsC100 EX_MEM_BUS_8	0x00000000
+dict set regsC100 EX_MEM_BUS_16       0x00000002
+dict set regsC100 EX_MEM_BUS_32	0x00000004
+dict set regsC100 EX_CS_HIGH		0x00000008
+dict set regsC100 EX_WE_HIGH		0x00000010
+dict set regsC100 EX_RE_HIGH		0x00000020
+dict set regsC100 EX_ALE_MODE		0x00000040
+dict set regsC100 EX_STRB_MODE	0x00000080
+dict set regsC100 EX_DM_MODE		0x00000100
+dict set regsC100 EX_NAND_MODE	0x00000200
+dict set regsC100 EX_RDY_EN		0x00000400
+dict set regsC100 EX_RDY_EDGE		0x00000800
+
+#////////////////////////////////////////////////////////////
+#//  GPIO block
+#////////////////////////////////////////////////////////////
+
+# GPIO outputs register
+dict set regsC100 GPIO_OUTPUT_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x00}]
+# GPIO Output Enable register
+dict set regsC100 GPIO_OE_REG		        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x04}]
+dict set regsC100 GPIO_HI_INT_ENABLE_REG	[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x08}]
+dict set regsC100 GPIO_LO_INT_ENABLE_REG	[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x0C}]
+# GPIO input register
+dict set regsC100 GPIO_INPUT_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x10}]
+dict set regsC100 APB_ACCESS_WS_REG	        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x14}]
+dict set regsC100 MUX_CONF_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x18}]
+dict set regsC100 SYSCONF_REG		        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x1C}]
+dict set regsC100 GPIO_ARM_ID_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x30}]
+dict set regsC100 GPIO_BOOTSTRAP_REG	        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x40}]
+dict set regsC100 GPIO_LOCK_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x38}]
+dict set regsC100 GPIO_IOCTRL_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x44}]
+dict set regsC100 GPIO_DEVID_REG		[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x50}]
+
+dict set regsC100 GPIO_IOCTRL_A15A16	0x00000001
+dict set regsC100 GPIO_IOCTRL_A17A18	0x00000002
+dict set regsC100 GPIO_IOCTRL_A19A21	0x00000004
+dict set regsC100 GPIO_IOCTRL_TMREVT0	0x00000008
+dict set regsC100 GPIO_IOCTRL_TMREVT1	0x00000010
+dict set regsC100 GPIO_IOCTRL_GPBT3	0x00000020
+dict set regsC100 GPIO_IOCTRL_I2C	0x00000040
+dict set regsC100 GPIO_IOCTRL_UART0	0x00000080
+dict set regsC100 GPIO_IOCTRL_UART1	0x00000100
+dict set regsC100 GPIO_IOCTRL_SPI	0x00000200
+dict set regsC100 GPIO_IOCTRL_HBMODE	0x00000400
+
+dict set regsC100 GPIO_IOCTRL_VAL	0x55555555
+
+dict set regsC100 GPIO_0			0x01
+dict set regsC100 GPIO_1			0x02
+dict set regsC100 GPIO_2			0x04
+dict set regsC100 GPIO_3			0x08
+dict set regsC100 GPIO_4			0x10
+dict set regsC100 GPIO_5			0x20
+dict set regsC100 GPIO_6			0x40
+dict set regsC100 GPIO_7			0x80
+
+dict set regsC100 GPIO_RISING_EDGE	1
+dict set regsC100 GPIO_FALLING_EDGE	2
+dict set regsC100 GPIO_BOTH_EDGES	3
+
+#////////////////////////////////////////////////////////////
+#// UART
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 UART0_RBR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]
+dict set regsC100 UART0_THR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]
+dict set regsC100 UART0_DLL		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]
+dict set regsC100 UART0_IER		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}]
+dict set regsC100 UART0_DLH		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}]
+dict set regsC100 UART0_IIR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}]
+dict set regsC100 UART0_FCR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}]
+dict set regsC100 UART0_LCR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x0C}]
+dict set regsC100 UART0_MCR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x10}]
+dict set regsC100 UART0_LSR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x14}]
+dict set regsC100 UART0_MSR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x18}]
+dict set regsC100 UART0_SCR		[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x1C}]
+
+dict set regsC100 UART1_RBR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]
+dict set regsC100 UART1_THR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]
+dict set regsC100 UART1_DLL		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]
+dict set regsC100 UART1_IER		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}]
+dict set regsC100 UART1_DLH		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}]
+dict set regsC100 UART1_IIR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}]
+dict set regsC100 UART1_FCR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}]
+dict set regsC100 UART1_LCR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x0C}]
+dict set regsC100 UART1_MCR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x10}]
+dict set regsC100 UART1_LSR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x14}]
+dict set regsC100 UART1_MSR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x18}]
+dict set regsC100 UART1_SCR		[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x1C}]
+
+# /* default */
+dict set regsC100 LCR_CHAR_LEN_5		0x00
+dict set regsC100 LCR_CHAR_LEN_6		0x01
+dict set regsC100 LCR_CHAR_LEN_7		0x02
+dict set regsC100 LCR_CHAR_LEN_8		0x03
+#/* One stop bit! - default */
+dict set regsC100 LCR_ONE_STOP		0x00
+#/* Two stop bit! */
+dict set regsC100 LCR_TWO_STOP		0x04
+#/* Parity Enable */
+dict set regsC100 LCR_PEN			0x08
+dict set regsC100 LCR_PARITY_NONE		0x00
+#/* Even Parity Select */
+dict set regsC100 LCR_EPS			0x10
+#/* Enable Parity  Stuff */
+dict set regsC100 LCR_PS			0x20
+#/* Start Break */
+dict set regsC100 LCR_SBRK		        0x40
+#/* Parity Stuff Bit */
+dict set regsC100 LCR_PSB			0x80
+#/* UART 16550 Divisor Latch Assess */
+dict set regsC100 LCR_DLAB		        0x80
+
+#/* FIFO Error Status */
+dict set regsC100 LSR_FIFOE		[expr {1 << 7}]
+#/* Transmitter Empty */
+dict set regsC100 LSR_TEMT		[expr {1 << 6}]
+#/* Transmit Data Request */
+dict set regsC100 LSR_TDRQ		[expr {1 << 5}]
+#/* Break Interrupt */
+dict set regsC100 LSR_BI			[expr {1 << 4}]
+#/* Framing Error */
+dict set regsC100 LSR_FE			[expr {1 << 3}]
+#/* Parity Error */
+dict set regsC100 LSR_PE			[expr {1 << 2}]
+#/* Overrun Error */
+dict set regsC100 LSR_OE			[expr {1 << 1}]
+#/* Data Ready */
+dict set regsC100 LSR_DR			[expr {1 << 0}]
+
+#/* DMA Requests Enable */
+dict set regsC100 IER_DMAE		        [expr {1 << 7}]
+#/* UART Unit Enable */
+dict set regsC100 IER_UUE			[expr {1 << 6}]
+#/* NRZ coding Enable */
+dict set regsC100 IER_NRZE		        [expr {1 << 5}]
+#/* Receiver Time Out Interrupt Enable */
+dict set regsC100 IER_RTIOE		        [expr {1 << 4}]
+#/* Modem Interrupt Enable */
+dict set regsC100 IER_MIE			[expr {1 << 3}]
+#/* Receiver Line Status Interrupt Enable */
+dict set regsC100 IER_RLSE		        [expr {1 << 2}]
+#/* Transmit Data request Interrupt Enable */
+dict set regsC100 IER_TIE			[expr {1 << 1}]
+#/* Receiver Data Available Interrupt Enable */
+dict set regsC100 IER_RAVIE		        [expr {1 << 0}]
+
+#/* FIFO Mode Enable Status */
+dict set regsC100 IIR_FIFOES1		        [expr {1 << 7}]
+#/* FIFO Mode Enable Status */
+dict set regsC100 IIR_FIFOES0		        [expr {1 << 6}]
+#/* Time Out Detected */
+dict set regsC100 IIR_TOD			[expr {1 << 3}]
+#/* Interrupt Source Encoded */
+dict set regsC100 IIR_IID2		        [expr {1 << 2}]
+#/* Interrupt Source Encoded */
+dict set regsC100 IIR_IID1		        [expr {1 << 1}]
+#/* Interrupt Pending (active low) */
+dict set regsC100 IIR_IP			[expr {1 << 0}]
+
+#/* UART 16550 FIFO Control Register */
+dict set regsC100 FCR_FIFOEN		0x01
+dict set regsC100 FCR_RCVRRES		0x02
+dict set regsC100 FCR_XMITRES		0x04
+
+#/* Interrupt Enable Register */
+#// UART 16550
+#// Enable Received Data Available Interrupt
+dict set regsC100 IER_RXTH		0x01
+#// Enable Transmitter Empty Interrupt
+dict set regsC100 IER_TXTH		0x02
+
+
+
+#////////////////////////////////////////////////////////////
+#// CLK  + RESET block
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 CLKCORE_ARM_CLK_CNTRL	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x00}]
+dict set regsC100 CLKCORE_AHB_CLK_CNTRL	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x04}]
+dict set regsC100 CLKCORE_PLL_STATUS	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x08}]
+dict set regsC100 CLKCORE_CLKDIV_CNTRL	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C}]
+dict set regsC100 CLKCORE_TDM_CLK_CNTRL	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x10}]
+dict set regsC100 CLKCORE_FSYNC_CNTRL	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x14}]
+dict set regsC100 CLKCORE_CLK_PWR_DWN	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x18}]
+dict set regsC100 CLKCORE_RNG_CNTRL	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C}]
+dict set regsC100 CLKCORE_RNG_STATUS	        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x20}]
+dict set regsC100 CLKCORE_ARM_CLK_CNTRL2	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x24}]
+dict set regsC100 CLKCORE_TDM_REF_DIV_RST	[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x40}]
+
+dict set regsC100 ARM_PLL_BY_CTRL	0x80000000
+dict set regsC100 ARM_AHB_BYP		0x04000000
+dict set regsC100 PLL_DISABLE		0x02000000
+dict set regsC100 PLL_CLK_BYPASS	0x01000000
+
+dict set regsC100 AHB_PLL_BY_CTRL	0x80000000
+dict set regsC100 DIV_BYPASS		0x40000000
+dict set regsC100 SYNC_MODE		0x20000000
+
+dict set regsC100 EPHY_CLKDIV_BYPASS	0x00200000
+dict set regsC100 EPHY_CLKDIV_RATIO_SHIFT	16
+dict set regsC100 PUI_CLKDIV_BYPASS	0x00004000
+dict set regsC100 PUI_CLKDIV_SRCCLK	0x00002000
+dict set regsC100 PUI_CLKDIV_RATIO_SHIFT	8
+dict set regsC100 PCI_CLKDIV_BYPASS	0x00000020
+dict set regsC100 PCI_CLKDIV_RATIO_SHIFT	0
+
+dict set regsC100 ARM0_CLK_PD		0x00200000
+dict set regsC100 ARM1_CLK_PD		0x00100000
+dict set regsC100 EPHY_CLK_PD		0x00080000
+dict set regsC100 TDM_CLK_PD		0x00040000
+dict set regsC100 PUI_CLK_PD		0x00020000
+dict set regsC100 PCI_CLK_PD		0x00010000
+dict set regsC100 MDMA_AHBCLK_PD	0x00000400
+dict set regsC100 I2CSPI_AHBCLK_PD	0x00000200
+dict set regsC100 UART_AHBCLK_PD	0x00000100
+dict set regsC100 IPSEC_AHBCLK_PD	0x00000080
+dict set regsC100 TDM_AHBCLK_PD	0x00000040
+dict set regsC100 USB1_AHBCLK_PD	0x00000020
+dict set regsC100 USB0_AHBCLK_PD	0x00000010
+dict set regsC100 GEMAC1_AHBCLK_PD	0x00000008
+dict set regsC100 GEMAC0_AHBCLK_PD	0x00000004
+dict set regsC100 PUI_AHBCLK_PD	0x00000002
+dict set regsC100 HIF_AHBCLK_PD	0x00000001
+
+dict set regsC100 ARM1_DIV_BP		0x00001000
+dict set regsC100 ARM1_DIV_VAL_SHIFT	8
+dict set regsC100 ARM0_DIV_BP		0x00000010
+dict set regsC100 ARM0_DIV_VAL_SHIFT	0
+
+dict set regsC100 AHBCLK_PLL_LOCK	0x00000002
+dict set regsC100 FCLK_PLL_LOCK	0x00000001
+
+
+#// reset block
+dict set regsC100 BLOCK_RESET_REG		[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x100}]
+dict set regsC100 CSP_RESET_REG		[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x104}]
+
+dict set regsC100 RNG_RST		0x1000
+dict set regsC100 IPSEC_RST		0x0800
+dict set regsC100 DDR_RST		0x0400
+dict set regsC100 USB1_PHY_RST	0x0200
+dict set regsC100 USB0_PHY_RST	0x0100
+dict set regsC100 USB1_RST		0x0080
+dict set regsC100 USB0_RST		0x0040
+dict set regsC100 GEMAC1_RST		0x0020
+dict set regsC100 GEMAC0_RST		0x0010
+dict set regsC100 TDM_RST		0x0008
+dict set regsC100 PUI_RST		0x0004
+dict set regsC100 HIF_RST		0x0002
+dict set regsC100 PCI_RST		0x0001
+
+#////////////////////////////////////////////////////////////////
+#//	DDR  CONTROLLER block
+#////////////////////////////////////////////////////////////////
+
+dict set regsC100 DDR_CONFIG_BASEADDR	0x0D000000
+dict set regsC100 DENALI_CTL_00_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00}]
+dict set regsC100 DENALI_CTL_01_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08}]
+dict set regsC100 DENALI_CTL_02_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10}]
+dict set regsC100 DENALI_CTL_03_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18}]
+dict set regsC100 DENALI_CTL_04_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20}]
+dict set regsC100 DENALI_CTL_05_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28}]
+dict set regsC100 DENALI_CTL_06_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30}]
+dict set regsC100 DENALI_CTL_07_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38}]
+dict set regsC100 DENALI_CTL_08_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40}]
+dict set regsC100 DENALI_CTL_09_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48}]
+dict set regsC100 DENALI_CTL_10_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50}]
+dict set regsC100 DENALI_CTL_11_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58}]
+dict set regsC100 DENALI_CTL_12_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60}]
+dict set regsC100 DENALI_CTL_13_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68}]
+dict set regsC100 DENALI_CTL_14_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70}]
+dict set regsC100 DENALI_CTL_15_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78}]
+dict set regsC100 DENALI_CTL_16_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80}]
+dict set regsC100 DENALI_CTL_17_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88}]
+dict set regsC100 DENALI_CTL_18_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90}]
+dict set regsC100 DENALI_CTL_19_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98}]
+dict set regsC100 DENALI_CTL_20_DATA	[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0}]
+
+# 32-bit value
+dict set regsC100 DENALI_READY_CHECK         [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44}]
+# 8-bit
+dict set regsC100 DENALI_WR_DQS              [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D}]
+# 8-bit
+dict set regsC100 DENALI_DQS_OUT             [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A}]
+# 8-bit
+dict set regsC100 DENALI_DQS_DELAY0          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F}]
+# 8-bit
+dict set regsC100 DENALI_DQS_DELAY1          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50}]
+# 8-bit
+dict set regsC100 DENALI_DQS_DELAY2          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51}]
+# 8-bit
+dict set regsC100 DENALI_DQS_DELAY3          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52}]
+
+
+# end of proc regsC100
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/cavium_cn61xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/cavium_cn61xx.cfg
new file mode 100644
index 0000000..60b56a5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/cavium_cn61xx.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Cavium Octeon II CN61xx (PrID 0x000D9301)
+
+jtag newtap cpu tap0 -irlen 5
+jtag newtap cpu tap1 -irlen 5
+
+target create cpu.core0 mips_mips64 -chain-position cpu.tap0 -endian big -rtos hwthread -coreid 0
+target create cpu.core1 mips_mips64 -chain-position cpu.tap1 -endian big -rtos hwthread -coreid 1
+target smp cpu.core0 cpu.core1
+
+cpu.core0 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000
+cpu.core1 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000
+
+targets cpu.core0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/cc2538.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/cc2538.cfg
new file mode 100644
index 0000000..e4fb02a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/cc2538.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config for Texas Instruments low power RF SoC CC2538
+# http://www.ti.com/lit/pdf/swru319
+
+adapter speed 100
+
+source [find target/icepick.cfg]
+source [find target/ti-cjtag.cfg]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cc2538
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x8B96402F
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+#
+# ICEpick-C (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID 0x8B96402F
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+# A start sequence is needed to change from cJTAG (Compact JTAG) to
+# 4-pin JTAG before talking via JTAG commands
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
+jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
+
+#
+# Cortex-M3 target
+#
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/cs351x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/cs351x.cfg
new file mode 100644
index 0000000..e67540a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/cs351x.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME cs351x
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x00526fa1
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# There is 16K of SRAM on this chip
+# FIXME: flash programming is not working by using this work area. So comment this out for now.
+#$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1
+
+# This chip has a DCC ... use it
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/davinci.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/davinci.cfg
new file mode 100644
index 0000000..54afb64
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/davinci.cfg
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Utility code for DaVinci-family chips
+#
+
+# davinci_pinmux: assigns PINMUX$reg <== $value
+proc davinci_pinmux {soc reg value} {
+	mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value
+}
+
+source [find mem_helper.tcl]
+
+#
+# pll_setup: initialize PLL
+#  - pll_addr ... physical addr of controller
+#  - mult ... pll multiplier
+#  - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
+#
+# For PLLs that don't have a given register (e.g. plldiv8), or where a
+# given divider is non-programmable, caller provides *NO* config mapping.
+#
+
+# PLL version 0x02: tested on dm355
+# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
+proc pll_v02_setup {pll_addr mult config} {
+	set pll_ctrl_addr [expr {$pll_addr + 0x100}]
+	set pll_ctrl [mrw $pll_ctrl_addr]
+
+	# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
+	# NOTE: this assumes we should clear that bit
+	set pll_ctrl [expr {$pll_ctrl & ~0x0100}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 2 - clear PLLENSRC (bit 5)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 3 - clear PLLEN (bit 0) ... enter bypass mode
+	set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 4 - wait at least 4 refclk cycles
+	sleep 1
+
+	# 5 - set PLLRST (bit 3)
+	set pll_ctrl [expr {$pll_ctrl | 0x0008}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 6 - set PLLDIS (bit 4)
+	set pll_ctrl [expr {$pll_ctrl | 0x0010}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 7 - clear PLLPWRDN (bit 1)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 8 - clear PLLDIS (bit 4)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0010}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 9 - optional: write prediv, postdiv, and pllm
+	# NOTE: for dm355 PLL1, postdiv is controlled via MISC register
+	mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}]
+	if { [dict exists $config prediv] } {
+		set div [dict get $config prediv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0114}] $div
+	}
+	if { [dict exists $config postdiv] } {
+		set div [dict get $config postdiv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0128}] $div
+	}
+
+	# 10 - optional: set plldiv1, plldiv2, ...
+	# NOTE:  this assumes some registers have their just-reset values:
+	#	- PLLSTAT.GOSTAT is clear when we enter
+	#	- ALNCTL has everything set
+	set go 0
+	if { [dict exists $config div1] } {
+		set div [dict get $config div1]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0118}] $div
+		set go 1
+	}
+	if { [dict exists $config div2] } {
+		set div [dict get $config div2]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x011c}] $div
+		set go 1
+	}
+	if { [dict exists $config div3] } {
+		set div [dict get $config div3]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0120}] $div
+		set go 1
+	}
+	if { [dict exists $config div4] } {
+		set div [dict get $config div4]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0160}] $div
+		set go 1
+	}
+	if { [dict exists $config div5] } {
+		set div [dict get $config div5]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0164}] $div
+		set go 1
+	}
+	if {$go != 0} {
+		# write pllcmd.GO; poll pllstat.GO
+		mww [expr {$pll_addr + 0x0138}] 0x01
+		set pllstat [expr {$pll_addr + 0x013c}]
+		while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
+	}
+	mww [expr {$pll_addr + 0x0138}] 0x00
+
+	# 11 - wait at least 5 usec for reset to finish
+	# (assume covered by overheads including JTAG messaging)
+
+	# 12 - clear PLLRST (bit 3)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 13 - wait at least 8000 refclk cycles for PLL to lock
+	# if we assume 24 MHz (slowest osc), that's 1/3 msec
+	sleep 3
+
+	# 14 - set PLLEN (bit 0) ... leave bypass mode
+	set pll_ctrl [expr {$pll_ctrl | 0x0001}]
+	mww $pll_ctrl_addr $pll_ctrl
+}
+
+# PLL version 0x03: tested on dm365
+proc pll_v03_setup {pll_addr mult config} {
+	set pll_ctrl_addr [expr {$pll_addr + 0x100}]
+	set pll_secctrl_addr [expr {$pll_addr + 0x108}]
+	set pll_ctrl [mrw $pll_ctrl_addr]
+
+	# 1 - power up the PLL
+	set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 2 - clear PLLENSRC (bit 5)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 2 - clear PLLEN (bit 0) ... enter bypass mode
+	set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 3 - wait at least 4 refclk cycles
+	sleep 1
+
+	# 4 - set PLLRST (bit 3)
+	set pll_ctrl [expr {$pll_ctrl | 0x0008}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 5 - wait at least 5 usec
+	sleep 1
+
+	# 6 - clear PLLRST (bit 3)
+	set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 9 - optional: write prediv, postdiv, and pllm
+	mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}]
+	if { [dict exists $config prediv] } {
+		set div [dict get $config prediv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0114}] $div
+	}
+	if { [dict exists $config postdiv] } {
+		set div [dict get $config postdiv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0128}] $div
+	}
+
+	# 10 - write start sequence to PLLSECCTL
+	mww $pll_secctrl_addr 0x00470000
+	mww $pll_secctrl_addr 0x00460000
+	mww $pll_secctrl_addr 0x00400000
+	mww $pll_secctrl_addr 0x00410000
+
+	# 11 - optional: set plldiv1, plldiv2, ...
+	# NOTE: this assumes some registers have their just-reset values:
+	#	- PLLSTAT.GOSTAT is clear when we enter
+	set aln 0
+	if { [dict exists $config div1] } {
+		set div [dict get $config div1]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0118}] $div
+		set aln [expr {$aln | 0x1}]
+	} else {
+		mww [expr {$pll_addr + 0x0118}] 0
+	}
+	if { [dict exists $config div2] } {
+		set div [dict get $config div2]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x011c}] $div
+		set aln [expr {$aln | 0x2}]
+	} else {
+		mww [expr {$pll_addr + 0x011c}] 0
+	}
+	if { [dict exists $config div3] } {
+		set div [dict get $config div3]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0120}] $div
+		set aln [expr {$aln | 0x4}]
+	} else {
+		mww [expr {$pll_addr + 0x0120}] 0
+	}
+	if { [dict exists $config oscdiv] } {
+		set div [dict get $config oscdiv]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0124}] $div
+	} else {
+		mww [expr {$pll_addr + 0x0124}] 0
+	}
+	if { [dict exists $config div4] } {
+		set div [dict get $config div4]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0160}] $div
+		set aln [expr {$aln | 0x8}]
+	} else {
+		mww [expr {$pll_addr + 0x0160}] 0
+	}
+	if { [dict exists $config div5] } {
+		set div [dict get $config div5]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0164}] $div
+		set aln [expr {$aln | 0x10}]
+	} else {
+		mww [expr {$pll_addr + 0x0164}] 0
+	}
+	if { [dict exists $config div6] } {
+		set div [dict get $config div6]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0168}] $div
+		set aln [expr {$aln | 0x20}]
+	} else {
+		mww [expr {$pll_addr + 0x0168}] 0
+	}
+	if { [dict exists $config div7] } {
+		set div [dict get $config div7]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x016c}] $div
+		set aln [expr {$aln | 0x40}]
+	} else {
+		mww [expr {$pll_addr + 0x016c}] 0
+	}
+	if { [dict exists $config div8] } {
+		set div [dict get $config div8]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0170}] $div
+		set aln [expr {$aln | 0x80}]
+	} else {
+		mww [expr {$pll_addr + 0x0170}] 0
+	}
+	if { [dict exists $config div9] } {
+		set div [dict get $config div9]
+		set div [expr {0x8000 | ($div - 1)}]
+		mww [expr {$pll_addr + 0x0174}] $div
+		set aln [expr {$aln | 0x100}]
+	} else {
+		mww [expr {$pll_addr + 0x0174}] 0
+	}
+	if {$aln != 0} {
+		# clear pllcmd.GO
+		mww [expr {$pll_addr + 0x0138}] 0x00
+		# write alignment flags
+		mww [expr {$pll_addr + 0x0140}] $aln
+		# write pllcmd.GO; poll pllstat.GO
+		mww [expr {$pll_addr + 0x0138}] 0x01
+		set pllstat [expr {$pll_addr + 0x013c}]
+		while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
+	}
+	mww [expr {$pll_addr + 0x0138}] 0x00
+	set addr [dict get $config ctladdr]
+	while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 }
+
+	# 12 - set PLLEN (bit 0) ... leave bypass mode
+	set pll_ctrl [expr {$pll_ctrl | 0x0001}]
+	mww $pll_ctrl_addr $pll_ctrl
+}
+
+# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
+# modules can be enabled.
+
+# prepare a non-DSP module to be enabled; finish with psc_go
+proc psc_enable {module} {
+	set psc_addr 0x01c41000
+	# write MDCTL
+	mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f
+}
+
+# prepare a non-DSP module to be reset; finish with psc_go
+proc psc_reset {module} {
+	set psc_addr 0x01c41000
+	# write MDCTL
+	mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f
+}
+
+# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
+proc psc_go {} {
+	set psc_addr 0x01c41000
+	set ptstat_addr [expr {$psc_addr + 0x0128}]
+
+	# just in case PTSTAT.go isn't clear
+	while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
+
+	# write PTCMD.go ... ignoring any DSP power domain
+	mww [expr {$psc_addr + 0x0120}] 1
+
+	# wait for PTSTAT.go to clear (again ignoring DSP power domain)
+	while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
+}
+
+#
+# A reset using only SRST is a "Warm Reset", resetting everything in the
+# chip except ARM emulation (and everything _outside_ the chip that hooks
+# up to SRST).  But many boards don't expose SRST via their JTAG connectors
+# (it's not present on TI-14 headers).
+#
+# From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except
+# without any board-wide side effects, since it's triggered using JTAG using
+# either (a) ARM watchdog timer, or (b) ICEpick.
+#
+proc davinci_wdog_reset {} {
+	set timer2_phys 0x01c21c00
+
+	# NOTE -- on entry
+	#   - JTAG communication with the ARM *must* be working OK; this
+	#     may imply using adaptive clocking or disabling WFI-in-idle
+	#   - current target must be the DaVinci ARM
+	#   - that ARM core must be halted
+	#   - timer2 clock is still enabled (PSC 29 on most chips)
+
+	#
+	# Part I -- run regardless of being halted via JTAG
+	#
+	# NOTE:  for now, we assume there's no DSP that could control the
+	# watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog
+	# suspend signal is controlled via ARM emulation suspend.
+	#
+
+	# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
+	mww phys [expr {$timer2_phys + 0x28}] 0x00004000
+
+	#
+	# Part II -- in case watchdog hasn't been set up
+	#
+
+	# TCR: disable, force internal clock source
+	mww phys [expr {$timer2_phys + 0x20}] 0
+
+	# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
+	mww phys [expr {$timer2_phys + 0x24}] 0
+	mww phys [expr {$timer2_phys + 0x24}] 0x110b
+
+	# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
+	# so watchdog triggers ASAP
+	mww phys [expr {$timer2_phys + 0x10}] 0
+	mww phys [expr {$timer2_phys + 0x14}] 0
+	mww phys [expr {$timer2_phys + 0x18}] 0
+	mww phys [expr {$timer2_phys + 0x1c}] 0
+
+	# WDTCR: put into pre-active state, then active
+	mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000
+	mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000
+
+	#
+	# Part III -- it's ready to rumble
+	#
+
+	# WDTCR: write invalid WDKEY to trigger reset
+	mww phys [expr {$timer2_phys + 0x28}] 0x00004000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dragonite.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dragonite.cfg
new file mode 100644
index 0000000..249de25
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dragonite.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Marvell Dragonite CPU core
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dragonite
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x121003d3
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
+
+reset_config trst_and_srst
+adapter srst delay 200
+jtag_ntrst_delay 200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dsp56321.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dsp56321.cfg
new file mode 100644
index 0000000..fac0ccc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dsp56321.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Script for freescale DSP56321
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dsp56321
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a big endian
+   set _ENDIAN big
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1181501d
+}
+
+#jtag speed
+adapter speed 4500
+
+#has only srst
+reset_config srst_only
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id $_CPUTAPID
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dsp563xx -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#working area at base of ram
+$_TARGETNAME configure -work-area-virt 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dsp568013.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dsp568013.cfg
new file mode 100644
index 0000000..5cf5c02
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dsp568013.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Script for freescale DSP568013
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dsp568013
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a big endian
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x01f2401d
+}
+
+#jtag speed
+adapter speed 800
+
+reset_config srst_only
+
+#MASTER tap
+jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
+
+#CORE tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
+
+#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Setup the interesting tap
+# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations require certain instruction to be in the IR register during reset, and polling would change this)
+jtag configure $_CHIPNAME.chp -event setup "
+     jtag tapenable $_TARGETNAME
+     poll off
+"
+
+#select CORE tap by modifying the TLM register.
+#to be used when MASTER tap is selected.
+jtag configure $_TARGETNAME -event tap-enable "
+     irscan $_CHIPNAME.chp 0x05;
+     drscan $_CHIPNAME.chp 4 0x02;
+     jtag tapdisable $_CHIPNAME.chp;
+"
+
+#select MASTER tap by modifying the TLM register.
+#to be used when CORE tap is selected.
+jtag configure $_CHIPNAME.chp -event tap-enable "
+     irscan $_TARGETNAME 0x08;
+     drscan $_TARGETNAME 4 0x1;
+     jtag tapdisable $_TARGETNAME;
+"
+
+#disables the master tap
+jtag configure $_TARGETNAME -event tap-disable "
+"
+#TODO FIND SMARTER WAY.
+
+jtag configure $_CHIPNAME.chp -event tap-disable "
+"
+#TODO FIND SMARTER WAY.
+
+
+#working area at base of ram
+$_TARGETNAME configure -work-area-virt 0
+
+#setup flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dsp568037.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dsp568037.cfg
new file mode 100644
index 0000000..5d86811
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/dsp568037.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Script for freescale DSP568037
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dsp568037
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a big endian
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x01f2801d
+}
+
+#jtag speed
+adapter speed 800
+
+reset_config srst_only
+
+#MASTER tap
+jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
+
+#CORE tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
+
+#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Setup the interesting tap
+jtag configure $_CHIPNAME.chp -event setup "jtag tapenable $_TARGETNAME"
+
+#select CORE tap by modifying the TLM register.
+#to be used when MASTER tap is selected.
+jtag configure $_TARGETNAME -event tap-enable "
+     irscan $_CHIPNAME.chp 0x05;
+     drscan $_CHIPNAME.chp 4 0x02;
+     jtag tapdisable $_CHIPNAME.chp;
+"
+
+#select MASTER tap by modifying the TLM register.
+#to be used when CORE tap is selected.
+jtag configure $_CHIPNAME.chp -event tap-enable "
+     irscan $_TARGETNAME 0x08;
+     drscan $_TARGETNAME 4 0x1;
+     jtag tapdisable $_TARGETNAME;
+"
+
+#disables the master tap
+jtag configure $_TARGETNAME -event tap-disable "
+"
+#TODO FIND SMARTER WAY.
+
+jtag configure $_CHIPNAME.chp -event tap-disable "
+"
+#TODO FIND SMARTER WAY.
+
+
+#working area at base of ram
+$_TARGETNAME configure -work-area-virt 0
+
+#setup flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/efm32.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/efm32.cfg
new file mode 100644
index 0000000..2187c0a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/efm32.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Silicon Labs (formerly Energy Micro) EFM32 target
+#
+# Note: All EFM32 chips have SWD support, but only newer series 1
+# chips have JTAG support.
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME efm32
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+adapter speed 1000
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
+flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
+flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/em357.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/em357.cfg
new file mode 100644
index 0000000..ddefa28
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/em357.cfg
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Target configuration for the Silicon Labs EM357 chips
+#
+
+#
+# em357 family supports JTAG and SWD transports
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME em357
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x3ba00477
+   } else {
+      set _CPUTAPID 0x1ba00477
+   }
+}
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+  set _BSTAPID 0x069a962b
+}
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME em358
+}
+
+if { [info exists FLASHSIZE] } {
+    set _FLASHSIZE $FLASHSIZE
+} else {
+    set _FLASHSIZE 0x30000
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+if { [using_jtag] } {
+    jtag newtap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME em357 0x08000000 $_FLASHSIZE 0 0 $_TARGETNAME
+
+if { ![using_hla]} {
+# according to errata, we need to use vectreset rather than sysresetreq to avoid lockup
+# There is a bug in the chip, which means that when using external debuggers the chip
+# may lock up in certain CPU clock modes. Affected modes are operating the CPU at
+# 24MHz derived from the 24MHz crystal, or 12MHz derived from the high frequency RC
+# oscillator. If an external debugger tool asserts SYSRESETREQ, the chip will lock up and
+# require a pin reset or power cycle.
+#
+# for details, refer to:
+# http://www.silabs.com/Support%20Documents/TechnicalDocs/EM35x-Errata.pdf
+    cortex_m reset_config vectreset
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/em358.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/em358.cfg
new file mode 100644
index 0000000..63f4088
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/em358.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Silicon Labs EM358 chips
+
+#
+# em357 family supports JTAG and SWD transports
+#
+
+if { ![info exists CHIPNAME] } {
+   set CHIPNAME em358
+}
+
+if { ![info exists BSTAPID] } {
+  set BSTAPID 0x069aa62b
+}
+
+# 512K of flash in the em358 chips
+set FLASHSIZE 0x80000
+source [find target/em357.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/eos_s3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/eos_s3.cfg
new file mode 100644
index 0000000..150ef4e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/eos_s3.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# QuickLogic EOS S3
+# https://www.quicklogic.com/products/soc/eos-s3-microcontroller/
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME eos_s3
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x80000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# For now we use SRAM only for software upload
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+adapter speed 4000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/epc9301.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/epc9301.cfg
new file mode 100644
index 0000000..41021d5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/epc9301.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME ep9301
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # Force an error until we get a good number.
+   set _CPUTAPID 0xffffffff
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
+
+#flash configuration
+#flash bank      [driver_options ...]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x60000000 0x1000000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esi32xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esi32xx.cfg
new file mode 100644
index 0000000..d29c636
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esi32xx.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# EnSilica eSi-32xx SoC (eSi-RISC Family)
+# http://www.ensilica.com/risc-ip/
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME esi32xx
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x11234001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME esirisc -chain-position $_CHIPNAME.cpu
+
+# Targets with the UNIFIED_ADDRESS_SPACE option disabled should set
+# CACHEARCH to 'harvard'. By default, 'von_neumann' is assumed.
+if { [info exists CACHEARCH] } {
+    $_TARGETNAME esirisc cache_arch $CACHEARCH
+}
+
+adapter speed 2000
+
+reset_config none
+
+# The default linker scripts provided by the eSi-RISC toolchain do not
+# specify attributes on memory regions, which results in incorrect
+# application of software breakpoints by GDB.
+gdb breakpoint_override hard
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32.cfg
new file mode 100644
index 0000000..b30a170
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"esp32"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH 					"xtensa"
+set _ONLYCPU					3
+set _FLASH_VOLTAGE 				3.3
+set _ESP_SMP_TARGET				1
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG 	0x3ff5A004
+
+if { [info exists ESP32_ONLYCPU] } {
+	set _ONLYCPU $ESP32_ONLYCPU
+}
+
+if { [info exists ESP32_FLASH_VOLTAGE] } {
+	set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
+}
+
+proc esp32_memprot_is_enabled { } {
+	return 0
+}
+
+proc esp32_soc_reset { } {
+	soft_reset_halt
+}
+
+create_esp_target $_ESP_ARCH
+
+source [find target/xtensa-core-esp32.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32c2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32c2.cfg
new file mode 100644
index 0000000..42aeb0a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32c2.cfg
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x0000cc25
+set _ESP_ARCH 					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60008840
+
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
+    # Halt event can occur during config phase (before "init" is done).
+    # Ignore it since mww commands don't work at that time.
+    if { [string compare [command mode] config] == 0 } {
+        return
+    }
+
+    # Timer Group 0 WDT
+    mww 0x6001f064 0x50D83AA1
+    mww 0x6001F048 0
+    # RTC WDT
+    mww 0x6000809C 0x50D83AA1
+    mww 0x60008084 0
+    # SWD
+    mww 0x600080A4 0x8F1D312A
+    mww 0x600080A0 0x84B00000
+}
+
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL
+
+    # This procedure does "digital system reset", i.e. resets
+    # all the peripherals except for the RTC block.
+    # It is called from reset-assert-post target event callback,
+    # after assert_reset procedure was called.
+    # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
+    # temporarily take it out of reset. Save the dmcontrol state before
+    # doing so.
+    riscv dmi_write $_RISCV_DMCONTROL 0x80000001
+    # Trigger the reset
+    mww 0x60008000 0x9c00a000
+    # Workaround for stuck in cpu start during calibration.
+    # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
+    mww 0x6001F068 0
+    # Wait for the reset to happen
+    sleep 10
+    poll
+    # Disable the watchdogs again
+    riscv_wdt_disable
+
+    # Here debugger reads allresumeack and allhalted bits as set (0x330a2)
+    # We will clean allhalted state by resuming the core.
+    riscv dmi_write $_RISCV_DMCONTROL 0x40000001
+
+    # Put the hart back into reset state. Note that we need to keep haltreq set.
+    riscv dmi_write $_RISCV_DMCONTROL 0x80000003
+}
+
+proc riscv_memprot_is_enabled { } {
+	global _RISCV_ABS_CMD _RISCV_ABS_DATA0
+
+	# PMPADDR 0-1 covers entire valid IRAM range and PMPADDR 2-3 covers entire DRAM region
+	# pmpcfg0 holds the configuration for the PMP 0-3 address registers
+
+	# read pmpcfg0 and extract into 8-bit variables.
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203a0
+	set pmpcfg0 [riscv dmi_read $_RISCV_ABS_DATA0]
+
+	set pmp0cfg [expr {($pmpcfg0 >> (8 * 0)) & 0xFF}]
+	set pmp1cfg [expr {($pmpcfg0 >> (8 * 1)) & 0xFF}]
+	set pmp2cfg [expr {($pmpcfg0 >> (8 * 2)) & 0xFF}]
+	set pmp3cfg [expr {($pmpcfg0 >> (8 * 3)) & 0xFF}]
+
+	# read PMPADDR 0-3
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b0
+	set pmpaddr0 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b1
+	set pmpaddr1 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b2
+	set pmpaddr2 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b3
+	set pmpaddr3 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+
+	set IRAM_LOW 	0x40380000
+	set IRAM_HIGH 	0x403C0000
+	set DRAM_LOW 	0x3FCA0000
+	set DRAM_HIGH 	0x3FCE0000
+	set PMP_RWX     0x07
+	set PMP_RW     	0x03
+
+	# The lock bit remains unset during the execution of the 2nd stage bootloader.
+	# Thus we do not perform a lock bit check for IRAM and DRAM regions.
+
+	# Check OpenOCD can write and execute from IRAM.
+	if {$pmpaddr0 >= $IRAM_LOW && $pmpaddr1 <= $IRAM_HIGH} {
+    	if {($pmp0cfg & $PMP_RWX) != 0 || ($pmp1cfg & $PMP_RWX) != $PMP_RWX} {
+			return 1
+		}
+	}
+
+	# Check OpenOCD can read/write entire DRAM region.
+	if {$pmpaddr2 >= $DRAM_LOW && $pmpaddr3 <= $DRAM_HIGH} {
+    	if {($pmp2cfg & $PMP_RW) != 0 && ($pmp3cfg & $PMP_RW) != $PMP_RW} {
+			return 1
+		}
+	}
+
+	return 0
+}
+
+create_esp_target $_ESP_ARCH
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32c3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32c3.cfg
new file mode 100644
index 0000000..d266ad5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32c3.cfg
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x00005c25
+set _ESP_ARCH					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60008844
+
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
+    # Halt event can occur during config phase (before "init" is done).
+    # Ignore it since mww commands don't work at that time.
+    if { [string compare [command mode] config] == 0 } {
+        return
+    }
+
+    # Timer Group 0 & 1 WDTs
+    mww 0x6001f064 0x50D83AA1
+    mww 0x6001F048 0
+    mww 0x60020064 0x50D83AA1
+    mww 0x60020048 0
+    # RTC WDT
+    mww 0x600080a8 0x50D83AA1
+    mww 0x60008090 0
+    # SWD
+    mww 0x600080b0 0x8F1D312A
+    mww 0x600080ac 0x84B00000
+}
+
+# This is almost identical with the esp32c2_soc_reset.
+# Will be refactored with the other common settings.
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL
+
+    # This procedure does "digital system reset", i.e. resets
+    # all the peripherals except for the RTC block.
+    # It is called from reset-assert-post target event callback,
+    # after assert_reset procedure was called.
+    # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
+    # temporarily take it out of reset. Save the dmcontrol state before
+    # doing so.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000001
+    # Trigger the reset
+    mww 0x60008000 0x9c00a000
+    # Workaround for stuck in cpu start during calibration.
+    # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
+    mww 0x6001F068 0
+    # Wait for the reset to happen
+    sleep 10
+    poll
+    # Disable the watchdogs again
+    riscv_wdt_disable
+
+    # Here debugger reads allresumeack and allhalted bits as set (0x330a2)
+    # We will clean allhalted state by resuming the core.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x40000001
+
+    # Put the hart back into reset state. Note that we need to keep haltreq set.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000003
+}
+
+proc riscv_memprot_is_enabled { } {
+    # IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+    if { [get_mmr_bit 0x600C10A8 0] != 0 } {
+        return 1
+    }
+    # DRAM0 PMS lock, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+    if { [get_mmr_bit 0x600C10C0 0] != 0 } {
+        return 1
+    }
+    return 0
+}
+
+create_esp_target $_ESP_ARCH
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32c6.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32c6.cfg
new file mode 100644
index 0000000..e1ef10a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32c6.cfg
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x0000dc25
+set _ESP_ARCH					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x600B0844
+
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
+    # Halt event can occur during config phase (before "init" is done).
+    # Ignore it since mww commands don't work at that time.
+    if { [string compare [command mode] config] == 0 } {
+        return
+    }
+
+    # Timer Group 0 & 1 WDTs
+    mww 0x60008064 0x50D83AA1
+    mww 0x60008048 0
+    mww 0x60009064 0x50D83AA1
+    mww 0x60009048 0
+    # LP_WDT_RTC
+    mww 0x600b1c18 0x50D83AA1
+    mww 0x600B1C00 0
+    # LP_WDT_SWD
+    mww 0x600b1c20 0x50D83AA1
+    mww 0x600b1c1c 0x40000000
+}
+
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0
+
+    riscv dmi_write $_RISCV_DMCONTROL 		0x80000001
+    riscv dmi_write $_RISCV_SB_CS 			0x48000
+    riscv dmi_write $_RISCV_SB_ADDR0 		0x600b1034
+    riscv dmi_write $_RISCV_SB_DATA0		0x80000000
+    # clear dmactive to clear sbbusy otherwise debug module gets stuck
+    riscv dmi_write $_RISCV_DMCONTROL 		0
+
+    riscv dmi_write $_RISCV_SB_CS 			0x48000
+    riscv dmi_write $_RISCV_SB_ADDR0 		0x600b1038
+    riscv dmi_write $_RISCV_SB_DATA0 		0x10000000
+
+    # clear dmactive to clear sbbusy otherwise debug module gets stuck
+    riscv dmi_write $_RISCV_DMCONTROL 		0
+    riscv dmi_write $_RISCV_DMCONTROL 		0x40000001
+    # Here debugger reads dmstatus as 0xc03a2
+
+    # Wait for the reset to happen
+    sleep 10
+    poll
+    # Here debugger reads dmstatus as 0x3a2
+
+    # Disable the watchdogs again
+    riscv_wdt_disable
+
+    # Here debugger reads anyhalted and allhalted bits as set (0x3a2)
+    # We will clean allhalted state by resuming the core.
+    riscv dmi_write $_RISCV_DMCONTROL 		0x40000001
+
+    # Put the hart back into reset state. Note that we need to keep haltreq set.
+    riscv dmi_write $_RISCV_DMCONTROL 		0x80000003
+}
+
+proc riscv_memprot_is_enabled { } {
+	global _RISCV_ABS_CMD _RISCV_ABS_DATA0
+
+	# If IRAM/DRAM split is enabled TOR address match mode is used.
+    # If IRAM/DRAM split is disabled NAPOT mode is used.
+	# In order to determine if the IRAM/DRAM regions are protected against RWX/RW,
+	# it is necessary to first read the mode and then apply the appropriate method for checking.
+	# We can understand the mode reading pmp5cfg in pmpcfg1 register.
+	# If it is none we know that pmp6cfg and pmp7cfg is in TOR mode.
+
+	# Read pmpcfg1 and extract into 8-bit variables.
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203a1
+	set pmpcfg1 [riscv dmi_read $_RISCV_ABS_DATA0]
+
+	set pmp5cfg [expr {($pmpcfg1 >> (8 * 1)) & 0xFF}]
+	set pmp6cfg [expr {($pmpcfg1 >> (8 * 2)) & 0xFF}]
+	set pmp7cfg [expr {($pmpcfg1 >> (8 * 3)) & 0xFF}]
+
+	set IRAM_LOW 	0x40800000
+	set IRAM_HIGH 	0x40880000
+	set DRAM_LOW 	0x40800000
+	set DRAM_HIGH 	0x40880000
+	set PMP_RWX     0x07
+	set PMP_RW     	0x03
+	set PMP_A		[expr {($pmp5cfg >> 3) & 0x03}]
+
+	if {$PMP_A == 0} {
+		# TOR mode used to protect valid address space.
+
+		# Read PMPADDR 5-7
+		riscv dmi_write $_RISCV_ABS_CMD 0x2203b5
+		set pmpaddr5 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+		riscv dmi_write $_RISCV_ABS_CMD 0x2203b6
+		set pmpaddr6 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+		riscv dmi_write $_RISCV_ABS_CMD 0x2203b7
+		set pmpaddr7 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+
+		# The lock bit remains unset during the execution of the 2nd stage bootloader.
+		# Thus we do not perform a lock bit check for IRAM and DRAM regions.
+
+		# Check OpenOCD can write and execute from IRAM.
+		if {$pmpaddr5 >= $IRAM_LOW && $pmpaddr6 <= $IRAM_HIGH} {
+			if {($pmp5cfg & $PMP_RWX) != 0 || ($pmp6cfg & $PMP_RWX) != $PMP_RWX} {
+				return 1
+			}
+		}
+
+		# Check OpenOCD can read/write  entire DRAM region.
+		if {$pmpaddr7 >= $DRAM_LOW && $pmpaddr7 <= $DRAM_HIGH} {
+			if {($pmp7cfg & $PMP_RW) != $PMP_RW} {
+				return 1
+			}
+		}
+	} elseif {$PMP_A == 3} {
+		# NAPOT mode used to protect valid address space.
+
+		# Read PMPADDR 5
+		riscv dmi_write $_RISCV_ABS_CMD 0x2203b5
+		set pmpaddr5 [expr {[riscv dmi_read $_RISCV_ABS_DATA0]}]
+
+		# Expected value written to the pmpaddr5
+		set pmpaddr_napot [expr {($IRAM_LOW | (($IRAM_HIGH - $IRAM_LOW - 1) >> 1)) >> 2}]
+		if {($pmpaddr_napot != $pmpaddr5) ||  ($pmp5cfg & $PMP_RWX) != $PMP_RWX} {
+			return 1
+		}
+	}
+
+	return 0
+}
+
+create_esp_target $_ESP_ARCH
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32h2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32h2.cfg
new file mode 100644
index 0000000..45f598f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32h2.cfg
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x00010c25
+set _ESP_ARCH					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x600B0844
+
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
+    # Halt event can occur during config phase (before "init" is done).
+    # Ignore it since mww commands don't work at that time.
+    if { [string compare [command mode] config] == 0 } {
+        return
+    }
+
+    # Timer Group 0 & 1 WDTs
+    mww 0x60009064 0x50D83AA1
+    mww 0x60009048 0
+    mww 0x6000A064 0x50D83AA1
+    mww 0x6000A048 0
+    # WDT_RTC
+    #mww 0x600b1c18 0x50D83AA1
+    #mww 0x600B1C00 0
+    # WDT_SWD
+    #mww 0x600b1c20 0x8F1D312A
+    #mww 0x600b1c1c 0x84B00000
+}
+
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0
+
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000001
+    riscv dmi_write $_RISCV_SB_CS 		0x48000
+    riscv dmi_write $_RISCV_SB_ADDR0 	0x600b1034
+    riscv dmi_write $_RISCV_SB_DATA0 	0x80000000
+    # clear dmactive to clear sbbusy otherwise debug module gets stuck
+    riscv dmi_write $_RISCV_DMCONTROL 	0
+
+    riscv dmi_write $_RISCV_SB_CS 		0x48000
+    riscv dmi_write $_RISCV_SB_ADDR0 	0x600b1038
+    riscv dmi_write $_RISCV_SB_DATA0 	0x10000000
+
+    # clear dmactive to clear sbbusy otherwise debug module gets stuck
+    riscv dmi_write $_RISCV_DMCONTROL 	0
+    riscv dmi_write $_RISCV_DMCONTROL 	0x40000001
+    # Here debugger reads dmstatus as 0xc03a2
+
+    # Wait for the reset to happen
+    sleep 10
+    poll
+    # Here debugger reads dmstatus as 0x3a2
+
+    # Disable the watchdogs again
+    riscv_wdt_disable
+
+    # Here debugger reads anyhalted and allhalted bits as set (0x3a2)
+    # We will clean allhalted state by resuming the core.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x40000001
+
+    # Put the hart back into reset state. Note that we need to keep haltreq set.
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000003
+}
+
+proc riscv_memprot_is_enabled { } {
+	global _RISCV_ABS_CMD _RISCV_ABS_DATA0
+	# If IRAM/DRAM split is enabled, PMPADDR 5-6 will cover valid IRAM region and PMPADDR 7 will cover valid DRAM region
+	# Only TOR mode is used for IRAM and DRAM protections.
+
+	# Read pmpcfg1 and extract into 8-bit variables.
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203a1
+	set pmpcfg1 [riscv dmi_read $_RISCV_ABS_DATA0]
+
+	set pmp5cfg [expr {($pmpcfg1 >> (8 * 1)) & 0xFF}]
+	set pmp6cfg [expr {($pmpcfg1 >> (8 * 2)) & 0xFF}]
+	set pmp7cfg [expr {($pmpcfg1 >> (8 * 3)) & 0xFF}]
+
+	# Read PMPADDR 5-7
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b5
+	set pmpaddr5 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b6
+	set pmpaddr6 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b7
+	set pmpaddr7 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+
+	set IRAM_LOW 	0x40800000
+	set IRAM_HIGH 	0x40850000
+	set DRAM_LOW 	0x40800000
+	set DRAM_HIGH 	0x40850000
+
+	set PMP_RWX     0x07
+	set PMP_RW     	0x03
+
+	# The lock bit remains unset during the execution of the 2nd stage bootloader.
+	# Thus, we do not perform a lock bit check for IRAM and DRAM regions.
+
+	# Check OpenOCD can write and execute from IRAM.
+	if {$pmpaddr5 >= $IRAM_LOW && $pmpaddr6 <= $IRAM_HIGH} {
+		if {($pmp5cfg & $PMP_RWX) != 0 || ($pmp6cfg & $PMP_RWX) != $PMP_RWX} {
+			return 1
+		}
+	}
+
+	# Check OpenOCD can read/write  entire DRAM region.
+	# If IRAM/DRAM split is disabled, pmpaddr7 will be zero, checking only IRAM region is enough.
+	if {$pmpaddr7 != 0 && $pmpaddr7 >= $DRAM_LOW && $pmpaddr7 <= $DRAM_HIGH} {
+		if {($pmp7cfg & $PMP_RW) != $PMP_RW} {
+			return 1
+		}
+	}
+
+	return 0
+}
+
+create_esp_target $_ESP_ARCH
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32s2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32s2.cfg
new file mode 100644
index 0000000..4c1362a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32s2.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"esp32s2"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH					"xtensa"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG  	0x3f41A004
+
+proc esp32s2_memprot_is_enabled { } {
+	# IRAM0, DPORT_PMS_PRO_IRAM0_0_REG
+	if { [get_mmr_bit 0x3f4c1010 0] != 0 } {
+		return 1
+	}
+	# DRAM0, DPORT_PMS_PRO_DRAM0_0_REG
+	if { [get_mmr_bit 0x3f4c1028 0] != 0 } {
+		return 1
+	}
+	# PERI1, DPORT_PMS_PRO_DPORT_0_REG
+	if { [get_mmr_bit 0x3f4c103c 0] != 0 } {
+		return 1
+	}
+	# PERI2, DPORT_PMS_PRO_AHB_0_REG
+	if { [get_mmr_bit 0x3f4c105c 0] != 0 } {
+		return 1
+	}
+	return 0
+}
+
+proc esp32s2_soc_reset { } {
+	soft_reset_halt
+}
+
+create_esp_target $_ESP_ARCH
+
+source [find target/xtensa-core-esp32s2.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32s3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32s3.cfg
new file mode 100644
index 0000000..12c166c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp32s3.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"esp32s3"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH 					"xtensa"
+set _ONLYCPU					3
+set _ESP_SMP_TARGET				1
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60007044
+
+if { [info exists ESP32_S3_ONLYCPU] } {
+	set _ONLYCPU $ESP32_S3_ONLYCPU
+}
+
+proc esp32s3_memprot_is_enabled { } {
+	# SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C10C0 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C1124 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C11D0 0] != 0 } {
+		return 1
+	}
+	# IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C10D8 0] != 0 } {
+		return 1
+	}
+	# DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C10FC 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C10E4 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C10F0 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C1104 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C1114 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C119C 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C1248 0] != 0 } {
+		return 1
+	}
+	return 0
+}
+
+proc esp32s3_soc_reset { } {
+	soft_reset_halt
+}
+
+create_esp_target $_ESP_ARCH
+
+source [find target/xtensa-core-esp32s3.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp_common.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp_common.cfg
new file mode 100644
index 0000000..5ea9bc8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/esp_common.cfg
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+source [find bitsbytes.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+# Riscv Debug Module Registers which are used around esp configuration files.
+set _RISCV_ABS_DATA0	0x04
+set _RISCV_DMCONTROL	0x10
+set _RISCV_ABS_CMD		0x17
+set _RISCV_SB_CS		0x38
+set _RISCV_SB_ADDR0		0x39
+set _RISCV_SB_DATA0		0x3C
+
+# Common ESP chips definitions
+
+# Espressif supports only NuttX in the upstream.
+# FreeRTOS support is not upstreamed yet.
+set _RTOS "hwthread"
+if { [info exists ESP_RTOS] } {
+	set _RTOS "$ESP_RTOS"
+}
+
+# by default current dir (when OOCD has been started)
+set _SEMIHOST_BASEDIR "."
+if { [info exists ESP_SEMIHOST_BASEDIR] } {
+	set _SEMIHOST_BASEDIR $ESP_SEMIHOST_BASEDIR
+}
+
+proc set_esp_common_variables { } {
+	global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET
+	global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1
+	global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED
+
+	# For now we support dual core at most.
+	if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} {
+		set _TARGETNAME_0 				$_CHIPNAME
+		set _CPUNAME_0					cpu
+		set _TAPNAME_0 					$_CHIPNAME.$_CPUNAME_0
+	} else {
+		set _CPUNAME_0 					cpu0
+		set _CPUNAME_1 					cpu1
+		set _TARGETNAME_0 				$_CHIPNAME.$_CPUNAME_0
+		set _TARGETNAME_1 				$_CHIPNAME.$_CPUNAME_1
+		set _TAPNAME_0 					$_TARGETNAME_0
+		set _TAPNAME_1 					$_TARGETNAME_1
+	}
+
+	set _ESP_WDT_DISABLE 			"${_CHIPNAME}_wdt_disable"
+	set _ESP_SOC_RESET 				"${_CHIPNAME}_soc_reset"
+	set _ESP_MEMPROT_IS_ENABLED 	"${_CHIPNAME}_memprot_is_enabled"
+}
+
+proc create_esp_jtag { } {
+	global _CHIPNAME _CPUNAME_0 _CPUNAME_1 _CPUTAPID _ONLYCPU
+	jtag newtap $_CHIPNAME $_CPUNAME_0 -irlen 5 -expected-id $_CPUTAPID
+	if { $_ONLYCPU != 1 } {
+		jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -expected-id $_CPUTAPID
+	} elseif [info exists _CPUNAME_1] {
+		jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -disable -expected-id $_CPUTAPID
+	}
+}
+
+proc create_openocd_targets  { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU
+
+	target create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS
+	if { $_ONLYCPU != 1 } {
+		target create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS
+		target smp $_TARGETNAME_0 $_TARGETNAME_1
+	}
+}
+
+proc create_esp_target { ARCH } {
+	set_esp_common_variables
+	create_esp_jtag
+	create_openocd_targets
+	configure_openocd_events $ARCH
+
+	if { $ARCH == "xtensa"} {
+		configure_esp_xtensa_default_settings
+	} else {
+		configure_esp_riscv_default_settings
+	}
+}
+
+#################### Set event handlers and default settings  ####################
+
+proc configure_event_examine_end { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
+
+	$_TARGETNAME_0 configure -event examine-end {
+		# Need to enable to set 'semihosting_basedir'
+		arm semihosting enable
+		arm semihosting_resexit enable
+		if { [info exists _SEMIHOST_BASEDIR] } {
+			if { $_SEMIHOST_BASEDIR != "" } {
+				arm semihosting_basedir $_SEMIHOST_BASEDIR
+			}
+		}
+	}
+
+	if { $_ONLYCPU != 1 } {
+		$_TARGETNAME_1 configure -event examine-end {
+			# Need to enable to set 'semihosting_basedir'
+			arm semihosting enable
+			arm semihosting_resexit enable
+			if { [info exists _SEMIHOST_BASEDIR] } {
+				if { $_SEMIHOST_BASEDIR != "" } {
+					arm semihosting_basedir $_SEMIHOST_BASEDIR
+				}
+			}
+		}
+	}
+}
+
+proc configure_event_reset_assert_post { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
+
+	$_TARGETNAME_0 configure -event reset-assert-post {
+		global _ESP_SOC_RESET
+		$_ESP_SOC_RESET
+	}
+
+	if { $_ONLYCPU != 1 } {
+		$_TARGETNAME_1 configure -event reset-assert-post {
+			global _ESP_SOC_RESET
+			$_ESP_SOC_RESET
+		}
+	}
+}
+
+proc configure_event_halted { } {
+	global _TARGETNAME_0
+
+	$_TARGETNAME_0 configure -event halted {
+		global _ESP_WDT_DISABLE
+	    $_ESP_WDT_DISABLE
+	}
+}
+
+proc configure_event_gdb_attach { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
+
+	$_TARGETNAME_0 configure -event gdb-attach {
+		if { $_ESP_SMP_BREAK != 0 } {
+			$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+		}
+		# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
+		halt 1000
+		if { [$_ESP_MEMPROT_IS_ENABLED] } {
+			# 'reset halt' to disable memory protection and allow flasher to work correctly
+			echo "Memory protection is enabled. Reset target to disable it..."
+			reset halt
+		}
+	}
+
+	if { $_ONLYCPU != 1 } {
+		$_TARGETNAME_1 configure -event gdb-attach {
+			if { $_ESP_SMP_BREAK != 0 } {
+				$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
+			}
+			# necessary to auto-probe flash bank when GDB is connected
+			halt 1000
+			if { [$_ESP_MEMPROT_IS_ENABLED] } {
+				# 'reset halt' to disable memory protection and allow flasher to work correctly
+				echo "Memory protection is enabled. Reset target to disable it..."
+				reset halt
+			}
+		}
+	}
+}
+
+proc configure_openocd_events { ARCH } {
+	if { $ARCH == "riscv" } {
+		configure_event_halted
+	}
+	configure_event_examine_end
+	configure_event_reset_assert_post
+	configure_event_gdb_attach
+}
+
+proc configure_esp_riscv_default_settings { } {
+	gdb_breakpoint_override hard
+	riscv set_reset_timeout_sec 2
+	riscv set_command_timeout_sec 5
+	riscv set_mem_access sysbus progbuf abstract
+	riscv set_ebreakm on
+	riscv set_ebreaks on
+	riscv set_ebreaku on
+}
+
+proc configure_esp_xtensa_default_settings { } {
+	global _TARGETNAME_0 _ESP_SMP_BREAK _FLASH_VOLTAGE _CHIPNAME
+
+	$_TARGETNAME_0 xtensa maskisr on
+	if { $_ESP_SMP_BREAK != 0 } {
+		$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+	}
+
+	gdb breakpoint_override hard
+
+	if { [info exists _FLASH_VOLTAGE] } {
+		$_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/exynos5250.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/exynos5250.cfg
new file mode 100644
index 0000000..a565022
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/exynos5250.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Samsung Exynos 5250 - dual-core ARM Cortex-A15
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME exynos5250
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap
+target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap
+
+target smp ${_TARGETNAME}0 ${_TARGETNAME}1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/faux.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/faux.cfg
new file mode 100644
index 0000000..71cb8b7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/faux.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#Script for faux target - used for testing
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91eb40a
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x00000000
+}
+
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#dummy flash driver
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/feroceon.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/feroceon.cfg
new file mode 100644
index 0000000..593569d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/feroceon.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Marvell Feroceon CPU core
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME feroceon
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x20a023d3
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
+
+reset_config trst_and_srst
+adapter srst delay 200
+jtag_ntrst_delay 200
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm3.cfg
new file mode 100644
index 0000000..0caf629
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm3.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MB9BF506
+# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME mb9bfxx6
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+# delays on reset lines
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+# Fujitsu Cortex-M3 reset configuration
+reset_config trst_only
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# MB9BF506 has 64kB of SRAM on its main system bus
+$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
+
+# MB9BF506 has 512kB internal FLASH
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
+
+# 4MHz / 6 = 666kHz, so use 500
+adapter speed 500
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm4.cfg
new file mode 100644
index 0000000..4318f2e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm4.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion FM4 (ARM Cortex-M4)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME fm4
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CPUTAPID] } {
+	set _CPU_TAPID $CPUTAPID
+} elseif { [using_jtag] } {
+	set _CPU_TAPID 0x4ba00477
+} else {
+	set _CPU_TAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+adapter speed 500
+
+if {![using_hla]} {
+	cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm4_mb9bf.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm4_mb9bf.cfg
new file mode 100644
index 0000000..4bc579c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm4_mb9bf.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion FM4 MB9BFxxx (ARM Cortex-M4)
+#
+
+source [find target/fm4.cfg]
+
+# MB9BF566 M/N/R have 32 KB SRAM0
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x8000
+}
+
+$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm4_s6e2cc.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm4_s6e2cc.cfg
new file mode 100644
index 0000000..7417d38
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/fm4_s6e2cc.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Spansion FM4 S6E2CC (ARM Cortex-M4)
+#
+
+source [find target/fm4.cfg]
+
+# S6E2CC8 H/J/L have 96 KB SRAM0
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x18000
+}
+
+$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank ${_FLASHNAME}0 fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES
+flash bank ${_FLASHNAME}1 fm4 0x00100000 0 0 0 $_TARGETNAME $CHIPSERIES
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gd32e23x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gd32e23x.cfg
new file mode 100644
index 0000000..2504274
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gd32e23x.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for GigaDevice gd32e23x Cortex-M23 Series
+
+# https://www.gigadevice.com/microcontroller/gd32e230c8t6/
+
+#
+# gd32e23x devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME gd32e23x
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB (as found on some GD32E230s)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # this is the SW-DP tap id not the jtag tap id
+   set _CPUTAPID 0x0bf11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# SWD speed (may be updated to higher value in board config file)
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Debug clock enable
+	# RCU_APB2EN |= DBGMCUEN
+	mmw 0x40021018 0x00400000 0
+
+	# Stop watchdog counters during halt
+	# DBG_CTL0 |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD
+	mmw 0x40015804 0x00000307 0
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gd32vf103.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gd32vf103.cfg
new file mode 100644
index 0000000..77fdff7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gd32vf103.cfg
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# GigaDevice GD32VF103 target
+#
+# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
+#
+
+adapter speed 1000
+source [find mem_helper.tcl]
+
+transport select jtag
+
+reset_config srst_nogate
+
+# The smallest RAM size 6kB (GD32VF103C4/T4/R4)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1800
+}
+
+set _CHIPNAME gd32vf103
+# The vendor's configuration expects an ID of 0x1e200a6d, but this one is what
+# I have on my board (Sipeed Longan Nano, GD32VF103CBT6).
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME riscv set_enable_virt2phys off
+
+proc default_mem_access {} {
+	riscv set_mem_access progbuf
+}
+
+default_mem_access
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+# Address 0 is only aliased to main flash when the chip is not running its
+# built-in bootloader. When it is, it's instead aliased to a read only section
+# of flash at 0x1fffb000. However, we can't detect or dynamically switch this,
+# so just pretend it's always aliased to main flash. We need to tell OpenOCD
+# about this alias because otherwise we'll try to use software breakpoints on
+# code in flash, which don't work because flash mappings are read-only.
+flash bank $_CHIPNAME.flashalias virtual 0x0 0 0 0 $_TARGETNAME $_FLASHNAME
+
+# On this chip, ndmreset (the debug module bit that triggers a software reset)
+# doesn't work. So for JTAG connections without an SRST, we need to trigger a
+# reset manually. This is an undocumented reset sequence that's used by the
+# JTAG flashing script in the vendor-supplied GD32VF103 PlatformIO plugin:
+#
+#   https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2
+#
+$_TARGETNAME configure -event reset-assert {
+	set dmcontrol 		0x10
+	set dmcontrol_dmactive	[expr 1 << 0]
+	set dmcontrol_haltreq	[expr 1 << 31]
+
+	global _RESETMODE
+	global _TARGETNAME
+
+	# Halt the core so that we can write to memory. We do this first so
+	# that it doesn't clobber our dmcontrol configuration.
+	halt
+
+	# Set haltreq appropriately for the type of reset we're doing. This
+	# replicates what the generic RISC-V reset_assert() function would
+	# do if we weren't overriding it. The $_RESETMODE hack sucks, but
+	# it's the least invasive way to determine whether we need to halt,
+	# and psoc6.cfg already uses the same trick. (reset_deassert(), which
+	# does run, also does this, but at that point it may be too late: the
+	# reset has already been triggered, so there's a race between it and
+	# the haltreq write.)
+	#
+	# If we didn't override the generic handler, we'd actually still have
+	# to do this: the default handler sets ndmreset, which prevents memory
+	# access even though it doesn't actually trigger a reset on this chip.
+	# So we'd need to unset it here, which involves a write to dmcontrol,
+	# Since haltreq is write-only and there's no way to leave it unchanged,
+	# we'd have to figure out its proper value anyway.
+	set val $dmcontrol_dmactive
+	if {$_RESETMODE ne "run"} {
+		set val [expr $val | $dmcontrol_haltreq]
+	}
+	$_TARGETNAME riscv dmi_write $dmcontrol $val
+
+	# Unlock 0xe0042008 so that the next write triggers a reset
+	$_TARGETNAME mww 0xe004200c 0x4b5a6978
+
+	# We need to trigger the reset using abstract memory access, since
+	# progbuf access tries to read a status code out of a core register
+	# after the write happens, which fails when the core is in reset.
+	riscv set_mem_access abstract
+
+	# Go!
+	$_TARGETNAME mww 0xe0042008 0x1
+
+	# Put the memory access mode back to what it was.
+	default_mem_access
+}
+
+# Capture the mode of a given reset so that we can use it later in the
+# reset-assert handler.
+proc init_reset { mode } {
+	global _RESETMODE
+	set _RESETMODE $mode
+
+	if {[using_jtag]} {
+		jtag arp_init-reset
+	}
+}
+
+# On this chip, ndmreset (the debug module bit that triggers a software reset)
+# doesn't work. So for JTAG connections without an SRST, we need to trigger a
+# reset manually. This is an undocumented reset sequence that's used by the
+# JTAG flashing script in the vendor-supplied GD32VF103 PlatformIO plugin:
+#
+#   https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2
+#
+$_TARGETNAME configure -event reset-assert {
+	set dmcontrol 		0x10
+	set dmcontrol_dmactive	[expr {1 << 0}]
+	set dmcontrol_ackhavereset [expr {1 << 28}]
+	set dmcontrol_haltreq	[expr {1 << 31}]
+
+	global _RESETMODE
+
+	# If hardware NRST signal is connected and configured (reset_config srst_only)
+	# the device has been recently reset in 'jtag arp_init-reset', therefore
+	# DM_DMSTATUS_ANYHAVERESET reads 1.
+	# The following 'halt' command checks this status bit
+	# and shows 'Hart 0 unexpectedly reset!' if set.
+	# Prevent this message by sending an acknowledge first.
+	set val [expr {$dmcontrol_dmactive | $dmcontrol_ackhavereset}]
+	riscv dmi_write $dmcontrol $val
+
+	# Halt the core so that we can write to memory. We do this first so
+	# that it doesn't clobber our dmcontrol configuration.
+	halt
+
+	# Set haltreq appropriately for the type of reset we're doing. This
+	# replicates what the generic RISC-V reset_assert() function would
+	# do if we weren't overriding it. The $_RESETMODE hack sucks, but
+	# it's the least invasive way to determine whether we need to halt.
+	#
+	# If we didn't override the generic handler, we'd actually still have
+	# to do this: the default handler sets ndmreset, which prevents memory
+	# access even though it doesn't actually trigger a reset on this chip.
+	# So we'd need to unset it here, which involves a write to dmcontrol,
+	# Since haltreq is write-only and there's no way to leave it unchanged,
+	# we'd have to figure out its proper value anyway.
+	set val $dmcontrol_dmactive
+	if {$_RESETMODE ne "run"} {
+		set val [expr {$val | $dmcontrol_haltreq}]
+	}
+	riscv dmi_write $dmcontrol $val
+
+	# Unlock 0xe0042008 so that the next write triggers a reset
+	mww 0xe004200c 0x4b5a6978
+
+	# We need to trigger the reset using abstract memory access, since
+	# progbuf access tries to read a status code out of a core register
+	# after the write happens, which fails when the core is in reset.
+	riscv set_mem_access abstract
+
+	# Go!
+	mww 0xe0042008 0x1
+
+	# Put the memory access mode back to what it was.
+	default_mem_access
+}
+
+# Capture the mode of a given reset so that we can use it later in the
+# reset-assert handler.
+proc init_reset { mode } {
+	global _RESETMODE
+	set _RESETMODE $mode
+
+	if {[using_jtag]} {
+		jtag arp_init-reset
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gd32vw55x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gd32vw55x.cfg
new file mode 100644
index 0000000..b44aab9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gd32vw55x.cfg
@@ -0,0 +1,35 @@
+#
+# GigaDevice GD32VW55x target
+#
+#
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10307a6d
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 20480 -work-area-backup 0
+
+
+# Work-area is a space in RAM used for flash programming
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x5000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME gd32vw55x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+riscv set_reset_timeout_sec 1
+init
+
+halt
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/geehy/apm32f0x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/geehy/apm32f0x.cfg
new file mode 100644
index 0000000..502c092
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/geehy/apm32f0x.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F0x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F0x devices support SWD transport only.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f0x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 1 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/geehy/apm32f1x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/geehy/apm32f1x.cfg
new file mode 100644
index 0000000..dc42e06
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/geehy/apm32f1x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F1x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F1x devices support JTAG and SWD transport.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f1x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/geehy/apm32f4x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/geehy/apm32f4x.cfg
new file mode 100644
index 0000000..3ed58d1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/geehy/apm32f4x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F4x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F4x devices support JTAG and SWD transport.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f4x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+     set _CPUTAPID 0x4ba00477
+   } else {
+     set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if { [using_jtag] } {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gp326xxxa.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gp326xxxa.cfg
new file mode 100644
index 0000000..447460b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/gp326xxxa.cfg
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Support for General Plus GP326XXXA chips
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME gp326xxxa
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4f1f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Use internal SRAM as a work area
+$_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0
+
+# The chip has both lines connected together
+reset_config trst_and_srst srst_pulls_trst
+# This delay is needed otherwise communication with the target would
+# be unreliable
+adapter srst delay 100
+
+# Set the adapter speed ridiculously low just in case we are
+# running off of a 32kHz clock
+adapter speed 2
+
+proc gp32xxxa_halt_and_reset_control_registers {} {
+	# System control registers
+	set P_SYSTEM_CTRL_NEW       0xD0000008
+	set P_SYSTEM_CTRL           0xD000000C
+	set P_SYSTEM_CLK_EN0        0xD0000010
+	set P_SYSTEM_CLK_EN1        0xD0000014
+	set P_SYSTEM_RESET_FLAG     0xD0000018
+	set P_SYSTEM_CLK_CTRL       0xD000001C
+	set P_SYSTEM_LVR_CTRL       0xD0000020
+	set P_SYSTEM_WATCHDOG_CTRL  0xD0000024
+	set P_SYSTEM_PLLEN          0xD000005C
+
+	# Since we can't use SRST without pulling TRST
+	# we can't assume the state of the clock configuration
+	# or watchdog settings. So reset them before porceeding
+
+	# Set the adapter speed ridiculously low just in case we are
+	# running off of a 32kHz clock
+	adapter speed 2
+
+	# Disable any advanced features at this stage
+	arm7_9 dcc_downloads disable
+	arm7_9 fast_memory_access disable
+
+	# Do a "soft reset"
+	soft_reset_halt
+	# Reset all system control registers to their default "after-reset" values
+	mwh $P_SYSTEM_WATCHDOG_CTRL  0x0000
+	mwh $P_SYSTEM_LVR_CTRL       0x0000
+
+	mwh $P_SYSTEM_CTRL_NEW       0x0001
+	mwh $P_SYSTEM_CTRL           0x0001
+	# Clear all reset flags by writing 1's
+	mwh $P_SYSTEM_RESET_FLAG     0x001C
+
+	mwh $P_SYSTEM_CLK_CTRL       0x8000
+	mwh $P_SYSTEM_CLK_EN0        0xFFFF
+	mwh $P_SYSTEM_CLK_EN1        0xFFFF
+	mwh $P_SYSTEM_PLLEN          0x0010
+
+	# Unfortunately there's no register that would allow us to
+	# know if PLL is locked. So just wait for 100ms in hopes that
+	# it would be enough.
+	sleep 100
+
+	# Now that we know that we are running at 48Mhz
+	# Increase JTAG speed and enable speed optimization features
+	adapter speed 5000
+	arm7_9 dcc_downloads enable
+	arm7_9 fast_memory_access enable
+}
+
+$_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers }
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hi3798.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hi3798.cfg
new file mode 100644
index 0000000..722305d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hi3798.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hisilicon Hi3798 Target
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME hi3798
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x5ba00477
+}
+
+# declare the one JTAG tap to access the DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+# declare the 4 main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+set $_TARGETNAME.cti(0) 0x80020000
+set $_TARGETNAME.cti(1) 0x80120000
+set $_TARGETNAME.cti(2) 0x80220000
+set $_TARGETNAME.cti(3) 0x80320000
+
+set _cores 4
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        #set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hi6220.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hi6220.cfg
new file mode 100644
index 0000000..5b03899
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hi6220.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hisilicon Hi6220 Target
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME hi6220
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4ba00477
+}
+
+# declare the one JTAG tap to access the DAP
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# declare the 8 main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+set $_TARGETNAME.cti(0) 0x80198000
+set $_TARGETNAME.cti(1) 0x80199000
+set $_TARGETNAME.cti(2) 0x8019A000
+set $_TARGETNAME.cti(3) 0x8019B000
+set $_TARGETNAME.cti(4) 0x801D8000
+set $_TARGETNAME.cti(5) 0x801D9000
+set $_TARGETNAME.cti(6) 0x801DA000
+set $_TARGETNAME.cti(7) 0x801DB000
+
+set _cores 8
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+cti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80003000
+
+# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin)
+target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+
+# declare the auxiliary Cortex-A7 core
+target create ${_TARGETNAME}.a7 cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hilscher_netx10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hilscher_netx10.cfg
new file mode 100644
index 0000000..054cac8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hilscher_netx10.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+#Hilscher netX 10 CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME netx10
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966021
+}
+
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# that TAP is associated with a target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hilscher_netx50.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hilscher_netx50.cfg
new file mode 100644
index 0000000..e8ba015
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hilscher_netx50.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+#Hilscher netX 50 CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME netx50
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966021
+}
+
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# that TAP is associated with a target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# On netX50 SDRAM is not accessible at offset 0xDEAD0-0xDEADF as it is busy from
+# DMA controller at init. This function will setup a dummy DMA to free this ares
+# and must be called before using SDRAM
+proc sdram_fix { } {
+
+  mww 0x1c005830 0x00000001
+
+  mww 0x1c005104 0xBFFFFFFC
+  mww 0x1c00510c 0x00480001
+  mww 0x1c005110 0x00000001
+
+  sleep 100
+
+  mww 0x1c00510c 0
+  mww 0x1c005110 0
+  mww 0x1c005830 0x00000000
+
+	puts "SDRAM Fix executed!"
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hilscher_netx500.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hilscher_netx500.cfg
new file mode 100644
index 0000000..d838a6b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/hilscher_netx500.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#Hilscher netX 500 CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME netx500
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926021
+}
+
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# that TAP is associated with a target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+proc mread32 {addr} {
+  return [read_memory $addr 32 1]
+}
+
+# This function must be called on netX100/500 right after halt
+# If it is called later the needed register cannot be written anymore
+proc sdram_fix { } {
+
+  set accesskey [mread32 0x00100070]
+  mww 0x00100070 $accesskey
+  mww 0x0010002c 0x00000001
+
+  if {[expr {[mread32 0x0010002c] & 0x07}] == 0x07} {
+	 puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!"
+  } else {
+	 puts "SDRAM Fix succeeded!"
+  }
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/icepick.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/icepick.cfg
new file mode 100644
index 0000000..e5d5706
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/icepick.cfg
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Copyright (C)   2011        by Karl Kurbjun
+# Copyright (C)   2009        by David Brownell
+#
+
+# Utilities for TI ICEpick-C/D used in most TI SoCs
+# Details about the ICEPick are available in the TRM for each SoC
+# and http://processors.wiki.ti.com/index.php/ICEPICK
+
+# create "constants"
+proc CONST { key } {
+
+	array set constant {
+		# define ICEPick instructions
+		IR_BYPASS   0x00
+		IR_ROUTER   0x02
+		IR_CONNECT  0x07
+		IF_BYPASS   0x3F
+	}
+	return $constant($key)
+}
+
+# Instruction to connect to the icepick module
+proc icepick_c_connect {jrc} {
+
+	# Send CONNECT instruction in IR state
+	irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
+
+	# Send write and connect key
+	drscan $jrc 8 0x89 -endstate DRPAUSE
+}
+
+# Instruction to disconnect to the icepick module
+proc icepick_c_disconnect {jrc} {
+
+	# Send CONNECT instruction in IR state
+	irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
+
+	# Send write and connect key
+	drscan $jrc 8 0x86 -endstate DRPAUSE
+}
+
+#
+# icepick_c_router:
+#  this function is for sending router commands
+# arguments are:
+#  jrc:        TAP name for the ICEpick
+#  rw:         read/write (0 for read, 1 for write)
+#  block:      icepick or DAP
+#  register:   which register to read/write
+#  payload:    value to read/write
+# this function is for sending router commands
+#
+proc icepick_c_router {jrc rw block register payload} {
+
+	set new_dr_value \
+		[expr { ( ($rw & 0x1) << 31)        | ( ($block & 0x7) << 28) | \
+				( ($register & 0xF) << 24)  | ( $payload & 0xFFFFFF ) } ]
+
+#	echo "\tNew router value:\t0x[format %x $new_dr_value]"
+
+	# select router
+	irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
+
+	# ROUTER instructions are 32 bits wide
+	set old_dr_value 0x[drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+#	echo "\tOld router value:\t0x[format %x $old_dr_value]"
+}
+
+# Configure the icepick control register
+proc icepick_c_setup {jrc} {
+
+	# send a router write, block is 0, register is 1, value is 0x2100
+	icepick_c_router $jrc 1 0x0 0x1 0x001000
+}
+
+# jrc	== TAP name for the ICEpick
+# port	== a port number, 0..15 for debug tap, 16..31 for test tap
+proc icepick_c_tapenable {jrc port} {
+
+	if { ($port >= 0) && ($port < 16) } {
+		# Debug tap"
+		set tap $port
+		set block 0x2
+	} elseif { $port < 32 } {
+		# Test tap
+		set tap [expr {$port - 16}]
+		set block 0x1
+	} else {
+		echo "ERROR: Invalid ICEPick C port number: $port"
+		return
+	}
+
+	# First CONNECT to the ICEPick
+#	echo "Connecting to ICEPick"
+	icepick_c_connect $jrc
+
+#	echo "Configuring the ICEpick"
+	icepick_c_setup $jrc
+
+	# NOTE: it's important not to enter RUN/IDLE state until
+	# done sending these instructions and data to the ICEpick.
+	# And never to enter RESET, which will disable the TAPs.
+
+	# first enable power and clock for TAP
+	icepick_c_router $jrc 1 $block $tap 0x110048
+
+	# TRM states that the register should be read back here, skipped for now
+
+	# enable debug "default" mode
+	icepick_c_router $jrc 1 $block $tap 0x112048
+
+	# TRM states that debug enable and debug mode should be read back and
+	# confirmed - skipped for now
+
+	# Finally select the tap
+	icepick_c_router $jrc 1 $block $tap 0x112148
+
+	# Enter the bypass state
+	irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
+	runtest 10
+}
+
+# jrc	== TAP name for the ICEpick
+# coreid== core id number 0..15 (not same as port number!)
+proc icepick_d_set_core_control {jrc coreid value } {
+	icepick_c_router $jrc 1 0x6 $coreid $value
+}
+
+# jrc	== TAP name for the ICEpick
+# port	== a port number, 0..15
+# Follow the sequence described in
+# http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
+proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
+
+	# First CONNECT to the ICEPick
+	icepick_c_connect $jrc
+	icepick_c_setup $jrc
+
+	# Select the port
+	icepick_c_router $jrc 1 0x2 $port 0x2108
+
+	# Set icepick core control for $coreid
+	icepick_d_set_core_control $jrc $coreid $value
+
+	# Enter the bypass state
+	irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE
+	runtest 10
+}
+
+# This function uses the ICEPick to send a warm system reset
+proc icepick_c_wreset {jrc} {
+
+	# send a router write, block is 0, register is 1, value is 0x2100
+	icepick_c_router $jrc 1 0x0 0x1 0x002101
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx.cfg
new file mode 100644
index 0000000..d76f60e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# utility fn's for Freescale i.MX series
+
+global TARGETNAME
+set TARGETNAME $_TARGETNAME
+
+# rewrite commands of the form below to arm11 mcr...
+#	Data.Set c15:0x042f %long 0x40000015
+proc setc15 {regs value} {
+	global TARGETNAME
+
+	echo [format "set p15 0x%04x, 0x%08x" $regs $value]
+
+	arm mcr 15 [expr {($regs>>12)&0x7}] [expr {($regs>>0)&0xf}] [expr {($regs>>4)&0xf}] [expr {($regs>>8)&0x7}] $value
+}
+
+
+proc imx3x_reset {} {
+	# this reset script comes from the Freescale PDK
+	#
+	# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
+
+	echo "Target Setup: initialize DRAM controller and peripherals"
+
+#	Data.Set c15:0x01 %long 0x00050078
+	setc15 0x01 0x00050078
+
+	echo "configuring CP15 for enabling the peripheral bus"
+#	Data.Set c15:0x042f %long 0x40000015
+	setc15 0x042f 0x40000015
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx21.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx21.cfg
new file mode 100644
index 0000000..7c9cca3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx21.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+#
+# Hmmm.... should srst_pulls_trst be used here like i.MX27???
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx21
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+
+# Note above there is 1 tap
+
+# The CPU tap
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0792611f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx25.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx25.cfg
new file mode 100644
index 0000000..ed94cc0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx25.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# imx25 config
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx25
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x1b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0x0f -expected-id $_ETBTAPID
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id 0x0
+
+if { [info exists SDMATAPID] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x0882301d
+}
+jtag newtap $_CHIPNAME sdma -irlen 5 -expected-id $_SDMATAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN \
+		-chain-position $_TARGETNAME
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx27.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx27.cfg
new file mode 100644
index 0000000..c79d85e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx27.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# page 3-34 of "MCIMC27 Multimedia Applications Processor Reference Manual, Rev 0.3"
+# SRST pulls TRST
+#
+# Without setting these options correctly you'll see all sorts
+# of weird errors, e.g. MOE=0xe, invalid cpsr values, reset
+# failing, etc.
+reset_config trst_and_srst srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx27
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+
+# Note above there are 2 taps
+
+# trace buffer
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x1b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
+
+# The CPU tap
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926121
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+# REVISIT what operating environment sets up this virtual address mapping?
+$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \
+	-work-area-size 0x8000 -work-area-backup 1
+# Internal to the chip, there is 45K of SRAM
+#
+
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx28.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx28.cfg
new file mode 100644
index 0000000..d52fc4e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx28.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# i.MX28 config file.
+# based off of the imx21.cfg file.
+
+reset_config trst_and_srst
+
+#jtag nTRST and nSRST delay
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx28
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+
+# Note above there is 1 tap
+
+# The CPU tap
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x079264f3
+}
+jtag newtap $_CHIPNAME cpu  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# Create the GDB Target.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx31.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx31.cfg
new file mode 100644
index 0000000..10e9fef
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx31.cfg
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# imx31 config
+#
+
+reset_config trst_and_srst srst_gates_jtag
+
+adapter srst delay 5
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx31
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07b3601d
+}
+
+if { [info exists SDMATAPID] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x2190101d
+}
+
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x2b900f0f
+}
+
+#========================================
+
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
+
+# The "SDMA" - mart  controller debug tap
+# Based on some IO pins - this can be disabled & removed
+# See diagram: 6-14
+#   SIGNAL NAME:
+#    SJC_MOD - controls multiplexer - disables ARM1136
+#    SDMA_BYPASS - disables SDMA    -
+#
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+# No IDCODE for this TAP
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
+
+# Per section 40.17.1, table 40-85 the IR register is 4 bits
+# But this conflicts with Diagram 6-13, "3bits ir and drs"
+jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx35.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx35.cfg
new file mode 100644
index 0000000..fa173bb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx35.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# imx35 config
+#
+
+reset_config trst_and_srst srst_gates_jtag
+jtag_ntrst_delay 100
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx35
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07b3601d
+}
+
+if { [info exists SDMATAPID] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x0882601d
+}
+
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x2b900f0f
+}
+
+#========================================
+
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+# No IDCODE for this TAP
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0
+
+jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx51.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx51.cfg
new file mode 100644
index 0000000..fc3dfa9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx51.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Freescale i.MX51
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx51
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x1ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+        -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
+
+# SJC
+if { [info exists SJC_TAPID] } {
+   set _SJC_TAPID SJC_TAPID
+} else {
+   set _SJC_TAPID 0x0190c01d
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
+        -expected-id $_SJC_TAPID -ignore-version
+
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
+
+proc imx51_dbginit {target} {
+     # General Cortex-A8 debug initialisation
+     cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx53.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx53.cfg
new file mode 100644
index 0000000..855a6ae
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx53.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Freescale i.MX53
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx53
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x1ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+        -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
+
+# SJC
+if { [info exists SJC_TAPID] } {
+   set _SJC_TAPID SJC_TAPID
+} else {
+   set _SJC_TAPID 0x0190d01d
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
+        -expected-id $_SJC_TAPID -ignore-version
+
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
+
+proc imx53_dbginit {target} {
+     # General Cortex-A8 debug initialisation
+     cortex_a dbginit
+}
+
+$_TARGETNAME configure -event reset-assert-post "imx53_dbginit $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx6.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx6.cfg
new file mode 100644
index 0000000..c9b6acf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx6.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale i.MX6 series
+#
+# Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
+#
+# Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx6
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
+
+# System JTAG Controller
+
+# List supported SJC TAPIDs from imx reference manuals:
+set _SJC_TAPID_6Q   0x0191c01d
+set _SJC_TAPID_6D   0x0191e01d
+set _SJC_TAPID_6QP  0x3191c01d
+set _SJC_TAPID_6DP  0x3191d01d
+set _SJC_TAPID_6DL  0x0891a01d
+set _SJC_TAPID_6S   0x0891b01d
+set _SJC_TAPID_6SL  0x0891f01d
+set _SJC_TAPID_6SLL 0x088c201d
+
+# Allow external override of the first SJC TAPID
+if { [info exists SJC_TAPID] } {
+    set _SJC_TAPID $SJC_TAPID
+} else {
+    set _SJC_TAPID $_SJC_TAPID_6Q
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
+        -ignore-version \
+        -expected-id $_SJC_TAPID \
+        -expected-id $_SJC_TAPID_6QP \
+        -expected-id $_SJC_TAPID_6DP \
+        -expected-id $_SJC_TAPID_6D \
+        -expected-id $_SJC_TAPID_6DL \
+        -expected-id $_SJC_TAPID_6S \
+        -expected-id $_SJC_TAPID_6SL \
+        -expected-id $_SJC_TAPID_6SLL
+
+# GDB target: Cortex-A9, using DAP, configuring only one core
+# Base addresses of cores:
+# core 0  -  0x82150000
+# core 1  -  0x82152000
+# core 2  -  0x82154000
+# core 3  -  0x82156000
+set _TARGETNAME $_CHIPNAME.cpu.0
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x82150000
+
+# some TCK cycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
+
+proc imx6_dbginit {target} {
+        # General Cortex-A8/A9 debug initialisation
+        cortex_a dbginit
+}
+
+# Slow speed to be sure it will work
+adapter speed 1000
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
+
+$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx6sx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx6sx.cfg
new file mode 100644
index 0000000..3d4240a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx6sx.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale i.MX6SoloX
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME imx6sx
+}
+
+# 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4
+
+jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
+
+# System JTAG Controller
+if { [info exists SJC_TAPID] } {
+    set _SJC_TAPID $SJC_TAPID
+} else {
+    set _SJC_TAPID 0x0891c01d
+}
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
+        -expected-id $_SJC_TAPID -ignore-version
+
+# Cortex-A9 (boot core)
+target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \
+        -coreid 0 -dbgbase 0x82150000
+
+# Cortex-M4 (default off)
+target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \
+        -ap-num 0 -defer-examine
+
+# AHB mem-ap target
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0
+
+# Default target is Cortex-A9
+targets $_CHIPNAME.cpu_a9
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx6ul.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx6ul.cfg
new file mode 100644
index 0000000..354745e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx6ul.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale i.MX6UltraLite series: 6UL 6ULL 6ULZ
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME imx6ul
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
+
+# System JTAG Controller
+set _SJC_TAPID_6UL  0x0891d01d
+set _SJC_TAPID_6ULL 0x0891e01d
+set _SJC_TAPID_6ULZ 0x1891e01d
+
+# Allow external override of the first SJC TAPID
+if { [info exists SJC_TAPID] } {
+    set _SJC_TAPID $SJC_TAPID
+} else {
+    set _SJC_TAPID $_SJC_TAPID_6UL
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
+        -ignore-version \
+        -expected-id $_SJC_TAPID \
+        -expected-id $_SJC_TAPID_6ULL \
+        -expected-id $_SJC_TAPID_6ULZ \
+
+# Create DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Main AHB bus
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# Cortex-A7 single core
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x82130000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx7.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx7.cfg
new file mode 100644
index 0000000..bd9e3dd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx7.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx7
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+#
+# Cortex-A7 target
+#
+# GDB target: Cortex-A7, using DAP, configuring only one core
+# Base addresses of cores:
+# core 0  -  0x80070000
+# core 1  -  0x80072000
+set _TARGETNAME $_CHIPNAME.cpu_a7
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x80070000
+
+target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap \
+        -coreid 1 -dbgbase 0x80072000 -defer-examine
+#
+# Cortex-M4 target
+#
+set _TARGETNAME_2 $_CHIPNAME.cpu_m4
+target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.dap -ap-num 4 \
+        -defer-examine
+
+#
+# AHB mem-ap target
+#
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+targets $_TARGETNAME.0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx7ulp.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx7ulp.cfg
new file mode 100644
index 0000000..1467f7c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx7ulp.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP i.MX7ULP: Cortex-A7 + Cortex-M4
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME imx7ulp
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    # TAPID is from FreeScale!
+    set _DAP_TAPID 0x188e101d
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Cortex-A7
+target create $_CHIPNAME.cpu_a7 cortex_a -dap $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x80030000
+
+# Cortex-M4
+# Boots by default so don't defer examination
+target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap -ap-num 3
+
+# AHB main soc bus
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# Default is Cortex-A7
+targets $_CHIPNAME.cpu_a7
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx8m.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx8m.cfg
new file mode 100644
index 0000000..6938090
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx8m.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for NXP i.MX8M family of SoCs
+#
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx8m
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 1
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+# the DAP tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+
+set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -baseaddr [lindex $CTIBASE $_core]
+
+    set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command $_TARGETNAME.$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp $_TARGETNAME.$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+# declare the auxiliary Cortex-M4 core on AP #4
+target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \
+               -defer-examine
+
+# AHB-AP for direct access to soc bus
+target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# default target is A53 core 0
+targets $_TARGETNAME.0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx8mp.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx8mp.cfg
new file mode 100644
index 0000000..bddbcfd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx8mp.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for NXP i.MX8M Plus SoCs
+#
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx8m
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 1
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+# the DAP tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+
+set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -baseaddr [lindex $CTIBASE $_core]
+
+    target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core
+}
+
+# declare the auxiliary Cortex-M7 core on AP #4
+target create ${_CHIPNAME}.m7 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4
+
+# AHB-AP for direct access to soc bus
+target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# default target is A53 core 0
+targets $_TARGETNAME.0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx8qm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx8qm.cfg
new file mode 100644
index 0000000..33f9ca1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/imx8qm.cfg
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP i.MX8QuadMax
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx8qm
+}
+
+# CoreSight Debug Access Port (DAP)
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    # TAPID is from FreeScale!
+    set _DAP_TAPID 0x1890101d
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# AXI: Main SOC bus on AP #0
+target create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# 4x Cortex-A53 on AP #6
+set _A53_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set _A53_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+cti create $_CHIPNAME.a53_cti.0 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 0]
+cti create $_CHIPNAME.a53_cti.1 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 1]
+cti create $_CHIPNAME.a53_cti.2 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 2]
+cti create $_CHIPNAME.a53_cti.3 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 3]
+target create $_CHIPNAME.a53.0 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a53_cti.0 -dbgbase [lindex $_A53_DBGBASE 0]
+target create $_CHIPNAME.a53.1 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a53_cti.1 -dbgbase [lindex $_A53_DBGBASE 1] -defer-examine
+target create $_CHIPNAME.a53.2 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a53_cti.2 -dbgbase [lindex $_A53_DBGBASE 2] -defer-examine
+target create $_CHIPNAME.a53.3 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a53_cti.3 -dbgbase [lindex $_A53_DBGBASE 3] -defer-examine
+
+# 2x Cortex-A72 on AP #6
+set _A72_DBGBASE {0x80210000 0x80310000}
+set _A72_CTIBASE {0x80220000 0x80220000}
+
+cti create $_CHIPNAME.a72_cti.0 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 0]
+cti create $_CHIPNAME.a72_cti.1 -dap $_CHIPNAME.dap \
+            -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 1]
+target create $_CHIPNAME.a72.0 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a72_cti.0 -dbgbase [lindex $_A72_DBGBASE 0] -defer-examine
+target create $_CHIPNAME.a72.1 aarch64 -dap $_CHIPNAME.dap \
+            -cti $_CHIPNAME.a72_cti.1 -dbgbase [lindex $_A72_DBGBASE 1] -defer-examine
+
+# All Cortex-A in SMP
+target smp \
+        $_CHIPNAME.a53.0 \
+        $_CHIPNAME.a53.1 \
+        $_CHIPNAME.a53.2 \
+        $_CHIPNAME.a53.3 \
+        $_CHIPNAME.a72.0 \
+        $_CHIPNAME.a72.1
+
+# SCU: Cortex-M4 core
+# always running imx SC firmware
+target create ${_CHIPNAME}.scu cortex_m -dap ${_CHIPNAME}.dap -ap-num 1
+
+# AHB from SCU perspective
+target create ${_CHIPNAME}.scu_ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 4
+
+# Cortex-M4 M4_0 core on AP #2 (default off)
+target create ${_CHIPNAME}.m4_0 cortex_m -dap ${_CHIPNAME}.dap -ap-num 2 \
+        -defer-examine
+
+# Cortex-M4 M4_1 core on AP #3 (default off)
+target create ${_CHIPNAME}.m4_1 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3 \
+        -defer-examine
+
+# Debug APB bus
+target create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 6
+
+# Default target is boot core a53.0
+targets $_CHIPNAME.a53.0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/infineon/tle987x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/infineon/tle987x.cfg
new file mode 100644
index 0000000..ac3db6c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/infineon/tle987x.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon TLE987x family (Arm Cortex-M3 @ up to 40 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME tle987x
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x2BA01477
+}
+
+if { [using_jtag] } {
+	# JTAG not supported, only SWD
+	set _CPU_TAPID 0
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME dap -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/is5114.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/is5114.cfg
new file mode 100644
index 0000000..d0b1d92
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/is5114.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Insilica IS-5114
+# AKA: Atmel AT76C114 - an ARM946 chip
+# ATMEL sold his product line to Insilica...
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME is5114
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a little endian
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # Force an error until we get a good number.
+   set _CPUTAPID 0xffffffff
+}
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+adapter speed 16
+
+reset_config trst_and_srst
+
+# Do not specify a tap id here...
+jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1
+# This is the "arm946" chip.
+jtag newtap $_CHIPNAME cpu      -irlen 4 -ircapture 0x0e -irmask 0xf
+jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
+
+
+#arm946e-s and
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	adapter speed 3000
+}
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ixp42x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ixp42x.cfg
new file mode 100644
index 0000000..5c8e903
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ixp42x.cfg
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#xscale ixp42x CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME ixp42x
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a bigendian
+   set _ENDIAN big
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x19274013
+}
+set _CPUTAPID2 0x19275013
+set _CPUTAPID3 0x19277013
+set _CPUTAPID4 0x29274013
+set _CPUTAPID5 0x29275013
+set _CPUTAPID6 0x29277013
+
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
+
+
+# register constants for IXP42x SDRAM controller
+global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
+global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
+set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD	0x0000
+set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD	0x0001
+
+global IXP42x_SDRAM_CL3
+global IXP42x_SDRAM_CL2
+set IXP42x_SDRAM_CL3			0x0008
+set IXP42x_SDRAM_CL2			0x0000
+
+global IXP42x_SDRAM_8MB_2Mx32_1BANK
+global IXP42x_SDRAM_16MB_2Mx32_2BANK
+global IXP42x_SDRAM_16MB_4Mx16_1BANK
+global IXP42x_SDRAM_32MB_4Mx16_2BANK
+global IXP42x_SDRAM_32MB_8Mx16_1BANK
+global IXP42x_SDRAM_64MB_8Mx16_2BANK
+global IXP42x_SDRAM_64MB_16Mx16_1BANK
+global IXP42x_SDRAM_128MB_16Mx16_2BANK
+global IXP42x_SDRAM_128MB_32Mx16_1BANK
+global IXP42x_SDRAM_256MB_32Mx16_2BANK
+
+set IXP42x_SDRAM_8MB_2Mx32_1BANK	0x0030
+set IXP42x_SDRAM_16MB_2Mx32_2BANK	0x0031
+set IXP42x_SDRAM_16MB_4Mx16_1BANK	0x0032
+set IXP42x_SDRAM_32MB_4Mx16_2BANK	0x0033
+set IXP42x_SDRAM_32MB_8Mx16_1BANK	0x0010
+set IXP42x_SDRAM_64MB_8Mx16_2BANK	0x0011
+set IXP42x_SDRAM_64MB_16Mx16_1BANK	0x0012
+set IXP42x_SDRAM_128MB_16Mx16_2BANK	0x0013
+set IXP42x_SDRAM_128MB_32Mx16_1BANK	0x0014
+set IXP42x_SDRAM_256MB_32Mx16_2BANK	0x0015
+
+
+# helper function to init SDRAM on IXP42x.
+# SDRAM_CFG: one of IXP42X_SDRAM_xxx
+# REFRESH: refresh counter reload value (integer)
+# CASLAT: 2 or 3
+proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
+
+    switch $CASLAT {
+	2 {
+	    set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL2} ]
+	    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
+	}
+	3 {
+	    set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL3} ]
+	    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
+	}
+	default { error [format "unsupported cas latency \"%s\" " $CASLAT] }
+    }
+    echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH]
+
+    mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3
+    mww 0xCC000004          0 ;# disable refresh
+    mww 0xCC000008          3 ;# NOP
+    sleep 100
+    mww 0xCC000004   $REFRESH ;# set refresh counter
+    mww 0xCC000008          2 ;# Precharge All Banks
+    sleep 100
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008          4 ;# Auto Refresh
+    mww 0xCC000008    $CASCMD ;# Mode Select CL2/CL3
+}
+
+proc ixp42x_set_bigendian { } {
+    reg XSCALE_CTRL 0xF8
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/k1921vk01t.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/k1921vk01t.cfg
new file mode 100644
index 0000000..a9500ef
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/k1921vk01t.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# K1921VK01T
+# http://niiet.ru/chips/nis?id=354
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME k1921vk01t
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      # SWD IDCODE
+      set _CPUTAPID 0x2ba01477
+   }
+}
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME
+
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/k40.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/k40.cfg
new file mode 100644
index 0000000..33e8235
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/k40.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis K40 devices
+#
+
+set CHIPNAME k40
+source [find target/kx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/k60.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/k60.cfg
new file mode 100644
index 0000000..3b89102
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/k60.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis K60 devices
+#
+
+set CHIPNAME k60
+source [find target/kx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ke0x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ke0x.cfg
new file mode 100644
index 0000000..b357767
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ke0x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis KE0x and KEAx series devices
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME ke
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+
+   # It is important that "kinetis_ke mdm check_security" is called for
+   # 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start'
+   # causes "kinetis_ke mdm check_security" to fail the first time openocd
+   # calls it when it tries to connect after the CPU has been power-cycled.
+   $_CHIPNAME.cpu configure -event examine-end {
+      kinetis_ke mdm check_security
+   }
+
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ke1xf.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ke1xf.cfg
new file mode 100644
index 0000000..86a1f3b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ke1xf.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP (Freescale) Kinetis KE1xF devices
+#
+
+set CHIPNAME ke
+
+source [find target/kx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ke1xz.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ke1xz.cfg
new file mode 100644
index 0000000..9e91542
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ke1xz.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP (Freescale) Kinetis KE1xZ devices
+#
+
+set CHIPNAME ke
+
+source [find target/klx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/kl25.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/kl25.cfg
new file mode 100644
index 0000000..916edf6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/kl25.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis KL25 devices
+#
+
+set CHIPNAME kl25
+source [find target/klx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/kl46.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/kl46.cfg
new file mode 100644
index 0000000..bf6b244
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/kl46.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Kinetis KL46 devices
+#
+
+set CHIPNAME kl46
+source [find target/klx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/klx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/klx.cfg
new file mode 100644
index 0000000..cd236b3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/klx.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP (former Freescale) Kinetis KL series devices
+# Also used for Cortex-M0+ equipped members of KVx and KE1xZ series
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME klx
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1KiB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.pflash
+flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
+kinetis create_banks
+
+# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
+# specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;
+# Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {[using_hla]} {
+   echo ""
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions."
+   echo " A high level adapter (like a ST-Link) you are currently using cannot access"
+   echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your"
+   echo " configuration. Also security locked state of the device will not be reported."
+   echo ""
+   echo " Be very careful as you can lock the device though there is no way to unlock"
+   echo " it without mass erase. Don't set write protection on the first block."
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo ""
+} else {
+   # Detect secured MCU
+   $_TARGETNAME configure -event examine-fail {
+      kinetis mdm check_security
+   }
+
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+# Disable watchdog not to disturb OpenOCD algorithms running on MCU
+# (e.g. armv7m_checksum_memory() in verify_image)
+# Flash driver also disables watchdog before FTFA flash programming.
+$_TARGETNAME configure -event reset-init {
+   kinetis disable_wdog
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ks869x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ks869x.cfg
new file mode 100644
index 0000000..06e710b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ks869x.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ARM920T CPU
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME ks869x
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set  _CPUTAPID $CPUTAPID
+} else {
+   set  _CPUTAPID 0x00922f0f
+}
+
+adapter speed 6000
+
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/kx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/kx.cfg
new file mode 100644
index 0000000..c87116b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/kx.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP (former Freescale) Kinetis Kx series devices
+# Also used for Cortex-M4 equipped members of KVx and KE1xF series
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME kx
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.pflash
+flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
+kinetis create_banks
+
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {[using_hla]} {
+   echo ""
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions."
+   echo " A high level adapter (like a ST-Link) you are currently using cannot access"
+   echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your"
+   echo " configuration. Also security locked state of the device will not be reported."
+   echo " Expect problems connecting to a blank device without boot ROM."
+   echo ""
+   echo " Be very careful as you can lock the device though there is no way to unlock"
+   echo " it without mass erase. Don't set write protection on the first block."
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo ""
+} else {
+   # Detect secured MCU or boot lock-up in RESET/WDOG loop
+   $_TARGETNAME configure -event examine-fail {
+      kinetis mdm check_security
+   }
+   # During RESET/WDOG loop the target is sometimes falsely examined
+   $_TARGETNAME configure -event examine-end {
+      kinetis mdm check_security
+   }
+
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+# Disable watchdog not to disturb OpenOCD algorithms running on MCU
+# (e.g. armv7m_checksum_memory() in verify_image)
+# Flash driver also disables watchdog before FTFA flash programming.
+$_TARGETNAME configure -event reset-init {
+   kinetis disable_wdog
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc11xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc11xx.cfg
new file mode 100644
index 0000000..d288e2a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc11xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC11xx Cortex-M0 with at least 1kB SRAM
+set CHIPNAME lpc11xx
+set CHIPSERIES lpc1100
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x400
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc12xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc12xx.cfg
new file mode 100644
index 0000000..ace5e06
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc12xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC12xx Cortex-M0 with at least 4kB SRAM
+set CHIPNAME lpc12xx
+set CHIPSERIES lpc1200
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x1000
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc13xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc13xx.cfg
new file mode 100644
index 0000000..5ac29d3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc13xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC13xx Cortex-M3 with at least 4kB SRAM
+set CHIPNAME lpc13xx
+set CHIPSERIES lpc1300
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x1000
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc17xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc17xx.cfg
new file mode 100644
index 0000000..35d8bad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc17xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC17xx Cortex-M3 with at least 8kB SRAM
+set CHIPNAME lpc17xx
+set CHIPSERIES lpc1700
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x2000
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc1850.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc1850.cfg
new file mode 100644
index 0000000..6dd1ab7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc1850.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/swj-dp.tcl]
+
+adapter speed 500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME lpc1850
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+#
+# M3 JTAG mode TAP
+#
+if { [info exists M3_JTAG_TAPID] } {
+   set _M3_JTAG_TAPID $M3_JTAG_TAPID
+} else {
+   set _M3_JTAG_TAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.m3
+
+set _TARGETNAME $_CHIPNAME.m3
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc1xxx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc1xxx.cfg
new file mode 100644
index 0000000..70d26d2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc1xxx.cfg
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
+#
+# !!!!!!
+#
+# This file should not be included directly, rather by the lpc11xx.cfg,
+# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
+# appropriate values.
+#
+# !!!!!!
+
+# LPC8xx chips support only SWD transport.
+# LPC11xx chips support only SWD transport.
+# LPC12xx chips support only SWD transport.
+# LPC11Uxx chips support only SWD transports.
+# LPC13xx chips support only SWD transports.
+# LPC17xx chips support both JTAG and SWD transports.
+# LPC40xx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
+}
+
+if { [info exists CHIPSERIES] } {
+	# Validate chip series is supported
+	if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700"  && $CHIPSERIES != "lpc4000" } {
+		error "Unsupported LPC1xxx chip series specified."
+	}
+	set _CHIPSERIES $CHIPSERIES
+} else {
+	error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
+}
+
+# After reset, the chip is clocked by an internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK] } {
+	# Allow user override
+	set _CCLK $CCLK
+} else {
+	# LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
+	if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
+		set _CCLK 12000
+	} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+		set _CCLK 4000
+	}
+}
+
+if { [info exists CPUTAPID] } {
+	# Allow user override
+	set _CPUTAPID $CPUTAPID
+} else {
+	# LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
+	if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
+		set _CPUTAPID 0x0bb11477
+	} elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+		if { [using_jtag] } {
+			set _CPUTAPID 0x4ba00477
+		} {
+			set _CPUTAPID 0x2ba01477
+		}
+	}
+}
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
+
+# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
+# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
+# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
+# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
+# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
+# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
+#
+# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
+# (same cmd51 destination boundary alignment, and all three support 256 byte
+# transfers).
+#
+# flash bank  lpc2000   0 0    [calc checksum] [iap entry]
+set _IAP_ENTRY 0
+if { [info exists IAP_ENTRY] } {
+	set _IAP_ENTRY $IAP_ENTRY
+}
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
+	auto $_CCLK calc_checksum $_IAP_ENTRY
+
+if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
+	# Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
+	# Bit Symbol Value Description
+	# 1:0 MAP          System memory remap
+	#            0x0   Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
+	#            0x1   User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
+	#            0x2   User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
+	# 31:2 -     -     Reserved.
+	$_TARGETNAME configure -event reset-init {
+		mww 0x40048000 0x02
+	}
+} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+	# Bit Symbol Value Description Reset
+	# value
+	# 0 MAP Memory map control. 0
+	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+	# 1 User mode. The on-chip Flash memory is mapped to address 0.
+	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+	#
+	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+	$_TARGETNAME configure -event reset-init {
+		mww 0x400FC040 0x01
+	}
+}
+
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+adapter speed 10
+
+# delays on reset lines
+adapter srst delay 200
+if {[using_jtag]} {
+ jtag_ntrst_delay 200
+}
+
+# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
+# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
+# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
+# LPC40xx (Cortex-M4F core) support SYSRESETREQ
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2103.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2103.cfg
new file mode 100644
index 0000000..c49b0e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2103.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2103 ARM7TDMI-S with 32kB flash and 8kB SRAM, clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2103 {core_freq_khz adapter_freq_khz} {
+	# 32kB flash and 8kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2103 0x4f1f0f0f 0x8000 lpc2000_v2 0x2000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2103  
+	setup_lpc2103 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2124.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2124.cfg
new file mode 100644
index 0000000..053ebeb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2124.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2124 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2124 {core_freq_khz adapter_freq_khz} {
+	# 256kB flash and 16kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2124 0x4f1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2124  
+	setup_lpc2124 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2129.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2129.cfg
new file mode 100644
index 0000000..88ee20f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2129.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2129 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2129 {core_freq_khz adapter_freq_khz} {
+	# 256kB flash and 16kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2129 0xcf1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2129  
+	setup_lpc2129 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2148.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2148.cfg
new file mode 100644
index 0000000..fda622f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2148.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2148 ARM7TDMI-S with 512kB flash (12kB used by bootloader) and 40kB SRAM (8kB for USB DMA), clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2148 {core_freq_khz adapter_freq_khz} {
+	# 500kB flash and 32kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2148 "0x3f0f0f0f 0x4f1f0f0f" 0x7d000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2148  
+	setup_lpc2148 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2294.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2294.cfg
new file mode 100644
index 0000000..7537a65
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2294.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2294 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
+	# 256kB flash and 16kB SRAM
+	# setup_lpc2xxx       
+
+	# !! TAPID unknown !!
+	setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 12MHz crystal
+	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2294  
+	setup_lpc2294 12000 1500
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2378.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2378.cfg
new file mode 100644
index 0000000..59e41c9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2378.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2378 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 56kB SRAM (16kB for ETH, 8kB for DMA), clocked with 4MHz internal oscillator
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2378 {core_freq_khz adapter_freq_khz} {
+	# 504kB flash and 32kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2378 0x4f1f0f0f 0x7e000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 4MHz internal oscillator
+	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2378  
+	setup_lpc2378 4000 500
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2460.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2460.cfg
new file mode 100644
index 0000000..59b6466
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2460.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2460 ARM7TDMI-S with 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2460 {core_freq_khz adapter_freq_khz} {
+	# 64kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2460 0x4f1f0f0f 0 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 4MHz internal oscillator
+	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2460  
+	setup_lpc2460 4000 500
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2478.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2478.cfg
new file mode 100644
index 0000000..e4fd49d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2478.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC2478 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator
+
+source [find target/lpc2xxx.cfg]
+
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2478 {core_freq_khz adapter_freq_khz} {
+	# 504kB flash and 64kB SRAM
+	# setup_lpc2xxx       
+	setup_lpc2xxx lpc2478 0x4f1f0f0f 0x7e000 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz
+}
+
+proc init_targets {} {
+	# default to core clocked with 4MHz internal oscillator
+	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
+
+	# setup_lpc2478  
+	setup_lpc2478 4000 500
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2900.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2900.cfg
new file mode 100644
index 0000000..67e3c92
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2900.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME lpc2900
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x0596802B
+}
+
+if { [info exists HAS_ETB] } {
+} else {
+    # Set default (no ETB).
+    # Show a warning, because this should have been configured explicitly.
+    set HAS_ETB 0
+    # TODO: warning?
+}
+
+if { [info exists ETBTAPID] } {
+    set _ETBTAPID $ETBTAPID
+} else {
+    set _ETBTAPID 0x1B900F0F
+}
+
+# TRST and SRST both exist, and can be controlled independently
+reset_config trst_and_srst separate
+
+# Define the _TARGETNAME
+set _TARGETNAME $_CHIPNAME.cpu
+
+# Include the ETB tap controller if asked for.
+# Has to be done manually for newer devices (not an "old" LPC2917/2919).
+if { $HAS_ETB == 1 } {
+    # Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
+    set HAS_ETB 0
+
+    # Add the ETB tap controller and the ARM9 core debug tap
+    jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
+    jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+    # Create the ".cpu" target
+    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
+
+    # Configure ETM and ETB
+    etm config $_TARGETNAME 8 normal full etb
+    etb config $_TARGETNAME $_CHIPNAME.etb
+
+} else {
+    # Add the ARM9 core debug tap
+    jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+    # Create the ".cpu" target
+    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
+}
+
+arm7_9 dbgrq enable
+arm7_9 dcc_downloads enable
+
+# Flash bank configuration:
+# Flash: flash bank lpc2900 0 0 0 0  
+# Flash base address, total flash size, and number of sectors are all configured automatically.
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2xxx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2xxx.cfg
new file mode 100644
index 0000000..bc5e600
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc2xxx.cfg
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Common setup for the LPC2xxx parts
+
+# parameters:
+# - chip_name - name of the chip, e.g. lpc2103
+# - cputapids - TAP IDs of the core, should be quoted if more than one, e.g. 0x4f1f0f0f or "0x3f0f0f0f 0x4f1f0f0f"
+# - flash_size - size of on-chip flash (available for code, not including the bootloader) in bytes, e.g. 0x8000
+# - flash_variant - "type" of LPC2xxx device, lpc2000_v1 (LPC22xx and older LPC21xx) or lpc2000_v2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
+# - workarea_size - size of work-area in RAM for flashing procedures, must not exceed the size of RAM available at 0x40000000, e.g. 0x2000
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
+
+proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size core_freq_khz adapter_freq_khz} {
+	reset_config trst_and_srst
+
+	# reset delays
+	adapter srst delay 100
+	jtag_ntrst_delay 100
+
+	adapter speed $adapter_freq_khz
+
+	foreach i $cputapids {
+		append expected_ids "-expected-id " $i " "
+	}
+
+	eval "jtag newtap $chip_name cpu -irlen 4 -ircapture 0x1 -irmask 0xf $expected_ids"
+
+	global _TARGETNAME
+	set _TARGETNAME $chip_name.cpu
+	target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
+
+	$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size $workarea_size -work-area-backup 0
+
+	if { $flash_size > 0 } {
+		# flash bank  lpc2000   0 0    [calc checksum]
+		set _FLASHNAME $chip_name.flash
+		flash bank $_FLASHNAME lpc2000 0x0 $flash_size 0 0 $_TARGETNAME $flash_variant $core_freq_khz calc_checksum
+	}
+}
+
+proc init_targets {} {
+	# FIX!!! read out CPUTAPID here and choose right setup. In addition to the
+	# CPUTAPID some querying of the target would be required.
+	return -error "This is a generic LPC2xxx configuration file, use a specific target file."
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc3131.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc3131.cfg
new file mode 100644
index 0000000..09d698a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc3131.cfg
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    NXP lpc3131
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lpc3131
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# ARM926EJS core
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926f0f
+}
+
+# Scan Tap
+# Wired to separate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
+# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
+if { [info exists SJCTAPID] } {
+   set _SJCTAPID $SJCTAPID
+} else {
+   set _SJCTAPID 0x1541E02B
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+##################################################################
+# various symbol definitions, to avoid hard-wiring addresses
+##################################################################
+
+global lpc313x
+set lpc313x [ dict create ]
+
+# Physical addresses for controllers and memory
+dict set lpc313x sram0			0x11028000
+dict set lpc313x sram1			0x11040000
+dict set lpc313x uart			0x15001000
+dict set lpc313x cgu			0x13004000
+dict set lpc313x ioconfig		0x13003000
+dict set lpc313x sysconfig		0x13002800
+dict set lpc313x wdt			0x13002400
+
+##################################################################
+# Target configuration
+##################################################################
+
+adapter srst delay 1000
+jtag_ntrst_delay 0
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME invoke-event halted
+
+$_TARGETNAME configure -work-area-phys [dict get $lpc313x sram0] -work-area-size 0x30000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+	echo "\nRunning reset init script for LPC3131\n"
+	halt
+	wait_halt
+	reg cpsr 0xa00000d3	;#Supervisor mode
+	reg pc 0x11029000
+	poll
+	sleep 500
+}
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc3250.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc3250.cfg
new file mode 100644
index 0000000..244d981
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc3250.cfg
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# lpc3250 config
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lpc3250
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x17900f0f
+}
+
+if { [info exists CPUTAPID_REV_A0] } {
+   set _CPUTAPID_REV_A0 $CPUTAPID_REV_A0
+} else {
+   set _CPUTAPID_REV_A0 0x17926f0f
+}
+
+if { [info exists SJCTAPID] } {
+   set _SJCTAPID $SJCTAPID
+} else {
+   set _SJCTAPID 0x1b900f0f
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID \
+     -expected-id $_CPUTAPID_REV_A0
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0
+
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc40xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc40xx.cfg
new file mode 100644
index 0000000..f0be5a1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc40xx.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC40xx Cortex-M4F with at least 16kB SRAM
+set CHIPNAME lpc40xx
+set CHIPSERIES lpc4000
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x4000
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc4350.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc4350.cfg
new file mode 100644
index 0000000..453306a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc4350.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/swj-dp.tcl]
+
+adapter speed 500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME lpc4350
+}
+
+#
+# M4 JTAG mode TAP
+#
+if { [info exists M4_JTAG_TAPID] } {
+	set _M4_JTAG_TAPID $M4_JTAG_TAPID
+} else {
+	set _M4_JTAG_TAPID 0x4ba00477
+}
+
+#
+# M4 SWD mode TAP
+#
+if { [info exists M4_SWD_TAPID] } {
+	set _M4_SWD_TAPID $M4_SWD_TAPID
+} else {
+	set _M4_SWD_TAPID 0x2ba01477
+}
+
+if { [using_jtag] } {
+	set _M4_TAPID $_M4_JTAG_TAPID
+} {
+	set _M4_TAPID $_M4_SWD_TAPID
+}
+
+#
+# M0 TAP
+#
+if { [info exists M0_JTAG_TAPID] } {
+	set _M0_JTAG_TAPID $M0_JTAG_TAPID
+} else {
+	set _M0_JTAG_TAPID 0x0ba01477
+}
+
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+				-expected-id $_M4_TAPID
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
+
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
+				-expected-id $_M0_JTAG_TAPID
+	dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0
+	target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap
+}
+
+# LPC4350 has 96+32 KB SRAM
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x20000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
+			-work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if {![using_hla]} {
+   # on this CPU we should use VECTRESET to perform a soft reset and
+   # manually reset the periphery
+   # SRST or SYSRESETREQ disable the debug interface for the time of
+   # the reset and will not fit our requirements for a consistent debug
+   # session
+   cortex_m reset_config vectreset
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc4357.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc4357.cfg
new file mode 100644
index 0000000..f783505
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc4357.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP LPC4357
+#
+
+if { ![info exists CHIPNAME] } {
+	set CHIPNAME lpc4357
+}
+set WORKAREASIZE 0x8000
+source [find target/lpc4350.cfg]
+
+flash bank $_CHIPNAME.flasha lpc2000 0x1A000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum
+flash bank $_CHIPNAME.flashb lpc2000 0x1B000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc4370.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc4370.cfg
new file mode 100644
index 0000000..fe9e76b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc4370.cfg
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
+#
+
+adapter speed 500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME lpc4370
+}
+
+#
+# M4 JTAG mode TAP
+#
+if { [info exists M4_JTAG_TAPID] } {
+	set _M4_JTAG_TAPID $M4_JTAG_TAPID
+} else {
+	set _M4_JTAG_TAPID 0x4ba00477
+}
+
+#
+# M4 SWD mode TAP
+#
+if { [info exists M4_SWD_TAPID] } {
+	set _M4_SWD_TAPID $M4_SWD_TAPID
+} else {
+	set _M4_SWD_TAPID 0x2ba01477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+	set _M4_TAPID $_M4_JTAG_TAPID
+} else {
+	set _M4_TAPID $_M4_SWD_TAPID
+}
+
+#
+# M0 TAP
+#
+if { [info exists M0_JTAG_TAPID] } {
+	set _M0_JTAG_TAPID $M0_JTAG_TAPID
+} else {
+	set _M0_JTAG_TAPID 0x0ba01477
+}
+
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+				-expected-id $_M4_TAPID
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
+
+# LPC4370 has 96+32 KB contiguous SRAM
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x20000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
+                        -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \
+					-expected-id $_M0_JTAG_TAPID
+	jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
+					-expected-id $_M0_JTAG_TAPID
+
+	dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
+	dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
+	target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
+	target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
+
+	# 32+8+32 KB SRAM
+	$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
+	                           -work-area-size 0x92000 -work-area-backup 0
+
+	# 16+2 KB M0 subsystem SRAM
+	$_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \
+	                           -work-area-size 0x4800 -work-area-backup 0
+
+	# Default to the Cortex-M4
+	targets $_CHIPNAME.m4
+}
+
+if { ![using_hla] } {
+	cortex_m reset_config vectreset
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc84x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc84x.cfg
new file mode 100644
index 0000000..af26f27
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc84x.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC84x Cortex-M0+ with at least 8kB SRAM
+if { ![info exists CHIPNAME] } {
+	set CHIPNAME lpc84x
+}
+set CHIPSERIES lpc800
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x1fe0
+}
+
+set IAP_ENTRY 0x0F001FF1
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc8nxx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc8nxx.cfg
new file mode 100644
index 0000000..859e99b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc8nxx.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM
+# Copyright (C) 2018 by Jean-Christian de Rivaz
+# Based on NXP proposal https://community.nxp.com/message/1011149
+# Many thanks to Dries Moors from NXP support.
+# SWD only transport
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME lpc8nxx
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+if {![using_hla]} {
+	# If srst is not fitted use SYSRESETREQ to  perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+adapter srst delay 100
+
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
+
+flash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500
+
+echo "*********************************************************************************"
+echo "*         !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!"
+echo "* When this IC is in power-off or peep power down mode, the SWD HW block is also"
+echo "* unpowered. These modes can be entered by firmware. The default firmware image"
+echo "* (flashed in production) makes use of this. Best is to avoid these power modes"
+echo "* during development, and only later add them when the functionality is complete."
+echo "* Hardware reset or NFC field are the only ways to connect in case the SWD is"
+echo "* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST"
+echo "* signal to the chip RESETN pin and add the following in your configuration:"
+echo "*     reset_config srst_only; flash init; catch init; reset"
+echo "* But if the actual firmware immediately set the power down mode after reset,"
+echo "* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In"
+echo "* that case the only solution is to apply a NFC field to keep the SWD powered."
+echo "*********************************************************************************"
+
+# Using soft-reset 'reset_config none' is strongly discouraged.
+# RESETN sets the system clock to 500 kHz. Unlike soft-reset does not.
+# Set the system clock to 500 kHz before reset to simulate the functionality of hw reset.
+#
+proc set_sysclk_500khz {} {
+	set SYSCLKCTRL 0x40048020
+	set SYSCLKUEN 0x40048024
+	mww $SYSCLKUEN 0
+	mmw $SYSCLKCTRL 0x8 0xe
+	mww $SYSCLKUEN 1
+	echo "Notice: sysclock set to 500kHz."
+}
+
+# Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
+# Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
+# Bit Symbol  Value   Description
+# 0   map         -   interrupt vector remap. 0 after boot.
+#                 0   interrupt vector reside in Flash
+#                 1   interrupt vector reside in SRAM
+# 5:1 offset      -   system memory remap offset. 00000b after boot.
+#            00000b   interrupt vectors in flash or remapped to SRAM but no offset
+#            00001b -
+#            00111b   interrupt vectors offset in flash or SRAM to 1K word segment
+#            01000b -
+#            11111b   interrupt vectors offset in flash to 1K word segment 8 to 31
+# 31:6                reserved
+#
+proc set_no_remap {} {
+	mww 0x40048000 0x00
+	echo "Notice: interrupt vector set to no remap."
+}
+
+$_TARGETNAME configure -event reset-init {
+	set_sysclk_500khz
+	set_no_remap
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc8xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc8xx.cfg
new file mode 100644
index 0000000..4c54a2a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lpc8xx.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC8xx Cortex-M0+ with at least 1kB SRAM
+if { ![info exists CHIPNAME] } {
+	set CHIPNAME lpc8xx
+}
+set CHIPSERIES lpc800
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x400
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1012a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1012a.cfg
new file mode 100644
index 0000000..7333ea8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1012a.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# NXP LS1012A
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ls1012a
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x5ba00477
+}
+
+if { [info exists SAP_TAPID] } {
+	set _SAP_TAPID $SAP_TAPID
+} else {
+	set _SAP_TAPID 0x06b2001d
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80420000
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase 0x80410000 -cti $_CHIPNAME.cti
+
+target smp $_TARGETNAME
+
+adapter speed 2000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1028a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1028a.cfg
new file mode 100644
index 0000000..463ec7d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1028a.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1028A
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ls1028a
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x6ba00477
+}
+
+set _CPUS 2
+
+source [find target/lsch3_common.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1046a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1046a.cfg
new file mode 100644
index 0000000..3d96a99
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1046a.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1046A
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ls1046a
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x5ba00477
+}
+
+if { [info exists SAP_TAPID] } {
+	set _SAP_TAPID $SAP_TAPID
+} else {
+	set _SAP_TAPID 0x06b3001d
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+set _CPU_BASE 0x80400000
+set _CPU_STRIDE 0x100000
+set _CPU_DBGOFF 0x10000
+set _CPU_CTIOFF 0x20000
+
+set _TARGETS {}
+for {set i 0} {$i < 4} {incr i} {
+	set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
+	cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 1 \
+		-baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
+	target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
+		-cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
+		-coreid $i {*}[expr {$i ? {-defer-examine} : {-rtos hwthread} }]
+	lappend _TARGETS $_CHIPNAME.cpu$i
+}
+
+target smp {*}$_TARGETS
+
+jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID
+target create $_CHIPNAME.sap ls1_sap -chain-position $_CHIPNAME.sap -endian big
+
+proc core_up { args } {
+    foreach core $args {
+        $::_CHIPNAME.cpu$core arp_examine
+    }
+}
+
+targets $_CHIPNAME.cpu0
+
+adapter speed 10000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1088a.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1088a.cfg
new file mode 100644
index 0000000..193d6dd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ls1088a.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1088A
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME ls1088a
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x5ba00477
+}
+
+set _CPUS 8
+
+source [find target/lsch3_common.cfg]
+
+# Seems to work OK in testing
+adapter speed 10000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lsch3_common.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lsch3_common.cfg
new file mode 100644
index 0000000..f48d59b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/lsch3_common.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This contains common configuration for NXP Layerscape chassis generation 3
+
+if { ![info exists _CPUS] } {
+	error "_CPUS must be set to the number of cores"
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1
+
+set _CPU_BASE 0x81000000
+set _CPU_STRIDE 0x100000
+set _CPU_DBGOFF 0x10000
+set _CPU_CTIOFF 0x20000
+
+set _TARGETS {}
+for {set i 0} {$i < $_CPUS} {incr i} {
+	set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
+	cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \
+		-baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
+	target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
+		-cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
+		{*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }]
+	lappend _TARGETS $_CHIPNAME.cpu$i
+}
+
+target smp {*}$_TARGETS
+
+# Service processor
+target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
+
+# Normally you will not need to call this, but if you are using the hard-coded
+# Reset Configuration Word (RCW) you will need to call this manually. The CPU's
+# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
+# instructions. This will cause the CPU to almost immediately execute an
+# illegal instruction.
+#
+# This code is idempotent; releasing a released CPU has no effect, although it
+# will halt/resume the service processor.
+add_help_text release_cpu "Release a cpu which is held off"
+proc release_cpu {cpu} {
+	set RST_BRRL 0x1e60060
+
+	set old [target current]
+	targets $::_CHIPNAME.sp
+	set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
+	if {$not_halted} {
+		halt
+	}
+
+	# Release the cpu; it will start executing something bogus
+	mem2array regs 32 $RST_BRRL 1
+	mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
+
+	if {$not_halted} {
+		resume
+	}
+	targets $old
+}
+
+targets $_CHIPNAME.cpu0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/88f3710.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/88f3710.cfg
new file mode 100644
index 0000000..dcc4516
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/88f3710.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell Armada 3710
+
+set CORES 1
+
+source [find target/marvell/88f37x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/88f3720.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/88f3720.cfg
new file mode 100644
index 0000000..7c29378
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/88f3720.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell Armada 3720
+
+set CORES 2
+
+source [find target/marvell/88f37x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/88f37x0.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/88f37x0.cfg
new file mode 100644
index 0000000..738d221
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/88f37x0.cfg
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Main file for Marvell Armada 3700 series targets
+#
+# !!!!!!
+#
+# This file should not be included directly. Instead, please include
+# either marvell/88f3710.cfg or marvell/88f3720.cfg, which set the needed
+# variables to the appropriate values.
+#
+# !!!!!!
+
+# Armada 3700 supports both JTAG and SWD transports.
+source [find target/swj-dp.tcl]
+
+if { [info exists CORES] } {
+    set _cores $CORES
+} else {
+    error "CORES not set. Please do not include marvell/88f37x0.cfg directly, but the specific chip configuration file (marvell/88f3710.cfg, marvell/88f3720.cfg, etc.)."
+}
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME [format a37%s0 $_cores]
+}
+
+set _ctis {0x80820000 0x80920000}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+# declare the one JTAG tap to access the DAP
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# declare the main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [lindex $_ctis $_core] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core \
+                         -cti cti$_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+# declare the auxiliary Cortex-M3 core on AP #3
+target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+
+targets ${_TARGETNAME}0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/cn9130.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/cn9130.cfg
new file mode 100644
index 0000000..23e472f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/marvell/cn9130.cfg
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# cn9130 -- support for the Marvell Octeon TX2 / CN9130 CPU family
+#
+# henrik.nordstorm@addiva.se, Nov 2023
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME cn9130
+}
+
+if { [info exists MASTERTAPID] } {
+   set _MASTERTAPID $MASTERTAPID
+} else {
+   set _MASTERTAPID 0x07025357
+}
+
+if { [info exists APTAPID] } {
+   set _APTAPID $APTAPID
+} else {
+   set _APTAPID 0x4ba00477
+}
+
+if { [info exists SBTAPID] } {
+   set _SBTAPID $SBTAPID
+} else {
+   set _SBTAPID 0x4ba00477
+}
+
+if { [info exists CORES] } {
+   set _CORES $CORES
+} else {
+   set _CORES 4
+}
+
+# CTI base address should be possible to read from the CoreSight
+# ROM table like how the DBG base address is when not specified.
+if { [info exists CTIBASE] } {
+   set _CTIBASE $CTIBASE
+} else {
+   set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+}
+
+# CN9130 is a multi-die chip and has a multi level hierarchical
+# JTAG TAP, where all the DAPs are disabled at reset, requiring
+# both configuration to enable access to the chip DAPs, and a
+# vendor specific bypass IR instruction to access the slave TAPs
+# via the master TAP. In addition there is a number of sample
+# bits that should be ignored.
+#
+# The default BYPASS instruction in the master TAP bypasses the
+# whole chip and not only the master TAP. And similarly on
+# IDCODE the master TAP only responds with it's own ID and
+# bypasses the other TAPs on the chip, while OpenOCD expects
+# ID from all enabled TAPs in the chain.
+
+# Bootstrap with the default boundary scan oriented TAP configuration
+# where the master,ap,sb TAPs are seen as one big fat TAP, which matches
+# what OpenOCD expects from IDCODE and BYPASS.
+
+jtag newtap $_CHIPNAME bs  -irlen 19 -enable -expected-id $_MASTERTAPID
+
+# Declare the full JTAG chain, but in disabled state during setup
+
+jtag newtap $_CHIPNAME sample4 -irlen 1 -disable
+jtag newtap $_CHIPNAME sample3 -irlen 1 -disable
+jtag newtap $_CHIPNAME sample2 -irlen 1 -disable
+jtag newtap $_CHIPNAME ap.cpu  -irlen 4 -disable -expected-id $_APTAPID
+jtag newtap $_CHIPNAME ap      -irlen 5 -disable
+jtag newtap $_CHIPNAME sample1 -irlen 1 -disable
+jtag newtap $_CHIPNAME sb.cpu  -irlen 4 -disable -expected-id $_SBTAPID
+jtag newtap $_CHIPNAME sb      -irlen 5 -disable
+jtag newtap $_CHIPNAME master  -irlen 5 -disable -ir-bypass 0x11 -expected-id $_MASTERTAPID
+
+# Once the iniial IDCODE scan has completed switch to more detailed
+# scan chain giving access to the individual chip TAPs.
+
+jtag configure $_CHIPNAME.bs -event setup "cn9130_enable_full_chain $_CHIPNAME"
+
+proc cn9130_enable_full_chain { _CHIPNAME } {
+   # Switch to detailed TAP declaration
+   jtag tapdisable $_CHIPNAME.bs
+   jtag tapenable $_CHIPNAME.master
+   jtag tapenable $_CHIPNAME.sb
+   jtag tapenable $_CHIPNAME.sample1
+   jtag tapenable $_CHIPNAME.ap
+   jtag tapenable $_CHIPNAME.sample2
+   jtag tapenable $_CHIPNAME.sample3
+   jtag tapenable $_CHIPNAME.sample4
+}
+
+# AP & SB TAPs have a config register to enable/disable access to
+# the auxilary DAP TAP. Default off which hides the DAP TAP from
+# the scan chain.
+proc cn9130_dap_config { chip tap state } {
+   irscan $chip.$tap 0x12
+   drscan $chip.$tap 32 $state
+}
+
+jtag configure $_CHIPNAME.bs -event tap-disable ""
+jtag configure $_CHIPNAME.bs -event tap-enable ""
+jtag configure $_CHIPNAME.sample4 -event tap-enable ""
+jtag configure $_CHIPNAME.sample3 -event tap-enable ""
+jtag configure $_CHIPNAME.sample2 -event tap-enable ""
+jtag configure $_CHIPNAME.ap.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME ap 0"
+jtag configure cn9130.ap.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME ap 1"
+jtag configure $_CHIPNAME.ap -event tap-enable ""
+jtag configure $_CHIPNAME.sample1 -event tap-enable ""
+jtag configure $_CHIPNAME.sb.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME sb 0"
+jtag configure cn9130.sb.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME sb 1"
+jtag configure $_CHIPNAME.sb -event tap-enable ""
+jtag configure $_CHIPNAME.master -event tap-enable ""
+
+dap create $_CHIPNAME.ap.dap -chain-position $_CHIPNAME.ap.cpu
+
+# Main bus
+target create $_CHIPNAME.ap.axi mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 0
+
+# Periperials bus
+target create $_CHIPNAME.ap.apb mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 1
+
+# MSS bus
+target create $_CHIPNAME.ap.ahb mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 2
+
+# AP A72 CPU cores
+set _smp_command ""
+for { set _core 0 } { $_core < $_CORES } { incr _core 1 } {
+   cti create $_CHIPNAME.ap.cti.$_core \
+      -dap $_CHIPNAME.ap.dap \
+      -baseaddr [ lindex $_CTIBASE $_core ]  \
+      -ap-num 1
+
+   if { $_core == 0 } {
+      target create $_CHIPNAME.ap.a72.$_core aarch64 \
+         -dap $_CHIPNAME.ap.dap \
+         -ap-num 1 \
+         -cti $_CHIPNAME.ap.cti.$_core \
+         -coreid $_core \
+         -rtos hwthread
+      set _smp_command "target smp $_CHIPNAME.ap.a72.$_core"
+   } else {
+      # Defer non-boot cores. Held hard in reset until
+      # SMP is activated.
+      target create $_CHIPNAME.ap.a72.$_core aarch64 \
+         -dap $_CHIPNAME.ap.dap \
+         -ap-num 1 \
+         -cti $_CHIPNAME.ap.cti.$_core \
+         -coreid $_core \
+         -defer-examine
+      set _smp_command "$_smp_command $_CHIPNAME.ap.a72.$_core"
+   }
+
+}
+
+# Set up the A72 cluster as SMP
+# Note: Only the boot core is active by default. The other core DAPs can
+# be enabled by arp_examine after they have been released from hard reset.
+eval $_smp_command
+
+# AP MSS M3 CPU core. Defer as it is held in reset until firmware is loaded.
+target create $_CHIPNAME.ap.mss cortex_m -dap $_CHIPNAME.ap.dap -ap-num 2 -defer-examine
+
+# Why is this needed? reset fails with "Debug regions are unpowered" otherwise
+$_CHIPNAME.ap.axi configure -event examine-start "dap init"
+
+# Automate enabling the AP A72 DAP once the full scan chain is enabled
+proc cn9130_ap_setup { _CHIPNAME } {
+   jtag tapenable $_CHIPNAME.ap.cpu
+   targets $_CHIPNAME.ap.a72.0
+}
+jtag configure $_CHIPNAME.ap -event setup "cn9130_ap_setup $_CHIPNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/max32620.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/max32620.cfg
new file mode 100644
index 0000000..f3a9f84
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/max32620.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Maxim Integrated MAX32620 OpenOCD target configuration file
+# www.maximintegrated.com
+
+# adapter speed
+adapter speed 4000
+
+# reset pin configuration
+reset_config srst_only
+
+if {[using_jtag]} {
+    jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
+    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
+} else {
+    swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
+}
+
+dap create max32620.dap -chain-position max32620.cpu
+
+# target configuration
+target create max32620.cpu cortex_m -dap max32620.dap
+max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+
+# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
+#   flash bank  max32xxx   0 0     
+#   max32620 flash base address   0x00000000
+#   max32620 flash size           0x200000 (2MB)
+#   max32620 FLC base address     0x40002000
+#   max32620 sector (page) size   0x2000 (8kB)
+#   max32620 clock speed          96 (MHz)
+flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/max32625.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/max32625.cfg
new file mode 100644
index 0000000..90eb392
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/max32625.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Maxim Integrated MAX32625 OpenOCD target configuration file
+# www.maximintegrated.com
+
+# adapter speed
+adapter speed 4000
+
+# reset pin configuration
+reset_config srst_only
+
+if {[using_jtag]} {
+    jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
+    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version
+} else {
+    swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
+}
+
+dap create max32625.dap -chain-position max32625.cpu
+
+# target configuration
+target create max32625.cpu cortex_m -dap max32625.dap
+max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+
+# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
+#   flash bank  max32xxx   0 0     
+#   max32625 flash base address   0x00000000
+#   max32625 flash size           0x80000 (512k)
+#   max32625 FLC base address     0x40002000
+#   max32625 sector (page) size   0x2000 (8kB)
+#   max32625 clock speed          96 (MHz)
+flash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/max3263x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/max3263x.cfg
new file mode 100644
index 0000000..852e04a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/max3263x.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Maxim Integrated MAX3263X OpenOCD target configuration file
+# www.maximintegrated.com
+
+# adapter speed
+adapter speed 4000
+
+# reset pin configuration
+reset_config srst_only
+
+if {[using_jtag]} {
+    jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
+    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version
+} else {
+    swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
+}
+
+dap create max3263x.dap -chain-position max3263x.cpu
+
+# target configuration
+target create max3263x.cpu cortex_m -dap max3263x.dap
+max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+
+# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
+#   flash bank  max32xxx   0 0     
+#   max3263x flash base address   0x00000000
+#   max3263x flash size           0x200000 (2MB)
+#   max3263x FLC base address     0x40002000
+#   max3263x sector (page) size   0x2000 (8kB)
+#   max3263x clock speed          96 (MHz)
+flash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/mc13224v.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/mc13224v.cfg
new file mode 100644
index 0000000..29e4d9d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/mc13224v.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find bitsbytes.tcl]
+source [find cpu/arm/arm7tdmi.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+set CHIP_MAKER             freescale
+set CHIP_FAMILY            mc1322x
+set CHIP_NAME              mc13224
+set N_RAM                  1
+set RAM(0,BASE)            0x00400000
+set RAM(0,LEN)             0x18000
+set RAM(0,HUMAN)           "internal SRAM"
+set RAM(0,TYPE)            "ram"
+set RAM(0,RWX)             $RWX_RWX
+set RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+# I AM LAZY... I create 1 region for all MMRs.
+set N_MMREGS                  1
+set MMREGS(0,CHIPSELECT)      -1
+set MMREGS(0,BASE)            0x80000000
+set MMREGS(0,LEN)             0x00030000
+set MMREGS(0,HUMAN)           "mm-regs"
+set MMREGS(0,TYPE)            "mmr"
+set MMREGS(0,RWX)             $RWX_RW
+set MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY
+
+set N_XMEM 0
+
+set _CHIPNAME mc13224v
+set _CPUTAPID 0x1f1f001d
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+reset_config srst_only
+jtag_ntrst_delay 200
+
+# rclk hasn't been working well. This maybe the mc13224v or something else.
+#adapter speed 2000
+adapter speed 2000
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
+
+# Internal sram memory
+$_TARGETNAME configure -work-area-phys 0x00408000 \
+                       -work-area-size 0x1000     \
+                       -work-area-backup 1
+
+# flash support is pending (should be straightforward to implement)
+#flash bank mc1322x 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/mdr32f9q2i.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/mdr32f9q2i.cfg
new file mode 100644
index 0000000..6e958c6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/mdr32f9q2i.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MDR32F9Q2I (1986ВЕ92У)
+# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME mdr32f9q2i
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      # SWD IDCODE
+      set _CPUTAPID 0x2ba01477
+   }
+}
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# can't handle overlapping memory regions
+if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
+   flash bank ${_CHIPNAME}_info.flash mdr 0x08000000 0x01000 0 0 $_TARGETNAME 1 1 4
+} else {
+   flash bank $_CHIPNAME.flash mdr 0x08000000 0x20000 0 0 $_TARGETNAME 0 32 4
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+   jtag_ntrst_delay 100
+}
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nds32v5.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nds32v5.cfg
new file mode 100644
index 0000000..56b5fed
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nds32v5.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Andes Core
+#
+# http://www.andestech.com
+#
+
+set _CHIPNAME nds
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563D
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp304.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp304.cfg
new file mode 100644
index 0000000..27c30a0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp304.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP304 processor by NetLogic Microsystems
+#
+
+set XLP_NT 4
+source [find target/netl_xlp3xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp308.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp308.cfg
new file mode 100644
index 0000000..c3ba11e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp308.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP308 processor by NetLogic Microsystems
+#
+
+set XLP_NT 8
+source [find target/netl_xlp3xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp316.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp316.cfg
new file mode 100644
index 0000000..961b67f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp316.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP316 processor by NetLogic Microsystems
+#
+
+set XLP_NT 16
+source [find target/netl_xlp3xx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp3xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp3xx.cfg
new file mode 100644
index 0000000..2366503
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/netl_xlp3xx.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP 300-series processors by NetLogic Microsystems
+#
+# See http://www.broadcom.com/products/Processors/Enterprise/XLP300-Series
+#
+# Use xlp304.cfg, xlp308.cfg, xlp316.cfg for particular processor model.
+#
+
+transport select jtag
+
+global XLP_NT
+
+for {set i $XLP_NT} {$i > 0} {incr i -1} {
+	jtag newtap xlp cpu_$i -irlen 5 -disable
+	if {$i != 1} {
+		jtag configure xlp.cpu_$i -event tap-enable {}
+	}
+}
+jtag newtap xlp jrc -irlen 16 -expected-id 0x00011449
+
+jtag configure xlp.cpu_1 -event tap-enable {
+	global XLP_NT
+	irscan xlp.jrc 0xe0
+	drscan xlp.jrc 1 1
+	for {set i $XLP_NT} {$i > 1} {incr i -1} {
+		jtag tapenable xlp.cpu_$i
+	}
+}
+
+proc chipreset {} {
+	irscan xlp.jrc 0xab
+	drscan xlp.jrc 1 1
+	drscan xlp.jrc 1 0
+}
+
+jtag configure xlp.jrc -event setup "jtag tapenable xlp.cpu_1"
+
+target create xlp.cpu_1 mips_mips64 -endian big -chain-position xlp.cpu_1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ngultra.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ngultra.cfg
new file mode 100644
index 0000000..956fdbb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ngultra.cfg
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2022 by NanoXplore, France - all rights reserved
+#
+# configuration file for NG-Ultra SoC from NanoXplore.
+# NG-Ultra is a quad-core Cortex-R52 SoC + an FPGA.
+#
+transport select jtag
+adapter speed 10000
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME NGULTRA
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 4
+}
+
+set DBGBASE {0x88210000 0x88310000 0x88410000 0x88510000}
+set CTIBASE {0x88220000 0x88320000 0x88420000 0x88520000}
+
+# Coresight access to the SoC
+jtag newtap $_CHIPNAME.coresight cpu      -irlen 4 -expected-id 0x6BA00477
+
+# Misc TAP devices
+jtag newtap $_CHIPNAME.soc       cpu      -irlen 7 -expected-id 0xFAAA0555
+jtag newtap $_CHIPNAME.pmb       unknown1 -irlen 5 -expected-id 0xBA20A005
+jtag newtap $_CHIPNAME.fpga      fpga     -irlen 4 -ignore-version -ignore-bypass
+
+# Create the Coresight DAP
+dap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+    cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \
+        -baseaddr [lindex $CTIBASE $_core]
+# Cores are armv8-r but works with aarch64 (since armv8-r not directly supported by openocd yet).
+    if { $_core == 0} {
+        target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \
+            -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core
+    } else {
+        target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \
+            -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine
+    }
+}
+
+# Create direct APB and AXI interfaces
+target create APB mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 0
+target create AXI mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nhs31xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nhs31xx.cfg
new file mode 100644
index 0000000..7e4bc4c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nhs31xx.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP NHS31xx Cortex-M0+ with 8kB SRAM
+
+set CHIPNAME nhs31xx
+source [find target/lpc8nxx.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/npcx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/npcx.cfg
new file mode 100644
index 0000000..84bb0b7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/npcx.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Nuvoton NPCX Cortex-M4 Series
+
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# Set Chipname
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME npcx
+}
+
+# SWD DAP ID of Nuvoton NPCX Cortex-M4.
+if { [info exists CPUDAPID ] } {
+   set _CPUDAPID $CPUDAPID
+} else {
+   set _CPUDAPID 0x4BA00477
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 32kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+if { [info exists FIUNAME]} {
+   set _FIUNAME $FIUNAME
+} else {
+   set _FIUNAME npcx.fiu
+}
+
+# Debug Adapter Target Settings
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# Initial JTAG/SWD speed
+# For safety purposes, set for the lowest cpu clock configuration
+# 4MHz / 6 = 666KHz, so use 600KHz for it
+adapter speed 600
+
+# For safety purposes, set for the lowest cpu clock configuration
+$_TARGETNAME configure -event reset-start {adapter speed 600}
+
+# use sysresetreq to perform a system reset
+cortex_m reset_config sysresetreq
+
+# flash configuration
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME $_FIUNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf51.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf51.cfg
new file mode 100644
index 0000000..3781ecc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf51.cfg
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# script for Nordic nRF51 series, a Cortex-M0 chip
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME nrf51
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if {![using_hla]} {
+   # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
+   cortex_m reset_config sysresetreq
+}
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME
+
+#  The chip should start up from internal 16Mhz RC, so setting adapter
+#  clock to 1Mhz should be OK
+adapter speed 1000
+
+proc enable_all_ram {} {
+	# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
+	# are reliably enabled after reset on some revisions (contrary to spec.) So after
+	# resetting we enable all banks via the RAMON register
+	mww 0x40000524 0xF
+}
+$_TARGETNAME configure -event reset-init {  enable_all_ram }
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf52.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf52.cfg
new file mode 100644
index 0000000..0703b18
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf52.cfg
@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME nrf52
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+adapter speed 1000
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { [using_hla] } {
+	echo ""
+	echo "nRF52 device has a CTRL-AP dedicated to recover the device from AP lock."
+	echo "A high level adapter (like a ST-Link) you are currently using cannot access"
+	echo "the CTRL-AP so 'nrf52_recover' command will not work."
+	echo "Do not enable UICR APPROTECT."
+	echo ""
+} else {
+	cortex_m reset_config sysresetreq
+
+	$_TARGETNAME configure -event examine-fail nrf52_check_ap_lock
+}
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
+
+# Test if MEM-AP is locked by UICR APPROTECT
+proc nrf52_check_ap_lock {} {
+	set dap [[target current] cget -dap]
+	set err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}]
+	if {$err == 0 && $APPROTECTSTATUS != 1} {
+		echo "****** WARNING ******"
+		echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)."
+		echo "Debug access is denied."
+		echo "Use 'nrf52_recover' to erase and unlock the device."
+		echo ""
+		poll off
+	}
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)
+# http://www.ebyte.com produces modules with nRF52 locked by default,
+# use nrf52_recover to enable flashing and debug.
+proc nrf52_recover {} {
+	set target [target current]
+	set dap [$target cget -dap]
+
+	set IDR [$dap apreg 1 0xfc]
+	if {$IDR != 0x02880000} {
+		echo "Error: Cannot access nRF52 CTRL-AP!"
+		return
+	}
+
+	poll off
+
+	# Reset and trigger ERASEALL task
+	$dap apreg 1 4 0
+	$dap apreg 1 4 1
+
+	for {set i 0} {1} {incr i} {
+		set ERASEALLSTATUS [$dap apreg 1 8]
+		if {$ERASEALLSTATUS == 0} {
+			echo "$target device has been successfully erased and unlocked."
+			break
+		}
+		if {$i == 0} {
+			echo "Waiting for chip erase..."
+		}
+		if {$i >= 150} {
+			echo "Error: $target recovery failed."
+			break
+		}
+		sleep 100
+	}
+
+	# Assert reset
+	$dap apreg 1 0 1
+
+	# Deassert reset
+	$dap apreg 1 0 0
+
+	# Reset ERASEALL task
+	$dap apreg 1 4 0
+
+	sleep 100
+	$target arp_examine
+	poll on
+}
+
+add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
+	targets $_targetname
+
+	# Read FICR.INFO.PART
+	set PART [mrw 0x10000100]
+
+	switch $PART {
+		0x52840 -
+		0x52833 -
+		0x52832 {
+			# Configuration values for all supported trace port speeds, see
+			# TRACECONFIG.TRACEPORTSPEED
+			set trace_port_speeds {
+				32000000 0
+				16000000 1
+				8000000  2
+				4000000  3
+			}
+
+			# Note that trace port clock stands for what is referred to as
+			# TRACECLKIN in the Arm CoreSight documentation.
+			set trace_port_clock [$_chipname.tpiu cget -traceclk]
+
+			if { ![dict exists $trace_port_speeds $trace_port_clock] } {
+				error "Trace clock speed is not supported"
+			}
+
+			# Set TRACECONFIG.TRACEPORTSPEED
+			mmw 0x4000055C [dict get $trace_port_speeds $trace_port_clock] 0x3
+
+			if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+				if { [$_chipname.tpiu cget -port-width] != 4 } {
+					error "Device only supports 4-bit sync traces"
+				}
+
+				# Set TRACECONFIG.TRACEMUX to enable synchronous trace
+				mmw 0x4000055C 0x00020000 0x00010000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00020000 0x00010000
+				}
+			} else {
+				# Set TRACECONFIG.TRACEMUX to enable SWO
+				mmw 0x4000055C 0x00010000 0x00020000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00010000 0x00020000
+				}
+			}
+		}
+		0x52820 -
+		0x52811 -
+		0x52810 -
+		0x52805 {
+			error "Device does not support TPIU"
+		}
+		default {
+			error "Unknown device, cannot configure TPIU"
+		}
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME $_CHIPNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf53.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf53.cfg
new file mode 100644
index 0000000..307df90
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf53.cfg
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF53 series: dual ARM Cortex-M33, multidrop SWD
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME nrf53
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x6ba02477
+}
+
+# Configurable instance ID resides in application UICR TINSTANCE
+if { [info exists SWD_INSTANCE_ID] } {
+	set _SWD_INSTANCE_ID $SWD_INSTANCE_ID
+} else {
+	set _SWD_INSTANCE_ID 0
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+if { [info exists SWD_MULTIDROP] } {
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0070289 -instance-id $_SWD_INSTANCE_ID
+} else {
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+}
+
+set _TARGETNAME_APP $_CHIPNAME.cpuapp
+target create $_TARGETNAME_APP cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME_APP configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# The network core is not accessible over HLA
+if { ![using_hla] } {
+	set _TARGETNAME_NET $_CHIPNAME.cpunet
+	target create $_TARGETNAME_NET cortex_m -dap $_CHIPNAME.dap -ap-num 1 -defer-examine
+
+	targets $_TARGETNAME_APP
+
+	$_TARGETNAME_NET configure -work-area-phys 0x21000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+}
+
+# Keep adapter speed less or equal 2000 kHz or flash programming fails!
+adapter speed 1000
+
+source [find target/nrf_common.cfg]
+
+flash bank $_CHIPNAME.app.flash nrf5 0x00000000 0 0 0 $_TARGETNAME_APP
+flash bank $_CHIPNAME.app.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME_APP
+
+if { ![using_hla] } {
+
+	flash bank $_CHIPNAME.net.flash nrf5 0x01000000 0 0 0 $_TARGETNAME_NET
+	flash bank $_CHIPNAME.net.uicr nrf5 0x01FF8000 0 0 0 $_TARGETNAME_NET
+
+	# System reset sets NETWORK.FORCEOFF which keeps the network core in reset
+	# Don't touch network core during reset
+	$_TARGETNAME_NET configure -event reset-assert {}
+	# and start it after application core reset is finished to make all flash accessible
+	$_TARGETNAME_APP configure -event reset-init "nrf53_cpunet_release $_CHIPNAME"
+
+	$_TARGETNAME_APP cortex_m reset_config sysresetreq
+	$_TARGETNAME_NET cortex_m reset_config sysresetreq
+
+	$_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 3 }
+	$_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 3 }
+
+	$_TARGETNAME_NET configure -event gdb-attach "_nrf53_cpunet_gdb_attach $_CHIPNAME"
+
+	proc _nrf53_cpunet_gdb_attach { _CHIPNAME } {
+		set _TARGETNAME_APP $_CHIPNAME.cpuapp
+		set _TARGETNAME_NET $_CHIPNAME.cpunet
+		set RESET_NETWORK_FORCEOFF 0x50005614
+
+		set is_off [$_TARGETNAME_APP read_memory $RESET_NETWORK_FORCEOFF 32 1]
+		if { $is_off } {
+			nrf53_cpunet_release $_CHIPNAME
+			$_TARGETNAME_NET arp_poll
+			$_TARGETNAME_NET arp_waitstate halted 100
+		} else {
+			if { ![$_TARGETNAME_NET was_examined] } {
+				$_TARGETNAME_NET arp_examine
+				$_TARGETNAME_NET arp_poll
+			}
+			set s [$_TARGETNAME_NET curstate]
+			if { ![string compare $s "halted"] } {
+				halt
+			}
+		}
+	}
+	lappend _telnet_autocomplete_skip _nrf53_cpunet_gdb_attach
+
+	# Release the network core
+	proc nrf53_cpunet_release { {_CHIPNAME nrf53} } {
+		set _TARGETNAME_APP $_CHIPNAME.cpuapp
+		set _TARGETNAME_NET $_CHIPNAME.cpunet
+		set RESET_NETWORK_FORCEOFF 0x50005614
+		set RESET_NETWORK_WORKAROUND 0x50005618
+		set CORTEX_M_DCB_DEMCR 0xE000EDFC
+
+		$_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 1
+		$_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
+		$_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 1
+		set err [catch {$_TARGETNAME_NET arp_examine}]
+		if { $err } {
+			if { ![_nrf_check_ap_lock 3 3] } {
+				echo "Error: \[$_TARGETNAME_NET\] examination failed"
+			}
+			return
+		}
+		# set TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET
+		$_TARGETNAME_NET mww $CORTEX_M_DCB_DEMCR 0x01000501
+		# Write DEMCR directly intead of permanetly setting by cortex_m vector_catch reset
+		# following cortex_m_endreset_event() restores the original DEMCR value
+		$_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
+		$_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 0
+	}
+
+	# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2 or #3)
+	proc nrf53_cpuapp_recover {} {
+		_nrf_ctrl_ap_recover 2
+	}
+	add_help_text nrf53_cpuapp_recover "Mass erase flash and unlock nRF53 application CPU"
+
+	proc nrf53_recover {} {
+		_nrf_ctrl_ap_recover 3 1
+	}
+	add_help_text nrf53_recover "Mass erase all device flash and unlock nRF53"
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf91.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf91.cfg
new file mode 100644
index 0000000..e0ff4e5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf91.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF91 series: ARM Cortex-M33, SWD only
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME nrf91
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x6ba02477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+# Contrary to the product specification at least nRF9161 supports multidrop SWD.
+# The instance ID is fixed, no more than one nRF91 can be connected to one SWD bus.
+if { [info exists SWD_MULTIDROP] } {
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0090289 -instance-id 0
+} else {
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# Keep adapter speed less or equal 2000 kHz or flash programming fails!
+adapter speed 1000
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+source [find target/nrf_common.cfg]
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME
+
+if { ![using_hla] } {
+	$_TARGETNAME cortex_m reset_config sysresetreq
+
+	$_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 3 }
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #4)
+proc nrf91_recover {} {
+	_nrf_ctrl_ap_recover 4
+}
+add_help_text nrf91_recover "Mass erase and unlock nRF91 device"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf_common.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf_common.cfg
new file mode 100644
index 0000000..2ae5011
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nrf_common.cfg
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF52, nRF53 and nRF91 CTRL-AP handling
+#
+
+if { [using_hla] } {
+	echo ""
+	echo "nRF device has a CTRL-AP dedicated to recover the device from AP lock."
+	echo "A high level adapter (like a ST-Link) you are currently using cannot access"
+	echo "the CTRL-AP so 'nrfxx_recover' command will not work."
+	echo "Do not enable UICR APPROTECT."
+	echo ""
+} else {
+
+	# Test if debug/MEM-AP is locked by UICR APPROTECT
+	proc _nrf_check_ap_lock { ctrl_ap_num unlocked_value } {
+		set target [target current]
+		set dap [$target cget -dap]
+		set err [catch {set APPROTECTSTATUS [$dap apreg $ctrl_ap_num 0xc]}]
+		if {$err == 0 && $APPROTECTSTATUS < $unlocked_value} {
+			echo ""
+			echo "****** WARNING ******"
+			echo "\[$target\] device has AP lock engaged (see UICR APPROTECT register)."
+			echo "Debug access is denied."
+			echo "Use 'nrfxx_recover' to erase and unlock the device."
+			echo ""
+			poll off
+			return 1
+		}
+		return 0
+	}
+
+	# Mass erase and unlock the device using proprietary nRF CTRL-AP
+	proc _nrf_ctrl_ap_recover { ctrl_ap_num {is_cpunet 0} } {
+		set target [target current]
+		set dap [$target cget -dap]
+
+		set IDR [$dap apreg $ctrl_ap_num 0xfc]
+		if {$IDR != 0x12880000} {
+			echo "Error: Cannot access nRF CTRL-AP!"
+			return
+		}
+
+		poll off
+
+		# Reset and trigger ERASEALL task
+		$dap apreg $ctrl_ap_num 4 0
+		$dap apreg $ctrl_ap_num 4 1
+
+		for {set i 0} {1} {incr i} {
+			set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 8]
+			if {$ERASEALLSTATUS == 0} {
+				echo "\[$target\] device has been successfully erased and unlocked."
+				break
+			}
+			if {$i == 0} {
+				echo "Waiting for chip erase..."
+			}
+			if {$i >= 150} {
+				echo "Error: \[$target\] recovery failed."
+				break
+			}
+			sleep 100
+		}
+
+		# Assert reset
+		$dap apreg $ctrl_ap_num 0 1
+
+		# Deassert reset
+		$dap apreg $ctrl_ap_num 0 0
+
+		# Reset ERASEALL task
+		$dap apreg $ctrl_ap_num 4 0
+
+		if { $is_cpunet } {
+			reset init
+		} else {
+			sleep 100
+			$target arp_examine
+			poll on
+		}
+	}
+
+	lappend _telnet_autocomplete_skip _nrf_check_ap_lock _nrf_ctrl_ap_recover
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nuc910.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nuc910.cfg
new file mode 100644
index 0000000..31a3ac6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/nuc910.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nuvoton nuc910 (previously W90P910) based soc
+#
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME nuc910
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # set useful default
+   set _CPUTAPID 0x07926f0f
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/numicro.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/numicro.cfg
new file mode 100644
index 0000000..29077f3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/numicro.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Nuvoton MuMicro Cortex-M0 Series
+
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# Set Chipname
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME NuMicro
+}
+
+# SWD DP-ID Nuvoton NuMicro Cortex-M0 has SWD Transport only.
+if { [info exists CPUDAPID] } {
+	set _CPUDAPID $CPUDAPID
+} else {
+	set _CPUDAPID 0x0BB11477
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+
+# Debug Adapter Target Settings
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash bank  numicro   0 0 
+#set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash_aprom
+flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_data
+flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_ldrom
+flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_config
+flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
+
+# set default SWCLK frequency
+adapter speed 1000
+
+# set default srst setting "none"
+reset_config none
+
+# HLA doesn't have cortex_m commands
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/numicro_m4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/numicro_m4.cfg
new file mode 100644
index 0000000..1302515
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/numicro_m4.cfg
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Nuvoton MuMicro Cortex-M4 Series
+
+source [find target/swj-dp.tcl]
+
+# Set Chipname
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME NuMicro
+}
+
+# SWD DP-ID Nuvoton NuMicro Cortex-M4 has SWD Transport only.
+if { [info exists CPUDAPID] } {
+	set _CPUDAPID $CPUDAPID
+} else {
+	set _CPUDAPID 0x2BA01477
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+
+# Debug Adapter Target Settings
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash bank  numicro   0 0 
+#set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash_aprom
+flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_data
+flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_ldrom
+flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash_config
+flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
+
+# set default SWCLK frequency
+adapter speed 1000
+
+# set default srst setting "none"
+reset_config none
+
+# HLA doesn't have cortex_m commands
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap2420.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap2420.cfg
new file mode 100644
index 0000000..3e31baf
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap2420.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Texas Instruments OMAP 2420
+#	http://www.ti.com/omap
+# as seen in Nokia N8x0 tablets
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omap2420
+}
+
+# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
+reset_config srst_nogate
+
+# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
+jtag newtap $_CHIPNAME iva -irlen 4 -disable
+
+# Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
+jtag newtap $_CHIPNAME dsp -irlen 38 -disable
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
+
+# Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07b3602f
+}
+jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
+
+# Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x01ce4801
+}
+jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
+
+# GDB target: the ARM.
+set _TARGETNAME $_CHIPNAME.arm
+target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
+
+# scratch: framebuffer, may be initially unavailable in some chips
+$_TARGETNAME configure -work-area-phys 0x40210000
+$_TARGETNAME configure -work-area-size 0x00081000
+$_TARGETNAME configure -work-area-backup 0
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
+
+# RM_RSTCTRL_WKUP.RST.GS - Trigger a global software reset, and
+# give it a chance to finish before we talk to the chip again.
+set RM_RSTCTRL_WKUP 0x48008450
+$_TARGETNAME configure -event reset-assert \
+	"halt; $_TARGETNAME mww $RM_RSTCTRL_WKUP 2; sleep 200"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap3530.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap3530.cfg
new file mode 100644
index 0000000..bd8b111
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap3530.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TI OMAP3530
+# http://focus.ti.com/docs/prod/folders/print/omap3530.html
+# Other OMAP3 chips remove DSP and/or the OpenGL support
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omap3530
+}
+
+# ICEpick-C ... used to route Cortex, DSP, and more not shown here
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
+jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
+
+# Subsidiary TAP: CoreSight Debug Access Port (DAP)
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x0b6d602f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 3"
+
+# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b7ae02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID
+
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+# SRAM: 64K at 0x4020.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
+
+###################
+
+# the reset sequence is event-driven
+# and kind of finicky...
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+
+proc omap3_dbginit {target} {
+     # General Cortex-A8 debug initialisation
+     cortex_a dbginit
+     # Enable DBGU signal for OMAP353x
+     $target mww phys 0x5401d030 0x00002000
+}
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
+# OK to speed up *after* PLL and clock tree setup.
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
+# would issue.  RST_DPLL3 (4) is a cold reset.
+set PRM_RSTCTRL 0x48307250
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
+
+$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap4430.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap4430.cfg
new file mode 100644
index 0000000..4bc7fe1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap4430.cfg
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OMAP4430
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME omap4430
+}
+
+
+# Although the OMAP4430 supposedly has an ICEpick-D, only the
+# ICEpick-C router commands seem to work.
+# See http://processors.wiki.ti.com/index.php/ICEPICK
+source [find target/icepick.cfg]
+
+
+#
+# A9 DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x3BA00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 9"
+
+
+#
+# M3 DAPs, one per core
+#
+if { [info exists M3_DAP_TAPID] } {
+	set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+	set _M3_DAP_TAPID 0x4BA00477
+}
+
+jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m31 -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 5"
+
+jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m30 -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 4"
+
+
+#
+# ICEpick-D JRC (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID  0x3b95c02f
+	set _JRC_TAPID2 0x1b85202f
+}
+
+# PandaBoard REV EA1 (PEAP platforms)
+if { [info exists JRC_TAPID2] } {
+	set _JRC_TAPID2 $JRC_TAPID2
+} else {
+	set _JRC_TAPID2 0x1b85202f
+}
+
+
+
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
+
+# Required by ICEpick to power-up the debug domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
+
+
+#
+# GDB target: Cortex-A9, using DAP
+#
+# The debugger can connect to either core of the A9, but currently
+# not both simultaneously.  Change -coreid to 1 to connect to the
+# second core.
+#
+set _TARGETNAME $_CHIPNAME.cpu
+
+# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
+# 0x80000000 is cpu0 coresight region
+#
+#
+# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
+# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
+
+set _coreid 0
+set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
+echo "Using dbgbase = [format 0x%x $_dbgbase]"
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
+  -coreid 0 -dbgbase $_dbgbase
+
+# SRAM: 56KiB at 0x4030.0000
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
+
+
+#
+# M3 targets, separate TAP/DAP for each core
+#
+dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
+dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
+target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
+
+
+# Once the JRC is up, enable our TAPs
+jtag configure $_CHIPNAME.jrc -event setup "
+	jtag tapenable $_CHIPNAME.cpu
+	jtag tapenable $_CHIPNAME.m30
+	jtag tapenable $_CHIPNAME.m31
+"
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  1 is a warm reset, 2 a cold reset.
+set PRM_RSTCTRL 0x4A307B00
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
+$_CHIPNAME.m30 configure -event reset-assert { }
+$_CHIPNAME.m31 configure -event reset-assert { }
+
+# Soft breakpoints don't currently work due to broken cache handling
+gdb breakpoint_override hard
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap4460.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap4460.cfg
new file mode 100644
index 0000000..85ba96c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap4460.cfg
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OMAP4460
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME omap4460
+}
+
+
+# Although the OMAP4430 supposedly has an ICEpick-D, only the
+# ICEpick-C router commands seem to work.
+# See http://processors.wiki.ti.com/index.php/ICEPICK
+source [find target/icepick.cfg]
+
+
+#
+# A9 DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x3BA00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 9"
+
+
+#
+# M3 DAPs, one per core
+#
+if { [info exists M3_DAP_TAPID] } {
+	set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+	set _M3_DAP_TAPID 0x4BA00477
+}
+
+jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m31 -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 5"
+
+jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m30 -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 4"
+
+
+#
+# ICEpick-D JRC (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID  0x2b94e02f
+	set _JRC_TAPID2 0x1b85202f
+}
+
+# PandaBoard REV EA1 (PEAP platforms)
+if { [info exists JRC_TAPID2] } {
+	set _JRC_TAPID2 $JRC_TAPID2
+} else {
+	set _JRC_TAPID2 0x1b85202f
+}
+
+
+
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
+
+# Required by ICEpick to power-up the debug domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
+
+
+#
+# GDB target: Cortex-A9, using DAP
+#
+# The debugger can connect to either core of the A9, but currently
+# not both simultaneously.  Change -coreid to 1 to connect to the
+# second core.
+#
+set _TARGETNAME $_CHIPNAME.cpu
+
+# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
+# 0x80000000 is cpu0 coresight region
+#
+#
+# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
+# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
+
+set _coreid 0
+set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
+echo "Using dbgbase = [format 0x%x $_dbgbase]"
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
+  -coreid 0 -dbgbase $_dbgbase
+
+# SRAM: 56KiB at 0x4030.0000
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
+
+
+#
+# M3 targets, separate TAP/DAP for each core
+#
+dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
+dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
+target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
+
+
+# Once the JRC is up, enable our TAPs
+jtag configure $_CHIPNAME.jrc -event setup "
+	jtag tapenable $_CHIPNAME.cpu
+	jtag tapenable $_CHIPNAME.m30
+	jtag tapenable $_CHIPNAME.m31
+"
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  1 is a warm reset, 2 a cold reset.
+set PRM_RSTCTRL 0x4A307B00
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
+$_CHIPNAME.m30 configure -event reset-assert { }
+$_CHIPNAME.m31 configure -event reset-assert { }
+
+# Soft breakpoints don't currently work due to broken cache handling
+gdb breakpoint_override hard
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap5912.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap5912.cfg
new file mode 100644
index 0000000..783f460
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omap5912.cfg
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TI OMAP5912 dual core processor
+# http://focus.ti.com/docs/prod/folders/print/omap5912.html
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omap5912
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # NOTE: validated with XOMAP5912 part
+   set _CPUTAPID 0x0692602f
+}
+
+adapter srst delay 100
+
+# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
+# its standalone siblings (like TMS320VC5502) of the same era
+
+#jtag scan chain
+jtag newtap $_CHIPNAME dsp -irlen 38 -expected-id 0x03df1d81
+jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME unknown -irlen 8
+
+set _TARGETNAME $_CHIPNAME.arm
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+
+proc omap5912_reset {} {
+	#
+	# halt target
+	#
+	poll
+	sleep 1
+	halt
+	wait_halt
+	#
+	# disable wdt
+	#
+	mww 0xfffec808 0x000000f5
+	mww 0xfffec808 0x000000a0
+
+	mww 0xfffeb048 0x0000aaaa
+	sleep 500
+	mww 0xfffeb048 0x00005555
+	sleep 500
+}
+
+# omap5912 lcd frame buffer as working area
+$_TARGETNAME configure -work-area-phys 0x20000000 \
+	-work-area-size 0x3e800 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omapl138.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omapl138.cfg
new file mode 100644
index 0000000..78c456d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/omapl138.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments DaVinci family: OMAPL138
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omapl138
+}
+
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID -disable
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 3"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07926001
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID -disable
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 2"
+
+# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b7d102f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
+# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
+# and the ETB memory (4K) are other options, while trace is unused.
+# Little-endian; use the OpenOCD default.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
+
+gdb breakpoint_override hard
+arm7_9 dbgrq enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/or1k.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/or1k.cfg
new file mode 100644
index 0000000..ddd4fa2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/or1k.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set  _ENDIAN big
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME or1k
+}
+
+if { [info exists TAP_TYPE] } {
+   set _TAP_TYPE $TAP_TYPE
+} else {
+   puts "You need to select a tap type"
+   shutdown
+}
+
+# Configure the target
+if { [string compare $_TAP_TYPE "VJTAG"] == 0 } {
+	if { [info exists FPGATAPID] } {
+	   set _FPGATAPID $FPGATAPID
+	} else {
+	   puts "You need to set your FPGA JTAG ID"
+		shutdown
+	}
+
+	jtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID
+
+	set _TARGETNAME $_CHIPNAME.cpu
+	target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
+
+	# Select the TAP core we are using
+	tap_select vjtag
+
+} elseif { [string compare $_TAP_TYPE "XILINX_BSCAN"] == 0 } {
+
+	if { [info exists FPGATAPID] } {
+	   set _FPGATAPID $FPGATAPID
+	} else {
+	   puts "You need to set your FPGA JTAG ID"
+		shutdown
+	}
+
+	jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_FPGATAPID
+
+	set _TARGETNAME $_CHIPNAME.cpu
+	target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
+
+	# Select the TAP core we are using
+	tap_select xilinx_bscan
+} else {
+	# OpenCores Mohor JTAG TAP ID
+	set _CPUTAPID  0x14951185
+
+	jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+	set _TARGETNAME $_CHIPNAME.cpu
+	target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
+
+	# Select the TAP core we are using
+	tap_select mohor
+}
+
+# Select the debug unit core we are using. This debug unit as an option.
+
+set ADBG_USE_HISPEED		1
+set ENABLE_JSP_SERVER		2
+set ENABLE_JSP_MULTI		4
+
+# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
+# on burst reads and writes to improve download speeds.
+# This option must match the RTL configured option.
+
+du_select adv [expr {$ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI}]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pec930.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pec930.cfg
new file mode 100644
index 0000000..312a212
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pec930.cfg
@@ -0,0 +1,131 @@
+
+adapter speed 5000
+reset_config srst_only
+adapter srst pulse_width 100
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+proc _get_loader {patt} {
+    set _orig_pwd [pwd]
+    set _patt_loader $patt
+    set _loader_bin 0
+    set _level 0
+
+    while {1} {
+        if {[file exists $_patt_loader]} {
+            set _loader_bin [pwd]
+            append _loader_bin "/" $patt
+            break
+        }
+
+        cd ..
+        incr _level 1
+        if {$_level > 20} {
+            set _loader_bin ""
+            break
+        }
+    }
+    cd $_orig_pwd
+    return $_loader_bin
+}
+
+set _2WIRE_ICE 1
+if { $_2WIRE_ICE == 0 } {
+    # jTag 4-wire
+    echo "=> Use 4-wires jTag..."
+    ftdi nscan1_mode off
+} else {
+    # cJtag 2-wire
+    echo "=> Use 2-wires cJTag..."
+    ftdi nscan1_mode on
+}
+
+#/*
+# * bindto 0.0.0.0 can be used to cover all available interfaces.
+# * Uncomment bindto line to enable remote machine debug
+# */
+# bindto 0.0.0.0
+
+#/*
+# * If ftdi device_desc not specified, the device description is ignored during device selection.
+# * So if you want to specify a dedicated FTDI device, you can select following device description:
+# * "Dual RS232-HS" is for Nuclei HummingBird Debugger V1
+# * "USB <-> JTAG-DEBUGGER" is for Nuclei HummingBird Debugger V2
+# * Uncomment one which match your device description
+# */
+# ftdi device_desc "Dual RS232-HS"
+# ftdi device_desc "USB <-> JTAG-DEBUGGER"
+#/* you can also specify adapter serial to select a ftdi chip */
+# adapter serial "FT6S9RD6"
+
+# Bind JTAG with specified serial number passed by JTAGSN
+if { [ info exists JTAGSN ] } {
+    puts "Bind JTAG with serial number $JTAGSN"
+    adapter serial $JTAGSN
+}
+
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
+#/* These signals are used for cJTAG escape sequence on initialization only */
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
+transport select jtag
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+#/* Work-area is a space in RAM used for flash programming */
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREA_SIZE $WORKAREASIZE
+} else {
+   set _WORKAREA_SIZE 0x600
+}
+
+set _WORKAREA_BASE 0x20000A00
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys $_WORKAREA_BASE -work-area-size $_WORKAREA_SIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+
+
+
+#/*
+# * Use external flash-loader 'loader.bin'
+# */
+
+set _BURN_DEV_BASE      0x0
+set _BURN_DEV_SIZE      0x8000
+
+# eflash
+echo "=> Burn Data to eFlash ..."
+set _LOADER_BIN [_get_loader ./flashloader/loader.bin]
+flash bank $_FLASHNAME custom $_BURN_DEV_BASE $_BURN_DEV_SIZE 0 0 $_TARGETNAME 0x4000F800 $_LOADER_BIN sectorsize=512
+
+
+
+#/*
+# * Expose Nuclei self-defined CSRS range
+# * See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
+# * Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
+# * no need to expose since Nuclei OpenOCD 2022
+# */
+#riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
+
+#/* expose N100 customized csr 0xbd0 -> 0xbdc, mainly irqc and timer csrs */
+# riscv expose_csrs 3024-3036
+
+riscv set_reset_timeout_sec 1
+
+init
+
+halt
+
+flash protect 0 0 last off
+
+arm semihosting enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pic32mx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pic32mx.cfg
new file mode 100644
index 0000000..df68e80
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pic32mx.cfg
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME pic32mx
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x30938053
+}
+
+# default working area is 16384
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#
+# At reset the pic32mx does not allow code execution from RAM
+# we have to setup the BMX registers to allow this.
+# One limitation is that we loose the first 2k of RAM.
+#
+
+global _PIC32MX_DATASIZE
+global _WORKAREASIZE
+set _PIC32MX_DATASIZE 0x800
+set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}]
+
+$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
+$_TARGETNAME configure -event reset-init {
+	#
+	# from reset the pic32 cannot execute code in ram - enable ram execution
+	# minimum offset from start of ram is 2k
+	#
+	global _PIC32MX_DATASIZE
+	global _WORKAREASIZE
+
+	# BMXCON	set 0 wait state option by clearing BMXWSDRM bit, bit 6
+	mww 0xbf882000 0x001f0000
+	# BMXDKPBA: 2k kernel data @ 0xa0000000
+	mww 0xbf882010 $_PIC32MX_DATASIZE
+	# BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
+	mww 0xbf882020 $_WORKAREASIZE
+	# BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
+	mww 0xbf882030 $_WORKAREASIZE
+
+	#
+	# Set system clock to 8Mhz if the default clock configuration is set
+	#
+
+	# SYSKEY register, make sure OSCCON is locked
+	mww 0xbf80f230 0x0
+	# SYSKEY register, write unlock sequence
+	mww 0xbf80f230 0xaa996655
+	mww 0xbf80f230 0x556699aa
+	# OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
+	mww 0xbf80f004 0x07000000
+	# SYSKEY register, relock OSCCON
+	mww 0xbf80f230 0x0
+}
+
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/psoc4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/psoc4.cfg
new file mode 100644
index 0000000..baa2c83
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/psoc4.cfg
@@ -0,0 +1,218 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Cypress PSoC 4 devices
+
+#
+# PSoC 4 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME psoc4
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
+
+adapter speed 1500
+
+# Reset, bloody PSoC 4 reset
+#
+# 1) XRES (nSRST) resets also SWD DP so SWD line reset and DP reinit is needed.
+# High level adapter stops working after SRST and needs OpenOCD restart.
+# If your hw does not use SRST for other circuits, use sysresetreq instead
+#
+# 2) PSoC 4 executes initialization code from system ROM after reset.
+# This code subsequently jumps to user flash reset vector address.
+# Unfortunately the system ROM code is protected from reading and debugging.
+# Protection breaks vector catch VC_CORERESET used for "reset halt" by cortex_m.
+#
+# Cypress uses TEST_MODE flag to loop CPU in system ROM before executing code
+# from user flash. Programming specifications states that TEST_MODE flag must be
+# set in time frame 400 usec delayed about 1 msec from reset.
+#
+# OpenOCD have no standard way how to set TEST_MODE in specified time frame.
+# As a workaround the TEST_MODE flag is set before reset instead.
+# It worked for the oldest family PSoC4100/4200 even though it is not guaranteed
+# by specification.
+#
+# Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE
+# clear TEST_MODE flag during device reset so workaround is not possible.
+# Use a KitProg adapter for these devices or "reset halt" will not stop
+# before executing user code.
+#
+# 3) SWD cannot be connected during system initialization after reset.
+# This might be a reason for unconnecting ST-Link v2 when deasserting reset.
+# As a workaround arp_reset deassert is not called for hla
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc psoc4_get_family_id {} {
+	set err [catch {set romtable_pid [read_memory 0xF0000FE0 32 3]}]
+	if { $err } {
+		return 0
+	}
+	if { [expr {[lindex $romtable_pid 0] & 0xffffff00 }]
+	  || [expr {[lindex $romtable_pid 1] & 0xffffff00 }]
+	  || [expr {[lindex $romtable_pid 2] & 0xffffff00 }] } {
+		echo "Unexpected data in ROMTABLE"
+		return 0
+	}
+	set designer_id [expr {(( [lindex $romtable_pid 1] & 0xf0 ) >> 4) | (( [lindex $romtable_pid 2] & 0xf ) << 4 ) }]
+	if { $designer_id != 0xb4 } {
+		echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id]
+		return 0
+	}
+	set family_id [expr {( [lindex $romtable_pid 0] & 0xff ) | (( [lindex $romtable_pid 1] & 0xf ) << 8 ) }]
+	return $family_id
+}
+
+proc ocd_process_reset_inner { MODE } {
+	global PSOC4_USE_ACQUIRE PSOC4_TEST_MODE_WORKAROUND
+	global _TARGETNAME
+
+	if { 0 != [string compare $_TARGETNAME [target names]] } {
+		return -code error "PSoC 4 reset can handle only one $_TARGETNAME target";
+	}
+	set t $_TARGETNAME
+
+	# If this target must be halted...
+	set halt -1
+	if { 0 == [string compare $MODE halt] } {
+		set halt 1
+	}
+	if { 0 == [string compare $MODE init] } {
+		set halt 1;
+	}
+	if { 0 == [string compare $MODE run ] } {
+		set halt 0;
+	}
+	if { $halt < 0 } {
+		return -code error "Invalid mode: $MODE, must be one of: halt, init, or run";
+	}
+
+	if { ! [info exists PSOC4_USE_ACQUIRE] } {
+		if { 0 == [string compare [adapter name] kitprog ] } {
+			set PSOC4_USE_ACQUIRE 1
+		} else {
+			set PSOC4_USE_ACQUIRE 0
+		}
+	}
+	if { $PSOC4_USE_ACQUIRE } {
+		set PSOC4_TEST_MODE_WORKAROUND 0
+	} elseif { ! [info exists PSOC4_TEST_MODE_WORKAROUND] } {
+		if { [psoc4_get_family_id] == 0x93 } {
+			set PSOC4_TEST_MODE_WORKAROUND 1
+		} else {
+			set PSOC4_TEST_MODE_WORKAROUND 0
+		}
+	}
+
+	#$t invoke-event reset-start
+	$t invoke-event reset-assert-pre
+
+	if { $halt && $PSOC4_USE_ACQUIRE } {
+		catch { [adapter name] acquire_psoc }
+		$t arp_examine
+	} else {
+		if { $PSOC4_TEST_MODE_WORKAROUND } {
+			set TEST_MODE 0x40030014
+			if { $halt == 1 } {
+				catch { mww $TEST_MODE 0x80000000 }
+			} else {
+				catch { mww $TEST_MODE 0 }
+			}
+		}
+
+		$t arp_reset assert 0
+	}
+
+	$t invoke-event reset-assert-post
+	$t invoke-event reset-deassert-pre
+	if {![using_hla]} {	# workaround ST-Link v2 fails and forcing reconnect
+		$t arp_reset deassert 0
+	}
+	$t invoke-event reset-deassert-post
+
+	# Pass 1 - Now wait for any halt (requested as part of reset
+	# assert/deassert) to happen.  Ideally it takes effect without
+	# first executing any instructions.
+	if { $halt } {
+		# Now PSoC CPU should loop in system ROM
+		$t arp_waitstate running 200
+		$t arp_halt
+
+		# Catch, but ignore any errors.
+		catch { $t arp_waitstate halted 1000 }
+
+		# Did we succeed?
+		set s [$t curstate]
+
+		if { 0 != [string compare $s "halted" ] } {
+			return -code error [format "TARGET: %s - Not halted" $t]
+		}
+
+		# Check if PSoC CPU is stopped in system ROM
+		set pc [reg pc]
+		regsub {pc[^:]*: } $pc "" pc
+		if { $pc < 0x10000000 || $pc > 0x1000ffff } {
+			set hint ""
+			set family_id [psoc4_get_family_id]
+			if { $family_id == 0x93 } {
+				set hint ", use 'reset_config none'"
+			} elseif { $family_id > 0x93 } {
+				set hint ", use a KitProg adapter"
+			}
+			return -code error [format "TARGET: %s - Not halted in system ROM%s" $t $hint]
+		}
+
+		# Set registers to reset vector values
+		set value [read_memory 0x0 32 2]
+		reg pc [expr {[lindex $value 1] & 0xfffffffe}]
+		reg msp [lindex $value 0]
+
+		if { $PSOC4_TEST_MODE_WORKAROUND } {
+			catch { mww $TEST_MODE 0 }
+		}
+	}
+
+	#Pass 2 - if needed "init"
+	if { 0 == [string compare init $MODE] } {
+		set err [catch "$t arp_waitstate halted 5000"]
+
+		# Did it halt?
+		if { $err == 0 } {
+			$t invoke-event reset-init
+		}
+	}
+
+	$t invoke-event reset-end
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/psoc5lp.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/psoc5lp.cfg
new file mode 100644
index 0000000..fe44174
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/psoc5lp.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Cypress PSoC 5LP
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME psoc5lp
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPU_TAPID $CPUTAPID
+} else {
+	set _CPU_TAPID 0x4BA00477
+}
+
+if { [using_jtag] } {
+	set _CPU_DAP_ID $_CPU_TAPID
+} else {
+	set _CPU_DAP_ID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x2000
+}
+
+$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+source [find mem_helper.tcl]
+
+$_TARGETNAME configure -event reset-init {
+	# Configure Target Device (PSoC 5LP Device Programming Specification 5.2)
+
+	set PANTHER_DBG_CFG 0x4008000C
+	set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}]
+	mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0
+
+	set PM_ACT_CFG0 0x400043A0
+	mww $PM_ACT_CFG0 0xBF
+
+	set FASTCLK_IMO_CR 0x40004200
+	set FASTCLK_IMO_CR_F_RANGE_2    [expr {2 << 0}]
+	set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}]
+	mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+	cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/psoc6.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/psoc6.cfg
new file mode 100644
index 0000000..52b04f5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/psoc6.cfg
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
+# PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+source [find target/swj-dp.tcl]
+
+adapter speed 1000
+
+global _CHIPNAME
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME psoc6
+}
+
+global TARGET
+set TARGET $_CHIPNAME.cpu
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Is CM0 Debugging enabled ?
+global _ENABLE_CM0
+if { [info exists ENABLE_CM0] } {
+	set _ENABLE_CM0 $ENABLE_CM0
+} else {
+	set _ENABLE_CM0 1
+}
+
+# Is CM4 Debugging enabled ?
+global _ENABLE_CM4
+if { [info exists ENABLE_CM4] } {
+	set _ENABLE_CM4 $ENABLE_CM4
+} else {
+	set _ENABLE_CM4 1
+}
+
+global _WORKAREASIZE_CM0
+if { [info exists WORKAREASIZE_CM0] } {
+	set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
+} else {
+	set _WORKAREASIZE_CM0 0x4000
+}
+
+global _WORKAREASIZE_CM4
+if { [info exists WORKAREASIZE_CM4] } {
+	set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
+} else {
+	set _WORKAREASIZE_CM4 0x4000
+}
+
+global _WORKAREAADDR_CM0
+if { [info exists WORKAREAADDR_CM0] } {
+	set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
+} else {
+	set _WORKAREAADDR_CM0 0x08000000
+}
+
+global _WORKAREAADDR_CM4
+if { [info exists WORKAREAADDR_CM4] } {
+	set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
+} else {
+	set _WORKAREAADDR_CM4 0x08000000
+}
+
+proc init_reset { mode } {
+	global RESET_MODE
+	set RESET_MODE $mode
+
+	if {[using_jtag]} {
+		jtag arp_init-reset
+	}
+}
+
+# Utility to make 'reset halt' work as reset;halt on a target
+# It does not prevent running code after reset
+proc psoc6_deassert_post { target } {
+	# PSoC6 cleared AP registers including TAR during reset
+	# Force examine to synchronize OpenOCD target status
+	$target arp_examine
+
+	global RESET_MODE
+	global TARGET
+
+	if { $RESET_MODE ne "run" } {
+		$target arp_poll
+		$target arp_poll
+		set st [$target curstate]
+
+		if { $st eq "reset" } {
+			# we assume running state follows
+			# if reset accidentally halts, waiting is useless
+			catch { $target arp_waitstate running 100 }
+			set st [$target curstate]
+		}
+
+		if { $st eq "running" } {
+			echo "$target: Ran after reset and before halt..."
+			if { $target eq "${TARGET}.cm0" } {
+				# Try to cleanly reset whole system
+				# and halt the CM0 at entry point
+				psoc6 reset_halt
+				$target arp_waitstate halted 100
+			} else {
+				$target arp_halt
+			}
+		}
+	}
+}
+
+if { $_ENABLE_CM0 } {
+	target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1
+	${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
+
+	flash bank main_flash_cm0		psoc6 0x10000000 0 0 0 ${TARGET}.cm0
+	flash bank work_flash_cm0		psoc6 0x14000000 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_user_cm0	psoc6 0x16000800 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_nar_cm0	psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_key_cm0	psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_toc2_cm0	psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
+
+	${TARGET}.cm0 cortex_m reset_config sysresetreq
+	${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
+}
+
+if { $_ENABLE_CM4 } {
+	target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2
+	${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
+
+	flash bank main_flash_cm4		psoc6 0x10000000 0 0 0 ${TARGET}.cm4
+	flash bank work_flash_cm4		psoc6 0x14000000 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_user_cm4	psoc6 0x16000800 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_nar_cm4	psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_key_cm4	psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_toc2_cm4	psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
+
+	${TARGET}.cm4 cortex_m reset_config vectreset
+	${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
+}
+
+if { $_ENABLE_CM0 } {
+	# Use CM0+ by default on dual-core devices
+	targets ${TARGET}.cm0
+}
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pxa255.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pxa255.cfg
new file mode 100644
index 0000000..14ee13c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pxa255.cfg
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
+# This chip is now at end-of-life.  Final orders have been taken.
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME pxa255
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x69264013
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME xscale -endian $_ENDIAN \
+	-chain-position $_CHIPNAME.cpu
+
+# PXA255 comes out of reset using 3.6864 MHz oscillator.
+# Until the PLL kicks in, keep the JTAG clock slow enough
+# that we get no errors.
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
+
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
+
+# reset processing that works with PXA
+proc init_reset {mode} {
+	# assert both resets; equivalent to power-on reset
+	adapter assert trst assert srst
+
+	# drop TRST after at least 32 cycles
+	sleep 1
+	adapter deassert trst assert srst
+
+	# minimum 32 TCK cycles to wake up the controller
+	runtest 50
+
+	# now the TAP will be responsive; validate scanchain
+	jtag arp_init
+
+	# ... and take it out of reset
+	adapter deassert trst deassert srst
+}
+
+proc jtag_init {} {
+	init_reset startup
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pxa270.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pxa270.cfg
new file mode 100644
index 0000000..3121e96
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pxa270.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#Marvell/Intel PXA270 Script
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME pxa270
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+#IDs for pxa270. Are there more?
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # set useful default
+   set _CPUTAPID 0x49265013
+}
+
+if { [info exists CPUTAPID2] } {
+   set _CPUTAPID2 $CPUTAPID2
+} else {
+  # set useful default
+   set _CPUTAPID2 0x79265013
+}
+
+if { [info exists CPUTAPID3] } {
+   set _CPUTAPID2 $CPUTAPID3
+} else {
+  # set useful default
+   set _CPUTAPID3 0x89265013
+}
+
+# set adapter srst delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+adapter srst delay 260
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 250
+
+set _TARGETNAME $_CHIPNAME.cpu
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3
+
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
+# maps to PXA internal RAM. If you are using a PXA255
+# you must initialize SDRAM or leave this option off
+$_TARGETNAME configure -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pxa3xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pxa3xx.cfg
new file mode 100644
index 0000000..d670c84
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/pxa3xx.cfg
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Marvell PXA3xx
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME pxa3xx
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# IDs for all currently known PXA3xx chips
+if { [info exists CPUTAPID_PXA30X_A0] } {
+   set _CPUTAPID_PXA30X_A0 $CPUTAPID_PXA30X_A0
+} else {
+   set _CPUTAPID_PXA30X_A0 0x0E648013
+}
+if { [info exists CPUTAPID_PXA30X_A1] } {
+   set _CPUTAPID_PXA30X_A1 $CPUTAPID_PXA30X_A1
+} else {
+   set _CPUTAPID_PXA30X_A1 0x1E648013
+}
+if { [info exists CPUTAPID_PXA31X_A0] } {
+   set _CPUTAPID_PXA31X_A0 $CPUTAPID_PXA31X_A0
+} else {
+   set _CPUTAPID_PXA31X_A0 0x0E649013
+}
+if { [info exists CPUTAPID_PXA31X_A1] } {
+   set _CPUTAPID_PXA31X_A1 $CPUTAPID_PXA31X_A1
+} else {
+   set _CPUTAPID_PXA31X_A1 0x1E649013
+}
+if { [info exists CPUTAPID_PXA31X_A2] } {
+   set _CPUTAPID_PXA31X_A2 $CPUTAPID_PXA31X_A2
+} else {
+   set _CPUTAPID_PXA31X_A2 0x2E649013
+}
+if { [info exists CPUTAPID_PXA31X_B0] } {
+   set _CPUTAPID_PXA31X_B0 $CPUTAPID_PXA31X_B0
+} else {
+   set _CPUTAPID_PXA31X_B0 0x3E649013
+}
+if { [info exists CPUTAPID_PXA32X_B1] } {
+   set _CPUTAPID_PXA32X_B1 $CPUTAPID_PXA32X_B1
+} else {
+   set _CPUTAPID_PXA32X_B1 0x5E642013
+}
+if { [info exists CPUTAPID_PXA32X_B2] } {
+   set _CPUTAPID_PXA32X_B2 $CPUTAPID_PXA32X_B2
+} else {
+   set _CPUTAPID_PXA32X_B2 0x6E642013
+}
+if { [info exists CPUTAPID_PXA32X_C0] } {
+   set _CPUTAPID_PXA32X_C0 $CPUTAPID_PXA32X_C0
+} else {
+   set _CPUTAPID_PXA32X_C0 0x7E642013
+}
+
+# set adapter srst delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+adapter srst delay 260
+
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 250
+
+set _TARGETNAME $_CHIPNAME.cpu
+jtag newtap $_CHIPNAME cpu -irlen 11 -ircapture 0x1 -irmask 0x7f \
+	-expected-id $_CPUTAPID_PXA30X_A0 \
+	-expected-id $_CPUTAPID_PXA30X_A1 \
+	-expected-id $_CPUTAPID_PXA31X_A0 \
+	-expected-id $_CPUTAPID_PXA31X_A1 \
+	-expected-id $_CPUTAPID_PXA31X_A2 \
+	-expected-id $_CPUTAPID_PXA31X_B0 \
+	-expected-id $_CPUTAPID_PXA32X_B1 \
+	-expected-id $_CPUTAPID_PXA32X_B2 \
+	-expected-id $_CPUTAPID_PXA32X_C0
+
+target create $_TARGETNAME xscale -endian $_ENDIAN \
+	-chain-position $_TARGETNAME
+
+# work area in internal RAM.
+$_TARGETNAME configure -work-area-phys 0x5c030000 -work-area-size 0x10000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/qn908x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/qn908x.cfg
new file mode 100644
index 0000000..ac3e06b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/qn908x.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP QN908x Cortex-M4F with 128 KiB SRAM
+
+source [find target/swj-dp.tcl]
+
+set CHIPNAME qn908x
+set CHIPSERIES qn9080
+if { ![info exists WORKAREASIZE] } {
+  set WORKAREASIZE 0x20000
+}
+
+# SWD IDCODE (Cortex M4).
+set CPUTAPID 0x2ba01477
+
+swj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID
+dap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu
+
+set TARGETNAME $CHIPNAME.cpu
+target create $TARGETNAME cortex_m -dap $CHIPNAME.dap
+
+# SRAM is mapped at 0x04000000.
+$TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE
+
+# flash bank  qn908x   0 0  [calc_checksum]
+# The base must be set as 0x01000000, and the size parameter is unused.
+set FLASHNAME $CHIPNAME.flash
+flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
+
+# We write directly to flash memory over this adapter interface. For debugging
+# this could in theory be faster (the Core clock on reset is normally at 32MHz),
+# but for flashing 1MHz is more reliable.
+adapter speed 1000
+
+# Delay on reset line.
+adapter srst delay 200
+
+cortex_m reset_config sysresetreq
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/qualcomm_qca4531.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/qualcomm_qca4531.cfg
new file mode 100644
index 0000000..be0c8fa
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/qualcomm_qca4531.cfg
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable
+# Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT).
+#
+# Product page:
+# https://www.qualcomm.com/products/qca4531
+#
+# Notes:
+# - MIPS Processor ID (PRId): 0x00019374
+# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
+#   operating at up to 650 MHz
+# - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up
+#   to 300 MHz
+# - TRST is not available.
+# - EJTAG PrRst signal is not supported
+# - RESET_L pin B56 on the SoC will reset internal JTAG logic.
+#
+# Pins related for debug and bootstrap:
+# Name		Pin		Description
+#   JTAG
+# JTAG_TCK	GPIO0, (A27)	Software configurable, default JTAG
+# JTAG_TDI	GPIO1, (B23)	Software configurable, default JTAG
+# JTAG_TDO	GPIO2, (A28)	Software configurable, default JTAG
+# JTAG_TMS	GPIO3, (A29)	Software configurable, default JTAG
+#   Reset
+# RESET_L	-, (B56)	Input only
+# SYS_RST_L	GPIO17, (A79)	Output reset request or GPIO
+#   Bootstrap
+# JTAG_MODE	GPIO16, (A78)	0 - JTAG (Default); 1 - EJTAG
+# DDR_SELECT	GPIO10, (A57)	0 - DDR2; 1 - DDR1
+#   UART
+# UART0_SOUT	GPIO10, (A57)
+# UART0_SIN	GPIO9, (B49)
+
+# Per default we need to use "none" variant to be able properly "reset init"
+# or "reset halt" the CPU.
+reset_config none srst_pulls_trst
+
+# For SRST based variant we still need proper timings.
+# For ETH part the reset should be asserted at least for 10ms
+# Since there is no other information let's take 100ms to be sure.
+adapter srst pulse_width 100
+
+# according to the SoC documentation it should take at least 5ms from
+# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
+# to live.
+adapter srst delay 8
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME qca4531
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+# provide watchdog helper.
+proc disable_watchdog { } {
+	mww 0xb8060008 0x0
+}
+
+$_TARGETNAME configure -event halted { disable_watchdog }
+
+# Since PrRst is not supported and SRST will reset complete chip
+# with JTAG engine, we need to reset CPU from CPU itself.
+$_TARGETNAME configure -event reset-assert-pre {
+	halt
+}
+
+$_TARGETNAME configure -event reset-assert {
+	catch "mww 0xb806001C 0x01000000"
+}
+
+# To be able to trigger complete chip reset, in case JTAG is blocked
+# or CPU not responding, we still can use this helper.
+proc full_reset { } {
+	reset_config srst_only
+	reset
+	halt
+	reset_config none
+}
+
+# Section with helpers which can be used by boards
+proc qca4531_ddr2_550_550_init {} {
+	# Clear reset flags for different SoC components
+	mww 0xb806001c 0xfeceffff
+	mww 0xb806001c 0xeeceffff
+	mww 0xb806001c 0xe6ceffff
+
+	# PMU configurations
+	# Internal Switcher
+	mww 0xb8116c40 0x633c8176
+	# Increase the DDR voltage
+	mww 0xb8116c44 0x10200000
+	# XTAL Configurations
+	mww 0xb81162c0 0x4b962100
+	mww 0xb81162c4 0x480
+	mww 0xb81162c8 0x04000144
+	# Recommended PLL configurations
+	mww 0xb81161c4 0x54086000
+	mww 0xb8116244 0x54086000
+
+	# PLL init
+	mww 0xb8050008 0x0131001c
+	mww 0xb8050000 0x40001580
+	mww 0xb8050004 0x40015800
+	mww 0xb8050008 0x0131001c
+	mww 0xb8050000 0x00001580
+	mww 0xb8050004 0x00015800
+	mww 0xb8050008 0x01310000
+	mww 0xb8050044 0x781003ff
+	mww 0xb8050048 0x003c103f
+
+	# DDR2 init
+	mww 0xb8000108 0x401f0042
+	mww 0xb80000b8 0x0000166d
+	mww 0xb8000000 0xcfaaf33b
+	mww 0xb800015c 0x0000000f
+	mww 0xb8000004 0xa272efa8
+	mww 0xb8000018 0x0000ffff
+	mww 0xb80000c4 0x74444444
+	mww 0xb80000c8 0x00000444
+	mww 0xb8000004 0xa210ee28
+	mww 0xb8000004 0xa2b2e1a8
+	mww 0xb8000010 0x8
+	mww 0xb80000bc 0x0
+	mww 0xb8000010 0x10
+	mww 0xb80000c0 0x0
+	mww 0xb8000010 0x40
+	mww 0xb800000c 0x2
+	mww 0xb8000010 0x2
+	mww 0xb8000008 0xb43
+	mww 0xb8000010 0x1
+	mww 0xb8000010 0x8
+	mww 0xb8000010 0x4
+	mww 0xb8000010 0x4
+	mww 0xb8000008 0xa43
+	mww 0xb8000010 0x1
+	mww 0xb800000c 0x382
+	mww 0xb8000010 0x2
+	mww 0xb800000c 0x402
+	mww 0xb8000010 0x2
+	mww 0xb8000014 0x40be
+	mww 0xb800001C 0x20
+	mww 0xb8000020 0x20
+	mww 0xb80000cc 0xfffff
+
+	# UART GPIO programming
+	mww 0xb8040000 0xff30b
+	mww 0xb8040044 0x908
+	mww 0xb8040034 0x160000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/quark_d20xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/quark_d20xx.cfg
new file mode 100644
index 0000000..ca8f440
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/quark_d20xx.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x38289013
+}
+
+jtag newtap quark_d20xx quark -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable
+jtag newtap quark_d20xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e786013 -enable
+
+proc quark_d20xx_tapenable {} {
+	echo "enabling quark core tap"
+	irscan quark_d20xx.cltap 0x11
+	drscan quark_d20xx.cltap 12 1
+	runtest 10
+}
+
+proc quark_d20xx_tapdisable {} {
+	echo "disabling quark core tap"
+	irscan quark_d20xx.cltap 0x11
+	drscan quark_d20xx.cltap 12 0
+	runtest 10
+}
+
+proc quark_d20xx_setup {} {
+	jtag tapenable quark_d20xx.quark
+}
+
+jtag configure quark_d20xx.quark -event tap-enable \
+   "quark_d20xx_tapenable"
+
+jtag configure quark_d20xx.quark -event tap-disable \
+   "quark_d20xx_tapdisable"
+
+target create quark_d20xx.quark quark_d20xx -endian little -chain-position quark_d20xx.quark
+
+quark_d20xx.quark configure -event reset-start {
+	# need to halt the target to write to memory
+	if {[quark_d20xx.quark curstate] ne "halted"} { halt }
+	# set resetbreak via the core tap
+	irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x1
+	# trigger a warm reset
+	mww 0xb0800570 0x2
+	# clear resetbreak
+	irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x0
+}
+
+jtag configure quark_d20xx.quark -event setup \
+   "quark_d20xx_setup"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/quark_x10xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/quark_x10xx.cfg
new file mode 100644
index 0000000..6463f21
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/quark_x10xx.cfg
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME quark_x10xx
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x18289013
+}
+
+jtag newtap quark_x10xx cpu   -irlen 8  -irmask 0xff  -expected-id   $_CPUTAPID  -disable
+jtag newtap quark_x10xx cltap -irlen 8  -irmask 0xff  -expected-id   0x0e681013  -enable
+
+#openocd puts tap at front of chain not end of chain
+proc quark_x10xx_tapenable {} {
+	echo "enabling core tap"
+	irscan quark_x10xx.cltap 0x11
+	drscan quark_x10xx.cltap 64 1
+	runtest 10
+}
+
+proc quark_x10xx_tapdisable {} {
+	echo "disabling core tap"
+	irscan quark_x10xx.cltap 0x11
+	drscan quark_x10xx.cltap 64 0
+	runtest 10
+}
+
+proc quark_x10xx_setup {} {
+	jtag tapenable quark_x10xx.cpu
+}
+
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+   "quark_x10xx_tapenable"
+
+jtag configure $_CHIPNAME.cpu -event tap-disable \
+   "quark_x10xx_tapdisable"
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create quark_x10xx.cpu quark_x10xx -endian $_ENDIAN -chain-position quark_x10xx.cpu
+
+jtag configure $_CHIPNAME.cpu -event setup \
+   "quark_x10xx_setup"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/readme.txt b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/readme.txt
new file mode 100644
index 0000000..deec5b5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/readme.txt
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+Prerequisites:
+The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands
+do the same thing across all the targets.
+
+Rules to follow when writing scripts:
+
+1. The configuration script should be defined such as , for example, the following sequences are working:
+	reset
+	flash info 
+and
+	reset
+	flash erase_address  
+and
+	reset init
+	load
+
+In most cases this can be accomplished by specifying the default startup mode as reset_init (target command
+in the configuration file).
+
+2. If the target is correctly configured, flash must be writable without any other helper commands. It is
+assumed that all write-protect mechanisms should be disabled.
+
+3. The configuration scripts should be defined such as the binary that was written to flash verifies
+(turn off remapping, checksums, etc...)
+
+flash write_image [file] 
+verify_image [file] 
+
+4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked
+multiple times only the last setting is used.
+
+interface/xxx.cfg files are always executed *before* target/xxx.cfg
+files, so any adapter speed in interface/xxx.cfg will be overridden by
+target/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively,
+set the default JTAG speed.
+
+Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
+so one can create target subtype configurations where e.g. only
+amount of DRAM, oscillator speeds differ and having a single
+config file for the default/common settings.
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_r7s72100.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_r7s72100.cfg
new file mode 100644
index 0000000..dc9a1d8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_r7s72100.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ/A1H
+# https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME r7s72100
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
+
+# Configuring only one core using DAP.
+# Base addresses of cores:
+#  core 0  -  0x80030000
+set _TARGETNAME $_CHIPNAME.ca9
+dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
+target create ${_TARGETNAME} cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x80030000
+
+targets ${_TARGETNAME}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rcar_gen2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rcar_gen2.cfg
new file mode 100644
index 0000000..31ba156
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rcar_gen2.cfg
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car Generation 2 SOCs
+# - There are a combination of Cortex-A15s and Cortex-A7s for each Gen2 SOC
+# - Each SOC can boot through any of the, up to 2, core types that it has
+#   e.g. H2 can boot through Cortex-A15 or Cortex-A7
+
+# Supported Gen2 SOCs and their cores:
+# H2:  Cortex-A15 x 4, Cortex-A7 x 4
+# M2:  Cortex-A15 x 2
+# V2H: Cortex-A15 x 2
+# M2N: Cortex-A15 x 2
+# E2:                  Cortex-A7 x 2
+
+# Usage:
+# There are 2 configuration options:
+# SOC:       Selects the supported SOC. (Default 'H2')
+# BOOT_CORE: Selects the booting core. 'CA15', or 'CA7'
+#            Defaults to 'CA15' if the SOC has one, else defaults to 'CA7'
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc H2
+}
+
+# Set configuration for each SOC and the default 'BOOT_CORE'
+switch $_soc {
+	H2 {
+		set _CHIPNAME r8a7790
+		set _num_ca15 4
+		set _num_ca7 4
+		set _boot_core CA15
+	}
+	M2 {
+		set _CHIPNAME r8a7791
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	V2H {
+		set _CHIPNAME r8a7792
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	M2N {
+		set _CHIPNAME r8a7793
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	E2 {
+		set _CHIPNAME r8a7794
+		set _num_ca15 0
+		set _num_ca7 2
+		set _boot_core CA7
+	}
+	default {
+		error "'$_soc' is invalid!"
+	}
+}
+
+# If configured, override the default 'CHIPNAME'
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+}
+
+# If configured, override the default 'BOOT_CORE'
+if { [info exists BOOT_CORE] } {
+	set _boot_core $BOOT_CORE
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+echo "\t$_soc - $_num_ca15 CA15(s), $_num_ca7 CA7(s)"
+echo "\tBoot Core - $_boot_core\n"
+
+set _DAPNAME $_CHIPNAME.dap
+
+# TAP and DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
+dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+
+set CA15_DBGBASE {0x800B0000 0x800B2000 0x800B4000 0x800B6000}
+set CA7_DBGBASE  {0x800F0000 0x800F2000 0x800F4000 0x800F6000}
+
+set _targets ""
+set smp_targets ""
+
+proc setup_ca {core_name dbgbase num boot} {
+	global _CHIPNAME
+	global _DAPNAME
+	global smp_targets
+	global _targets
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $_CHIPNAME.$core_name.$_core
+		set _CTINAME $_TARGETNAME.cti
+		set _command "target create $_TARGETNAME cortex_a -dap $_DAPNAME \
+			-coreid $_core -dbgbase [lindex $dbgbase $_core]"
+		if { $_core == 0  && $boot == 1 } {
+			set _targets "$_TARGETNAME"
+		} else {
+			set _command "$_command -defer-examine"
+		}
+		set smp_targets "$smp_targets $_TARGETNAME"
+		eval $_command
+	}
+}
+
+# Organize target list based on the boot core
+if { [string equal $_boot_core CA15] } {
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 1
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 0
+} elseif { [string equal $_boot_core CA7] } {
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 1
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+} else {
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 0
+}
+
+source [find target/renesas_rcar_reset_common.cfg]
+
+eval "target smp $smp_targets"
+targets $_targets
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rcar_gen3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rcar_gen3.cfg
new file mode 100644
index 0000000..73b3003
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rcar_gen3.cfg
@@ -0,0 +1,207 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car Generation 3 SOCs
+# - There are a combination of Cortex-A57s, Cortex-A53s, and Cortex-R7 for each Gen3 SOC
+# - Each SOC can boot through any of the, up to 3, core types that it has
+#   e.g. H3 can boot through Cortex-A57, Cortex-A53, or Cortex-R7
+
+# Supported Gen3 SOCs and their cores:
+#  H3: Cortex-A57 x 4, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
+# M3W: Cortex-A57 x 2, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
+# M3N: Cortex-A57 x 2,                 Cortex-R7 x 2 (Lock-Step)
+# V3U:                 Cortex-A76 x 8, Cortex-R52 x2 (Lock-Step)
+# V3H:                 Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
+# V3M:                 Cortex-A53 x 2, Cortex-R7 x 2 (Lock-Step)
+#  E3:                 Cortex-A53 x 1, Cortex-R7 x 2 (Lock-Step)
+#  D3:                 Cortex-A53 x 1
+
+# Usage:
+# There are 2 configuration options:
+# SOC:       Selects the supported SOC. (Default 'H3')
+# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', or 'CR7'
+#            Defaults to 'CA57' if the SOC has one, else defaults to 'CA53'
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc H3
+}
+
+set _num_ca53 0
+set _num_ca57 0
+set _num_ca76 0
+set _num_cr52 0
+set _num_cr7 0
+
+# Set configuration for each SOC and the default 'BOOT_CORE'
+switch $_soc {
+	H3 {
+		set _CHIPNAME r8a77950
+		set _num_ca57 4
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+	}
+	M3W {
+		set _CHIPNAME r8a77960
+		set _num_ca57 2
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+	}
+	M3N {
+		set _CHIPNAME r8a77965
+		set _num_ca57 2
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+	}
+	V3M {
+		set _CHIPNAME r8a77970
+		set _num_ca57 0
+		set _num_ca53 2
+		set _num_cr7 1
+		set _boot_core CA53
+	}
+	V3H {
+		set _CHIPNAME r8a77980
+		set _num_ca57 0
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA53
+	}
+	E3 {
+		set _CHIPNAME r8a77990
+		set _num_ca57 0
+		set _num_ca53 1
+		set _num_cr7 1
+		set _boot_core CA53
+	}
+	D3 {
+		set _CHIPNAME r8a77995
+		set _num_ca57 0
+		set _num_ca53 1
+		set _num_cr7 0
+		set _boot_core CA53
+	}
+	V3U {
+		set _CHIPNAME r8a779a0
+		set _num_ca76 8
+		set _num_cr52 1
+		set _boot_core CA76
+	}
+	default {
+		error "'$_soc' is invalid!"
+	}
+}
+
+# If configured, override the default 'CHIPNAME'
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+}
+
+# If configured, override the default 'BOOT_CORE'
+if { [info exists BOOT_CORE] } {
+	set _boot_core $BOOT_CORE
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x5ba00477
+}
+
+echo "\t$_soc - $_num_ca76 CA76(s), $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr52 CR52(s), $_num_cr7 CR7(s)"
+echo "\tBoot Core - $_boot_core\n"
+
+set _DAPNAME $_CHIPNAME.dap
+
+# TAP and DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
+dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+
+set CA76_DBGBASE {0x81410000 0x81510000 0x81610000 0x81710000 0x81c10000 0x81d10000 0x81e10000 0x81f10000}
+set CA76_CTIBASE {0x81420000 0x81520000 0x81620000 0x81720000 0x81c20000 0x81d20000 0x81e20000 0x81f20000}
+set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
+set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
+set CR52_DBGBASE 0x80c10000
+set CR52_CTIBASE 0x80c20000
+set  CR7_DBGBASE 0x80910000
+set  CR7_CTIBASE 0x80918000
+
+set _targets ""
+set smp_targets ""
+
+proc setup_a5x {core_name dbgbase ctibase num boot} {
+	global _CHIPNAME
+	global _DAPNAME
+	global smp_targets
+	global _targets
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $_CHIPNAME.$core_name.$_core
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $_DAPNAME -ap-num 1 \
+			-baseaddr [lindex $ctibase $_core]
+		set _command "target create $_TARGETNAME aarch64 -dap $_DAPNAME \
+			-ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME"
+		if { $_core == 0  && $boot == 1 } {
+			set _targets "$_TARGETNAME"
+		} else {
+			set _command "$_command -defer-examine"
+		}
+		set smp_targets "$smp_targets $_TARGETNAME"
+		eval $_command
+	}
+}
+
+proc setup_crx {core_name dbgbase ctibase num boot} {
+	global _CHIPNAME
+	global _DAPNAME
+	global _targets
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $_CHIPNAME.$core_name
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
+		if { $core_name == "r52" } {
+			set _command "target create $_TARGETNAME armv8r -dap $_DAPNAME \
+				-ap-num 1 -dbgbase $dbgbase -cti $_CTINAME"
+		} else {
+			set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
+				-ap-num 1 -dbgbase $dbgbase"
+		}
+		if { $boot == 1 } {
+			set _targets "$_TARGETNAME"
+		} else {
+			set _command "$_command -defer-examine"
+		}
+		eval $_command
+	}
+}
+
+# Organize target list based on the boot core
+if { [string equal $_boot_core CA76] } {
+	setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 1
+	setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0
+} elseif { [string equal $_boot_core CA57] } {
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
+	setup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
+} elseif { [string equal $_boot_core CA53] } {
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
+	setup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
+} elseif { [string equal $_boot_core CR52] } {
+	setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1
+	setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 0
+} else {
+	setup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  1
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
+}
+
+source [find target/renesas_rcar_reset_common.cfg]
+
+eval "target smp $smp_targets"
+targets $_targets
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rcar_reset_common.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rcar_reset_common.cfg
new file mode 100644
index 0000000..987f0c8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rcar_reset_common.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas R-Car Gen2 Evaluation Board common settings
+
+reset_config trst_and_srst srst_nogate
+
+proc init_reset {mode} {
+    # Assert both resets: equivalent to a power-on reset
+    adapter assert trst assert srst
+
+    # Deassert TRST to begin TAP communication
+    adapter deassert trst assert srst
+
+    # TAP should now be responsive, validate the scan-chain
+    jtag arp_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rz.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rz.cfg
new file mode 100644
index 0000000..a0489de
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rz.cfg
@@ -0,0 +1,239 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ SOCs
+# - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7
+# and Cortex-M33 for each SOC
+# - Each SOC can boot through the Cortex-A5x cores or the Cortex-M33
+
+# Supported RZ SOCs and their cores:
+# RZ/G2H:   Cortex-A57 x4, Cortex-A53 x4, Cortex-R7
+# RZ/G2M:   Cortex-A57 x2, Cortex-A53 x4, Cortex-R7
+# RZ/G2N:   Cortex-A57 x2,                Cortex-R7
+# RZ/G2E:                  Cortex-A53 x2, Cortex-R7
+# RZ/G2L:                  Cortex-A55 x2, Cortex-M33
+# RZ/V2L:                  Cortex-A55 x2, Cortex-M33
+# RZ/G2LC:                 Cortex-A55 x2, Cortex-M33
+# RZ/G2UL:                 Cortex-A55 x1, Cortex-M33
+# RZ/G3S:                  Cortex-A55 x1, Cortex-M33 x2
+
+# Usage:
+# There are 2 configuration options:
+# SOC:       Selects the supported SOC. (Default 'G2L')
+# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', 'CA55' or CM33
+
+transport select jtag
+reset_config trst_and_srst srst_gates_jtag
+adapter speed 4000
+adapter srst delay 500
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc G2L
+}
+
+set _num_ca57 0
+set _num_ca55 0
+set _num_ca53 0
+set _num_cr7 0
+set _num_cm33 0
+
+# Set configuration for each SOC and the default 'BOOT_CORE'
+switch $_soc {
+	G2H {
+		set _CHIPNAME r8a774ex
+		set _num_ca57 4
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+		set _ap_num 1
+	}
+	G2M {
+		set _CHIPNAME r8a774ax
+		set _num_ca57 2
+		set _num_ca53 4
+		set _num_cr7 1
+		set _boot_core CA57
+		set _ap_num 1
+	}
+	G2N {
+		set _CHIPNAME r8a774bx
+		set _num_ca57 2
+		set _num_ca53 0
+		set _num_cr7 1
+		set _boot_core CA57
+		set _ap_num 1
+	}
+	G2E {
+		set _CHIPNAME r8a774c0
+		set _num_ca57 0
+		set _num_ca53 2
+		set _num_cr7 1
+		set _boot_core CA53
+		set _ap_num 1
+	}
+	G2L {
+		set _CHIPNAME r9a07g044l
+		set _num_ca55 2
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	V2L {
+		set _CHIPNAME r9a07g054l
+		set _num_ca55 2
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	G2LC {
+		set _CHIPNAME r9a07g044c
+		set _num_ca55 2
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	G2UL {
+		set _CHIPNAME r9a07g043u
+		set _num_ca55 1
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	G3S {
+		set _CHIPNAME r9a08g045s
+		set _num_ca55 1
+		set _num_cm33 2
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	default {
+		error "'$_soc' is invalid!"
+	}
+}
+
+# If configured, override the default 'CHIPNAME'
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+}
+
+# If configured, override the default 'BOOT_CORE'
+if { [info exists BOOT_CORE] } {
+	set _boot_core $BOOT_CORE
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x6ba00477
+}
+
+echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), \
+	$_num_cr7 CR7(s), $_num_cm33 CM33(s)"
+echo "\tBoot Core - $_boot_core\n"
+
+set _DAPNAME $_CHIPNAME.dap
+
+
+# TAP and DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -ignore-version
+dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+echo "$_CHIPNAME.cpu"
+
+set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+set CA55_DBGBASE {0x10E10000 0x10F10000}
+set CA55_CTIBASE {0x10E20000 0x10F20000}
+set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
+set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
+set  CR7_DBGBASE 0x80910000
+set  CR7_CTIBASE 0x80918000
+set CM33_DBGBASE {0xE000E000 0xE010E000}
+set CM33_CTIBASE {0xE0042000 0xE0142000}
+
+set smp_targets ""
+
+proc setup_a5x {core_name dbgbase ctibase num boot} {
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $::_CHIPNAME.$core_name.$_core
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \
+			-baseaddr [lindex $ctibase $_core]
+		target create $_TARGETNAME aarch64 -dap $::_DAPNAME \
+			-ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] \
+			-cti $_CTINAME
+		if { $_core > 0 || $boot == 0 } {
+			$_TARGETNAME configure -defer-examine
+		}
+		set ::smp_targets "$::smp_targets $_TARGETNAME"
+	}
+}
+
+proc setup_cr7 {dbgbase ctibase} {
+	set _TARGETNAME $::_CHIPNAME.r7
+	set _CTINAME $_TARGETNAME.cti
+	cti create $_CTINAME -dap $::_DAPNAME -ap-num 1 -baseaddr $ctibase
+	target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \
+		-ap-num 1 -dbgbase $dbgbase -defer-examine
+}
+proc setup_cm33 {dbgbase ctibase num boot} {
+	if { $::_soc == "G2L" || $::_soc == "V2L" \
+	|| $::_soc == "G2LC" || $::_soc == "G2UL" } {
+		set _ap_num  2
+	} elseif { $::_soc == "G3S" } {
+		set _ap_num  3
+	}
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		if { $num <= 1 } {
+			set _TARGETNAME $::_CHIPNAME.m33
+		} else {
+			set _TARGETNAME $::_CHIPNAME.m33.$_core
+		}
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $::_DAPNAME -ap-num $_ap_num \
+			-baseaddr [lindex $ctibase $_core]
+		target create $_TARGETNAME cortex_m -dap $::_DAPNAME \
+			-ap-num $_ap_num -dbgbase [lindex $dbgbase $_core]
+		if { $boot == 0 } {
+			$_TARGETNAME configure -defer-examine
+		}
+		incr $_ap_num
+	}
+}
+
+# Organize target list based on the boot core
+if { $_boot_core == "CA57" } {
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
+	setup_cr7 $CR7_DBGBASE $CR7_CTIBASE
+} elseif { $_boot_core == "CA53" } {
+	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
+	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
+	setup_cr7 $CR7_DBGBASE $CR7_CTIBASE
+} elseif { $_boot_core == "CA55" } {
+	setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1
+	setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 0
+} elseif { $_boot_core == "CM33" } {
+	setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 0
+	setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 1
+}
+
+echo "SMP targets:$smp_targets"
+eval "target smp $smp_targets"
+
+if { $_soc == "G2L" || $_soc == "V2L" || $_soc == "G2LC" \
+|| $_soc == "G2UL" || $_soc == "G3S"} {
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1
+}
+
+proc init_reset {mode} {
+    # Assert both resets: equivalent to a power-on reset
+    adapter assert trst assert srst
+
+    # Deassert TRST to begin TAP communication
+    adapter deassert trst assert srst
+
+    # TAP should now be responsive, validate the scan-chain
+    jtag arp_init
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rz_five.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rz_five.cfg
new file mode 100644
index 0000000..5ab94ab
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_rz_five.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ/Five SoC
+#
+# General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz)
+
+transport select jtag
+
+reset_config trst_and_srst srst_gates_jtag
+adapter speed 4000
+adapter srst delay 500
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME r9A07g043u
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_s7g2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_s7g2.cfg
new file mode 100644
index 0000000..fa9c579
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/renesas_s7g2.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Renesas Synergy S7 G2 w/ ARM Cortex-M4 @ 240 MHz
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME s7g2
+}
+
+if { [info exists CPU_JTAG_TAPID] } {
+	set _CPU_JTAG_TAPID $CPU_JTAG_TAPID
+} else {
+	set _CPU_JTAG_TAPID 0x5ba00477
+}
+
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x5ba02477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+	set _CPU_TAPID $_CPU_JTAG_TAPID
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	# 640 KB On-Chip SRAM
+	set _WORKAREASIZE 0xa0000
+}
+
+$_TARGETNAME configure -work-area-phys 0x1ffe0000 \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rk3308.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rk3308.cfg
new file mode 100644
index 0000000..b6086f1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rk3308.cfg
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Rockchip RK3308 Target
+# https://rockchip.fr/RK3308%20datasheet%20V1.5.pdf
+# https://dl.radxa.com/rockpis/docs/hw/datasheets/Rockchip%20RK3308TRM%20V1.1%20Part1-20180810.pdf
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME rk3308
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x2ba01477
+}
+
+adapter speed 12000
+
+transport select swd
+
+# declare the one SWD tap to access the DAP
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# declare the 4 main application cores
+set _TARGETNAME $_CHIPNAME.core
+set _smp_command ""
+
+set $_TARGETNAME.base(0) 0x81010000
+set $_TARGETNAME.base(1) 0x81012000
+set $_TARGETNAME.base(2) 0x81014000
+set $_TARGETNAME.base(3) 0x81016000
+
+set $_TARGETNAME.cti(0) 0x81018000
+set $_TARGETNAME.cti(1) 0x81019000
+set $_TARGETNAME.cti(2) 0x8101a000
+set $_TARGETNAME.cti(3) 0x8101b000
+
+set _cores 4
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
+                         -dbgbase [set $_TARGETNAME.base($_core)]"
+
+    if { $_core != 0 } {
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+        set _command "$_command -defer-examine"
+    } else {
+        # uncomment to use hardware threads pseudo rtos
+        # set _command "$_command -rtos hwthread"
+        set _command "$_command -work-area-size 0x40000 -work-area-phys 0xfff80000 \
+                                -work-area-backup 0"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+targets ${_TARGETNAME}0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rk3399.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rk3399.cfg
new file mode 100644
index 0000000..1e90414
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rk3399.cfg
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Rockchip RK3399 Target
+# https://rockchip.fr/RK3399%20datasheet%20V1.8.pdf
+# https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.4%20Part1.pdf
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME rk3399
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x5ba02477
+}
+
+adapter speed 12000
+
+transport select swd
+
+# declare the one SWD tap to access the DAP
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+set _TARGETNAME $_CHIPNAME.lcore
+# declare the 6 main application cores
+set _smp_command ""
+
+set $_TARGETNAME.base(0) 0x80030000
+set $_TARGETNAME.base(1) 0x80032000
+set $_TARGETNAME.base(2) 0x80034000
+set $_TARGETNAME.base(3) 0x80036000
+set $_TARGETNAME.cti(0) 0x80038000
+set $_TARGETNAME.cti(1) 0x80039000
+set $_TARGETNAME.cti(2) 0x8003a000
+set $_TARGETNAME.cti(3) 0x8003b000
+
+
+set _TARGETNAME $_CHIPNAME.bcore
+set $_TARGETNAME.base(4) 0x80210000
+set $_TARGETNAME.base(5) 0x80310000
+set $_TARGETNAME.cti(4) 0x80220000
+set $_TARGETNAME.cti(5) 0x80320000
+
+set _cores 6
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+    if {$_core < 4} {
+        set _TARGETNAME $_CHIPNAME.lcore
+    } else {
+        set _TARGETNAME $_CHIPNAME.bcore
+    }
+
+
+    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 1
+
+    target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
+                         -dbgbase [set $_TARGETNAME.base($_core)]
+
+    if { $_core != 0 } {
+        ${_TARGETNAME}$_core configure -defer-examine
+    } else {
+        # uncomment to use hardware threads pseudo rtos
+        # ${_TARGETNAME}$_core configure -rtos hwthread"
+        ${_TARGETNAME}$_core configure -work-area-size 0x30000 -work-area-phys 0xff8c0000 \
+                                -work-area-backup 0
+    }
+    set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+}
+
+target smp $_smp_command
+
+targets rk3399.lcore0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rp2040.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rp2040.cfg
new file mode 100644
index 0000000..5e78c69
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rp2040.cfg
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# RP2040 is a microcontroller with dual Cortex-M0+ core.
+# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html
+
+# The device requires multidrop SWD for debug.
+transport select swd
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME rp2040
+}
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x01002927
+}
+
+# Set to '1' to start rescue mode
+if { [info exists RESCUE] } {
+	set _RESCUE $RESCUE
+} else {
+	set _RESCUE 0
+}
+
+# Set to '0' or '1' for single core configuration, 'SMP' for -rtos hwthread
+# handling of both cores, anything else for isolated debugging of both cores
+if { [info exists USE_CORE] } {
+	set _USE_CORE $USE_CORE
+} else {
+	set _USE_CORE SMP
+}
+set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }]
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+# The rescue debug port uses the DP CTRL/STAT bit DBGPWRUPREQ to reset the
+# PSM (power on state machine) of the RP2040 with a flag set in the
+# VREG_AND_POR_CHIP_RESET register. Once the reset is released
+# (by clearing the DBGPWRUPREQ flag), the bootrom will run, see this flag,
+# and halt. Allowing the user to load some fresh code, rather than loading
+# the potentially broken code stored in flash
+if { $_RESCUE } {
+	dap create $_CHIPNAME.rescue_dap -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0xf -ignore-syspwrupack
+	init
+
+	# Clear DBGPWRUPREQ
+	$_CHIPNAME.rescue_dap dpreg 0x4 0x00000000
+
+	# Verifying CTRL/STAT is 0
+	set _CTRLSTAT [$_CHIPNAME.rescue_dap dpreg 0x4]
+	if {[expr {$_CTRLSTAT & 0xf0000000}]} {
+		echo "Rescue failed, DP CTRL/STAT readback $_CTRLSTAT"
+	} else {
+		echo "Now restart OpenOCD without RESCUE flag and load code to RP2040"
+	}
+	shutdown
+}
+
+# core 0
+if { $_USE_CORE != 1 } {
+	dap create $_CHIPNAME.dap0 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0
+	set _TARGETNAME_0 $_CHIPNAME.core0
+	target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0
+	# srst does not exist; use SYSRESETREQ to perform a soft reset
+	$_TARGETNAME_0 cortex_m reset_config sysresetreq
+}
+
+# core 1
+if { $_USE_CORE != 0 } {
+	dap create $_CHIPNAME.dap1 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 1
+	set _TARGETNAME_1 $_CHIPNAME.core1
+	target create $_TARGETNAME_1 cortex_m -dap $_CHIPNAME.dap1 -coreid 1
+	$_TARGETNAME_1 cortex_m reset_config sysresetreq
+}
+
+if {[string compare $_USE_CORE SMP] == 0} {
+	$_TARGETNAME_0 configure  -rtos hwthread
+	$_TARGETNAME_1 configure  -rtos hwthread
+	target smp $_TARGETNAME_0 $_TARGETNAME_1
+}
+
+if { $_USE_CORE == 1 } {
+	set _FLASH_TARGET $_TARGETNAME_1
+} else {
+	set _FLASH_TARGET $_TARGETNAME_0
+}
+# Backup the work area. The flash probe runs an algorithm on the target CPU.
+# The flash is probed during gdb connect if gdb memory_map is enabled (by default).
+$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET
+
+if { $_BOTH_CORES } {
+	# Alias to ensure gdb connecting to core 1 gets the correct memory map
+	flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME
+
+	# Select core 0
+	targets $_TARGETNAME_0
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rsl10.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rsl10.cfg
new file mode 100644
index 0000000..f4692cc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rsl10.cfg
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# RSL10: ARM Cortex-M3
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME rsl10
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# TODO: configure reset
+# reset_config srst_only srst_nogate connect_assert_srst
+
+$_TARGETNAME configure -event examine-fail rsl10_lock_warning
+
+proc rsl10_check_connection {} {
+    set target [target current]
+    set dap [$target cget -dap]
+
+	set IDR [$dap apreg 0 0xfc]
+	if {$IDR != 0x24770011} {
+		echo "Error: Cannot access RSL10 AP, maybe connection problem!"
+		return 1
+	}
+    return 0
+}
+
+proc rsl10_lock_warning {} {
+    if {[rsl10_check_connection]} {return}
+
+    poll off
+    echo "****** WARNING ******"
+    echo "RSL10 device probably has lock engaged."
+    echo "Debug access is denied."
+    echo "Use 'rsl10 unlock key1 key2 key3 key4' to erase and unlock the device."
+    echo "****** ....... ******"
+    echo ""
+}
+
+flash bank $_CHIPNAME.main rsl10 0x00100000 0x60000 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvr1 rsl10 0x00080000 0x800 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvr2 rsl10 0x00080800 0x800 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvr3 rsl10 0x00081000 0x800 0 0 $_TARGETNAME
+
+# TODO: implement flashing for nvr4
+# flash bank $_CHIPNAME.nvr4 rsl10 0x00081800 0x400 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rtl872xd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rtl872xd.cfg
new file mode 100644
index 0000000..65730e2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/rtl872xd.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+# Realtek RTL872xD (ARM Cortex-M33 + M23, wifi+bt dualband soc)
+
+# HLA does not support AP other than 0
+if { [using_hla] } {
+        echo "ERROR: HLA transport cannot work with this target."
+        shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+        set _CHIPNAME $CHIPNAME
+} else {
+        set _CHIPNAME rtl872xd
+}
+
+if { [info exists CPUTAPID] } {
+        set _CPUTAPID $CPUTAPID
+} else {
+        set _CPUTAPID 0x6ba02477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME.km0 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+target create $_TARGETNAME.km4 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 2
+
+cortex_m reset_config sysresetreq
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/s32k.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/s32k.cfg
new file mode 100644
index 0000000..3ff3239
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/s32k.cfg
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale S32K devices
+# Similar to Kinetis Kx series devices.
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME s32k
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x0995001d
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.pflash
+flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME -s32k
+kinetis create_banks
+
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {[using_hla]} {
+   echo ""
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions."
+   echo " A high level adapter (like a ST-Link) you are currently using cannot access"
+   echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your"
+   echo " configuration. Also security locked state of the device will not be reported."
+   echo " Expect problems connecting to a blank device without boot ROM."
+   echo ""
+   echo " Be very careful as you can lock the device though there is no way to unlock"
+   echo " it without mass erase. Don't set write protection on the first block."
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo ""
+} else {
+   # Detect secured MCU or boot lock-up in RESET/WDOG loop
+   $_TARGETNAME configure -event examine-fail {
+      kinetis mdm check_security
+   }
+   # During RESET/WDOG loop the target is sometimes falsely examined
+   $_TARGETNAME configure -event examine-end {
+      kinetis mdm check_security
+   }
+
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+# Disable watchdog not to disturb OpenOCD algorithms running on MCU
+# (e.g. armv7m_checksum_memory() in verify_image)
+# Flash driver also disables watchdog before FTFA flash programming.
+$_TARGETNAME configure -event reset-init {
+   kinetis disable_wdog
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c2410.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c2410.cfg
new file mode 100644
index 0000000..5a04871
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c2410.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Found on the 'TinCanTools' Hammer board.
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME s3c2410
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # This config file was defaulting to big endian..
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # Force an error until we get a good number.
+   set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that cannot set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c2440.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c2440.cfg
new file mode 100644
index 0000000..d976a8e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c2440.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Samsung 2440 system on chip
+# Tested on a S3C2440 Evaluation board by keesj
+# Processor       : ARM920Tid(wb) rev 0 (v4l)
+# Info:   JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME s3c2440
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a bigendian
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0032409d
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
+
+#reset configuration
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c2450.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c2450.cfg
new file mode 100644
index 0000000..801e1bc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c2450.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the Samsung 2450 system on chip
+# Processor       : ARM926ejs (wb) rev 0 (v4l)
+# Info:   JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F
+
+
+# FIX!!! what to use here?
+#
+# RCLK?
+#
+# adapter speed 0
+#
+# Really low clock during reset?
+#
+# adapter speed 1
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME s3c2450
+}
+
+if { [info exists ENDIAN] } {
+  set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+  set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+  set _CPUTAPID $CPUTAPID
+} else {
+  set _CPUTAPID 0x07926f0f
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# FIX!!!!! should this really use srst_pulls_trst?
+# With srst_pulls_trst "reset halt" will not reset into the
+# halted mode, but rather "reset run" and then halt the target.
+#
+# However, without "srst_pulls_trst", then "reset halt" produces weird
+# errors:
+# WARNING: unknown debug reason: 0x0
+reset_config trst_and_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c4510.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c4510.cfg
new file mode 100644
index 0000000..45bed2f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c4510.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME s3c4510
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+
+# This appears to be a "Version 1" arm7tdmi.
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c6410.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c6410.cfg
new file mode 100644
index 0000000..c157458
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/samsung_s3c6410.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# -*- tcl -*-
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a SMDK6410
+# Processor       : ARM1176
+# Info:   JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
+# [and I do not believe it to be accurate, hence the 0xffffffff below]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME s3c6410
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+  # this defaults to a bigendian
+   set _ENDIAN little
+}
+
+# trace buffer
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x2b900f0f
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07b76f0f
+}
+
+#jtag scan chain
+
+jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETBTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+#reset configuration
+reset_config trst_and_srst
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/sharp_lh79532.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/sharp_lh79532.cfg
new file mode 100644
index 0000000..af6ceab
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/sharp_lh79532.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lh79532
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # sharp changed the number!
+   set _CPUTAPID 0x00002061
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/sim3x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/sim3x.cfg
new file mode 100644
index 0000000..e6bea70
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/sim3x.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Silicon Laboratories SiM3x Cortex-M3
+#
+
+# SiM3x devices support both JTAG and SWD transports.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME SiM3x
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+if { [info exists CPURAMSIZE] } {
+  set _CPURAMSIZE $CPURAMSIZE
+} else {
+# Minimum size of RAM in the Silicon Labs product matrix (8KB)
+	set _CPURAMSIZE 0x2000
+}
+
+if { [info exists CPUROMSIZE] } {
+  set _CPUROMSIZE $CPUROMSIZE
+} else {
+# Minimum size of FLASH in the Silicon Labs product matrix (32KB)
+	set _CPUROMSIZE 0x8000
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE $_CPURAMSIZE
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/smp8634.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/smp8634.cfg
new file mode 100644
index 0000000..0e609d8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/smp8634.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Sigma Designs SMP8634 (eventually even SMP8635)
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME smp8634
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x08630001
+}
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+reset_config trst_and_srst separate
+
+# jtag scan chain
+# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/snps_em_sk_fpga.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/snps_em_sk_fpga.cfg
new file mode 100644
index 0000000..62f4dec
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/snps_em_sk_fpga.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2014-2015,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# Xilinx Spartan-6 XC6SLX45  FPGA on EM Starter Kit v1.
+# Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2.
+#
+
+source [find cpu/arc/em.tcl]
+
+set _CHIPNAME arc-em
+set _TARGETNAME $_CHIPNAME.cpu
+
+# EM SK IDENTITY is 0x200444b1
+# EM SK v2 IDENTITY is 0x200044b1
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \
+  -expected-id 0x200044b1
+
+set _coreid 0
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
+  -coreid 0 -dbgbase $_dbgbase -endian little
+
+# There is no SRST, so do a software reset
+$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
+
+arc_em_init_regs
+
+# vim:ft=tcl
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/snps_hsdk.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/snps_hsdk.cfg
new file mode 100644
index 0000000..b4f3684
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/snps_hsdk.cfg
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) 2019,2020 Synopsys, Inc.
+#  Anton Kolesov 
+#  Didin Evgeniy 
+
+#
+# HS Development Kit SoC.
+#
+# Contains quad-core ARC HS38.
+#
+
+source [find cpu/arc/hs.tcl]
+
+set _coreid 0
+set _dbgbase [expr {$_coreid << 13}]
+
+# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
+# OpenOCD is concerned EM and HS are identical.
+set _CHIPNAME arc-em
+
+# OpenOCD discovers JTAG TAPs in reverse order.
+
+# ARC HS38 core 4
+set _TARGETNAME $_CHIPNAME.cpu4
+jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+# Flush L2$.
+$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {$_coreid << 13}]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 4.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 3
+set _TARGETNAME $_CHIPNAME.cpu3
+jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {$_coreid << 13}]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 3.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 2
+set _TARGETNAME $_CHIPNAME.cpu2
+jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {$_coreid << 13}]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 2.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 1
+set _TARGETNAME $_CHIPNAME.cpu1
+jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 1.
+$_TARGETNAME arc cache l2 auto 1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/snps_hsdk_4xd.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/snps_hsdk_4xd.cfg
new file mode 100644
index 0000000..1520e3d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/snps_hsdk_4xd.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Copyright (C) 2023 Synopsys, Inc.
+# Artemiy Volkov 
+
+# Adapted from tcl/target/snps_hsdk.cfg.
+
+#
+# HS Development Kit SoC.
+#
+# Contains quad-core ARC HS47D.
+#
+
+source [find cpu/arc/hs.tcl]
+
+set _coreid 0
+set _dbgbase [expr {$_coreid << 13}]
+
+# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
+# OpenOCD is concerned EM and HS are identical.
+set _CHIPNAME arc-em
+
+
+proc setup_cpu {core_index expected_id} {
+	global _coreid
+	global _dbgbase
+	global _CHIPNAME
+
+	set _TARGETNAME $_CHIPNAME.cpu$core_index
+	jtag newtap $_CHIPNAME cpu$core_index -irlen 4 -ircapture 0x1 -expected-id $expected_id
+
+	target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+	$_TARGETNAME configure -coreid $_coreid
+	$_TARGETNAME configure -dbgbase $_dbgbase
+	$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
+
+	arc_hs_init_regs
+
+	$_TARGETNAME arc cache l2 auto 1
+
+	set _coreid [expr {$_coreid + 1}]
+	set _dbgbase [expr {$_coreid << 13}]
+}
+
+# OpenOCD discovers JTAG TAPs in reverse order.
+
+setup_cpu 4 0x100c54b1
+setup_cpu 3 0x100854b1
+setup_cpu 2 0x100454b1
+setup_cpu 1 0x100054b1
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/spacemit-k1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/spacemit-k1.cfg
new file mode 100644
index 0000000..ef5d783
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/spacemit-k1.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# SpacemiT Key Stone K1 target
+#
+# https://www.spacemit.com/key-stone-k1
+#
+
+transport select jtag
+
+adapter speed 2000
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME k1
+}
+
+if { [info exists CORES] } {
+    set _cores $CORES
+} else {
+    set _cores 1
+}
+
+if { [info exists SECJTAG] } {
+    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21
+} else {
+    jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable
+    jtag configure pre.unknown -event tap-enable ""
+
+    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21 -disable
+    jtag configure $_CHIPNAME.cpu -event tap-enable ""
+
+    jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version
+
+    jtag configure post.unknown -event setup {
+        global _CHIPNAME
+
+        irscan post.unknown 0x98
+        drscan post.unknown 16 0xa
+
+        jtag tapenable pre.unknown
+        jtag tapenable $_CHIPNAME.cpu
+    }
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+set DBGBASE {0x0 0x400}
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+    target create $_TARGETNAME.$_core riscv -chain-position $_TARGETNAME \
+        -coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr {$_core / 4}]]
+
+    if { [expr {$_core % 4}] == 0 } {
+        $_TARGETNAME.$_core configure -rtos hwthread
+    }
+
+    set _smp_command "$_smp_command $_TARGETNAME.$_core"
+}
+
+eval $_smp_command
+
+set _SPEED 8000
+
+$_TARGETNAME.0 configure -event examine-start {
+    adapter speed $_SPEED
+    puts [ adapter speed ]
+}
+
+foreach t [target names] {
+    # $t riscv set_mem_access sysbus progbuf
+    $t riscv set_mem_access progbuf
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/spear3xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/spear3xx.cfg
new file mode 100644
index 0000000..1261cd4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/spear3xx.cfg
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Target configuration for the ST SPEAr3xx family of system on chip
+# Supported SPEAr300, SPEAr310, SPEAr320
+# http://www.st.com/spear
+#
+# Processor: ARM926ejs
+# Info:      JTAG tap: spear3xx.cpu tap/device found: 0x07926041
+# Date:      2009-10-31
+# Author:    Antonio Borneo 
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME spear3xx
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x07926041
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x03 \
+	-expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN \
+	-chain-position $_TARGETNAME
+
+# SPEAr3xx has a 8K block of sram @ 0xd280.0000
+# REVISIT: what OS puts virtual address equal to phys?
+$_TARGETNAME configure \
+	-work-area-virt 0xd2800000 \
+	-work-area-phys 0xd2800000 \
+	-work-area-size 0x2000 \
+	-work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stellaris.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stellaris.cfg
new file mode 100644
index 0000000..3cd91eb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stellaris.cfg
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TI/Luminary Stellaris LM3S chip family
+
+# Some devices have errata in returning their device class.
+# DEVICECLASS is provided as a manual override
+# Manual setting of a device class of 0xff is not allowed
+
+global _DEVICECLASS
+
+if { [info exists DEVICECLASS] } {
+   set _DEVICECLASS $DEVICECLASS
+} else {
+   set _DEVICECLASS 0xff
+}
+
+# Luminary chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# For now we ignore the SPI and UART options, which
+# are usable only for ISP style initial flash programming.
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lm3s
+}
+
+# CPU TAP ID 0x1ba00477 for early Sandstorm parts
+# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
+# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
+# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
+# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
+# ... we'll ignore the JTAG version field, rather than list every
+# chip revision that turns up.
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0ba00477
+}
+
+# SWD DAP, and JTAG TAP, take same params for now;
+# ... even though SWD ignores all except TAPID, and
+# JTAG shouldn't need anything more then irlen. (and TAPID).
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
+    -expected-id $_CPUTAPID -ignore-version
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   # default to 2K working area
+   set _WORKAREASIZE 0x800
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# 8K working area at base of ram, not backed up
+#
+# NOTE: you may need or want to reconfigure the work area;
+# some parts have just 6K, and you may want to use other
+# addresses (at end of mem not beginning) or back it up.
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
+
+# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
+# LM3S parts don't support RTCK
+#
+# NOTE: this may be increased by a reset-init handler, after it
+# configures and enables the PLL.  Or you might need to decrease
+# this, if you're using a slower clock.
+adapter speed 500
+
+source [find mem_helper.tcl]
+
+proc reset_peripherals {family} {
+
+	source [find chip/ti/lm3s/lm3s.tcl]
+
+	echo "Resetting Core Peripherals"
+
+	# Disable the PLL and the system clock divider (nop if disabled)
+	mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
+	mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
+
+	# RCC and RCC2 to their reset values
+	mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]
+	mww $SYSCTL_RCC2 0x07806810
+	mww $SYSCTL_RCC 0x078e3ad1
+
+	# Reset the deep sleep clock configuration register
+	mww $SYSCTL_DSLPCLKCFG 0x07800000
+
+	# Reset the clock gating registers
+	mww $SYSCTL_RCGC0 0x00000040
+	mww $SYSCTL_RCGC1 0
+	mww $SYSCTL_RCGC2 0
+	mww $SYSCTL_SCGC0 0x00000040
+	mww $SYSCTL_SCGC1 0
+	mww $SYSCTL_SCGC2 0
+	mww $SYSCTL_DCGC0 0x00000040
+	mww $SYSCTL_DCGC1 0
+	mww $SYSCTL_DCGC2 0
+
+	# Reset the remaining SysCtl registers
+	mww $SYSCTL_PBORCTL 0
+	mww $SYSCTL_IMC 0
+	mww $SYSCTL_GPIOHBCTL 0
+	mww $SYSCTL_MOSCCTL 0
+	mww $SYSCTL_PIOSCCAL 0
+	mww $SYSCTL_I2SMCLKCFG 0
+
+	# Reset the peripherals
+	mww $SYSCTL_SRCR0 0xffffffff
+	mww $SYSCTL_SRCR1 0xffffffff
+	mww $SYSCTL_SRCR2 0xffffffff
+	mww $SYSCTL_SRCR0 0
+	mww $SYSCTL_SRCR1 0
+	mww $SYSCTL_SRCR2 0
+
+	# Clear any pending SysCtl interrupts
+	mww $SYSCTL_MISC 0xffffffff
+
+	# Wait for any pending flash operations to complete
+	while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }
+	while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }
+
+	# Reset the flash controller registers
+	mww $FLASH_FMA 0
+	mww $FLASH_FCIM 0
+	mww $FLASH_FCMISC 0xffffffff
+	mww $FLASH_FWBVAL 0
+}
+
+$_TARGETNAME configure -event reset-start {
+	adapter speed 500
+
+	#
+	# When nRST is asserted on most Stellaris devices, it clears some of
+	# the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
+	# and OpenOCD depends on those TRMs.  So we won't use SRST on those
+	# chips.  (Only power-on reset should affect debug state, beyond a
+	# few specified bits; not the chip's nRST input, wired to SRST.)
+	#
+	# REVISIT current errata specs don't seem to cover this issue.
+	# Do we have more details than this email?
+	#   https://lists.berlios.de/pipermail
+	#	/openocd-development/2008-August/003065.html
+	#
+
+	global _DEVICECLASS
+
+	if {$_DEVICECLASS != 0xff} {
+	   set device_class $_DEVICECLASS
+	} else {
+	   set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]
+	}
+
+	if {$device_class == 0 || $device_class == 1 ||
+		$device_class == 3 || $device_class == 5 || $device_class == 0xa} {
+		if {![using_hla]} {
+		   # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
+		   cortex_m reset_config sysresetreq
+		}
+	} else {
+		if {![using_hla]} {
+		   # Tempest and Firestorm default to using NVIC VECTRESET
+		   # peripherals will need resetting manually, see proc reset_peripherals
+		   cortex_m reset_config vectreset
+		}
+		# reset peripherals, based on code in
+		# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
+		reset_peripherals $device_class
+	}
+}
+
+# flash configuration ... autodetects sizes, autoprobed
+flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32c0x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32c0x.cfg
new file mode 100644
index 0000000..d015120
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32c0x.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32c0x family
+#
+# stm32c0 devices support SWD transports only.
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32c0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 6kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1800
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # SWD IDCODE (single drop, arm)
+   set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable DBGMCU clock
+	# RCC_APB1ENR |= DBGMCUEN
+	mmw 0x4002103C 0x08000000 0
+
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f0x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f0x.cfg
new file mode 100644
index 0000000..5b8954e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f0x.cfg
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f0x family
+
+#
+# stm32 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+	set _FLASH_SIZE $FLASH_SIZE
+} else {
+	# autodetect size
+	set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0091
+  # Section 29.5.3
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32f0x_default_reset_start {} {
+	# Reset clock is HSI (8 MHz)
+	adapter speed 1000
+}
+
+proc stm32f0x_default_examine_end {} {
+	# Enable debug during low power modes (uses more power)
+	mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+
+	# Stop watchdog counters during halt
+	mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f0x_default_reset_init {} {
+	# Configure PLL to boost clock to HSI x 6 (48 MHz)
+	mww 0x40021004 0x00100000   ;# RCC_CFGR = PLLMUL[2]
+	mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
+	mww 0x40022000 0x00000011   ;# FLASH_ACR = PRFTBE | LATENCY[0]
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+	# Boost JTAG frequency
+	adapter speed 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f1x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f1x.cfg
new file mode 100644
index 0000000..53e81a5
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f1x.cfg
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f1x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f1x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB (as found on some STM32F100s)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0008 Section 26.6.3
+      set _CPUTAPID 0x3ba00477
+   } {
+      # this is the SW-DP tap id not the jtag tap id
+      set _CPUTAPID 0x1ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000307 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f2x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f2x.cfg
new file mode 100644
index 0000000..f475826
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f2x.cfg
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f2x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f2x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0033
+      # Section 32.6.3 - corresponds to Cortex-M3 r2p0
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f3x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f3x.cfg
new file mode 100644
index 0000000..aa978d9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f3x.cfg
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f3x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f3x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+   set _FLASH_SIZE $FLASH_SIZE
+} else {
+   # autodetect size
+   set _FLASH_SIZE 0
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0316
+      # Section 29.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32f3x_default_reset_start {} {
+	# Reset clock is HSI (8 MHz)
+	adapter speed 1000
+}
+
+proc stm32f3x_default_examine_end {} {
+	# Enable debug during low power modes (uses more power)
+	mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+
+	# Stop watchdog counters during halt
+	mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f3x_default_reset_init {} {
+	# Configure PLL to boost clock to HSI x 8 (64 MHz)
+	mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+	mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
+	mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+	# Boost JTAG frequency
+	adapter speed 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xe0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f4x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f4x.cfg
new file mode 100644
index 0000000..35d8275
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f4x.cfg
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f4x family
+
+#
+# stm32f4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 32kB (Available RAM in smallest device STM32F410)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0090
+      # Section 38.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
+	targets $_chipname.cpu
+
+	if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+		switch [$_chipname.tpiu cget -port-width] {
+			1 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
+				mmw 0xE0042004 0x00000060 0x000000c0
+				mmw 0x40021020 0x00000000 0x0000ff00
+				mmw 0x40021000 0x000000a0 0x000000f0
+				mmw 0x40021008 0x000000f0 0x00000000
+			  }
+			2 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
+				mmw 0xE0042004 0x000000a0 0x000000c0
+				mmw 0x40021020 0x00000000 0x000fff00
+				mmw 0x40021000 0x000002a0 0x000003f0
+				mmw 0x40021008 0x000003f0 0x00000000
+			  }
+			4 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
+				mmw 0xE0042004 0x000000e0 0x000000c0
+				mmw 0x40021020 0x00000000 0x0fffff00
+				mmw 0x40021000 0x00002aa0 0x00003ff0
+				mmw 0x40021008 0x00003ff0 0x00000000
+			  }
+		}
+	} else {
+		# Set TRACE_IOEN; TRACE_MODE to async
+		mmw 0xE0042004 0x00000020 0x000000c0
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
+
+$_TARGETNAME configure -event reset-init {
+	# Configure PLL to boost clock to HSI x 4 (64 MHz)
+	mww 0x40023804 0x08012008   ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
+	mww 0x40023C00 0x00000102   ;# FLASH_ACR = PRFTBE | 2(Latency)
+	mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
+	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
+
+	# Boost JTAG frequency
+	adapter speed 8000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reduce speed since CPU speed will slow down to 16MHz with the reset
+	adapter speed 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f7x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f7x.cfg
new file mode 100644
index 0000000..3782b9a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32f7x.cfg
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32f7x family
+
+#
+# stm32f7 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f7x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 128kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x20000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0385
+      # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
+      set _CPUTAPID 0x5ba00477
+   } {
+      set _CPUTAPID 0x5ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
+
+# On the STM32F7, the Flash is mapped at address 0x08000000 via the AXI and
+# also address 0x00200000 via the ITCM. The former mapping is read-write in
+# hardware, while the latter is read-only. By presenting an alias, we
+# accomplish two things:
+# (1) We allow writing at 0x00200000 (because the alias acts identically to the
+#     original bank), which allows code intended to run from that address to
+#     also be linked for loading at that address, simplifying linking.
+# (2) We allow the proper memory map to be delivered to GDB, which will cause
+#     it to use hardware breakpoints at the 0x00200000 mapping (correctly
+#     identifying it as Flash), which it would otherwise not do. Configuring
+#     the Flash via ITCM alias as virtual
+flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+# Use hardware reset.
+#
+# This target is compatible with connect_assert_srst, which may be set in a
+# board file.
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
+
+$_TARGETNAME configure -event reset-init {
+	# If the HSE was previously enabled and the external clock source
+	# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
+	# properly switched back to HSI. This situation persists even over a system
+	# reset, including a pin reset via SRST. However, activating the clock
+	# security system will detect the problem and clear HSERDY to 0, which in
+	# turn allows the PLL to switch back to HSI properly. Since we just came
+	# out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
+	# have happened; in that case, activate the clock security system to clear
+	# HSERDY.
+	if {[mrw 0x40023800] & 0x00020000} {
+		mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
+		sleep 10                    ;# Wait for CSS to fire, if it wants to
+		mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
+		mww 0x4002380C 0x00800000   ;# RCC_CIR = CSSC
+		sleep 1                     ;# Wait for CSSF to clear
+	}
+
+	# If the clock security system fired, it will pend an NMI. A pending NMI
+	# will cause a bad time for any subsequent executing code, such as a
+	# programming algorithm.
+	if {[mrw 0xE000ED04] & 0x80000000} {
+		# ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be
+		# cleared by any normal means (such as ICSR or NVIC). It can only be
+		# cleared by entering the NMI handler or by resetting the processor.
+		echo "[target current]: Clock security system generated NMI. Clearing."
+
+		# Keep the old DEMCR value.
+		set old [mrw 0xE000EDFC]
+
+		# Enable vector catch on reset.
+		mww 0xE000EDFC 0x01000001
+
+		# Issue local reset via AIRCR.
+		mww 0xE000ED0C 0x05FA0001
+
+		# Restore old DEMCR value.
+		mww 0xE000EDFC $old
+	}
+
+	# Configure PLL to boost clock to HSI x 10 (160 MHz)
+	mww 0x40023804 0x08002808   ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
+	mww 0x40023C00 0x00000107   ;# FLASH_ACR = PRFTBE | 7(Latency)
+	mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
+	sleep 10                    ;# Wait for PLL to lock
+	mww 0x40023808 0x00009400   ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
+	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
+
+	# Boost SWD frequency
+	# Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
+	# suffers from DAP WAITs
+	if {[using_jtag]} {
+		[[target current] cget -dap] memaccess 16
+	} {
+		adapter speed 8000
+	}
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reduce speed since CPU speed will slow down to 16MHz with the reset
+	adapter speed 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32g0x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32g0x.cfg
new file mode 100644
index 0000000..b6d9a22
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32g0x.cfg
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32g0x family
+
+#
+# stm32g0 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	# Section 37.5.5 - corresponds to Cortex-M0+
+	set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc stm32g0x_default_reset_start {} {
+	# Reset clock is HSI16 (16 MHz)
+	adapter speed 2000
+}
+
+proc stm32g0x_default_examine_end {} {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
+
+proc stm32g0x_default_reset_init {} {
+	# Increase clock to 64 Mhz
+	mmw 0x40022000 0x00000002 0x00000005	;# FLASH_ACR: Latency = 2
+	mww 0x4002100C 0x30000802				;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
+	mmw 0x40021000 0x01000000 0x00000000	;# RCC_CR |= PLLON
+	mmw 0x40021008 0x00000002 0x00000005	;# RCC_CFGR: SW=PLLRCLK
+
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32g4x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32g4x.cfg
new file mode 100644
index 0000000..39ed1e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32g4x.cfg
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32g4x family
+
+#
+# stm32g4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest current target has 32kB ram, use 16kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		# See STM Document RM0440
+		# Section 46.6.3 - corresponds to Cortex-M4 r0p1
+		set _CPUTAPID 0x4ba00477
+	} {
+		set _CPUTAPID 0x2ba01477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+	set a [llength [flash list]]
+	set _QSPINAME $_CHIPNAME.qspi
+	flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with HSION | HSIRDY.
+	# Use HSI 16 MHz clock, compliant even with VOS == 2.
+	# 1 WS compliant with VOS == 2 and 16 MHz.
+	mmw 0x40022000 0x00000001 0x0000000E	;# FLASH_ACR: Latency = 1
+	mmw 0x40021000 0x00000100 0x00000000	;# RCC_CR |= HSION
+	mmw 0x40021008 0x00000001 0x00000002	;# RCC_CFGR: SW=HSI16
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is HSI (16 MHz)
+	adapter speed 2000
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32h7x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32h7x.cfg
new file mode 100644
index 0000000..5aae938
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32h7x.cfg
@@ -0,0 +1,308 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32h7x family
+
+#
+# stm32h7 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32h7x
+}
+
+if { [info exists DUAL_BANK] } {
+	set $_CHIPNAME.DUAL_BANK $DUAL_BANK
+	unset DUAL_BANK
+} else {
+	set $_CHIPNAME.DUAL_BANK 0
+}
+
+if { [info exists DUAL_CORE] } {
+	set $_CHIPNAME.DUAL_CORE $DUAL_CORE
+	unset DUAL_CORE
+} else {
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
+	echo "Warning : hla does not support multicore debugging"
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+if { [info exists USE_CTI] } {
+	set $_CHIPNAME.USE_CTI $USE_CTI
+	unset USE_CTI
+} else {
+	set $_CHIPNAME.USE_CTI 0
+}
+
+# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
+if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
+	echo "Warning : could not use CTI with a single core device, CTI is disabled"
+	set $_CHIPNAME.USE_CTI 0
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+	  set _CPUTAPID 0x6ba00477
+   } {
+      set _CPUTAPID 0x6ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+if {![using_hla]} {
+	# STM32H7 provides an APB-AP at access port 2, which allows the access to
+	# the debug and trace features on the system APB System Debug Bus (APB-D).
+	target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+	swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
+	tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
+}
+
+target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
+
+$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+
+if {[set $_CHIPNAME.DUAL_BANK]} {
+	flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
+
+	$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+	flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+
+	if {[set $_CHIPNAME.DUAL_BANK]} {
+		flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
+	}
+}
+
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+} else {
+   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+      set a [llength [flash list]]
+      set _OCTOSPINAME1 $_CHIPNAME.octospi1
+      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+   }
+   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+      set b [llength [flash list]]
+      set _OCTOSPINAME2 $_CHIPNAME.octospi2
+      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
+   }
+}
+
+# Clock after reset is HSI at 64 MHz, no need of PLL
+adapter speed 1800
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+# use hardware reset
+#
+# The STM32H7 does not support connect_assert_srst mode because the AXI is
+# unavailable while SRST is asserted, and that is used to access the DBGMCU
+# component at 0x5C001000 in the examine-end event handler.
+#
+# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
+# of the default AP0, and that works with SRST asserted; however, nonzero AP
+# usage does not work with HLA, so is not done by default. That change could be
+# made in a local configuration file if connect_assert_srst mode is needed for
+# a specific application and a non-HLA adapter is in use.
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+	$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
+
+	if {[set $_CHIPNAME.DUAL_CORE]} {
+		$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+	}
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
+}
+
+$_CHIPNAME.cpu0 configure -event examine-end {
+	# Enable D3 and D1 DBG clocks
+	# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
+	stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
+
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
+	stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
+	stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB3FZ1 |= WWDG1
+	stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
+	# DBGMCU_APB1LFZ1 |= WWDG2
+	stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
+	# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
+	stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
+
+	# Enable clock for tracing
+	# DBGMCU_CR |= TRACECLKEN
+	stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
+
+	# RM0399 (id 0x450) M7+M4 with SWO Funnel
+	# RM0433 (id 0x450) M7 with SWO Funnel
+	# RM0455 (id 0x480) M7 without SWO Funnel
+	# RM0468 (id 0x483) M7 without SWO Funnel
+	# Enable CM7 and CM4 slave ports in SWO trace Funnel
+	# Works ok also on devices single core and without SWO funnel
+	# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
+	# SWTF_CTRL |= ENS0 | ENS1
+	stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	# Clock after reset is HSI at 64 MHz, no need of PLL
+	adapter speed 4000
+}
+
+# get _CHIPNAME from current target
+proc stm32h7x_get_chipname {} {
+	set t [target current]
+	set sep [string last "." $t]
+	if {$sep == -1} {
+		return $t
+	}
+	return [string range $t 0 [expr {$sep - 1}]]
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	$_CHIPNAME.cpu1 configure -event examine-end {
+		set _CHIPNAME [stm32h7x_get_chipname]
+		global $_CHIPNAME.USE_CTI
+
+		# Stop watchdog counters during halt
+		# DBGMCU_APB3FZ2 |= WWDG1
+		stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
+		# DBGMCU_APB1LFZ2 |= WWDG2
+		stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
+		# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
+		stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
+
+		if {[set $_CHIPNAME.USE_CTI]} {
+			stm32h7x_cti_start
+		}
+	}
+}
+
+# like mrw, but with target selection
+proc stm32h7x_mrw {used_target reg} {
+	return [$used_target read_memory $reg 32 1]
+}
+
+# like mmw, but with target selection
+proc stm32h7x_mmw {used_target reg setbits clearbits} {
+	set old [stm32h7x_mrw $used_target $reg]
+	set new [expr {($old & ~$clearbits) | $setbits}]
+	$used_target mww $reg $new
+}
+
+# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
+# this procedure will use the mem_ap on AP2 whenever possible
+proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
+	# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
+	if {![using_hla]} {
+		set _CHIPNAME [stm32h7x_get_chipname]
+		set used_target $_CHIPNAME.ap2
+		set reg_addr [expr {0xE00E1000 + $reg_offset}]
+	} {
+		set used_target [target current]
+		set reg_addr [expr {0x5C001000 + $reg_offset}]
+	}
+
+	stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
+}
+
+if {[set $_CHIPNAME.USE_CTI]} {
+	# create CTI instances for both cores
+	cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
+	cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
+
+	$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
+
+	$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+
+	proc stm32h7x_cti_start {} {
+		set _CHIPNAME [stm32h7x_get_chipname]
+
+		# Configure Cores' CTIs to halt each other
+		# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
+		$_CHIPNAME.cti0 write INEN0 0x1
+		$_CHIPNAME.cti0 write OUTEN0 0x1
+		$_CHIPNAME.cti1 write INEN0 0x1
+		$_CHIPNAME.cti1 write OUTEN0 0x1
+
+		# enable CTIs
+		$_CHIPNAME.cti0 enable on
+		$_CHIPNAME.cti1 enable on
+	}
+
+	proc stm32h7x_cti_stop {} {
+		set _CHIPNAME [stm32h7x_get_chipname]
+
+		$_CHIPNAME.cti0 enable off
+		$_CHIPNAME.cti1 enable off
+	}
+
+	proc stm32h7x_cti_prepare_restart_all {} {
+		stm32h7x_cti_prepare_restart cti0
+		stm32h7x_cti_prepare_restart cti1
+	}
+
+	proc stm32h7x_cti_prepare_restart {cti} {
+		set _CHIPNAME [stm32h7x_get_chipname]
+
+		# Acknowlodge EDBGRQ at TRIGOUT0
+		$_CHIPNAME.$cti write INACK 0x01
+		$_CHIPNAME.$cti write INACK 0x00
+	}
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32h7x_dual_bank.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32h7x_dual_bank.cfg
new file mode 100644
index 0000000..41a4773
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32h7x_dual_bank.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32h7x family (dual flash bank)
+
+# STM32H7xxxI 2Mo have a dual bank flash.
+set DUAL_BANK 1
+
+source [find target/stm32h7x.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l0.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l0.cfg
new file mode 100644
index 0000000..b4bdb18
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l0.cfg
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# M0+ devices only have SW-DP, but swj-dp code works, just don't
+# set any jtag related features
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l0
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB (max ram on smallest part)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+# JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
+adapter speed 300
+
+adapter srst delay 100
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    # Arm, m0+, non-multidrop.
+    # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
+    set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32l0_enable_HSI16 {} {
+	# Enable HSI16 as clock source
+	echo "STM32L0: Enabling HSI16"
+
+	# Set HSI16ON in RCC_CR (leave MSI enabled)
+    mmw 0x40021000 0x00000101 0
+
+	# Set HSI16 as SYSCLK (RCC_CFGR)
+	mmw 0x4002100c 0x00000001 0
+
+	# Wait until System clock switches to HSI16
+	while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
+
+	# Increase speed
+	adapter speed 2500
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32l0_enable_HSI16
+}
+
+$_TARGETNAME configure -event reset-start {
+	adapter speed 300
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0x40015804 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l0_dual_bank.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l0_dual_bank.cfg
new file mode 100644
index 0000000..ff3cb90
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l0_dual_bank.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/stm32l0.cfg]
+
+# Add the second flash bank.
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l1.cfg
new file mode 100644
index 0000000..53d9076
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l1.cfg
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# stm32l1 devices support both JTAG and SWD transports.
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l1
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 10kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x2800
+}
+
+# JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
+adapter speed 300
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0038
+      # Section 30.6.3 - corresponds to Cortex-M3 r2p0
+      set _CPUTAPID 0x4ba00477
+   } else {
+      # SWD IDCODE (single drop, arm)
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32l_enable_HSI {} {
+	# Enable HSI as clock source
+	echo "STM32L: Enabling HSI"
+
+	# Set HSION in RCC_CR
+	mmw 0x40023800 0x00000101 0
+
+	# Set HSI as SYSCLK
+	mmw 0x40023808 0x00000001 0
+
+	# Increase JTAG speed
+	adapter speed 2000
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32l_enable_HSI
+}
+
+$_TARGETNAME configure -event reset-start {
+	adapter speed 300
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l1x_dual_bank.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l1x_dual_bank.cfg
new file mode 100644
index 0000000..deefdb4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l1x_dual_bank.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/stm32l1.cfg]
+
+# The stm32l1x 384kb have a dual bank flash.
+# Let's add a definition for the second bank here.
+
+# Add the second flash bank.
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l4x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l4x.cfg
new file mode 100644
index 0000000..9a69673
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l4x.cfg
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32l4x family
+
+#
+# stm32l4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 40kB (Available RAM in smallest device STM32L412)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0xa000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0351
+      # Section 44.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+} else {
+   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+      set a [llength [flash list]]
+      set _OCTOSPINAME1 $_CHIPNAME.octospi1
+      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+   }
+   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+      set b [llength [flash list]]
+      set _OCTOSPINAME2 $_CHIPNAME.octospi2
+      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400
+   }
+}
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
+	targets $_chipname.cpu
+
+	if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+		switch [$_chipname.tpiu cget -port-width] {
+			1 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
+				mmw 0xE0042004 0x00000060 0x000000c0
+				mmw 0x48001020 0x00000000 0x0000ff00
+				mmw 0x48001000 0x000000a0 0x000000f0
+				mmw 0x48001008 0x000000f0 0x00000000
+			  }
+			2 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
+				mmw 0xE0042004 0x000000a0 0x000000c0
+				mmw 0x48001020 0x00000000 0x000fff00
+				mmw 0x48001000 0x000002a0 0x000003f0
+				mmw 0x48001008 0x000003f0 0x00000000
+			  }
+			4 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
+				mmw 0xE0042004 0x000000e0 0x000000c0
+				mmw 0x48001020 0x00000000 0x0fffff00
+				mmw 0x48001000 0x00002aa0 0x00003ff0
+				mmw 0x48001008 0x00003ff0 0x00000000
+			  }
+		}
+	} else {
+		# Set TRACE_IOEN; TRACE_MODE to async
+		mmw 0xE0042004 0x00000020 0x000000c0
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
+	# Use MSI 24 MHz clock, compliant even with VOS == 2.
+	# 3 WS compliant with VOS == 2 and 24 MHz.
+	mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
+	mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
+
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 500
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l5x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l5x.cfg
new file mode 100644
index 0000000..c43b699
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32l5x.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32l5x family
+# stm32l5x devices support both JTAG and SWD transports.
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32l5x
+}
+
+source [find target/stm32x5x_common.cfg]
+
+proc stm32l5x_clock_config {} {
+	set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
+	# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
+	# RCC_APB1ENR1 = PWREN
+	mww [expr {0x40021058 + $offset}] 0x10000000
+	# delay for register clock enable (read back reg)
+	mrw [expr {0x40021058 + $offset}]
+	# PWR_CR1 : VOS Range 0
+	mww [expr {0x40007000 + $offset}] 0
+	# while (PWR_SR2 & VOSF)
+	while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}
+	# FLASH_ACR : 5 WS for 110 MHz HCLK
+	mww 0x40022000 0x00000005
+	# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
+	# fVCO = 4 x 55 /1 = 220
+	# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
+	mww [expr {0x4002100C + $offset}] 0x01003711
+	# RCC_CR |= PLLON
+	mmw [expr {0x40021000 + $offset}] 0x01000000 0
+	# while !(RCC_CR & PLLRDY)
+	while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}
+	# RCC_CFGR |= SW_PLL
+	mmw [expr {0x40021008 + $offset}] 0x00000003 0
+	# while ((RCC_CFGR & SWS) != PLL)
+	while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32l5x_clock_config
+	# Boost JTAG frequency
+	adapter speed 4000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32mp13x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32mp13x.cfg
new file mode 100644
index 0000000..bcf25c9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32mp13x.cfg
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP13x (Single Cortex-A7)
+# http://www.st.com/stm32mp1
+
+# HLA does not support custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp13x_dk.cfg\"."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp13x
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x06501041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# NOTE: keep ap-num and dbgbase to speed-up examine after reset
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+
+$_CHIPNAME.cpu cortex_a maskisr on
+$_CHIPNAME.cpu cortex_a dacrfixup on
+
+# interface does not work while srst is asserted
+# this is target specific, valid for every board
+# srst resets the debug unit, behavior equivalent to "srst_pulls_trst"
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# bootrom has an internal timeout of 1 second for detecting the boot flash.
+# wait at least 1 second to guarantee we are out of bootrom
+adapter srst delay 1100
+
+add_help_text axi_secure "Set secure mode for following AXI accesses"
+proc axi_secure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x10006000
+}
+
+add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
+proc axi_nsecure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x30006000
+}
+
+axi_secure
+
+proc dbgmcu_enable_debug {} {
+	# keep clock enabled in low-power
+	## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
+	# freeze watchdog 1 and 2 on core halted
+	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
+}
+
+proc toggle_cpu_dbg_claim0 {} {
+	# toggle CPU0 DBG_CLAIM[0]
+	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
+	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+}
+
+# FIXME: most of handlers below will be removed once reset framework get merged
+$_CHIPNAME.ap1 configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+	catch {dap init}
+	catch {$::_CHIPNAME.dap apid 1}
+}
+$_CHIPNAME.cpu configure -event reset-deassert-pre  {$::_CHIPNAME.cpu arp_examine}
+$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
+$_CHIPNAME.ap1 configure -event examine-start       {dap init}
+$_CHIPNAME.ap1 configure -event examine-end         {dbgmcu_enable_debug}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32mp15x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32mp15x.cfg
new file mode 100644
index 0000000..bcdda73
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32mp15x.cfg
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
+# http://www.st.com/stm32mp1
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp15x
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x06500041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
+# so defer-examine it until the reset framework get merged
+# NOTE: keep ap-num and dbgbase to speed-up examine after reset
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+
+targets $_CHIPNAME.cpu0
+
+target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
+$_CHIPNAME.cpu0 cortex_a maskisr on
+$_CHIPNAME.cpu1 cortex_a maskisr on
+$_CHIPNAME.cpu0 cortex_a dacrfixup on
+$_CHIPNAME.cpu1 cortex_a dacrfixup on
+
+cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000
+cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000
+cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
+cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
+
+# interface does not work while srst is asserted
+# this is target specific, valid for every board
+# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
+# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
+# debug unit, behavior equivalent to "srst_pulls_trst"
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# bootrom has an internal timeout of 1 second for detecting the boot flash.
+# wait at least 1 second to guarantee we are out of bootrom
+adapter srst delay 1100
+
+add_help_text axi_secure "Set secure mode for following AXI accesses"
+proc axi_secure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x10006000
+}
+
+add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
+proc axi_nsecure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x30006000
+}
+
+axi_secure
+
+proc dbgmcu_enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
+	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+	# freeze watchdog 1 and 2 on cores halted
+	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
+}
+
+proc toggle_cpu0_dbg_claim0 {} {
+	# toggle CPU0 DBG_CLAIM[0]
+	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
+	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+}
+
+proc detect_cpu1 {} {
+	set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
+	set dual_core [expr {$cpu1_prsr & 1}]
+	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
+}
+
+proc rcc_enable_traceclk {} {
+	$::_CHIPNAME.ap2 mww 0x5000080c 0x301
+}
+
+# FIXME: most of handler below will be removed once reset framework get merged
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
+$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
+$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
+$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
+$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
+$_CHIPNAME.ap1  configure -event examine-start       {dap init}
+$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
+$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
+$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32u5x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32u5x.cfg
new file mode 100644
index 0000000..44b51e2
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32u5x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32u5x family
+# stm32u5x devices support both JTAG and SWD transports.
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32u5x
+}
+
+source [find target/stm32x5x_common.cfg]
+
+proc stm32u5x_clock_config {} {
+	set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
+	# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
+
+	# Enable voltage range 1 for frequency above 100 Mhz
+	# RCC_AHB3ENR = PWREN
+	mww [expr {0x46020C94 + $offset}] 0x00000004
+	# delay for register clock enable (read back reg)
+	mrw [expr {0x46020C94 + $offset}]
+	# PWR_VOSR : VOS Range 1
+	mmw [expr {0x4602080C + $offset}] 0x00030000 0
+	# while !(PWR_VOSR & VOSRDY)
+	while {!([mrw [expr {0x4602080C + $offset}]] & 0x00008000)} {}
+	# FLASH_ACR : 4 WS for 160 MHz HCLK
+	mww [expr {0x40022000 + $offset}] 0x00000004
+	# RCC_PLL1CFGR => PLL1MBOOST=0, PLL1M=0=/1, PLL1FRACEN=0, PLL1SRC=MSI 4MHz
+	#                 PLL1REN=1, PLL1RGE => VCOInputRange=PLLInputRange_4_8
+	mww [expr {0x46020C28 + $offset}] 0x00040009
+	# Enable EPOD Booster
+	mmw [expr {0x4602080C + $offset}] 0x00040000 0
+	# while !(PWR_VOSR & BOOSTRDY)
+	while {!([mrw [expr {0x4602080C + $offset}]] & 0x00004000)} {}
+	# RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80
+	# fVCO = 4 x 80 /1 = 320
+	# SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz
+	mww [expr {0x46020C34 + $offset}] 0x0101024F
+	# RCC_CR |= PLL1ON
+	mmw [expr {0x46020C00 + $offset}] 0x01000000 0
+	# while !(RCC_CR & PLL1RDY)
+	while {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {}
+	# RCC_CFGR1 |= SW_PLL
+	mmw [expr {0x46020C1C + $offset}] 0x00000003 0
+	# while ((RCC_CFGR1 & SWS) != PLL)
+	while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32u5x_clock_config
+	# Boost JTAG frequency
+	adapter speed 4000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32w108xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32w108xx.cfg
new file mode 100644
index 0000000..e6a62e8
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32w108xx.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Target configuration for the ST STM32W108xx chips
+#
+# Processor: ARM Cortex-M3
+# Date:      2013-06-09
+# Author:    Giuseppe Barba 
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] == 0 } {
+   set _CHIPNAME stm32w108
+} else {
+   set _CHIPNAME $CHIPNAME
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 8kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x2000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x3ba00477
+   } {
+      set _CPUTAPID 0x1ba01477
+   }
+}
+
+set _ENDIAN little
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+ if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID
+ } else {
+   set _BSTAPID_1 0x169a862b
+   set _BSTAPID_2 0x269a862b
+   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
+		-expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2
+ }
+}
+#
+# Set Target
+#
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+
+# Use the flash driver from the EM357
+set _FLASHNAME $_CHIPNAME.flash
+
+# 64k (0x10000) of flash
+flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32wbax.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32wbax.cfg
new file mode 100644
index 0000000..1299407
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32wbax.cfg
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32wbax family
+
+#
+# stm32wba devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME stm32wbax
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+    set _WORKAREASIZE $WORKAREASIZE
+} else {
+    set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    if { [using_jtag] } {
+        set _CPUTAPID 0x6ba00477
+    } else {
+        # SWD IDCODE (single drop, arm)
+        set _CPUTAPID 0x6ba02477
+    }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+    jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+    jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+    # CPU comes out of reset with HSION | HSIRDY.
+    # Use HSI 16 MHz clock, compliant even with VOS == 2.
+    # 1 WS compliant with VOS == 2 and 16 MHz.
+    mmw 0x40022000 0x00000001 0x0000000E	;# FLASH_ACR: Latency = 1
+    mmw 0x56020C00 0x00000100 0x00000000	;# RCC_CR |= HSION
+    mmw 0x56020C1C 0x00000000 0x00000002	;# RCC_CFGR1: SW=HSI16
+    # Boost JTAG frequency
+    adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+    # Reset clock is HSI (16 MHz)
+    adapter speed 2000
+}
+
+$_TARGETNAME configure -event examine-end {
+    # Enable debug during low power modes (uses more power)
+    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+    mmw 0xE0042004 0x00000006 0
+
+    # Stop watchdog counters during halt
+    # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
+    mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+    targets $_targetname
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32wbx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32wbx.cfg
new file mode 100644
index 0000000..737b144
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32wbx.cfg
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32wbx family
+
+#
+# stm32wb devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32wbx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x6ba00477
+   } else {
+      # SWD IDCODE (single drop, arm)
+      set _CPUTAPID 0x6ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+    # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+    # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+    # 2 WS compliant with VOS=Range1 and 24 MHz.
+    mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTBE | 2(Latency)
+    mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+    # Boost JTAG frequency
+    adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+    # Reset clock is MSI (4 MHz)
+    adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+    # Enable debug during low power modes (uses more power)
+    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+    mmw 0xE0042004 0x00000007 0
+
+    # Stop watchdog counters during halt
+    # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+    mmw 0xE004203C 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+    targets $_targetname
+
+    # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+    # change this value accordingly to configure trace pins
+    # assignment
+    mmw 0xE0042004 0x00000020 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32wlx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32wlx.cfg
new file mode 100644
index 0000000..39c897f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32wlx.cfg
@@ -0,0 +1,185 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32wlx family
+
+#
+# stm32wl devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32wlx
+}
+
+if { [info exists DUAL_CORE] } {
+	set $_CHIPNAME.DUAL_CORE $DUAL_CORE
+	unset DUAL_CORE
+} else {
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+if { [info exists WKUP_CM0P] } {
+	set $_CHIPNAME.WKUP_CM0P $WKUP_CM0P
+	unset WKUP_CM0P
+} else {
+	set $_CHIPNAME.WKUP_CM0P 0
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
+	echo "Warning : hla does not support multicore debugging"
+	set $_CHIPNAME.DUAL_CORE 0
+	set $_CHIPNAME.WKUP_CM0P 0
+}
+
+# setup the Work-area start address and size
+# Work-area is a space in RAM used for flash programming
+
+# Memory map for known devices:
+# STM32WL   x5JC   x5JB   x5J8
+#   FLASH   256    128    64
+#   SRAM1   32     16     0
+#   SRAM2   32     32     20
+
+# By default use 8kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x2000
+}
+
+# Use SRAM2 as work area (some devices do not have SRAM1):
+set WORKAREASTART_CM4   0x20008000
+set WORKAREASTART_CM0P  [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}]
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+target create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+flash bank $_CHIPNAME.otp.cpu0   stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+	# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+	# 2 WS compliant with VOS=Range1 and 24 MHz.
+	mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTEN | 2(Latency)
+	mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+$_CHIPNAME.cpu0 configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 500
+}
+
+$_CHIPNAME.cpu0 configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE004203C 0x00001800 0
+
+	set _CHIPNAME [stm32wlx_get_chipname]
+	global $_CHIPNAME.WKUP_CM0P
+
+	if {[set $_CHIPNAME.WKUP_CM0P]} {
+		stm32wlx_wkup_cm0p
+	}
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+
+	$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+	flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+	flash bank $_CHIPNAME.otp.cpu1   stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1
+
+	if {![using_hla]} {
+		# if srst is not fitted use SYSRESETREQ to
+		# perform a soft reset
+		$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+	}
+
+	proc stm32wlx_wkup_cm0p {} {
+		set _CHIPNAME [stm32wlx_get_chipname]
+
+		# enable CPU2 boot after reset and after wakeup from Stop or Standby mode
+		# PWR_CR4 |= C2BOOT
+		stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0
+	}
+}
+
+# get _CHIPNAME from current target
+proc stm32wlx_get_chipname {} {
+	set t [target current]
+	set sep [string last "." $t]
+	if {$sep == -1} {
+		return $t
+	}
+	return [string range $t 0 [expr {$sep - 1}]]
+}
+
+# like mrw, but with target selection
+proc stm32wlx_mrw {used_target reg} {
+	return [$used_target read_memory $reg 32 1]
+}
+
+# like mmw, but with target selection
+proc stm32wlx_mmw {used_target reg setbits clearbits} {
+	set old [stm32wlx_mrw $used_target $reg]
+	set new [expr {($old & ~$clearbits) | $setbits}]
+	$used_target mww $reg $new
+}
+
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32x5x_common.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32x5x_common.cfg
new file mode 100644
index 0000000..fb3aeb1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32x5x_common.cfg
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common script for stm32l5x and stm32u5x families
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		# STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
+		# STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
+		# Corresponds to Cortex®-M33 JTAG debug port ID code
+		set _CPUTAPID 0x0ba04477
+	} {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x0be12477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+# use non-secure RAM by default
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# create sec/ns flash and otp memories (sizes will be probed)
+flash bank $_CHIPNAME.flash_ns      stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp           stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
+
+# Common knowledge tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://review.openocd.org/3366
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {[using_hla]} {
+	echo "Warn : The selected adapter does not support debugging this device in secure mode"
+} else {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc stm32x5x_is_secure {} {
+	# read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16)
+	set DSCSR [mrw 0xE000EE08]
+	return [expr {($DSCSR & (1 << 16)) != 0}]
+}
+
+proc stm32x5x_ahb_ap_non_secure_access {} {
+	# in HLA mode, non-secure debugging is possible without changing the AP CSW
+	if {![using_hla]} {
+		# SPROT=1=Non Secure access, Priv=1
+		[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
+	}
+}
+
+proc stm32x5x_ahb_ap_secure_access {} {
+	if {![using_hla]} {
+		# SPROT=0=Secure access, Priv=1
+		[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
+	}
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 480
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0xE0044004 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0044008 0x00001800 0
+}
+
+$_TARGETNAME configure -event halted {
+	set secure [stm32x5x_is_secure]
+
+	if {$secure} {
+		set secure_str "Secure"
+		stm32x5x_ahb_ap_secure_access
+	} else {
+		set secure_str "Non-Secure"
+		stm32x5x_ahb_ap_non_secure_access
+	}
+
+	# print the secure state only when it changes
+	set _TARGETNAME [target current]
+	global $_TARGETNAME.secure
+
+	if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
+		echo "CPU in $secure_str state"
+		# update saved security state
+		set $_TARGETNAME.secure $secure
+	}
+}
+
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	set use_secure_workarea 0
+	# check if FLASH_OPTR.TZEN is enabled
+	set FLASH_OPTR [mrw 0x40022040]
+	if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
+		echo "TZEN option bit disabled"
+		stm32x5x_ahb_ap_non_secure_access
+	} else {
+		stm32x5x_ahb_ap_secure_access
+		echo "TZEN option bit enabled"
+
+		# check if FLASH_OPTR.RDP is not Level 0.5
+		if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
+			set use_secure_workarea 1
+		}
+	}
+
+	set _TARGETNAME [target current]
+	set workarea_addr [$_TARGETNAME cget -work-area-phys]
+	echo "workarea_addr $workarea_addr"
+
+	if {$use_secure_workarea} {
+		set workarea_addr [expr {$workarea_addr | 0x10000000}]
+	} else {
+		set workarea_addr [expr {$workarea_addr & ~0x10000000}]
+	}
+
+	$_TARGETNAME configure -work-area-phys $workarea_addr
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
+	# Set TRACE_EN and TRACE_IOEN in DBGMCU_CR
+	# Leave TRACE_MODE untouched (defaults to async).
+	# When using sync change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0044004 0x00000030 0
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32xl.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32xl.cfg
new file mode 100644
index 0000000..ad68f3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm32xl.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32xl family (dual flash bank)
+source [find target/stm32f1x.cfg]
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l.cfg
new file mode 100644
index 0000000..583a2a4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l.cfg
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm8l family
+
+#
+# stm8 devices support SWIM transports only.
+#
+
+transport select swim
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm8l
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists FLASHSTART] } {
+   set _FLASHSTART $FLASHSTART
+} else {
+   set _FLASHSTART 0x8000
+}
+
+if { [info exists FLASHEND] } {
+   set _FLASHEND $FLASHEND
+} else {
+   set _FLASHEND 0xffff
+}
+
+if { [info exists EEPROMSTART] } {
+   set _EEPROMSTART $EEPROMSTART
+} else {
+   set _EEPROMSTART 0x4000
+}
+
+if { [info exists EEPROMEND] } {
+   set _EEPROMEND $EEPROMEND
+} else {
+   set _EEPROMEND 0x43ff
+}
+
+if { [info exists OPTIONSTART] } {
+   set _OPTIONSTART $OPTIONSTART
+} else {
+   set _OPTIONSTART 0x4800
+}
+
+if { [info exists OPTIONEND] } {
+   set _OPTIONEND $OPTIONEND
+} else {
+   set _OPTIONEND 0x487f
+}
+
+if { [info exists BLOCKSIZE] } {
+   set _BLOCKSIZE $BLOCKSIZE
+} else {
+   set _BLOCKSIZE 0x80
+}
+
+swim newtap $_CHIPNAME cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu
+
+$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
+$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND
+$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE
+
+# Uncomment this line to enable interrupts while instruction step
+#$_TARGETNAME configure -enable_step_irq
+
+# Set stm8l type
+$_TARGETNAME configure -enable_stm8l
+
+# Set high speed
+adapter speed 800
+# Set low speed
+#adapter speed 363
+
+reset_config srst_only
+
+#uncomment this line to connect under reset
+#reset_config srst_nogate connect_assert_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l151x2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l151x2.cfg
new file mode 100644
index 0000000..db88c71
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l151x2.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x2
+# Supported Devices:
+# STM8L151C2
+# STM8L151F2
+# STM8L151G2
+# STM8L151K2
+
+# 1kB RAM
+# Start 0x0000
+# End   0x03ff
+set WORKAREASIZE 1024
+
+# 4kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0x8fff
+
+# 256B EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x10ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x487f
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l151x3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l151x3.cfg
new file mode 100644
index 0000000..fe904b4
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l151x3.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x3
+# Supported Devices:
+# STM8L151C3
+# STM8L151F3
+# STM8L151G3
+# STM8L151K3
+
+# 1kB RAM
+# Start 0x0000
+# End   0x03ff
+set WORKAREASIZE 1024
+
+# 8kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0x9fff
+
+# 256B EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x10ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x487f
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l152.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l152.cfg
new file mode 100644
index 0000000..033b826
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l152.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo 'DEPRECATED: choose between stm8l15xx4.cfg, stm8l15xx6.cfg and stm8l15xx8.cfg instead of stm8l152.cfg'
+echo '            using stm8l152.cfg for backwards compatability'
+
+set EEPROMSTART 0x1000
+set EEPROMEND 0x13ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l15xx4.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l15xx4.cfg
new file mode 100644
index 0000000..4438193
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l15xx4.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x4/STM8L152x4
+# Supported Devices:
+# STM8L151C4
+# STM8L151G4
+# STM8L151K4
+# STM8L152C4
+# STM8L152K4
+
+# 2kB RAM
+# Start 0x0000
+# End   0x07ff
+set WORKAREASIZE 2048
+
+# 16kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0xbfff
+
+# 1kB EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x13ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x48ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l15xx6.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l15xx6.cfg
new file mode 100644
index 0000000..5243295
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l15xx6.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x6/STM8L152x6
+# Supported Devices:
+# STM8L151C6
+# STM8L151G6
+# STM8L151K6
+# STM8L151R6
+# STM8L152C6
+# STM8L152K6
+# STM8L152R6
+
+# 2kB RAM
+# Start 0x0000
+# End   0x07ff
+set WORKAREASIZE 2048
+
+# 32kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0xffff
+
+# 1kB EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x13ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x48ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l15xx8.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l15xx8.cfg
new file mode 100644
index 0000000..e354827
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8l15xx8.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x8/STM8L152x8
+# Supported Devices:
+# STM8L151C8
+# STM8L151M8
+# STM8L151R8
+# STM8L152C8
+# STM8L152K8
+# STM8L152M8
+# STM8L152R8
+
+# 4kB RAM
+# Start 0x0000
+# End   0x0fff
+set WORKAREASIZE 4096
+
+# 64kB Flash
+set FLASHSTART  0x08000
+set FLASHEND    0x17fff
+
+# 2kB EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x17ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x48ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s.cfg
new file mode 100644
index 0000000..01e50d0
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s.cfg
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm8s family
+
+#
+# stm8 devices support SWIM transports only.
+#
+
+transport select swim
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm8s
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists FLASHSTART] } {
+   set _FLASHSTART $FLASHSTART
+} else {
+   set _FLASHSTART 0x8000
+}
+
+if { [info exists FLASHEND] } {
+   set _FLASHEND $FLASHEND
+} else {
+   set _FLASHEND 0xffff
+}
+
+if { [info exists EEPROMSTART] } {
+   set _EEPROMSTART $EEPROMSTART
+} else {
+   set _EEPROMSTART 0x4000
+}
+
+if { [info exists EEPROMEND] } {
+   set _EEPROMEND $EEPROMEND
+} else {
+   set _EEPROMEND 0x43ff
+}
+
+if { [info exists OPTIONSTART] } {
+   set _OPTIONSTART $OPTIONSTART
+} else {
+   set _OPTIONSTART 0x4800
+}
+
+if { [info exists OPTIONEND] } {
+   set _OPTIONEND $OPTIONEND
+} else {
+   set _OPTIONEND 0x487f
+}
+
+if { [info exists BLOCKSIZE] } {
+   set _BLOCKSIZE $BLOCKSIZE
+} else {
+   set _BLOCKSIZE 0x80
+}
+
+swim newtap $_CHIPNAME cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu
+
+$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
+$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND
+$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE
+
+# Uncomment this line to enable interrupts while instruction step
+#$_TARGETNAME configure -enable_step_irq
+
+# Set high speed
+adapter speed 800
+# Set low speed
+#adapter speed 363
+
+reset_config srst_only
+
+# uncomment this line to connect under reset
+#reset_config srst_nogate connect_assert_srst
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s003.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s003.cfg
new file mode 100644
index 0000000..60f5c3c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s003.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#config script for STM8S003
+
+set FLASHEND 0x9FFF
+set BLOCKSIZE 0x40
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0x00
+   reset halt
+}
+
+source [find target/stm8s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s103.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s103.cfg
new file mode 100644
index 0000000..41350cb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s103.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#config script for STM8S103
+
+set FLASHEND 0x9FFF
+set EEPROMEND 0x427F
+set OPTIONEND 0x480A
+set BLOCKSIZE 0x40
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0x00
+   reset halt
+}
+
+source [find target/stm8s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s105.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s105.cfg
new file mode 100644
index 0000000..6af491e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/stm8s105.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#config script for STM8S105
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0x00
+   reset halt
+}
+
+source [find target/stm8s.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str710.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str710.cfg
new file mode 100644
index 0000000..ff89717
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str710.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#start slow, speed up after reset
+adapter speed 10
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME str710
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
+$_TARGETNAME configure -event reset-init {
+	adapter speed 6000
+
+# Because the hardware cannot be interrogated for the protection state
+# of sectors, initialize all the sectors to be unprotected. The initial
+# state is reflected by the driver, too.
+	flash protect 0 0 last off
+	flash protect 1 0 last off
+}
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	flash protect 0 0 7 off
+	flash protect 1 0 1 off
+}
+
+$_TARGETNAME configure -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank str7x   0 0  
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 $_TARGETNAME STR71x
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str730.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str730.cfg
new file mode 100644
index 0000000..57681f9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str730.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#STR730 CPU
+
+adapter speed 3000
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME str730
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+#jtag nTRST and nSRST delay
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
+
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
+$_TARGETNAME configure -event reset-init {
+	adapter speed 3000
+
+# Because the hardware cannot be interrogated for the protection state
+# of sectors, initialize all the sectors to be unprotected. The initial
+# state is reflected by the driver, too.
+	flash protect 0 0 last off
+}
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank     
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR73x
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str750.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str750.cfg
new file mode 100644
index 0000000..5af7b74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str750.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#STR750 CPU
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME str750
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4f1f0041
+}
+
+# jtag speed
+adapter speed 10
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+#jtag nTRST and nSRST delay
+adapter srst delay 500
+jtag_ntrst_delay 500
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
+
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
+$_TARGETNAME configure -event reset-init {
+	adapter speed 3000
+
+	init_smi
+# Because the hardware cannot be interrogated for the protection state
+# of sectors, initialize all the sectors to be unprotected. The initial
+# state is reflected by the driver, too.
+	flash protect 0 0 last off
+	flash protect 1 0 last off
+}
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	flash protect 0 0 7 off
+	flash protect 1 0 1 off
+}
+
+$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank     
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x
+
+# Serial NOR on SMI CS0.
+set _FLASHNAME $_CHIPNAME.snor
+flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME
+
+source [find mem_helper.tcl]
+
+proc init_smi {} {
+	mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs
+	mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit
+	mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str912.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str912.cfg
new file mode 100644
index 0000000..3167b40
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/str912.cfg
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for str9
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+adapter speed 16
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+if { [info exists FLASHTAPID] } {
+   set _FLASHTAPID $FLASHTAPID
+} else {
+   set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+   # possible values: 0x1457f041, 0x2457f041
+   # we ignore version in check below
+   set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID -ignore-version
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
+
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	#adapter speed 3000
+
+	# -- Enable 96K RAM
+	# PFQBC enabled / DTCM & AHB wait-states disabled
+	mww 0x5C002034 0x0191
+
+	str9x flash_config 0 4 2 0 0x80000
+	flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+
+#flash bank str9x   0 0  
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 $_TARGETNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/swj-dp.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/swj-dp.tcl
new file mode 100644
index 0000000..f2b233f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/swj-dp.tcl
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# ARM Debug Interface V5 (ADI_V5) utility
+# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
+# SW-DP and JTAG-DP targets don't need to switch based
+# on which transport is active.
+#
+# declare a JTAG or SWD Debug Access Point (DAP)
+# based on the transport in use with this session.
+# You can't access JTAG ops when SWD is active, etc.
+
+# params are currently what "jtag newtap" uses
+# because OpenOCD internals are still strongly biased
+# to JTAG ....  but for SWD, "irlen" etc are ignored,
+# and the internals work differently
+
+# for now, ignore non-JTAG and non-SWD transports
+# (e.g. initial flash programming via SPI or UART)
+
+# split out "chip" and "tag" so we can someday handle
+# them more uniformly irlen too...)
+
+if [catch {transport select}] {
+  echo "Error: unable to select a session transport. Can't continue."
+  shutdown
+}
+
+proc swj_newdap {chip tag args} {
+ if [using_jtag] {
+     eval jtag newtap $chip $tag $args
+ } elseif [using_swd] {
+     eval swd newdap $chip $tag $args
+ } else {
+     echo "Error: transport '[ transport select ]' not supported by swj_newdap"
+     shutdown
+ }
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/swm050.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/swm050.cfg
new file mode 100644
index 0000000..6cc5f6d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/swm050.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Synwit SWM050
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME swm050
+}
+set _CHIPSERIES swm050
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+$_TARGETNAME configure -event reset-init {
+	# Stop the watchdog, just to be safe
+	mww 0x40019000 0x00
+	# Set clock divider value to 1
+	mww 0x400F0000 0x01
+	# Set system clock to 18Mhz
+	mww 0x400F0008 0x00
+}
+
+# SWM050 (Cortex-M0 core) supports SYSRESETREQ
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/test_reset_syntax_error.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/test_reset_syntax_error.cfg
new file mode 100644
index 0000000..7ef5914
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/test_reset_syntax_error.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Test script to check that syntax error in reset
+# script is reported properly.
+
+# at91eb40a target
+
+#jtag scan chain
+set _CHIPNAME syntaxtest
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+
+	syntax error
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/test_syntax_error.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/test_syntax_error.cfg
new file mode 100644
index 0000000..2d5da7f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/test_syntax_error.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This script tests a syntax error in the startup
+# config script
+
+syntax error here
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti-ar7.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti-ar7.cfg
new file mode 100644
index 0000000..28b6cf7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti-ar7.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments AR7 SOC - used in many adsl modems.
+# http://www.linux-mips.org/wiki/AR7
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME ti-ar7
+}
+
+if { [info exists ENDIAN] } {
+    set _ENDIAN $ENDIAN
+} else {
+    set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x0000100f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_CHIPNAME.cpu
+
+# use onboard 4k sram as working area
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti-cjtag.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti-cjtag.cfg
new file mode 100644
index 0000000..97111f1
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti-cjtag.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# A start sequence to change from cJTAG to 4-pin JTAG
+# This is needed for CC2538 and CC26xx to be able to communicate through JTAG
+# Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information.
+proc ti_cjtag_to_4pin_jtag {jrc} {
+	# Bypass
+	runtest 20
+	irscan $jrc 0x3f -endstate RUN/IDLE
+	# Two zero bit scans and a one bit drshift
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+
+	# A two bit drhift and a 9 bit drshift
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRPAUSE
+	pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
+	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
+
+	# Bypass
+	irscan $jrc 0x3f -endstate RUN/IDLE
+
+	# Set ICEPick IDCODE in data register
+	irscan $jrc 0x04 -endstate RUN/IDLE
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_calypso.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_calypso.cfg
new file mode 100644
index 0000000..9083336
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_calypso.cfg
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI Calypso (lite) G2 C035 Digital Base Band chip
+#
+# ARM7TDMIE + DSP subchip (S28C128)
+#
+# 512K SRAM Calypso
+# 256K SRAM Calypso lite
+#
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME calypso
+}
+
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x3100e02f
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+adapter speed 1000
+
+reset_config trst_and_srst
+
+jtag newtap $_CHIPNAME dsp -expected-id 0x00000000 -irlen 8
+jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# target
+
+set _TARGETNAME $_CHIPNAME.arm
+target create $_TARGETNAME arm7tdmi -endian little -chain-position $_TARGETNAME
+
+# workarea
+
+$_TARGETNAME configure -work-area-phys 0x00800000 -work-area-size $_WORKAREASIZE -work-area-backup 1
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+$_TARGETNAME configure -event examine-start {
+	irscan calypso.arm 0x0b -endstate DRPAUSE
+	drscan calypso.arm 2 2 -endstate RUN/IDLE
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc13x0.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc13x0.cfg
new file mode 100644
index 0000000..f1c43a6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc13x0.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC13x0 - ARM Cortex-M3
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc13x0
+set JRC_TAPID 0x0B9BE02F
+set WORKAREASIZE 0x4000
+
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc13x2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc13x2.cfg
new file mode 100644
index 0000000..c850816
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc13x2.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC13x2 - ARM Cortex-M4
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc13x2
+set JRC_TAPID 0x0BB4102F
+set WORKAREASIZE 0x7000
+
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc26x0.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc26x0.cfg
new file mode 100644
index 0000000..b9ccf31
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc26x0.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC26x0 - ARM Cortex-M3
+#
+# http://www.ti.com
+#
+
+source [find target/icepick.cfg]
+source [find target/ti-cjtag.cfg]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cc26x0
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4BA00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+#
+# ICEpick-C (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID 0x0B99A02F
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
+# A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG
+jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
+
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x4000
+}
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
+
+cortex_m reset_config vectreset
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc26x2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc26x2.cfg
new file mode 100644
index 0000000..62c91c3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc26x2.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC26x2 - ARM Cortex-M4
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc26x2
+set JRC_TAPID 0x0BB4102F
+set WORKAREASIZE 0x7000
+
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc26x2x7.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc26x2x7.cfg
new file mode 100644
index 0000000..91c1a80
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc26x2x7.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC26x2 - ARM Cortex-M4
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc26x2x7
+set JRC_TAPID 0x1BB7702F
+set WORKAREASIZE 0x7000
+
+source [find target/ti_cc26x0.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc3220sf.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc3220sf.cfg
new file mode 100644
index 0000000..cf43363
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc3220sf.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC3220SF - ARM Cortex-M4
+#
+# http://www.ti.com/CC3220SF
+#
+
+source [find target/swj-dp.tcl]
+source [find target/icepick.cfg]
+source [find target/ti_cc32xx.cfg]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
+
+#
+# On CC32xx family of devices, sysreqreset is disabled, and vectreset is
+# blocked by the boot loader (stops in a while(1) statement). srst reset can
+# leave the target in a state that prevents debug. The following uses the
+# soft_reset_halt command to reset and halt the target. Then the PC and stack
+# are initialized from internal flash. This allows for a more reliable reset,
+# but with two caveats: it only works for the SF variant that has internal
+# flash, and it only resets the CPU and not any peripherals.
+#
+
+proc ocd_process_reset_inner { MODE } {
+
+	soft_reset_halt
+
+	# Initialize MSP, PSP, and PC from vector table at flash 0x01000800
+	set boot [read_memory 0x01000800 32 2]
+
+	reg msp [lindex $boot 0]
+	reg psp [lindex $boot 0]
+	reg pc [lindex $boot 1]
+
+	if { 0 == [string compare $MODE run ] } {
+		resume
+	}
+
+	cc32xx.cpu invoke-event reset-end
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc32xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc32xx.cfg
new file mode 100644
index 0000000..9eb03eb
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_cc32xx.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC32xx - ARM Cortex-M4
+#
+# http://www.ti.com/product/CC3200
+# http://www.ti.com/product/CC3220
+#
+
+source [find target/swj-dp.tcl]
+source [find target/icepick.cfg]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cc32xx
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	if {[using_jtag]} {
+		set _DAP_TAPID 0x4BA00477
+	} else {
+		set _DAP_TAPID 0x2BA01477
+	}
+}
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+	jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+} else {
+	swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
+}
+
+#
+# ICEpick-C (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+} else {
+	set _JRC_TAPID 0x0B97C02F
+}
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+	jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x2000
+}
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_dm355.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_dm355.cfg
new file mode 100644
index 0000000..4292373
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_dm355.cfg
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments DaVinci family: TMS320DM355
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dm355
+}
+
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
+#
+# Also note: when running without RTCK before the PLLs are set up, you
+# may need to slow the JTAG clock down quite a lot (under 2 MHz).
+#
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 1"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07926001
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b73b02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
+
+# various symbol definitions, to avoid hard-wiring addresses
+# and enable some sharing of DaVinci-family utility code
+global dm355
+set dm355 [ dict create ]
+
+# Physical addresses for controllers and memory
+# (Some of these are valid for many DaVinci family chips)
+dict set dm355 sram0		0x00010000
+dict set dm355 sram1		0x00014000
+dict set dm355 sysbase		0x01c40000
+dict set dm355 pllc1		0x01c40800
+dict set dm355 pllc2		0x01c40c00
+dict set dm355 psc		0x01c41000
+dict set dm355 gpio		0x01c67000
+dict set dm355 a_emif		0x01e10000
+dict set dm355 a_emif_cs0	0x02000000
+dict set dm355 a_emif_cs1	0x04000000
+dict set dm355 ddr_emif		0x20000000
+dict set dm355 ddr		0x80000000
+dict set dm355 uart0		0x01c20000
+dict set dm355 uart1		0x01c20400
+dict set dm355 uart2		0x01e06000
+
+source [find target/davinci.cfg]
+
+################
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
+# and the ETB memory (4K) are other options, while trace is unused.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+
+# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
+# and that the work area is used only with a kernel mmu context ...
+$_TARGETNAME configure \
+	-work-area-virt [expr {0xfffe0000 + 0x4000}] \
+	-work-area-phys [dict get $dm355 sram1] \
+	-work-area-size 0x4000 \
+	-work-area-backup 0
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_dm365.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_dm365.cfg
new file mode 100644
index 0000000..e19efd7
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_dm365.cfg
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments DaVinci family: TMS320DM365
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dm365
+}
+
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 1"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x0792602f
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b83e02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
+
+# various symbol definitions, to avoid hard-wiring addresses
+# and enable some sharing of DaVinci-family utility code
+global dm365
+set dm365 [ dict create ]
+
+# Physical addresses for controllers and memory
+# (Some of these are valid for many DaVinci family chips)
+dict set dm365 sram0		0x00010000
+dict set dm365 sram1		0x00014000
+dict set dm365 sysbase		0x01c40000
+dict set dm365 pllc1		0x01c40800
+dict set dm365 pllc2		0x01c40c00
+dict set dm365 psc		0x01c41000
+dict set dm365 gpio		0x01c67000
+dict set dm365 a_emif		0x01d10000
+dict set dm365 a_emif_cs0	0x02000000
+dict set dm365 a_emif_cs1	0x04000000
+dict set dm365 ddr_emif		0x20000000
+dict set dm365 ddr		0x80000000
+
+source [find target/davinci.cfg]
+
+################
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
+# and the ETB memory (4K) are other options, while trace is unused.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+
+# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
+# and that the work area is used only with a kernel mmu context ...
+$_TARGETNAME configure \
+	-work-area-virt [expr {0xfffe0000 + 0x4000}] \
+	-work-area-phys [dict get $dm365 sram1] \
+	-work-area-size 0x4000 \
+	-work-area-backup 0
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_dm6446.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_dm6446.cfg
new file mode 100644
index 0000000..8938234
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_dm6446.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments DaVinci family: TMS320DM6446
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME dm6446
+}
+
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
+# Subsidiary TAP: unknown ... must enable via ICEpick
+jtag newtap $_CHIPNAME unknown -irlen 8 -disable
+jtag configure $_CHIPNAME.unknown -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 3"
+
+# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
+jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
+jtag configure $_CHIPNAME.dsp -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 2"
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 1"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07926001
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b70002f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
+# and the ETB memory (4K) are other options, while trace is unused.
+# Little-endian; use the OpenOCD default.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_k3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_k3.cfg
new file mode 100644
index 0000000..2ae0f75
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_k3.cfg
@@ -0,0 +1,501 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments K3 devices:
+# * AM243: https://www.ti.com/lit/pdf/spruim2
+#  Has 4 R5 Cores, M4F and an M3
+# * AM263: https://www.ti.com/lit/pdf/spruj17
+#  Has 4 R5 Cores and an M3
+# * AM273: https://www.ti.com/lit/pdf/spruiu0
+#  Has 2 R5 Cores and an M3
+# * AM625: https://www.ti.com/lit/pdf/spruiv7a
+#  Has 4 ARMV8 Cores and 1 R5 Core and an M4F
+# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
+#  Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM62P: https://www.ti.com/lit/pdf/spruj83
+#  Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM642: https://www.ti.com/lit/pdf/spruim2
+#  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
+# * AM654x: https://www.ti.com/lit/pdf/spruid7
+#  Has 4 ARMV8 Cores and 2 R5 Cores and an M3
+# * J7200: https://www.ti.com/lit/pdf/spruiu1
+#  Has 2 ARMV8 Cores and 4 R5 Cores and an M3
+# * J721E: https://www.ti.com/lit/pdf/spruil1
+#  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
+# * J721S2: https://www.ti.com/lit/pdf/spruj28
+#  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
+# * J722S: https://www.ti.com/lit/zip/sprujb3
+#  Has 4 ARMV8 Cores and 3 R5 Cores
+# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
+#  Has 8 ARMV8 Cores and 8 R5 Cores
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc am654
+}
+
+# set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
+if { [info exists V8_SMP_DEBUG] } {
+	set _v8_smp_debug $V8_SMP_DEBUG
+} else {
+	set _v8_smp_debug 0
+}
+
+# Common Definitions
+
+# System Controller is the very first processor - all current SoCs have it.
+set CM3_CTIBASE		{0x3C016000}
+
+# sysctrl power-ap unlock offsets
+set _sysctrl_ap_unlock_offsets {0xf0 0x44}
+set _sysctrl_ap_num 7
+
+# All the ARMV8s are the next processors.
+#		   CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1
+set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
+set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
+
+# And we add up the R5s
+#		(0)MCU 0   (1)MCU 1   (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
+set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
+set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+set _r5_ap_num 1
+
+# Finally an General Purpose(GP) MCU
+set CM4_CTIBASE		{0x20001000}
+
+# General Purpose MCU (M4) may be present on some very few SoCs
+set _gp_mcu_cores 0
+# General Purpose MCU power-ap unlock offsets
+set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
+
+# Generic mem-ap port number
+set _mem_ap_num 2
+
+# Set configuration overrides for each SOC
+switch $_soc {
+	am263 {
+		set _K3_DAP_TAPID 0x2bb7d02f
+
+		# Mem-ap port
+		set _mem_ap_num 6
+
+		# AM263 has 0 ARMV8 CPUs
+		set _armv8_cores 0
+
+		# AM263 has 2 cluster of 2 R5s cores.
+		set _r5_cores 4
+		set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+		set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
+		set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
+		set _r5_ap_num 5
+	}
+	am273 {
+		set _K3_DAP_TAPID 0x1bb6a02f
+
+		# Mem-ap port
+		set _mem_ap_num 6
+
+		# system controller is on AP0
+		set _sysctrl_ap_num 0
+
+		# AM273 has 0 ARMV8 CPUs
+		set _armv8_cores 0
+
+		# AM273 has 1 cluster of 2 R5s cores.
+		set _r5_cores 2
+		set R5_NAMES {main0_r5.0 main0_r5.1}
+		set R5_DBGBASE {0x90030000 0x90032000}
+		set R5_CTIBASE {0x90038000 0x90039000}
+		set _r5_ap_num 5
+	}
+	am654 {
+		set _K3_DAP_TAPID 0x0bb5a02f
+
+		# AM654 has 2 clusters of 2 A53 cores each.
+		set _armv8_cpu_name a53
+		set _armv8_cores 4
+
+		# AM654 has 1 cluster of 2 R5s cores.
+		set _r5_cores 2
+		set R5_NAMES {mcu_r5.0 mcu_r5.1}
+
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x50}
+	}
+	am243 -
+	am642 {
+		set _K3_DAP_TAPID 0x0bb3802f
+
+		# AM642 has 1 clusters of 2 A53 cores each.
+		set _armv8_cpu_name a53
+		set _armv8_cores 2
+		set ARMV8_DBGBASE {0x90010000 0x90110000}
+		set ARMV8_CTIBASE {0x90020000 0x90120000}
+
+		# AM642 has 2 cluster of 2 R5s cores.
+		set _r5_cores 4
+		set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+		set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
+		set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+
+		# M4 processor
+		set _gp_mcu_cores 1
+
+		# Overrides for am243
+		if { "$_soc" == "am243" } {
+			# Uses the same JTAG ID
+			set _armv8_cores 0
+		}
+	}
+	am625 {
+		set _K3_DAP_TAPID 0x0bb7e02f
+
+		# AM625 has 1 clusters of 4 A53 cores.
+		set _armv8_cpu_name a53
+		set _armv8_cores 4
+		set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+		set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+		# AM625 has 1 cluster of 1 R5s core.
+		set _r5_cores 1
+		set R5_NAMES {main0_r5.0}
+		set R5_DBGBASE {0x9d410000}
+		set R5_CTIBASE {0x9d418000}
+
+		# sysctrl CTI base
+		set CM3_CTIBASE {0x20001000}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+		# M4 processor
+		set _gp_mcu_cores 1
+		set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+
+		# Setup DMEM access descriptions
+		# DAPBUS (Debugger) description
+		set _dmem_base_address 0x740002000
+		set _dmem_ap_address_offset 0x100
+		set _dmem_max_aps 10
+		# Emulated AP description
+		set _dmem_emu_base_address 0x760000000
+		set _dmem_emu_base_address_map_to 0x1d500000
+		set _dmem_emu_ap_list 1
+	}
+	j722s -
+	am62p -
+	am62a7 {
+		set _K3_DAP_TAPID 0x0bb8d02f
+
+		# AM62a7/AM62P has 1 cluster of 4 A53 cores.
+		set _armv8_cpu_name a53
+		set _armv8_cores 4
+		set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+		set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+		# AM62a7/AM62P has 2 cluster of 1 R5 core.
+		set _r5_cores 2
+		set R5_NAMES {main0_r5.0 mcu0_r5.0}
+		set R5_DBGBASE {0x9d410000 0x9d810000}
+		set R5_CTIBASE {0x9d418000 0x9d818000}
+
+		# sysctrl CTI base
+		set CM3_CTIBASE {0x20001000}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+		# Setup DMEM access descriptions
+		# DAPBUS (Debugger) description
+		set _dmem_base_address 0x740002000
+		set _dmem_ap_address_offset 0x100
+		set _dmem_max_aps 10
+		# Emulated AP description
+		set _dmem_emu_base_address 0x760000000
+		set _dmem_emu_base_address_map_to 0x1d500000
+		set _dmem_emu_ap_list 1
+
+		# Overrides for am62p
+		if { "$_soc" == "am62p" } {
+			set _K3_DAP_TAPID 0x0bb9d02f
+			set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
+		}
+		# Overrides for j722s
+		if { "$_soc" == "j722s" } {
+			set _K3_DAP_TAPID 0x0bba002f
+			set _r5_cores 3
+			set R5_NAMES {wkup0_r5.0 main0_r5.0 mcu0_r5.0}
+			set R5_DBGBASE {0x9d410000 0x9d510000 0x9d810000}
+			set R5_CTIBASE {0x9d418000 0x9d518000 0x9d818000}
+		}
+	}
+	j721e {
+		set _K3_DAP_TAPID 0x0bb6402f
+		# J721E has 1 cluster of 2 A72 cores.
+		set _armv8_cpu_name a72
+		set _armv8_cores 2
+
+		# J721E has 3 clusters of 2 R5 cores each.
+		set _r5_cores 6
+
+		# Setup DMEM access descriptions
+		# DAPBUS (Debugger) description
+		set _dmem_base_address 0x4c40002000
+		set _dmem_ap_address_offset 0x100
+		set _dmem_max_aps 8
+		# Emulated AP description
+		set _dmem_emu_base_address 0x4c60000000
+		set _dmem_emu_base_address_map_to 0x1d600000
+		set _dmem_emu_ap_list 1
+	}
+	j7200 {
+		set _K3_DAP_TAPID 0x0bb6d02f
+
+		# J7200 has 1 cluster of 2 A72 cores.
+		set _armv8_cpu_name a72
+		set _armv8_cores 2
+
+		# J7200 has 2 clusters of 2 R5 cores each.
+		set _r5_cores 4
+		set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
+		set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
+
+		# M3 CTI base
+		set CM3_CTIBASE {0x20001000}
+	}
+	j721s2 {
+		set _K3_DAP_TAPID 0x0bb7502f
+
+		# J721s2 has 1 cluster of 2 A72 cores.
+		set _armv8_cpu_name a72
+		set _armv8_cores 2
+
+		# J721s2 has 3 clusters of 2 R5 cores each.
+		set _r5_cores 6
+
+		# sysctrl CTI base
+		set CM3_CTIBASE {0x20001000}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+		# M4 processor
+		set _gp_mcu_cores 1
+		set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+	}
+	j784s4 {
+		set _K3_DAP_TAPID 0x0bb8002f
+
+		# j784s4 has 2 cluster of 4 A72 cores each.
+		set _armv8_cpu_name a72
+		set _armv8_cores 8
+		set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
+                           0x90810000 0x90910000 0x90a10000 0x90b10000}
+		set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
+                           0x90820000 0x90920000 0x90a20000 0x90b20000}
+
+		# J721s2 has 4 clusters of 2 R5 cores each.
+		set _r5_cores 8
+		set R5_DBGBASE {0x9d010000 0x9d012000
+                        0x9d410000 0x9d412000
+                        0x9d510000 0x9d512000
+                        0x9d610000 0x9d612000}
+		set R5_CTIBASE {0x9d018000 0x9d019000
+                        0x9d418000 0x9d419000
+                        0x9d518000 0x9d519000
+                        0x9d618000 0x9d619000}
+		set R5_NAMES {mcu_r5.0 mcu_r5.1
+                      main0_r5.0 main0_r5.1
+                      main1_r5.0 main1_r5.1
+                      main2_r5.0 main2_r5.1}
+
+		# sysctrl CTI base
+		set CM3_CTIBASE {0x20001000}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+	}
+	default {
+		echo "'$_soc' is invalid!"
+	}
+}
+
+proc _get_rtos_type_for_cpu { target_name } {
+	if { [info exists ::RTOS($target_name)] } {
+		return $::RTOS($target_name)
+	}
+	return none
+}
+
+set _CHIPNAME $_soc
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+set _CTINAME $_CHIPNAME.cti
+
+# sysctrl is always present
+cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
+	-ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
+
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
+	-ap-num $_sysctrl_ap_num -defer-examine \
+	-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
+
+$_TARGETNAME.sysctrl configure -event reset-assert { }
+
+proc sysctrl_up {} {
+	# To access sysctrl, we need to enable the JTAG access for the same.
+	# Ensure Power-AP unlocked
+	$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
+	$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
+
+	$::_TARGETNAME.sysctrl arp_examine
+}
+
+$_TARGETNAME.sysctrl configure -event gdb-attach {
+	sysctrl_up
+	# gdb-attach default rule
+	halt 1000
+}
+
+proc _cpu_no_smp_up {} {
+	set _current_target [target current]
+	set _current_type [$_current_target cget -type]
+
+	$_current_target arp_examine
+	$_current_target $_current_type dbginit
+}
+
+proc _armv8_smp_up {} {
+	for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
+		$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
+		$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+		$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
+	}
+	# Set Default target as core 0
+	targets $::_TARGETNAME.$::_armv8_cpu_name.0
+}
+
+set _v8_smp_targets ""
+
+for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
+
+	cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+		-baseaddr [lindex $ARMV8_CTIBASE $_core]
+
+	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
+		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
+
+	set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
+
+	if { $_v8_smp_debug == 0 } {
+		$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+			_cpu_no_smp_up
+			# gdb-attach default rule
+			halt 1000
+		}
+	} else {
+		$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+			_armv8_smp_up
+			# gdb-attach default rule
+			halt 1000
+		}
+	}
+}
+
+if { $_armv8_cores > 0 } {
+	# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
+	set _armv8_up_cmd "$_armv8_cpu_name"_up
+	# Available if V8_SMP_DEBUG is set to non-zero value
+	set _armv8_smp_cmd "$_armv8_cpu_name"_smp
+
+	if { $_v8_smp_debug == 0 } {
+		proc $_armv8_up_cmd { args } {
+			foreach _core $args {
+				targets $_core
+				_cpu_no_smp_up
+			}
+		}
+	} else {
+		proc $_armv8_smp_cmd { args } {
+			_armv8_smp_up
+		}
+		# Declare SMP
+		target smp {*}$_v8_smp_targets
+	}
+}
+
+for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
+	set _r5_name [lindex $R5_NAMES $_core]
+	cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
+		-baseaddr [lindex $R5_CTIBASE $_core]
+
+	# inactive core examination will fail - wait till startup of additional core
+	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
+		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
+
+	$_TARGETNAME.$_r5_name configure -event gdb-attach {
+		_cpu_no_smp_up
+		# gdb-attach default rule
+		halt 1000
+	}
+}
+
+proc r5_up { args } {
+	foreach  _core $args {
+		targets $_core
+		_cpu_no_smp_up
+	}
+}
+
+if { $_gp_mcu_cores != 0 } {
+	cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
+	target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
+	$_TARGETNAME.gp_mcu configure -event reset-assert { }
+
+	proc gp_mcu_up {} {
+		# To access GP MCU, we need to enable the JTAG access for the same.
+		# Ensure Power-AP unlocked
+		$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
+		$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
+
+		$::_TARGETNAME.gp_mcu arp_examine
+	}
+
+	$_TARGETNAME.gp_mcu configure -event gdb-attach {
+		gp_mcu_up
+		# gdb-attach default rule
+		halt 1000
+	}
+}
+
+# In case of DMEM access, configure the dmem adapter with offsets from above.
+if { 0 == [string compare [adapter name] dmem ] } {
+	if { [info exists _dmem_base_address] } {
+		# DAPBUS (Debugger) description
+		dmem base_address $_dmem_base_address
+		dmem ap_address_offset $_dmem_ap_address_offset
+		dmem max_aps $_dmem_max_aps
+
+		# The following are the details of APs to be emulated for direct address access.
+		# Debug Config (Debugger) description
+		dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
+		dmem emu_ap_list $_dmem_emu_ap_list
+		# We are going local bus, so speed is really dummy here.
+		adapter speed 2500
+	} else {
+		puts "ERROR: ${SOC} data is missing to support dmem access!"
+	}
+} else {
+	# AXI AP access port for SoC address map
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_msp432.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_msp432.cfg
new file mode 100644
index 0000000..8a90b98
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_msp432.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments MSP432 - ARM Cortex-M4F @ up to 48 MHz
+#
+# http://www.ti.com/MSP432
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME msp432
+}
+
+if { [info exists CPUTAPID] } {
+	set _DAP_TAPID $CPUTAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+if { [info exists DAP_SWD_ID] } {
+	set _DAP_SWD_ID $DAP_SWD_ID
+} else {
+	set _DAP_SWD_ID 0x2ba01477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+	set _DAP_ID $_DAP_TAPID
+} else {
+	set _DAP_ID $_DAP_SWD_ID
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x4000
+}
+
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
+
+cortex_m reset_config sysresetreq
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_rm4x.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_rm4x.cfg
new file mode 100644
index 0000000..715aa5b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_rm4x.cfg
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find target/ti_tms570.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570.cfg
new file mode 100644
index 0000000..18e0d82
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570.cfg
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter speed 1500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME tms570
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN big
+}
+
+# TMS570 has an ICEpick-C on which we need the router commands.
+source [find target/icepick.cfg]
+
+# Main DAP
+# DAP_TAPID should be set before source-ing this file
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# ICEpick-C (JTAG route controller)
+# JRC_TAPID should be set before source-ing this file
+if { [info exists JRC_TAPID] } {
+	set _JRC_TAPID $JRC_TAPID
+}
+
+set _JRC_TAPID2 0x0B7B302F
+set _JRC_TAPID3 0x0B95502F
+set _JRC_TAPID4 0x0B97102F
+set _JRC_TAPID5 0x0D8A002F
+set _JRC_TAPID6 0x0B8A002F
+
+
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+	-expected-id $_JRC_TAPID \
+	-expected-id $_JRC_TAPID2 \
+	-expected-id $_JRC_TAPID3 \
+	-expected-id $_JRC_TAPID4 \
+	-expected-id $_JRC_TAPID5 \
+	-expected-id $_JRC_TAPID6 \
+	-ignore-version
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Cortex-R4 target
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
+	-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000
+
+# TMS570 uses quirky BE-32 mode
+$_CHIPNAME.dap ti_be_32_quirks 1
+
+$_TARGETNAME configure -event "reset-assert" {
+	global _CHIPNAME
+
+	# assert warm system reset through ICEPick
+	icepick_c_wreset $_CHIPNAME.jrc
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570lc43xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570lc43xx.cfg
new file mode 100644
index 0000000..ffda989
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570lc43xx.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set DAP_TAPID 0x0B95A02F
+set JRC_TAPID 0x0B95A02F
+
+source [find target/ti_tms570.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570ls20xxx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570ls20xxx.cfg
new file mode 100644
index 0000000..cc2bbd6
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570ls20xxx.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TMS570LS20216, TMS570LS20206, TMS570LS10216
+# TMS570LS10206, TMS570LS10116, TMS570LS10106
+set DAP_TAPID 0x0B7B302F
+set JRC_TAPID 0x0B7B302F
+
+source [find target/ti_tms570.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570ls3137.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570ls3137.cfg
new file mode 100644
index 0000000..ebe2cfc
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/ti_tms570ls3137.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# TMS570LS3137
+set DAP_TAPID 0x0B8A002F
+set JRC_TAPID 0x0B8A002F
+
+source [find target/ti_tms570.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/tmpa900.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/tmpa900.cfg
new file mode 100644
index 0000000..b7ec689
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/tmpa900.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Toshiba TMPA900
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME tmpa900
+}
+
+# Toshiba TMPA900 series MCUs are always little endian as per datasheet.
+set _ENDIAN little
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926031
+}
+
+#TMPA900 has following IDs:
+# CP15.0 register 0x41069265
+# CP15.1 register 0x1d152152
+# ARM core 0x07926031
+
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+adapter srst delay 20
+jtag_ntrst_delay 20
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Internal RAM-0 (16kB): 0xf8004000
+# Internal RAM-1 (8kB): 0xf8008000
+
+# Use internal RAM-0 and RAM-1 as working area (24kB total).
+$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0x6000 \
+-work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/tmpa910.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/tmpa910.cfg
new file mode 100644
index 0000000..276d1ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/tmpa910.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+######################################
+# Target:    Toshiba TMPA910
+######################################
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME tmpa910
+}
+
+# Toshiba TMPA910 series MCUs are always little endian as per datasheet.
+set _ENDIAN little
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926031
+}
+
+#TMPA910 has following IDs:
+# CP15.0 register 0x41069265
+# CP15.1 register 0x1d152152
+# ARM core 0x07926031
+
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+adapter srst delay 20
+jtag_ntrst_delay 20
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# Internal RAM-0 (16kB): 0xf8004000
+# Internal RAM-1 (16kB): 0xf8008000
+# Internal RAM-2 (16kB): 0xf800c000
+
+# Use internal RAM-0, RAM-1, and RAM-2 as working area (48kB total).
+$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0xc000 \
+-work-area-backup 0
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/tnetc4401.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/tnetc4401.cfg
new file mode 100644
index 0000000..6a24980
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/tnetc4401.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Texas Instruments (TI) TNETC4401, MIPS32 DOCSIS-tailored SoC (4Kc-based)
+# Used in Knovative KC-100 and Motorola Surfboard SB5120 cable modems.
+# Datasheet: https://brezn.muc.ccc.de/~mazzoo/DOCSIS/tnetc4401.pdf
+transport select jtag
+set _TARGETNAME tnetc4401
+set _CPUTAPID 0x0000100f
+jtag newtap $_TARGETNAME tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
+target create $_TARGETNAME mips_m4k -chain-position $_TARGETNAME.tap -endian big
+
+# May need to halt manually before calling reset init
+$_TARGETNAME configure -event reset-init {
+	halt
+	echo "Attempting to disable watchdog..."
+	mwb phys 0xa8610b00 0 256
+	halt
+	wait_halt
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/u8500.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/u8500.cfg
new file mode 100644
index 0000000..1fdc11f
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/u8500.cfg
@@ -0,0 +1,326 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#  Copyright (C) ST-Ericsson SA 2011
+#  Author : michel.jaouen@stericsson.com
+#  U8500 target
+
+proc mmu_off {} {
+	set cp [arm mrc 15 0 1 0 0]
+	set cp [expr {$cp & ~1}]
+	arm mcr 15 0 1 0 0 $cp
+}
+
+proc mmu_on {} {
+	set cp [arm mrc 15 0 1 0 0]
+	set cp [expr {$cp | 1}]
+	arm mcr 15 0 1 0 0 $cp
+}
+
+proc ocd_gdb_restart {target_id} {
+    global _TARGETNAME_1
+	global _SMP
+    targets $_TARGETNAME_1
+	if { $_SMP == 1 } {
+	cortex_a smp off
+	}
+	rst_run
+	halt
+	if { $_SMP == 1 } {
+	cortex_a smp on
+	}
+}
+
+proc smp_reg {} {
+	global _TARGETNAME_1
+    global _TARGETNAME_2
+    targets $_TARGETNAME_1
+	echo "$_TARGETNAME_1"
+	set pc1 [reg pc]
+	set stck1 [reg sp_svc]
+	targets $_TARGETNAME_2
+	echo "$_TARGETNAME_1"
+	set pc2 [reg pc]
+	set stck2 [reg sp_svc]
+}
+
+
+proc u8500_tapenable {chip val} {
+	echo "JTAG tap enable $chip"
+}
+
+
+proc pwrsts { } {
+	global _CHIPNAME
+	irscan $_CHIPNAME.jrc 0x3a
+	drscan $_CHIPNAME.jrc 4 0
+	set pwrsts [drscan $_CHIPNAME.jrc 16 0]
+	echo "pwrsts ="$pwrsts
+	set a9 [expr "0x$pwrsts & 0xc"]
+	set ape [expr "0x$pwrsts & 0x3"]
+	if {[string equal "0" $ape]} {
+		echo "ape off"
+	} else {
+		echo "ape on"
+	}
+	echo "$a9"
+	switch $a9 {
+		4 {
+			echo "A9 in retention"
+		  }
+		8 {
+			echo "A9 100% DVFS"
+		  }
+		c {
+			echo "A9 50% DVFS"
+		}
+	}
+}
+
+proc poll_pwrsts { } {
+	global _CHIPNAME
+	set result 1
+	set i 0
+	irscan $_CHIPNAME.jrc 0x3a
+	drscan $_CHIPNAME.jrc 4 0
+	set pwrsts [drscan $_CHIPNAME.jrc 16 0]
+	set pwrsts [expr "0x$pwrsts & 0xc"]
+	while {[string equal "4" $pwrsts] && $i<20} {
+		irscan $_CHIPNAME.jrc 0x3a
+		drscan $_CHIPNAME.jrc 4 0;
+		set pwrsts [drscan $_CHIPNAME.jrc 16 0]
+		set pwrsts [expr "0x$pwrsts & 0xc"]
+		if {![string equal "4" $pwrsts]} {
+			set result 1
+		} else {
+			set result 0
+			sleep 200
+			echo "loop $i"
+		}
+		incr i
+	}
+	return $result
+}
+
+proc halt_ { } {
+	if {[poll_pwrsts]==1} {
+		halt
+	} else {
+		echo "halt failed : target in retention"
+	}
+}
+
+
+proc u8500_dapenable {chip} {
+}
+
+proc u8500_tapdisable {chip val} {
+	echo "JTAG tap disable $chip"
+}
+
+
+proc enable_apetap {} {
+	global _CHIPNAME
+	global _TARGETNAME_2
+    global _TARGETNAME_1
+	poll off
+	irscan $_CHIPNAME.jrc 0x3e
+	drscan $_CHIPNAME.jrc 8 0xcf
+	jtag tapenable $_CHIPNAME.dap
+	irscan $_CHIPNAME.jrc 0x6
+	drscan $_CHIPNAME.jrc 32 0
+	irscan $_CHIPNAME.jrc 0x6
+	drscan $_CHIPNAME.jrc 32 0
+	set status [$_TARGETNAME_1 curstate]
+    if {[string equal "unknown" $status]} {
+	$_TARGETNAME_1 arp_examine
+	cache_config l2x 0xa0412000 8
+	}
+
+	set status [$_TARGETNAME_2 curstate]
+    if {[string equal "unknown" $status]} {
+	$_TARGETNAME_2 arp_examine
+	}
+	}
+
+tcl port 5555
+telnet port 4444
+gdb port 3333
+
+if { [info exists CHIPNAME] } {
+global _CHIPNAME
+    set _CHIPNAME $CHIPNAME
+} else {
+global _CHIPNAME
+	set _CHIPNAME u8500
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+	set _ENDIAN little
+}
+
+
+
+# Subsidiary TAP: APE with scan chains for ARM Debug, EmbeddedICE-RT,
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+	"u8500_dapenable $_CHIPNAME.cpu"
+jtag configure $_CHIPNAME.cpu -event tap-disable \
+	"u8500_tapdisable $_CHIPNAME.cpu 0xc0"
+
+
+#CLTAPC TAP JRC equivalent
+if { [info exists CLTAPC_ID] } {
+   set _CLTAPC_ID $CLTAPC_ID
+} else {
+   set _CLTAPC_ID 0x22286041
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x6 -irmask 0xf -expected-id $_CLTAPC_ID -ignore-version
+
+
+if { ![info exists TARGETNAME_1] } {
+global _TARGETNAME_1
+set _TARGETNAME_1 $_CHIPNAME.cpu1
+} else {
+global _TARGETNAME_1
+set _TARGETNAME_1 $TARGETNAME_1
+}
+
+if { [info exists DAP_DBG1] } {
+	set _DAP_DBG1 $DAP_DBG1
+} else {
+	set _DAP_DBG1 0x801A8000
+}
+if { [info exists DAP_DBG2] } {
+	set _DAP_DBG2 $DAP_DBG2
+} else {
+	set _DAP_DBG2 0x801AA000
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME_1 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
+
+
+if { ![info exists TARGETNAME_2] } {
+global _TARGETNAME_2
+set _TARGETNAME_2 $_CHIPNAME.cpu2
+} else {
+global _TARGETNAME_2
+set _TARGETNAME_2 $TARGETNAME_2
+}
+
+target create $_TARGETNAME_2 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
+
+
+if {![info exists SMP]} {
+global _SMP
+set _SMP 1
+} else {
+global _SMP
+set _SMP $SMP
+}
+global SMP
+if { $_SMP == 1} {
+target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
+}
+
+
+
+
+proc secsts1 { } {
+	global _CHIPNAME
+        irscan $_CHIPNAME.jrc 0x3a
+		drscan $_CHIPNAME.jrc 4 4
+	set secsts1 [drscan $_CHIPNAME.jrc 16 0]
+	echo "secsts1 ="$secsts1
+	set secsts1 [expr "0x$secsts1 & 0x4"]
+	if {![string equal "4" $secsts1]} {
+	echo "APE target secured"
+        } else {
+        echo "APE target not secured"
+        }
+}
+
+proc att { } {
+	global _CHIPNAME
+	jtag arp_init
+	irscan $_CHIPNAME.jrc 0x3a
+	drscan $_CHIPNAME.jrc 4 4
+	set secsts1 [drscan $_CHIPNAME.jrc 16 0]
+	echo "secsts1 ="$secsts1
+	set secsts1 [expr "0x$secsts1 & 0x4"]
+	if {[string equal "4" $secsts1]} {
+		if {[poll_pwrsts]==1} {
+		enable_apetap
+                } else {
+		echo "target in retention"
+		}
+	} else {
+		echo "target secured"
+	}
+
+}
+
+
+
+proc rst_run { } {
+	global _CHIPNAME
+	global _TARGETNAME_2
+	global _TARGETNAME_1
+	set status [$_TARGETNAME_1 curstate]
+	if {[string equal "halted" $status]} {
+	resume
+	targets $_TARGETNAME_1
+	}
+    set status [$_TARGETNAME_2 curstate]
+	if {[string equal "halted" $status]} {
+	resume
+	targets $_TARGETNAME_2
+	}
+   	poll off
+	jtag arp_init
+	reset
+	sleep 20
+	irscan $_CHIPNAME.jrc 0x3a
+	drscan $_CHIPNAME.jrc 4 4
+	set secsts1 [drscan $_CHIPNAME.jrc 16 0]
+	echo "secsts1 ="$secsts1
+	set secsts1 [expr "0x$secsts1 & 0x4"]
+	while {![string equal "4" $secsts1]} {
+		irscan u8500.jrc 0x3a
+		drscan u8500.jrc 4 4
+		set secsts1 [drscan $_CHIPNAME.jrc 16 0]
+		echo "secsts1 ="$secsts1
+		set secsts1 [expr "0x$secsts1 & 0x4"]
+	}
+	echo "ape debugable"
+	enable_apetap
+	poll on
+	targets $_TARGETNAME_1
+	dap apsel 1
+}
+
+if {![info exists MAXSPEED]} {
+global _MAXSPEED
+set _MAXSPEED 15000
+} else {
+global _MAXSPEED
+set _MAXSPEED $MAXSPEED
+}
+global _MAXSPEED
+adapter speed $_MAXSPEED
+
+
+gdb breakpoint_override hard
+set mem inaccessible-by-default-off
+
+jtag_ntrst_delay 100
+reset_config trst_and_srst combined
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vd_aarch64.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vd_aarch64.cfg
new file mode 100644
index 0000000..177416b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vd_aarch64.cfg
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm v8 64b Cortex A
+
+if {![info exists CORES]} {
+	set CORES 1
+}
+if {![info exists CHIPNAME]} {
+	set CHIPNAME aarch64
+}
+if {[info exists ACCESSPORT]} {
+	set _APNUM "-ap-num $ACCESSPORT"
+	if { $ACCESSPORT > 0xff } {
+		set _DAP6 "-adiv6"
+	} else {
+		set _DAP6 "-adiv5"
+	}
+} else {
+	set _APNUM ""
+}
+
+set _TARGETNAME $CHIPNAME.cpu
+set _CTINAME $CHIPNAME.cti
+set _DAPNAME $CHIPNAME.dap
+
+dap create $_DAPNAME $_DAP6 -chain-position $_TARGETNAME
+
+for { set _core 0 } { $_core < $CORES } { incr _core } \
+{
+	set _cmd "cti create $_CTINAME.$_core -dap $_DAPNAME $_APNUM -baseaddr [lindex $CTIBASE $_core]"
+	eval $_cmd
+	set _cmd "target create $_TARGETNAME.$_core aarch64 -dap $_DAPNAME $_APNUM -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
+	if { $_core != 0 } {
+		# non-boot core examination may fail
+		set _cmd "$_cmd -defer-examine"
+		set _smp_cmd "$_smp_cmd $_TARGETNAME.$_core"
+	} else {
+		set _smp_cmd "target smp $_TARGETNAME.$_core"
+	}
+	eval $_cmd
+}
+eval $_smp_cmd
+
+set _TARGETCUR $_TARGETNAME.0
+targets $_TARGETCUR
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vd_cortex_m.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vd_cortex_m.cfg
new file mode 100644
index 0000000..7db9d3a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vd_cortex_m.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# ARM Cortex M
+
+if {![info exists CHIPNAME]} {
+	set CHIPNAME cortex_m
+}
+set _TARGETNAME $CHIPNAME.cpu
+set _DAPNAME $CHIPNAME.dap
+
+dap create $_DAPNAME -chain-position $_TARGETNAME
+
+target create $_TARGETNAME cortex_m -dap $_DAPNAME
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vd_riscv.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vd_riscv.cfg
new file mode 100644
index 0000000..f08cb1a
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vd_riscv.cfg
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV core
+
+if {![info exists _HARTID]} {
+	set _HARTID 0x00
+}
+if {![info exists _CHIPNAME]} {
+	set _CHIPNAME riscv
+}
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+riscv set_mem_access sysbus progbuf
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vybrid_vf6xx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vybrid_vf6xx.cfg
new file mode 100644
index 0000000..776c16b
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/vybrid_vf6xx.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale Vybrid VF610
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME vf610
+}
+
+if { [info exists A5_JTAG_TAPID] } {
+	set _A5_JTAG_TAPID $A5_JTAG_TAPID
+} else {
+	set _A5_JTAG_TAPID 0x4BA00477
+}
+
+if { [info exists A5_SWD_TAPID] } {
+	set _A5_SWD_TAPID $A5_SWD_TAPID
+} else {
+	set _A5_SWD_TAPID 0x3BA02477
+}
+
+if { [using_jtag] } {
+	set _A5_TAPID $_A5_JTAG_TAPID
+} else {
+	set _A5_TAPID $_A5_SWD_TAPID
+}
+
+source [find target/swj-dp.tcl]
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000
+target create ${_TARGETNAME}1 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xilinx_zynqmp.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xilinx_zynqmp.cfg
new file mode 100644
index 0000000..e8224be
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xilinx_zynqmp.cfg
@@ -0,0 +1,240 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# target configuration for
+# Xilinx ZynqMP (UltraScale+ / A53)
+#
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME uscale
+}
+
+#
+# DAP tap (Quard core A53)
+#
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x5ba00477
+}
+
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+#
+# PS tap (UltraScale+)
+#
+if { [info exists PS_TAPID] } {
+    set _PS_TAPID $PS_TAPID
+    jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
+} else {
+    # FPGA Programmable logic. Values take from Table 39-1 in UG1085:
+    jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -ignore-version \
+        -expected-id 0x04711093 \
+        -expected-id 0x04710093 \
+        -expected-id 0x04721093 \
+        -expected-id 0x04720093 \
+        -expected-id 0x04739093 \
+        -expected-id 0x04730093 \
+        -expected-id 0x04738093 \
+        -expected-id 0x04740093 \
+        -expected-id 0x04750093 \
+        -expected-id 0x04759093 \
+        -expected-id 0x04758093
+}
+
+set jtag_configured 0
+
+jtag configure $_CHIPNAME.ps -event setup {
+    global _CHIPNAME
+    global jtag_configured
+
+    if { $jtag_configured == 0 } {
+        # add the DAP tap to the chain
+        # See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924
+        irscan $_CHIPNAME.ps 0x824
+        drscan $_CHIPNAME.ps 32 0x00000003
+        runtest 100
+
+        # setup event will be re-entered through jtag arp_init
+        # break the recursion
+        set jtag_configured 1
+        # re-initialized the jtag chain
+        jtag arp_init
+    }
+}
+
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+set _smp_command ""
+
+set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+set _cores 4
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -baseaddr [lindex $CTIBASE $_core]
+
+    set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command $_TARGETNAME.$_core"
+    } else {
+        set _command "$_command -rtos hwthread"
+        set _smp_command "target smp $_TARGETNAME.$_core"
+    }
+
+    eval $_command
+}
+
+target create uscale.axi mem_ap -dap uscale.dap -ap-num 0
+
+eval $_smp_command
+targets $_TARGETNAME.0
+
+proc core_up { args } {
+    global _TARGETNAME
+    foreach core $args {
+        $_TARGETNAME.$core arp_examine
+    }
+}
+
+proc BIT {n} {
+	return [expr {1 << $n}]
+}
+
+set IPI_BASE			0xff300000
+set IPI_PMU_0_TRIG		[expr {$IPI_BASE + 0x30000}]
+set IPI_PMU_0_IER		[expr {$IPI_BASE + 0x30018}]
+set IPI_PMU_0					[BIT 16]
+
+set CRF_APB_BASE		0xfd1a0000
+set CRF_APB_RST_FPD_APU		[expr {$CRF_APB_BASE + 0x104}]
+set CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET	[BIT 10]
+set CRF_APB_RST_FPD_APU_L2_RESET		[BIT  8]
+set CRF_APB_RST_FPD_APU_ACPU0_RESET		[BIT  0]
+
+set APU_BASE			0xfd5c0000
+set APU_RVBARADDR_BASE		[expr {$APU_BASE + 0x40}]
+
+set PMU_BASE			0xffd80000
+set PMU_GLOBAL			$PMU_BASE
+set PMU_GLOBAL_MB_SLEEP				[BIT 16]
+set PMU_GLOBAL_FW_IS_PRESENT			[BIT  4]
+set PMU_GLOBAL_DONT_SLEEP			[BIT  0]
+
+set PMU_RAM_BASE		0xffdc0000
+
+set OCM_RAM_BASE		0xfffc0000
+
+rename BIT {}
+
+add_help_text halt_pmu "Halt the PMU in preparation for loading new firmware.\
+	This should be matched with a call to resume_pmu."
+proc halt_pmu {} {
+	set axi $::_CHIPNAME.axi
+	set val [$axi read_memory $::IPI_PMU_0_IER 32 1]
+	$axi write_memory $::IPI_PMU_0_IER 32 [expr {$val | $::IPI_PMU_0}]
+
+	set val [$axi read_memory $::IPI_PMU_0_TRIG 32 1]
+	$axi write_memory $::IPI_PMU_0_TRIG 32 [expr {$val | $::IPI_PMU_0}]
+
+	set start [ms]
+	while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_MB_SLEEP)} {
+		if {[ms] - $start > 1000} {
+			error "Timed out waiting for PMU to halt"
+		}
+	}
+}
+
+add_help_text resume_pmu "Resume the PMU after loading new firmware. This\
+	should be matched with a call to halt_pmu."
+proc resume_pmu {} {
+	set axi $::_CHIPNAME.axi
+	set val [$axi read_memory $::PMU_GLOBAL 32 1]
+	$axi write_memory $::PMU_GLOBAL 32 [expr {$val | $::PMU_GLOBAL_DONT_SLEEP}]
+
+	set start [ms]
+	while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_FW_IS_PRESENT)} {
+		if {[ms] - $start > 5000} {
+			error "Timed out waiting for PMU firmware"
+		}
+	}
+}
+
+add_usage_text release_apu {apu}
+add_help_text release_apu "Release an APU from reset. It will start executing\
+	at RVBARADDR. You probably want resume_apu or start_apu instead."
+proc release_apu {apu} {
+	set axi $::_CHIPNAME.axi
+	set val [$axi read_memory $::CRF_APB_RST_FPD_APU 32 1]
+	set mask [expr {
+		(($::CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET | \
+		  $::CRF_APB_RST_FPD_APU_ACPU0_RESET) << $apu) | \
+		$::CRF_APB_RST_FPD_APU_L2_RESET
+	}]
+	$axi write_memory $::CRF_APB_RST_FPD_APU 32 [expr {$val & ~$mask}]
+
+	core_up $apu
+	$::_TARGETNAME.$apu aarch64 dbginit
+}
+
+proc _rvbaraddr {apu} {
+	return [expr {$::APU_RVBARADDR_BASE + 8 * $apu}]
+}
+
+add_usage_text resume_apu {apu addr}
+add_help_text resume_apu "Resume an APU at a given address."
+proc resume_apu {apu addr} {
+	set addrl [expr {$addr & 0xffffffff}]
+	set addrh [expr {$addr >> 32}]
+	$::_CHIPNAME.axi write_memory [_rvbaraddr $apu] 32 [list $addrl $addrh]
+
+	release_apu $apu
+}
+
+add_usage_text start_apu {apu}
+add_help_text start_apu "Start an APU and put it into an infinite loop at\
+	RVBARADDR. This can be convenient if you just want to halt the APU\
+	(since it won't execute anything unusual)."
+proc start_apu {apu} {
+	set axi $::_CHIPNAME.axi
+	foreach {addrl addrh} [$axi read_memory [_rvbaraddr $apu] 32 2] {
+		set addr [expr {($addrh << 32) | $addrl}]
+	}
+	# write the infinite loop instruction
+	$axi write_memory $addr 32 0x14000000
+
+	release_apu $apu
+}
+
+add_usage_text boot_pmu {image}
+add_help_text boot_pmu "Boot the PMU with a given firmware image, loading it\
+	to the beginning of PMU RAM. The PMU ROM will jump to this location\
+	after we resume it."
+proc boot_pmu {image} {
+	halt_pmu
+	echo "Info : Loading PMU firmware $image to $::PMU_RAM_BASE"
+	load_image $image $::PMU_RAM_BASE
+	resume_pmu
+}
+
+add_usage_text boot_apu "image \[apu=0 \[addr=$OCM_RAM_BASE\]\]"
+add_help_text boot_apu "Boot an APU with a given firmware image. The default\
+	address is the beginning of OCM RAM. Upon success, the default target\
+	will be changed to the (running) apu."
+proc boot_apu [list image {apu 0} [list addr $OCM_RAM_BASE]] {
+	start_apu $apu
+	targets $::_TARGETNAME.$apu
+	halt
+
+	echo "Info : Loading APU$apu firmware $image to $addr"
+	load_image $image $addr
+	resume $addr
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xmc1xxx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xmc1xxx.cfg
new file mode 100644
index 0000000..cafd032
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xmc1xxx.cfg
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC1100/XMC1200/XMC1300 family (ARM Cortex-M0 @ 32 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xmc1000
+}
+
+#
+# Only SWD and SPD supported
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CPUTAPID] } {
+	set _CPU_SWD_TAPID $CPUTAPID
+} else {
+	set _CPU_SWD_TAPID 0x0BB11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+$_TARGETNAME configure -work-area-phys 0x20000000 \
+                       -work-area-size $_WORKAREASIZE \
+                       -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xmc4xxx.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xmc4xxx.cfg
new file mode 100644
index 0000000..0e28494
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xmc4xxx.cfg
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Infineon XMC4100/XMC4200/XMC4400/XMC4500 family (ARM Cortex-M4 @ 80-120 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xmc4000
+}
+
+source [find target/swj-dp.tcl]
+
+#
+# SWJ-DP
+#
+if { [info exists CPU_JTAG_TAPID] } {
+	set _CPU_JTAG_TAPID $CPU_JTAG_TAPID
+} else {
+	set _CPU_JTAG_TAPID 0x4BA00477
+}
+
+#
+# SW_DP
+#
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x2BA01477
+}
+
+if { [using_jtag] } {
+	set _CPU_TAPID $_CPU_JTAG_TAPID
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16 kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME xmc4xxx 0x0C000000 0 0 0 $_TARGETNAME
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+adapter speed 1000
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xmos_xs1-xau8a-10_arm.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xmos_xs1-xau8a-10_arm.cfg
new file mode 100644
index 0000000..60fe9ad
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xmos_xs1-xau8a-10_arm.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# XMOS xCORE-XA XS1-XAU8A-10: ARM Cortex-M3 @ 48 MHz
+#
+# http://www.xmos.com/products/silicon/xcore-xa/xa-series
+#
+
+if { ![info exists CHIPNAME] } {
+	set CHIPNAME xcorexa
+}
+
+if { ![info exists WORKAREASIZE] } {
+	# XS1-XAU8A-10-FB265: 128 KB SRAM
+	set WORKAREASIZE 0x20000
+}
+
+source [find target/efm32.cfg]
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-esp32.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-esp32.cfg
new file mode 100644
index 0000000..9a70072
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-esp32.cfg
@@ -0,0 +1,224 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa ESP32 target
+
+#  Core definition and ABI
+xtensa xtdef	LX
+xtensa xtopt	arnum				64
+xtensa xtopt	windowed			1
+
+#  Exception/Interrupt Options
+xtensa xtopt	exceptions			1
+xtensa xtopt	hipriints			1
+xtensa xtopt	intlevels			6
+xtensa xtopt	excmlevel			3
+
+#  Cache Options
+xtensa xtmem	icache				4 0 1
+xtensa xtmem	dcache				4 0 1 0
+
+#  Memory Options
+xtensa xtmem	irom				0x400D0000	0x330000
+xtensa xtmem	irom				0x40000000	0x64F00
+xtensa xtmem	iram				0x40070000	0x30000
+xtensa xtmem	iram				0x400C0000	0x2000
+xtensa xtmem	drom				0x3F400000	0x800000
+xtensa xtmem	drom				0x3FF90000	0x10000
+xtensa xtmem	dram				0x3FFAE000	0x52000
+xtensa xtmem	dram				0x3FF80000	0x2000
+xtensa xtmem	dram				0x3F800000	0x400000
+xtensa xtmem	dram				0x50000000	0x2000
+xtensa xtmem	dram				0x3FF00000	0x71000
+xtensa xtmem	dram				0x60000000	0x20000000
+
+#  Memory Protection/Translation Options
+
+#  Debug Options
+xtensa xtopt	debuglevel			6
+xtensa xtopt	ibreaknum			2
+xtensa xtopt	dbreaknum			2
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			1
+xtensa xtopt	perfcount			2
+
+#  Core Registers
+#  xtregfmt:	Optionally specify "contiguous" vs. "sparse" GDB register map.
+#				Default setting is "sparse" and is used with xt-gdb.
+#				If contiguous, optional parameter specifies number of registers
+#				in "Read General Registers" (g-packet) requests.
+#				NOTE: For contiguous format, registers listed in GDB order.
+#  xtregs:		Total number of Xtensa registers in the system
+xtensa xtregs	173
+xtensa xtregfmt	contiguous			105
+xtensa xtreg	pc					0x0020
+xtensa xtreg	ar0					0x0100
+xtensa xtreg	ar1					0x0101
+xtensa xtreg	ar2					0x0102
+xtensa xtreg	ar3					0x0103
+xtensa xtreg	ar4					0x0104
+xtensa xtreg	ar5					0x0105
+xtensa xtreg	ar6					0x0106
+xtensa xtreg	ar7					0x0107
+xtensa xtreg	ar8					0x0108
+xtensa xtreg	ar9					0x0109
+xtensa xtreg	ar10				0x010a
+xtensa xtreg	ar11				0x010b
+xtensa xtreg	ar12				0x010c
+xtensa xtreg	ar13				0x010d
+xtensa xtreg	ar14				0x010e
+xtensa xtreg	ar15				0x010f
+xtensa xtreg	ar16				0x0110
+xtensa xtreg	ar17				0x0111
+xtensa xtreg	ar18				0x0112
+xtensa xtreg	ar19				0x0113
+xtensa xtreg	ar20				0x0114
+xtensa xtreg	ar21				0x0115
+xtensa xtreg	ar22				0x0116
+xtensa xtreg	ar23				0x0117
+xtensa xtreg	ar24				0x0118
+xtensa xtreg	ar25				0x0119
+xtensa xtreg	ar26				0x011a
+xtensa xtreg	ar27				0x011b
+xtensa xtreg	ar28				0x011c
+xtensa xtreg	ar29				0x011d
+xtensa xtreg	ar30				0x011e
+xtensa xtreg	ar31				0x011f
+xtensa xtreg	ar32				0x0120
+xtensa xtreg	ar33				0x0121
+xtensa xtreg	ar34				0x0122
+xtensa xtreg	ar35				0x0123
+xtensa xtreg	ar36				0x0124
+xtensa xtreg	ar37				0x0125
+xtensa xtreg	ar38				0x0126
+xtensa xtreg	ar39				0x0127
+xtensa xtreg	ar40				0x0128
+xtensa xtreg	ar41				0x0129
+xtensa xtreg	ar42				0x012a
+xtensa xtreg	ar43				0x012b
+xtensa xtreg	ar44				0x012c
+xtensa xtreg	ar45				0x012d
+xtensa xtreg	ar46				0x012e
+xtensa xtreg	ar47				0x012f
+xtensa xtreg	ar48				0x0130
+xtensa xtreg	ar49				0x0131
+xtensa xtreg	ar50				0x0132
+xtensa xtreg	ar51				0x0133
+xtensa xtreg	ar52				0x0134
+xtensa xtreg	ar53				0x0135
+xtensa xtreg	ar54				0x0136
+xtensa xtreg	ar55				0x0137
+xtensa xtreg	ar56				0x0138
+xtensa xtreg	ar57				0x0139
+xtensa xtreg	ar58				0x013a
+xtensa xtreg	ar59				0x013b
+xtensa xtreg	ar60				0x013c
+xtensa xtreg	ar61				0x013d
+xtensa xtreg	ar62				0x013e
+xtensa xtreg	ar63				0x013f
+xtensa xtreg	lbeg				0x0200
+xtensa xtreg	lend				0x0201
+xtensa xtreg	lcount				0x0202
+xtensa xtreg	sar					0x0203
+xtensa xtreg	windowbase			0x0248
+xtensa xtreg	windowstart			0x0249
+xtensa xtreg	configid0			0x02b0
+xtensa xtreg	configid1			0x02d0
+xtensa xtreg	ps					0x02e6
+xtensa xtreg	threadptr			0x03e7
+xtensa xtreg	br					0x0204
+xtensa xtreg	scompare1			0x020c
+xtensa xtreg	acclo				0x0210
+xtensa xtreg	acchi				0x0211
+xtensa xtreg	m0					0x0220
+xtensa xtreg	m1					0x0221
+xtensa xtreg	m2					0x0222
+xtensa xtreg	m3					0x0223
+xtensa xtreg	expstate			0x03e6
+xtensa xtreg	f64r_lo				0x03ea
+xtensa xtreg	f64r_hi				0x03eb
+xtensa xtreg	f64s				0x03ec
+xtensa xtreg	f0					0x0030
+xtensa xtreg	f1					0x0031
+xtensa xtreg	f2					0x0032
+xtensa xtreg	f3					0x0033
+xtensa xtreg	f4					0x0034
+xtensa xtreg	f5					0x0035
+xtensa xtreg	f6					0x0036
+xtensa xtreg	f7					0x0037
+xtensa xtreg	f8					0x0038
+xtensa xtreg	f9					0x0039
+xtensa xtreg	f10					0x003a
+xtensa xtreg	f11					0x003b
+xtensa xtreg	f12					0x003c
+xtensa xtreg	f13					0x003d
+xtensa xtreg	f14					0x003e
+xtensa xtreg	f15					0x003f
+xtensa xtreg	fcr					0x03e8
+xtensa xtreg	fsr					0x03e9
+xtensa xtreg	mmid				0x0259
+xtensa xtreg	ibreakenable		0x0260
+xtensa xtreg	memctl				0x0261
+xtensa xtreg	atomctl				0x0263
+xtensa xtreg	ddr					0x0268
+xtensa xtreg	ibreaka0			0x0280
+xtensa xtreg	ibreaka1			0x0281
+xtensa xtreg	dbreaka0			0x0290
+xtensa xtreg	dbreaka1			0x0291
+xtensa xtreg	dbreakc0			0x02a0
+xtensa xtreg	dbreakc1			0x02a1
+xtensa xtreg	epc1				0x02b1
+xtensa xtreg	epc2				0x02b2
+xtensa xtreg	epc3				0x02b3
+xtensa xtreg	epc4				0x02b4
+xtensa xtreg	epc5				0x02b5
+xtensa xtreg	epc6				0x02b6
+xtensa xtreg	epc7				0x02b7
+xtensa xtreg	depc				0x02c0
+xtensa xtreg	eps2				0x02c2
+xtensa xtreg	eps3				0x02c3
+xtensa xtreg	eps4				0x02c4
+xtensa xtreg	eps5				0x02c5
+xtensa xtreg	eps6				0x02c6
+xtensa xtreg	eps7				0x02c7
+xtensa xtreg	excsave1			0x02d1
+xtensa xtreg	excsave2			0x02d2
+xtensa xtreg	excsave3			0x02d3
+xtensa xtreg	excsave4			0x02d4
+xtensa xtreg	excsave5			0x02d5
+xtensa xtreg	excsave6			0x02d6
+xtensa xtreg	excsave7			0x02d7
+xtensa xtreg	cpenable			0x02e0
+xtensa xtreg	interrupt			0x02e2
+xtensa xtreg	intset				0x02e2
+xtensa xtreg	intclear			0x02e3
+xtensa xtreg	intenable			0x02e4
+xtensa xtreg	vecbase				0x02e7
+xtensa xtreg	exccause			0x02e8
+xtensa xtreg	debugcause			0x02e9
+xtensa xtreg	ccount				0x02ea
+xtensa xtreg	prid				0x02eb
+xtensa xtreg	icount				0x02ec
+xtensa xtreg	icountlevel			0x02ed
+xtensa xtreg	excvaddr			0x02ee
+xtensa xtreg	ccompare0			0x02f0
+xtensa xtreg	ccompare1			0x02f1
+xtensa xtreg	ccompare2			0x02f2
+xtensa xtreg	misc0				0x02f4
+xtensa xtreg	misc1				0x02f5
+xtensa xtreg	misc2				0x02f6
+xtensa xtreg	misc3				0x02f7
+xtensa xtreg	a0					0x0000
+xtensa xtreg	a1					0x0001
+xtensa xtreg	a2					0x0002
+xtensa xtreg	a3					0x0003
+xtensa xtreg	a4					0x0004
+xtensa xtreg	a5					0x0005
+xtensa xtreg	a6					0x0006
+xtensa xtreg	a7					0x0007
+xtensa xtreg	a8					0x0008
+xtensa xtreg	a9					0x0009
+xtensa xtreg	a10					0x000a
+xtensa xtreg	a11					0x000b
+xtensa xtreg	a12					0x000c
+xtensa xtreg	a13					0x000d
+xtensa xtreg	a14					0x000e
+xtensa xtreg	a15					0x000f
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-esp32s2.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-esp32s2.cfg
new file mode 100644
index 0000000..b38cb1d
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-esp32s2.cfg
@@ -0,0 +1,223 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa ESP32S2 target
+
+#  Core definition and ABI
+xtensa xtdef	LX
+xtensa xtopt	arnum				64
+xtensa xtopt	windowed			1
+
+#  Exception/Interrupt Options
+xtensa xtopt	exceptions			1
+xtensa xtopt	hipriints			1
+xtensa xtopt	intlevels			6
+xtensa xtopt	excmlevel			3
+
+#  Cache Options
+xtensa xtmem	icache				4 0 1
+xtensa xtmem	dcache				4 0 1 0
+
+#  Memory Options
+xtensa xtmem	irom				0x40080000	0x780000
+xtensa xtmem	irom				0x40000000	0x20000
+xtensa xtmem	iram				0x40020000	0x50000
+xtensa xtmem	iram				0x40070000	0x2000
+xtensa xtmem	drom				0x3F000000	0x400000
+xtensa xtmem	drom				0x3F4D3FFC	0xAAC004
+xtensa xtmem	drom				0x3FFA0000	0x10000
+xtensa xtmem	dram				0x3FFB0000	0x50000
+xtensa xtmem	dram				0x3FF9E000	0x2000
+xtensa xtmem	dram				0x50000000	0x2000
+xtensa xtmem	dram				0x3F500000	0xA80000
+xtensa xtmem	dram				0x3F400000	0xD3FFC
+xtensa xtmem	dram				0x60000000	0x20000000
+
+#  Memory Protection/Translation Options
+
+#  Debug Options
+xtensa xtopt	debuglevel			6
+xtensa xtopt	ibreaknum			2
+xtensa xtopt	dbreaknum			2
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			0
+xtensa xtopt	perfcount			2
+
+#  Core Registers
+#  xtregfmt:	Optionally specify "contiguous" vs. "sparse" GDB register map.
+#				Default setting is "sparse" and is used with xt-gdb.
+#				If contiguous, optional parameter specifies number of registers
+#				in "Read General Registers" (g-packet) requests.
+#				NOTE: For contiguous format, registers listed in GDB order.
+#  xtregs:		Total number of Xtensa registers in the system
+xtensa xtregs	171
+xtensa xtregfmt	contiguous			73
+xtensa xtreg	pc					0x0020
+xtensa xtreg	ar0					0x0100
+xtensa xtreg	ar1					0x0101
+xtensa xtreg	ar2					0x0102
+xtensa xtreg	ar3					0x0103
+xtensa xtreg	ar4					0x0104
+xtensa xtreg	ar5					0x0105
+xtensa xtreg	ar6					0x0106
+xtensa xtreg	ar7					0x0107
+xtensa xtreg	ar8					0x0108
+xtensa xtreg	ar9					0x0109
+xtensa xtreg	ar10				0x010a
+xtensa xtreg	ar11				0x010b
+xtensa xtreg	ar12				0x010c
+xtensa xtreg	ar13				0x010d
+xtensa xtreg	ar14				0x010e
+xtensa xtreg	ar15				0x010f
+xtensa xtreg	ar16				0x0110
+xtensa xtreg	ar17				0x0111
+xtensa xtreg	ar18				0x0112
+xtensa xtreg	ar19				0x0113
+xtensa xtreg	ar20				0x0114
+xtensa xtreg	ar21				0x0115
+xtensa xtreg	ar22				0x0116
+xtensa xtreg	ar23				0x0117
+xtensa xtreg	ar24				0x0118
+xtensa xtreg	ar25				0x0119
+xtensa xtreg	ar26				0x011a
+xtensa xtreg	ar27				0x011b
+xtensa xtreg	ar28				0x011c
+xtensa xtreg	ar29				0x011d
+xtensa xtreg	ar30				0x011e
+xtensa xtreg	ar31				0x011f
+xtensa xtreg	ar32				0x0120
+xtensa xtreg	ar33				0x0121
+xtensa xtreg	ar34				0x0122
+xtensa xtreg	ar35				0x0123
+xtensa xtreg	ar36				0x0124
+xtensa xtreg	ar37				0x0125
+xtensa xtreg	ar38				0x0126
+xtensa xtreg	ar39				0x0127
+xtensa xtreg	ar40				0x0128
+xtensa xtreg	ar41				0x0129
+xtensa xtreg	ar42				0x012a
+xtensa xtreg	ar43				0x012b
+xtensa xtreg	ar44				0x012c
+xtensa xtreg	ar45				0x012d
+xtensa xtreg	ar46				0x012e
+xtensa xtreg	ar47				0x012f
+xtensa xtreg	ar48				0x0130
+xtensa xtreg	ar49				0x0131
+xtensa xtreg	ar50				0x0132
+xtensa xtreg	ar51				0x0133
+xtensa xtreg	ar52				0x0134
+xtensa xtreg	ar53				0x0135
+xtensa xtreg	ar54				0x0136
+xtensa xtreg	ar55				0x0137
+xtensa xtreg	ar56				0x0138
+xtensa xtreg	ar57				0x0139
+xtensa xtreg	ar58				0x013a
+xtensa xtreg	ar59				0x013b
+xtensa xtreg	ar60				0x013c
+xtensa xtreg	ar61				0x013d
+xtensa xtreg	ar62				0x013e
+xtensa xtreg	ar63				0x013f
+xtensa xtreg	sar					0x0203
+xtensa xtreg	windowbase			0x0248
+xtensa xtreg	windowstart			0x0249
+xtensa xtreg	configid0			0x02b0
+xtensa xtreg	configid1			0x02d0
+xtensa xtreg	ps					0x02e6
+xtensa xtreg	threadptr			0x03e7
+xtensa xtreg	gpio_out			0x0300
+xtensa xtreg	mmid				0x0259
+xtensa xtreg	ibreakenable		0x0260
+xtensa xtreg	ddr					0x0268
+xtensa xtreg	ibreaka0			0x0280
+xtensa xtreg	ibreaka1			0x0281
+xtensa xtreg	dbreaka0			0x0290
+xtensa xtreg	dbreaka1			0x0291
+xtensa xtreg	dbreakc0			0x02a0
+xtensa xtreg	dbreakc1			0x02a1
+xtensa xtreg	epc1				0x02b1
+xtensa xtreg	epc2				0x02b2
+xtensa xtreg	epc3				0x02b3
+xtensa xtreg	epc4				0x02b4
+xtensa xtreg	epc5				0x02b5
+xtensa xtreg	epc6				0x02b6
+xtensa xtreg	epc7				0x02b7
+xtensa xtreg	depc				0x02c0
+xtensa xtreg	eps2				0x02c2
+xtensa xtreg	eps3				0x02c3
+xtensa xtreg	eps4				0x02c4
+xtensa xtreg	eps5				0x02c5
+xtensa xtreg	eps6				0x02c6
+xtensa xtreg	eps7				0x02c7
+xtensa xtreg	excsave1			0x02d1
+xtensa xtreg	excsave2			0x02d2
+xtensa xtreg	excsave3			0x02d3
+xtensa xtreg	excsave4			0x02d4
+xtensa xtreg	excsave5			0x02d5
+xtensa xtreg	excsave6			0x02d6
+xtensa xtreg	excsave7			0x02d7
+xtensa xtreg	cpenable			0x02e0
+xtensa xtreg	interrupt			0x02e2
+xtensa xtreg	intset				0x02e2
+xtensa xtreg	intclear			0x02e3
+xtensa xtreg	intenable			0x02e4
+xtensa xtreg	vecbase				0x02e7
+xtensa xtreg	exccause			0x02e8
+xtensa xtreg	debugcause			0x02e9
+xtensa xtreg	ccount				0x02ea
+xtensa xtreg	prid				0x02eb
+xtensa xtreg	icount				0x02ec
+xtensa xtreg	icountlevel			0x02ed
+xtensa xtreg	excvaddr			0x02ee
+xtensa xtreg	ccompare0			0x02f0
+xtensa xtreg	ccompare1			0x02f1
+xtensa xtreg	ccompare2			0x02f2
+xtensa xtreg	misc0				0x02f4
+xtensa xtreg	misc1				0x02f5
+xtensa xtreg	misc2				0x02f6
+xtensa xtreg	misc3				0x02f7
+xtensa xtreg	pwrctl				0x2014
+xtensa xtreg	pwrstat				0x2015
+xtensa xtreg	eristat				0x2016
+xtensa xtreg	cs_itctrl			0x2017
+xtensa xtreg	cs_claimset			0x2018
+xtensa xtreg	cs_claimclr			0x2019
+xtensa xtreg	cs_lockaccess		0x201a
+xtensa xtreg	cs_lockstatus		0x201b
+xtensa xtreg	cs_authstatus		0x201c
+xtensa xtreg	fault_info			0x202b
+xtensa xtreg	trax_id				0x202c
+xtensa xtreg	trax_control		0x202d
+xtensa xtreg	trax_status			0x202e
+xtensa xtreg	trax_data			0x202f
+xtensa xtreg	trax_address		0x2030
+xtensa xtreg	trax_pctrigger		0x2031
+xtensa xtreg	trax_pcmatch		0x2032
+xtensa xtreg	trax_delay			0x2033
+xtensa xtreg	trax_memstart		0x2034
+xtensa xtreg	trax_memend			0x2035
+xtensa xtreg	pmg					0x2043
+xtensa xtreg	pmpc				0x2044
+xtensa xtreg	pm0					0x2045
+xtensa xtreg	pm1					0x2046
+xtensa xtreg	pmctrl0				0x2047
+xtensa xtreg	pmctrl1				0x2048
+xtensa xtreg	pmstat0				0x2049
+xtensa xtreg	pmstat1				0x204a
+xtensa xtreg	ocdid				0x204b
+xtensa xtreg	ocd_dcrclr			0x204c
+xtensa xtreg	ocd_dcrset			0x204d
+xtensa xtreg	ocd_dsr				0x204e
+xtensa xtreg	a0					0x0000
+xtensa xtreg	a1					0x0001
+xtensa xtreg	a2					0x0002
+xtensa xtreg	a3					0x0003
+xtensa xtreg	a4					0x0004
+xtensa xtreg	a5					0x0005
+xtensa xtreg	a6					0x0006
+xtensa xtreg	a7					0x0007
+xtensa xtreg	a8					0x0008
+xtensa xtreg	a9					0x0009
+xtensa xtreg	a10					0x000a
+xtensa xtreg	a11					0x000b
+xtensa xtreg	a12					0x000c
+xtensa xtreg	a13					0x000d
+xtensa xtreg	a14					0x000e
+xtensa xtreg	a15					0x000f
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-esp32s3.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-esp32s3.cfg
new file mode 100644
index 0000000..b3f20e3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-esp32s3.cfg
@@ -0,0 +1,276 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa ESP32S3 target
+
+#  Core definition and ABI
+xtensa xtdef	LX
+xtensa xtopt	arnum				64
+xtensa xtopt	windowed			1
+
+#  Exception/Interrupt Options
+xtensa xtopt	exceptions			1
+xtensa xtopt	hipriints			1
+xtensa xtopt	intlevels			6
+xtensa xtopt	excmlevel			3
+
+#  Cache Options
+
+#  Memory Options
+xtensa xtmem	irom				0x42000000	0x2000000
+xtensa xtmem	irom				0x40000000	0x60000
+xtensa xtmem	iram				0x40370000	0x70000
+xtensa xtmem	iram				0x600FE000	0x2000
+xtensa xtmem	drom				0x3C000000	0x1000000
+xtensa xtmem	drom				0x3FF00000	0x20000
+xtensa xtmem	dram				0x3FC88000	0x78000
+xtensa xtmem	dram				0x600FE000	0x2000
+xtensa xtmem	dram				0x50000000	0x2000
+xtensa xtmem	dram				0x60000000	0x10000000
+
+#  Memory Protection/Translation Options
+
+#  Debug Options
+xtensa xtopt	debuglevel			6
+xtensa xtopt	ibreaknum			2
+xtensa xtopt	dbreaknum			2
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			0
+xtensa xtopt	perfcount			2
+
+
+#  Core Registers
+#  xtregfmt:	Optionally specify "contiguous" vs. "sparse" GDB register map.
+#				Default setting is "sparse" and is used with xt-gdb.
+#				If contiguous, optional parameter specifies number of registers
+#				in "Read General Registers" (g-packet) requests.
+#				NOTE: For contiguous format, registers listed in GDB order.
+#  xtregs:		Total number of Xtensa registers in the system
+xtensa xtregs	228
+xtensa xtregfmt	contiguous			128
+xtensa xtreg	pc					0x0020
+xtensa xtreg	ar0					0x0100
+xtensa xtreg	ar1					0x0101
+xtensa xtreg	ar2					0x0102
+xtensa xtreg	ar3					0x0103
+xtensa xtreg	ar4					0x0104
+xtensa xtreg	ar5					0x0105
+xtensa xtreg	ar6					0x0106
+xtensa xtreg	ar7					0x0107
+xtensa xtreg	ar8					0x0108
+xtensa xtreg	ar9					0x0109
+xtensa xtreg	ar10				0x010a
+xtensa xtreg	ar11				0x010b
+xtensa xtreg	ar12				0x010c
+xtensa xtreg	ar13				0x010d
+xtensa xtreg	ar14				0x010e
+xtensa xtreg	ar15				0x010f
+xtensa xtreg	ar16				0x0110
+xtensa xtreg	ar17				0x0111
+xtensa xtreg	ar18				0x0112
+xtensa xtreg	ar19				0x0113
+xtensa xtreg	ar20				0x0114
+xtensa xtreg	ar21				0x0115
+xtensa xtreg	ar22				0x0116
+xtensa xtreg	ar23				0x0117
+xtensa xtreg	ar24				0x0118
+xtensa xtreg	ar25				0x0119
+xtensa xtreg	ar26				0x011a
+xtensa xtreg	ar27				0x011b
+xtensa xtreg	ar28				0x011c
+xtensa xtreg	ar29				0x011d
+xtensa xtreg	ar30				0x011e
+xtensa xtreg	ar31				0x011f
+xtensa xtreg	ar32				0x0120
+xtensa xtreg	ar33				0x0121
+xtensa xtreg	ar34				0x0122
+xtensa xtreg	ar35				0x0123
+xtensa xtreg	ar36				0x0124
+xtensa xtreg	ar37				0x0125
+xtensa xtreg	ar38				0x0126
+xtensa xtreg	ar39				0x0127
+xtensa xtreg	ar40				0x0128
+xtensa xtreg	ar41				0x0129
+xtensa xtreg	ar42				0x012a
+xtensa xtreg	ar43				0x012b
+xtensa xtreg	ar44				0x012c
+xtensa xtreg	ar45				0x012d
+xtensa xtreg	ar46				0x012e
+xtensa xtreg	ar47				0x012f
+xtensa xtreg	ar48				0x0130
+xtensa xtreg	ar49				0x0131
+xtensa xtreg	ar50				0x0132
+xtensa xtreg	ar51				0x0133
+xtensa xtreg	ar52				0x0134
+xtensa xtreg	ar53				0x0135
+xtensa xtreg	ar54				0x0136
+xtensa xtreg	ar55				0x0137
+xtensa xtreg	ar56				0x0138
+xtensa xtreg	ar57				0x0139
+xtensa xtreg	ar58				0x013a
+xtensa xtreg	ar59				0x013b
+xtensa xtreg	ar60				0x013c
+xtensa xtreg	ar61				0x013d
+xtensa xtreg	ar62				0x013e
+xtensa xtreg	ar63				0x013f
+xtensa xtreg	lbeg				0x0200
+xtensa xtreg	lend				0x0201
+xtensa xtreg	lcount				0x0202
+xtensa xtreg	sar					0x0203
+xtensa xtreg	windowbase			0x0248
+xtensa xtreg	windowstart			0x0249
+xtensa xtreg	configid0			0x02b0
+xtensa xtreg	configid1			0x02d0
+xtensa xtreg	ps					0x02e6
+xtensa xtreg	threadptr			0x03e7
+xtensa xtreg	br					0x0204
+xtensa xtreg	scompare1			0x020c
+xtensa xtreg	acclo				0x0210
+xtensa xtreg	acchi				0x0211
+xtensa xtreg	m0					0x0220
+xtensa xtreg	m1					0x0221
+xtensa xtreg	m2					0x0222
+xtensa xtreg	m3					0x0223
+xtensa xtreg	gpio_out			0x030c
+xtensa xtreg	f0					0x0030
+xtensa xtreg	f1					0x0031
+xtensa xtreg	f2					0x0032
+xtensa xtreg	f3					0x0033
+xtensa xtreg	f4					0x0034
+xtensa xtreg	f5					0x0035
+xtensa xtreg	f6					0x0036
+xtensa xtreg	f7					0x0037
+xtensa xtreg	f8					0x0038
+xtensa xtreg	f9					0x0039
+xtensa xtreg	f10					0x003a
+xtensa xtreg	f11					0x003b
+xtensa xtreg	f12					0x003c
+xtensa xtreg	f13					0x003d
+xtensa xtreg	f14					0x003e
+xtensa xtreg	f15					0x003f
+xtensa xtreg	fcr					0x03e8
+xtensa xtreg	fsr					0x03e9
+xtensa xtreg	accx_0				0x0300
+xtensa xtreg	accx_1				0x0301
+xtensa xtreg	qacc_h_0			0x0302
+xtensa xtreg	qacc_h_1			0x0303
+xtensa xtreg	qacc_h_2			0x0304
+xtensa xtreg	qacc_h_3			0x0305
+xtensa xtreg	qacc_h_4			0x0306
+xtensa xtreg	qacc_l_0			0x0307
+xtensa xtreg	qacc_l_1			0x0308
+xtensa xtreg	qacc_l_2			0x0309
+xtensa xtreg	qacc_l_3			0x030a
+xtensa xtreg	qacc_l_4			0x030b
+xtensa xtreg	sar_byte			0x030d
+xtensa xtreg	fft_bit_width		0x030e
+xtensa xtreg	ua_state_0			0x030f
+xtensa xtreg	ua_state_1			0x0310
+xtensa xtreg	ua_state_2			0x0311
+xtensa xtreg	ua_state_3			0x0312
+xtensa xtreg	q0					0x1008
+xtensa xtreg	q1					0x1009
+xtensa xtreg	q2					0x100a
+xtensa xtreg	q3					0x100b
+xtensa xtreg	q4					0x100c
+xtensa xtreg	q5					0x100d
+xtensa xtreg	q6					0x100e
+xtensa xtreg	q7					0x100f
+xtensa xtreg	mmid				0x0259
+xtensa xtreg	ibreakenable		0x0260
+xtensa xtreg	memctl				0x0261
+xtensa xtreg	atomctl				0x0263
+xtensa xtreg	ddr					0x0268
+xtensa xtreg	ibreaka0			0x0280
+xtensa xtreg	ibreaka1			0x0281
+xtensa xtreg	dbreaka0			0x0290
+xtensa xtreg	dbreaka1			0x0291
+xtensa xtreg	dbreakc0			0x02a0
+xtensa xtreg	dbreakc1			0x02a1
+xtensa xtreg	epc1				0x02b1
+xtensa xtreg	epc2				0x02b2
+xtensa xtreg	epc3				0x02b3
+xtensa xtreg	epc4				0x02b4
+xtensa xtreg	epc5				0x02b5
+xtensa xtreg	epc6				0x02b6
+xtensa xtreg	epc7				0x02b7
+xtensa xtreg	depc				0x02c0
+xtensa xtreg	eps2				0x02c2
+xtensa xtreg	eps3				0x02c3
+xtensa xtreg	eps4				0x02c4
+xtensa xtreg	eps5				0x02c5
+xtensa xtreg	eps6				0x02c6
+xtensa xtreg	eps7				0x02c7
+xtensa xtreg	excsave1			0x02d1
+xtensa xtreg	excsave2			0x02d2
+xtensa xtreg	excsave3			0x02d3
+xtensa xtreg	excsave4			0x02d4
+xtensa xtreg	excsave5			0x02d5
+xtensa xtreg	excsave6			0x02d6
+xtensa xtreg	excsave7			0x02d7
+xtensa xtreg	cpenable			0x02e0
+xtensa xtreg	interrupt			0x02e2
+xtensa xtreg	intset				0x02e2
+xtensa xtreg	intclear			0x02e3
+xtensa xtreg	intenable			0x02e4
+xtensa xtreg	vecbase				0x02e7
+xtensa xtreg	exccause			0x02e8
+xtensa xtreg	debugcause			0x02e9
+xtensa xtreg	ccount				0x02ea
+xtensa xtreg	prid				0x02eb
+xtensa xtreg	icount				0x02ec
+xtensa xtreg	icountlevel			0x02ed
+xtensa xtreg	excvaddr			0x02ee
+xtensa xtreg	ccompare0			0x02f0
+xtensa xtreg	ccompare1			0x02f1
+xtensa xtreg	ccompare2			0x02f2
+xtensa xtreg	misc0				0x02f4
+xtensa xtreg	misc1				0x02f5
+xtensa xtreg	misc2				0x02f6
+xtensa xtreg	misc3				0x02f7
+xtensa xtreg	pwrctl				0x2028
+xtensa xtreg	pwrstat				0x2029
+xtensa xtreg	eristat				0x202a
+xtensa xtreg	cs_itctrl			0x202b
+xtensa xtreg	cs_claimset			0x202c
+xtensa xtreg	cs_claimclr			0x202d
+xtensa xtreg	cs_lockaccess		0x202e
+xtensa xtreg	cs_lockstatus		0x202f
+xtensa xtreg	cs_authstatus		0x2030
+xtensa xtreg	fault_info			0x203f
+xtensa xtreg	trax_id				0x2040
+xtensa xtreg	trax_control		0x2041
+xtensa xtreg	trax_status			0x2042
+xtensa xtreg	trax_data			0x2043
+xtensa xtreg	trax_address		0x2044
+xtensa xtreg	trax_pctrigger		0x2045
+xtensa xtreg	trax_pcmatch		0x2046
+xtensa xtreg	trax_delay			0x2047
+xtensa xtreg	trax_memstart		0x2048
+xtensa xtreg	trax_memend			0x2049
+xtensa xtreg	pmg					0x2057
+xtensa xtreg	pmpc				0x2058
+xtensa xtreg	pm0					0x2059
+xtensa xtreg	pm1					0x205a
+xtensa xtreg	pmctrl0				0x205b
+xtensa xtreg	pmctrl1				0x205c
+xtensa xtreg	pmstat0				0x205d
+xtensa xtreg	pmstat1				0x205e
+xtensa xtreg	ocdid				0x205f
+xtensa xtreg	ocd_dcrclr			0x2060
+xtensa xtreg	ocd_dcrset			0x2061
+xtensa xtreg	ocd_dsr				0x2062
+xtensa xtreg	a0					0x0000
+xtensa xtreg	a1					0x0001
+xtensa xtreg	a2					0x0002
+xtensa xtreg	a3					0x0003
+xtensa xtreg	a4					0x0004
+xtensa xtreg	a5					0x0005
+xtensa xtreg	a6					0x0006
+xtensa xtreg	a7					0x0007
+xtensa xtreg	a8					0x0008
+xtensa xtreg	a9					0x0009
+xtensa xtreg	a10					0x000a
+xtensa xtreg	a11					0x000b
+xtensa xtreg	a12					0x000c
+xtensa xtreg	a13					0x000d
+xtensa xtreg	a14					0x000e
+xtensa xtreg	a15					0x000f
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-nxp_rt600.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-nxp_rt600.cfg
new file mode 100644
index 0000000..ca7fd68
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-nxp_rt600.cfg
@@ -0,0 +1,255 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa HiFi DSP in NXP RT600 target
+
+
+#  Core instance default definition
+if { [info exists XTNAME] } {
+    set _XTNAME $XTNAME
+} else {
+    set _XTNAME xtensa.cpu
+}
+
+
+#  Core definition and ABI
+$_XTNAME xtensa xtdef	LX
+$_XTNAME xtensa xtopt	arnum           	32
+$_XTNAME xtensa xtopt	windowed        	1
+
+
+#  Exception/Interrupt Options
+$_XTNAME xtensa xtopt	exceptions      	1
+$_XTNAME xtensa xtopt	hipriints       	1
+$_XTNAME xtensa xtopt	intlevels       	4
+$_XTNAME xtensa xtopt	excmlevel       	2
+
+
+#  Cache Options
+$_XTNAME xtensa xtmem	icache          	256	32768	4
+$_XTNAME xtensa xtmem	dcache          	256	65536	4	1
+
+
+#  Memory Options
+$_XTNAME xtensa xtmem	iram            	0x24020000	65536
+$_XTNAME xtensa xtmem	dram            	0x24000000	65536
+$_XTNAME xtensa xtmem	sram            	0x00000000	603979776
+
+
+#  Memory Protection/Translation Options
+
+
+#  Debug Options
+$_XTNAME xtensa xtopt	debuglevel      	4
+$_XTNAME xtensa xtopt	ibreaknum       	2
+$_XTNAME xtensa xtopt	dbreaknum       	2
+
+
+#  Core Registers
+$_XTNAME xtensa xtregs	208
+$_XTNAME xtensa xtreg	pc              	0x0020
+$_XTNAME xtensa xtreg	ar0             	0x0100
+$_XTNAME xtensa xtreg	ar1             	0x0101
+$_XTNAME xtensa xtreg	ar2             	0x0102
+$_XTNAME xtensa xtreg	ar3             	0x0103
+$_XTNAME xtensa xtreg	ar4             	0x0104
+$_XTNAME xtensa xtreg	ar5             	0x0105
+$_XTNAME xtensa xtreg	ar6             	0x0106
+$_XTNAME xtensa xtreg	ar7             	0x0107
+$_XTNAME xtensa xtreg	ar8             	0x0108
+$_XTNAME xtensa xtreg	ar9             	0x0109
+$_XTNAME xtensa xtreg	ar10            	0x010a
+$_XTNAME xtensa xtreg	ar11            	0x010b
+$_XTNAME xtensa xtreg	ar12            	0x010c
+$_XTNAME xtensa xtreg	ar13            	0x010d
+$_XTNAME xtensa xtreg	ar14            	0x010e
+$_XTNAME xtensa xtreg	ar15            	0x010f
+$_XTNAME xtensa xtreg	ar16            	0x0110
+$_XTNAME xtensa xtreg	ar17            	0x0111
+$_XTNAME xtensa xtreg	ar18            	0x0112
+$_XTNAME xtensa xtreg	ar19            	0x0113
+$_XTNAME xtensa xtreg	ar20            	0x0114
+$_XTNAME xtensa xtreg	ar21            	0x0115
+$_XTNAME xtensa xtreg	ar22            	0x0116
+$_XTNAME xtensa xtreg	ar23            	0x0117
+$_XTNAME xtensa xtreg	ar24            	0x0118
+$_XTNAME xtensa xtreg	ar25            	0x0119
+$_XTNAME xtensa xtreg	ar26            	0x011a
+$_XTNAME xtensa xtreg	ar27            	0x011b
+$_XTNAME xtensa xtreg	ar28            	0x011c
+$_XTNAME xtensa xtreg	ar29            	0x011d
+$_XTNAME xtensa xtreg	ar30            	0x011e
+$_XTNAME xtensa xtreg	ar31            	0x011f
+$_XTNAME xtensa xtreg	lbeg            	0x0200
+$_XTNAME xtensa xtreg	lend            	0x0201
+$_XTNAME xtensa xtreg	lcount          	0x0202
+$_XTNAME xtensa xtreg	sar             	0x0203
+$_XTNAME xtensa xtreg	prefctl         	0x0228
+$_XTNAME xtensa xtreg	windowbase      	0x0248
+$_XTNAME xtensa xtreg	windowstart     	0x0249
+$_XTNAME xtensa xtreg	configid0       	0x02b0
+$_XTNAME xtensa xtreg	configid1       	0x02d0
+$_XTNAME xtensa xtreg	ps              	0x02e6
+$_XTNAME xtensa xtreg	threadptr       	0x03e7
+$_XTNAME xtensa xtreg	br              	0x0204
+$_XTNAME xtensa xtreg	scompare1       	0x020c
+$_XTNAME xtensa xtreg	acclo           	0x0210
+$_XTNAME xtensa xtreg	acchi           	0x0211
+$_XTNAME xtensa xtreg	m0              	0x0220
+$_XTNAME xtensa xtreg	m1              	0x0221
+$_XTNAME xtensa xtreg	m2              	0x0222
+$_XTNAME xtensa xtreg	m3              	0x0223
+$_XTNAME xtensa xtreg	expstate        	0x03e6
+$_XTNAME xtensa xtreg	f64r_lo         	0x03ea
+$_XTNAME xtensa xtreg	f64r_hi         	0x03eb
+$_XTNAME xtensa xtreg	f64s            	0x03ec
+$_XTNAME xtensa xtreg	ae_ovf_sar      	0x03f0
+$_XTNAME xtensa xtreg	ae_bithead      	0x03f1
+$_XTNAME xtensa xtreg	ae_ts_fts_bu_bp 	0x03f2
+$_XTNAME xtensa xtreg	ae_cw_sd_no     	0x03f3
+$_XTNAME xtensa xtreg	ae_cbegin0      	0x03f6
+$_XTNAME xtensa xtreg	ae_cend0        	0x03f7
+$_XTNAME xtensa xtreg	ae_cbegin1      	0x03f8
+$_XTNAME xtensa xtreg	ae_cend1        	0x03f9
+$_XTNAME xtensa xtreg	aed0            	0x1010
+$_XTNAME xtensa xtreg	aed1            	0x1011
+$_XTNAME xtensa xtreg	aed2            	0x1012
+$_XTNAME xtensa xtreg	aed3            	0x1013
+$_XTNAME xtensa xtreg	aed4            	0x1014
+$_XTNAME xtensa xtreg	aed5            	0x1015
+$_XTNAME xtensa xtreg	aed6            	0x1016
+$_XTNAME xtensa xtreg	aed7            	0x1017
+$_XTNAME xtensa xtreg	aed8            	0x1018
+$_XTNAME xtensa xtreg	aed9            	0x1019
+$_XTNAME xtensa xtreg	aed10           	0x101a
+$_XTNAME xtensa xtreg	aed11           	0x101b
+$_XTNAME xtensa xtreg	aed12           	0x101c
+$_XTNAME xtensa xtreg	aed13           	0x101d
+$_XTNAME xtensa xtreg	aed14           	0x101e
+$_XTNAME xtensa xtreg	aed15           	0x101f
+$_XTNAME xtensa xtreg	u0              	0x1020
+$_XTNAME xtensa xtreg	u1              	0x1021
+$_XTNAME xtensa xtreg	u2              	0x1022
+$_XTNAME xtensa xtreg	u3              	0x1023
+$_XTNAME xtensa xtreg	aep0            	0x1024
+$_XTNAME xtensa xtreg	aep1            	0x1025
+$_XTNAME xtensa xtreg	aep2            	0x1026
+$_XTNAME xtensa xtreg	aep3            	0x1027
+$_XTNAME xtensa xtreg	fcr_fsr         	0x1029
+$_XTNAME xtensa xtreg	mmid            	0x0259
+$_XTNAME xtensa xtreg	ibreakenable    	0x0260
+$_XTNAME xtensa xtreg	memctl          	0x0261
+$_XTNAME xtensa xtreg	atomctl         	0x0263
+$_XTNAME xtensa xtreg	ddr             	0x0268
+$_XTNAME xtensa xtreg	ibreaka0        	0x0280
+$_XTNAME xtensa xtreg	ibreaka1        	0x0281
+$_XTNAME xtensa xtreg	dbreaka0        	0x0290
+$_XTNAME xtensa xtreg	dbreaka1        	0x0291
+$_XTNAME xtensa xtreg	dbreakc0        	0x02a0
+$_XTNAME xtensa xtreg	dbreakc1        	0x02a1
+$_XTNAME xtensa xtreg	epc1            	0x02b1
+$_XTNAME xtensa xtreg	epc2            	0x02b2
+$_XTNAME xtensa xtreg	epc3            	0x02b3
+$_XTNAME xtensa xtreg	epc4            	0x02b4
+$_XTNAME xtensa xtreg	epc5            	0x02b5
+$_XTNAME xtensa xtreg	depc            	0x02c0
+$_XTNAME xtensa xtreg	eps2            	0x02c2
+$_XTNAME xtensa xtreg	eps3            	0x02c3
+$_XTNAME xtensa xtreg	eps4            	0x02c4
+$_XTNAME xtensa xtreg	eps5            	0x02c5
+$_XTNAME xtensa xtreg	excsave1        	0x02d1
+$_XTNAME xtensa xtreg	excsave2        	0x02d2
+$_XTNAME xtensa xtreg	excsave3        	0x02d3
+$_XTNAME xtensa xtreg	excsave4        	0x02d4
+$_XTNAME xtensa xtreg	excsave5        	0x02d5
+$_XTNAME xtensa xtreg	cpenable        	0x02e0
+$_XTNAME xtensa xtreg	interrupt       	0x02e2
+$_XTNAME xtensa xtreg	intset          	0x02e2
+$_XTNAME xtensa xtreg	intclear        	0x02e3
+$_XTNAME xtensa xtreg	intenable       	0x02e4
+$_XTNAME xtensa xtreg	vecbase         	0x02e7
+$_XTNAME xtensa xtreg	exccause        	0x02e8
+$_XTNAME xtensa xtreg	debugcause      	0x02e9
+$_XTNAME xtensa xtreg	ccount          	0x02ea
+$_XTNAME xtensa xtreg	prid            	0x02eb
+$_XTNAME xtensa xtreg	icount          	0x02ec
+$_XTNAME xtensa xtreg	icountlevel     	0x02ed
+$_XTNAME xtensa xtreg	excvaddr        	0x02ee
+$_XTNAME xtensa xtreg	ccompare0       	0x02f0
+$_XTNAME xtensa xtreg	ccompare1       	0x02f1
+$_XTNAME xtensa xtreg	misc0           	0x02f4
+$_XTNAME xtensa xtreg	misc1           	0x02f5
+$_XTNAME xtensa xtreg	pwrctl          	0x2024
+$_XTNAME xtensa xtreg	pwrstat         	0x2025
+$_XTNAME xtensa xtreg	eristat         	0x2026
+$_XTNAME xtensa xtreg	cs_itctrl       	0x2027
+$_XTNAME xtensa xtreg	cs_claimset     	0x2028
+$_XTNAME xtensa xtreg	cs_claimclr     	0x2029
+$_XTNAME xtensa xtreg	cs_lockaccess   	0x202a
+$_XTNAME xtensa xtreg	cs_lockstatus   	0x202b
+$_XTNAME xtensa xtreg	cs_authstatus   	0x202c
+$_XTNAME xtensa xtreg	pmg             	0x203b
+$_XTNAME xtensa xtreg	pmpc            	0x203c
+$_XTNAME xtensa xtreg	pm0             	0x203d
+$_XTNAME xtensa xtreg	pm1             	0x203e
+$_XTNAME xtensa xtreg	pmctrl0         	0x203f
+$_XTNAME xtensa xtreg	pmctrl1         	0x2040
+$_XTNAME xtensa xtreg	pmstat0         	0x2041
+$_XTNAME xtensa xtreg	pmstat1         	0x2042
+$_XTNAME xtensa xtreg	ocdid           	0x2043
+$_XTNAME xtensa xtreg	ocd_dcrclr      	0x2044
+$_XTNAME xtensa xtreg	ocd_dcrset      	0x2045
+$_XTNAME xtensa xtreg	ocd_dsr         	0x2046
+$_XTNAME xtensa xtreg	a0              	0x0000
+$_XTNAME xtensa xtreg	a1              	0x0001
+$_XTNAME xtensa xtreg	a2              	0x0002
+$_XTNAME xtensa xtreg	a3              	0x0003
+$_XTNAME xtensa xtreg	a4              	0x0004
+$_XTNAME xtensa xtreg	a5              	0x0005
+$_XTNAME xtensa xtreg	a6              	0x0006
+$_XTNAME xtensa xtreg	a7              	0x0007
+$_XTNAME xtensa xtreg	a8              	0x0008
+$_XTNAME xtensa xtreg	a9              	0x0009
+$_XTNAME xtensa xtreg	a10             	0x000a
+$_XTNAME xtensa xtreg	a11             	0x000b
+$_XTNAME xtensa xtreg	a12             	0x000c
+$_XTNAME xtensa xtreg	a13             	0x000d
+$_XTNAME xtensa xtreg	a14             	0x000e
+$_XTNAME xtensa xtreg	a15             	0x000f
+$_XTNAME xtensa xtreg	b0              	0x0010
+$_XTNAME xtensa xtreg	b1              	0x0011
+$_XTNAME xtensa xtreg	b2              	0x0012
+$_XTNAME xtensa xtreg	b3              	0x0013
+$_XTNAME xtensa xtreg	b4              	0x0014
+$_XTNAME xtensa xtreg	b5              	0x0015
+$_XTNAME xtensa xtreg	b6              	0x0016
+$_XTNAME xtensa xtreg	b7              	0x0017
+$_XTNAME xtensa xtreg	b8              	0x0018
+$_XTNAME xtensa xtreg	b9              	0x0019
+$_XTNAME xtensa xtreg	b10             	0x001a
+$_XTNAME xtensa xtreg	b11             	0x001b
+$_XTNAME xtensa xtreg	b12             	0x001c
+$_XTNAME xtensa xtreg	b13             	0x001d
+$_XTNAME xtensa xtreg	b14             	0x001e
+$_XTNAME xtensa xtreg	b15             	0x001f
+$_XTNAME xtensa xtreg	psintlevel      	0x2006
+$_XTNAME xtensa xtreg	psum            	0x2007
+$_XTNAME xtensa xtreg	pswoe           	0x2008
+$_XTNAME xtensa xtreg	psexcm          	0x2009
+$_XTNAME xtensa xtreg	pscallinc       	0x200a
+$_XTNAME xtensa xtreg	psowb           	0x200b
+$_XTNAME xtensa xtreg	acc             	0x200c
+$_XTNAME xtensa xtreg	dbnum           	0x2011
+$_XTNAME xtensa xtreg	ae_overflow     	0x2014
+$_XTNAME xtensa xtreg	ae_sar          	0x2015
+$_XTNAME xtensa xtreg	ae_cwrap        	0x2016
+$_XTNAME xtensa xtreg	ae_bitptr       	0x2017
+$_XTNAME xtensa xtreg	ae_bitsused     	0x2018
+$_XTNAME xtensa xtreg	ae_tablesize    	0x2019
+$_XTNAME xtensa xtreg	ae_first_ts     	0x201a
+$_XTNAME xtensa xtreg	ae_nextoffset   	0x201b
+$_XTNAME xtensa xtreg	ae_searchdone   	0x201c
+$_XTNAME xtensa xtreg	roundmode       	0x201d
+$_XTNAME xtensa xtreg	invalidflag     	0x201e
+$_XTNAME xtensa xtreg	divzeroflag     	0x201f
+$_XTNAME xtensa xtreg	overflowflag    	0x2020
+$_XTNAME xtensa xtreg	underflowflag   	0x2021
+$_XTNAME xtensa xtreg	inexactflag     	0x2022
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-xt8.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-xt8.cfg
new file mode 100644
index 0000000..523dc74
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa-core-xt8.cfg
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa xt8 target
+
+
+#  Core instance default definition
+if { [info exists XTNAME] } {
+    set _XTNAME $XTNAME
+} else {
+    set _XTNAME xtensa
+}
+
+
+#  Core definition and ABI
+$_XTNAME xtensa xtdef	LX
+$_XTNAME xtensa xtopt	arnum           	32
+$_XTNAME xtensa xtopt	windowed        	1
+
+
+#  Exception/Interrupt Options
+$_XTNAME xtensa xtopt	exceptions      	1
+$_XTNAME xtensa xtopt	hipriints       	1
+$_XTNAME xtensa xtopt	intlevels       	3
+$_XTNAME xtensa xtopt	excmlevel       	1
+
+
+#  Cache Options
+$_XTNAME xtensa xtmem	icache          	16	1024	1
+$_XTNAME xtensa xtmem	dcache          	16	1024	1	1
+
+
+#  Memory Options
+$_XTNAME xtensa xtmem	iram            	0x40000000	1048576
+$_XTNAME xtensa xtmem	dram            	0x3ff00000	262144
+$_XTNAME xtensa xtmem	srom            	0x50000000	131072
+$_XTNAME xtensa xtmem	sram            	0x60000000	4194304
+
+
+#  Memory Protection/Translation Options
+
+
+#  Debug Options
+$_XTNAME xtensa xtopt	debuglevel      	3
+$_XTNAME xtensa xtopt	ibreaknum       	2
+$_XTNAME xtensa xtopt	dbreaknum       	2
+
+
+#  Core Registers
+$_XTNAME xtensa xtregs	127
+$_XTNAME xtensa xtreg	a0              	0x0000
+$_XTNAME xtensa xtreg	a1              	0x0001
+$_XTNAME xtensa xtreg	a2              	0x0002
+$_XTNAME xtensa xtreg	a3              	0x0003
+$_XTNAME xtensa xtreg	a4              	0x0004
+$_XTNAME xtensa xtreg	a5              	0x0005
+$_XTNAME xtensa xtreg	a6              	0x0006
+$_XTNAME xtensa xtreg	a7              	0x0007
+$_XTNAME xtensa xtreg	a8              	0x0008
+$_XTNAME xtensa xtreg	a9              	0x0009
+$_XTNAME xtensa xtreg	a10             	0x000a
+$_XTNAME xtensa xtreg	a11             	0x000b
+$_XTNAME xtensa xtreg	a12             	0x000c
+$_XTNAME xtensa xtreg	a13             	0x000d
+$_XTNAME xtensa xtreg	a14             	0x000e
+$_XTNAME xtensa xtreg	a15             	0x000f
+$_XTNAME xtensa xtreg	pc              	0x0020
+$_XTNAME xtensa xtreg	ar0             	0x0100
+$_XTNAME xtensa xtreg	ar1             	0x0101
+$_XTNAME xtensa xtreg	ar2             	0x0102
+$_XTNAME xtensa xtreg	ar3             	0x0103
+$_XTNAME xtensa xtreg	ar4             	0x0104
+$_XTNAME xtensa xtreg	ar5             	0x0105
+$_XTNAME xtensa xtreg	ar6             	0x0106
+$_XTNAME xtensa xtreg	ar7             	0x0107
+$_XTNAME xtensa xtreg	ar8             	0x0108
+$_XTNAME xtensa xtreg	ar9             	0x0109
+$_XTNAME xtensa xtreg	ar10            	0x010a
+$_XTNAME xtensa xtreg	ar11            	0x010b
+$_XTNAME xtensa xtreg	ar12            	0x010c
+$_XTNAME xtensa xtreg	ar13            	0x010d
+$_XTNAME xtensa xtreg	ar14            	0x010e
+$_XTNAME xtensa xtreg	ar15            	0x010f
+$_XTNAME xtensa xtreg	ar16            	0x0110
+$_XTNAME xtensa xtreg	ar17            	0x0111
+$_XTNAME xtensa xtreg	ar18            	0x0112
+$_XTNAME xtensa xtreg	ar19            	0x0113
+$_XTNAME xtensa xtreg	ar20            	0x0114
+$_XTNAME xtensa xtreg	ar21            	0x0115
+$_XTNAME xtensa xtreg	ar22            	0x0116
+$_XTNAME xtensa xtreg	ar23            	0x0117
+$_XTNAME xtensa xtreg	ar24            	0x0118
+$_XTNAME xtensa xtreg	ar25            	0x0119
+$_XTNAME xtensa xtreg	ar26            	0x011a
+$_XTNAME xtensa xtreg	ar27            	0x011b
+$_XTNAME xtensa xtreg	ar28            	0x011c
+$_XTNAME xtensa xtreg	ar29            	0x011d
+$_XTNAME xtensa xtreg	ar30            	0x011e
+$_XTNAME xtensa xtreg	ar31            	0x011f
+$_XTNAME xtensa xtreg	lbeg            	0x0200
+$_XTNAME xtensa xtreg	lend            	0x0201
+$_XTNAME xtensa xtreg	lcount          	0x0202
+$_XTNAME xtensa xtreg	sar             	0x0203
+$_XTNAME xtensa xtreg	windowbase      	0x0248
+$_XTNAME xtensa xtreg	windowstart     	0x0249
+$_XTNAME xtensa xtreg	configid0       	0x02b0
+$_XTNAME xtensa xtreg	configid1       	0x02d0
+$_XTNAME xtensa xtreg	ps              	0x02e6
+$_XTNAME xtensa xtreg	expstate        	0x03e6
+$_XTNAME xtensa xtreg	mmid            	0x0259
+$_XTNAME xtensa xtreg	ibreakenable    	0x0260
+$_XTNAME xtensa xtreg	ddr             	0x0268
+$_XTNAME xtensa xtreg	ibreaka0        	0x0280
+$_XTNAME xtensa xtreg	ibreaka1        	0x0281
+$_XTNAME xtensa xtreg	dbreaka0        	0x0290
+$_XTNAME xtensa xtreg	dbreaka1        	0x0291
+$_XTNAME xtensa xtreg	dbreakc0        	0x02a0
+$_XTNAME xtensa xtreg	dbreakc1        	0x02a1
+$_XTNAME xtensa xtreg	epc1            	0x02b1
+$_XTNAME xtensa xtreg	epc2            	0x02b2
+$_XTNAME xtensa xtreg	epc3            	0x02b3
+$_XTNAME xtensa xtreg	depc            	0x02c0
+$_XTNAME xtensa xtreg	eps2            	0x02c2
+$_XTNAME xtensa xtreg	eps3            	0x02c3
+$_XTNAME xtensa xtreg	excsave1        	0x02d1
+$_XTNAME xtensa xtreg	excsave2        	0x02d2
+$_XTNAME xtensa xtreg	excsave3        	0x02d3
+$_XTNAME xtensa xtreg	interrupt       	0x02e2
+$_XTNAME xtensa xtreg	intset          	0x02e2
+$_XTNAME xtensa xtreg	intclear        	0x02e3
+$_XTNAME xtensa xtreg	intenable       	0x02e4
+$_XTNAME xtensa xtreg	exccause        	0x02e8
+$_XTNAME xtensa xtreg	debugcause      	0x02e9
+$_XTNAME xtensa xtreg	ccount          	0x02ea
+$_XTNAME xtensa xtreg	icount          	0x02ec
+$_XTNAME xtensa xtreg	icountlevel     	0x02ed
+$_XTNAME xtensa xtreg	excvaddr        	0x02ee
+$_XTNAME xtensa xtreg	ccompare0       	0x02f0
+$_XTNAME xtensa xtreg	ccompare1       	0x02f1
+$_XTNAME xtensa xtreg	pwrctl          	0x200f
+$_XTNAME xtensa xtreg	pwrstat         	0x2010
+$_XTNAME xtensa xtreg	eristat         	0x2011
+$_XTNAME xtensa xtreg	cs_itctrl       	0x2012
+$_XTNAME xtensa xtreg	cs_claimset     	0x2013
+$_XTNAME xtensa xtreg	cs_claimclr     	0x2014
+$_XTNAME xtensa xtreg	cs_lockaccess   	0x2015
+$_XTNAME xtensa xtreg	cs_lockstatus   	0x2016
+$_XTNAME xtensa xtreg	cs_authstatus   	0x2017
+$_XTNAME xtensa xtreg	fault_info      	0x2026
+$_XTNAME xtensa xtreg	trax_id         	0x2027
+$_XTNAME xtensa xtreg	trax_control    	0x2028
+$_XTNAME xtensa xtreg	trax_status     	0x2029
+$_XTNAME xtensa xtreg	trax_data       	0x202a
+$_XTNAME xtensa xtreg	trax_address    	0x202b
+$_XTNAME xtensa xtreg	trax_pctrigger  	0x202c
+$_XTNAME xtensa xtreg	trax_pcmatch    	0x202d
+$_XTNAME xtensa xtreg	trax_delay      	0x202e
+$_XTNAME xtensa xtreg	trax_memstart   	0x202f
+$_XTNAME xtensa xtreg	trax_memend     	0x2030
+$_XTNAME xtensa xtreg	pmg             	0x203e
+$_XTNAME xtensa xtreg	pmpc            	0x203f
+$_XTNAME xtensa xtreg	pm0             	0x2040
+$_XTNAME xtensa xtreg	pm1             	0x2041
+$_XTNAME xtensa xtreg	pmctrl0         	0x2042
+$_XTNAME xtensa xtreg	pmctrl1         	0x2043
+$_XTNAME xtensa xtreg	pmstat0         	0x2044
+$_XTNAME xtensa xtreg	pmstat1         	0x2045
+$_XTNAME xtensa xtreg	ocdid           	0x2046
+$_XTNAME xtensa xtreg	ocd_dcrclr      	0x2047
+$_XTNAME xtensa xtreg	ocd_dcrset      	0x2048
+$_XTNAME xtensa xtreg	ocd_dsr         	0x2049
+$_XTNAME xtensa xtreg	psintlevel      	0x2003
+$_XTNAME xtensa xtreg	psum            	0x2004
+$_XTNAME xtensa xtreg	pswoe           	0x2005
+$_XTNAME xtensa xtreg	psexcm          	0x2006
+$_XTNAME xtensa xtreg	pscallinc       	0x2007
+$_XTNAME xtensa xtreg	psowb           	0x2008
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa.cfg
new file mode 100644
index 0000000..c277673
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/xtensa.cfg
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Target Support for Xtensa Processors
+#
+
+set xtensa_ids { 0x120034e5 0x120134e5
+				 0x209034e5 0x209134e5 0x209234e5 0x209334e5 0x209434e5 0x209534e5 0x209634e5 0x209734e5
+				 0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5 0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5
+				 0x20b034e5 0x20b33ac5 0x20b33ac7 }
+set expected_xtensa_ids {}
+foreach i $xtensa_ids {
+	lappend expected_xtensa_ids -expected-id $i
+}
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xtensa
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPARGLIST "-expected-id $CPUTAPID"
+} else {
+	set _CPUTAPARGLIST [join $expected_xtensa_ids]
+}
+
+if { [info exists XTENSA_NUM_CORES] } {
+	set _XTENSA_NUM_CORES $XTENSA_NUM_CORES
+} else {
+	set _XTENSA_NUM_CORES 1
+}
+
+set _TARGETNAME $_CHIPNAME
+set _CPU0NAME cpu
+set _TAPNAME $_CHIPNAME.$_CPU0NAME
+
+if { [info exists XTENSA_DAP] } {
+	source [find target/swj-dp.tcl]
+	# SWD mode ignores the -irlen parameter
+	eval swj_newdap $_CHIPNAME cpu -irlen 4 $_CPUTAPARGLIST
+	dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+	set _TARGETNAME $_CHIPNAME.cpu
+	if { [info exists XTENSA_DAP_BASE] } {
+		# Specify fixed offset for accessing XDM via APB behind a DAP interface
+		target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap -dbgbase $XTENSA_DAP_BASE
+	} else {
+		target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap
+	}
+} elseif { $_XTENSA_NUM_CORES > 1 } {
+	# JTAG direct (without DAP)
+	for {set i 0} {$i < $_XTENSA_NUM_CORES} {incr i} {
+		set _LCPUNAME $_CPU0NAME$i
+		set _LTAPNAME $_CHIPNAME.$_LCPUNAME
+		eval jtag newtap $_CHIPNAME $_LCPUNAME -irlen 5 $_CPUTAPARGLIST
+		target create $_LTAPNAME xtensa -chain-position $_LTAPNAME -coreid $i
+
+		$_LTAPNAME configure -event reset-assert-post { soft_reset_halt }
+	}
+} else {
+	# JTAG direct (without DAP) - for legacy xtensa-config-XXX.cfg format
+	eval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST
+	target create $_TARGETNAME xtensa -chain-position $_TAPNAME
+}
+
+if { $_XTENSA_NUM_CORES == 1 } {
+	# DAP and single-core legacy JTAG
+	$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
+}
+
+gdb report_register_access_error enable
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/zynq_7000.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/zynq_7000.cfg
new file mode 100644
index 0000000..5a88b6e
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/target/zynq_7000.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx Zynq-7000 All Programmable SoC
+#
+# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
+# https://www.xilinx.com/member/forms/download/sim-model-eval-license-xef.html?filename=bsdl_zynq_2.zip
+#
+# 0x03736093  XQ7Z100 XC7Z100I XC7Z100
+# 0x03731093  XQ7Z045 XC7Z045I XC7Z045
+# 0x0372c093  XQ7Z030 XC7Z030I XC7Z030 XA7Z030
+# 0x03727093  XQ7Z020 XC7Z020I XC7Z020 XA7Z020
+# 0x03732093  XC7Z035I XC7Z035
+# 0x0373b093  XC7Z015I XC7Z015
+# 0x03728093  XC7Z014S
+# 0x0373c093  XC7Z012S
+# 0x03722093  XC7Z010I XC7Z010 XA7Z010
+# 0x03723093  XC7Z007S
+
+set _CHIPNAME zynq
+set _TARGETNAME $_CHIPNAME.cpu
+
+jtag newtap zynq_pl bs -irlen 6 -ignore-version -ircapture 0x1 -irmask 0x03 \
+    -expected-id 0x03723093 \
+    -expected-id 0x03722093 \
+    -expected-id 0x0373c093 \
+    -expected-id 0x03728093 \
+    -expected-id 0x0373B093 \
+    -expected-id 0x03732093 \
+    -expected-id 0x03727093 \
+    -expected-id 0x0372C093 \
+    -expected-id 0x03731093 \
+    -expected-id 0x03736093
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
+    -coreid 0 -dbgbase 0x80090000
+target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
+    -coreid 1 -dbgbase 0x80092000
+target smp ${_TARGETNAME}0 ${_TARGETNAME}1
+
+adapter speed 1000
+
+${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
+${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
+
+pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
+virtex2 set_user_codes zynq_pl.pld 0x02 0x03 0x22 0x23
+
+set XC7_JSHUTDOWN 0x0d
+set XC7_JPROGRAM 0x0b
+set XC7_JSTART 0x0c
+set XC7_BYPASS 0x3f
+
+proc zynqpl_program {tap} {
+	echo "DEPRECATED! use 'virtex2 program ...' not 'zynqpl_program'"
+	global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
+	irscan $tap $XC7_JSHUTDOWN
+	irscan $tap $XC7_JPROGRAM
+	runtest 60000
+	#JSTART prevents this from working...
+	#irscan $tap $XC7_JSTART
+	runtest 2000
+	irscan $tap $XC7_BYPASS
+	runtest 2000
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/test/selftest.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/test/selftest.cfg
new file mode 100644
index 0000000..10efb0c
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/test/selftest.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+add_help_text selftest "run selftest using working ram  
       "
+
+proc selftest {tmpfile address size} {
+
+   for {set i 0} {$i < $size } {set i [expr {$i+4}]} {
+       mww [expr {$address+$i}] $i
+   }
+
+   for {set i 0} {$i < 10 } {set i [expr {$i+1}]} {
+    echo "Test iteration $i"
+    dump_image $tmpfile $address $size
+	verify_image $tmpfile $address bin
+	load_image $tmpfile $address bin
+   }
+
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/test/syntax1.cfg b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/test/syntax1.cfg
new file mode 100644
index 0000000..7735ee9
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/test/syntax1.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough
+adapter assert trst assert srst
+adapter deassert trst deassert srst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f
+
+#target configuration
+#daemon_startup reset
+
+set _TARGETNAME [format "%s.cpu" lpc2148]
+target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+soft_reset_halt
+mvb 0xE01FC040 0x01
+}
+
+
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/tools/firmware-recovery.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/tools/firmware-recovery.tcl
new file mode 100644
index 0000000..6a328cd
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/tools/firmware-recovery.tcl
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+echo "\n\nFirmware recovery helpers"
+echo "Use -c firmware_help to get help\n"
+
+set known_boards {
+    "asus-rt-n16		ASUS RT-N16"
+    "asus-rt-n66u		ASUS RT-N66U"
+    "linksys-wag200g		Linksys WAG200G"
+    "linksys-wrt54gl		Linksys WRT54GL v1.1"
+    "netgear-dg834v3		Netgear DG834G v3"
+    "tp-link_tl-mr3020		TP-LINK TL-MR3020"
+    "bt-homehubv1		BT HomeHub v1"
+}
+
+proc firmware_help { } {
+    echo "
+Your OpenOCD command should look like this:
+openocd -f interface/.cfg -f tools/firmware-recovery.tcl -c \"*; shutdown\"
+
+Where:
+ is one of the supported devices, e.g. ftdi/jtagkey2
+ are firmware-recovery commands separated by semicolon
+
+Supported commands:
+firmware_help			get this help
+list_boards			list known boards and exit
+board 			select board you work with
+list_partitions			list partitions of the currently selected board
+dump_part  	save partition's contents to a file
+erase_part 		erase the given partition
+flash_part  	erase, flash and verify the given partition
+ram_boot 		load binary file to RAM and run it
+adapter speed 		set JTAG clock frequency in kHz
+
+For example, to clear nvram and reflash CFE on an RT-N16 using TUMPA, run:
+openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\
+	-c \"board asus-rt-n16; erase_part nvram; flash_part CFE cfe-n16.bin; shutdown\"
+\n\n"
+    shutdown
+}
+
+# set default, can be overridden later
+adapter speed 1000
+
+proc get_partition { name } {
+    global partition_list
+    dict get $partition_list $name
+}
+
+proc partition_desc { name } { lindex [get_partition $name] 0 }
+proc partition_start { name } { lindex [get_partition $name] 1 }
+proc partition_size { name } { lindex [get_partition $name] 2 }
+
+proc list_boards { } {
+    global known_boards
+    echo "List of the supported boards:\n"
+    echo "Board name\t\tDescription"
+    echo "-----------------------------------"
+    foreach i $known_boards {
+	echo $i
+    }
+    echo "\n\n"
+}
+
+proc board { name } {
+    script [find board/$name.cfg]
+}
+
+proc list_partitions { } {
+    global partition_list
+    set fstr "%-16s%-14s%-14s%s"
+    echo "\nThe currently selected board is known to have these partitions:\n"
+    echo [format $fstr Name Start Size Description]
+    echo "-------------------------------------------------------"
+    for {set i 0} {$i < [llength $partition_list]} {incr i 2} {
+	set key [lindex $partition_list $i]
+	echo [format $fstr $key [partition_start $key] [partition_size $key] [partition_desc $key]]
+    }
+    echo "\n\n"
+}
+
+# Magic to work with any targets, including semi-functional
+proc prepare_target { } {
+    init
+    catch {halt}
+    catch {reset init}
+    catch {halt}
+}
+
+proc dump_part { name filename } {
+    prepare_target
+    dump_image $filename [partition_start $name] [partition_size $name]
+}
+
+proc erase_part { name } {
+    prepare_target
+    flash erase_address [partition_start $name] [partition_size $name]
+}
+
+proc flash_part { name filename } {
+    prepare_target
+    flash write_image erase $filename [partition_start $name] bin
+    echo "Verifying:"
+    verify_image $filename [partition_start $name]
+}
+
+proc ram_boot { filename } {
+    global ram_boot_address
+    prepare_target
+    load_image $filename $ram_boot_address bin
+    resume $ram_boot_address
+}
+
+echo ""
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/tools/memtest.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/tools/memtest.tcl
new file mode 100644
index 0000000..f70f950
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/tools/memtest.tcl
@@ -0,0 +1,191 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Algorithms by Michael Barr, released into public domain
+# Ported to OpenOCD by Shane Volpe, additional fixes by Paul Fertser
+
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+source [find bitsbytes.tcl]
+source [find memory.tcl]
+
+proc runAllMemTests { baseAddress nBytes } {
+    memTestDataBus $baseAddress
+    memTestAddressBus $baseAddress $nBytes
+    memTestDevice $baseAddress $nBytes
+}
+
+#***********************************************************************************
+# *
+# * Function:    memTestDataBus()
+# *
+# * Description: Test the data bus wiring in a memory region by
+# *              performing a walking 1's test at a fixed address
+# *              within that region.  The address (and hence the
+# *              memory region) is selected by the caller.
+# *		 Ported from:
+# *		 http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C
+# * Notes:
+# *
+# * Returns:     Empty string if the test succeeds.
+# *              A non-zero result is the first pattern that failed.
+# *
+#***********************************************************************************
+proc memTestDataBus { address } {
+    echo "Running memTestDataBus"
+
+    for {set i 0} {$i < 32} {incr i} {
+	# Shift bit
+	set pattern [expr {1 << $i}]
+
+	# Write pattern to memory
+	memwrite32 $address $pattern
+
+	# Read pattern from memory
+	set data [memread32 $address]
+
+	if {$data != $pattern} {
+	    echo "FAILED DATABUS: Address: $address, Pattern: $pattern, Returned: $data"
+	    return $pattern
+	}
+    }
+}
+
+#***********************************************************************************
+# *
+# * Function:    memTestAddressBus()
+# *
+# * Description: Perform a walking 1's test on the relevant bits
+# *              of the address and check for aliasing.  This test
+# *              will find single-bit address failures such as stuck
+# *              -high, stuck-low, and shorted pins.  The base address
+# *              and size of the region are selected by the caller.
+# *		 Ported from:
+# *		 http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C
+# *
+# * Notes:       For best results, the selected base address should
+# *              have enough LSB 0's to guarantee single address bit
+# *              changes.  For example, to test a 64-Kbyte region,
+# *              select a base address on a 64-Kbyte boundary.  Also,
+# *              select the region size as a power-of-two--if at all
+# *              possible.
+# *
+# * Returns:     Empty string if the test succeeds.
+# *              A non-zero result is the first address at which an
+# *              aliasing problem was uncovered.  By examining the
+# *              contents of memory, it may be possible to gather
+# *              additional information about the problem.
+# *
+#***********************************************************************************
+proc memTestAddressBus { baseAddress nBytes } {
+    set addressMask [expr {$nBytes - 1}]
+    set pattern 0xAAAAAAAA
+    set antipattern 0x55555555
+
+    echo "Running memTestAddressBus"
+
+    echo "addressMask: [convertToHex $addressMask]"
+
+    echo "memTestAddressBus: Writing the default pattern at each of the power-of-two offsets..."
+    for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}] } {
+	set addr [expr {$baseAddress + $offset}]
+	memwrite32 $addr $pattern
+    }
+
+    echo "memTestAddressBus: Checking for address bits stuck high..."
+    memwrite32 $baseAddress $antipattern
+
+    for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} {
+	set addr [expr {$baseAddress + $offset}]
+	set data [memread32 $addr]
+
+	if {$data != $pattern} {
+	    echo "FAILED DATA_ADDR_BUS_SHIGH: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]"
+	    return $pattern
+	}
+    }
+
+    echo "memTestAddressBus: Checking for address bits stuck low or shorted..."
+    memwrite32 $baseAddress $pattern
+    for {set testOffset 32} {[expr {$testOffset & $addressMask}] != 0} {set testOffset [expr {$testOffset << 1}] } {
+	set addr [expr {$baseAddress + $testOffset}]
+	memwrite32 $addr $antipattern
+
+	set data [memread32 $baseAddress]
+	if {$data != $pattern} {
+	    echo "FAILED DATA_ADDR_BUS_SLOW: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]"
+	    return $pattern
+	}
+
+	for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} {
+	    set addr [expr {$baseAddress + $offset}]
+	    set data [memread32 $baseAddress]
+
+            if {(($data != $pattern) && ($offset != $testOffset))} {
+		echo "FAILED DATA_ADDR_BUS_SLOW2: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset], testOffset [convertToHex $testOffset]"
+		return $pattern
+	    }
+        }
+	set addr [expr {$baseAddress + $testOffset}]
+	memwrite32 $addr $pattern
+    }
+}
+
+#***********************************************************************************
+# *
+# * Function:    memTestDevice()
+# *
+# * Description: Test the integrity of a physical memory device by
+# *              performing an increment/decrement test over the
+# *              entire region.  In the process every storage bit
+# *              in the device is tested as zero and as one.  The
+# *              base address and the size of the region are
+# *              selected by the caller.
+# *		 Ported from:
+# *		 http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C
+# * Notes:
+# *
+# * Returns:     Empty string if the test succeeds.
+# *              A non-zero result is the first address at which an
+# *              incorrect value was read back.  By examining the
+# *              contents of memory, it may be possible to gather
+# *              additional information about the problem.
+# *
+#***********************************************************************************
+proc memTestDevice { baseAddress nBytes } {
+    echo "Running memTestDevice"
+
+    echo "memTestDevice: Filling memory with a known pattern..."
+    for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {
+	memwrite32 [expr {$baseAddress + $offset}] $pattern
+    }
+
+    echo "memTestDevice: Checking each location and inverting it for the second pass..."
+    for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {
+	set addr [expr {$baseAddress + $offset}]
+	set data [memread32 $addr]
+
+	if {$data != $pattern} {
+	    echo "FAILED memTestDevice_pattern: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset]"
+	    return $pattern
+	}
+
+	set antiPattern [expr {~$pattern}]
+	memwrite32 [expr {$baseAddress + $offset}] $antiPattern
+    }
+
+    echo "memTestDevice: Checking each location for the inverted pattern and zeroing it..."
+    for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {
+	set antiPattern [expr {~$pattern & ((1<<32) - 1)}]
+	set addr [expr {$baseAddress + $offset}]
+	set data [memread32 $addr]
+	set dataHex [convertToHex $data]
+	set antiPatternHex [convertToHex $antiPattern]
+	if {$dataHex != $antiPatternHex} {
+	    echo "FAILED memTestDevice_antipattern: Address: [convertToHex $addr], antiPattern: $antiPatternHex, Returned: $dataHex, offset: $offset"
+	    return $pattern
+	}
+    }
+}
+
+proc convertToHex { value } {
+    format 0x%08x $value
+}
diff --git a/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/tools/test_cpu_speed.tcl b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/tools/test_cpu_speed.tcl
new file mode 100644
index 0000000..f1a3fb3
--- /dev/null
+++ b/flash_code_20260525/flash_code/openocd/win/2025.10/scripts/tools/test_cpu_speed.tcl
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Description:
+#  Measure the CPU clock frequency of an ARM Cortex-M based device.
+#
+# Return:
+#  The CPU clock frequency in Hz. A negative value indicates that the loop
+#  counter was saturated.
+#
+# Note:
+#  You may need to adapt the number of cycles for your device.
+#
+add_help_text cortex_m_test_cpu_speed "Measure the CPU clock frequency of an ARM Cortex-M based device"
+add_usage_text cortex_m_test_cpu_speed {address [timeout [cycles_per_loop]]}
+proc cortex_m_test_cpu_speed { address { timeout 200 } { cycles_per_loop 4 } } {
+	set loop_counter_start 0xffffffff
+
+	halt
+
+	# Backup registers and memory.
+	set backup_regs [get_reg -force {pc r0 xpsr}]
+	set backup_mem [read_memory $address 16 3]
+
+	# We place the following code at the given address to measure the
+	# CPU clock frequency:
+	#
+	# 3801: subs r0, #1
+	# d1fd: bne #-2
+	# e7fe: b #-4
+	write_memory $address 16 {0x3801 0xd1fd 0xe7fe}
+
+	set_reg "pc $address r0 $loop_counter_start"
+	resume
+	sleep $timeout
+	halt
+
+	# Get the loop counter value from register r0.
+	set loop_counter_end [dict values [get_reg r0]]
+	set loop_counter_diff [expr {$loop_counter_start - $loop_counter_end}]
+
+	# Restore registers and memory.
+	set_reg $backup_regs
+	write_memory $address 16 $backup_mem
+
+	if { [expr {$loop_counter_end == 0}] } {
+		return -1
+	}
+
+	return [expr {double($loop_counter_diff) * $cycles_per_loop / $timeout * 1000}]
+}
diff --git a/flash_code_20260525/flash_code/pec930.hex b/flash_code_20260525/flash_code/pec930.hex
new file mode 100644
index 0000000..6d1fbf1
--- /dev/null
+++ b/flash_code_20260525/flash_code/pec930.hex
@@ -0,0 +1,662 @@
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