microchip-application-pec930-pec930_peripheral/pec930_sdk-v1.0.1/file_implementation_plan.md

SPI DAQ Transmission Feature

This plan outlines the changes needed to support continuous 24kHz transmission of DAQ_Packet_t variables via SPI based on the "test_data:" UART command.

User Review Required

Warning

SPI Pin Conflict with PWM: The standard SPI pin mapping configures PA2, PA3, PA4, and PA5. However, in your application init.c, PA0 to PA5 are mapped to Alternative Function 6 (GPIO_AF_6) as EPWM output for motor control. Please review and clarify which pins you want to use for the SPI bus. If there are alternate routing mappings or a second SPI interface (SPI1), please specify them.

Caution

Performance Constraint at 24kHz: DAQ_Packet_t is 34-36 bytes long (depending on packing). Transmitting this much data at 24,000 times per second means pushing an SPI bandwidth of almost 7 Megabits per second (if back-to-back), plus software overhead. If standard polling is used, this could take a significant chunk of time out of the 41.6µs period. Please advise if a high SPI Baudrate or DMA is available/desired.

Proposed Changes

[MODIFY] main.c

1. Add global runtime flag: bool send_daq_enabled = false;.
2. Extend cmd_parser to check strncmp(data, "test_data:1", 11) == 0 (enable) and test_data:0 (disable).
3. Inside the flag_24Khz_timer loop, populate DAQ_Packet_t structure (using actual timestamp, phase duty values mapped to current/voltage, dds_amp, dds_ftw, etc.).
4. Send the structure bytes over SPI0 if send_daq_enabled == true.

[MODIFY] main.h

1. Provide the definition of DAQ_Packet_t. Ensure it has #pragma pack(push, 1) behavior to preserve proper byte alignment for parsing.

[MODIFY] init.c

1. Create spi_config(void) function taking into account the relevant GPIO_AF_x mappings and highest reasonably possible .SPI_BaudRatePrescaler.
2. Initialize SPI0 in Master mode.
3. Call spi_config() in SYS_Config().

[MODIFY] init.h

1. Add function prototype for spi_config().

Open Questions

1. Which specific GPIO pins should be configured for the SPI bus mapping to avoid conflict with EPWM?
2. What data exactly should be mapping into variables like i_u, v_u, v_bus, error_val etc? Currently there are phase[0].duty and predefined values. Should we mock these fields, leave them as 0, or link them to specific placeholders?
3. Can we assume SPI0 in Master mode is perfectly fine for this application?
4. CRC16 Implementation: Is the crc16 field generated by software or a hardware peripheral?

Verification Plan

Automated/Code Verification

• Compile code to ensure DAQ_Packet_t structures are safely populated and no definitions are missing.

Manual Verification

• Send test_data:1 over UART.
• Measure the SPI clock and MOSI pin using a logic analyzer to verify data is successfully bursted exactly at the 24kHz rate.
• Parse the resulting values logic analyzer to ensure DAQ_Packet_t crc16 and fields align correctly.