diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h
index 89bf65d..1ed48da 100644
--- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h
+++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h
@@ -15,7 +15,7 @@ static void AD5940_init(){
     w16_REG(0x02C9);
     select_REG(0x0A28);
     w16_REG(0x0009);
-    select_REG(0x238C);
+    select_REG(ADCBUFCON);
     w16_REG(0x0104);
     select_REG(0x0A04);
     w16_REG(0x4859);
@@ -25,7 +25,7 @@ static void AD5940_init(){
     w16_REG(0x8009);
     select_REG(0x0A04);
     w16_REG(0x4859);
-    select_REG(0x22F0);
+    select_REG(PMBW);
     w16_REG(0x0000);
 }
 
@@ -105,27 +105,27 @@ static void setEIS_EIS (void)
 static void setEIS_CV (void)
 {
    //Clock and Ref
-    select_REG(0x0414); //CLKSEL
+    select_REG(CLKSEL); //CLKSEL
     w16_REG(0x0);
-    select_REG(0x20BC); //HSOSCCON
+    select_REG(HSOSCCON); //HSOSCCON
     w32_REG(0x00000004); //16 MHz output
     select_REG(0x2180); //BUFSENCON
     w32_REG(0x00000037); //0b110110
 
     //Configure LPDAC LPTIA
-    select_REG(0x2050); //LPREFBUFCON
+    select_REG(LPREFBUFCON); //LPREFBUFCON
     w32_REG(0x0); //enable lpref and lp 2.5V buffer
-    select_REG(0x2124); //LPDACSW0
+    select_REG(LPDACSW0); //LPDACSW0
     w32_REG(0x0000003E);
-    select_REG(0x20E4); //LPTIASW0
+    select_REG(LPTIASW0); //LPTIASW0
     w32_REG(0x00008034); // SW2 | SW4 | SW5
-    select_REG(0x20EC); //LPTIACON0
+    select_REG(LPTIACON0); //LPTIACON0
     w32_REG(0x00000038); //RF 0 | RTIA 200R | Rload 0 | High Current Mode
-    select_REG(0x2128); //LPDACCON0
+    select_REG(LPDACCON0); //LPDACCON0
     w32_REG(0x00000001);
 
     //Configure ADC | ADCDAT (0x2074)
-    select_REG(0x21A8); //ADCCON
+    select_REG(ADCCON); //ADCCON
     w32_REG(0x00001021); //PGA = 1 | VZERO | LPTIA_OUT
     select_REG(ADCFILTERCON); //ADCFILTERCON
     w32_REG(0x00002011); // Sinc3 En | SINC3OSR2 | SINC2OSR22
@@ -135,7 +135,7 @@ static void setEIS_CV (void)
     //AFE and PWMB
     select_REG(AFECON); //AFECON
     w32_REG(0x00098780); //ADC on //0b10011000011110000000
-    select_REG(0x22F0); //PWMB
+    select_REG(PMBW); //PWMB
     w32_REG(0x00000005);//fc 50kHz, low power mode
 }
 
@@ -188,27 +188,27 @@ static void HS_cali_config (void)
 static void LP_cali_config (void)
 {
    //Clock and Ref
-    select_REG(0x0414); //CLKSEL
+    select_REG(CLKSEL); //CLKSEL
     w16_REG(0x0);
-    select_REG(0x20BC); //HSOSCCON
+    select_REG(HSOSCCON); //HSOSCCON
     w32_REG(0x00000004); //16 MHz output
     select_REG(0x2180); //BUFSENCON
     w32_REG(0x00000037); //0b110110
 
     //Configure LPDAC LPTIA
-    select_REG(0x2050); //LPREFBUFCON
+    select_REG(LPREFBUFCON); //LPREFBUFCON
     w32_REG(0x0); //enable lpref and lp 2.5V buffer
-    select_REG(0x2124); //LPDACSW0
+    select_REG(LPDACSW0); //LPDACSW0
     w32_REG(0x0000003E);
-    select_REG(0x20E4); //LPTIASW0
+    select_REG(LPTIASW0); //LPTIASW0
     w32_REG(0x00008034); // SW2 | SW4 | SW5
-    select_REG(0x20EC); //LPTIACON0
+    select_REG(LPTIACON0); //LPTIACON0
     w32_REG(0x00000038); //RF 0 | RTIA 200R | Rload 0 | High Current Mode
-    select_REG(0x2128); //LPDACCON0
+    select_REG(LPDACCON0); //LPDACCON0
     w32_REG(0x00000001);
 
     //Configure ADC | ADCDAT (0x2074)
-    select_REG(0x21A8); //ADCCON
+    select_REG(ADCCON); //ADCCON
     w32_REG(0x00001021); //PGA = 1 | VZERO | LPTIA_OUT
     select_REG(ADCFILTERCON); //ADCFILTERCON
     w32_REG(0x00006091); //AVR 4 | Sinc3 En | OSR 2
@@ -219,7 +219,7 @@ static void LP_cali_config (void)
     //AFE and PWMB
     select_REG(AFECON); //AFECON
     w32_REG(0x00098780); //ADC on //0b10011000011110000000
-    select_REG(0x22F0); //PWMB
+    select_REG(PMBW); //PWMB
     w32_REG(0x00000005);//fc 50kHz, low power mode
 }
 
diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h
index ac91e20..3b04258 100644
--- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h
+++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteADC.h
@@ -233,7 +233,7 @@ static void LPTIAGainCtrl(uint8_t LPTIALevel){
     uint16_t data;
 
 
-    select_REG(0x20EC); //LPTIACON0
+    select_REG(LPTIACON0); //LPTIACON0
     code = r32_REG();
 
     if (LPTIALevel == LPRTIA_200R) {
@@ -253,7 +253,7 @@ static void LPTIAGainCtrl(uint8_t LPTIALevel){
     }
 
     code = (code & (~(31 << 5))) | (data << 5);
-    select_REG(0x20EC); //LPTIACON0
+    select_REG(LPTIACON0); //LPTIACON0
     w32_REG(code);
 
     record_flag = false;
@@ -1075,7 +1075,7 @@ static void BpSINC3(uint8_t ret){ // 1: bypass sinc3
 
 static void EnNotch(uint8_t ret){
     uint32_t code;
-    select_REG(0x2000);
+    select_REG(AFECON);
     code = r32_REG();
     code = (code & (~(1 << 16))) | (ret << 16);
     w32_REG(code);
diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h
index 30b519d..19b2499 100644
--- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h
+++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h
@@ -982,7 +982,7 @@ static void update_ZM_instruction(uint8 *ins) {
                 }
 
                 case CTL_RD_DFTR: { // ble write: 0x3000FF 78FFFFFFFF
-                    select_REG(0x2078);
+                    select_REG(DFTREAL);
                     r32_REG();
 
                     initCISBuf();
@@ -998,7 +998,7 @@ static void update_ZM_instruction(uint8 *ins) {
                 }
 
                 case CTL_RD_DFTI: { // ble write: 0x3000FF 7CFFFFFFFF
-                    select_REG(0x207C);
+                    select_REG(DFTIMAG);
                     r32_REG();
 
                     initCISBuf();