From 7ec507fc2e429eeb2a6e80ff9cbbb98558510d91 Mon Sep 17 00:00:00 2001 From: ROY Date: Tue, 7 Mar 2023 11:39:18 +0800 Subject: [PATCH] cali AC dcbias --- .../cc26xx/app/headstage/AD5940.h | 37 +++++++++ .../cc26xx/app/headstage/EliteDAC.h | 20 +++++ .../cc26xx/app/headstage/headstage.h | 82 +++++++++++++++++++ .../cc26xx/app/headstage/mode_cf.h | 17 +++- 4 files changed, 155 insertions(+), 1 deletion(-) diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h index 3dd68dd..ffb788a 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/AD5940.h @@ -2,6 +2,8 @@ #ifndef AD5940 #define AD5940 +#define NV2USC(_n) (n / 1e7 * 625 + 25000) // [5nV] / 1e6 * 5 * 12.5 + 25000 + static void setEIS_EIS (void) { AD5940_SPIWriteReg(LPDACCON0, 0x00000001); // Direct from LPDACDAT0 | Vzero(6bit) & Vbias(12bit) | LP 2.5v as ref @@ -128,6 +130,41 @@ static void setEIS_CV (void) AD5940_SPIWriteReg(PMBW, 0x00000005); //fc 50kHz, low power mode } +static void set_hs_only(void) +{ + AD5940_SPIWriteReg(LPDACCON0, 0x00000001); // Direct from LPDACDAT0 | Vzero(6bit) & Vbias(12bit) | LP 2.5v as ref + AD5940_SPIWriteReg(LPDACSW0, 0b111111); // orverride LPDACCON0[5] | LPDACSW0[0~5] close + + AD5940_SPIWriteReg(HSRTIACON, 0x00000000); // CTIA=1pF | SW6 off(open) | RTIA=200R + AD5940_SPIWriteReg(HSTIACON, 0x00000001); // Vzero + + AD5940_SPIWriteReg(ADCCON, 0x00000101); // PGA=1 | HSTIA neg input | HSTIA pos signal + AD5940_SPIWriteReg(DFTCON, 0x00000091); // DFTNUM=2048 | enable hanning window | SINC2 + AD5940_SPIWriteReg(SWCON, 0x00026355); // D5 | P5 | N3 | T6 | T9 close + + AD5940_SPIWriteReg(AFECON, 0x0031CFC0); // en dc DAC buf | HSDAC ref disable | LDO buf current limit enable | en SINC2 | + // DFT hardware accelerator enable | waveform generator enable | HSTIA enable | + // intru amplifier enable | excitation buf enable | ADC conversions enable | + // ADC power enable | HSDAC enable | HP ref enable + + //HIGH POWER MODE + AD5940_SPIWriteReg(PMBW, 0x0000000D); // HS mode | Set cutooff frequency to 250kHz, -3 dB bandwidth + AD5940_SPIWriteReg(CLKSEL, 0x0000); + AD5940_SPIWriteReg(CLKCON0KEY, 0xA815); // !!!Write 0xA815 to this register before accessing the CLKCON0 register + AD5940_SPIWriteReg(CLKCON0, 0x0442); //6bit system clock divider //set divider = 2 + AD5940_SPIWriteReg(HSOSCCON, 0x00000000); // HP osc select 32MHz output + AD5940_SPIWriteReg(ADCFILTERCON, 0x00000311); // en DFT clk | en DAC wave clk | en SINC2 filter clk | 2 ADC samples used for average function | + // SINC3 filter oversampling rate is 800kSPS | + // SINC2 filter oversampling rate is 178 samples | + // disable average | SINC3 filter enable | + // Bypass 50/60Hz | ADC data rate 800kHz + AD5940_SPIWriteReg(HSDACCON, 0x0000000E); // HSDAC gain = 2, DAC update rate = ACLK/HSDACCON = 32Mhz/7 + AD5940_SPIWriteReg(ADCBUFCON, 0x005F3D0F); //recommended + SetEISHIGHZ(0); + + return; +} + // static void AD5940_Initialize() { // AD5940_SPIWriteReg(0x0908, 0x02C9);//initiation // AD5940_SPIWriteReg(0x0C08, 0x206C); diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h index ea51671..cf4e8bd 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/EliteDAC.h @@ -64,6 +64,26 @@ static int32_t DAC_outputV(int32_t voltLVraw) { // LPDAC output, voltLV = Vbia return ret; } +/* user code: 0 ~ 50000: -2V ~ +2V */ +static void HSDAC_outputV(int32_t voltLVraw) +{ + uint8_t n_zero;//6btit + uint16_t n_bias;//12bit + uint32_t DACOutCode; + int64_t value = ((int64_t)voltLVraw * 14885967 + 595265249756) / 1e8; + + n_zero = 31; + n_bias = (uint16_t)value; + + if(n_bias > 4095) n_bias = 4095; + if(n_zero > 63) n_zero = 63; + DACOutCode = (0x0003FFFF & ((n_zero << 12) + n_bias)); + + AD5940_SPIWriteReg(LPDACDAT0, DACOutCode); + + return; +} + /* user code: 0 ~ 50000; LPDAC bias value: -2V ~ +2V */ static void set_lpdac_ce_1100mv(uint8_t z, uint16_t b) { // LPDAC output, voltLV = Vbias-Vzero /* new code*/ diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h index c88166b..66bf91b 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/headstage.h @@ -407,6 +407,88 @@ static void decode_ris_ins(uint8 *ins) break; } + case 0xF7: { //debug: create nzero & nbias table + uint32_t DACOutCode; + uint16_t n_bias = (uint16_t)ins[4] << 8 | (uint16_t)ins[5]; + uint16_t n_zero = (uint16_t)ins[6] << 8 | (uint16_t)ins[7]; + + instru.acamp = (uint16_t)ins[8] << 8 | (uint16_t)ins[9]; + instru.fset = (uint32_t)ins[10] << 24 | (uint32_t)ins[11] << 16 | (uint32_t)ins[12] << 8 | (uint32_t)ins[13]; + instru.gain_lv_hstia = HSRTIA_200R; + + if(n_bias > 4095) n_bias = 4095; + if(n_zero > 63) n_zero = 63; + DACOutCode = (0x0003FFFF & ((n_zero << 12) + n_bias)); + + set_hs_only(); + if (instru.gain_lv_hstia < HSRTIA_MAX) { + instru.HSTIAAutoGainEnable = 0; + HSTIAGainCtrl(instru.gain_lv_hstia); + } else { + instru.HSTIAAutoGainEnable = 1; + instru.gain_lv_hstia = HSRTIA_200R; + HSTIAGainCtrl(instru.gain_lv_hstia); + } + AD5940_SPIWriteReg(LPDACDAT0, DACOutCode); + AD5940_SPIWriteReg(WGFCW, instru.fset); + AD5940_SPIWriteReg(WGCON, 0x0); // 0x0: DC disable ac first + AD5940_SPIWriteReg(WGAMPLITUDE, instru.acamp); + AD5940_SPIWriteReg(WGCON, 0x00000004); //0x4: Sinusoid + + led_color_set(LED_NB_MAX, LED_BR_LV1, LED_CLR_PURPLE); + SetEISHIGHZ(1); + + initCISBuf(); + cis_buf[0] = 6; + cis_buf[1] = 0xF7; + cis_buf[2] = ins[4]; + cis_buf[3] = ins[5]; + cis_buf[4] = ins[6]; + cis_buf[5] = ins[7]; + SimpleProfile_SetParameter(BLE_CIS_BUFF_CHAR, BLE_CIS_BUFF_SIZE, cis_buf); + break; + } + + case 0xF8: { //debug: fixed zero + instru.dcbias = (uint16_t)ins[4] << 8 | (uint16_t)ins[5]; + instru.acamp = (uint16_t)ins[8] << 8 | (uint16_t)ins[9]; + instru.fset = (uint32_t)ins[10] << 24 | (uint32_t)ins[11] << 16 | (uint32_t)ins[12] << 8 | (uint32_t)ins[13]; + uint8_t cali_mode = (uint8_t)ins[14]; //0:x/a+b 1:ax+b + + instru.gain_lv_hstia = HSRTIA_200R; + + set_hs_only(); + if (instru.gain_lv_hstia < HSRTIA_MAX) { + instru.HSTIAAutoGainEnable = 0; + HSTIAGainCtrl(instru.gain_lv_hstia); + } else { + instru.HSTIAAutoGainEnable = 1; + instru.gain_lv_hstia = HSRTIA_200R; + HSTIAGainCtrl(instru.gain_lv_hstia); + } + + HSDAC_outputV(instru.dcbias); + + + AD5940_SPIWriteReg(WGFCW, instru.fset); + AD5940_SPIWriteReg(WGCON, 0x0); // 0x0: DC disable ac first + AD5940_SPIWriteReg(WGAMPLITUDE, instru.acamp); + AD5940_SPIWriteReg(WGCON, 0x00000004); //0x4: Sinusoid + + led_color_set(LED_NB_MAX, LED_BR_LV1, LED_CLR_PURPLE); + SetEISHIGHZ(1); + + initCISBuf(); + cis_buf[0] = 6; + cis_buf[1] = 0xF7; + cis_buf[2] = ins[4]; + cis_buf[3] = ins[5]; + cis_buf[4] = ins[6]; + cis_buf[5] = ins[7]; + SimpleProfile_SetParameter(BLE_CIS_BUFF_CHAR, BLE_CIS_BUFF_SIZE, cis_buf); + break; + } + case 0xFD: { // ble write: 0x3000FF 20FFFFFFFFFFFF CTL_WRT //0x20->0xfd uint16_t address = (uint16_t)ins[4] << 8 | (uint16_t)ins[5]; uint32_t data = (uint32_t)ins[6] << 24 | (uint32_t)ins[7] << 16 | diff --git a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/mode_cf.h b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/mode_cf.h index 78efb7b..a17cc68 100644 --- a/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/mode_cf.h +++ b/simplelink/ble_sdk_2_02_02_25/src/examples/simple_peripheral/cc26xx/app/headstage/mode_cf.h @@ -45,7 +45,22 @@ static void decode_cf_mode(uint8_t *instruction) if (ins_step == DECODE_INS_MODE) { instru.eliteFxn = CURVE_CF; - setEIS_EIS(); + + set_hs_only(); + if (instru.gain_lv_hstia < HSRTIA_MAX) { + instru.HSTIAAutoGainEnable = 0; + HSTIAGainCtrl(instru.gain_lv_hstia); + } else { + instru.HSTIAAutoGainEnable = 1; + instru.gain_lv_hstia = HSRTIA_200R; + HSTIAGainCtrl(instru.gain_lv_hstia); + } + HSDAC_outputV(instru.dcbias); + //AD5940_SPIWriteReg(LPDACDAT0, DACOutCode); + AD5940_SPIWriteReg(WGFCW, instru.fset); + AD5940_SPIWriteReg(WGCON, 0x0); // 0x0: DC disable ac first + AD5940_SPIWriteReg(WGAMPLITUDE, instru.acamp); + AD5940_SPIWriteReg(WGCON, 0x00000004); //0x4: Sinusoid ModeLED(WORKING); return;