Roy_01
404 lines
13 KiB
C
404 lines
13 KiB
C
#include "elite_board.h"
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#include "nrf_gpio.h"
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#include "nrf_gpiote.h"
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#include "nrf_saadc.h"
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#include "nrf_spim.h"
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#include "nrf_timer.h"
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "task.h"
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#include "SEGGER_RTT.h"
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#if (DEF_ELITE_MODEL == DEF_ELITE_PEL_V2_0)
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void spim_xfer(uint32_t cs_pin,
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nrf_spim_mode_t spi_mode,
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uint8_t *p_tx_buffer,
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uint16_t tx_buffer_length,
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uint8_t *p_rx_buf,
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uint16_t rx_buffer_length)
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{
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__disable_irq();
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NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
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switch (spi_mode)
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{
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default:
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case NRF_SPIM_MODE_0:
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NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
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(SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
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(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
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break;
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case NRF_SPIM_MODE_1:
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NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
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(SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
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(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
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break;
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case NRF_SPIM_MODE_2:
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NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
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(SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
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(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
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break;
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case NRF_SPIM_MODE_3:
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NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
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(SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
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(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
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break;
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}
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NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
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NRF_SPIM3->TXD.MAXCNT = tx_buffer_length;
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NRF_SPIM3->TXD.PTR = (uint32_t)p_tx_buffer;
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NRF_SPIM3->RXD.MAXCNT = rx_buffer_length;
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NRF_SPIM3->RXD.PTR = (uint32_t)p_rx_buf;
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nrf_gpio_pin_clear(cs_pin);
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NRF_SPIM3->EVENTS_END = 0;
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NRF_SPIM3->TASKS_START = 1;
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do {
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} while (NRF_SPIM3->EVENTS_END == 0);
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nrf_gpio_pin_set(cs_pin);
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__enable_irq();
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}
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#define MIN_PULSE_WIDTH 2
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#define MIN_PULSE_IDLE 2
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#define MAX_PULSE_WIDTH INT16_MAX
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#define MAX_PULSE_IDLE INT16_MAX
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typedef struct
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{
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uint32_t anode_pin;
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uint32_t cathode_pin;
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uint32_t smaple_r_pin;
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uint32_t sample_v_pin;
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uint32_t test_pin;
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uint32_t point_us[5]; // toggle point timestamp
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uint32_t pulse_cnt; // min: 1, max: 0xFFFFFFFF
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uint32_t mode; // 0: IOPL mode, 1: IOPH mode
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nrf_saadc_gain_t gain;
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nrf_saadc_acqtime_t smaple_time;
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int32_t adc_timing_shift;
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} pel_config_t;
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typedef struct
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{
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nrf_saadc_gain_t gain;
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nrf_saadc_acqtime_t smaple_time;
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uint32_t channels[5];
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int16_t results[5];
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} pel_adc_t;
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typedef struct
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{
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NRF_TIMER_Type *pulse_tmr;
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uint32_t pulse_irq_n;
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uint32_t pulse_cnt;
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pel_adc_t adc;
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} pel_hw_t;
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pel_hw_t pel_hw = {
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.pulse_tmr = NRF_TIMER3,
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.pulse_irq_n = TIMER3_IRQn,
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.pulse_cnt = 0,
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.adc.channels = {
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[OUTPUT_R1_IDX] = OUTPUT_R1_CHANNEL,
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[OUTPUT_R2_IDX] = OUTPUT_R2_CHANNEL,
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[OUTPUT_VO_IDX] = OUTPUT_VO_CHANNEL,
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[OUTPUT_VC_IDX] = OUTPUT_VC_CHANNEL,
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[OUTPUT_VE_IDX] = OUTPUT_VE_CHANNEL},
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.adc.gain = NRF_SAADC_GAIN1_6,
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.adc.smaple_time = NRF_SAADC_ACQTIME_3US
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};
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static void pel_saadc_init(pel_adc_t *p_adc)
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{
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/* stop ssadc */
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NRF_SAADC->EVENTS_STOPPED = 0;
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NRF_SAADC->TASKS_STOP = 1;
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do {
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} while (NRF_SAADC->EVENTS_STOPPED == 0);
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/* disable ssadc */
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NRF_SAADC->ENABLE = 0;
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/*
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ref: p.381, nrf52840_PS_v1.1.pdf
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Note: Oversampling should only be used when a single input channel is enabled, as averaging is
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performed over all enabled channels.
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*/
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NRF_SAADC->OVERSAMPLE = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass;
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NRF_SAADC->RESOLUTION = SAADC_RESOLUTION_VAL_14bit;
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/* config analog inputs */
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for (uint32_t i = 0; i < COUNTOF(NRF_SAADC->CH); i++)
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{
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if (i < COUNTOF(p_adc->channels))
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{
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NRF_SAADC->CH[i].PSELP = NRF_SAADC_INPUT_AIN0 + p_adc->channels[i];
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NRF_SAADC->CH[i].PSELN = NRF_SAADC_INPUT_DISABLED;
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NRF_SAADC->CH[i].CONFIG =
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(NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESP_Pos) |
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(NRF_SAADC_RESISTOR_DISABLED << SAADC_CH_CONFIG_RESN_Pos) |
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(p_adc->gain << SAADC_CH_CONFIG_GAIN_Pos) |
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(NRF_SAADC_REFERENCE_INTERNAL << SAADC_CH_CONFIG_REFSEL_Pos) |
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(p_adc->smaple_time << SAADC_CH_CONFIG_TACQ_Pos) |
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(NRF_SAADC_MODE_SINGLE_ENDED << SAADC_CH_CONFIG_MODE_Pos) |
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(NRF_SAADC_BURST_DISABLED << SAADC_CH_CONFIG_BURST_Pos);
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}
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else
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{
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NRF_SAADC->CH[i].PSELP = NRF_SAADC_INPUT_DISABLED;
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NRF_SAADC->CH[i].PSELN = NRF_SAADC_INPUT_DISABLED;
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NRF_SAADC->CH[i].CONFIG = 0;
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}
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}
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/* enable ssadc */
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NRF_SAADC->ENABLE = 1;
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NRF_SAADC->RESULT.PTR = (uint32_t)p_adc->results;
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NRF_SAADC->RESULT.MAXCNT = COUNTOF(p_adc->results);
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}
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void TIMER3_IRQHandler(void)
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{
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if (pel_hw.pulse_tmr->EVENTS_COMPARE[0])
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{
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pel_hw.pulse_tmr->EVENTS_COMPARE[0] = 0;
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if (pel_hw.pulse_cnt)
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{
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pel_hw.pulse_cnt--;
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}
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}
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else if (pel_hw.pulse_tmr->EVENTS_COMPARE[5])
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{
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pel_hw.pulse_tmr->EVENTS_COMPARE[5] = 0;
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if (pel_hw.pulse_cnt)
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{
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NRF_SAADC->RESULT.PTR = (uint32_t)pel_hw.adc.results;
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NRF_SAADC->RESULT.MAXCNT = COUNTOF(pel_hw.adc.results);
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}
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else
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{
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pel_hw.pulse_tmr->TASKS_STOP = 1;
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}
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}
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}
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void pel_pulse_gen_init(pel_config_t cfg)
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{
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pel_hw.pulse_tmr->TASKS_STOP = 1;
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sd_nvic_DisableIRQ(pel_hw.pulse_irq_n);
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sd_nvic_ClearPendingIRQ(pel_hw.pulse_irq_n);
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pel_hw.pulse_cnt = cfg.pulse_cnt;
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pel_hw.adc.gain = cfg.gain;
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pel_hw.adc.smaple_time = cfg.smaple_time;
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pel_saadc_init(&pel_hw.adc);
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switch (cfg.mode)
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{
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default:
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case 1:
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nrf_gpiote_task_configure(0, cfg.anode_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
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nrf_gpiote_task_enable(0);
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nrf_gpiote_task_configure(1, cfg.cathode_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_HIGH);
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nrf_gpiote_task_enable(1);
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break;
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case 0:
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nrf_gpiote_task_configure(0, cfg.anode_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_HIGH);
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nrf_gpiote_task_enable(0);
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nrf_gpiote_task_configure(1, cfg.cathode_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
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nrf_gpiote_task_enable(1);
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break;
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}
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nrf_gpiote_task_configure(2, cfg.smaple_r_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
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nrf_gpiote_task_enable(2);
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nrf_gpiote_task_configure(3, cfg.sample_v_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
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nrf_gpiote_task_enable(3);
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if (cfg.test_pin != 0xFFFFFFFF)
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{
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nrf_gpiote_task_configure(4, cfg.test_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW);
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nrf_gpiote_task_enable(4);
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}
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NRF_PPI->CH[0].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[0];
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NRF_PPI->CH[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0];
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NRF_PPI->FORK[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1];
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NRF_PPI->CHENSET = (1 << (0));
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NRF_PPI->CH[1].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[1];
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NRF_PPI->CH[1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2];
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NRF_PPI->FORK[1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3];
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NRF_PPI->CHENSET = (1 << (1));
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NRF_PPI->CH[2].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[2];
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NRF_PPI->CH[2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2];
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NRF_PPI->FORK[2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3];
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NRF_PPI->CHENSET = (1 << (2));
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NRF_PPI->CH[3].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[3];
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NRF_PPI->CH[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0];
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NRF_PPI->FORK[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1];
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NRF_PPI->CHENSET = (1 << (3));
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NRF_PPI->CH[4].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[4];
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NRF_PPI->CH[4].TEP = (uint32_t)&NRF_SAADC->TASKS_START;
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NRF_PPI->CHENSET = (1 << (4));
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if (cfg.test_pin != 0xFFFFFFFF)
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{
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NRF_PPI->CH[6].EEP = (uint32_t)&NRF_SAADC->EVENTS_STARTED;
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NRF_PPI->CH[6].TEP = (uint32_t)&NRF_SAADC->TASKS_SAMPLE;
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NRF_PPI->FORK[6].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4];
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NRF_PPI->CHENSET = (1 << (6));
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NRF_PPI->CH[7].EEP = (uint32_t)&NRF_SAADC->EVENTS_END;
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NRF_PPI->CH[7].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4];
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NRF_PPI->CHENSET = (1 << (7));
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}
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pel_hw.pulse_tmr->PRESCALER = NRF_TIMER_FREQ_16MHz;
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pel_hw.pulse_tmr->MODE = NRF_TIMER_MODE_TIMER;
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pel_hw.pulse_tmr->BITMODE = NRF_TIMER_BIT_WIDTH_32;
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pel_hw.pulse_tmr->CC[0] = 1;
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pel_hw.pulse_tmr->CC[1] = pel_hw.pulse_tmr->CC[0] + cfg.point_us[1] * 16;
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pel_hw.pulse_tmr->CC[2] = pel_hw.pulse_tmr->CC[1] + cfg.point_us[2] * 16;
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pel_hw.pulse_tmr->CC[3] = pel_hw.pulse_tmr->CC[2] + cfg.point_us[3] * 16;
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pel_hw.pulse_tmr->CC[4] = pel_hw.pulse_tmr->CC[3] + cfg.point_us[4] * 16 + cfg.adc_timing_shift;
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pel_hw.pulse_tmr->CC[5] = pel_hw.pulse_tmr->CC[4] + cfg.point_us[0] * 16;
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pel_hw.pulse_tmr->SHORTS = NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK;
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pel_hw.pulse_tmr->INTENSET = NRF_TIMER_INT_COMPARE0_MASK | NRF_TIMER_INT_COMPARE5_MASK;
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sd_nvic_SetPriority(pel_hw.pulse_irq_n, _PRIO_APP_HIGH);
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sd_nvic_EnableIRQ(pel_hw.pulse_irq_n);
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}
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void pel_pulse_gen_start(void)
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{
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pel_hw.pulse_tmr->TASKS_START = 1;
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}
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void pel_pulse_gen_stop(void)
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{
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pel_hw.pulse_cnt = 0;
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}
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#if (DEF_ELITE_DEMO_W_SOFTDEVICE == 1) || (DEF_ELITE_DEMO_WO_SOFTDEVICE == 1)
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static void pel_pulse_gen_demo_task(void *p_arg)
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{
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pel_config_t pel_cfg = {
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.anode_pin = ANODE_PIN,
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.cathode_pin = CATHODE_PIN,
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.smaple_r_pin = SAMPLE_R_PIN,
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.sample_v_pin = SAMPLE_V_PIN,
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.test_pin = NRF_GPIO_PIN_MAP(0, 5),
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.mode = 1,
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.point_us = {
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10000,
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3,
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5,
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2,
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0,
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},
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.pulse_cnt = 0xFFFFFFFF,
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.gain = NRF_SAADC_GAIN1_6,
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.smaple_time = NRF_SAADC_ACQTIME_10US,
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.adc_timing_shift = 0,
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};
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pel_pulse_gen_init(pel_cfg);
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pel_pulse_gen_start();
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for (;;)
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{
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static uint32_t i = 0;
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vTaskDelay(pdMS_TO_TICKS(pel_cfg.point_us[0] / 1000));
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SEGGER_RTT_printf(0, "%d, %d, %d, %d, %d, %d\r\n", i++, pel_hw.adc.results[0], pel_hw.adc.results[1], pel_hw.adc.results[2], pel_hw.adc.results[3], pel_hw.adc.results[4]);
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}
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}
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void pel_pulse_gen_demo(void)
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{
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xTaskCreate(pel_pulse_gen_demo_task, "pel_demo", 256, NULL, 3, NULL);
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}
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#endif
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void pel20_io_init(void)
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{
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const uint32_t pel_pins_default_high[] = {
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INPUT_1_PIN,
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INPUT_2_PIN,
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INPUT_3_PIN,
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INPUT_4_PIN,
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INPUT_5_PIN,
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INPUT_6_PIN,
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INPUT_7_PIN,
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INPUT_8_PIN,
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INPUT_9_PIN,
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INPUT_10_PIN,
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INPUT_11_PIN,
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INPUT_12_PIN
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};
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const uint32_t pel_pins_default_low[] = {
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ANODE_PIN,
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CATHODE_PIN,
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SAMPLE_R_PIN,
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SAMPLE_V_PIN,
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RELAY1_PIN,
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RELAY2_PIN
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};
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for (int i = 0; i < COUNTOF(pel_pins_default_high); i++)
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{
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nrf_gpio_pin_set(pel_pins_default_high[i]);
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nrf_gpio_cfg_output(pel_pins_default_high[i]);
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}
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for (int i = 0; i < COUNTOF(pel_pins_default_low); i++)
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{
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nrf_gpio_pin_clear(pel_pins_default_low[i]);
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nrf_gpio_cfg_output(pel_pins_default_low[i]);
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}
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// Config spi module
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nrf_gpio_pin_set(WP_MEM_PIN);
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nrf_gpio_cfg_output(WP_MEM_PIN);
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nrf_gpio_pin_set(CS_MEM_PIN);
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nrf_gpio_cfg_output(CS_MEM_PIN);
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nrf_gpio_pin_clear(SPIM_MOSI_PIN);
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nrf_gpio_cfg_output(SPIM_MOSI_PIN);
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nrf_gpio_pin_clear(SPIM_CLK_PIN);
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nrf_gpio_cfg_output(SPIM_CLK_PIN);
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nrf_gpio_cfg_input(SPIM_MISO_PIN, NRF_GPIO_PIN_NOPULL);
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NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
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NRF_SPIM3->ORC = 0x00000000;
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NRF_SPIM3->FREQUENCY = SPIM_FREQUENCY_FREQUENCY_M32;
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NRF_SPIM3->CSNPOL = SPIM_CSNPOL_CSNPOL_LOW;
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NRF_SPIM3->IFTIMING.CSNDUR = 8;
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NRF_SPIM3->PSEL.CSN = CS_MEM_PIN;
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NRF_SPIM3->PSEL.SCK = SPIM_CLK_PIN;
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NRF_SPIM3->PSEL.MOSI = SPIM_MOSI_PIN;
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NRF_SPIM3->PSEL.MISO = SPIM_MISO_PIN;
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NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
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}
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#endif
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