wisetop/microchip-application-bmd380-bmd380_peripheral
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
a96cc2feb23740c8b1dd2e3d392fc733d83f084d
microchip-application-bmd38…/edc20_io.c
T
Roy_01 9b9c710f63 update: redefine elite model
2024-10-01 16:10:30 +08:00

722 lines
20 KiB
C
Raw Blame History

#include "elite_board.h"
#include "nrf_drv_spi.h"
#include "nrf_drv_twi.h"
#include "nrf_gpio.h"
#include "nrf_log.h"
#include "nrf_timer.h"
#include "FreeRTOS.h"
#include "queue.h"
#include "semphr.h"
#include "adc_drv.h"
#include "dac_drv.h"
#include "sw_drv.h"
#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_V2_0)
//==========================================================
// gpio
//==========================================================
void gpio_init(void)
{
nrf_gpio_pin_set(POWER_5V_EN_PIN);
nrf_gpio_pin_set(POWER_12V_EN_PIN);
nrf_gpio_pin_set(OFF_PIN);
nrf_gpio_pin_clear(Vout_FB_PIN);
nrf_gpio_pin_clear(Vout_IN_PIN);
nrf_gpio_pin_clear(Iin4_TEST_PIN);
nrf_gpio_pin_clear(Iin3_SEL_PIN);
nrf_gpio_pin_clear(Iin3_PIN);
nrf_gpio_pin_clear(Iin2_PIN);
nrf_gpio_pin_clear(Iin1_PIN);
nrf_gpio_pin_clear(Vin2_PIN);
nrf_gpio_pin_clear(Vin1_PIN);
nrf_gpio_pin_clear(CV_CTRL_PIN);
nrf_gpio_pin_clear(ADCA2_PIN);
nrf_gpio_pin_clear(ADCA1_PIN);
nrf_gpio_pin_clear(ADCA0_PIN);
nrf_gpio_pin_clear(RST_SW_PIN);
nrf_gpio_cfg_output(POWER_5V_EN_PIN);
nrf_gpio_cfg_output(POWER_12V_EN_PIN);
nrf_gpio_cfg_output(OFF_PIN);
nrf_gpio_cfg_output(Vout_FB_PIN);
nrf_gpio_cfg_output(Vout_IN_PIN);
nrf_gpio_cfg_output(Iin4_TEST_PIN);
nrf_gpio_cfg_output(Iin3_SEL_PIN);
nrf_gpio_cfg_output(Iin3_PIN);
nrf_gpio_cfg_output(Iin2_PIN);
nrf_gpio_cfg_output(Iin1_PIN);
nrf_gpio_cfg_output(Vin2_PIN);
nrf_gpio_cfg_output(Vin1_PIN);
nrf_gpio_cfg_output(CV_CTRL_PIN);
nrf_gpio_cfg_output(ADCA2_PIN);
nrf_gpio_cfg_output(ADCA1_PIN);
nrf_gpio_cfg_output(ADCA0_PIN);
nrf_gpio_cfg_output(RST_SW_PIN);
nrf_gpio_cfg_output(CS_SW_PIN);
nrf_gpio_cfg_output(CS_MEM_PIN);
nrf_gpio_cfg_output(CS_ADC_PIN);
nrf_gpio_cfg_output(CS_DAC_PIN);
nrf_gpio_cfg_input(VBAT_PIN, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(SHUT_DOWN_PIN, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(INT9466_PIN, NRF_GPIO_PIN_NOPULL);
// Config spi cs pin
uint32_t cs_pins[] = {
CS_SW_PIN, CS_MEM_PIN, CS_ADC_PIN, CS_DAC_PIN
};
for (int i = 0; i < COUNTOF(cs_pins); i++)
{
nrf_gpio_pin_set(cs_pins[i]);
nrf_gpio_cfg(
cs_pins[i],
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_H0H1,
NRF_GPIO_PIN_NOSENSE);
}
// Config spi mosi pin
nrf_gpio_pin_set(SPIM_MOSI_PIN);
nrf_gpio_cfg(
SPIM_MOSI_PIN,
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_H0H1,
NRF_GPIO_PIN_NOSENSE);
// Config spi miso pin
nrf_gpio_cfg_input(SPIM_MISO_PIN, NRF_GPIO_PIN_NOPULL);
// Config spi clk pin
nrf_gpio_pin_clear(SPIM_CLK_PIN);
nrf_gpio_cfg(
SPIM_CLK_PIN,
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_H0H1,
NRF_GPIO_PIN_NOSENSE);
}
// circuit_select combination
void circuit_selection_vin_0(void)
{
nrf_gpio_pin_clear(Vin1_PIN);
nrf_gpio_pin_clear(Vin2_PIN);
}
void circuit_selection_vin_1(void)
{
nrf_gpio_pin_set(Vin1_PIN);
nrf_gpio_pin_clear(Vin2_PIN);
}
void circuit_selection_vin_2(void)
{
nrf_gpio_pin_clear(Vin1_PIN);
nrf_gpio_pin_set(Vin2_PIN);
}
void circuit_selection_Iin_0(void)
{
nrf_gpio_pin_clear(Iin4_TEST_PIN);
nrf_gpio_pin_clear(Iin3_SEL_PIN);
nrf_gpio_pin_clear(Iin1_PIN);
nrf_gpio_pin_clear(Iin2_PIN);
nrf_gpio_pin_clear(Iin3_PIN);
}
void circuit_selection_Iin_1(void)
{
nrf_gpio_pin_clear(Iin4_TEST_PIN);
nrf_gpio_pin_clear(Iin3_SEL_PIN);
nrf_gpio_pin_set(Iin1_PIN);
nrf_gpio_pin_clear(Iin2_PIN);
nrf_gpio_pin_clear(Iin3_PIN);
}
void circuit_selection_Iin_2(void)
{
nrf_gpio_pin_clear(Iin4_TEST_PIN);
nrf_gpio_pin_clear(Iin3_SEL_PIN);
nrf_gpio_pin_clear(Iin1_PIN);
nrf_gpio_pin_set(Iin2_PIN);
nrf_gpio_pin_clear(Iin3_PIN);
}
void circuit_selection_Iin_3(void)
{
nrf_gpio_pin_clear(Iin4_TEST_PIN);
nrf_gpio_pin_set(Iin3_SEL_PIN);
nrf_gpio_pin_clear(Iin1_PIN);
nrf_gpio_pin_clear(Iin2_PIN);
nrf_gpio_pin_set(Iin3_PIN);
}
void circuit_selection_Iin_4(void)
{
nrf_gpio_pin_set(Iin4_TEST_PIN);
nrf_gpio_pin_clear(Iin3_SEL_PIN);
nrf_gpio_pin_clear(Iin1_PIN);
nrf_gpio_pin_clear(Iin2_PIN);
nrf_gpio_pin_clear(Iin3_PIN);
}
void circuit_selection_dac_coarse_tune_c(void)
{
sw_t sw;
uint32_t sw_cnt;
sw_count(&sw_cnt);
sw_read(&sw);
sw.val = 0b10000000;
NRF_LOG_INFO("sw.val= %08X", sw.val);
NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
sw_write(sw);
nrf_gpio_pin_set(Vout_FB_PIN);
nrf_gpio_pin_clear(Vout_IN_PIN);
}
void circuit_selection_dac_fine_tune_f0(void)
{
sw_t sw;
uint32_t sw_cnt;
sw_count(&sw_cnt);
sw_read(&sw);
sw.val = 0b10000100;
NRF_LOG_INFO("sw.val= %08X", sw.val);
NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
sw_write(sw);
nrf_gpio_pin_set(Vout_FB_PIN);
nrf_gpio_pin_clear(Vout_IN_PIN);
}
void circuit_selection_dac_fine_tune_f1(void)
{
sw_t sw;
uint32_t sw_cnt;
sw_count(&sw_cnt);
sw_read(&sw);
sw.val = 0b10001000;
NRF_LOG_INFO("sw.val= %08X", sw.val);
NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
sw_write(sw);
nrf_gpio_pin_set(Vout_FB_PIN);
nrf_gpio_pin_clear(Vout_IN_PIN);
}
void circuit_selection_dac_fine_tune_f2(void)
{
sw_t sw;
uint32_t sw_cnt;
sw_count(&sw_cnt);
sw_read(&sw);
sw.val = 0b10000000;
NRF_LOG_INFO("sw.val= %08X", sw.val);
NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
sw_write(sw);
nrf_gpio_pin_set(Vout_FB_PIN);
nrf_gpio_pin_clear(Vout_IN_PIN);
}
void circuit_selection_dac_circuit_open(void)
{
sw_t sw;
uint32_t sw_cnt;
sw_count(&sw_cnt);
sw_read(&sw);
sw.sw4 = 0;
sw.sw5 = 0;
sw.sw6 = 0;
sw.sw7 = 0;
NRF_LOG_INFO("sw.val= %08X", sw.val);
NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
sw_write(sw);
}
void circuit_selection_cv3_config(void)
{
nrf_gpio_pin_clear(Vout_FB_PIN);
nrf_gpio_pin_set(Vout_IN_PIN);
nrf_gpio_pin_clear(Iin4_TEST_PIN);
nrf_gpio_pin_clear(Iin3_SEL_PIN);
nrf_gpio_pin_clear(Iin1_PIN);
nrf_gpio_pin_clear(Iin2_PIN);
nrf_gpio_pin_clear(Iin3_PIN);
nrf_gpio_pin_set(CV_CTRL_PIN);
}
void circuit_selection_cc_config(void)
{
nrf_gpio_pin_clear(Vout_FB_PIN);
nrf_gpio_pin_set(Vout_IN_PIN);
nrf_gpio_pin_clear(Iin4_TEST_PIN);
nrf_gpio_pin_clear(Iin3_SEL_PIN);
nrf_gpio_pin_clear(Iin1_PIN);
nrf_gpio_pin_clear(Iin2_PIN);
nrf_gpio_pin_clear(Iin3_PIN);
nrf_gpio_pin_clear(CV_CTRL_PIN);
}
//==========================================================
// i2c
//==========================================================
static const nrf_drv_twi_t twi0 = NRF_DRV_TWI_INSTANCE(0);
static SemaphoreHandle_t i2c_sem = NULL;
static SemaphoreHandle_t i2c_mutex = NULL;
static QueueHandle_t i2c_evt_queue = NULL;
static void nrf_drv_twi_evt_handler(nrf_drv_twi_evt_t const *p_event, void *p_context)
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
xQueueSendFromISR(i2c_evt_queue, p_event, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
}
void twi_init(void)
{
ret_code_t err_code;
i2c_sem = xSemaphoreCreateBinary();
i2c_mutex = xSemaphoreCreateMutex();
i2c_evt_queue = xQueueCreate(2, sizeof(nrf_drv_twi_evt_t));
const nrf_drv_twi_config_t twi0_config = {
.scl = I2C0_SCL,
.sda = I2C0_SDA,
.frequency = NRF_DRV_TWI_FREQ_100K,
.interrupt_priority = APP_IRQ_PRIORITY_HIGH,
.clear_bus_init = true
};
err_code = nrf_drv_twi_init(&twi0, &twi0_config, nrf_drv_twi_evt_handler, NULL);
APP_ERROR_CHECK(err_code);
nrf_drv_twi_enable(&twi0);
}
void twi0_write_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t data_len)
{
xSemaphoreTake(i2c_mutex, portMAX_DELAY);
static uint8_t i2c_buf[255];
static nrf_drv_twi_evt_t evt;
ret_code_t err_code;
memcpy(i2c_buf, &reg_addr, sizeof(reg_addr));
memcpy(i2c_buf + sizeof(reg_addr), data, data_len);
err_code = nrf_drv_twi_tx(&twi0, slave_addr, i2c_buf, data_len + 1, false);
APP_ERROR_CHECK(err_code);
xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
switch (evt.type)
{
/* Transfer completed event. */
case NRF_DRV_TWI_EVT_DONE:
// TODO...
break;
/* Error event: NACK received after sending the address. */
case NRF_DRV_TWI_EVT_ADDRESS_NACK:
// TODO...
__BKPT(255);
break;
/* Error event: NACK received after sending a data byte. */
case NRF_DRV_TWI_EVT_DATA_NACK:
// TODO...
__BKPT(255);
break;
default:
__BKPT(255);
break;
}
xSemaphoreGive(i2c_mutex);
NRF_LOG_INFO("i2c(W): slave_addr=0x%02x", slave_addr);
NRF_LOG_HEXDUMP_INFO(i2c_buf, data_len + 1);
}
void twi0_read_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *p_rx_buf, uint8_t rx_buffer_length)
{
xSemaphoreTake(i2c_mutex, portMAX_DELAY);
nrf_drv_twi_evt_t evt;
ret_code_t err_code;
err_code = nrf_drv_twi_tx(&twi0, slave_addr, &reg_addr, sizeof(reg_addr), false);
APP_ERROR_CHECK(err_code);
xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
switch (evt.type)
{
/* Transfer completed event. */
case NRF_DRV_TWI_EVT_DONE:
// TODO...
break;
/* Error event: NACK received after sending the address. */
case NRF_DRV_TWI_EVT_ADDRESS_NACK:
// TODO...
__BKPT(255);
break;
/* Error event: NACK received after sending a data byte. */
case NRF_DRV_TWI_EVT_DATA_NACK:
// TODO...
__BKPT(255);
break;
default:
break;
}
err_code = nrf_drv_twi_rx(&twi0, slave_addr, p_rx_buf, rx_buffer_length);
APP_ERROR_CHECK(err_code);
xQueueReceive(i2c_evt_queue, &evt, portMAX_DELAY);
switch (evt.type)
{
/* Transfer completed event. */
case NRF_DRV_TWI_EVT_DONE:
// TODO...
break;
/* Error event: NACK received after sending the address. */
case NRF_DRV_TWI_EVT_ADDRESS_NACK:
// TODO...
__BKPT(255);
break;
/* Error event: NACK received after sending a data byte. */
case NRF_DRV_TWI_EVT_DATA_NACK:
// TODO...
__BKPT(255);
break;
default:
break;
}
xSemaphoreGive(i2c_mutex);
NRF_LOG_INFO("i2c(R): slave_addr=0x%02x reg_addr=0x%02x", slave_addr, reg_addr);
NRF_LOG_HEXDUMP_INFO(p_rx_buf, rx_buffer_length);
}
//==========================================================
// spi
//==========================================================
static const nrf_drv_spi_t spim1 = NRF_DRV_SPI_INSTANCE(1); /**< SPI instance. */
static SemaphoreHandle_t spim1_sem = NULL;
static void nrf_drv_spim1_evt_handler(nrf_drv_spi_evt_t const *p_event, void *p_context)
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
switch (p_event->type)
{
case NRF_DRV_SPI_EVENT_DONE:
xSemaphoreGiveFromISR(spim1_sem, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
break;
default:
break;
}
}
void spi_init(void)
{
spim1_sem = xSemaphoreCreateBinary();
nrf_drv_spi_config_t spi1_config = NRF_DRV_SPI_DEFAULT_CONFIG;
spi1_config.ss_pin = NRF_DRV_SPI_PIN_NOT_USED;
spi1_config.miso_pin = NRF_DRV_SPI_PIN_NOT_USED;
spi1_config.mosi_pin = SPI1_MOSI_PIN;
spi1_config.sck_pin = SPI1_CLK_PIN;
spi1_config.mode = NRF_DRV_SPI_MODE_0;
spi1_config.frequency = NRF_DRV_SPI_FREQ_8M;
APP_ERROR_CHECK(nrf_drv_spi_init(&spim1, &spi1_config, nrf_drv_spim1_evt_handler, NULL));
// Config spi module
NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
NRF_SPIM3->ORC = 0x00000000;
NRF_SPIM3->FREQUENCY = SPIM_FREQUENCY_FREQUENCY_M32;
NRF_SPIM3->CSNPOL = SPIM_CSNPOL_CSNPOL_LOW;
NRF_SPIM3->IFTIMING.CSNDUR = 8;
NRF_SPIM3->PSEL.SCK = SPIM_CLK_PIN;
NRF_SPIM3->PSEL.MOSI = SPIM_MOSI_PIN;
NRF_SPIM3->PSEL.MISO = SPIM_MISO_PIN;
NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
}
void spi1_write(uint8_t *p_tx_buffer, uint16_t tx_buffer_length)
{
APP_ERROR_CHECK(nrf_drv_spi_transfer(&spim1, p_tx_buffer, tx_buffer_length, NULL, 0));
xSemaphoreTake(spim1_sem, portMAX_DELAY);
}
void spim_xfer(uint32_t cs_pin, nrf_spim_mode_t spi_mode, uint8_t *p_tx_buffer, uint16_t tx_buffer_length, uint8_t *p_rx_buf, uint16_t rx_buffer_length)
{
__disable_irq();
/* set spi mode and order */
NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
switch (spi_mode)
{
default:
case NRF_SPIM_MODE_0:
NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
(SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
break;
case NRF_SPIM_MODE_1:
NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
(SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
break;
case NRF_SPIM_MODE_2:
NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
(SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
(SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
break;
case NRF_SPIM_MODE_3:
NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
(SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
(SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
break;
}
NRF_SPIM3->PSEL.CSN = cs_pin;
NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
if (p_tx_buffer != NULL)
{
NRF_SPIM3->TXD.PTR = (uint32_t)p_tx_buffer;
NRF_SPIM3->TXD.MAXCNT = tx_buffer_length;
}
else
{
NRF_SPIM3->TXD.MAXCNT = 0;
}
if (p_rx_buf != NULL)
{
NRF_SPIM3->RXD.PTR = (uint32_t)p_rx_buf;
NRF_SPIM3->RXD.MAXCNT = rx_buffer_length;
}
else
{
NRF_SPIM3->RXD.MAXCNT = 0;
}
/* workaround for ADC acquisition time */
nrf_gpio_pin_set(CS_ADC_PIN);
NRF_SPIM3->EVENTS_END = 0;
NRF_SPIM3->TASKS_START = 1;
do {
} while (NRF_SPIM3->EVENTS_END == 0);
NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
NRF_SPIM3->PSEL.CSN = 0xFFFFFFFF;
NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
/* workaround for ADC acquisition time */
nrf_gpio_pin_clear(CS_ADC_PIN);
__enable_irq();
}
//==========================================================
// timer
//==========================================================
#if (DEF_DAC_DRV_ENABLED)
#define ELITE_DAC_TMR NRF_TIMER2
static void (*dac_tmr_cb)(void *p_arg) = NULL;
static void *dac_tmr_p_arg = NULL;
void TIMER2_IRQHandler(void)
{
if (ELITE_DAC_TMR->EVENTS_COMPARE[0])
{
ELITE_DAC_TMR->EVENTS_COMPARE[0] = 0;
if (dac_tmr_cb)
{
dac_tmr_cb(dac_tmr_p_arg);
}
return;
}
}
void edc20_dac_tim_start(uint32_t period, void (*callback)(void *p_arg), void *p_arg)
{
NRF_LOG_INFO("%s()", __FUNCTION__);
__disable_irq();
sd_nvic_DisableIRQ(TIMER2_IRQn);
sd_nvic_ClearPendingIRQ(TIMER2_IRQn);
ELITE_DAC_TMR->SHORTS = 0;
ELITE_DAC_TMR->TASKS_STOP = 1;
dac_tmr_p_arg = p_arg;
dac_tmr_cb = callback;
ELITE_DAC_TMR->PRESCALER = NRF_TIMER_FREQ_1MHz;
ELITE_DAC_TMR->MODE = NRF_TIMER_MODE_TIMER;
ELITE_DAC_TMR->BITMODE = NRF_TIMER_BIT_WIDTH_32;
ELITE_DAC_TMR->INTENSET = NRF_TIMER_INT_COMPARE0_MASK;
ELITE_DAC_TMR->CC[0] = period;
ELITE_DAC_TMR->SHORTS = NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK;
sd_nvic_SetPriority(TIMER2_IRQn, _PRIO_APP_HIGH);
sd_nvic_EnableIRQ(TIMER2_IRQn);
ELITE_DAC_TMR->TASKS_CLEAR = 1;
ELITE_DAC_TMR->TASKS_START = 1;
__enable_irq();
}
void edc20_dac_tim_stop(void)
{
NRF_LOG_INFO("%s()", __FUNCTION__);
__disable_irq();
dac_tmr_cb = NULL;
dac_tmr_p_arg = NULL;
sd_nvic_DisableIRQ(TIMER2_IRQn);
sd_nvic_ClearPendingIRQ(TIMER2_IRQn);
ELITE_DAC_TMR->TASKS_STOP = 1;
ELITE_DAC_TMR->SHORTS = 0;
__enable_irq();
}
#endif /* ! DEF_DAC_DRV_ENABLED */
#if (DEF_ADC_DRV_ENABLED)
#define ELITE_ADC_TMR NRF_TIMER3
void TIMER3_IRQHandler(void)
{
if (ELITE_ADC_TMR->EVENTS_COMPARE[0])
{
ELITE_ADC_TMR->EVENTS_COMPARE[0] = 0;
float mv;
extern int adc_read_milivolt(uint32_t channel, float *mv);
adc_read_milivolt(2, &mv);
float v = mv / 1000.0 - 5;
#if (DEF_RTT_JSCOP_ENABLED)
extern void j_scope_update(float f);
j_scope_update(v * 5);
#endif
return;
}
if (ELITE_ADC_TMR->EVENTS_COMPARE[1])
{
ELITE_ADC_TMR->EVENTS_COMPARE[1] = 0;
int32_t val;
adc_read(1, &val);
return;
}
if (ELITE_ADC_TMR->EVENTS_COMPARE[2])
{
ELITE_ADC_TMR->EVENTS_COMPARE[2] = 0;
int32_t val;
adc_read(2, &val);
return;
}
}
void edc20_adc_tim_start(elite_dac_config_t *p_config)
{
NRF_LOG_INFO("%s()", __FUNCTION__);
/*
ADC Sample rate 10KHz
*/
ELITE_ADC_TMR->PRESCALER = NRF_TIMER_FREQ_1MHz;
ELITE_ADC_TMR->MODE = NRF_TIMER_MODE_TIMER;
ELITE_ADC_TMR->BITMODE = NRF_TIMER_BIT_WIDTH_32;
ELITE_ADC_TMR->INTENSET = NRF_TIMER_INT_COMPARE0_MASK;
ELITE_ADC_TMR->CC[0] = 1000;
ELITE_ADC_TMR->SHORTS = NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK;
sd_nvic_SetPriority(TIMER3_IRQn, _PRIO_APP_HIGH);
sd_nvic_EnableIRQ(TIMER3_IRQn);
}
void edc20_adc_tim_stop(void)
{
NRF_LOG_INFO("%s()", __FUNCTION__);
}
#endif /* ! DEF_ADC_DRV_ENABLED */
void edc20_io_init(void)
{
gpio_init();
twi_init();
spi_init();
}
void edc20_io_power_off(void)
{
nrf_gpio_pin_clear(OFF_PIN);
nrf_gpio_pin_clear(POWER_12V_EN_PIN);
nrf_gpio_pin_clear(POWER_5V_EN_PIN);
for (;;)
{
__DSB();
__ISB();
}
}
void edc20_io_power_on(void)
{
uint32_t cnt = 0;
for (int i = 0; i < 1000 / 50; i++)
{
vTaskDelay(pdMS_TO_TICKS(50));
if (nrf_gpio_pin_read(SHUT_DOWN_PIN))
{
cnt++;
if (cnt == 2)
{
edc20_io_power_off();
}
}
}
}
#endif /* ! DEF_ELITE_MODEL */
Reference in New Issue View Git Blame Copy Permalink