Roy_01
498690219e
1. to set the resistors, the large resistor (Input12) needs to be controlled first 2. new dev_mode: pel_select_resistor_combinations_mode
619 lines
19 KiB
C
619 lines
19 KiB
C
#include "pel.h"
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#include "pel10_io.h"
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#include "elite_def.h"
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#include "nrf_delay.h"
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#include "nrf_gpio.h"
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#include "nrf_log.h"
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#include "adc_drv.h"
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#if (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
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typedef struct
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{
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float val;
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uint32_t pin;
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uint32_t mask;
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} input_pin_t;
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TaskHandle_t test_gpio_task_Handle = NULL;
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static pel_output_t output_data = { 0 };
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const input_pin_t input_pin_tab[] = {
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{ 0.5, INPUT_1_PIN, PEL_0P5R_MASK},
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{ 1.0, INPUT_2_PIN, PEL_1P0R_MASK},
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{ 2.0, INPUT_3_PIN, PEL_2P0R_MASK},
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{ 4.0, INPUT_4_PIN, PEL_4P0R_MASK},
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{ 8.0, INPUT_5_PIN, PEL_8P0R_MASK},
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{ 16.2, INPUT_6_PIN, PEL_16P2R_MASK},
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{ 32.4, INPUT_7_PIN, PEL_32P4R_MASK},
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{ 63.4, INPUT_8_PIN, PEL_63P4R_MASK},
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{ 127.0, INPUT_9_PIN, PEL_127R_MASK},
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{ 255.0, INPUT_10_PIN, PEL_255R_MASK},
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{ 511.0, INPUT_11_PIN, PEL_511R_MASK},
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{1000.0, INPUT_12_PIN, PEL_1000R_MASK},
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};
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static float _load_set(uint32_t mask)
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{
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float ohms = 0;
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for (int32_t i = COUNTOF(input_pin_tab) - 1; i >= 0; i--)
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{
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if (input_pin_tab[i].mask & mask)
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{
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nrf_gpio_pin_clear(input_pin_tab[i].pin);
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ohms += input_pin_tab[i].val;
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}
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else
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{
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nrf_gpio_pin_set(input_pin_tab[i].pin);
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}
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}
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return ohms;
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}
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static void set_resistor_to_default(void)
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{
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const uint32_t resistor_to_default = 0b000000000000;
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_load_set(resistor_to_default);
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}
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static float _load_set_by_ohms(float ohms)
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{
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// TODO...
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return ohms;
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}
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static void _sample_measure_out_is_low(void)
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{
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nrf_gpio_pin_set(ANODE_PIN);
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nrf_gpio_pin_clear(CATHODE_PIN);
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nrf_gpio_pin_clear(SAMPLE_R_PIN);
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nrf_gpio_pin_clear(SAMPLE_V_PIN);
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nrf_delay_us(10);
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nrf_gpio_pin_toggle(ANODE_PIN);
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nrf_gpio_pin_toggle(CATHODE_PIN);
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nrf_delay_us(3);
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nrf_gpio_pin_toggle(SAMPLE_R_PIN);
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nrf_gpio_pin_toggle(SAMPLE_V_PIN);
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nrf_delay_us(5);
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nrf_gpio_pin_toggle(SAMPLE_R_PIN);
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nrf_gpio_pin_toggle(SAMPLE_V_PIN);
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nrf_gpio_pin_toggle(CATHODE_PIN);
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nrf_gpio_pin_toggle(ANODE_PIN);
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}
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static void _sample_measure_out_is_high(void)
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{
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nrf_gpio_pin_clear(ANODE_PIN);
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nrf_gpio_pin_set(CATHODE_PIN);
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nrf_gpio_pin_clear(SAMPLE_R_PIN);
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nrf_gpio_pin_clear(SAMPLE_V_PIN);
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nrf_delay_us(10);
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nrf_gpio_pin_toggle(ANODE_PIN);
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nrf_gpio_pin_toggle(CATHODE_PIN);
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nrf_delay_us(3);
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nrf_gpio_pin_toggle(SAMPLE_R_PIN);
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nrf_gpio_pin_toggle(SAMPLE_V_PIN);
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nrf_delay_us(5);
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nrf_gpio_pin_toggle(SAMPLE_R_PIN);
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nrf_gpio_pin_toggle(SAMPLE_V_PIN);
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nrf_gpio_pin_toggle(CATHODE_PIN);
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nrf_gpio_pin_toggle(ANODE_PIN);
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}
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void pel_relays_set(uint32_t measure_out)
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{
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if (measure_out)
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{
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nrf_gpio_pin_set(RELAY1_PIN);
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nrf_gpio_pin_clear(RELAY2_PIN);
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}
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else
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{
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nrf_gpio_pin_clear(RELAY1_PIN);
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nrf_gpio_pin_set(RELAY2_PIN);
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}
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/* delay 30ms */
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vTaskDelay(pdMS_TO_TICKS(30));
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}
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pel_output_t pel_smaple_and_convt_all(uint32_t measure_out, uint32_t load_mask)
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{
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uint32_t ch_list[] = {
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[OUTPUT_R1_IDX] = OUTPUT_R1_CHANNEL,
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[OUTPUT_R2_IDX] = OUTPUT_R2_CHANNEL,
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[OUTPUT_VO_IDX] = OUTPUT_VO_CHANNEL,
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[OUTPUT_VC_IDX] = OUTPUT_VC_CHANNEL,
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[OUTPUT_VE_IDX] = OUTPUT_VE_CHANNEL
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};
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int32_t results[COUNTOF(ch_list)];
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float f_results[COUNTOF(ch_list)];
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/* config E-load */
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set_resistor_to_default();
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_load_set(load_mask);
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/* send a pulse to sample and then read ADC channels */
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if (measure_out)
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{
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adc_read_mutiple_channels_ex(ch_list, results, COUNTOF(ch_list), _sample_measure_out_is_high);
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adc_read_multiple_milivolt_ex(ch_list, f_results, COUNTOF(ch_list), _sample_measure_out_is_high);
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}
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else
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{
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adc_read_mutiple_channels_ex(ch_list, results, COUNTOF(ch_list), _sample_measure_out_is_low);
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adc_read_multiple_milivolt_ex(ch_list, f_results, COUNTOF(ch_list), _sample_measure_out_is_low);
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}
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/* copy results */
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output_data.output_r1 = results[OUTPUT_R1_IDX];
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output_data.output_r2 = results[OUTPUT_R2_IDX];
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output_data.output_vo = results[OUTPUT_VO_IDX];
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output_data.output_vc = results[OUTPUT_VC_IDX];
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output_data.output_ve = results[OUTPUT_VE_IDX];
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{
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char str[128];
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snprintf(str, sizeof(str), "%s: 0x%04lX, %.3fmV", "output_r1", output_data.output_r1, f_results[OUTPUT_R1_IDX]);
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NRF_LOG_INFO("%s", str);
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snprintf(str, sizeof(str), "%s: 0x%04lX, %.3fmV", "output_r2", output_data.output_r2, f_results[OUTPUT_R2_IDX]);
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NRF_LOG_INFO("%s", str);
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snprintf(str, sizeof(str), "%s: 0x%04lX, %.3fmV", "output_vo", output_data.output_vo, f_results[OUTPUT_VO_IDX]);
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NRF_LOG_INFO("%s", str);
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snprintf(str, sizeof(str), "%s: 0x%04lX, %.3fmV", "output_vc", output_data.output_vc, f_results[OUTPUT_VC_IDX]);
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NRF_LOG_INFO("%s", str);
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snprintf(str, sizeof(str), "%s: 0x%04lX, %.3fmV", "output_ve", output_data.output_ve, f_results[OUTPUT_VE_IDX]);
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NRF_LOG_INFO("%s", str);
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}
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return output_data;
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}
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#define VERSION_DATE_YEAR 24
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#define VERSION_DATE_MONTH 7
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#define VERSION_DATE_DAY 30
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#define VERSION_DATE_HOUR 13
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#define VERSION_DATE_MINUTE 40
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static void cis_version(uint8_t *ins, uint16_t size)
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{
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NRF_LOG_INFO("%s", __FUNCTION__);
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uint8_t cis_ver[] = {
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CIS_VERSION,
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VERSION_DATE_YEAR,
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VERSION_DATE_MONTH,
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VERSION_DATE_DAY,
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VERSION_DATE_HOUR,
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VERSION_DATE_MINUTE,
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};
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extern ret_code_t le_data_upadate(uint8_t * p_value, uint16_t len);
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le_data_upadate((void *)cis_ver, sizeof(cis_ver));
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}
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static void vis_rst(uint8_t *ins, uint16_t size)
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{
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NRF_LOG_INFO("%s", __FUNCTION__);
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}
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void test_gpio_task(void *pArg)
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{
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const uint32_t pel_pins[] = {
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INPUT_1_PIN,
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INPUT_2_PIN,
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INPUT_3_PIN,
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INPUT_4_PIN,
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INPUT_5_PIN,
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INPUT_6_PIN,
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INPUT_7_PIN,
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INPUT_8_PIN,
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INPUT_9_PIN,
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INPUT_10_PIN,
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INPUT_11_PIN,
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INPUT_12_PIN,
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ANODE_PIN,
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CATHODE_PIN,
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SAMPLE_R_PIN,
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SAMPLE_V_PIN,
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RELAY1_PIN,
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RELAY2_PIN
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};
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for (;;)
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{
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NRF_LOG_INFO("[test] all output pin set low");
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for (int i = 0; i < COUNTOF(pel_pins); i++)
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{
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nrf_gpio_pin_clear(pel_pins[i]);
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}
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vTaskDelay(1000);
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NRF_LOG_INFO("[test] all output pin set high");
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for (int i = 0; i < COUNTOF(pel_pins); i++)
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{
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nrf_gpio_pin_set(pel_pins[i]);
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}
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vTaskDelay(1000);
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NRF_LOG_INFO("[test] alternating high and low signals on all output pins");
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for (int i = 0; i < COUNTOF(pel_pins); i++)
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{
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nrf_gpio_pin_clear(pel_pins[i]);
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}
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vTaskDelay(1000);
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for (int i = 0; i < COUNTOF(pel_pins); i++)
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{
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nrf_gpio_pin_set(pel_pins[i]);
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vTaskDelay(100);
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nrf_gpio_pin_clear(pel_pins[i]);
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}
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vTaskDelay(1000);
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}
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}
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void set_a_specific_resistor_combination(uint16_t resistor_combination)
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{
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typedef struct
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{
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uint16_t val;
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uint32_t mask;
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} resistor_combination_t;
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const resistor_combination_t resis_combination_tab[] = {
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{ 1, 0b111},
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{ 2, 0b011},
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{ 3, 0b101},
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{ 4, 0b001},
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{ 5, 0b111 << 1},
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{ 6, 0b011 << 1},
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{ 7, 0b101 << 1},
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{ 8, 0b001 << 1},
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{ 9, 0b111 << 2},
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{10, 0b011 << 2},
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{11, 0b101 << 2},
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{12, 0b001 << 2},
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{13, 0b111 << 3},
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{14, 0b011 << 3},
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{15, 0b101 << 3},
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{16, 0b001 << 3},
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{17, 0b111 << 4},
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{18, 0b011 << 4},
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{19, 0b101 << 4},
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{20, 0b001 << 4},
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{21, 0b111 << 5},
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{22, 0b011 << 5},
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{23, 0b101 << 5},
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{24, 0b001 << 5},
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{25, 0b111 << 6},
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{26, 0b011 << 6},
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{27, 0b101 << 6},
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{28, 0b001 << 6},
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{29, 0b111 << 7},
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{30, 0b011 << 7},
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{31, 0b101 << 7},
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{32, 0b001 << 7},
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{33, 0b111 << 8},
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{34, 0b011 << 8},
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{35, 0b101 << 8},
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{36, 0b001 << 8},
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{37, 0b111 << 9},
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{38, 0b011 << 9},
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{39, 0b101 << 9},
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{40, 0b001 << 9},
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{41, 0b11 << 10},
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{42, 0b01 << 10},
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{43, 0b1 << 11},
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};
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for (int32_t i = 0; i < COUNTOF(resis_combination_tab); i++)
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{
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if (resis_combination_tab[i].val == resistor_combination)
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{
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NRF_LOG_INFO("No.%d resistor_combination: 0x%03X(FW) ", resis_combination_tab[i].val, resis_combination_tab[i].mask);
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NRF_LOG_INFO("Input | 1 | 2 | 3 | 4 | 5 | 6 |");
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NRF_LOG_INFO(" | %d | %d | %d | %d | %d | %d |",
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(resis_combination_tab[i].mask & 1 << 0),
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(resis_combination_tab[i].mask & 1 << 1) >> 1,
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(resis_combination_tab[i].mask & 1 << 2) >> 2,
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(resis_combination_tab[i].mask & 1 << 3) >> 3,
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(resis_combination_tab[i].mask & 1 << 4) >> 4,
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(resis_combination_tab[i].mask & 1 << 5) >> 5);
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NRF_LOG_INFO("Input | 7 | 8 | 9 | 10 | 11 | 12 |");
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NRF_LOG_INFO(" | %d | %d | %d | %d | %d | %d |",
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(resis_combination_tab[i].mask & 1 << 6) >> 6,
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(resis_combination_tab[i].mask & 1 << 7) >> 7,
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(resis_combination_tab[i].mask & 1 << 8) >> 8,
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(resis_combination_tab[i].mask & 1 << 9) >> 9,
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(resis_combination_tab[i].mask & 1 << 10) >> 10,
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(resis_combination_tab[i].mask & 1 << 11) >> 11);
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set_resistor_to_default();
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_load_set(resis_combination_tab[i].mask);
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}
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}
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}
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void pel_select_resistor_combinations_mode(uint8_t *ins)
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{
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#define SET_A_SPECIFIC_RESISTOR_COMBINATION 0x00
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#define SET_ALL_RESISTORS_AT_ONCE 0x01
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uint16_t set_resistor_type = (ins[4] & 0xF0) >> 4;
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uint16_t val = ((ins[4] & 0x0F) << 8) | ins[5];
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if (set_resistor_type == 0)
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{
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set_a_specific_resistor_combination(val);
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}
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else if (set_resistor_type == 1)
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{
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typedef union
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{
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struct
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{
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uint32_t input1 : 1;
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uint32_t input2 : 1;
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uint32_t input3 : 1;
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uint32_t input4 : 1;
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uint32_t input5 : 1;
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uint32_t input6 : 1;
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uint32_t input7 : 1;
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uint32_t input8 : 1;
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uint32_t input9 : 1;
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uint32_t input10 : 1;
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uint32_t input11 : 1;
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uint32_t input12 : 1;
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};
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uint32_t val;
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} resis_t;
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resis_t resis;
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resis.input1 = (val & 0b0000100000000000) >> 11;
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resis.input2 = (val & 0b0000010000000000) >> 10;
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resis.input3 = (val & 0b0000001000000000) >> 9;
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resis.input4 = (val & 0b0000000100000000) >> 8;
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resis.input5 = (val & 0b0000000010000000) >> 7;
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resis.input6 = (val & 0b0000000001000000) >> 6;
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resis.input7 = (val & 0b0000000000100000) >> 5;
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resis.input8 = (val & 0b0000000000010000) >> 4;
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resis.input9 = (val & 0b0000000000001000) >> 3;
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resis.input10 = (val & 0b0000000000000100) >> 2;
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resis.input11 = (val & 0b0000000000000010) >> 1;
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resis.input12 = (val & 0b0000000000000001) >> 0;
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NRF_LOG_INFO("Set_all_resistors_at_once: 0x%03X(FW) ", resis.val);
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NRF_LOG_INFO("Input | 1 | 2 | 3 | 4 | 5 | 6 |");
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NRF_LOG_INFO(" | %d | %d | %d | %d | %d | %d |",
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(resis.val & 1 << 0),
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(resis.val & 1 << 1) >> 1,
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(resis.val & 1 << 2) >> 2,
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(resis.val & 1 << 3) >> 3,
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(resis.val & 1 << 4) >> 4,
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(resis.val & 1 << 5) >> 5);
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NRF_LOG_INFO("Input | 7 | 8 | 9 | 10 | 11 | 12 |");
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NRF_LOG_INFO(" | %d | %d | %d | %d | %d | %d |",
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(resis.val & 1 << 6) >> 6,
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(resis.val & 1 << 7) >> 7,
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(resis.val & 1 << 8) >> 8,
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(resis.val & 1 << 9) >> 9,
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(resis.val & 1 << 10) >> 10,
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(resis.val & 1 << 11) >> 11);
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set_resistor_to_default();
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_load_set(resis.val);
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}
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else
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{
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printf("No this cmd...");
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}
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}
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#define MAGIC_NUM 0xFF00
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static pel_output_t dev_mode_pel_output;
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static void dev_mode(uint8_t *ins, uint16_t size)
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{
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NRF_LOG_INFO("%s", __FUNCTION__);
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struct __PACKED
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{
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uint8_t id : 4;
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uint8_t : 4;
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uint16_t magic : 16;
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uint8_t opcode;
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uint8_t param[];
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} *p_ins = (void *)ins;
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if (p_ins->magic != MAGIC_NUM)
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{
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return;
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}
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switch (p_ins->opcode)
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{
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case 0x60: {
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struct
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{
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uint8_t status;
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uint16_t mask;
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} __PACKED *p_param = (void *)p_ins->param;
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pel_relays_set(p_param->status);
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dev_mode_pel_output = pel_smaple_and_convt_all(p_param->status, __REVSH(p_param->mask));
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break;
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}
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case 0x61: {
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struct
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{
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uint8_t channel;
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} __PACKED *p_param = (void *)p_ins->param;
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if (p_param->channel == 0x01)
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{
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extern ret_code_t le_data_upadate(uint8_t * p_value, uint16_t len);
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le_data_upadate((void *)&dev_mode_pel_output.output_r1, sizeof(dev_mode_pel_output.output_r1));
|
|
}
|
|
else if (p_param->channel == 0x02)
|
|
{
|
|
extern ret_code_t le_data_upadate(uint8_t * p_value, uint16_t len);
|
|
le_data_upadate((void *)&dev_mode_pel_output.output_r2, sizeof(dev_mode_pel_output.output_r2));
|
|
}
|
|
else if (p_param->channel == 0x03)
|
|
{
|
|
extern ret_code_t le_data_upadate(uint8_t * p_value, uint16_t len);
|
|
le_data_upadate((void *)&dev_mode_pel_output.output_vo, sizeof(dev_mode_pel_output.output_vo));
|
|
}
|
|
else if (p_param->channel == 0x04)
|
|
{
|
|
extern ret_code_t le_data_upadate(uint8_t * p_value, uint16_t len);
|
|
le_data_upadate((void *)&dev_mode_pel_output.output_vc, sizeof(dev_mode_pel_output.output_vc));
|
|
}
|
|
else if (p_param->channel == 0x05)
|
|
{
|
|
extern ret_code_t le_data_upadate(uint8_t * p_value, uint16_t len);
|
|
le_data_upadate((void *)&dev_mode_pel_output.output_ve, sizeof(dev_mode_pel_output.output_ve));
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0x62: {
|
|
pel_select_resistor_combinations_mode(ins);
|
|
break;
|
|
}
|
|
|
|
case 0xF0: {
|
|
pel10_io_init();
|
|
break;
|
|
}
|
|
|
|
case 0xF1: {
|
|
struct
|
|
{
|
|
uint8_t status;
|
|
} __PACKED *p_param = (void *)p_ins->param;
|
|
|
|
if (p_param->status == 0x01)
|
|
{
|
|
if (test_gpio_task_Handle == NULL)
|
|
{
|
|
NRF_LOG_INFO("[test] start test_gpio_task task");
|
|
xTaskCreate(test_gpio_task, "test_gpio_task", 1024, NULL, 4, &test_gpio_task_Handle);
|
|
}
|
|
}
|
|
else if (p_param->status == 0x00)
|
|
{
|
|
if (test_gpio_task_Handle != NULL)
|
|
{
|
|
NRF_LOG_INFO("[test] delete test_gpio_task task");
|
|
vTaskDelete(test_gpio_task_Handle);
|
|
test_gpio_task_Handle = NULL;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0xF2: {
|
|
struct
|
|
{
|
|
uint8_t input_n;
|
|
uint8_t status;
|
|
} __PACKED *p_param = (void *)p_ins->param;
|
|
|
|
uint32_t high_low = p_param->status;
|
|
|
|
switch (p_param->input_n)
|
|
{
|
|
case 0x01:
|
|
nrf_gpio_pin_write(INPUT_1_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_1_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x02:
|
|
nrf_gpio_pin_write(INPUT_2_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_2_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x03:
|
|
nrf_gpio_pin_write(INPUT_3_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_3_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x04:
|
|
nrf_gpio_pin_write(INPUT_4_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_4_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x05:
|
|
nrf_gpio_pin_write(INPUT_5_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_5_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x06:
|
|
nrf_gpio_pin_write(INPUT_6_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_6_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x07:
|
|
nrf_gpio_pin_write(INPUT_7_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_7_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x08:
|
|
nrf_gpio_pin_write(INPUT_8_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_8_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x09:
|
|
nrf_gpio_pin_write(INPUT_9_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_9_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x0A:
|
|
nrf_gpio_pin_write(INPUT_10_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_10_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x0B:
|
|
nrf_gpio_pin_write(INPUT_11_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_11_PIN = %d", high_low);
|
|
break;
|
|
|
|
case 0x0C:
|
|
nrf_gpio_pin_write(INPUT_12_PIN, high_low);
|
|
NRF_LOG_INFO("set INPUT_12_PIN = %d", high_low);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
default: {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
const elite_instance_t pel_elite_instance = {
|
|
.cis_func = {
|
|
[CIS_VERSION] = cis_version,
|
|
},
|
|
.vis_func = {
|
|
[VIS_RST] = vis_rst,
|
|
},
|
|
.ris_func = {
|
|
[DEV_MODE] = dev_mode,
|
|
}
|
|
};
|
|
|
|
const elite_instance_t *pel_init(void)
|
|
{
|
|
return &pel_elite_instance;
|
|
}
|
|
|
|
#endif
|