From f3a746a6f4a0914dcc842eebdf87b3782f2ffbcc Mon Sep 17 00:00:00 2001 From: chain40 Date: Wed, 5 Mar 2025 21:31:12 +0800 Subject: [PATCH] update: optimize pel procedure --- pel.c | 50 +++++++++++++++++++++++++++----------------------- pel20_io.c | 41 +++++++++++++++++------------------------ pel20_io.h | 3 ++- 3 files changed, 46 insertions(+), 48 deletions(-) diff --git a/pel.c b/pel.c index db14d1a..d001486 100644 --- a/pel.c +++ b/pel.c @@ -196,6 +196,7 @@ typedef struct static uint8_t global_memoryboard_id = 0xFF; static SemaphoreHandle_t auto_scan_cplt_sem = NULL; +static SemaphoreHandle_t adc_convt_cplt_sem = NULL; static MessageBufferHandle_t pel_scan_msqQ = NULL; static void vis_rst(uint8_t *ins, uint16_t size) @@ -375,7 +376,7 @@ static void dev_mode_input_resistor(uint8_t *ins) } } -static void start_adc_pulse(uint32_t pusle_cnt) +static void start_adc_pulse(uint32_t pusle_cnt, void (*convt_done_cb)(void)) { pel_config_t pel_cfg = { .anode_pin = ANODE_PIN, @@ -391,10 +392,11 @@ static void start_adc_pulse(uint32_t pusle_cnt) 2, 0, }, - .pulse_cnt = pusle_cnt, - .gain = NRF_SAADC_GAIN1_6, - .smaple_time = NRF_SAADC_ACQTIME_10US, - .adc_timing_shift = 0, + .pulse_cnt = pusle_cnt, + .gain = NRF_SAADC_GAIN1_6, + .smaple_time = NRF_SAADC_ACQTIME_10US, + .adc_timing_shift = 0, + .convt_new_arrival_cb = convt_done_cb, }; pel_pulse_gen_init(pel_cfg); @@ -406,6 +408,13 @@ static void stop_adc_pulse(void) pel_pulse_gen_stop(); } +static void adc_event_end_cb(void) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xSemaphoreGiveFromISR(adc_convt_cplt_sem, &xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + static void pel_pulse_start(void *p_arg) { NRF_LOG_INFO("%s()", __FUNCTION__); @@ -430,7 +439,7 @@ static void pel_pulse_start(void *p_arg) } nrf_gpio_pin_set(TP2_PIN); // For testing - start_adc_pulse(0xFFFFFFFF); + start_adc_pulse(0xFFFFFFFF, adc_event_end_cb); nrf_gpio_pin_clear(TP2_PIN); // For testing } @@ -451,24 +460,16 @@ static void pel_pulse_notify(void *p_arg) static pel20_notify_packet1_t packet_buf = { 0 }; - extern bool pel_adc_convt_new_arrival(void); - - TickType_t t0 = xTaskGetTickCount(); + xSemaphoreTake(adc_convt_cplt_sem, 0); for (uint32_t i = 0; i < p_setting->drop; i++) { - pel_adc_convt_new_arrival(); - do { - vTaskDelay(pdMS_TO_TICKS(2)); - } while (pel_adc_convt_new_arrival() == false); + xSemaphoreTake(adc_convt_cplt_sem, pdMS_TO_TICKS(1000)); } for (uint32_t i = 0; i < p_setting->count; i++) { - pel_adc_convt_new_arrival(); - do { - vTaskDelay(pdMS_TO_TICKS(1)); - } while (pel_adc_convt_new_arrival() == false); + xSemaphoreTake(adc_convt_cplt_sem, pdMS_TO_TICKS(1000)); nrf_gpio_pin_set(TP2_PIN); pel_scan_mode_notify(&packet_buf, sizeof(packet_buf)); nrf_gpio_pin_clear(TP2_PIN); @@ -570,9 +571,9 @@ static void manual_scan_mode(uint8_t *ins, uint16_t size) pel_scan_msg.resistor_setting.value = u8_to_u32(p_ins->param[1], p_ins->param[2], p_ins->param[3], p_ins->param[4]); ASSERT(xMessageBufferSend(pel_scan_msqQ, &pel_scan_msg, sizeof(pel_scan_msg.opcode) + sizeof(pel_scan_msg.resistor_setting), pdMS_TO_TICKS(500))); - pel_scan_msg.opcode = PEL_NOTIFY; - pel_scan_msg.notify_setting.count = u8_to_u16(p_ins->param[5], p_ins->param[6]); - pel_scan_msg.notify_setting.drop = 0; + pel_scan_msg.opcode = PEL_NOTIFY; + pel_scan_msg.notify_setting.count = u8_to_u16(p_ins->param[5], p_ins->param[6]); + pel_scan_msg.notify_setting.drop = 0; ASSERT(xMessageBufferSend(pel_scan_msqQ, &pel_scan_msg, sizeof(pel_scan_msg.opcode) + sizeof(pel_scan_msg.notify_setting), pdMS_TO_TICKS(500))); break; @@ -585,9 +586,9 @@ static void manual_scan_mode(uint8_t *ins, uint16_t size) pel_scan_msg.resistor_setting.value = u8_to_u32(p_ins->param[1], p_ins->param[2], p_ins->param[3], p_ins->param[4]); ASSERT(xMessageBufferSend(pel_scan_msqQ, &pel_scan_msg, sizeof(pel_scan_msg.opcode) + sizeof(pel_scan_msg.resistor_setting), pdMS_TO_TICKS(500))); - pel_scan_msg.opcode = PEL_NOTIFY; - pel_scan_msg.notify_setting.count = u8_to_u16(p_ins->param[5], p_ins->param[6]); - pel_scan_msg.notify_setting.drop = 0; + pel_scan_msg.opcode = PEL_NOTIFY; + pel_scan_msg.notify_setting.count = u8_to_u16(p_ins->param[5], p_ins->param[6]); + pel_scan_msg.notify_setting.drop = 0; ASSERT(xMessageBufferSend(pel_scan_msqQ, &pel_scan_msg, sizeof(pel_scan_msg.opcode) + sizeof(pel_scan_msg.notify_setting), pdMS_TO_TICKS(500))); break; @@ -729,6 +730,9 @@ const elite_instance_t *pel_init(void) auto_scan_cplt_sem = xSemaphoreCreateBinary(); ASSERT(auto_scan_cplt_sem); + adc_convt_cplt_sem = xSemaphoreCreateBinary(); + ASSERT(adc_convt_cplt_sem); + pel_scan_msqQ = xMessageBufferCreate(1024); ASSERT(pel_scan_msqQ); diff --git a/pel20_io.c b/pel20_io.c index 717f04c..3476ba0 100644 --- a/pel20_io.c +++ b/pel20_io.c @@ -158,7 +158,7 @@ static void pel_saadc_init(pel_adc_t *p_adc) } } /* enable ssadc */ - NRF_SAADC->INTENSET = NRF_SAADC_INT_STARTED | NRF_SAADC_INT_RESULTDONE; + NRF_SAADC->INTENSET = NRF_SAADC_INT_STARTED | NRF_SAADC_INT_END; NRF_SAADC->ENABLE = 1; NRF_SAADC->RESULT.PTR = (uint32_t)p_adc->results; NRF_SAADC->RESULT.MAXCNT = COUNTOF(p_adc->results); @@ -191,13 +191,16 @@ void SAADC_IRQHandler(void) return; } - if (NRF_SAADC->EVENTS_RESULTDONE) + if (NRF_SAADC->EVENTS_END) { - NRF_SAADC->EVENTS_RESULTDONE = 0; - NRF_SAADC->RESULT.PTR = (uint32_t)pel_hw.adc.results; - NRF_SAADC->RESULT.MAXCNT = COUNTOF(pel_hw.adc.results); - pel_hw.pulse_is_running = 0; - pel_hw.convt_new_arrival = 1; + NRF_SAADC->EVENTS_END = 0; + NRF_SAADC->RESULT.PTR = (uint32_t)pel_hw.adc.results; + NRF_SAADC->RESULT.MAXCNT = COUNTOF(pel_hw.adc.results); + pel_hw.pulse_is_running = 0; + if (pel_hw.adc.convt_new_arrival_cb) + { + pel_hw.adc.convt_new_arrival_cb(); + } } } @@ -211,9 +214,10 @@ void pel_pulse_gen_init(pel_config_t cfg) sd_nvic_DisableIRQ(SAADC_IRQn); sd_nvic_ClearPendingIRQ(SAADC_IRQn); - pel_hw.pulse_cnt = cfg.pulse_cnt; - pel_hw.adc.gain = cfg.gain; - pel_hw.adc.smaple_time = cfg.smaple_time; + pel_hw.pulse_cnt = cfg.pulse_cnt; + pel_hw.adc.gain = cfg.gain; + pel_hw.adc.smaple_time = cfg.smaple_time; + pel_hw.adc.convt_new_arrival_cb = cfg.convt_new_arrival_cb; pel_saadc_init(&pel_hw.adc); @@ -291,12 +295,12 @@ void pel_pulse_gen_init(pel_config_t cfg) pel_hw.pulse_tmr->PRESCALER = NRF_TIMER_FREQ_16MHz; pel_hw.pulse_tmr->MODE = NRF_TIMER_MODE_TIMER; pel_hw.pulse_tmr->BITMODE = NRF_TIMER_BIT_WIDTH_32; - pel_hw.pulse_tmr->CC[0] = 1; + pel_hw.pulse_tmr->CC[0] = cfg.point_us[0] * 16; pel_hw.pulse_tmr->CC[1] = pel_hw.pulse_tmr->CC[0] + cfg.point_us[1] * 16; pel_hw.pulse_tmr->CC[2] = pel_hw.pulse_tmr->CC[1] + cfg.point_us[2] * 16; pel_hw.pulse_tmr->CC[3] = pel_hw.pulse_tmr->CC[2] + cfg.point_us[3] * 16; pel_hw.pulse_tmr->CC[4] = pel_hw.pulse_tmr->CC[3] + cfg.point_us[4] * 16 + cfg.adc_timing_shift; - pel_hw.pulse_tmr->CC[5] = pel_hw.pulse_tmr->CC[4] + cfg.point_us[0] * 16; + pel_hw.pulse_tmr->CC[5] = pel_hw.pulse_tmr->CC[4]; pel_hw.pulse_tmr->SHORTS = NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK; pel_hw.pulse_tmr->INTENSET = NRF_TIMER_INT_COMPARE0_MASK; @@ -309,7 +313,6 @@ void pel_pulse_gen_init(pel_config_t cfg) void pel_pulse_gen_start(void) { - pel_hw.convt_new_arrival = 0; pel_hw.pulse_tmr->TASKS_START = 1; } @@ -318,17 +321,7 @@ void pel_pulse_gen_stop(void) pel_hw.pulse_cnt = 0; do { } while (pel_hw.pulse_is_running == 1); -} - -bool pel_adc_convt_new_arrival(void) -{ - bool ret = false; - if (pel_hw.convt_new_arrival) - { - pel_hw.convt_new_arrival = 0; - ret = true; - } - return ret; + pel_hw.adc.convt_new_arrival_cb = NULL; } #if (DEF_ELITE_DEMO_W_SOFTDEVICE == 1) || (DEF_ELITE_DEMO_WO_SOFTDEVICE == 1) diff --git a/pel20_io.h b/pel20_io.h index b5b16d1..73311ea 100644 --- a/pel20_io.h +++ b/pel20_io.h @@ -76,6 +76,7 @@ extern "C" nrf_saadc_gain_t gain; nrf_saadc_acqtime_t smaple_time; int32_t adc_timing_shift; + void (*convt_new_arrival_cb)(void); } pel_config_t; typedef struct @@ -85,6 +86,7 @@ extern "C" uint32_t channels[5]; int16_t results[5]; float results_f[5]; + void (*convt_new_arrival_cb)(void); } pel_adc_t; typedef struct @@ -94,7 +96,6 @@ extern "C" uint32_t pulse_cnt; uint32_t pulse_is_running; pel_adc_t adc; - uint32_t convt_new_arrival; } pel_hw_t; extern pel_hw_t pel_hw;