diff --git a/app_config.h b/app_config.h
index e40eebd..ccb26bc 100644
--- a/app_config.h
+++ b/app_config.h
@@ -105,6 +105,7 @@ extern "C"
#define DEF_ELITE_DEV 0x00000000
#define DEF_ELITE_EDC_20 0x00020109
#define DEF_PULSE_E_LOAD_10 0x00070000
+#define DEF_CURRENT_PULSE_GANERATOR_10 0x00080000
#define DEF_ELITE_MODEL DEF_ELITE_DEV
#if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
@@ -194,6 +195,35 @@ extern "C"
#define DEF_RTT_JSCOP_ENABLED 0
+#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+#define ELITE_DEVICE_NAME "Elite-CPG"
+#define MAJOR_PRODUCT_NUMBER 0
+#define MINOR_PRODUCT_NUMBER 2
+#define MAJOR_VERSION_NUMBER 1
+#define MINOR_VERSION_NUMBER 9
+
+#define DEF_LED_COUNT 0
+#define DEF_LED_DRV_ENABLED 0
+#define DEF_APA102_2020_ENABLED 0
+
+#define DEF_ADC_DRV_ENABLED 0
+#define DEF_ADS8691_ENABLED 0
+#define DEF_BULTIN_ADC_ENABED 0
+
+#define DEF_DAC_DRV_ENABLED 0
+#define DEF_MAX5136_ENABLED 0
+
+#define DEF_SW_DRV_ENABLED 0
+#define DEF_ADGS1412_ENABLED 0
+
+#define DEF_FS_ENABLED 0
+#define DEF_FS_RTT_DIR 0
+#define DEF_GD25D10C_ENABLED 0
+
+#define DEF_BTN_ENABLED 0
+
+#define DEF_RTT_JSCOP_ENABLED 0
+
#endif
#define BLE_ELITE_SRV_ENABLED 1
diff --git a/bmd380_peripheral.vcxproj b/bmd380_peripheral.vcxproj
index 7236b25..89bec64 100644
--- a/bmd380_peripheral.vcxproj
+++ b/bmd380_peripheral.vcxproj
@@ -197,6 +197,8 @@
+
+
@@ -373,6 +375,8 @@
+
+
diff --git a/cpg.c b/cpg.c
new file mode 100644
index 0000000..54a3ffb
--- /dev/null
+++ b/cpg.c
@@ -0,0 +1,59 @@
+#include "pel.h"
+#include "pel10_io.h"
+
+#include "elite_def.h"
+
+#include "nrf_delay.h"
+#include "nrf_gpio.h"
+#include "nrf_log.h"
+
+#if (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+
+#define VERSION_DATE_YEAR 24
+#define VERSION_DATE_MONTH 5
+#define VERSION_DATE_DAY 21
+#define VERSION_DATE_HOUR 18
+#define VERSION_DATE_MINUTE 39
+static void cis_version(uint8_t *ins, uint16_t size)
+{
+ NRF_LOG_INFO("%s", __FUNCTION__);
+ uint8_t cis_ver[] = {
+ CIS_VERSION,
+ VERSION_DATE_YEAR,
+ VERSION_DATE_MONTH,
+ VERSION_DATE_DAY,
+ VERSION_DATE_HOUR,
+ VERSION_DATE_MINUTE,
+ };
+ extern ret_code_t le_data_upadate(uint8_t * p_value, uint16_t len);
+ le_data_upadate((void *)cis_ver, sizeof(cis_ver));
+}
+
+static void vis_rst(uint8_t *ins, uint16_t size)
+{
+ NRF_LOG_INFO("%s", __FUNCTION__);
+}
+
+static void dev_mode(uint8_t *ins, uint16_t size)
+{
+ NRF_LOG_INFO("%s", __FUNCTION__);
+}
+
+const elite_instance_t cpg_elite_instance = {
+ .cis_func = {
+ [CIS_VERSION] = cis_version,
+ },
+ .vis_func = {
+ [VIS_RST] = vis_rst,
+ },
+ .ris_func = {
+ [DEV_MODE] = dev_mode,
+ }
+};
+
+const elite_instance_t *cpg_init(void)
+{
+ return &cpg_elite_instance;
+}
+
+#endif
diff --git a/cpg.h b/cpg.h
new file mode 100644
index 0000000..9530c5a
--- /dev/null
+++ b/cpg.h
@@ -0,0 +1,15 @@
+#ifndef __CPG_H__
+#define __CPG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+ const elite_instance_t *cpg_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __CPG_H__ */
diff --git a/cpg10_io.c b/cpg10_io.c
new file mode 100644
index 0000000..9817a62
--- /dev/null
+++ b/cpg10_io.c
@@ -0,0 +1,146 @@
+#include "elite_board.h"
+
+#include "nrf_spim.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+#if (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+
+void spim_xfer(uint32_t cs_pin,
+ nrf_spim_mode_t spi_mode,
+ uint8_t *p_tx_buffer,
+ uint16_t tx_buffer_length,
+ uint8_t *p_rx_buf,
+ uint16_t rx_buffer_length)
+{
+ __disable_irq();
+
+ NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
+
+ switch (spi_mode)
+ {
+ default:
+ case NRF_SPIM_MODE_0:
+ NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+ (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+ (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
+ break;
+
+ case NRF_SPIM_MODE_1:
+ NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+ (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+ (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
+ break;
+
+ case NRF_SPIM_MODE_2:
+ NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+ (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
+ (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
+ break;
+
+ case NRF_SPIM_MODE_3:
+ NRF_SPIM3->CONFIG = (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos) |
+ (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
+ (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
+ break;
+ }
+
+ NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+
+ NRF_SPIM3->TXD.MAXCNT = tx_buffer_length;
+ NRF_SPIM3->TXD.PTR = (uint32_t)p_tx_buffer;
+
+ NRF_SPIM3->RXD.MAXCNT = rx_buffer_length;
+ NRF_SPIM3->RXD.PTR = (uint32_t)p_rx_buf;
+
+ nrf_gpio_pin_clear(cs_pin);
+
+ NRF_SPIM3->EVENTS_END = 0;
+ NRF_SPIM3->TASKS_START = 1;
+ do {
+ } while (NRF_SPIM3->EVENTS_END == 0);
+
+ nrf_gpio_pin_set(cs_pin);
+
+ __enable_irq();
+}
+
+void cpg10_io_init(void)
+{
+ const uint32_t pel_pins_default_high[] = {
+ VA1H_PIN,
+ VA2H_PIN,
+ VA3H_PIN,
+ VA4H_PIN,
+ VB1H_PIN,
+ VB2H_PIN,
+ VB3H_PIN,
+ VB4H_PIN,
+ LED_R_PIN,
+ LED_G_PIN,
+ LED_B_PIN
+ };
+
+ const uint32_t pel_pins_default_low[] = {
+ ADPT0_S4_PIN,
+ ADPT0_S3_PIN,
+ ADPT0_S2_PIN,
+ ADPT0_S1_PIN,
+ ADPT_LE_PIN,
+ ADPT_CLR_PIN,
+ TW_SCKI_0_PIN,
+ TW_SCKI_1_PIN,
+ HV_EN_PIN,
+ ADPT1_S1_PIN,
+ VA1L_PIN,
+ VA2L_PIN,
+ VA3L_PIN,
+ VA4L_PIN,
+ VB1L_PIN,
+ VB2L_PIN,
+ VB3L_PIN,
+ VB4L_PIN,
+ ADPT1_S4_PIN,
+ ADPT1_S3_PIN,
+ ADPT1_S2_PIN
+ };
+
+ for (int i = 0; i < COUNTOF(pel_pins_default_high); i++)
+ {
+ nrf_gpio_pin_set(pel_pins_default_high[i]);
+ nrf_gpio_cfg_output(pel_pins_default_high[i]);
+ }
+
+ for (int i = 0; i < COUNTOF(pel_pins_default_low); i++)
+ {
+ nrf_gpio_pin_clear(pel_pins_default_low[i]);
+ nrf_gpio_cfg_output(pel_pins_default_low[i]);
+ }
+
+ nrf_gpio_cfg_input(AIN0_PIN, NRF_GPIO_PIN_NOPULL);
+ nrf_gpio_cfg_input(AIN1_PIN, NRF_GPIO_PIN_NOPULL);
+
+ // Config spi module
+ nrf_gpio_pin_set(CS_MEM_PIN);
+ nrf_gpio_cfg_output(CS_MEM_PIN);
+ nrf_gpio_pin_clear(SPIM_MOSI_PIN);
+ nrf_gpio_cfg_output(SPIM_MOSI_PIN);
+ nrf_gpio_pin_clear(SPIM_CLK_PIN);
+ nrf_gpio_cfg_output(SPIM_CLK_PIN);
+ nrf_gpio_cfg_input(SPIM_MISO_PIN, NRF_GPIO_PIN_NOPULL);
+
+ NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos;
+ NRF_SPIM3->ORC = 0x00000000;
+ NRF_SPIM3->FREQUENCY = SPIM_FREQUENCY_FREQUENCY_M32;
+ NRF_SPIM3->CSNPOL = SPIM_CSNPOL_CSNPOL_LOW;
+ NRF_SPIM3->IFTIMING.CSNDUR = 8;
+ NRF_SPIM3->PSEL.CSN = CS_MEM_PIN;
+ NRF_SPIM3->PSEL.SCK = SPIM_CLK_PIN;
+ NRF_SPIM3->PSEL.MOSI = SPIM_MOSI_PIN;
+ NRF_SPIM3->PSEL.MISO = SPIM_MISO_PIN;
+ NRF_SPIM3->ENABLE = SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos;
+}
+
+#endif
diff --git a/cpg10_io.h b/cpg10_io.h
new file mode 100644
index 0000000..a23bc25
--- /dev/null
+++ b/cpg10_io.h
@@ -0,0 +1,70 @@
+#ifndef __CPG10_IO_H__
+#define __CPG10_IO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "app_config.h"
+#include "elite_board.h"
+#include "nrf_gpio.h"
+#include "nrf_spim.h"
+
+#if (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+
+#define ADPT0_S4_PIN NRF_GPIO_PIN_MAP(0, 22)
+#define ADPT0_S3_PIN NRF_GPIO_PIN_MAP(0, 25)
+#define ADPT0_S2_PIN NRF_GPIO_PIN_MAP(0, 19)
+#define ADPT0_S1_PIN NRF_GPIO_PIN_MAP(0, 21)
+#define ADPT_LE_PIN NRF_GPIO_PIN_MAP(0, 17)
+#define ADPT_CLR_PIN NRF_GPIO_PIN_MAP(0, 20)
+#define TW_SCKI_0_PIN NRF_GPIO_PIN_MAP(0, 14)
+#define TW_SCKI_1_PIN NRF_GPIO_PIN_MAP(0, 13)
+#define HV_EN_PIN NRF_GPIO_PIN_MAP(0, 11)
+#define SPIM_CLK_PIN NRF_GPIO_PIN_MAP(0, 12)
+#define SPIM_MOSI_PIN NRF_GPIO_PIN_MAP(0, 7)
+#define SPIM_MISO_PIN NRF_GPIO_PIN_MAP(1, 9)
+#define ADPT1_S1_PIN NRF_GPIO_PIN_MAP(0, 6)
+#define CS_MEM_PIN NRF_GPIO_PIN_MAP(0, 27)
+#define VA1H_PIN NRF_GPIO_PIN_MAP(0, 26)
+#define VA1L_PIN NRF_GPIO_PIN_MAP(0, 4)
+#define VA2H_PIN NRF_GPIO_PIN_MAP(0, 1)
+#define VA2L_PIN NRF_GPIO_PIN_MAP(0, 29)
+#define VA3H_PIN NRF_GPIO_PIN_MAP(0, 0)
+#define VA3L_PIN NRF_GPIO_PIN_MAP(0, 31)
+#define VA4H_PIN NRF_GPIO_PIN_MAP(1, 15)
+#define VA4L_PIN NRF_GPIO_PIN_MAP(0, 2)
+#define AIN0_PIN NRF_GPIO_PIN_MAP(0, 30)
+#define AIN1_PIN NRF_GPIO_PIN_MAP(0, 28)
+#define VB1H_PIN NRF_GPIO_PIN_MAP(1, 12)
+#define VB1L_PIN NRF_GPIO_PIN_MAP(1, 14)
+#define VB2H_PIN NRF_GPIO_PIN_MAP(0, 3)
+#define VB2L_PIN NRF_GPIO_PIN_MAP(1, 13)
+#define VB3H_PIN NRF_GPIO_PIN_MAP(1, 3)
+#define VB3L_PIN NRF_GPIO_PIN_MAP(1, 10)
+#define VB4H_PIN NRF_GPIO_PIN_MAP(1, 6)
+#define VB4L_PIN NRF_GPIO_PIN_MAP(1, 11)
+#define LED_R_PIN NRF_GPIO_PIN_MAP(0, 10)
+#define LED_G_PIN NRF_GPIO_PIN_MAP(0, 9)
+#define LED_B_PIN NRF_GPIO_PIN_MAP(1, 2)
+#define ADPT1_S4_PIN NRF_GPIO_PIN_MAP(0, 24)
+#define ADPT1_S3_PIN NRF_GPIO_PIN_MAP(0, 23)
+#define ADPT1_S2_PIN NRF_GPIO_PIN_MAP(0, 16)
+
+ void spim_xfer(uint32_t cs_pin,
+ nrf_spim_mode_t spi_mode,
+ uint8_t *p_tx_buffer,
+ uint16_t tx_buffer_length,
+ uint8_t *p_rx_buf,
+ uint16_t rx_buffer_length);
+
+ void cpg10_io_init(void);
+
+#endif /* ! DEF_ELITE_MODEL */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __CPG10_IO_H__ */
diff --git a/elite.c b/elite.c
index b4b3ddf..3a8b049 100644
--- a/elite.c
+++ b/elite.c
@@ -6,6 +6,8 @@
#include "edc.h"
#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
#include "pel.h"
+#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+#include "cpg.h"
#else
#error "Unknown DEF_ELITE_MODEL"
#endif
@@ -105,6 +107,8 @@ void elite_init(void)
p_instance = edc.p_elite_instance;
#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
p_instance = pel_init();
+#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+ p_instance = cpg_init();
#else
#error "Unknown DEF_ELITE_MODEL"
#endif
diff --git a/elite_board.c b/elite_board.c
index 4b67795..bcac99c 100644
--- a/elite_board.c
+++ b/elite_board.c
@@ -6,6 +6,8 @@ void elite_board_init(void)
edc20_io_init();
#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
pel10_io_init();
+#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+ cpg10_io_init();
#endif
}
@@ -14,6 +16,7 @@ void elite_board_power_off(void)
#if (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
edc20_io_power_off();
#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
+#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
#endif
}
diff --git a/elite_board.h b/elite_board.h
index 64dcc52..9a32c5d 100644
--- a/elite_board.h
+++ b/elite_board.h
@@ -2,29 +2,32 @@
#define __ELITE_BOARD_H__
#ifdef __cplusplus
-extern "C" {
+extern "C"
+{
#endif
-#include "app_config.h"
#include "adc_drv.h"
+#include "app_config.h"
+#include "btn.h"
#include "dac_drv.h"
#include "fs.h"
#include "led_drv.h"
#include "sw_drv.h"
-#include "btn.h"
#if (DEF_ELITE_MODEL == DEF_ELITE_DEV)
#elif (DEF_ELITE_MODEL == DEF_ELITE_EDC_20)
#include "edc20_io.h"
#elif (DEF_ELITE_MODEL == DEF_PULSE_E_LOAD_10)
#include "pel10_io.h"
+#elif (DEF_ELITE_MODEL == DEF_CURRENT_PULSE_GANERATOR_10)
+#include "cpg10_io.h"
#else
#error "Not implemented xxx_io.h"
#endif
-void elite_board_init(void);
-void elite_board_power_off(void);
-void elite_drv_init(void);
+ void elite_board_init(void);
+ void elite_board_power_off(void);
+ void elite_drv_init(void);
#ifdef __cplusplus
}