From b561b86f3b14eaacc892ce83e01a6327f671e830 Mon Sep 17 00:00:00 2001 From: Roy_01 Date: Fri, 28 Mar 2025 09:45:14 +0800 Subject: [PATCH] feat: 1. add a 1ms delay before and after controlling the ADPT GPIO in max14802_write 2. dev mode commands (except those already available to users) start with 3xxxFFFF --- cpg.c | 429 ++++++++++++++++++++--------------------------------- cpg.h | 6 +- max14802.c | 3 + tw1508.c | 1 + 4 files changed, 170 insertions(+), 269 deletions(-) diff --git a/cpg.c b/cpg.c index 5450ea8..9facbd7 100644 --- a/cpg.c +++ b/cpg.c @@ -199,184 +199,105 @@ static void dev_mode_gpio(uint8_t *ins) } } -static void electrode_pulse_channel(uint16_t elec_ch_setting) -{ // ExN: electrode x negative // ExP: electrode x positive -#define ELECTRODE_ALL_HIGHZ 0x0000 -#define ELECTRODE_E1_IDLE 0x0001 -#define ELECTRODE_E2_IDLE 0x0002 -#define ELECTRODE_E3_IDLE 0x0003 -#define ELECTRODE_E4_IDLE 0x0004 -#define ELECTRODE_E1P_ENABLE 0x0005 -#define ELECTRODE_E1P_DISABLE 0x0006 -#define ELECTRODE_E1N_ENABLE 0x0007 -#define ELECTRODE_E1N_DISABLE 0x0008 -#define ELECTRODE_E2P_ENABLE 0x0009 -#define ELECTRODE_E2P_DISABLE 0x000A -#define ELECTRODE_E2N_ENABLE 0x000B -#define ELECTRODE_E2N_DISABLE 0x000C -#define ELECTRODE_E3P_ENABLE 0x000D -#define ELECTRODE_E3P_DISABLE 0x000E -#define ELECTRODE_E3N_ENABLE 0x000F -#define ELECTRODE_E3N_DISABLE 0x0010 -#define ELECTRODE_E4P_ENABLE 0x0011 -#define ELECTRODE_E4P_DISABLE 0x0012 -#define ELECTRODE_E4N_ENABLE 0x0013 -#define ELECTRODE_E4N_DISABLE 0x0014 +#define ELEC_CH_ALL_HIGHZ 0x0000 +#define ELEC_CH_E1_HIGHZ 0x0001 +#define ELEC_CH_E2_HIGHZ 0x0002 +#define ELEC_CH_E3_HIGHZ 0x0003 +#define ELEC_CH_E4_HIGHZ 0x0004 +#define ELEC_CH_ALL_IDLE 0x0005 +#define ELEC_CH_E1_IDLE 0x0006 +#define ELEC_CH_E2_IDLE 0x0007 +#define ELEC_CH_E3_IDLE 0x0008 +#define ELEC_CH_E4_IDLE 0x0009 +static void electrode_pulse_channel(uint16_t elec_ch_setting) +{ switch (elec_ch_setting) { - case ELECTRODE_ALL_HIGHZ: - NRF_LOG_INFO("ELECTRODE_ALL_HIGHZ()"); + case ELEC_CH_ALL_HIGHZ: { + NRF_LOG_INFO("ELEC_CH_ALL_HIGHZ()"); + electrode_pulse_channel(ELEC_CH_E1_HIGHZ); + electrode_pulse_channel(ELEC_CH_E2_HIGHZ); + electrode_pulse_channel(ELEC_CH_E3_HIGHZ); + electrode_pulse_channel(ELEC_CH_E4_HIGHZ); + break; + } + + case ELEC_CH_E1_HIGHZ: { + NRF_LOG_INFO("ELEC_CH_E1_HIGHZ()"); nrf_gpio_pin_write(VB1L_PIN, 0); nrf_gpio_pin_write(VB1H_PIN, 0); nrf_gpio_pin_write(VA1L_PIN, 0); nrf_gpio_pin_write(VA1H_PIN, 0); - + break; + } + case ELEC_CH_E2_HIGHZ: { + NRF_LOG_INFO("ELEC_CH_E2_HIGHZ()"); nrf_gpio_pin_write(VB2L_PIN, 0); nrf_gpio_pin_write(VB2H_PIN, 0); nrf_gpio_pin_write(VA2L_PIN, 0); nrf_gpio_pin_write(VA2H_PIN, 0); - + break; + } + case ELEC_CH_E3_HIGHZ: { + NRF_LOG_INFO("ELEC_CH_E3_HIGHZ()"); nrf_gpio_pin_write(VB3L_PIN, 0); nrf_gpio_pin_write(VB3H_PIN, 0); nrf_gpio_pin_write(VA3L_PIN, 0); nrf_gpio_pin_write(VA3H_PIN, 0); - + break; + } + case ELEC_CH_E4_HIGHZ: { + NRF_LOG_INFO("ELEC_CH_E4_HIGHZ()"); nrf_gpio_pin_write(VB4L_PIN, 0); nrf_gpio_pin_write(VB4H_PIN, 0); nrf_gpio_pin_write(VA4L_PIN, 0); nrf_gpio_pin_write(VA4H_PIN, 0); break; + } - case ELECTRODE_E1_IDLE: - NRF_LOG_INFO("ELECTRODE_E1_IDLE()"); + case ELEC_CH_ALL_IDLE: { + NRF_LOG_INFO("ELEC_CH_ALL_IDLE()"); + electrode_pulse_channel(ELEC_CH_E1_IDLE); + electrode_pulse_channel(ELEC_CH_E2_IDLE); + electrode_pulse_channel(ELEC_CH_E3_IDLE); + electrode_pulse_channel(ELEC_CH_E4_IDLE); + break; + } + + case ELEC_CH_E1_IDLE: + NRF_LOG_INFO("ELEC_CH_E1_IDLE()"); nrf_gpio_pin_write(VB1L_PIN, 0); nrf_gpio_pin_write(VB1H_PIN, 1); nrf_gpio_pin_write(VA1L_PIN, 0); nrf_gpio_pin_write(VA1H_PIN, 1); break; - case ELECTRODE_E2_IDLE: - NRF_LOG_INFO("ELECTRODE_E2_IDLE()"); + case ELEC_CH_E2_IDLE: + NRF_LOG_INFO("ELEC_CH_E2_IDLE()"); nrf_gpio_pin_write(VB2L_PIN, 0); nrf_gpio_pin_write(VB2H_PIN, 1); nrf_gpio_pin_write(VA2L_PIN, 0); nrf_gpio_pin_write(VA2H_PIN, 1); break; - case ELECTRODE_E3_IDLE: - NRF_LOG_INFO("ELECTRODE_E3_IDLE()"); + case ELEC_CH_E3_IDLE: + NRF_LOG_INFO("ELEC_CH_E3_IDLE()"); nrf_gpio_pin_write(VB3L_PIN, 0); nrf_gpio_pin_write(VB3H_PIN, 1); nrf_gpio_pin_write(VA3L_PIN, 0); nrf_gpio_pin_write(VA3H_PIN, 1); break; - case ELECTRODE_E4_IDLE: - NRF_LOG_INFO("ELECTRODE_E4_IDLE()"); + case ELEC_CH_E4_IDLE: + NRF_LOG_INFO("ELEC_CH_E4_IDLE()"); nrf_gpio_pin_write(VB4L_PIN, 0); nrf_gpio_pin_write(VB4H_PIN, 1); nrf_gpio_pin_write(VA4L_PIN, 0); nrf_gpio_pin_write(VA4H_PIN, 1); break; - - case ELECTRODE_E1P_ENABLE: - NRF_LOG_INFO("ELECTRODE_E1P_ENABLE()"); - nrf_gpio_pin_write(VB1H_PIN, 0); - nrf_gpio_pin_write(VB1L_PIN, 1); - break; - - case ELECTRODE_E1P_DISABLE: - NRF_LOG_INFO("ELECTRODE_E1P_DISABLE()"); - nrf_gpio_pin_write(VB1L_PIN, 0); - nrf_gpio_pin_write(VB1H_PIN, 1); - break; - - case ELECTRODE_E1N_ENABLE: - NRF_LOG_INFO("ELECTRODE_E1N_ENABLE()"); - nrf_gpio_pin_write(VA1H_PIN, 0); - nrf_gpio_pin_write(VA1L_PIN, 1); - break; - - case ELECTRODE_E1N_DISABLE: - NRF_LOG_INFO("ELECTRODE_E1N_DISABLE()"); - nrf_gpio_pin_write(VA1L_PIN, 0); - nrf_gpio_pin_write(VA1H_PIN, 1); - break; - - case ELECTRODE_E2P_ENABLE: - NRF_LOG_INFO("ELECTRODE_E2P_ENABLE()"); - nrf_gpio_pin_write(VB2H_PIN, 0); - nrf_gpio_pin_write(VB2L_PIN, 1); - break; - - case ELECTRODE_E2P_DISABLE: - NRF_LOG_INFO("ELECTRODE_E2P_DISABLE()"); - nrf_gpio_pin_write(VB2L_PIN, 0); - nrf_gpio_pin_write(VB2H_PIN, 1); - break; - - case ELECTRODE_E2N_ENABLE: - NRF_LOG_INFO("ELECTRODE_E2N_ENABLE()"); - nrf_gpio_pin_write(VA2H_PIN, 0); - nrf_gpio_pin_write(VA2L_PIN, 1); - break; - - case ELECTRODE_E2N_DISABLE: - NRF_LOG_INFO("ELECTRODE_E2N_DISABLE()"); - nrf_gpio_pin_write(VA2L_PIN, 0); - nrf_gpio_pin_write(VA2H_PIN, 1); - break; - - case ELECTRODE_E3P_ENABLE: - NRF_LOG_INFO("ELECTRODE_E3P_ENABLE()"); - nrf_gpio_pin_write(VB3H_PIN, 0); - nrf_gpio_pin_write(VB3L_PIN, 1); - break; - - case ELECTRODE_E3P_DISABLE: - NRF_LOG_INFO("ELECTRODE_E3P_DISABLE()"); - nrf_gpio_pin_write(VB3L_PIN, 0); - nrf_gpio_pin_write(VB3H_PIN, 1); - break; - - case ELECTRODE_E3N_ENABLE: - NRF_LOG_INFO("ELECTRODE_E3N_ENABLE()"); - nrf_gpio_pin_write(VA3H_PIN, 0); - nrf_gpio_pin_write(VA3L_PIN, 1); - break; - - case ELECTRODE_E3N_DISABLE: - NRF_LOG_INFO("ELECTRODE_E3N_DISABLE()"); - nrf_gpio_pin_write(VA3L_PIN, 0); - nrf_gpio_pin_write(VA3H_PIN, 1); - break; - - case ELECTRODE_E4P_ENABLE: - NRF_LOG_INFO("ELECTRODE_E4P_ENABLE()"); - nrf_gpio_pin_write(VB4H_PIN, 0); - nrf_gpio_pin_write(VB4L_PIN, 1); - break; - - case ELECTRODE_E4P_DISABLE: - NRF_LOG_INFO("ELECTRODE_E4P_DISABLE()"); - nrf_gpio_pin_write(VB4L_PIN, 0); - nrf_gpio_pin_write(VB4H_PIN, 1); - break; - - case ELECTRODE_E4N_ENABLE: - NRF_LOG_INFO("ELECTRODE_E4N_ENABLE()"); - nrf_gpio_pin_write(VA4H_PIN, 0); - nrf_gpio_pin_write(VA4L_PIN, 1); - break; - - case ELECTRODE_E4N_DISABLE: - NRF_LOG_INFO("ELECTRODE_E4N_DISABLE()"); - nrf_gpio_pin_write(VA4L_PIN, 0); - nrf_gpio_pin_write(VA4H_PIN, 1); - break; } } @@ -849,18 +770,13 @@ void tw1508_set_mA(float out_0_mA, float out_1_mA) char str[128]; snprintf(str, sizeof(str), "%s: %.3f", "out_0_mA float", out_0_mA); NRF_LOG_INFO("%s", str); - } - - { - char str[128]; - snprintf(str, sizeof(str), "%s: %.3f", "out_0_mA float", out_1_mA); + snprintf(str, sizeof(str), "%s: %.3f", "out_1_mA float", out_1_mA); NRF_LOG_INFO("%s", str); } out_0 = current_mA_convert_tw1508_value(out_0_mA); out_1 = current_mA_convert_tw1508_value(out_1_mA); tw1508_set(out_0, out_1); - NRF_LOG_INFO("tw1508_set(%d, %d)", out_0, out_1); } void start_electrodes_api(uint8_t *ins) @@ -1013,7 +929,7 @@ void dev_mode_electrode_switch(uint8_t *ins) case 0x0400: { // electrode_switch default // 3000FFFF 0400 - electrode_pulse_channel(0); + electrode_pulse_channel(ELEC_CH_ALL_HIGHZ); break; } @@ -1027,57 +943,47 @@ void dev_mode_electrode_switch(uint8_t *ins) } } -/* - dev_mode_tw1508 - - (1) Command Format: 0x3000FF0100 - - feat: tw1508_init() out_0 = 0, out_1 = 0 - - (2) Command Format: 0x3000FF0101aaaabbbb - - feat: tw1508_set() - - - aaaa: out_0 value (0x0000 to 0x03FF) - - - bbbb: out_1 value (0x0000 to 0x03FF) - - (3) Command Format: 0x3000FF0102aaaaaaaabbbbbbbb - - feat: tw1508_set_mA() - - - aaaaaaaa: out_0_mA (float) (0x00000000 to 0xFFFFFFFF) - - - bbbbbbbb: out_1_mA (float) (0x00000000 to 0xFFFFFFFF) -*/ void dev_mode_tw1508(uint8_t *ins) { struct __PACKED { - uint8_t id : 4; - uint8_t : 4; - uint16_t magic : 16; - uint8_t func_id; - uint8_t tw1508_opcode; + uint8_t id : 4; + uint8_t ins_type : 4; + uint8_t pkg_size; + uint8_t mode; + uint8_t mode_opcode; // dev mode could ignore + uint8_t dev_feat; + uint8_t dev_feat_opcode; uint8_t param[]; } *p_ins = (void *)ins; - switch (p_ins->tw1508_opcode) + switch (u8_to_u16(p_ins->dev_feat, p_ins->dev_feat_opcode)) { - case 0x00: { + case 0x0100: { + // tw1508 init + // 3000FFFF 0100 tw1508_init(); - NRF_LOG_INFO("tw1508_init()"); break; } - case 0x01: { - uint16_t out_0 = u8_to_i16(ins[5], ins[6]); - uint16_t out_1 = u8_to_i16(ins[7], ins[8]); - NRF_LOG_INFO("tw1508_set(%d, %d)", out_0, out_1); + case 0x0101: { + // tw1508 set raw value + // 3000FFFF 0101 0005 0008 + uint16_t out_0 = u8_to_u16(p_ins->param[0], p_ins->param[1]); + uint16_t out_1 = u8_to_u16(p_ins->param[2], p_ins->param[3]); tw1508_set(out_0, out_1); break; } - case 0x02: { - float out_0_mA = u8_to_float(ins, 5); - float out_1_mA = u8_to_float(ins, 9); - tw1508_set_mA(out_0_mA, out_1_mA); + case 0x0102: { + // tw1508 set mA float value + // 3000FFFF 0102 3F800000 40B00000 + uint32_t out_0_mA_u32 = u8_to_u32(p_ins->param[0], p_ins->param[1], p_ins->param[2], p_ins->param[3]); + uint32_t out_1_mA_u32 = u8_to_u32(p_ins->param[4], p_ins->param[5], p_ins->param[6], p_ins->param[7]); + float out_0_mA_f; + float out_1_mA_f; + memcpy(&out_0_mA_f, &out_0_mA_u32, sizeof(out_0_mA_f)); + memcpy(&out_1_mA_f, &out_1_mA_u32, sizeof(out_1_mA_f)); + tw1508_set_mA(out_0_mA_f, out_1_mA_f); break; } } @@ -1196,119 +1102,105 @@ void dev_mode_ctrl_cpg11_electrodes_task(uint8_t *ins) } } -void adapter_channel(uint8_t channel) +void adapter_channel(uint16_t channel) { - uint8_t ADPT0_S1_en = (channel & BIT0) >> 0; - uint8_t ADPT0_S2_en = (channel & BIT1) >> 1; - uint8_t ADPT0_S3_en = (channel & BIT2) >> 2; - uint8_t ADPT0_S4_en = (channel & BIT3) >> 3; - uint8_t ADPT1_S1_en = (channel & BIT4) >> 4; - uint8_t ADPT1_S2_en = (channel & BIT5) >> 5; - uint8_t ADPT1_S3_en = (channel & BIT6) >> 6; - uint8_t ADPT1_S4_en = (channel & BIT7) >> 7; + union + { + uint16_t val; + struct + { + uint16_t adpt0_s1 : 1; + uint16_t adpt0_s2 : 1; + uint16_t adpt0_s3 : 1; + uint16_t adpt0_s4 : 1; + uint16_t adpt1_s1 : 1; + uint16_t adpt1_s2 : 1; + uint16_t adpt1_s3 : 1; + uint16_t adpt1_s4 : 1; + uint16_t adpt_rsvd : 8; + }; + } adap_ch; - NRF_LOG_INFO("ADPT0_S1_en:%d", ADPT0_S1_en); - NRF_LOG_INFO("ADPT0_S2_en:%d", ADPT0_S2_en); - NRF_LOG_INFO("ADPT0_S3_en:%d", ADPT0_S3_en); - NRF_LOG_INFO("ADPT0_S4_en:%d", ADPT0_S4_en); - NRF_LOG_INFO("ADPT1_S1_en:%d", ADPT1_S1_en); - NRF_LOG_INFO("ADPT1_S2_en:%d", ADPT1_S2_en); - NRF_LOG_INFO("ADPT1_S3_en:%d", ADPT1_S3_en); - NRF_LOG_INFO("ADPT1_S4_en:%d", ADPT1_S4_en); + adap_ch.val = channel; + NRF_LOG_INFO("ADPT0_S1_PIN(%d)", adap_ch.adpt0_s1); + NRF_LOG_INFO("ADPT0_S2_PIN(%d)", adap_ch.adpt0_s2); + NRF_LOG_INFO("ADPT0_S3_PIN(%d)", adap_ch.adpt0_s3); + NRF_LOG_INFO("ADPT0_S4_PIN(%d)", adap_ch.adpt0_s4); + NRF_LOG_INFO("ADPT1_S1_PIN(%d)", adap_ch.adpt1_s1); + NRF_LOG_INFO("ADPT1_S2_PIN(%d)", adap_ch.adpt1_s2); + NRF_LOG_INFO("ADPT1_S3_PIN(%d)", adap_ch.adpt1_s3); + NRF_LOG_INFO("ADPT1_S4_PIN(%d)", adap_ch.adpt1_s4); - ADPT0_S1_en ? nrf_gpio_pin_set(ADPT0_S1_PIN) : nrf_gpio_pin_clear(ADPT0_S1_PIN); - ADPT0_S2_en ? nrf_gpio_pin_set(ADPT0_S2_PIN) : nrf_gpio_pin_clear(ADPT0_S2_PIN); - ADPT0_S3_en ? nrf_gpio_pin_set(ADPT0_S3_PIN) : nrf_gpio_pin_clear(ADPT0_S3_PIN); - ADPT0_S4_en ? nrf_gpio_pin_set(ADPT0_S4_PIN) : nrf_gpio_pin_clear(ADPT0_S4_PIN); - - ADPT1_S1_en ? nrf_gpio_pin_set(ADPT1_S1_PIN) : nrf_gpio_pin_clear(ADPT1_S1_PIN); - ADPT1_S2_en ? nrf_gpio_pin_set(ADPT1_S2_PIN) : nrf_gpio_pin_clear(ADPT1_S2_PIN); - ADPT1_S3_en ? nrf_gpio_pin_set(ADPT1_S3_PIN) : nrf_gpio_pin_clear(ADPT1_S3_PIN); - ADPT1_S4_en ? nrf_gpio_pin_set(ADPT1_S4_PIN) : nrf_gpio_pin_clear(ADPT1_S4_PIN); + adap_ch.adpt0_s1 ? nrf_gpio_pin_set(ADPT0_S1_PIN) : nrf_gpio_pin_clear(ADPT0_S1_PIN); + adap_ch.adpt0_s2 ? nrf_gpio_pin_set(ADPT0_S2_PIN) : nrf_gpio_pin_clear(ADPT0_S2_PIN); + adap_ch.adpt0_s3 ? nrf_gpio_pin_set(ADPT0_S3_PIN) : nrf_gpio_pin_clear(ADPT0_S3_PIN); + adap_ch.adpt0_s4 ? nrf_gpio_pin_set(ADPT0_S4_PIN) : nrf_gpio_pin_clear(ADPT0_S4_PIN); + adap_ch.adpt1_s1 ? nrf_gpio_pin_set(ADPT1_S1_PIN) : nrf_gpio_pin_clear(ADPT1_S1_PIN); + adap_ch.adpt1_s2 ? nrf_gpio_pin_set(ADPT1_S2_PIN) : nrf_gpio_pin_clear(ADPT1_S2_PIN); + adap_ch.adpt1_s3 ? nrf_gpio_pin_set(ADPT1_S3_PIN) : nrf_gpio_pin_clear(ADPT1_S3_PIN); + adap_ch.adpt1_s4 ? nrf_gpio_pin_set(ADPT1_S4_PIN) : nrf_gpio_pin_clear(ADPT1_S4_PIN); } void high_volt_channel(uint16_t channel) { sw_t sw; sw.val = channel; - NRF_LOG_INFO("sw.val= 0x%X", sw.val); - NRF_LOG_INFO("sw.sw15~sw12=%X %X %X %X", sw.sw15, sw.sw14, sw.sw13, sw.sw12); - NRF_LOG_INFO("sw.sw11~sw8=%X %X %X %X", sw.sw11, sw.sw10, sw.sw9, sw.sw8); - NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4); - NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0); + NRF_LOG_INFO("HV_sw.val= 0x%04X", sw.val); + { + char str[128]; + snprintf(str, sizeof(str), "%4d, %4d, %4d, %4d, %4d, %4d, %3d, %3d", sw.sw15, sw.sw14, sw.sw13, sw.sw12, sw.sw11, sw.sw10, sw.sw9, sw.sw8); + NRF_LOG_INFO("sw15, sw14, sw13, sw12, sw11, sw10, sw9, sw8"); + NRF_LOG_INFO("%s", str); + snprintf(str, sizeof(str), "%3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d", sw.sw7, sw.sw6, sw.sw5, sw.sw4, sw.sw3, sw.sw2, sw.sw1, sw.sw0); + NRF_LOG_INFO("sw7, sw6, sw5, sw4, sw3, sw2, sw1, sw0"); + NRF_LOG_INFO("%s", str); + } sw_write(sw); } -/* - dev_mode_adapter_block_switch - - (1) Command Format: 0x3000FF0300nn - - feat: control adapter_channel() - - - nn: channel (0x00 to 0xFF) - Bit 7 = 0 ADPT1_S4 disable, Bit 7 = 1 ADPT1_S4 enable - Bit 6 = 0 ADPT1_S3 disable, Bit 6 = 1 ADPT1_S3 enable - Bit 5 = 0 ADPT1_S2 disable, Bit 5 = 1 ADPT1_S2 enable - Bit 4 = 0 ADPT1_S1 disable, Bit 4 = 1 ADPT1_S1 enable - Bit 3 = 0 ADPT0_S4 disable, Bit 3 = 1 ADPT0_S4 enable - Bit 2 = 0 ADPT0_S3 disable, Bit 2 = 1 ADPT0_S3 enable - Bit 1 = 0 ADPT0_S2 disable, Bit 1 = 1 ADPT0_S2 enable - Bit 0 = 0 ADPT0_S1 disable, Bit 0 = 1 ADPT0_S1 enable - - (2) Command Format: 0x3000FF0301nnnn - - feat: control high_volt_channel() - ps. hv_sw: high volt switch - - - nnnn: channel (0x0000 to 0xFFFF) - Bit 15 = 0 hv_sw_15 disable, Bit 15 = 1 hv_sw_15 enable - Bit 14 = 0 hv_sw_14 disable, Bit 14 = 1 hv_sw_14 enable - Bit 13 = 0 hv_sw_13 disable, Bit 13 = 1 hv_sw_13 enable - Bit 12 = 0 hv_sw_12 disable, Bit 12 = 1 hv_sw_12 enable - Bit 11 = 0 hv_sw_11 disable, Bit 11 = 1 hv_sw_11 enable - Bit 10 = 0 hv_sw_10 disable, Bit 10 = 1 hv_sw_10 enable - Bit 9 = 0 hv_sw_9 disable, Bit 9 = 1 hv_sw_9 enable - Bit 8 = 0 hv_sw_8 disable, Bit 8 = 1 hv_sw_8 enable - Bit 7 = 0 hv_sw_7 disable, Bit 7 = 1 hv_sw_7 enable - Bit 6 = 0 hv_sw_6 disable, Bit 6 = 1 hv_sw_6 enable - Bit 5 = 0 hv_sw_5 disable, Bit 5 = 1 hv_sw_5 enable - Bit 4 = 0 hv_sw_4 disable, Bit 4 = 1 hv_sw_4 enable - Bit 3 = 0 hv_sw_3 disable, Bit 3 = 1 hv_sw_3 enable - Bit 2 = 0 hv_sw_2 disable, Bit 2 = 1 hv_sw_2 enable - Bit 1 = 0 hv_sw_1 disable, Bit 1 = 1 hv_sw_1 enable - Bit 0 = 0 hv_sw_0 disable, Bit 0 = 1 hv_sw_0 enable - - (2) Command Format: 0x3000FF0302 - - feat: reset high volt channel switch - -*/ void dev_mode_adapter_block_switch(uint8_t *ins) { struct __PACKED { - uint8_t id : 4; - uint8_t : 4; - uint16_t magic : 16; - uint8_t func_id; - uint8_t switch_opcode; + uint8_t id : 4; + uint8_t ins_type : 4; + uint8_t pkg_size; + uint8_t mode; + uint8_t mode_opcode; // dev mode could ignore + uint8_t dev_feat; + uint8_t dev_feat_opcode; uint8_t param[]; } *p_ins = (void *)ins; - switch (p_ins->switch_opcode) + switch (u8_to_u16(p_ins->dev_feat, p_ins->dev_feat_opcode)) { - case 0x00: { - uint8_t channel = ins[5]; + case 0x0200: { + // adapter_block_switch reset ADPT0/1 switch + // 3000FFFF 0200 + adapter_channel(0b00000000); + break; + } + + case 0x0201: { + // adapter_block_switch set ADPT0/1 switch + // 3000FFFF 0201 00FF + uint16_t channel = u8_to_u16(p_ins->param[0], p_ins->param[1]); adapter_channel(channel); break; } - case 0x01: { - uint16_t channel = u8_to_u16(ins[5], ins[6]); - high_volt_channel(channel); + case 0x0202: { + // adapter_block_switch reset hv switch + // 3000FFFF 0202 + sw_reset(); break; } - case 0x02: { - sw_reset(); // high volt + case 0x0203: { + // adapter_block_switch set hv switch + // 3000FFFF 0203 00FF + uint16_t channel = u8_to_u16(p_ins->param[0], p_ins->param[1]); + high_volt_channel(channel); break; } } @@ -1348,6 +1240,15 @@ void dev_mode(uint8_t *ins, uint16_t size) uint8_t param[]; } *p_ins = (void *)ins; + if (u8_to_u16(p_ins->mode, p_ins->mode_opcode) == 0xFF02) + { + dev_mode_ctrl_cpg11_electrodes_task(ins); + return; + } + + if (u8_to_u16(p_ins->mode, p_ins->mode_opcode) != 0xFFFF) + return; + switch (p_ins->dev_feat) { case 0x01: @@ -1355,10 +1256,6 @@ void dev_mode(uint8_t *ins, uint16_t size) break; case 0x02: - dev_mode_ctrl_cpg11_electrodes_task(ins); - break; - - case 0x03: dev_mode_adapter_block_switch(ins); break; @@ -1405,7 +1302,7 @@ const elite_instance_t *cpg_init(void) { NRF_LOG_INFO("[Board] FW ver: %02d%02d%02d %02d:%02d", VERSION_DATE_YEAR, VERSION_DATE_MONTH, VERSION_DATE_DAY, VERSION_DATE_HOUR, VERSION_DATE_MINUTE); tw1508_init(); - tw1508_set(5, 5); // 5*0.13= 0.65mA, formula:value*0.13=mA + tw1508_set(5, 5); // 5*0.104= 0.52mA, formula:value*0.104=mA return &cpg_elite_instance; } diff --git a/cpg.h b/cpg.h index b9ea554..7a2ab6d 100644 --- a/cpg.h +++ b/cpg.h @@ -12,9 +12,9 @@ extern "C" #define VERSION_DATE_YEAR 25 #define VERSION_DATE_MONTH 3 -#define VERSION_DATE_DAY 25 -#define VERSION_DATE_HOUR 16 -#define VERSION_DATE_MINUTE 36 +#define VERSION_DATE_DAY 28 +#define VERSION_DATE_HOUR 9 +#define VERSION_DATE_MINUTE 45 const elite_instance_t *cpg_init(void); diff --git a/max14802.c b/max14802.c index 25f5485..e5f4691 100644 --- a/max14802.c +++ b/max14802.c @@ -124,6 +124,8 @@ int max14802_write(sw_t sw_mask) nrf_gpio_pin_write(exclude_io[i], EXCLUDE_IO_DISABLE); } + nrf_delay_ms(1); + // Set max14082 shift_out((uint8_t *)&m_sw.val, SW_TOTAL_COUNT / SW_PER_BYTE); @@ -131,6 +133,7 @@ int max14802_write(sw_t sw_mask) if (m_sw.val == 0) { + nrf_delay_ms(1); for (uint32_t i = 0; i < SW_TOTAL_COUNT; i++) { nrf_gpio_pin_write(exclude_io[i], EXCLUDE_IO_ENABLE); diff --git a/tw1508.c b/tw1508.c index 12e8d64..c76eb43 100644 --- a/tw1508.c +++ b/tw1508.c @@ -10,6 +10,7 @@ void tw1508_set(uint16_t out_0, uint16_t out_1) { + NRF_LOG_INFO("%s(0x%04X, 0x%04X)", __FUNCTION__, out_0, out_1); typedef struct { uint32_t scki_pin;