From e7cbc16a7b6a7d2b9fd14781f112f17f464daa8c Mon Sep 17 00:00:00 2001 From: Roy_01 Date: Tue, 12 Aug 2025 09:38:57 +0800 Subject: [PATCH 1/4] config: switch project configuration to PEL v3.0 --- app/inc/app_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/app/inc/app_config.h b/app/inc/app_config.h index 9b8bb08..ed8a592 100644 --- a/app/inc/app_config.h +++ b/app/inc/app_config.h @@ -111,7 +111,7 @@ extern "C" #define DEF_ELITE_PEL_V3_0 0x00070002 #define DEF_ELITE_CPG_V1_1 0x00080001 #define DEF_ELITE_MMM_V1_0 0x00090001 -#define DEF_ELITE_MODEL DEF_ELITE_DEV +#define DEF_ELITE_MODEL DEF_ELITE_PEL_V3_0 #define DEF_ELITE_DEMO_W_SOFTDEVICE 0 From 3603861e0efe9cc82c59beb8b4a2b46682cb0da8 Mon Sep 17 00:00:00 2001 From: Roy_01 Date: Tue, 12 Aug 2025 10:40:07 +0800 Subject: [PATCH 2/4] feat: add INA_HI_PIN to ADC pulse process --- app/inc/elite_pel_v3_0.h | 6 ++--- app/inc/elite_pel_v3_0_io.h | 2 +- app/src/elite_pel_v3_0.c | 4 +-- app/src/elite_pel_v3_0_io.c | 53 ++++++++++++++++++++----------------- 4 files changed, 34 insertions(+), 31 deletions(-) diff --git a/app/inc/elite_pel_v3_0.h b/app/inc/elite_pel_v3_0.h index 0800288..539d4fa 100644 --- a/app/inc/elite_pel_v3_0.h +++ b/app/inc/elite_pel_v3_0.h @@ -12,9 +12,9 @@ extern "C" #define VERSION_DATE_YEAR 25 #define VERSION_DATE_MONTH 8 -#define VERSION_DATE_DAY 6 -#define VERSION_DATE_HOUR 15 -#define VERSION_DATE_MINUTE 38 +#define VERSION_DATE_DAY 12 +#define VERSION_DATE_HOUR 10 +#define VERSION_DATE_MINUTE 40 #define PEL_0P5R_MASK (0x01 << 0) #define PEL_1P0R_MASK (0x01 << 1) diff --git a/app/inc/elite_pel_v3_0_io.h b/app/inc/elite_pel_v3_0_io.h index b199ee9..6cebf5f 100644 --- a/app/inc/elite_pel_v3_0_io.h +++ b/app/inc/elite_pel_v3_0_io.h @@ -74,7 +74,7 @@ extern "C" typedef struct { uint32_t anode_pin; - uint32_t cathode_pin; + uint32_t ina_hi_pin; uint32_t smaple_i_pin; uint32_t sample_v_pin; uint32_t test_pin; diff --git a/app/src/elite_pel_v3_0.c b/app/src/elite_pel_v3_0.c index ebbd7c0..fd34446 100644 --- a/app/src/elite_pel_v3_0.c +++ b/app/src/elite_pel_v3_0.c @@ -549,7 +549,7 @@ static void start_adc_pulse(uint32_t pusle_cnt, void (*convt_done_cb)(void)) { pel_config_t pel_cfg = { .anode_pin = ANODE_PIN, - .cathode_pin = CATHODE_PIN, + .ina_hi_pin = INA_HI_PIN, .smaple_i_pin = SAMPLE_I_PIN, .sample_v_pin = SAMPLE_V_PIN, .test_pin = TP1_PIN, @@ -603,9 +603,7 @@ static void pel_pulse_start(void *p_arg) set_resistor_load_bits(p_setting->bitmask); } - nrf_gpio_pin_set(TP2_PIN); // For testing start_adc_pulse(0xFFFFFFFF, adc_event_end_cb); - nrf_gpio_pin_clear(TP2_PIN); // For testing } static void pel_pulse_stop(void *p_arg) diff --git a/app/src/elite_pel_v3_0_io.c b/app/src/elite_pel_v3_0_io.c index b5063ac..69b4051 100644 --- a/app/src/elite_pel_v3_0_io.c +++ b/app/src/elite_pel_v3_0_io.c @@ -98,6 +98,7 @@ void set_anode_cathode_to_default(void) if (BOARD_IOPx == BOARD_IOPH) { nrf_gpio_pin_clear(ANODE_PIN); + nrf_gpio_pin_clear(INA_HI_PIN); nrf_gpio_pin_clear(SAMPLE_I_PIN); nrf_gpio_pin_clear(SAMPLE_V_PIN); nrf_gpio_pin_clear(TP1_PIN); @@ -106,6 +107,7 @@ void set_anode_cathode_to_default(void) else if (BOARD_IOPx == BOARD_IOPL) { nrf_gpio_pin_set(ANODE_PIN); + nrf_gpio_pin_clear(INA_HI_PIN); nrf_gpio_pin_clear(SAMPLE_I_PIN); nrf_gpio_pin_clear(SAMPLE_V_PIN); nrf_gpio_pin_clear(TP1_PIN); @@ -228,37 +230,34 @@ void pel_pulse_gen_init(pel_config_t cfg) // config gpiote task nrf_gpiote_task_configure(0, cfg.anode_pin, NRF_GPIOTE_POLARITY_TOGGLE, (cfg.mode == 0) ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW); - nrf_gpiote_task_configure(1, cfg.smaple_i_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); - nrf_gpiote_task_configure(2, cfg.sample_v_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); + nrf_gpiote_task_configure(1, cfg.ina_hi_pin, NRF_GPIOTE_POLARITY_TOGGLE, (cfg.mode == 0) ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW); + nrf_gpiote_task_configure(2, cfg.smaple_i_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); + nrf_gpiote_task_configure(3, cfg.sample_v_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); if (cfg.test_pin != 0xFFFFFFFF) { - nrf_gpiote_task_configure(3, cfg.test_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); + nrf_gpiote_task_configure(4, cfg.test_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); } - // enable gpio task - for (int i = 0; i < 4; i++) - { - nrf_gpiote_task_enable(i); - } - - NRF_PPI->CH[0].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[0]; - NRF_PPI->CH[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0]; // anode_pin - NRF_PPI->CHENSET = (1 << (0)); + NRF_PPI->CH[0].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[0]; + NRF_PPI->CH[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0]; // anode_pin + NRF_PPI->FORK[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1]; // ina_hi_pin + NRF_PPI->CHENSET = (1 << (0)); NRF_PPI->CH[1].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[1]; - NRF_PPI->CH[1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1]; // smaple_i_pin - NRF_PPI->FORK[1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2]; // sample_v_pin + NRF_PPI->CH[1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2]; // smaple_i_pin + NRF_PPI->FORK[1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3]; // sample_v_pin NRF_PPI->CHENSET = (1 << (1)); NRF_PPI->CH[2].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[2]; - NRF_PPI->CH[2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1]; - NRF_PPI->FORK[2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2]; + NRF_PPI->CH[2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[2]; + NRF_PPI->FORK[2].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3]; NRF_PPI->CHENSET = (1 << (2)); - NRF_PPI->CH[3].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[3]; - NRF_PPI->CH[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0]; // anode_pin - NRF_PPI->CHENSET = (1 << (3)); + NRF_PPI->CH[3].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[3]; + NRF_PPI->CH[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0]; // anode_pin + NRF_PPI->FORK[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1]; // ina_hi_pin + NRF_PPI->CHENSET = (1 << (3)); NRF_PPI->CH[4].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[4]; NRF_PPI->CH[4].TEP = (uint32_t)&NRF_SAADC->TASKS_START; @@ -268,13 +267,19 @@ void pel_pulse_gen_init(pel_config_t cfg) { NRF_PPI->CH[6].EEP = (uint32_t)&NRF_SAADC->EVENTS_STARTED; NRF_PPI->CH[6].TEP = (uint32_t)&NRF_SAADC->TASKS_SAMPLE; - NRF_PPI->FORK[6].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3]; // test_pin + NRF_PPI->FORK[6].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4]; // test_pin NRF_PPI->CHENSET = (1 << (6)); NRF_PPI->CH[7].EEP = (uint32_t)&NRF_SAADC->EVENTS_END; - NRF_PPI->CH[7].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[3]; + NRF_PPI->CH[7].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4]; NRF_PPI->CHENSET = (1 << (7)); } + // enable gpio task + for (int i = 0; i < 5; i++) + { + nrf_gpiote_task_enable(i); + } + pel_hw.pulse_tmr->PRESCALER = NRF_TIMER_FREQ_16MHz; pel_hw.pulse_tmr->MODE = NRF_TIMER_MODE_TIMER; pel_hw.pulse_tmr->BITMODE = NRF_TIMER_BIT_WIDTH_32; @@ -312,7 +317,7 @@ static void pel_pulse_gen_demo_task(void *p_arg) { pel_config_t pel_cfg = { .anode_pin = ANODE_PIN, - .cathode_pin = CATHODE_PIN, + .ina_hi_pin = INA_HI_PIN, .smaple_i_pin = SAMPLE_I_PIN, .sample_v_pin = SAMPLE_V_PIN, .test_pin = TP1_PIN, @@ -391,14 +396,14 @@ void pel30_io_init(void) if (BOARD_IOPx == BOARD_IOPH) { nrf_gpio_pin_clear(ANODE_PIN); - nrf_gpio_pin_set(INA_HI_PIN); + nrf_gpio_pin_clear(INA_HI_PIN); nrf_gpio_pin_set(LED_IOPL_PIN); nrf_gpio_pin_clear(LED_IOPH_PIN); } else if (BOARD_IOPx == BOARD_IOPL) { nrf_gpio_pin_set(ANODE_PIN); - nrf_gpio_pin_clear(INA_HI_PIN); + nrf_gpio_pin_set(INA_HI_PIN); nrf_gpio_pin_clear(LED_IOPL_PIN); nrf_gpio_pin_set(LED_IOPH_PIN); } From 7d5900b58b5dbdd13b23e39ef57d0b0f3ffd0481 Mon Sep 17 00:00:00 2001 From: Roy_01 Date: Tue, 12 Aug 2025 15:44:20 +0800 Subject: [PATCH 3/4] fix: ADC pulse config --- app/inc/elite_pel_v3_0.h | 4 +-- app/src/elite_pel_v3_0.c | 4 +-- app/src/elite_pel_v3_0_io.c | 64 +++++++++++-------------------------- 3 files changed, 22 insertions(+), 50 deletions(-) diff --git a/app/inc/elite_pel_v3_0.h b/app/inc/elite_pel_v3_0.h index 539d4fa..f303918 100644 --- a/app/inc/elite_pel_v3_0.h +++ b/app/inc/elite_pel_v3_0.h @@ -13,8 +13,8 @@ extern "C" #define VERSION_DATE_YEAR 25 #define VERSION_DATE_MONTH 8 #define VERSION_DATE_DAY 12 -#define VERSION_DATE_HOUR 10 -#define VERSION_DATE_MINUTE 40 +#define VERSION_DATE_HOUR 15 +#define VERSION_DATE_MINUTE 44 #define PEL_0P5R_MASK (0x01 << 0) #define PEL_1P0R_MASK (0x01 << 1) diff --git a/app/src/elite_pel_v3_0.c b/app/src/elite_pel_v3_0.c index fd34446..5855867 100644 --- a/app/src/elite_pel_v3_0.c +++ b/app/src/elite_pel_v3_0.c @@ -899,7 +899,7 @@ static void auto_scan_mode(uint8_t *ins, uint16_t size) vTaskDelete(auto_scan_start_handle); auto_scan_start_handle = NULL; } - running = true; + running = false; led_set(LED_IDLE_CONNECTED); taskEXIT_CRITICAL(); break; @@ -927,7 +927,7 @@ static void auto_scan_mode(uint8_t *ins, uint16_t size) // using a 100ms delay to ensure the parameter is copied to to auto_scan_start_task() vTaskDelay(pdMS_TO_TICKS(100)); - running = false; + running = true; led_set(LED_REC); } break; diff --git a/app/src/elite_pel_v3_0_io.c b/app/src/elite_pel_v3_0_io.c index 69b4051..7ed0aaf 100644 --- a/app/src/elite_pel_v3_0_io.c +++ b/app/src/elite_pel_v3_0_io.c @@ -93,28 +93,6 @@ void spim_xfer(uint32_t cs_pin, #define MAX_PULSE_WIDTH INT16_MAX #define MAX_PULSE_IDLE INT16_MAX -void set_anode_cathode_to_default(void) -{ - if (BOARD_IOPx == BOARD_IOPH) - { - nrf_gpio_pin_clear(ANODE_PIN); - nrf_gpio_pin_clear(INA_HI_PIN); - nrf_gpio_pin_clear(SAMPLE_I_PIN); - nrf_gpio_pin_clear(SAMPLE_V_PIN); - nrf_gpio_pin_clear(TP1_PIN); - nrf_gpio_pin_clear(TP2_PIN); - } - else if (BOARD_IOPx == BOARD_IOPL) - { - nrf_gpio_pin_set(ANODE_PIN); - nrf_gpio_pin_clear(INA_HI_PIN); - nrf_gpio_pin_clear(SAMPLE_I_PIN); - nrf_gpio_pin_clear(SAMPLE_V_PIN); - nrf_gpio_pin_clear(TP1_PIN); - nrf_gpio_pin_clear(TP2_PIN); - } -} - static void pel_saadc_init(pel_adc_t *p_adc) { /* stop ssadc */ @@ -206,10 +184,8 @@ void SAADC_IRQHandler(void) void pel_pulse_gen_init(pel_config_t cfg) { pel_hw.pulse_tmr->TASKS_STOP = 1; - sd_nvic_DisableIRQ(pel_hw.pulse_irq_n); sd_nvic_ClearPendingIRQ(pel_hw.pulse_irq_n); - sd_nvic_DisableIRQ(SAADC_IRQn); sd_nvic_ClearPendingIRQ(SAADC_IRQn); @@ -217,28 +193,20 @@ void pel_pulse_gen_init(pel_config_t cfg) pel_hw.adc.gain = cfg.gain; pel_hw.adc.smaple_time = cfg.smaple_time; pel_hw.adc.convt_new_arrival_cb = cfg.convt_new_arrival_cb; - pel_saadc_init(&pel_hw.adc); // disable gpio task - for (int i = 0; i < 4; i++) + for (int i = 0; i < 5; i++) { nrf_gpiote_task_disable(i); } - set_anode_cathode_to_default(); - // config gpiote task nrf_gpiote_task_configure(0, cfg.anode_pin, NRF_GPIOTE_POLARITY_TOGGLE, (cfg.mode == 0) ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW); nrf_gpiote_task_configure(1, cfg.ina_hi_pin, NRF_GPIOTE_POLARITY_TOGGLE, (cfg.mode == 0) ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW); nrf_gpiote_task_configure(2, cfg.smaple_i_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); nrf_gpiote_task_configure(3, cfg.sample_v_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); - if (cfg.test_pin != 0xFFFFFFFF) - { - nrf_gpiote_task_configure(4, cfg.test_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); - } - NRF_PPI->CH[0].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[0]; NRF_PPI->CH[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0]; // anode_pin NRF_PPI->FORK[0].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1]; // ina_hi_pin @@ -255,31 +223,35 @@ void pel_pulse_gen_init(pel_config_t cfg) NRF_PPI->CHENSET = (1 << (2)); NRF_PPI->CH[3].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[3]; - NRF_PPI->CH[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0]; // anode_pin - NRF_PPI->FORK[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1]; // ina_hi_pin + NRF_PPI->CH[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[0]; + NRF_PPI->FORK[3].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[1]; NRF_PPI->CHENSET = (1 << (3)); NRF_PPI->CH[4].EEP = (uint32_t)&pel_hw.pulse_tmr->EVENTS_COMPARE[4]; NRF_PPI->CH[4].TEP = (uint32_t)&NRF_SAADC->TASKS_START; NRF_PPI->CHENSET = (1 << (4)); - if (cfg.test_pin != 0xFFFFFFFF) - { - NRF_PPI->CH[6].EEP = (uint32_t)&NRF_SAADC->EVENTS_STARTED; - NRF_PPI->CH[6].TEP = (uint32_t)&NRF_SAADC->TASKS_SAMPLE; - NRF_PPI->FORK[6].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4]; // test_pin - NRF_PPI->CHENSET = (1 << (6)); - NRF_PPI->CH[7].EEP = (uint32_t)&NRF_SAADC->EVENTS_END; - NRF_PPI->CH[7].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4]; - NRF_PPI->CHENSET = (1 << (7)); - } + NRF_PPI->CH[5].EEP = (uint32_t)&NRF_SAADC->EVENTS_STARTED; + NRF_PPI->CH[5].TEP = (uint32_t)&NRF_SAADC->TASKS_SAMPLE; + NRF_PPI->CHENSET = (1 << (5)); + + NRF_PPI->CH[6].EEP = (uint32_t)&NRF_SAADC->EVENTS_END; + NRF_PPI->CHENSET = (1 << (6)); // enable gpio task - for (int i = 0; i < 5; i++) + for (int i = 0; i < 4; i++) { nrf_gpiote_task_enable(i); } + if (cfg.test_pin != 0xFFFFFFFF) + { + nrf_gpiote_task_configure(4, cfg.test_pin, NRF_GPIOTE_POLARITY_TOGGLE, NRF_GPIOTE_INITIAL_VALUE_LOW); + NRF_PPI->FORK[5].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4]; // test_pin + NRF_PPI->CH[6].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[4]; + nrf_gpiote_task_enable(4); + } + pel_hw.pulse_tmr->PRESCALER = NRF_TIMER_FREQ_16MHz; pel_hw.pulse_tmr->MODE = NRF_TIMER_MODE_TIMER; pel_hw.pulse_tmr->BITMODE = NRF_TIMER_BIT_WIDTH_32; From ecfaeec09a42cd2a5b1b8e5aff7f4bc5294b16a2 Mon Sep 17 00:00:00 2001 From: Roy_01 Date: Wed, 13 Aug 2025 17:34:53 +0800 Subject: [PATCH 4/4] config: switch project configuration to DEF_ELITE_DEV --- app/inc/app_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/app/inc/app_config.h b/app/inc/app_config.h index ed8a592..9b8bb08 100644 --- a/app/inc/app_config.h +++ b/app/inc/app_config.h @@ -111,7 +111,7 @@ extern "C" #define DEF_ELITE_PEL_V3_0 0x00070002 #define DEF_ELITE_CPG_V1_1 0x00080001 #define DEF_ELITE_MMM_V1_0 0x00090001 -#define DEF_ELITE_MODEL DEF_ELITE_PEL_V3_0 +#define DEF_ELITE_MODEL DEF_ELITE_DEV #define DEF_ELITE_DEMO_W_SOFTDEVICE 0