diff --git a/cpg.c b/cpg.c
index a30c374..fca0bdb 100644
--- a/cpg.c
+++ b/cpg.c
@@ -14,9 +14,9 @@
 
 #define VERSION_DATE_YEAR   24
 #define VERSION_DATE_MONTH  9
-#define VERSION_DATE_DAY    25
-#define VERSION_DATE_HOUR   17
-#define VERSION_DATE_MINUTE 35
+#define VERSION_DATE_DAY    26
+#define VERSION_DATE_HOUR   11
+#define VERSION_DATE_MINUTE 04
 static void cis_version(uint8_t *ins, uint16_t size)
 {
     NRF_LOG_INFO("%s", __FUNCTION__);
@@ -112,3 +112,4 @@ const elite_instance_t *cpg_init(void)
 }
 
 #endif
+   
\ No newline at end of file
diff --git a/cpg11_dev_mode.c b/cpg11_dev_mode.c
index 484411b..51e9983 100644
--- a/cpg11_dev_mode.c
+++ b/cpg11_dev_mode.c
@@ -1382,14 +1382,14 @@ void dev_mode_ctrl_cpg11_electrodes_task(uint8_t *ins)
 
 void adapter_channel(uint8_t channel)
 {
-    uint8_t ADPT0_S1_en = (channel & BIT7) >> 7;
-    uint8_t ADPT0_S2_en = (channel & BIT6) >> 6;
-    uint8_t ADPT0_S3_en = (channel & BIT5) >> 5;
-    uint8_t ADPT0_S4_en = (channel & BIT4) >> 4;
-    uint8_t ADPT1_S1_en = (channel & BIT3) >> 3;
-    uint8_t ADPT1_S2_en = (channel & BIT2) >> 2;
-    uint8_t ADPT1_S3_en = (channel & BIT1) >> 1;
-    uint8_t ADPT1_S4_en = (channel & BIT0) >> 0;
+    uint8_t ADPT0_S1_en = (channel & BIT0) >> 0;
+    uint8_t ADPT0_S2_en = (channel & BIT1) >> 1;
+    uint8_t ADPT0_S3_en = (channel & BIT2) >> 2;
+    uint8_t ADPT0_S4_en = (channel & BIT3) >> 3;
+    uint8_t ADPT1_S1_en = (channel & BIT4) >> 4;
+    uint8_t ADPT1_S2_en = (channel & BIT5) >> 5;
+    uint8_t ADPT1_S3_en = (channel & BIT6) >> 6;
+    uint8_t ADPT1_S4_en = (channel & BIT7) >> 7;
 
     NRF_LOG_INFO("ADPT0_S1_en:%d", ADPT0_S1_en);
     NRF_LOG_INFO("ADPT0_S2_en:%d", ADPT0_S2_en);
@@ -1412,6 +1412,18 @@ void adapter_channel(uint8_t channel)
 
 }
 
+void high_volt_channel(uint16_t channel)
+{
+    sw_t sw;
+    sw.val = channel;
+    NRF_LOG_INFO("sw.val= 0x%X", sw.val);
+    NRF_LOG_INFO("sw.sw15~sw12=%X %X %X %X", sw.sw15, sw.sw14, sw.sw13, sw.sw12);
+    NRF_LOG_INFO("sw.sw11~sw8=%X %X %X %X", sw.sw11, sw.sw10, sw.sw9, sw.sw8);
+    NRF_LOG_INFO("sw.sw7~sw4=%X %X %X %X", sw.sw7, sw.sw6, sw.sw5, sw.sw4);
+    NRF_LOG_INFO("sw.sw3~sw0=%X %X %X %X", sw.sw3, sw.sw2, sw.sw1, sw.sw0);
+    sw_write(sw);
+}
+
 /*
     dev_mode_adapter_block_switch
 
@@ -1419,14 +1431,40 @@ void adapter_channel(uint8_t channel)
         - feat: control adapter_channel()
 
         - nn: channel (0x00 to 0xFF)
-            Bit 7 = 0 ADPT0_S1 disable, Bit 7 = 1  ADPT0_S1 enable
-            Bit 6 = 0 ADPT0_S2 disable, Bit 6 = 1  ADPT0_S2 enable
-            Bit 5 = 0 ADPT0_S3 disable, Bit 5 = 1  ADPT0_S3 enable
-            Bit 4 = 0 ADPT0_S4 disable, Bit 4 = 1  ADPT0_S4 enable
-            Bit 3 = 0 ADPT1_S1 disable, Bit 3 = 1  ADPT1_S1 enable
-            Bit 2 = 0 ADPT1_S2 disable, Bit 2 = 1  ADPT1_S2 enable
-            Bit 1 = 0 ADPT1_S3 disable, Bit 1 = 1  ADPT1_S3 enable
-            Bit 0 = 0 ADPT1_S4 disable, Bit 0 = 1  ADPT1_S4 enable
+            Bit 7 = 0 ADPT1_S4 disable, Bit 7 = 1  ADPT1_S4 enable
+            Bit 6 = 0 ADPT1_S3 disable, Bit 6 = 1  ADPT1_S3 enable
+            Bit 5 = 0 ADPT1_S2 disable, Bit 5 = 1  ADPT1_S2 enable
+            Bit 4 = 0 ADPT1_S1 disable, Bit 4 = 1  ADPT1_S1 enable
+            Bit 3 = 0 ADPT0_S4 disable, Bit 3 = 1  ADPT0_S4 enable
+            Bit 2 = 0 ADPT0_S3 disable, Bit 2 = 1  ADPT0_S3 enable
+            Bit 1 = 0 ADPT0_S2 disable, Bit 1 = 1  ADPT0_S2 enable
+            Bit 0 = 0 ADPT0_S1 disable, Bit 0 = 1  ADPT0_S1 enable
+
+    (2) Command Format: 0x3000FF0301nnnn
+        - feat: control high_volt_channel()
+            ps. hv_sw: high volt switch
+
+        - nnnn: channel (0x0000 to 0xFFFF)
+            Bit 15 = 0 hv_sw_15 disable, Bit 15 = 1 hv_sw_15 enable
+            Bit 14 = 0 hv_sw_14 disable, Bit 14 = 1 hv_sw_14 enable
+            Bit 13 = 0 hv_sw_13 disable, Bit 13 = 1 hv_sw_13 enable
+            Bit 12 = 0 hv_sw_12 disable, Bit 12 = 1 hv_sw_12 enable
+            Bit 11 = 0 hv_sw_11 disable, Bit 11 = 1 hv_sw_11 enable
+            Bit 10 = 0 hv_sw_10 disable, Bit 10 = 1 hv_sw_10 enable
+            Bit 9  = 0 hv_sw_9  disable, Bit 9  = 1 hv_sw_9  enable
+            Bit 8  = 0 hv_sw_8  disable, Bit 8  = 1 hv_sw_8  enable
+            Bit 7  = 0 hv_sw_7  disable, Bit 7  = 1 hv_sw_7  enable
+            Bit 6  = 0 hv_sw_6  disable, Bit 6  = 1 hv_sw_6  enable
+            Bit 5  = 0 hv_sw_5  disable, Bit 5  = 1 hv_sw_5  enable
+            Bit 4  = 0 hv_sw_4  disable, Bit 4  = 1 hv_sw_4  enable
+            Bit 3  = 0 hv_sw_3  disable, Bit 3  = 1 hv_sw_3  enable
+            Bit 2  = 0 hv_sw_2  disable, Bit 2  = 1 hv_sw_2  enable
+            Bit 1  = 0 hv_sw_1  disable, Bit 1  = 1 hv_sw_1  enable
+            Bit 0  = 0 hv_sw_0  disable, Bit 0  = 1 hv_sw_0  enable
+
+    (2) Command Format: 0x3000FF0302
+        - feat: reset high volt channel switch
+
 */
 void dev_mode_adapter_block_switch(uint8_t *ins)
 {
@@ -1447,6 +1485,17 @@ void dev_mode_adapter_block_switch(uint8_t *ins)
             adapter_channel(channel);
             break;
         }
+
+        case 0x01: {
+            uint16_t channel = u8_to_u16(ins[5], ins[6]);
+            high_volt_channel(channel);
+            break;
+        }
+
+        case 0x02: {
+            sw_reset(); //high volt
+            break;
+        }
     }
 }