chain40
138 lines
3.5 KiB
C
138 lines
3.5 KiB
C
#include <string.h>
|
|
|
|
#ifdef __cplusplus
|
|
extern "C"
|
|
{
|
|
#endif
|
|
|
|
#include "nrf_gpio.h"
|
|
#include "nrf_gpiote.h"
|
|
#include "nrf_spim.h"
|
|
|
|
#include "FreeRTOS.h"
|
|
#include "semphr.h"
|
|
#include "task.h"
|
|
|
|
#include "nrf_log.h"
|
|
#include "nrf_log_ctrl.h"
|
|
#include "nrf_log_default_backends.h"
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#define MEM_SEL_PIN NRF_GPIO_PIN_MAP(1, 9)
|
|
#define MEM_BZY_PIN NRF_GPIO_PIN_MAP(0, 8)
|
|
#define MEM_REQ_PIN NRF_GPIO_PIN_MAP(0, 6)
|
|
|
|
#define RAM_SEL_PIN NRF_GPIO_PIN_MAP(0, 5)
|
|
|
|
#define MEM_TEST_01_PIN NRF_GPIO_PIN_MAP(0, 26)
|
|
#define MEM_TEST_02_PIN NRF_GPIO_PIN_MAP(0, 17)
|
|
#define MEM_TEST_03_PIN NRF_GPIO_PIN_MAP(0, 21)
|
|
#define MEM_TEST_04_PIN NRF_GPIO_PIN_MAP(0, 19)
|
|
#define MEM_TEST_05_PIN NRF_GPIO_PIN_MAP(0, 22)
|
|
|
|
#define MEM_REQ_GPIOTE_ID 0
|
|
|
|
static int ram_sel_signal = 0;
|
|
|
|
static SemaphoreHandle_t mem_drv_semphr = NULL;
|
|
static TaskHandle_t mem_drv_task_handle = NULL;
|
|
|
|
void mem_ram_select(int select)
|
|
{
|
|
ram_sel_signal = select;
|
|
switch (ram_sel_signal)
|
|
{
|
|
case 0:
|
|
nrf_gpio_pin_clear(RAM_SEL_PIN);
|
|
break;
|
|
case 1:
|
|
nrf_gpio_pin_set(RAM_SEL_PIN);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void mem_drv_task(void *p_arg)
|
|
{
|
|
static uint32_t sel = 0;
|
|
|
|
extern void sram_drv_init(void);
|
|
sram_drv_init();
|
|
|
|
extern void sram_drv_reset(void);
|
|
for (int i = 0; i < 2; i++)
|
|
{
|
|
sel ^= 1;
|
|
mem_ram_select(sel);
|
|
sram_drv_reset();
|
|
}
|
|
|
|
for (;;)
|
|
{
|
|
extern int sram_drv_write(uint32_t addr, void *p_dest, uint32_t len);
|
|
extern int sram_drv_read(uint32_t addr, void *p_dest, uint32_t len);
|
|
|
|
uint8_t buf[4];
|
|
|
|
xSemaphoreTake(mem_drv_semphr, portMAX_DELAY);
|
|
|
|
sel ^= 0x01;
|
|
mem_ram_select(sel);
|
|
sram_drv_read(0x0000, buf, sizeof(buf));
|
|
NRF_LOG_INFO("mem_sel[%d]: 0x%02X, 0x%02X, 0x%02X, 0x%02X", sel, buf[0], buf[1], buf[2], buf[3]);
|
|
}
|
|
}
|
|
|
|
void mem_board_init(void)
|
|
{
|
|
// Config RAM test pin
|
|
nrf_gpio_cfg_input(MEM_TEST_01_PIN, NRF_GPIO_PIN_PULLUP);
|
|
nrf_gpio_cfg_input(MEM_TEST_02_PIN, NRF_GPIO_PIN_PULLUP);
|
|
nrf_gpio_cfg_input(MEM_TEST_03_PIN, NRF_GPIO_PIN_PULLUP);
|
|
nrf_gpio_cfg_input(MEM_TEST_04_PIN, NRF_GPIO_PIN_PULLUP);
|
|
nrf_gpio_cfg_input(MEM_TEST_05_PIN, NRF_GPIO_PIN_PULLUP);
|
|
|
|
// Config RAM select pin
|
|
nrf_gpio_cfg_output(RAM_SEL_PIN);
|
|
nrf_gpio_pin_clear(RAM_SEL_PIN);
|
|
|
|
// Config PI Ctrl pin
|
|
nrf_gpio_cfg_input(MEM_SEL_PIN, NRF_GPIO_PIN_NOPULL);
|
|
nrf_gpio_cfg_input(MEM_REQ_PIN, NRF_GPIO_PIN_NOPULL);
|
|
nrf_gpiote_event_configure(MEM_REQ_GPIOTE_ID, MEM_REQ_PIN, NRF_GPIOTE_POLARITY_TOGGLE);
|
|
nrf_gpiote_event_enable(MEM_REQ_GPIOTE_ID);
|
|
nrf_gpiote_int_enable(0x01 << MEM_REQ_GPIOTE_ID);
|
|
|
|
// Create Semphr & Task
|
|
mem_drv_semphr = xSemaphoreCreateBinary();
|
|
xTaskCreate(mem_drv_task, "mem_drv", 256, NULL, 5, NULL);
|
|
|
|
sd_nvic_SetPriority(GPIOTE_IRQn, _PRIO_APP_HIGH);
|
|
sd_nvic_EnableIRQ(GPIOTE_IRQn);
|
|
}
|
|
|
|
static void mem_req_int_callback(void)
|
|
{
|
|
uint32_t mem_sel = nrf_gpio_pin_read(MEM_SEL_PIN);
|
|
uint32_t mem_req = nrf_gpio_pin_read(MEM_REQ_PIN);
|
|
if (mem_sel != mem_req)
|
|
{
|
|
BaseType_t xHigherPriorityTaskWoken;
|
|
xSemaphoreGiveFromISR(mem_drv_semphr, &xHigherPriorityTaskWoken);
|
|
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
|
}
|
|
}
|
|
|
|
void GPIOTE_IRQHandler(void)
|
|
{
|
|
if (NRF_GPIOTE->EVENTS_IN[MEM_REQ_GPIOTE_ID])
|
|
{
|
|
NRF_GPIOTE->EVENTS_IN[MEM_REQ_GPIOTE_ID] = 0;
|
|
mem_req_int_callback();
|
|
}
|
|
}
|