Roy dfbbfe4e07 [update] set ram status register = 0x41

2023-06-26 17:34:45 +08:00

..

cc2650

Refactor(4): uart data reserve len, optimize chk memboard

2023-04-20 18:00:22 +08:00

__init__.py

fisrt commit

2021-12-20 14:52:55 +08:00

ext_mem.py

[update] set ram status register = 0x41

2023-06-26 17:34:45 +08:00

gpio.py

fisrt commit

2021-12-20 14:52:55 +08:00

interface_spi.py

[update] fix spi reset

2022-02-10 17:46:36 +08:00

interface_uart.py

Style: uart formatting

2023-04-20 18:20:52 +08:00

led.py

fisrt commit

2021-12-20 14:52:55 +08:00

mount.py

fisrt commit

2021-12-20 14:52:55 +08:00

selector.py

[update] read RAM data bug

2022-06-10 17:22:10 +08:00

vcgencmd.py

fisrt commit

2021-12-20 14:52:55 +08:00