Roy 9ad1f394be [update] update decode and data length = 40 byte

2022-02-18 13:16:49 +08:00

..

__pycache__

[update] project path change

2021-12-22 14:29:56 +08:00

cc2650

[update] update uart read timeout: 0.01s

2022-02-10 17:39:45 +08:00

__init__.py

fisrt commit

2021-12-20 14:52:55 +08:00

ext_mem.py

[update] update decode and data length = 40 byte

2022-02-18 13:16:49 +08:00

gpio.py

fisrt commit

2021-12-20 14:52:55 +08:00

interface_spi.py

[update] fix spi reset

2022-02-10 17:46:36 +08:00

interface_uart.py

[update] update uart read timeout: 0.01s

2022-02-10 17:39:45 +08:00

led.py

fisrt commit

2021-12-20 14:52:55 +08:00

mount.py

fisrt commit

2021-12-20 14:52:55 +08:00

selector.py

[update] clear not used code in class ExtMemManager

2022-02-10 17:41:49 +08:00

vcgencmd.py

fisrt commit

2021-12-20 14:52:55 +08:00